Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/drivers/net/ethernet/cirrus/ep93xx_eth.c

  1 /*
  2  * EP93xx ethernet network device driver
  3  * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
  4  * Dedicated to Marija Kulikova.
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License as published by
  8  * the Free Software Foundation; either version 2 of the License, or
  9  * (at your option) any later version.
 10  */
 11 
 12 #define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__
 13 
 14 #include <linux/dma-mapping.h>
 15 #include <linux/module.h>
 16 #include <linux/kernel.h>
 17 #include <linux/netdevice.h>
 18 #include <linux/mii.h>
 19 #include <linux/etherdevice.h>
 20 #include <linux/ethtool.h>
 21 #include <linux/interrupt.h>
 22 #include <linux/moduleparam.h>
 23 #include <linux/platform_device.h>
 24 #include <linux/delay.h>
 25 #include <linux/io.h>
 26 #include <linux/slab.h>
 27 
 28 #include <mach/hardware.h>
 29 
 30 #define DRV_MODULE_NAME         "ep93xx-eth"
 31 #define DRV_MODULE_VERSION      "0.1"
 32 
 33 #define RX_QUEUE_ENTRIES        64
 34 #define TX_QUEUE_ENTRIES        8
 35 
 36 #define MAX_PKT_SIZE            2044
 37 #define PKT_BUF_SIZE            2048
 38 
 39 #define REG_RXCTL               0x0000
 40 #define  REG_RXCTL_DEFAULT      0x00073800
 41 #define REG_TXCTL               0x0004
 42 #define  REG_TXCTL_ENABLE       0x00000001
 43 #define REG_MIICMD              0x0010
 44 #define  REG_MIICMD_READ        0x00008000
 45 #define  REG_MIICMD_WRITE       0x00004000
 46 #define REG_MIIDATA             0x0014
 47 #define REG_MIISTS              0x0018
 48 #define  REG_MIISTS_BUSY        0x00000001
 49 #define REG_SELFCTL             0x0020
 50 #define  REG_SELFCTL_RESET      0x00000001
 51 #define REG_INTEN               0x0024
 52 #define  REG_INTEN_TX           0x00000008
 53 #define  REG_INTEN_RX           0x00000007
 54 #define REG_INTSTSP             0x0028
 55 #define  REG_INTSTS_TX          0x00000008
 56 #define  REG_INTSTS_RX          0x00000004
 57 #define REG_INTSTSC             0x002c
 58 #define REG_AFP                 0x004c
 59 #define REG_INDAD0              0x0050
 60 #define REG_INDAD1              0x0051
 61 #define REG_INDAD2              0x0052
 62 #define REG_INDAD3              0x0053
 63 #define REG_INDAD4              0x0054
 64 #define REG_INDAD5              0x0055
 65 #define REG_GIINTMSK            0x0064
 66 #define  REG_GIINTMSK_ENABLE    0x00008000
 67 #define REG_BMCTL               0x0080
 68 #define  REG_BMCTL_ENABLE_TX    0x00000100
 69 #define  REG_BMCTL_ENABLE_RX    0x00000001
 70 #define REG_BMSTS               0x0084
 71 #define  REG_BMSTS_RX_ACTIVE    0x00000008
 72 #define REG_RXDQBADD            0x0090
 73 #define REG_RXDQBLEN            0x0094
 74 #define REG_RXDCURADD           0x0098
 75 #define REG_RXDENQ              0x009c
 76 #define REG_RXSTSQBADD          0x00a0
 77 #define REG_RXSTSQBLEN          0x00a4
 78 #define REG_RXSTSQCURADD        0x00a8
 79 #define REG_RXSTSENQ            0x00ac
 80 #define REG_TXDQBADD            0x00b0
 81 #define REG_TXDQBLEN            0x00b4
 82 #define REG_TXDQCURADD          0x00b8
 83 #define REG_TXDENQ              0x00bc
 84 #define REG_TXSTSQBADD          0x00c0
 85 #define REG_TXSTSQBLEN          0x00c4
 86 #define REG_TXSTSQCURADD        0x00c8
 87 #define REG_MAXFRMLEN           0x00e8
 88 
 89 struct ep93xx_rdesc
 90 {
 91         u32     buf_addr;
 92         u32     rdesc1;
 93 };
 94 
 95 #define RDESC1_NSOF             0x80000000
 96 #define RDESC1_BUFFER_INDEX     0x7fff0000
 97 #define RDESC1_BUFFER_LENGTH    0x0000ffff
 98 
 99 struct ep93xx_rstat
100 {
101         u32     rstat0;
102         u32     rstat1;
103 };
104 
105 #define RSTAT0_RFP              0x80000000
106 #define RSTAT0_RWE              0x40000000
107 #define RSTAT0_EOF              0x20000000
108 #define RSTAT0_EOB              0x10000000
109 #define RSTAT0_AM               0x00c00000
110 #define RSTAT0_RX_ERR           0x00200000
111 #define RSTAT0_OE               0x00100000
112 #define RSTAT0_FE               0x00080000
113 #define RSTAT0_RUNT             0x00040000
114 #define RSTAT0_EDATA            0x00020000
115 #define RSTAT0_CRCE             0x00010000
116 #define RSTAT0_CRCI             0x00008000
117 #define RSTAT0_HTI              0x00003f00
118 #define RSTAT1_RFP              0x80000000
119 #define RSTAT1_BUFFER_INDEX     0x7fff0000
120 #define RSTAT1_FRAME_LENGTH     0x0000ffff
121 
122 struct ep93xx_tdesc
123 {
124         u32     buf_addr;
125         u32     tdesc1;
126 };
127 
128 #define TDESC1_EOF              0x80000000
129 #define TDESC1_BUFFER_INDEX     0x7fff0000
130 #define TDESC1_BUFFER_ABORT     0x00008000
131 #define TDESC1_BUFFER_LENGTH    0x00000fff
132 
133 struct ep93xx_tstat
134 {
135         u32     tstat0;
136 };
137 
138 #define TSTAT0_TXFP             0x80000000
139 #define TSTAT0_TXWE             0x40000000
140 #define TSTAT0_FA               0x20000000
141 #define TSTAT0_LCRS             0x10000000
142 #define TSTAT0_OW               0x04000000
143 #define TSTAT0_TXU              0x02000000
144 #define TSTAT0_ECOLL            0x01000000
145 #define TSTAT0_NCOLL            0x001f0000
146 #define TSTAT0_BUFFER_INDEX     0x00007fff
147 
148 struct ep93xx_descs
149 {
150         struct ep93xx_rdesc     rdesc[RX_QUEUE_ENTRIES];
151         struct ep93xx_tdesc     tdesc[TX_QUEUE_ENTRIES];
152         struct ep93xx_rstat     rstat[RX_QUEUE_ENTRIES];
153         struct ep93xx_tstat     tstat[TX_QUEUE_ENTRIES];
154 };
155 
156 struct ep93xx_priv
157 {
158         struct resource         *res;
159         void __iomem            *base_addr;
160         int                     irq;
161 
162         struct ep93xx_descs     *descs;
163         dma_addr_t              descs_dma_addr;
164 
165         void                    *rx_buf[RX_QUEUE_ENTRIES];
166         void                    *tx_buf[TX_QUEUE_ENTRIES];
167 
168         spinlock_t              rx_lock;
169         unsigned int            rx_pointer;
170         unsigned int            tx_clean_pointer;
171         unsigned int            tx_pointer;
172         spinlock_t              tx_pending_lock;
173         unsigned int            tx_pending;
174 
175         struct net_device       *dev;
176         struct napi_struct      napi;
177 
178         struct mii_if_info      mii;
179         u8                      mdc_divisor;
180 };
181 
182 #define rdb(ep, off)            __raw_readb((ep)->base_addr + (off))
183 #define rdw(ep, off)            __raw_readw((ep)->base_addr + (off))
184 #define rdl(ep, off)            __raw_readl((ep)->base_addr + (off))
185 #define wrb(ep, off, val)       __raw_writeb((val), (ep)->base_addr + (off))
186 #define wrw(ep, off, val)       __raw_writew((val), (ep)->base_addr + (off))
187 #define wrl(ep, off, val)       __raw_writel((val), (ep)->base_addr + (off))
188 
189 static int ep93xx_mdio_read(struct net_device *dev, int phy_id, int reg)
190 {
191         struct ep93xx_priv *ep = netdev_priv(dev);
192         int data;
193         int i;
194 
195         wrl(ep, REG_MIICMD, REG_MIICMD_READ | (phy_id << 5) | reg);
196 
197         for (i = 0; i < 10; i++) {
198                 if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
199                         break;
200                 msleep(1);
201         }
202 
203         if (i == 10) {
204                 pr_info("mdio read timed out\n");
205                 data = 0xffff;
206         } else {
207                 data = rdl(ep, REG_MIIDATA);
208         }
209 
210         return data;
211 }
212 
213 static void ep93xx_mdio_write(struct net_device *dev, int phy_id, int reg, int data)
214 {
215         struct ep93xx_priv *ep = netdev_priv(dev);
216         int i;
217 
218         wrl(ep, REG_MIIDATA, data);
219         wrl(ep, REG_MIICMD, REG_MIICMD_WRITE | (phy_id << 5) | reg);
220 
221         for (i = 0; i < 10; i++) {
222                 if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
223                         break;
224                 msleep(1);
225         }
226 
227         if (i == 10)
228                 pr_info("mdio write timed out\n");
229 }
230 
231 static int ep93xx_rx(struct net_device *dev, int processed, int budget)
232 {
233         struct ep93xx_priv *ep = netdev_priv(dev);
234 
235         while (processed < budget) {
236                 int entry;
237                 struct ep93xx_rstat *rstat;
238                 u32 rstat0;
239                 u32 rstat1;
240                 int length;
241                 struct sk_buff *skb;
242 
243                 entry = ep->rx_pointer;
244                 rstat = ep->descs->rstat + entry;
245 
246                 rstat0 = rstat->rstat0;
247                 rstat1 = rstat->rstat1;
248                 if (!(rstat0 & RSTAT0_RFP) || !(rstat1 & RSTAT1_RFP))
249                         break;
250 
251                 rstat->rstat0 = 0;
252                 rstat->rstat1 = 0;
253 
254                 if (!(rstat0 & RSTAT0_EOF))
255                         pr_crit("not end-of-frame %.8x %.8x\n", rstat0, rstat1);
256                 if (!(rstat0 & RSTAT0_EOB))
257                         pr_crit("not end-of-buffer %.8x %.8x\n", rstat0, rstat1);
258                 if ((rstat1 & RSTAT1_BUFFER_INDEX) >> 16 != entry)
259                         pr_crit("entry mismatch %.8x %.8x\n", rstat0, rstat1);
260 
261                 if (!(rstat0 & RSTAT0_RWE)) {
262                         dev->stats.rx_errors++;
263                         if (rstat0 & RSTAT0_OE)
264                                 dev->stats.rx_fifo_errors++;
265                         if (rstat0 & RSTAT0_FE)
266                                 dev->stats.rx_frame_errors++;
267                         if (rstat0 & (RSTAT0_RUNT | RSTAT0_EDATA))
268                                 dev->stats.rx_length_errors++;
269                         if (rstat0 & RSTAT0_CRCE)
270                                 dev->stats.rx_crc_errors++;
271                         goto err;
272                 }
273 
274                 length = rstat1 & RSTAT1_FRAME_LENGTH;
275                 if (length > MAX_PKT_SIZE) {
276                         pr_notice("invalid length %.8x %.8x\n", rstat0, rstat1);
277                         goto err;
278                 }
279 
280                 /* Strip FCS.  */
281                 if (rstat0 & RSTAT0_CRCI)
282                         length -= 4;
283 
284                 skb = netdev_alloc_skb(dev, length + 2);
285                 if (likely(skb != NULL)) {
286                         struct ep93xx_rdesc *rxd = &ep->descs->rdesc[entry];
287                         skb_reserve(skb, 2);
288                         dma_sync_single_for_cpu(dev->dev.parent, rxd->buf_addr,
289                                                 length, DMA_FROM_DEVICE);
290                         skb_copy_to_linear_data(skb, ep->rx_buf[entry], length);
291                         dma_sync_single_for_device(dev->dev.parent,
292                                                    rxd->buf_addr, length,
293                                                    DMA_FROM_DEVICE);
294                         skb_put(skb, length);
295                         skb->protocol = eth_type_trans(skb, dev);
296 
297                         netif_receive_skb(skb);
298 
299                         dev->stats.rx_packets++;
300                         dev->stats.rx_bytes += length;
301                 } else {
302                         dev->stats.rx_dropped++;
303                 }
304 
305 err:
306                 ep->rx_pointer = (entry + 1) & (RX_QUEUE_ENTRIES - 1);
307                 processed++;
308         }
309 
310         return processed;
311 }
312 
313 static int ep93xx_have_more_rx(struct ep93xx_priv *ep)
314 {
315         struct ep93xx_rstat *rstat = ep->descs->rstat + ep->rx_pointer;
316         return !!((rstat->rstat0 & RSTAT0_RFP) && (rstat->rstat1 & RSTAT1_RFP));
317 }
318 
319 static int ep93xx_poll(struct napi_struct *napi, int budget)
320 {
321         struct ep93xx_priv *ep = container_of(napi, struct ep93xx_priv, napi);
322         struct net_device *dev = ep->dev;
323         int rx = 0;
324 
325 poll_some_more:
326         rx = ep93xx_rx(dev, rx, budget);
327         if (rx < budget) {
328                 int more = 0;
329 
330                 spin_lock_irq(&ep->rx_lock);
331                 __napi_complete(napi);
332                 wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
333                 if (ep93xx_have_more_rx(ep)) {
334                         wrl(ep, REG_INTEN, REG_INTEN_TX);
335                         wrl(ep, REG_INTSTSP, REG_INTSTS_RX);
336                         more = 1;
337                 }
338                 spin_unlock_irq(&ep->rx_lock);
339 
340                 if (more && napi_reschedule(napi))
341                         goto poll_some_more;
342         }
343 
344         if (rx) {
345                 wrw(ep, REG_RXDENQ, rx);
346                 wrw(ep, REG_RXSTSENQ, rx);
347         }
348 
349         return rx;
350 }
351 
352 static int ep93xx_xmit(struct sk_buff *skb, struct net_device *dev)
353 {
354         struct ep93xx_priv *ep = netdev_priv(dev);
355         struct ep93xx_tdesc *txd;
356         int entry;
357 
358         if (unlikely(skb->len > MAX_PKT_SIZE)) {
359                 dev->stats.tx_dropped++;
360                 dev_kfree_skb(skb);
361                 return NETDEV_TX_OK;
362         }
363 
364         entry = ep->tx_pointer;
365         ep->tx_pointer = (ep->tx_pointer + 1) & (TX_QUEUE_ENTRIES - 1);
366 
367         txd = &ep->descs->tdesc[entry];
368 
369         txd->tdesc1 = TDESC1_EOF | (entry << 16) | (skb->len & 0xfff);
370         dma_sync_single_for_cpu(dev->dev.parent, txd->buf_addr, skb->len,
371                                 DMA_TO_DEVICE);
372         skb_copy_and_csum_dev(skb, ep->tx_buf[entry]);
373         dma_sync_single_for_device(dev->dev.parent, txd->buf_addr, skb->len,
374                                    DMA_TO_DEVICE);
375         dev_kfree_skb(skb);
376 
377         spin_lock_irq(&ep->tx_pending_lock);
378         ep->tx_pending++;
379         if (ep->tx_pending == TX_QUEUE_ENTRIES)
380                 netif_stop_queue(dev);
381         spin_unlock_irq(&ep->tx_pending_lock);
382 
383         wrl(ep, REG_TXDENQ, 1);
384 
385         return NETDEV_TX_OK;
386 }
387 
388 static void ep93xx_tx_complete(struct net_device *dev)
389 {
390         struct ep93xx_priv *ep = netdev_priv(dev);
391         int wake;
392 
393         wake = 0;
394 
395         spin_lock(&ep->tx_pending_lock);
396         while (1) {
397                 int entry;
398                 struct ep93xx_tstat *tstat;
399                 u32 tstat0;
400 
401                 entry = ep->tx_clean_pointer;
402                 tstat = ep->descs->tstat + entry;
403 
404                 tstat0 = tstat->tstat0;
405                 if (!(tstat0 & TSTAT0_TXFP))
406                         break;
407 
408                 tstat->tstat0 = 0;
409 
410                 if (tstat0 & TSTAT0_FA)
411                         pr_crit("frame aborted %.8x\n", tstat0);
412                 if ((tstat0 & TSTAT0_BUFFER_INDEX) != entry)
413                         pr_crit("entry mismatch %.8x\n", tstat0);
414 
415                 if (tstat0 & TSTAT0_TXWE) {
416                         int length = ep->descs->tdesc[entry].tdesc1 & 0xfff;
417 
418                         dev->stats.tx_packets++;
419                         dev->stats.tx_bytes += length;
420                 } else {
421                         dev->stats.tx_errors++;
422                 }
423 
424                 if (tstat0 & TSTAT0_OW)
425                         dev->stats.tx_window_errors++;
426                 if (tstat0 & TSTAT0_TXU)
427                         dev->stats.tx_fifo_errors++;
428                 dev->stats.collisions += (tstat0 >> 16) & 0x1f;
429 
430                 ep->tx_clean_pointer = (entry + 1) & (TX_QUEUE_ENTRIES - 1);
431                 if (ep->tx_pending == TX_QUEUE_ENTRIES)
432                         wake = 1;
433                 ep->tx_pending--;
434         }
435         spin_unlock(&ep->tx_pending_lock);
436 
437         if (wake)
438                 netif_wake_queue(dev);
439 }
440 
441 static irqreturn_t ep93xx_irq(int irq, void *dev_id)
442 {
443         struct net_device *dev = dev_id;
444         struct ep93xx_priv *ep = netdev_priv(dev);
445         u32 status;
446 
447         status = rdl(ep, REG_INTSTSC);
448         if (status == 0)
449                 return IRQ_NONE;
450 
451         if (status & REG_INTSTS_RX) {
452                 spin_lock(&ep->rx_lock);
453                 if (likely(napi_schedule_prep(&ep->napi))) {
454                         wrl(ep, REG_INTEN, REG_INTEN_TX);
455                         __napi_schedule(&ep->napi);
456                 }
457                 spin_unlock(&ep->rx_lock);
458         }
459 
460         if (status & REG_INTSTS_TX)
461                 ep93xx_tx_complete(dev);
462 
463         return IRQ_HANDLED;
464 }
465 
466 static void ep93xx_free_buffers(struct ep93xx_priv *ep)
467 {
468         struct device *dev = ep->dev->dev.parent;
469         int i;
470 
471         for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
472                 dma_addr_t d;
473 
474                 d = ep->descs->rdesc[i].buf_addr;
475                 if (d)
476                         dma_unmap_single(dev, d, PKT_BUF_SIZE, DMA_FROM_DEVICE);
477 
478                 if (ep->rx_buf[i] != NULL)
479                         kfree(ep->rx_buf[i]);
480         }
481 
482         for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
483                 dma_addr_t d;
484 
485                 d = ep->descs->tdesc[i].buf_addr;
486                 if (d)
487                         dma_unmap_single(dev, d, PKT_BUF_SIZE, DMA_TO_DEVICE);
488 
489                 if (ep->tx_buf[i] != NULL)
490                         kfree(ep->tx_buf[i]);
491         }
492 
493         dma_free_coherent(dev, sizeof(struct ep93xx_descs), ep->descs,
494                                                         ep->descs_dma_addr);
495 }
496 
497 static int ep93xx_alloc_buffers(struct ep93xx_priv *ep)
498 {
499         struct device *dev = ep->dev->dev.parent;
500         int i;
501 
502         ep->descs = dma_alloc_coherent(dev, sizeof(struct ep93xx_descs),
503                                 &ep->descs_dma_addr, GFP_KERNEL);
504         if (ep->descs == NULL)
505                 return 1;
506 
507         for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
508                 void *buf;
509                 dma_addr_t d;
510 
511                 buf = kmalloc(PKT_BUF_SIZE, GFP_KERNEL);
512                 if (buf == NULL)
513                         goto err;
514 
515                 d = dma_map_single(dev, buf, PKT_BUF_SIZE, DMA_FROM_DEVICE);
516                 if (dma_mapping_error(dev, d)) {
517                         kfree(buf);
518                         goto err;
519                 }
520 
521                 ep->rx_buf[i] = buf;
522                 ep->descs->rdesc[i].buf_addr = d;
523                 ep->descs->rdesc[i].rdesc1 = (i << 16) | PKT_BUF_SIZE;
524         }
525 
526         for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
527                 void *buf;
528                 dma_addr_t d;
529 
530                 buf = kmalloc(PKT_BUF_SIZE, GFP_KERNEL);
531                 if (buf == NULL)
532                         goto err;
533 
534                 d = dma_map_single(dev, buf, PKT_BUF_SIZE, DMA_TO_DEVICE);
535                 if (dma_mapping_error(dev, d)) {
536                         kfree(buf);
537                         goto err;
538                 }
539 
540                 ep->tx_buf[i] = buf;
541                 ep->descs->tdesc[i].buf_addr = d;
542         }
543 
544         return 0;
545 
546 err:
547         ep93xx_free_buffers(ep);
548         return 1;
549 }
550 
551 static int ep93xx_start_hw(struct net_device *dev)
552 {
553         struct ep93xx_priv *ep = netdev_priv(dev);
554         unsigned long addr;
555         int i;
556 
557         wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
558         for (i = 0; i < 10; i++) {
559                 if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
560                         break;
561                 msleep(1);
562         }
563 
564         if (i == 10) {
565                 pr_crit("hw failed to reset\n");
566                 return 1;
567         }
568 
569         wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9));
570 
571         /* Does the PHY support preamble suppress?  */
572         if ((ep93xx_mdio_read(dev, ep->mii.phy_id, MII_BMSR) & 0x0040) != 0)
573                 wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9) | (1 << 8));
574 
575         /* Receive descriptor ring.  */
576         addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rdesc);
577         wrl(ep, REG_RXDQBADD, addr);
578         wrl(ep, REG_RXDCURADD, addr);
579         wrw(ep, REG_RXDQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rdesc));
580 
581         /* Receive status ring.  */
582         addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rstat);
583         wrl(ep, REG_RXSTSQBADD, addr);
584         wrl(ep, REG_RXSTSQCURADD, addr);
585         wrw(ep, REG_RXSTSQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rstat));
586 
587         /* Transmit descriptor ring.  */
588         addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tdesc);
589         wrl(ep, REG_TXDQBADD, addr);
590         wrl(ep, REG_TXDQCURADD, addr);
591         wrw(ep, REG_TXDQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tdesc));
592 
593         /* Transmit status ring.  */
594         addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tstat);
595         wrl(ep, REG_TXSTSQBADD, addr);
596         wrl(ep, REG_TXSTSQCURADD, addr);
597         wrw(ep, REG_TXSTSQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tstat));
598 
599         wrl(ep, REG_BMCTL, REG_BMCTL_ENABLE_TX | REG_BMCTL_ENABLE_RX);
600         wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
601         wrl(ep, REG_GIINTMSK, 0);
602 
603         for (i = 0; i < 10; i++) {
604                 if ((rdl(ep, REG_BMSTS) & REG_BMSTS_RX_ACTIVE) != 0)
605                         break;
606                 msleep(1);
607         }
608 
609         if (i == 10) {
610                 pr_crit("hw failed to start\n");
611                 return 1;
612         }
613 
614         wrl(ep, REG_RXDENQ, RX_QUEUE_ENTRIES);
615         wrl(ep, REG_RXSTSENQ, RX_QUEUE_ENTRIES);
616 
617         wrb(ep, REG_INDAD0, dev->dev_addr[0]);
618         wrb(ep, REG_INDAD1, dev->dev_addr[1]);
619         wrb(ep, REG_INDAD2, dev->dev_addr[2]);
620         wrb(ep, REG_INDAD3, dev->dev_addr[3]);
621         wrb(ep, REG_INDAD4, dev->dev_addr[4]);
622         wrb(ep, REG_INDAD5, dev->dev_addr[5]);
623         wrl(ep, REG_AFP, 0);
624 
625         wrl(ep, REG_MAXFRMLEN, (MAX_PKT_SIZE << 16) | MAX_PKT_SIZE);
626 
627         wrl(ep, REG_RXCTL, REG_RXCTL_DEFAULT);
628         wrl(ep, REG_TXCTL, REG_TXCTL_ENABLE);
629 
630         return 0;
631 }
632 
633 static void ep93xx_stop_hw(struct net_device *dev)
634 {
635         struct ep93xx_priv *ep = netdev_priv(dev);
636         int i;
637 
638         wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
639         for (i = 0; i < 10; i++) {
640                 if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
641                         break;
642                 msleep(1);
643         }
644 
645         if (i == 10)
646                 pr_crit("hw failed to reset\n");
647 }
648 
649 static int ep93xx_open(struct net_device *dev)
650 {
651         struct ep93xx_priv *ep = netdev_priv(dev);
652         int err;
653 
654         if (ep93xx_alloc_buffers(ep))
655                 return -ENOMEM;
656 
657         napi_enable(&ep->napi);
658 
659         if (ep93xx_start_hw(dev)) {
660                 napi_disable(&ep->napi);
661                 ep93xx_free_buffers(ep);
662                 return -EIO;
663         }
664 
665         spin_lock_init(&ep->rx_lock);
666         ep->rx_pointer = 0;
667         ep->tx_clean_pointer = 0;
668         ep->tx_pointer = 0;
669         spin_lock_init(&ep->tx_pending_lock);
670         ep->tx_pending = 0;
671 
672         err = request_irq(ep->irq, ep93xx_irq, IRQF_SHARED, dev->name, dev);
673         if (err) {
674                 napi_disable(&ep->napi);
675                 ep93xx_stop_hw(dev);
676                 ep93xx_free_buffers(ep);
677                 return err;
678         }
679 
680         wrl(ep, REG_GIINTMSK, REG_GIINTMSK_ENABLE);
681 
682         netif_start_queue(dev);
683 
684         return 0;
685 }
686 
687 static int ep93xx_close(struct net_device *dev)
688 {
689         struct ep93xx_priv *ep = netdev_priv(dev);
690 
691         napi_disable(&ep->napi);
692         netif_stop_queue(dev);
693 
694         wrl(ep, REG_GIINTMSK, 0);
695         free_irq(ep->irq, dev);
696         ep93xx_stop_hw(dev);
697         ep93xx_free_buffers(ep);
698 
699         return 0;
700 }
701 
702 static int ep93xx_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
703 {
704         struct ep93xx_priv *ep = netdev_priv(dev);
705         struct mii_ioctl_data *data = if_mii(ifr);
706 
707         return generic_mii_ioctl(&ep->mii, data, cmd, NULL);
708 }
709 
710 static void ep93xx_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
711 {
712         strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
713         strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
714 }
715 
716 static int ep93xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
717 {
718         struct ep93xx_priv *ep = netdev_priv(dev);
719         return mii_ethtool_gset(&ep->mii, cmd);
720 }
721 
722 static int ep93xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
723 {
724         struct ep93xx_priv *ep = netdev_priv(dev);
725         return mii_ethtool_sset(&ep->mii, cmd);
726 }
727 
728 static int ep93xx_nway_reset(struct net_device *dev)
729 {
730         struct ep93xx_priv *ep = netdev_priv(dev);
731         return mii_nway_restart(&ep->mii);
732 }
733 
734 static u32 ep93xx_get_link(struct net_device *dev)
735 {
736         struct ep93xx_priv *ep = netdev_priv(dev);
737         return mii_link_ok(&ep->mii);
738 }
739 
740 static const struct ethtool_ops ep93xx_ethtool_ops = {
741         .get_drvinfo            = ep93xx_get_drvinfo,
742         .get_settings           = ep93xx_get_settings,
743         .set_settings           = ep93xx_set_settings,
744         .nway_reset             = ep93xx_nway_reset,
745         .get_link               = ep93xx_get_link,
746 };
747 
748 static const struct net_device_ops ep93xx_netdev_ops = {
749         .ndo_open               = ep93xx_open,
750         .ndo_stop               = ep93xx_close,
751         .ndo_start_xmit         = ep93xx_xmit,
752         .ndo_do_ioctl           = ep93xx_ioctl,
753         .ndo_validate_addr      = eth_validate_addr,
754         .ndo_change_mtu         = eth_change_mtu,
755         .ndo_set_mac_address    = eth_mac_addr,
756 };
757 
758 static struct net_device *ep93xx_dev_alloc(struct ep93xx_eth_data *data)
759 {
760         struct net_device *dev;
761 
762         dev = alloc_etherdev(sizeof(struct ep93xx_priv));
763         if (dev == NULL)
764                 return NULL;
765 
766         memcpy(dev->dev_addr, data->dev_addr, ETH_ALEN);
767 
768         dev->ethtool_ops = &ep93xx_ethtool_ops;
769         dev->netdev_ops = &ep93xx_netdev_ops;
770 
771         dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
772 
773         return dev;
774 }
775 
776 
777 static int ep93xx_eth_remove(struct platform_device *pdev)
778 {
779         struct net_device *dev;
780         struct ep93xx_priv *ep;
781 
782         dev = platform_get_drvdata(pdev);
783         if (dev == NULL)
784                 return 0;
785 
786         ep = netdev_priv(dev);
787 
788         /* @@@ Force down.  */
789         unregister_netdev(dev);
790         ep93xx_free_buffers(ep);
791 
792         if (ep->base_addr != NULL)
793                 iounmap(ep->base_addr);
794 
795         if (ep->res != NULL) {
796                 release_resource(ep->res);
797                 kfree(ep->res);
798         }
799 
800         free_netdev(dev);
801 
802         return 0;
803 }
804 
805 static int ep93xx_eth_probe(struct platform_device *pdev)
806 {
807         struct ep93xx_eth_data *data;
808         struct net_device *dev;
809         struct ep93xx_priv *ep;
810         struct resource *mem;
811         int irq;
812         int err;
813 
814         if (pdev == NULL)
815                 return -ENODEV;
816         data = dev_get_platdata(&pdev->dev);
817 
818         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
819         irq = platform_get_irq(pdev, 0);
820         if (!mem || irq < 0)
821                 return -ENXIO;
822 
823         dev = ep93xx_dev_alloc(data);
824         if (dev == NULL) {
825                 err = -ENOMEM;
826                 goto err_out;
827         }
828         ep = netdev_priv(dev);
829         ep->dev = dev;
830         SET_NETDEV_DEV(dev, &pdev->dev);
831         netif_napi_add(dev, &ep->napi, ep93xx_poll, 64);
832 
833         platform_set_drvdata(pdev, dev);
834 
835         ep->res = request_mem_region(mem->start, resource_size(mem),
836                                      dev_name(&pdev->dev));
837         if (ep->res == NULL) {
838                 dev_err(&pdev->dev, "Could not reserve memory region\n");
839                 err = -ENOMEM;
840                 goto err_out;
841         }
842 
843         ep->base_addr = ioremap(mem->start, resource_size(mem));
844         if (ep->base_addr == NULL) {
845                 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
846                 err = -EIO;
847                 goto err_out;
848         }
849         ep->irq = irq;
850 
851         ep->mii.phy_id = data->phy_id;
852         ep->mii.phy_id_mask = 0x1f;
853         ep->mii.reg_num_mask = 0x1f;
854         ep->mii.dev = dev;
855         ep->mii.mdio_read = ep93xx_mdio_read;
856         ep->mii.mdio_write = ep93xx_mdio_write;
857         ep->mdc_divisor = 40;   /* Max HCLK 100 MHz, min MDIO clk 2.5 MHz.  */
858 
859         if (is_zero_ether_addr(dev->dev_addr))
860                 eth_hw_addr_random(dev);
861 
862         err = register_netdev(dev);
863         if (err) {
864                 dev_err(&pdev->dev, "Failed to register netdev\n");
865                 goto err_out;
866         }
867 
868         printk(KERN_INFO "%s: ep93xx on-chip ethernet, IRQ %d, %pM\n",
869                         dev->name, ep->irq, dev->dev_addr);
870 
871         return 0;
872 
873 err_out:
874         ep93xx_eth_remove(pdev);
875         return err;
876 }
877 
878 
879 static struct platform_driver ep93xx_eth_driver = {
880         .probe          = ep93xx_eth_probe,
881         .remove         = ep93xx_eth_remove,
882         .driver         = {
883                 .name   = "ep93xx-eth",
884                 .owner  = THIS_MODULE,
885         },
886 };
887 
888 module_platform_driver(ep93xx_eth_driver);
889 
890 MODULE_LICENSE("GPL");
891 MODULE_ALIAS("platform:ep93xx-eth");
892 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us