Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4

Linux/drivers/net/ethernet/cadence/macb.c

  1 /*
  2  * Cadence MACB/GEM Ethernet Controller driver
  3  *
  4  * Copyright (C) 2004-2006 Atmel Corporation
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License version 2 as
  8  * published by the Free Software Foundation.
  9  */
 10 
 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 12 #include <linux/clk.h>
 13 #include <linux/module.h>
 14 #include <linux/moduleparam.h>
 15 #include <linux/kernel.h>
 16 #include <linux/types.h>
 17 #include <linux/circ_buf.h>
 18 #include <linux/slab.h>
 19 #include <linux/init.h>
 20 #include <linux/io.h>
 21 #include <linux/gpio.h>
 22 #include <linux/interrupt.h>
 23 #include <linux/netdevice.h>
 24 #include <linux/etherdevice.h>
 25 #include <linux/dma-mapping.h>
 26 #include <linux/platform_data/macb.h>
 27 #include <linux/platform_device.h>
 28 #include <linux/phy.h>
 29 #include <linux/of.h>
 30 #include <linux/of_device.h>
 31 #include <linux/of_mdio.h>
 32 #include <linux/of_net.h>
 33 
 34 #include "macb.h"
 35 
 36 #define MACB_RX_BUFFER_SIZE     128
 37 #define RX_BUFFER_MULTIPLE      64  /* bytes */
 38 #define RX_RING_SIZE            512 /* must be power of 2 */
 39 #define RX_RING_BYTES           (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
 40 
 41 #define TX_RING_SIZE            128 /* must be power of 2 */
 42 #define TX_RING_BYTES           (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
 43 
 44 /* level of occupied TX descriptors under which we wake up TX process */
 45 #define MACB_TX_WAKEUP_THRESH   (3 * TX_RING_SIZE / 4)
 46 
 47 #define MACB_RX_INT_FLAGS       (MACB_BIT(RCOMP) | MACB_BIT(RXUBR)      \
 48                                  | MACB_BIT(ISR_ROVR))
 49 #define MACB_TX_ERR_FLAGS       (MACB_BIT(ISR_TUND)                     \
 50                                         | MACB_BIT(ISR_RLE)             \
 51                                         | MACB_BIT(TXERR))
 52 #define MACB_TX_INT_FLAGS       (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
 53 
 54 #define MACB_MAX_TX_LEN         ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1))
 55 #define GEM_MAX_TX_LEN          ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1))
 56 
 57 #define GEM_MTU_MIN_SIZE        68
 58 
 59 /*
 60  * Graceful stop timeouts in us. We should allow up to
 61  * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
 62  */
 63 #define MACB_HALT_TIMEOUT       1230
 64 
 65 /* Ring buffer accessors */
 66 static unsigned int macb_tx_ring_wrap(unsigned int index)
 67 {
 68         return index & (TX_RING_SIZE - 1);
 69 }
 70 
 71 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
 72                                           unsigned int index)
 73 {
 74         return &queue->tx_ring[macb_tx_ring_wrap(index)];
 75 }
 76 
 77 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
 78                                        unsigned int index)
 79 {
 80         return &queue->tx_skb[macb_tx_ring_wrap(index)];
 81 }
 82 
 83 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
 84 {
 85         dma_addr_t offset;
 86 
 87         offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
 88 
 89         return queue->tx_ring_dma + offset;
 90 }
 91 
 92 static unsigned int macb_rx_ring_wrap(unsigned int index)
 93 {
 94         return index & (RX_RING_SIZE - 1);
 95 }
 96 
 97 static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
 98 {
 99         return &bp->rx_ring[macb_rx_ring_wrap(index)];
100 }
101 
102 static void *macb_rx_buffer(struct macb *bp, unsigned int index)
103 {
104         return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
105 }
106 
107 /* I/O accessors */
108 static u32 hw_readl_native(struct macb *bp, int offset)
109 {
110         return __raw_readl(bp->regs + offset);
111 }
112 
113 static void hw_writel_native(struct macb *bp, int offset, u32 value)
114 {
115         __raw_writel(value, bp->regs + offset);
116 }
117 
118 static u32 hw_readl(struct macb *bp, int offset)
119 {
120         return readl_relaxed(bp->regs + offset);
121 }
122 
123 static void hw_writel(struct macb *bp, int offset, u32 value)
124 {
125         writel_relaxed(value, bp->regs + offset);
126 }
127 
128 /*
129  * Find the CPU endianness by using the loopback bit of NCR register. When the
130  * CPU is in big endian we need to program swaped mode for management
131  * descriptor access.
132  */
133 static bool hw_is_native_io(void __iomem *addr)
134 {
135         u32 value = MACB_BIT(LLB);
136 
137         __raw_writel(value, addr + MACB_NCR);
138         value = __raw_readl(addr + MACB_NCR);
139 
140         /* Write 0 back to disable everything */
141         __raw_writel(0, addr + MACB_NCR);
142 
143         return value == MACB_BIT(LLB);
144 }
145 
146 static bool hw_is_gem(void __iomem *addr, bool native_io)
147 {
148         u32 id;
149 
150         if (native_io)
151                 id = __raw_readl(addr + MACB_MID);
152         else
153                 id = readl_relaxed(addr + MACB_MID);
154 
155         return MACB_BFEXT(IDNUM, id) >= 0x2;
156 }
157 
158 static void macb_set_hwaddr(struct macb *bp)
159 {
160         u32 bottom;
161         u16 top;
162 
163         bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
164         macb_or_gem_writel(bp, SA1B, bottom);
165         top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
166         macb_or_gem_writel(bp, SA1T, top);
167 
168         /* Clear unused address register sets */
169         macb_or_gem_writel(bp, SA2B, 0);
170         macb_or_gem_writel(bp, SA2T, 0);
171         macb_or_gem_writel(bp, SA3B, 0);
172         macb_or_gem_writel(bp, SA3T, 0);
173         macb_or_gem_writel(bp, SA4B, 0);
174         macb_or_gem_writel(bp, SA4T, 0);
175 }
176 
177 static void macb_get_hwaddr(struct macb *bp)
178 {
179         struct macb_platform_data *pdata;
180         u32 bottom;
181         u16 top;
182         u8 addr[6];
183         int i;
184 
185         pdata = dev_get_platdata(&bp->pdev->dev);
186 
187         /* Check all 4 address register for vaild address */
188         for (i = 0; i < 4; i++) {
189                 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
190                 top = macb_or_gem_readl(bp, SA1T + i * 8);
191 
192                 if (pdata && pdata->rev_eth_addr) {
193                         addr[5] = bottom & 0xff;
194                         addr[4] = (bottom >> 8) & 0xff;
195                         addr[3] = (bottom >> 16) & 0xff;
196                         addr[2] = (bottom >> 24) & 0xff;
197                         addr[1] = top & 0xff;
198                         addr[0] = (top & 0xff00) >> 8;
199                 } else {
200                         addr[0] = bottom & 0xff;
201                         addr[1] = (bottom >> 8) & 0xff;
202                         addr[2] = (bottom >> 16) & 0xff;
203                         addr[3] = (bottom >> 24) & 0xff;
204                         addr[4] = top & 0xff;
205                         addr[5] = (top >> 8) & 0xff;
206                 }
207 
208                 if (is_valid_ether_addr(addr)) {
209                         memcpy(bp->dev->dev_addr, addr, sizeof(addr));
210                         return;
211                 }
212         }
213 
214         dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
215         eth_hw_addr_random(bp->dev);
216 }
217 
218 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
219 {
220         struct macb *bp = bus->priv;
221         int value;
222 
223         macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
224                               | MACB_BF(RW, MACB_MAN_READ)
225                               | MACB_BF(PHYA, mii_id)
226                               | MACB_BF(REGA, regnum)
227                               | MACB_BF(CODE, MACB_MAN_CODE)));
228 
229         /* wait for end of transfer */
230         while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
231                 cpu_relax();
232 
233         value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
234 
235         return value;
236 }
237 
238 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
239                            u16 value)
240 {
241         struct macb *bp = bus->priv;
242 
243         macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
244                               | MACB_BF(RW, MACB_MAN_WRITE)
245                               | MACB_BF(PHYA, mii_id)
246                               | MACB_BF(REGA, regnum)
247                               | MACB_BF(CODE, MACB_MAN_CODE)
248                               | MACB_BF(DATA, value)));
249 
250         /* wait for end of transfer */
251         while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
252                 cpu_relax();
253 
254         return 0;
255 }
256 
257 /**
258  * macb_set_tx_clk() - Set a clock to a new frequency
259  * @clk         Pointer to the clock to change
260  * @rate        New frequency in Hz
261  * @dev         Pointer to the struct net_device
262  */
263 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
264 {
265         long ferr, rate, rate_rounded;
266 
267         if (!clk)
268                 return;
269 
270         switch (speed) {
271         case SPEED_10:
272                 rate = 2500000;
273                 break;
274         case SPEED_100:
275                 rate = 25000000;
276                 break;
277         case SPEED_1000:
278                 rate = 125000000;
279                 break;
280         default:
281                 return;
282         }
283 
284         rate_rounded = clk_round_rate(clk, rate);
285         if (rate_rounded < 0)
286                 return;
287 
288         /* RGMII allows 50 ppm frequency error. Test and warn if this limit
289          * is not satisfied.
290          */
291         ferr = abs(rate_rounded - rate);
292         ferr = DIV_ROUND_UP(ferr, rate / 100000);
293         if (ferr > 5)
294                 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
295                                 rate);
296 
297         if (clk_set_rate(clk, rate_rounded))
298                 netdev_err(dev, "adjusting tx_clk failed.\n");
299 }
300 
301 static void macb_handle_link_change(struct net_device *dev)
302 {
303         struct macb *bp = netdev_priv(dev);
304         struct phy_device *phydev = bp->phy_dev;
305         unsigned long flags;
306         int status_change = 0;
307 
308         spin_lock_irqsave(&bp->lock, flags);
309 
310         if (phydev->link) {
311                 if ((bp->speed != phydev->speed) ||
312                     (bp->duplex != phydev->duplex)) {
313                         u32 reg;
314 
315                         reg = macb_readl(bp, NCFGR);
316                         reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
317                         if (macb_is_gem(bp))
318                                 reg &= ~GEM_BIT(GBE);
319 
320                         if (phydev->duplex)
321                                 reg |= MACB_BIT(FD);
322                         if (phydev->speed == SPEED_100)
323                                 reg |= MACB_BIT(SPD);
324                         if (phydev->speed == SPEED_1000 &&
325                             bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
326                                 reg |= GEM_BIT(GBE);
327 
328                         macb_or_gem_writel(bp, NCFGR, reg);
329 
330                         bp->speed = phydev->speed;
331                         bp->duplex = phydev->duplex;
332                         status_change = 1;
333                 }
334         }
335 
336         if (phydev->link != bp->link) {
337                 if (!phydev->link) {
338                         bp->speed = 0;
339                         bp->duplex = -1;
340                 }
341                 bp->link = phydev->link;
342 
343                 status_change = 1;
344         }
345 
346         spin_unlock_irqrestore(&bp->lock, flags);
347 
348         if (status_change) {
349                 if (phydev->link) {
350                         /* Update the TX clock rate if and only if the link is
351                          * up and there has been a link change.
352                          */
353                         macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
354 
355                         netif_carrier_on(dev);
356                         netdev_info(dev, "link up (%d/%s)\n",
357                                     phydev->speed,
358                                     phydev->duplex == DUPLEX_FULL ?
359                                     "Full" : "Half");
360                 } else {
361                         netif_carrier_off(dev);
362                         netdev_info(dev, "link down\n");
363                 }
364         }
365 }
366 
367 /* based on au1000_eth. c*/
368 static int macb_mii_probe(struct net_device *dev)
369 {
370         struct macb *bp = netdev_priv(dev);
371         struct macb_platform_data *pdata;
372         struct phy_device *phydev;
373         int phy_irq;
374         int ret;
375 
376         phydev = phy_find_first(bp->mii_bus);
377         if (!phydev) {
378                 netdev_err(dev, "no PHY found\n");
379                 return -ENXIO;
380         }
381 
382         pdata = dev_get_platdata(&bp->pdev->dev);
383         if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
384                 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int");
385                 if (!ret) {
386                         phy_irq = gpio_to_irq(pdata->phy_irq_pin);
387                         phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
388                 }
389         }
390 
391         /* attach the mac to the phy */
392         ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
393                                  bp->phy_interface);
394         if (ret) {
395                 netdev_err(dev, "Could not attach to PHY\n");
396                 return ret;
397         }
398 
399         /* mask with MAC supported features */
400         if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
401                 phydev->supported &= PHY_GBIT_FEATURES;
402         else
403                 phydev->supported &= PHY_BASIC_FEATURES;
404 
405         if (bp->caps & MACB_CAPS_NO_GIGABIT_HALF)
406                 phydev->supported &= ~SUPPORTED_1000baseT_Half;
407 
408         phydev->advertising = phydev->supported;
409 
410         bp->link = 0;
411         bp->speed = 0;
412         bp->duplex = -1;
413         bp->phy_dev = phydev;
414 
415         return 0;
416 }
417 
418 static int macb_mii_init(struct macb *bp)
419 {
420         struct macb_platform_data *pdata;
421         struct device_node *np;
422         int err = -ENXIO, i;
423 
424         /* Enable management port */
425         macb_writel(bp, NCR, MACB_BIT(MPE));
426 
427         bp->mii_bus = mdiobus_alloc();
428         if (bp->mii_bus == NULL) {
429                 err = -ENOMEM;
430                 goto err_out;
431         }
432 
433         bp->mii_bus->name = "MACB_mii_bus";
434         bp->mii_bus->read = &macb_mdio_read;
435         bp->mii_bus->write = &macb_mdio_write;
436         snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
437                 bp->pdev->name, bp->pdev->id);
438         bp->mii_bus->priv = bp;
439         bp->mii_bus->parent = &bp->dev->dev;
440         pdata = dev_get_platdata(&bp->pdev->dev);
441 
442         bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
443         if (!bp->mii_bus->irq) {
444                 err = -ENOMEM;
445                 goto err_out_free_mdiobus;
446         }
447 
448         dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
449 
450         np = bp->pdev->dev.of_node;
451         if (np) {
452                 /* try dt phy registration */
453                 err = of_mdiobus_register(bp->mii_bus, np);
454 
455                 /* fallback to standard phy registration if no phy were
456                    found during dt phy registration */
457                 if (!err && !phy_find_first(bp->mii_bus)) {
458                         for (i = 0; i < PHY_MAX_ADDR; i++) {
459                                 struct phy_device *phydev;
460 
461                                 phydev = mdiobus_scan(bp->mii_bus, i);
462                                 if (IS_ERR(phydev)) {
463                                         err = PTR_ERR(phydev);
464                                         break;
465                                 }
466                         }
467 
468                         if (err)
469                                 goto err_out_unregister_bus;
470                 }
471         } else {
472                 for (i = 0; i < PHY_MAX_ADDR; i++)
473                         bp->mii_bus->irq[i] = PHY_POLL;
474 
475                 if (pdata)
476                         bp->mii_bus->phy_mask = pdata->phy_mask;
477 
478                 err = mdiobus_register(bp->mii_bus);
479         }
480 
481         if (err)
482                 goto err_out_free_mdio_irq;
483 
484         err = macb_mii_probe(bp->dev);
485         if (err)
486                 goto err_out_unregister_bus;
487 
488         return 0;
489 
490 err_out_unregister_bus:
491         mdiobus_unregister(bp->mii_bus);
492 err_out_free_mdio_irq:
493         kfree(bp->mii_bus->irq);
494 err_out_free_mdiobus:
495         mdiobus_free(bp->mii_bus);
496 err_out:
497         return err;
498 }
499 
500 static void macb_update_stats(struct macb *bp)
501 {
502         u32 *p = &bp->hw_stats.macb.rx_pause_frames;
503         u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
504         int offset = MACB_PFR;
505 
506         WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
507 
508         for(; p < end; p++, offset += 4)
509                 *p += bp->macb_reg_readl(bp, offset);
510 }
511 
512 static int macb_halt_tx(struct macb *bp)
513 {
514         unsigned long   halt_time, timeout;
515         u32             status;
516 
517         macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
518 
519         timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
520         do {
521                 halt_time = jiffies;
522                 status = macb_readl(bp, TSR);
523                 if (!(status & MACB_BIT(TGO)))
524                         return 0;
525 
526                 usleep_range(10, 250);
527         } while (time_before(halt_time, timeout));
528 
529         return -ETIMEDOUT;
530 }
531 
532 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
533 {
534         if (tx_skb->mapping) {
535                 if (tx_skb->mapped_as_page)
536                         dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
537                                        tx_skb->size, DMA_TO_DEVICE);
538                 else
539                         dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
540                                          tx_skb->size, DMA_TO_DEVICE);
541                 tx_skb->mapping = 0;
542         }
543 
544         if (tx_skb->skb) {
545                 dev_kfree_skb_any(tx_skb->skb);
546                 tx_skb->skb = NULL;
547         }
548 }
549 
550 static void macb_tx_error_task(struct work_struct *work)
551 {
552         struct macb_queue       *queue = container_of(work, struct macb_queue,
553                                                       tx_error_task);
554         struct macb             *bp = queue->bp;
555         struct macb_tx_skb      *tx_skb;
556         struct macb_dma_desc    *desc;
557         struct sk_buff          *skb;
558         unsigned int            tail;
559         unsigned long           flags;
560 
561         netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
562                     (unsigned int)(queue - bp->queues),
563                     queue->tx_tail, queue->tx_head);
564 
565         /* Prevent the queue IRQ handlers from running: each of them may call
566          * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
567          * As explained below, we have to halt the transmission before updating
568          * TBQP registers so we call netif_tx_stop_all_queues() to notify the
569          * network engine about the macb/gem being halted.
570          */
571         spin_lock_irqsave(&bp->lock, flags);
572 
573         /* Make sure nobody is trying to queue up new packets */
574         netif_tx_stop_all_queues(bp->dev);
575 
576         /*
577          * Stop transmission now
578          * (in case we have just queued new packets)
579          * macb/gem must be halted to write TBQP register
580          */
581         if (macb_halt_tx(bp))
582                 /* Just complain for now, reinitializing TX path can be good */
583                 netdev_err(bp->dev, "BUG: halt tx timed out\n");
584 
585         /*
586          * Treat frames in TX queue including the ones that caused the error.
587          * Free transmit buffers in upper layer.
588          */
589         for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
590                 u32     ctrl;
591 
592                 desc = macb_tx_desc(queue, tail);
593                 ctrl = desc->ctrl;
594                 tx_skb = macb_tx_skb(queue, tail);
595                 skb = tx_skb->skb;
596 
597                 if (ctrl & MACB_BIT(TX_USED)) {
598                         /* skb is set for the last buffer of the frame */
599                         while (!skb) {
600                                 macb_tx_unmap(bp, tx_skb);
601                                 tail++;
602                                 tx_skb = macb_tx_skb(queue, tail);
603                                 skb = tx_skb->skb;
604                         }
605 
606                         /* ctrl still refers to the first buffer descriptor
607                          * since it's the only one written back by the hardware
608                          */
609                         if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
610                                 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
611                                             macb_tx_ring_wrap(tail), skb->data);
612                                 bp->stats.tx_packets++;
613                                 bp->stats.tx_bytes += skb->len;
614                         }
615                 } else {
616                         /*
617                          * "Buffers exhausted mid-frame" errors may only happen
618                          * if the driver is buggy, so complain loudly about those.
619                          * Statistics are updated by hardware.
620                          */
621                         if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
622                                 netdev_err(bp->dev,
623                                            "BUG: TX buffers exhausted mid-frame\n");
624 
625                         desc->ctrl = ctrl | MACB_BIT(TX_USED);
626                 }
627 
628                 macb_tx_unmap(bp, tx_skb);
629         }
630 
631         /* Set end of TX queue */
632         desc = macb_tx_desc(queue, 0);
633         desc->addr = 0;
634         desc->ctrl = MACB_BIT(TX_USED);
635 
636         /* Make descriptor updates visible to hardware */
637         wmb();
638 
639         /* Reinitialize the TX desc queue */
640         queue_writel(queue, TBQP, queue->tx_ring_dma);
641         /* Make TX ring reflect state of hardware */
642         queue->tx_head = 0;
643         queue->tx_tail = 0;
644 
645         /* Housework before enabling TX IRQ */
646         macb_writel(bp, TSR, macb_readl(bp, TSR));
647         queue_writel(queue, IER, MACB_TX_INT_FLAGS);
648 
649         /* Now we are ready to start transmission again */
650         netif_tx_start_all_queues(bp->dev);
651         macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
652 
653         spin_unlock_irqrestore(&bp->lock, flags);
654 }
655 
656 static void macb_tx_interrupt(struct macb_queue *queue)
657 {
658         unsigned int tail;
659         unsigned int head;
660         u32 status;
661         struct macb *bp = queue->bp;
662         u16 queue_index = queue - bp->queues;
663 
664         status = macb_readl(bp, TSR);
665         macb_writel(bp, TSR, status);
666 
667         if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
668                 queue_writel(queue, ISR, MACB_BIT(TCOMP));
669 
670         netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
671                 (unsigned long)status);
672 
673         head = queue->tx_head;
674         for (tail = queue->tx_tail; tail != head; tail++) {
675                 struct macb_tx_skb      *tx_skb;
676                 struct sk_buff          *skb;
677                 struct macb_dma_desc    *desc;
678                 u32                     ctrl;
679 
680                 desc = macb_tx_desc(queue, tail);
681 
682                 /* Make hw descriptor updates visible to CPU */
683                 rmb();
684 
685                 ctrl = desc->ctrl;
686 
687                 /* TX_USED bit is only set by hardware on the very first buffer
688                  * descriptor of the transmitted frame.
689                  */
690                 if (!(ctrl & MACB_BIT(TX_USED)))
691                         break;
692 
693                 /* Process all buffers of the current transmitted frame */
694                 for (;; tail++) {
695                         tx_skb = macb_tx_skb(queue, tail);
696                         skb = tx_skb->skb;
697 
698                         /* First, update TX stats if needed */
699                         if (skb) {
700                                 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
701                                             macb_tx_ring_wrap(tail), skb->data);
702                                 bp->stats.tx_packets++;
703                                 bp->stats.tx_bytes += skb->len;
704                         }
705 
706                         /* Now we can safely release resources */
707                         macb_tx_unmap(bp, tx_skb);
708 
709                         /* skb is set only for the last buffer of the frame.
710                          * WARNING: at this point skb has been freed by
711                          * macb_tx_unmap().
712                          */
713                         if (skb)
714                                 break;
715                 }
716         }
717 
718         queue->tx_tail = tail;
719         if (__netif_subqueue_stopped(bp->dev, queue_index) &&
720             CIRC_CNT(queue->tx_head, queue->tx_tail,
721                      TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH)
722                 netif_wake_subqueue(bp->dev, queue_index);
723 }
724 
725 static void gem_rx_refill(struct macb *bp)
726 {
727         unsigned int            entry;
728         struct sk_buff          *skb;
729         dma_addr_t              paddr;
730 
731         while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, RX_RING_SIZE) > 0) {
732                 entry = macb_rx_ring_wrap(bp->rx_prepared_head);
733 
734                 /* Make hw descriptor updates visible to CPU */
735                 rmb();
736 
737                 bp->rx_prepared_head++;
738 
739                 if (bp->rx_skbuff[entry] == NULL) {
740                         /* allocate sk_buff for this free entry in ring */
741                         skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
742                         if (unlikely(skb == NULL)) {
743                                 netdev_err(bp->dev,
744                                            "Unable to allocate sk_buff\n");
745                                 break;
746                         }
747 
748                         /* now fill corresponding descriptor entry */
749                         paddr = dma_map_single(&bp->pdev->dev, skb->data,
750                                                bp->rx_buffer_size, DMA_FROM_DEVICE);
751                         if (dma_mapping_error(&bp->pdev->dev, paddr)) {
752                                 dev_kfree_skb(skb);
753                                 break;
754                         }
755 
756                         bp->rx_skbuff[entry] = skb;
757 
758                         if (entry == RX_RING_SIZE - 1)
759                                 paddr |= MACB_BIT(RX_WRAP);
760                         bp->rx_ring[entry].addr = paddr;
761                         bp->rx_ring[entry].ctrl = 0;
762 
763                         /* properly align Ethernet header */
764                         skb_reserve(skb, NET_IP_ALIGN);
765                 } else {
766                         bp->rx_ring[entry].addr &= ~MACB_BIT(RX_USED);
767                         bp->rx_ring[entry].ctrl = 0;
768                 }
769         }
770 
771         /* Make descriptor updates visible to hardware */
772         wmb();
773 
774         netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
775                    bp->rx_prepared_head, bp->rx_tail);
776 }
777 
778 /* Mark DMA descriptors from begin up to and not including end as unused */
779 static void discard_partial_frame(struct macb *bp, unsigned int begin,
780                                   unsigned int end)
781 {
782         unsigned int frag;
783 
784         for (frag = begin; frag != end; frag++) {
785                 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
786                 desc->addr &= ~MACB_BIT(RX_USED);
787         }
788 
789         /* Make descriptor updates visible to hardware */
790         wmb();
791 
792         /*
793          * When this happens, the hardware stats registers for
794          * whatever caused this is updated, so we don't have to record
795          * anything.
796          */
797 }
798 
799 static int gem_rx(struct macb *bp, int budget)
800 {
801         unsigned int            len;
802         unsigned int            entry;
803         struct sk_buff          *skb;
804         struct macb_dma_desc    *desc;
805         int                     count = 0;
806 
807         while (count < budget) {
808                 u32 addr, ctrl;
809 
810                 entry = macb_rx_ring_wrap(bp->rx_tail);
811                 desc = &bp->rx_ring[entry];
812 
813                 /* Make hw descriptor updates visible to CPU */
814                 rmb();
815 
816                 addr = desc->addr;
817                 ctrl = desc->ctrl;
818 
819                 if (!(addr & MACB_BIT(RX_USED)))
820                         break;
821 
822                 bp->rx_tail++;
823                 count++;
824 
825                 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
826                         netdev_err(bp->dev,
827                                    "not whole frame pointed by descriptor\n");
828                         bp->stats.rx_dropped++;
829                         break;
830                 }
831                 skb = bp->rx_skbuff[entry];
832                 if (unlikely(!skb)) {
833                         netdev_err(bp->dev,
834                                    "inconsistent Rx descriptor chain\n");
835                         bp->stats.rx_dropped++;
836                         break;
837                 }
838                 /* now everything is ready for receiving packet */
839                 bp->rx_skbuff[entry] = NULL;
840                 len = ctrl & bp->rx_frm_len_mask;
841 
842                 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
843 
844                 skb_put(skb, len);
845                 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr));
846                 dma_unmap_single(&bp->pdev->dev, addr,
847                                  bp->rx_buffer_size, DMA_FROM_DEVICE);
848 
849                 skb->protocol = eth_type_trans(skb, bp->dev);
850                 skb_checksum_none_assert(skb);
851                 if (bp->dev->features & NETIF_F_RXCSUM &&
852                     !(bp->dev->flags & IFF_PROMISC) &&
853                     GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
854                         skb->ip_summed = CHECKSUM_UNNECESSARY;
855 
856                 bp->stats.rx_packets++;
857                 bp->stats.rx_bytes += skb->len;
858 
859 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
860                 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
861                             skb->len, skb->csum);
862                 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
863                                skb_mac_header(skb), 16, true);
864                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
865                                skb->data, 32, true);
866 #endif
867 
868                 netif_receive_skb(skb);
869         }
870 
871         gem_rx_refill(bp);
872 
873         return count;
874 }
875 
876 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
877                          unsigned int last_frag)
878 {
879         unsigned int len;
880         unsigned int frag;
881         unsigned int offset;
882         struct sk_buff *skb;
883         struct macb_dma_desc *desc;
884 
885         desc = macb_rx_desc(bp, last_frag);
886         len = desc->ctrl & bp->rx_frm_len_mask;
887 
888         netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
889                 macb_rx_ring_wrap(first_frag),
890                 macb_rx_ring_wrap(last_frag), len);
891 
892         /*
893          * The ethernet header starts NET_IP_ALIGN bytes into the
894          * first buffer. Since the header is 14 bytes, this makes the
895          * payload word-aligned.
896          *
897          * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
898          * the two padding bytes into the skb so that we avoid hitting
899          * the slowpath in memcpy(), and pull them off afterwards.
900          */
901         skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
902         if (!skb) {
903                 bp->stats.rx_dropped++;
904                 for (frag = first_frag; ; frag++) {
905                         desc = macb_rx_desc(bp, frag);
906                         desc->addr &= ~MACB_BIT(RX_USED);
907                         if (frag == last_frag)
908                                 break;
909                 }
910 
911                 /* Make descriptor updates visible to hardware */
912                 wmb();
913 
914                 return 1;
915         }
916 
917         offset = 0;
918         len += NET_IP_ALIGN;
919         skb_checksum_none_assert(skb);
920         skb_put(skb, len);
921 
922         for (frag = first_frag; ; frag++) {
923                 unsigned int frag_len = bp->rx_buffer_size;
924 
925                 if (offset + frag_len > len) {
926                         BUG_ON(frag != last_frag);
927                         frag_len = len - offset;
928                 }
929                 skb_copy_to_linear_data_offset(skb, offset,
930                                 macb_rx_buffer(bp, frag), frag_len);
931                 offset += bp->rx_buffer_size;
932                 desc = macb_rx_desc(bp, frag);
933                 desc->addr &= ~MACB_BIT(RX_USED);
934 
935                 if (frag == last_frag)
936                         break;
937         }
938 
939         /* Make descriptor updates visible to hardware */
940         wmb();
941 
942         __skb_pull(skb, NET_IP_ALIGN);
943         skb->protocol = eth_type_trans(skb, bp->dev);
944 
945         bp->stats.rx_packets++;
946         bp->stats.rx_bytes += skb->len;
947         netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
948                    skb->len, skb->csum);
949         netif_receive_skb(skb);
950 
951         return 0;
952 }
953 
954 static int macb_rx(struct macb *bp, int budget)
955 {
956         int received = 0;
957         unsigned int tail;
958         int first_frag = -1;
959 
960         for (tail = bp->rx_tail; budget > 0; tail++) {
961                 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
962                 u32 addr, ctrl;
963 
964                 /* Make hw descriptor updates visible to CPU */
965                 rmb();
966 
967                 addr = desc->addr;
968                 ctrl = desc->ctrl;
969 
970                 if (!(addr & MACB_BIT(RX_USED)))
971                         break;
972 
973                 if (ctrl & MACB_BIT(RX_SOF)) {
974                         if (first_frag != -1)
975                                 discard_partial_frame(bp, first_frag, tail);
976                         first_frag = tail;
977                 }
978 
979                 if (ctrl & MACB_BIT(RX_EOF)) {
980                         int dropped;
981                         BUG_ON(first_frag == -1);
982 
983                         dropped = macb_rx_frame(bp, first_frag, tail);
984                         first_frag = -1;
985                         if (!dropped) {
986                                 received++;
987                                 budget--;
988                         }
989                 }
990         }
991 
992         if (first_frag != -1)
993                 bp->rx_tail = first_frag;
994         else
995                 bp->rx_tail = tail;
996 
997         return received;
998 }
999 
1000 static int macb_poll(struct napi_struct *napi, int budget)
1001 {
1002         struct macb *bp = container_of(napi, struct macb, napi);
1003         int work_done;
1004         u32 status;
1005 
1006         status = macb_readl(bp, RSR);
1007         macb_writel(bp, RSR, status);
1008 
1009         work_done = 0;
1010 
1011         netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
1012                    (unsigned long)status, budget);
1013 
1014         work_done = bp->macbgem_ops.mog_rx(bp, budget);
1015         if (work_done < budget) {
1016                 napi_complete(napi);
1017 
1018                 /* Packets received while interrupts were disabled */
1019                 status = macb_readl(bp, RSR);
1020                 if (status) {
1021                         if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1022                                 macb_writel(bp, ISR, MACB_BIT(RCOMP));
1023                         napi_reschedule(napi);
1024                 } else {
1025                         macb_writel(bp, IER, MACB_RX_INT_FLAGS);
1026                 }
1027         }
1028 
1029         /* TODO: Handle errors */
1030 
1031         return work_done;
1032 }
1033 
1034 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1035 {
1036         struct macb_queue *queue = dev_id;
1037         struct macb *bp = queue->bp;
1038         struct net_device *dev = bp->dev;
1039         u32 status, ctrl;
1040 
1041         status = queue_readl(queue, ISR);
1042 
1043         if (unlikely(!status))
1044                 return IRQ_NONE;
1045 
1046         spin_lock(&bp->lock);
1047 
1048         while (status) {
1049                 /* close possible race with dev_close */
1050                 if (unlikely(!netif_running(dev))) {
1051                         queue_writel(queue, IDR, -1);
1052                         break;
1053                 }
1054 
1055                 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1056                             (unsigned int)(queue - bp->queues),
1057                             (unsigned long)status);
1058 
1059                 if (status & MACB_RX_INT_FLAGS) {
1060                         /*
1061                          * There's no point taking any more interrupts
1062                          * until we have processed the buffers. The
1063                          * scheduling call may fail if the poll routine
1064                          * is already scheduled, so disable interrupts
1065                          * now.
1066                          */
1067                         queue_writel(queue, IDR, MACB_RX_INT_FLAGS);
1068                         if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1069                                 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1070 
1071                         if (napi_schedule_prep(&bp->napi)) {
1072                                 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1073                                 __napi_schedule(&bp->napi);
1074                         }
1075                 }
1076 
1077                 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1078                         queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1079                         schedule_work(&queue->tx_error_task);
1080 
1081                         if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1082                                 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1083 
1084                         break;
1085                 }
1086 
1087                 if (status & MACB_BIT(TCOMP))
1088                         macb_tx_interrupt(queue);
1089 
1090                 /*
1091                  * Link change detection isn't possible with RMII, so we'll
1092                  * add that if/when we get our hands on a full-blown MII PHY.
1093                  */
1094 
1095                 /* There is a hardware issue under heavy load where DMA can
1096                  * stop, this causes endless "used buffer descriptor read"
1097                  * interrupts but it can be cleared by re-enabling RX. See
1098                  * the at91 manual, section 41.3.1 or the Zynq manual
1099                  * section 16.7.4 for details.
1100                  */
1101                 if (status & MACB_BIT(RXUBR)) {
1102                         ctrl = macb_readl(bp, NCR);
1103                         macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1104                         macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1105 
1106                         if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1107                                 macb_writel(bp, ISR, MACB_BIT(RXUBR));
1108                 }
1109 
1110                 if (status & MACB_BIT(ISR_ROVR)) {
1111                         /* We missed at least one packet */
1112                         if (macb_is_gem(bp))
1113                                 bp->hw_stats.gem.rx_overruns++;
1114                         else
1115                                 bp->hw_stats.macb.rx_overruns++;
1116 
1117                         if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1118                                 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1119                 }
1120 
1121                 if (status & MACB_BIT(HRESP)) {
1122                         /*
1123                          * TODO: Reset the hardware, and maybe move the
1124                          * netdev_err to a lower-priority context as well
1125                          * (work queue?)
1126                          */
1127                         netdev_err(dev, "DMA bus error: HRESP not OK\n");
1128 
1129                         if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1130                                 queue_writel(queue, ISR, MACB_BIT(HRESP));
1131                 }
1132 
1133                 status = queue_readl(queue, ISR);
1134         }
1135 
1136         spin_unlock(&bp->lock);
1137 
1138         return IRQ_HANDLED;
1139 }
1140 
1141 #ifdef CONFIG_NET_POLL_CONTROLLER
1142 /*
1143  * Polling receive - used by netconsole and other diagnostic tools
1144  * to allow network i/o with interrupts disabled.
1145  */
1146 static void macb_poll_controller(struct net_device *dev)
1147 {
1148         struct macb *bp = netdev_priv(dev);
1149         struct macb_queue *queue;
1150         unsigned long flags;
1151         unsigned int q;
1152 
1153         local_irq_save(flags);
1154         for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1155                 macb_interrupt(dev->irq, queue);
1156         local_irq_restore(flags);
1157 }
1158 #endif
1159 
1160 static unsigned int macb_tx_map(struct macb *bp,
1161                                 struct macb_queue *queue,
1162                                 struct sk_buff *skb)
1163 {
1164         dma_addr_t mapping;
1165         unsigned int len, entry, i, tx_head = queue->tx_head;
1166         struct macb_tx_skb *tx_skb = NULL;
1167         struct macb_dma_desc *desc;
1168         unsigned int offset, size, count = 0;
1169         unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1170         unsigned int eof = 1;
1171         u32 ctrl;
1172 
1173         /* First, map non-paged data */
1174         len = skb_headlen(skb);
1175         offset = 0;
1176         while (len) {
1177                 size = min(len, bp->max_tx_length);
1178                 entry = macb_tx_ring_wrap(tx_head);
1179                 tx_skb = &queue->tx_skb[entry];
1180 
1181                 mapping = dma_map_single(&bp->pdev->dev,
1182                                          skb->data + offset,
1183                                          size, DMA_TO_DEVICE);
1184                 if (dma_mapping_error(&bp->pdev->dev, mapping))
1185                         goto dma_error;
1186 
1187                 /* Save info to properly release resources */
1188                 tx_skb->skb = NULL;
1189                 tx_skb->mapping = mapping;
1190                 tx_skb->size = size;
1191                 tx_skb->mapped_as_page = false;
1192 
1193                 len -= size;
1194                 offset += size;
1195                 count++;
1196                 tx_head++;
1197         }
1198 
1199         /* Then, map paged data from fragments */
1200         for (f = 0; f < nr_frags; f++) {
1201                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1202 
1203                 len = skb_frag_size(frag);
1204                 offset = 0;
1205                 while (len) {
1206                         size = min(len, bp->max_tx_length);
1207                         entry = macb_tx_ring_wrap(tx_head);
1208                         tx_skb = &queue->tx_skb[entry];
1209 
1210                         mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1211                                                    offset, size, DMA_TO_DEVICE);
1212                         if (dma_mapping_error(&bp->pdev->dev, mapping))
1213                                 goto dma_error;
1214 
1215                         /* Save info to properly release resources */
1216                         tx_skb->skb = NULL;
1217                         tx_skb->mapping = mapping;
1218                         tx_skb->size = size;
1219                         tx_skb->mapped_as_page = true;
1220 
1221                         len -= size;
1222                         offset += size;
1223                         count++;
1224                         tx_head++;
1225                 }
1226         }
1227 
1228         /* Should never happen */
1229         if (unlikely(tx_skb == NULL)) {
1230                 netdev_err(bp->dev, "BUG! empty skb!\n");
1231                 return 0;
1232         }
1233 
1234         /* This is the last buffer of the frame: save socket buffer */
1235         tx_skb->skb = skb;
1236 
1237         /* Update TX ring: update buffer descriptors in reverse order
1238          * to avoid race condition
1239          */
1240 
1241         /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1242          * to set the end of TX queue
1243          */
1244         i = tx_head;
1245         entry = macb_tx_ring_wrap(i);
1246         ctrl = MACB_BIT(TX_USED);
1247         desc = &queue->tx_ring[entry];
1248         desc->ctrl = ctrl;
1249 
1250         do {
1251                 i--;
1252                 entry = macb_tx_ring_wrap(i);
1253                 tx_skb = &queue->tx_skb[entry];
1254                 desc = &queue->tx_ring[entry];
1255 
1256                 ctrl = (u32)tx_skb->size;
1257                 if (eof) {
1258                         ctrl |= MACB_BIT(TX_LAST);
1259                         eof = 0;
1260                 }
1261                 if (unlikely(entry == (TX_RING_SIZE - 1)))
1262                         ctrl |= MACB_BIT(TX_WRAP);
1263 
1264                 /* Set TX buffer descriptor */
1265                 desc->addr = tx_skb->mapping;
1266                 /* desc->addr must be visible to hardware before clearing
1267                  * 'TX_USED' bit in desc->ctrl.
1268                  */
1269                 wmb();
1270                 desc->ctrl = ctrl;
1271         } while (i != queue->tx_head);
1272 
1273         queue->tx_head = tx_head;
1274 
1275         return count;
1276 
1277 dma_error:
1278         netdev_err(bp->dev, "TX DMA map failed\n");
1279 
1280         for (i = queue->tx_head; i != tx_head; i++) {
1281                 tx_skb = macb_tx_skb(queue, i);
1282 
1283                 macb_tx_unmap(bp, tx_skb);
1284         }
1285 
1286         return 0;
1287 }
1288 
1289 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1290 {
1291         u16 queue_index = skb_get_queue_mapping(skb);
1292         struct macb *bp = netdev_priv(dev);
1293         struct macb_queue *queue = &bp->queues[queue_index];
1294         unsigned long flags;
1295         unsigned int count, nr_frags, frag_size, f;
1296 
1297 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1298         netdev_vdbg(bp->dev,
1299                    "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1300                    queue_index, skb->len, skb->head, skb->data,
1301                    skb_tail_pointer(skb), skb_end_pointer(skb));
1302         print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1303                        skb->data, 16, true);
1304 #endif
1305 
1306         /* Count how many TX buffer descriptors are needed to send this
1307          * socket buffer: skb fragments of jumbo frames may need to be
1308          * splitted into many buffer descriptors.
1309          */
1310         count = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
1311         nr_frags = skb_shinfo(skb)->nr_frags;
1312         for (f = 0; f < nr_frags; f++) {
1313                 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1314                 count += DIV_ROUND_UP(frag_size, bp->max_tx_length);
1315         }
1316 
1317         spin_lock_irqsave(&bp->lock, flags);
1318 
1319         /* This is a hard error, log it. */
1320         if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < count) {
1321                 netif_stop_subqueue(dev, queue_index);
1322                 spin_unlock_irqrestore(&bp->lock, flags);
1323                 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1324                            queue->tx_head, queue->tx_tail);
1325                 return NETDEV_TX_BUSY;
1326         }
1327 
1328         /* Map socket buffer for DMA transfer */
1329         if (!macb_tx_map(bp, queue, skb)) {
1330                 dev_kfree_skb_any(skb);
1331                 goto unlock;
1332         }
1333 
1334         /* Make newly initialized descriptor visible to hardware */
1335         wmb();
1336 
1337         skb_tx_timestamp(skb);
1338 
1339         macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1340 
1341         if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < 1)
1342                 netif_stop_subqueue(dev, queue_index);
1343 
1344 unlock:
1345         spin_unlock_irqrestore(&bp->lock, flags);
1346 
1347         return NETDEV_TX_OK;
1348 }
1349 
1350 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1351 {
1352         if (!macb_is_gem(bp)) {
1353                 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1354         } else {
1355                 bp->rx_buffer_size = size;
1356 
1357                 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1358                         netdev_dbg(bp->dev,
1359                                     "RX buffer must be multiple of %d bytes, expanding\n",
1360                                     RX_BUFFER_MULTIPLE);
1361                         bp->rx_buffer_size =
1362                                 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1363                 }
1364         }
1365 
1366         netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n",
1367                    bp->dev->mtu, bp->rx_buffer_size);
1368 }
1369 
1370 static void gem_free_rx_buffers(struct macb *bp)
1371 {
1372         struct sk_buff          *skb;
1373         struct macb_dma_desc    *desc;
1374         dma_addr_t              addr;
1375         int i;
1376 
1377         if (!bp->rx_skbuff)
1378                 return;
1379 
1380         for (i = 0; i < RX_RING_SIZE; i++) {
1381                 skb = bp->rx_skbuff[i];
1382 
1383                 if (skb == NULL)
1384                         continue;
1385 
1386                 desc = &bp->rx_ring[i];
1387                 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1388                 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
1389                                  DMA_FROM_DEVICE);
1390                 dev_kfree_skb_any(skb);
1391                 skb = NULL;
1392         }
1393 
1394         kfree(bp->rx_skbuff);
1395         bp->rx_skbuff = NULL;
1396 }
1397 
1398 static void macb_free_rx_buffers(struct macb *bp)
1399 {
1400         if (bp->rx_buffers) {
1401                 dma_free_coherent(&bp->pdev->dev,
1402                                   RX_RING_SIZE * bp->rx_buffer_size,
1403                                   bp->rx_buffers, bp->rx_buffers_dma);
1404                 bp->rx_buffers = NULL;
1405         }
1406 }
1407 
1408 static void macb_free_consistent(struct macb *bp)
1409 {
1410         struct macb_queue *queue;
1411         unsigned int q;
1412 
1413         bp->macbgem_ops.mog_free_rx_buffers(bp);
1414         if (bp->rx_ring) {
1415                 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
1416                                   bp->rx_ring, bp->rx_ring_dma);
1417                 bp->rx_ring = NULL;
1418         }
1419 
1420         for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1421                 kfree(queue->tx_skb);
1422                 queue->tx_skb = NULL;
1423                 if (queue->tx_ring) {
1424                         dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
1425                                           queue->tx_ring, queue->tx_ring_dma);
1426                         queue->tx_ring = NULL;
1427                 }
1428         }
1429 }
1430 
1431 static int gem_alloc_rx_buffers(struct macb *bp)
1432 {
1433         int size;
1434 
1435         size = RX_RING_SIZE * sizeof(struct sk_buff *);
1436         bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
1437         if (!bp->rx_skbuff)
1438                 return -ENOMEM;
1439         else
1440                 netdev_dbg(bp->dev,
1441                            "Allocated %d RX struct sk_buff entries at %p\n",
1442                            RX_RING_SIZE, bp->rx_skbuff);
1443         return 0;
1444 }
1445 
1446 static int macb_alloc_rx_buffers(struct macb *bp)
1447 {
1448         int size;
1449 
1450         size = RX_RING_SIZE * bp->rx_buffer_size;
1451         bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1452                                             &bp->rx_buffers_dma, GFP_KERNEL);
1453         if (!bp->rx_buffers)
1454                 return -ENOMEM;
1455         else
1456                 netdev_dbg(bp->dev,
1457                            "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1458                            size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
1459         return 0;
1460 }
1461 
1462 static int macb_alloc_consistent(struct macb *bp)
1463 {
1464         struct macb_queue *queue;
1465         unsigned int q;
1466         int size;
1467 
1468         for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1469                 size = TX_RING_BYTES;
1470                 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1471                                                     &queue->tx_ring_dma,
1472                                                     GFP_KERNEL);
1473                 if (!queue->tx_ring)
1474                         goto out_err;
1475                 netdev_dbg(bp->dev,
1476                            "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
1477                            q, size, (unsigned long)queue->tx_ring_dma,
1478                            queue->tx_ring);
1479 
1480                 size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
1481                 queue->tx_skb = kmalloc(size, GFP_KERNEL);
1482                 if (!queue->tx_skb)
1483                         goto out_err;
1484         }
1485 
1486         size = RX_RING_BYTES;
1487         bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1488                                          &bp->rx_ring_dma, GFP_KERNEL);
1489         if (!bp->rx_ring)
1490                 goto out_err;
1491         netdev_dbg(bp->dev,
1492                    "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1493                    size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
1494 
1495         if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
1496                 goto out_err;
1497 
1498         return 0;
1499 
1500 out_err:
1501         macb_free_consistent(bp);
1502         return -ENOMEM;
1503 }
1504 
1505 static void gem_init_rings(struct macb *bp)
1506 {
1507         struct macb_queue *queue;
1508         unsigned int q;
1509         int i;
1510 
1511         for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1512                 for (i = 0; i < TX_RING_SIZE; i++) {
1513                         queue->tx_ring[i].addr = 0;
1514                         queue->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1515                 }
1516                 queue->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1517                 queue->tx_head = 0;
1518                 queue->tx_tail = 0;
1519         }
1520 
1521         bp->rx_tail = 0;
1522         bp->rx_prepared_head = 0;
1523 
1524         gem_rx_refill(bp);
1525 }
1526 
1527 static void macb_init_rings(struct macb *bp)
1528 {
1529         int i;
1530         dma_addr_t addr;
1531 
1532         addr = bp->rx_buffers_dma;
1533         for (i = 0; i < RX_RING_SIZE; i++) {
1534                 bp->rx_ring[i].addr = addr;
1535                 bp->rx_ring[i].ctrl = 0;
1536                 addr += bp->rx_buffer_size;
1537         }
1538         bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
1539 
1540         for (i = 0; i < TX_RING_SIZE; i++) {
1541                 bp->queues[0].tx_ring[i].addr = 0;
1542                 bp->queues[0].tx_ring[i].ctrl = MACB_BIT(TX_USED);
1543         }
1544         bp->queues[0].tx_head = 0;
1545         bp->queues[0].tx_tail = 0;
1546         bp->queues[0].tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1547 
1548         bp->rx_tail = 0;
1549 }
1550 
1551 static void macb_reset_hw(struct macb *bp)
1552 {
1553         struct macb_queue *queue;
1554         unsigned int q;
1555 
1556         /*
1557          * Disable RX and TX (XXX: Should we halt the transmission
1558          * more gracefully?)
1559          */
1560         macb_writel(bp, NCR, 0);
1561 
1562         /* Clear the stats registers (XXX: Update stats first?) */
1563         macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
1564 
1565         /* Clear all status flags */
1566         macb_writel(bp, TSR, -1);
1567         macb_writel(bp, RSR, -1);
1568 
1569         /* Disable all interrupts */
1570         for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1571                 queue_writel(queue, IDR, -1);
1572                 queue_readl(queue, ISR);
1573         }
1574 }
1575 
1576 static u32 gem_mdc_clk_div(struct macb *bp)
1577 {
1578         u32 config;
1579         unsigned long pclk_hz = clk_get_rate(bp->pclk);
1580 
1581         if (pclk_hz <= 20000000)
1582                 config = GEM_BF(CLK, GEM_CLK_DIV8);
1583         else if (pclk_hz <= 40000000)
1584                 config = GEM_BF(CLK, GEM_CLK_DIV16);
1585         else if (pclk_hz <= 80000000)
1586                 config = GEM_BF(CLK, GEM_CLK_DIV32);
1587         else if (pclk_hz <= 120000000)
1588                 config = GEM_BF(CLK, GEM_CLK_DIV48);
1589         else if (pclk_hz <= 160000000)
1590                 config = GEM_BF(CLK, GEM_CLK_DIV64);
1591         else
1592                 config = GEM_BF(CLK, GEM_CLK_DIV96);
1593 
1594         return config;
1595 }
1596 
1597 static u32 macb_mdc_clk_div(struct macb *bp)
1598 {
1599         u32 config;
1600         unsigned long pclk_hz;
1601 
1602         if (macb_is_gem(bp))
1603                 return gem_mdc_clk_div(bp);
1604 
1605         pclk_hz = clk_get_rate(bp->pclk);
1606         if (pclk_hz <= 20000000)
1607                 config = MACB_BF(CLK, MACB_CLK_DIV8);
1608         else if (pclk_hz <= 40000000)
1609                 config = MACB_BF(CLK, MACB_CLK_DIV16);
1610         else if (pclk_hz <= 80000000)
1611                 config = MACB_BF(CLK, MACB_CLK_DIV32);
1612         else
1613                 config = MACB_BF(CLK, MACB_CLK_DIV64);
1614 
1615         return config;
1616 }
1617 
1618 /*
1619  * Get the DMA bus width field of the network configuration register that we
1620  * should program.  We find the width from decoding the design configuration
1621  * register to find the maximum supported data bus width.
1622  */
1623 static u32 macb_dbw(struct macb *bp)
1624 {
1625         if (!macb_is_gem(bp))
1626                 return 0;
1627 
1628         switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1629         case 4:
1630                 return GEM_BF(DBW, GEM_DBW128);
1631         case 2:
1632                 return GEM_BF(DBW, GEM_DBW64);
1633         case 1:
1634         default:
1635                 return GEM_BF(DBW, GEM_DBW32);
1636         }
1637 }
1638 
1639 /*
1640  * Configure the receive DMA engine
1641  * - use the correct receive buffer size
1642  * - set best burst length for DMA operations
1643  *   (if not supported by FIFO, it will fallback to default)
1644  * - set both rx/tx packet buffers to full memory size
1645  * These are configurable parameters for GEM.
1646  */
1647 static void macb_configure_dma(struct macb *bp)
1648 {
1649         u32 dmacfg;
1650 
1651         if (macb_is_gem(bp)) {
1652                 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1653                 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
1654                 if (bp->dma_burst_length)
1655                         dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
1656                 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
1657                 dmacfg &= ~GEM_BIT(ENDIA_PKT);
1658 
1659                 if (bp->native_io)
1660                         dmacfg &= ~GEM_BIT(ENDIA_DESC);
1661                 else
1662                         dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
1663 
1664                 if (bp->dev->features & NETIF_F_HW_CSUM)
1665                         dmacfg |= GEM_BIT(TXCOEN);
1666                 else
1667                         dmacfg &= ~GEM_BIT(TXCOEN);
1668                 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
1669                            dmacfg);
1670                 gem_writel(bp, DMACFG, dmacfg);
1671         }
1672 }
1673 
1674 static void macb_init_hw(struct macb *bp)
1675 {
1676         struct macb_queue *queue;
1677         unsigned int q;
1678 
1679         u32 config;
1680 
1681         macb_reset_hw(bp);
1682         macb_set_hwaddr(bp);
1683 
1684         config = macb_mdc_clk_div(bp);
1685         if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
1686                 config |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
1687         config |= MACB_BF(RBOF, NET_IP_ALIGN);  /* Make eth data aligned */
1688         config |= MACB_BIT(PAE);                /* PAuse Enable */
1689         config |= MACB_BIT(DRFCS);              /* Discard Rx FCS */
1690         if (bp->caps & MACB_CAPS_JUMBO)
1691                 config |= MACB_BIT(JFRAME);     /* Enable jumbo frames */
1692         else
1693                 config |= MACB_BIT(BIG);        /* Receive oversized frames */
1694         if (bp->dev->flags & IFF_PROMISC)
1695                 config |= MACB_BIT(CAF);        /* Copy All Frames */
1696         else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
1697                 config |= GEM_BIT(RXCOEN);
1698         if (!(bp->dev->flags & IFF_BROADCAST))
1699                 config |= MACB_BIT(NBC);        /* No BroadCast */
1700         config |= macb_dbw(bp);
1701         macb_writel(bp, NCFGR, config);
1702         if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
1703                 gem_writel(bp, JML, bp->jumbo_max_len);
1704         bp->speed = SPEED_10;
1705         bp->duplex = DUPLEX_HALF;
1706         bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
1707         if (bp->caps & MACB_CAPS_JUMBO)
1708                 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
1709 
1710         macb_configure_dma(bp);
1711 
1712         /* Initialize TX and RX buffers */
1713         macb_writel(bp, RBQP, bp->rx_ring_dma);
1714         for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1715                 queue_writel(queue, TBQP, queue->tx_ring_dma);
1716 
1717                 /* Enable interrupts */
1718                 queue_writel(queue, IER,
1719                              MACB_RX_INT_FLAGS |
1720                              MACB_TX_INT_FLAGS |
1721                              MACB_BIT(HRESP));
1722         }
1723 
1724         /* Enable TX and RX */
1725         macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
1726 }
1727 
1728 /*
1729  * The hash address register is 64 bits long and takes up two
1730  * locations in the memory map.  The least significant bits are stored
1731  * in EMAC_HSL and the most significant bits in EMAC_HSH.
1732  *
1733  * The unicast hash enable and the multicast hash enable bits in the
1734  * network configuration register enable the reception of hash matched
1735  * frames. The destination address is reduced to a 6 bit index into
1736  * the 64 bit hash register using the following hash function.  The
1737  * hash function is an exclusive or of every sixth bit of the
1738  * destination address.
1739  *
1740  * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1741  * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1742  * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1743  * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1744  * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1745  * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1746  *
1747  * da[0] represents the least significant bit of the first byte
1748  * received, that is, the multicast/unicast indicator, and da[47]
1749  * represents the most significant bit of the last byte received.  If
1750  * the hash index, hi[n], points to a bit that is set in the hash
1751  * register then the frame will be matched according to whether the
1752  * frame is multicast or unicast.  A multicast match will be signalled
1753  * if the multicast hash enable bit is set, da[0] is 1 and the hash
1754  * index points to a bit set in the hash register.  A unicast match
1755  * will be signalled if the unicast hash enable bit is set, da[0] is 0
1756  * and the hash index points to a bit set in the hash register.  To
1757  * receive all multicast frames, the hash register should be set with
1758  * all ones and the multicast hash enable bit should be set in the
1759  * network configuration register.
1760  */
1761 
1762 static inline int hash_bit_value(int bitnr, __u8 *addr)
1763 {
1764         if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1765                 return 1;
1766         return 0;
1767 }
1768 
1769 /*
1770  * Return the hash index value for the specified address.
1771  */
1772 static int hash_get_index(__u8 *addr)
1773 {
1774         int i, j, bitval;
1775         int hash_index = 0;
1776 
1777         for (j = 0; j < 6; j++) {
1778                 for (i = 0, bitval = 0; i < 8; i++)
1779                         bitval ^= hash_bit_value(i * 6 + j, addr);
1780 
1781                 hash_index |= (bitval << j);
1782         }
1783 
1784         return hash_index;
1785 }
1786 
1787 /*
1788  * Add multicast addresses to the internal multicast-hash table.
1789  */
1790 static void macb_sethashtable(struct net_device *dev)
1791 {
1792         struct netdev_hw_addr *ha;
1793         unsigned long mc_filter[2];
1794         unsigned int bitnr;
1795         struct macb *bp = netdev_priv(dev);
1796 
1797         mc_filter[0] = mc_filter[1] = 0;
1798 
1799         netdev_for_each_mc_addr(ha, dev) {
1800                 bitnr = hash_get_index(ha->addr);
1801                 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1802         }
1803 
1804         macb_or_gem_writel(bp, HRB, mc_filter[0]);
1805         macb_or_gem_writel(bp, HRT, mc_filter[1]);
1806 }
1807 
1808 /*
1809  * Enable/Disable promiscuous and multicast modes.
1810  */
1811 static void macb_set_rx_mode(struct net_device *dev)
1812 {
1813         unsigned long cfg;
1814         struct macb *bp = netdev_priv(dev);
1815 
1816         cfg = macb_readl(bp, NCFGR);
1817 
1818         if (dev->flags & IFF_PROMISC) {
1819                 /* Enable promiscuous mode */
1820                 cfg |= MACB_BIT(CAF);
1821 
1822                 /* Disable RX checksum offload */
1823                 if (macb_is_gem(bp))
1824                         cfg &= ~GEM_BIT(RXCOEN);
1825         } else {
1826                 /* Disable promiscuous mode */
1827                 cfg &= ~MACB_BIT(CAF);
1828 
1829                 /* Enable RX checksum offload only if requested */
1830                 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
1831                         cfg |= GEM_BIT(RXCOEN);
1832         }
1833 
1834         if (dev->flags & IFF_ALLMULTI) {
1835                 /* Enable all multicast mode */
1836                 macb_or_gem_writel(bp, HRB, -1);
1837                 macb_or_gem_writel(bp, HRT, -1);
1838                 cfg |= MACB_BIT(NCFGR_MTI);
1839         } else if (!netdev_mc_empty(dev)) {
1840                 /* Enable specific multicasts */
1841                 macb_sethashtable(dev);
1842                 cfg |= MACB_BIT(NCFGR_MTI);
1843         } else if (dev->flags & (~IFF_ALLMULTI)) {
1844                 /* Disable all multicast mode */
1845                 macb_or_gem_writel(bp, HRB, 0);
1846                 macb_or_gem_writel(bp, HRT, 0);
1847                 cfg &= ~MACB_BIT(NCFGR_MTI);
1848         }
1849 
1850         macb_writel(bp, NCFGR, cfg);
1851 }
1852 
1853 static int macb_open(struct net_device *dev)
1854 {
1855         struct macb *bp = netdev_priv(dev);
1856         size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
1857         int err;
1858 
1859         netdev_dbg(bp->dev, "open\n");
1860 
1861         /* carrier starts down */
1862         netif_carrier_off(dev);
1863 
1864         /* if the phy is not yet register, retry later*/
1865         if (!bp->phy_dev)
1866                 return -EAGAIN;
1867 
1868         /* RX buffers initialization */
1869         macb_init_rx_buffer_size(bp, bufsz);
1870 
1871         err = macb_alloc_consistent(bp);
1872         if (err) {
1873                 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1874                            err);
1875                 return err;
1876         }
1877 
1878         napi_enable(&bp->napi);
1879 
1880         bp->macbgem_ops.mog_init_rings(bp);
1881         macb_init_hw(bp);
1882 
1883         /* schedule a link state check */
1884         phy_start(bp->phy_dev);
1885 
1886         netif_tx_start_all_queues(dev);
1887 
1888         return 0;
1889 }
1890 
1891 static int macb_close(struct net_device *dev)
1892 {
1893         struct macb *bp = netdev_priv(dev);
1894         unsigned long flags;
1895 
1896         netif_tx_stop_all_queues(dev);
1897         napi_disable(&bp->napi);
1898 
1899         if (bp->phy_dev)
1900                 phy_stop(bp->phy_dev);
1901 
1902         spin_lock_irqsave(&bp->lock, flags);
1903         macb_reset_hw(bp);
1904         netif_carrier_off(dev);
1905         spin_unlock_irqrestore(&bp->lock, flags);
1906 
1907         macb_free_consistent(bp);
1908 
1909         return 0;
1910 }
1911 
1912 static int macb_change_mtu(struct net_device *dev, int new_mtu)
1913 {
1914         struct macb *bp = netdev_priv(dev);
1915         u32 max_mtu;
1916 
1917         if (netif_running(dev))
1918                 return -EBUSY;
1919 
1920         max_mtu = ETH_DATA_LEN;
1921         if (bp->caps & MACB_CAPS_JUMBO)
1922                 max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
1923 
1924         if ((new_mtu > max_mtu) || (new_mtu < GEM_MTU_MIN_SIZE))
1925                 return -EINVAL;
1926 
1927         dev->mtu = new_mtu;
1928 
1929         return 0;
1930 }
1931 
1932 static void gem_update_stats(struct macb *bp)
1933 {
1934         unsigned int i;
1935         u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1936 
1937         for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
1938                 u32 offset = gem_statistics[i].offset;
1939                 u64 val = bp->macb_reg_readl(bp, offset);
1940 
1941                 bp->ethtool_stats[i] += val;
1942                 *p += val;
1943 
1944                 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
1945                         /* Add GEM_OCTTXH, GEM_OCTRXH */
1946                         val = bp->macb_reg_readl(bp, offset + 4);
1947                         bp->ethtool_stats[i] += ((u64)val) << 32;
1948                         *(++p) += val;
1949                 }
1950         }
1951 }
1952 
1953 static struct net_device_stats *gem_get_stats(struct macb *bp)
1954 {
1955         struct gem_stats *hwstat = &bp->hw_stats.gem;
1956         struct net_device_stats *nstat = &bp->stats;
1957 
1958         gem_update_stats(bp);
1959 
1960         nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1961                             hwstat->rx_alignment_errors +
1962                             hwstat->rx_resource_errors +
1963                             hwstat->rx_overruns +
1964                             hwstat->rx_oversize_frames +
1965                             hwstat->rx_jabbers +
1966                             hwstat->rx_undersized_frames +
1967                             hwstat->rx_length_field_frame_errors);
1968         nstat->tx_errors = (hwstat->tx_late_collisions +
1969                             hwstat->tx_excessive_collisions +
1970                             hwstat->tx_underrun +
1971                             hwstat->tx_carrier_sense_errors);
1972         nstat->multicast = hwstat->rx_multicast_frames;
1973         nstat->collisions = (hwstat->tx_single_collision_frames +
1974                              hwstat->tx_multiple_collision_frames +
1975                              hwstat->tx_excessive_collisions);
1976         nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1977                                    hwstat->rx_jabbers +
1978                                    hwstat->rx_undersized_frames +
1979                                    hwstat->rx_length_field_frame_errors);
1980         nstat->rx_over_errors = hwstat->rx_resource_errors;
1981         nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1982         nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1983         nstat->rx_fifo_errors = hwstat->rx_overruns;
1984         nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1985         nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1986         nstat->tx_fifo_errors = hwstat->tx_underrun;
1987 
1988         return nstat;
1989 }
1990 
1991 static void gem_get_ethtool_stats(struct net_device *dev,
1992                                   struct ethtool_stats *stats, u64 *data)
1993 {
1994         struct macb *bp;
1995 
1996         bp = netdev_priv(dev);
1997         gem_update_stats(bp);
1998         memcpy(data, &bp->ethtool_stats, sizeof(u64) * GEM_STATS_LEN);
1999 }
2000 
2001 static int gem_get_sset_count(struct net_device *dev, int sset)
2002 {
2003         switch (sset) {
2004         case ETH_SS_STATS:
2005                 return GEM_STATS_LEN;
2006         default:
2007                 return -EOPNOTSUPP;
2008         }
2009 }
2010 
2011 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2012 {
2013         unsigned int i;
2014 
2015         switch (sset) {
2016         case ETH_SS_STATS:
2017                 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2018                         memcpy(p, gem_statistics[i].stat_string,
2019                                ETH_GSTRING_LEN);
2020                 break;
2021         }
2022 }
2023 
2024 static struct net_device_stats *macb_get_stats(struct net_device *dev)
2025 {
2026         struct macb *bp = netdev_priv(dev);
2027         struct net_device_stats *nstat = &bp->stats;
2028         struct macb_stats *hwstat = &bp->hw_stats.macb;
2029 
2030         if (macb_is_gem(bp))
2031                 return gem_get_stats(bp);
2032 
2033         /* read stats from hardware */
2034         macb_update_stats(bp);
2035 
2036         /* Convert HW stats into netdevice stats */
2037         nstat->rx_errors = (hwstat->rx_fcs_errors +
2038                             hwstat->rx_align_errors +
2039                             hwstat->rx_resource_errors +
2040                             hwstat->rx_overruns +
2041                             hwstat->rx_oversize_pkts +
2042                             hwstat->rx_jabbers +
2043                             hwstat->rx_undersize_pkts +
2044                             hwstat->rx_length_mismatch);
2045         nstat->tx_errors = (hwstat->tx_late_cols +
2046                             hwstat->tx_excessive_cols +
2047                             hwstat->tx_underruns +
2048                             hwstat->tx_carrier_errors +
2049                             hwstat->sqe_test_errors);
2050         nstat->collisions = (hwstat->tx_single_cols +
2051                              hwstat->tx_multiple_cols +
2052                              hwstat->tx_excessive_cols);
2053         nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2054                                    hwstat->rx_jabbers +
2055                                    hwstat->rx_undersize_pkts +
2056                                    hwstat->rx_length_mismatch);
2057         nstat->rx_over_errors = hwstat->rx_resource_errors +
2058                                    hwstat->rx_overruns;
2059         nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2060         nstat->rx_frame_errors = hwstat->rx_align_errors;
2061         nstat->rx_fifo_errors = hwstat->rx_overruns;
2062         /* XXX: What does "missed" mean? */
2063         nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2064         nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2065         nstat->tx_fifo_errors = hwstat->tx_underruns;
2066         /* Don't know about heartbeat or window errors... */
2067 
2068         return nstat;
2069 }
2070 
2071 static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2072 {
2073         struct macb *bp = netdev_priv(dev);
2074         struct phy_device *phydev = bp->phy_dev;
2075 
2076         if (!phydev)
2077                 return -ENODEV;
2078 
2079         return phy_ethtool_gset(phydev, cmd);
2080 }
2081 
2082 static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2083 {
2084         struct macb *bp = netdev_priv(dev);
2085         struct phy_device *phydev = bp->phy_dev;
2086 
2087         if (!phydev)
2088                 return -ENODEV;
2089 
2090         return phy_ethtool_sset(phydev, cmd);
2091 }
2092 
2093 static int macb_get_regs_len(struct net_device *netdev)
2094 {
2095         return MACB_GREGS_NBR * sizeof(u32);
2096 }
2097 
2098 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2099                           void *p)
2100 {
2101         struct macb *bp = netdev_priv(dev);
2102         unsigned int tail, head;
2103         u32 *regs_buff = p;
2104 
2105         regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2106                         | MACB_GREGS_VERSION;
2107 
2108         tail = macb_tx_ring_wrap(bp->queues[0].tx_tail);
2109         head = macb_tx_ring_wrap(bp->queues[0].tx_head);
2110 
2111         regs_buff[0]  = macb_readl(bp, NCR);
2112         regs_buff[1]  = macb_or_gem_readl(bp, NCFGR);
2113         regs_buff[2]  = macb_readl(bp, NSR);
2114         regs_buff[3]  = macb_readl(bp, TSR);
2115         regs_buff[4]  = macb_readl(bp, RBQP);
2116         regs_buff[5]  = macb_readl(bp, TBQP);
2117         regs_buff[6]  = macb_readl(bp, RSR);
2118         regs_buff[7]  = macb_readl(bp, IMR);
2119 
2120         regs_buff[8]  = tail;
2121         regs_buff[9]  = head;
2122         regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2123         regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
2124 
2125         regs_buff[12] = macb_or_gem_readl(bp, USRIO);
2126         if (macb_is_gem(bp)) {
2127                 regs_buff[13] = gem_readl(bp, DMACFG);
2128         }
2129 }
2130 
2131 static const struct ethtool_ops macb_ethtool_ops = {
2132         .get_settings           = macb_get_settings,
2133         .set_settings           = macb_set_settings,
2134         .get_regs_len           = macb_get_regs_len,
2135         .get_regs               = macb_get_regs,
2136         .get_link               = ethtool_op_get_link,
2137         .get_ts_info            = ethtool_op_get_ts_info,
2138 };
2139 
2140 static const struct ethtool_ops gem_ethtool_ops = {
2141         .get_settings           = macb_get_settings,
2142         .set_settings           = macb_set_settings,
2143         .get_regs_len           = macb_get_regs_len,
2144         .get_regs               = macb_get_regs,
2145         .get_link               = ethtool_op_get_link,
2146         .get_ts_info            = ethtool_op_get_ts_info,
2147         .get_ethtool_stats      = gem_get_ethtool_stats,
2148         .get_strings            = gem_get_ethtool_strings,
2149         .get_sset_count         = gem_get_sset_count,
2150 };
2151 
2152 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2153 {
2154         struct macb *bp = netdev_priv(dev);
2155         struct phy_device *phydev = bp->phy_dev;
2156 
2157         if (!netif_running(dev))
2158                 return -EINVAL;
2159 
2160         if (!phydev)
2161                 return -ENODEV;
2162 
2163         return phy_mii_ioctl(phydev, rq, cmd);
2164 }
2165 
2166 static int macb_set_features(struct net_device *netdev,
2167                              netdev_features_t features)
2168 {
2169         struct macb *bp = netdev_priv(netdev);
2170         netdev_features_t changed = features ^ netdev->features;
2171 
2172         /* TX checksum offload */
2173         if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
2174                 u32 dmacfg;
2175 
2176                 dmacfg = gem_readl(bp, DMACFG);
2177                 if (features & NETIF_F_HW_CSUM)
2178                         dmacfg |= GEM_BIT(TXCOEN);
2179                 else
2180                         dmacfg &= ~GEM_BIT(TXCOEN);
2181                 gem_writel(bp, DMACFG, dmacfg);
2182         }
2183 
2184         /* RX checksum offload */
2185         if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
2186                 u32 netcfg;
2187 
2188                 netcfg = gem_readl(bp, NCFGR);
2189                 if (features & NETIF_F_RXCSUM &&
2190                     !(netdev->flags & IFF_PROMISC))
2191                         netcfg |= GEM_BIT(RXCOEN);
2192                 else
2193                         netcfg &= ~GEM_BIT(RXCOEN);
2194                 gem_writel(bp, NCFGR, netcfg);
2195         }
2196 
2197         return 0;
2198 }
2199 
2200 static const struct net_device_ops macb_netdev_ops = {
2201         .ndo_open               = macb_open,
2202         .ndo_stop               = macb_close,
2203         .ndo_start_xmit         = macb_start_xmit,
2204         .ndo_set_rx_mode        = macb_set_rx_mode,
2205         .ndo_get_stats          = macb_get_stats,
2206         .ndo_do_ioctl           = macb_ioctl,
2207         .ndo_validate_addr      = eth_validate_addr,
2208         .ndo_change_mtu         = macb_change_mtu,
2209         .ndo_set_mac_address    = eth_mac_addr,
2210 #ifdef CONFIG_NET_POLL_CONTROLLER
2211         .ndo_poll_controller    = macb_poll_controller,
2212 #endif
2213         .ndo_set_features       = macb_set_features,
2214 };
2215 
2216 /*
2217  * Configure peripheral capabilities according to device tree
2218  * and integration options used
2219  */
2220 static void macb_configure_caps(struct macb *bp, const struct macb_config *dt_conf)
2221 {
2222         u32 dcfg;
2223 
2224         if (dt_conf)
2225                 bp->caps = dt_conf->caps;
2226 
2227         if (hw_is_gem(bp->regs, bp->native_io)) {
2228                 bp->caps |= MACB_CAPS_MACB_IS_GEM;
2229 
2230                 dcfg = gem_readl(bp, DCFG1);
2231                 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
2232                         bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
2233                 dcfg = gem_readl(bp, DCFG2);
2234                 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
2235                         bp->caps |= MACB_CAPS_FIFO_MODE;
2236         }
2237 
2238         dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
2239 }
2240 
2241 static void macb_probe_queues(void __iomem *mem,
2242                               bool native_io,
2243                               unsigned int *queue_mask,
2244                               unsigned int *num_queues)
2245 {
2246         unsigned int hw_q;
2247 
2248         *queue_mask = 0x1;
2249         *num_queues = 1;
2250 
2251         /* is it macb or gem ?
2252          *
2253          * We need to read directly from the hardware here because
2254          * we are early in the probe process and don't have the
2255          * MACB_CAPS_MACB_IS_GEM flag positioned
2256          */
2257         if (!hw_is_gem(mem, native_io))
2258                 return;
2259 
2260         /* bit 0 is never set but queue 0 always exists */
2261         *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
2262 
2263         *queue_mask |= 0x1;
2264 
2265         for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
2266                 if (*queue_mask & (1 << hw_q))
2267                         (*num_queues)++;
2268 }
2269 
2270 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
2271                          struct clk **hclk, struct clk **tx_clk)
2272 {
2273         int err;
2274 
2275         *pclk = devm_clk_get(&pdev->dev, "pclk");
2276         if (IS_ERR(*pclk)) {
2277                 err = PTR_ERR(*pclk);
2278                 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
2279                 return err;
2280         }
2281 
2282         *hclk = devm_clk_get(&pdev->dev, "hclk");
2283         if (IS_ERR(*hclk)) {
2284                 err = PTR_ERR(*hclk);
2285                 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
2286                 return err;
2287         }
2288 
2289         *tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
2290         if (IS_ERR(*tx_clk))
2291                 *tx_clk = NULL;
2292 
2293         err = clk_prepare_enable(*pclk);
2294         if (err) {
2295                 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
2296                 return err;
2297         }
2298 
2299         err = clk_prepare_enable(*hclk);
2300         if (err) {
2301                 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
2302                 goto err_disable_pclk;
2303         }
2304 
2305         err = clk_prepare_enable(*tx_clk);
2306         if (err) {
2307                 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
2308                 goto err_disable_hclk;
2309         }
2310 
2311         return 0;
2312 
2313 err_disable_hclk:
2314         clk_disable_unprepare(*hclk);
2315 
2316 err_disable_pclk:
2317         clk_disable_unprepare(*pclk);
2318 
2319         return err;
2320 }
2321 
2322 static int macb_init(struct platform_device *pdev)
2323 {
2324         struct net_device *dev = platform_get_drvdata(pdev);
2325         unsigned int hw_q, q;
2326         struct macb *bp = netdev_priv(dev);
2327         struct macb_queue *queue;
2328         int err;
2329         u32 val;
2330 
2331         /* set the queue register mapping once for all: queue0 has a special
2332          * register mapping but we don't want to test the queue index then
2333          * compute the corresponding register offset at run time.
2334          */
2335         for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
2336                 if (!(bp->queue_mask & (1 << hw_q)))
2337                         continue;
2338 
2339                 queue = &bp->queues[q];
2340                 queue->bp = bp;
2341                 if (hw_q) {
2342                         queue->ISR  = GEM_ISR(hw_q - 1);
2343                         queue->IER  = GEM_IER(hw_q - 1);
2344                         queue->IDR  = GEM_IDR(hw_q - 1);
2345                         queue->IMR  = GEM_IMR(hw_q - 1);
2346                         queue->TBQP = GEM_TBQP(hw_q - 1);
2347                 } else {
2348                         /* queue0 uses legacy registers */
2349                         queue->ISR  = MACB_ISR;
2350                         queue->IER  = MACB_IER;
2351                         queue->IDR  = MACB_IDR;
2352                         queue->IMR  = MACB_IMR;
2353                         queue->TBQP = MACB_TBQP;
2354                 }
2355 
2356                 /* get irq: here we use the linux queue index, not the hardware
2357                  * queue index. the queue irq definitions in the device tree
2358                  * must remove the optional gaps that could exist in the
2359                  * hardware queue mask.
2360                  */
2361                 queue->irq = platform_get_irq(pdev, q);
2362                 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
2363                                        IRQF_SHARED, dev->name, queue);
2364                 if (err) {
2365                         dev_err(&pdev->dev,
2366                                 "Unable to request IRQ %d (error %d)\n",
2367                                 queue->irq, err);
2368                         return err;
2369                 }
2370 
2371                 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
2372                 q++;
2373         }
2374 
2375         dev->netdev_ops = &macb_netdev_ops;
2376         netif_napi_add(dev, &bp->napi, macb_poll, 64);
2377 
2378         /* setup appropriated routines according to adapter type */
2379         if (macb_is_gem(bp)) {
2380                 bp->max_tx_length = GEM_MAX_TX_LEN;
2381                 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
2382                 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
2383                 bp->macbgem_ops.mog_init_rings = gem_init_rings;
2384                 bp->macbgem_ops.mog_rx = gem_rx;
2385                 dev->ethtool_ops = &gem_ethtool_ops;
2386         } else {
2387                 bp->max_tx_length = MACB_MAX_TX_LEN;
2388                 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
2389                 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
2390                 bp->macbgem_ops.mog_init_rings = macb_init_rings;
2391                 bp->macbgem_ops.mog_rx = macb_rx;
2392                 dev->ethtool_ops = &macb_ethtool_ops;
2393         }
2394 
2395         /* Set features */
2396         dev->hw_features = NETIF_F_SG;
2397         /* Checksum offload is only available on gem with packet buffer */
2398         if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
2399                 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
2400         if (bp->caps & MACB_CAPS_SG_DISABLED)
2401                 dev->hw_features &= ~NETIF_F_SG;
2402         dev->features = dev->hw_features;
2403 
2404         val = 0;
2405         if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
2406                 val = GEM_BIT(RGMII);
2407         else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
2408                  (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
2409                 val = MACB_BIT(RMII);
2410         else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
2411                 val = MACB_BIT(MII);
2412 
2413         if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
2414                 val |= MACB_BIT(CLKEN);
2415 
2416         macb_or_gem_writel(bp, USRIO, val);
2417 
2418         /* Set MII management clock divider */
2419         val = macb_mdc_clk_div(bp);
2420         val |= macb_dbw(bp);
2421         if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
2422                 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
2423         macb_writel(bp, NCFGR, val);
2424 
2425         return 0;
2426 }
2427 
2428 #if defined(CONFIG_OF)
2429 /* 1518 rounded up */
2430 #define AT91ETHER_MAX_RBUFF_SZ  0x600
2431 /* max number of receive buffers */
2432 #define AT91ETHER_MAX_RX_DESCR  9
2433 
2434 /* Initialize and start the Receiver and Transmit subsystems */
2435 static int at91ether_start(struct net_device *dev)
2436 {
2437         struct macb *lp = netdev_priv(dev);
2438         dma_addr_t addr;
2439         u32 ctl;
2440         int i;
2441 
2442         lp->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
2443                                          (AT91ETHER_MAX_RX_DESCR *
2444                                           sizeof(struct macb_dma_desc)),
2445                                          &lp->rx_ring_dma, GFP_KERNEL);
2446         if (!lp->rx_ring)
2447                 return -ENOMEM;
2448 
2449         lp->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
2450                                             AT91ETHER_MAX_RX_DESCR *
2451                                             AT91ETHER_MAX_RBUFF_SZ,
2452                                             &lp->rx_buffers_dma, GFP_KERNEL);
2453         if (!lp->rx_buffers) {
2454                 dma_free_coherent(&lp->pdev->dev,
2455                                   AT91ETHER_MAX_RX_DESCR *
2456                                   sizeof(struct macb_dma_desc),
2457                                   lp->rx_ring, lp->rx_ring_dma);
2458                 lp->rx_ring = NULL;
2459                 return -ENOMEM;
2460         }
2461 
2462         addr = lp->rx_buffers_dma;
2463         for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
2464                 lp->rx_ring[i].addr = addr;
2465                 lp->rx_ring[i].ctrl = 0;
2466                 addr += AT91ETHER_MAX_RBUFF_SZ;
2467         }
2468 
2469         /* Set the Wrap bit on the last descriptor */
2470         lp->rx_ring[AT91ETHER_MAX_RX_DESCR - 1].addr |= MACB_BIT(RX_WRAP);
2471 
2472         /* Reset buffer index */
2473         lp->rx_tail = 0;
2474 
2475         /* Program address of descriptor list in Rx Buffer Queue register */
2476         macb_writel(lp, RBQP, lp->rx_ring_dma);
2477 
2478         /* Enable Receive and Transmit */
2479         ctl = macb_readl(lp, NCR);
2480         macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
2481 
2482         return 0;
2483 }
2484 
2485 /* Open the ethernet interface */
2486 static int at91ether_open(struct net_device *dev)
2487 {
2488         struct macb *lp = netdev_priv(dev);
2489         u32 ctl;
2490         int ret;
2491 
2492         /* Clear internal statistics */
2493         ctl = macb_readl(lp, NCR);
2494         macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
2495 
2496         macb_set_hwaddr(lp);
2497 
2498         ret = at91ether_start(dev);
2499         if (ret)
2500                 return ret;
2501 
2502         /* Enable MAC interrupts */
2503         macb_writel(lp, IER, MACB_BIT(RCOMP)    |
2504                              MACB_BIT(RXUBR)    |
2505                              MACB_BIT(ISR_TUND) |
2506                              MACB_BIT(ISR_RLE)  |
2507                              MACB_BIT(TCOMP)    |
2508                              MACB_BIT(ISR_ROVR) |
2509                              MACB_BIT(HRESP));
2510 
2511         /* schedule a link state check */
2512         phy_start(lp->phy_dev);
2513 
2514         netif_start_queue(dev);
2515 
2516         return 0;
2517 }
2518 
2519 /* Close the interface */
2520 static int at91ether_close(struct net_device *dev)
2521 {
2522         struct macb *lp = netdev_priv(dev);
2523         u32 ctl;
2524 
2525         /* Disable Receiver and Transmitter */
2526         ctl = macb_readl(lp, NCR);
2527         macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
2528 
2529         /* Disable MAC interrupts */
2530         macb_writel(lp, IDR, MACB_BIT(RCOMP)    |
2531                              MACB_BIT(RXUBR)    |
2532                              MACB_BIT(ISR_TUND) |
2533                              MACB_BIT(ISR_RLE)  |
2534                              MACB_BIT(TCOMP)    |
2535                              MACB_BIT(ISR_ROVR) |
2536                              MACB_BIT(HRESP));
2537 
2538         netif_stop_queue(dev);
2539 
2540         dma_free_coherent(&lp->pdev->dev,
2541                           AT91ETHER_MAX_RX_DESCR *
2542                           sizeof(struct macb_dma_desc),
2543                           lp->rx_ring, lp->rx_ring_dma);
2544         lp->rx_ring = NULL;
2545 
2546         dma_free_coherent(&lp->pdev->dev,
2547                           AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
2548                           lp->rx_buffers, lp->rx_buffers_dma);
2549         lp->rx_buffers = NULL;
2550 
2551         return 0;
2552 }
2553 
2554 /* Transmit packet */
2555 static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
2556 {
2557         struct macb *lp = netdev_priv(dev);
2558 
2559         if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
2560                 netif_stop_queue(dev);
2561 
2562                 /* Store packet information (to free when Tx completed) */
2563                 lp->skb = skb;
2564                 lp->skb_length = skb->len;
2565                 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len,
2566                                                         DMA_TO_DEVICE);
2567 
2568                 /* Set address of the data in the Transmit Address register */
2569                 macb_writel(lp, TAR, lp->skb_physaddr);
2570                 /* Set length of the packet in the Transmit Control register */
2571                 macb_writel(lp, TCR, skb->len);
2572 
2573         } else {
2574                 netdev_err(dev, "%s called, but device is busy!\n", __func__);
2575                 return NETDEV_TX_BUSY;
2576         }
2577 
2578         return NETDEV_TX_OK;
2579 }
2580 
2581 /* Extract received frame from buffer descriptors and sent to upper layers.
2582  * (Called from interrupt context)
2583  */
2584 static void at91ether_rx(struct net_device *dev)
2585 {
2586         struct macb *lp = netdev_priv(dev);
2587         unsigned char *p_recv;
2588         struct sk_buff *skb;
2589         unsigned int pktlen;
2590 
2591         while (lp->rx_ring[lp->rx_tail].addr & MACB_BIT(RX_USED)) {
2592                 p_recv = lp->rx_buffers + lp->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
2593                 pktlen = MACB_BF(RX_FRMLEN, lp->rx_ring[lp->rx_tail].ctrl);
2594                 skb = netdev_alloc_skb(dev, pktlen + 2);
2595                 if (skb) {
2596                         skb_reserve(skb, 2);
2597                         memcpy(skb_put(skb, pktlen), p_recv, pktlen);
2598 
2599                         skb->protocol = eth_type_trans(skb, dev);
2600                         lp->stats.rx_packets++;
2601                         lp->stats.rx_bytes += pktlen;
2602                         netif_rx(skb);
2603                 } else {
2604                         lp->stats.rx_dropped++;
2605                 }
2606 
2607                 if (lp->rx_ring[lp->rx_tail].ctrl & MACB_BIT(RX_MHASH_MATCH))
2608                         lp->stats.multicast++;
2609 
2610                 /* reset ownership bit */
2611                 lp->rx_ring[lp->rx_tail].addr &= ~MACB_BIT(RX_USED);
2612 
2613                 /* wrap after last buffer */
2614                 if (lp->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
2615                         lp->rx_tail = 0;
2616                 else
2617                         lp->rx_tail++;
2618         }
2619 }
2620 
2621 /* MAC interrupt handler */
2622 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
2623 {
2624         struct net_device *dev = dev_id;
2625         struct macb *lp = netdev_priv(dev);
2626         u32 intstatus, ctl;
2627 
2628         /* MAC Interrupt Status register indicates what interrupts are pending.
2629          * It is automatically cleared once read.
2630          */
2631         intstatus = macb_readl(lp, ISR);
2632 
2633         /* Receive complete */
2634         if (intstatus & MACB_BIT(RCOMP))
2635                 at91ether_rx(dev);
2636 
2637         /* Transmit complete */
2638         if (intstatus & MACB_BIT(TCOMP)) {
2639                 /* The TCOM bit is set even if the transmission failed */
2640                 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
2641                         lp->stats.tx_errors++;
2642 
2643                 if (lp->skb) {
2644                         dev_kfree_skb_irq(lp->skb);
2645                         lp->skb = NULL;
2646                         dma_unmap_single(NULL, lp->skb_physaddr,
2647                                          lp->skb_length, DMA_TO_DEVICE);
2648                         lp->stats.tx_packets++;
2649                         lp->stats.tx_bytes += lp->skb_length;
2650                 }
2651                 netif_wake_queue(dev);
2652         }
2653 
2654         /* Work-around for EMAC Errata section 41.3.1 */
2655         if (intstatus & MACB_BIT(RXUBR)) {
2656                 ctl = macb_readl(lp, NCR);
2657                 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
2658                 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
2659         }
2660 
2661         if (intstatus & MACB_BIT(ISR_ROVR))
2662                 netdev_err(dev, "ROVR error\n");
2663 
2664         return IRQ_HANDLED;
2665 }
2666 
2667 #ifdef CONFIG_NET_POLL_CONTROLLER
2668 static void at91ether_poll_controller(struct net_device *dev)
2669 {
2670         unsigned long flags;
2671 
2672         local_irq_save(flags);
2673         at91ether_interrupt(dev->irq, dev);
2674         local_irq_restore(flags);
2675 }
2676 #endif
2677 
2678 static const struct net_device_ops at91ether_netdev_ops = {
2679         .ndo_open               = at91ether_open,
2680         .ndo_stop               = at91ether_close,
2681         .ndo_start_xmit         = at91ether_start_xmit,
2682         .ndo_get_stats          = macb_get_stats,
2683         .ndo_set_rx_mode        = macb_set_rx_mode,
2684         .ndo_set_mac_address    = eth_mac_addr,
2685         .ndo_do_ioctl           = macb_ioctl,
2686         .ndo_validate_addr      = eth_validate_addr,
2687         .ndo_change_mtu         = eth_change_mtu,
2688 #ifdef CONFIG_NET_POLL_CONTROLLER
2689         .ndo_poll_controller    = at91ether_poll_controller,
2690 #endif
2691 };
2692 
2693 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
2694                               struct clk **hclk, struct clk **tx_clk)
2695 {
2696         int err;
2697 
2698         *hclk = NULL;
2699         *tx_clk = NULL;
2700 
2701         *pclk = devm_clk_get(&pdev->dev, "ether_clk");
2702         if (IS_ERR(*pclk))
2703                 return PTR_ERR(*pclk);
2704 
2705         err = clk_prepare_enable(*pclk);
2706         if (err) {
2707                 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
2708                 return err;
2709         }
2710 
2711         return 0;
2712 }
2713 
2714 static int at91ether_init(struct platform_device *pdev)
2715 {
2716         struct net_device *dev = platform_get_drvdata(pdev);
2717         struct macb *bp = netdev_priv(dev);
2718         int err;
2719         u32 reg;
2720 
2721         dev->netdev_ops = &at91ether_netdev_ops;
2722         dev->ethtool_ops = &macb_ethtool_ops;
2723 
2724         err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
2725                                0, dev->name, dev);
2726         if (err)
2727                 return err;
2728 
2729         macb_writel(bp, NCR, 0);
2730 
2731         reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
2732         if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
2733                 reg |= MACB_BIT(RM9200_RMII);
2734 
2735         macb_writel(bp, NCFGR, reg);
2736 
2737         return 0;
2738 }
2739 
2740 static const struct macb_config at91sam9260_config = {
2741         .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII,
2742         .clk_init = macb_clk_init,
2743         .init = macb_init,
2744 };
2745 
2746 static const struct macb_config pc302gem_config = {
2747         .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
2748         .dma_burst_length = 16,
2749         .clk_init = macb_clk_init,
2750         .init = macb_init,
2751 };
2752 
2753 static const struct macb_config sama5d2_config = {
2754         .caps = 0,
2755         .dma_burst_length = 16,
2756         .clk_init = macb_clk_init,
2757         .init = macb_init,
2758 };
2759 
2760 static const struct macb_config sama5d3_config = {
2761         .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
2762         .dma_burst_length = 16,
2763         .clk_init = macb_clk_init,
2764         .init = macb_init,
2765 };
2766 
2767 static const struct macb_config sama5d4_config = {
2768         .caps = 0,
2769         .dma_burst_length = 4,
2770         .clk_init = macb_clk_init,
2771         .init = macb_init,
2772 };
2773 
2774 static const struct macb_config emac_config = {
2775         .clk_init = at91ether_clk_init,
2776         .init = at91ether_init,
2777 };
2778 
2779 
2780 static const struct macb_config zynqmp_config = {
2781         .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO,
2782         .dma_burst_length = 16,
2783         .clk_init = macb_clk_init,
2784         .init = macb_init,
2785         .jumbo_max_len = 10240,
2786 };
2787 
2788 static const struct macb_config zynq_config = {
2789         .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF,
2790         .dma_burst_length = 16,
2791         .clk_init = macb_clk_init,
2792         .init = macb_init,
2793 };
2794 
2795 static const struct of_device_id macb_dt_ids[] = {
2796         { .compatible = "cdns,at32ap7000-macb" },
2797         { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
2798         { .compatible = "cdns,macb" },
2799         { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
2800         { .compatible = "cdns,gem", .data = &pc302gem_config },
2801         { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
2802         { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
2803         { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
2804         { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
2805         { .compatible = "cdns,emac", .data = &emac_config },
2806         { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
2807         { .compatible = "cdns,zynq-gem", .data = &zynq_config },
2808         { /* sentinel */ }
2809 };
2810 MODULE_DEVICE_TABLE(of, macb_dt_ids);
2811 #endif /* CONFIG_OF */
2812 
2813 static int macb_probe(struct platform_device *pdev)
2814 {
2815         int (*clk_init)(struct platform_device *, struct clk **,
2816                         struct clk **, struct clk **)
2817                                               = macb_clk_init;
2818         int (*init)(struct platform_device *) = macb_init;
2819         struct device_node *np = pdev->dev.of_node;
2820         const struct macb_config *macb_config = NULL;
2821         struct clk *pclk, *hclk, *tx_clk;
2822         unsigned int queue_mask, num_queues;
2823         struct macb_platform_data *pdata;
2824         bool native_io;
2825         struct phy_device *phydev;
2826         struct net_device *dev;
2827         struct resource *regs;
2828         void __iomem *mem;
2829         const char *mac;
2830         struct macb *bp;
2831         int err;
2832 
2833         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2834         mem = devm_ioremap_resource(&pdev->dev, regs);
2835         if (IS_ERR(mem))
2836                 return PTR_ERR(mem);
2837 
2838         if (np) {
2839                 const struct of_device_id *match;
2840 
2841                 match = of_match_node(macb_dt_ids, np);
2842                 if (match && match->data) {
2843                         macb_config = match->data;
2844                         clk_init = macb_config->clk_init;
2845                         init = macb_config->init;
2846                 }
2847         }
2848 
2849         err = clk_init(pdev, &pclk, &hclk, &tx_clk);
2850         if (err)
2851                 return err;
2852 
2853         native_io = hw_is_native_io(mem);
2854 
2855         macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
2856         dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
2857         if (!dev) {
2858                 err = -ENOMEM;
2859                 goto err_disable_clocks;
2860         }
2861 
2862         dev->base_addr = regs->start;
2863 
2864         SET_NETDEV_DEV(dev, &pdev->dev);
2865 
2866         bp = netdev_priv(dev);
2867         bp->pdev = pdev;
2868         bp->dev = dev;
2869         bp->regs = mem;
2870         bp->native_io = native_io;
2871         if (native_io) {
2872                 bp->macb_reg_readl = hw_readl_native;
2873                 bp->macb_reg_writel = hw_writel_native;
2874         } else {
2875                 bp->macb_reg_readl = hw_readl;
2876                 bp->macb_reg_writel = hw_writel;
2877         }
2878         bp->num_queues = num_queues;
2879         bp->queue_mask = queue_mask;
2880         if (macb_config)
2881                 bp->dma_burst_length = macb_config->dma_burst_length;
2882         bp->pclk = pclk;
2883         bp->hclk = hclk;
2884         bp->tx_clk = tx_clk;
2885         if (macb_config)
2886                 bp->jumbo_max_len = macb_config->jumbo_max_len;
2887 
2888         spin_lock_init(&bp->lock);
2889 
2890         /* setup capabilities */
2891         macb_configure_caps(bp, macb_config);
2892 
2893         platform_set_drvdata(pdev, dev);
2894 
2895         dev->irq = platform_get_irq(pdev, 0);
2896         if (dev->irq < 0) {
2897                 err = dev->irq;
2898                 goto err_disable_clocks;
2899         }
2900 
2901         mac = of_get_mac_address(np);
2902         if (mac)
2903                 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
2904         else
2905                 macb_get_hwaddr(bp);
2906 
2907         err = of_get_phy_mode(np);
2908         if (err < 0) {
2909                 pdata = dev_get_platdata(&pdev->dev);
2910                 if (pdata && pdata->is_rmii)
2911                         bp->phy_interface = PHY_INTERFACE_MODE_RMII;
2912                 else
2913                         bp->phy_interface = PHY_INTERFACE_MODE_MII;
2914         } else {
2915                 bp->phy_interface = err;
2916         }
2917 
2918         /* IP specific init */
2919         err = init(pdev);
2920         if (err)
2921                 goto err_out_free_netdev;
2922 
2923         err = register_netdev(dev);
2924         if (err) {
2925                 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
2926                 goto err_out_unregister_netdev;
2927         }
2928 
2929         err = macb_mii_init(bp);
2930         if (err)
2931                 goto err_out_unregister_netdev;
2932 
2933         netif_carrier_off(dev);
2934 
2935         netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
2936                     macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
2937                     dev->base_addr, dev->irq, dev->dev_addr);
2938 
2939         phydev = bp->phy_dev;
2940         netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
2941                     phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
2942 
2943         return 0;
2944 
2945 err_out_unregister_netdev:
2946         unregister_netdev(dev);
2947 
2948 err_out_free_netdev:
2949         free_netdev(dev);
2950 
2951 err_disable_clocks:
2952         clk_disable_unprepare(tx_clk);
2953         clk_disable_unprepare(hclk);
2954         clk_disable_unprepare(pclk);
2955 
2956         return err;
2957 }
2958 
2959 static int macb_remove(struct platform_device *pdev)
2960 {
2961         struct net_device *dev;
2962         struct macb *bp;
2963 
2964         dev = platform_get_drvdata(pdev);
2965 
2966         if (dev) {
2967                 bp = netdev_priv(dev);
2968                 if (bp->phy_dev)
2969                         phy_disconnect(bp->phy_dev);
2970                 mdiobus_unregister(bp->mii_bus);
2971                 kfree(bp->mii_bus->irq);
2972                 mdiobus_free(bp->mii_bus);
2973                 unregister_netdev(dev);
2974                 clk_disable_unprepare(bp->tx_clk);
2975                 clk_disable_unprepare(bp->hclk);
2976                 clk_disable_unprepare(bp->pclk);
2977                 free_netdev(dev);
2978         }
2979 
2980         return 0;
2981 }
2982 
2983 static int __maybe_unused macb_suspend(struct device *dev)
2984 {
2985         struct platform_device *pdev = to_platform_device(dev);
2986         struct net_device *netdev = platform_get_drvdata(pdev);
2987         struct macb *bp = netdev_priv(netdev);
2988 
2989         netif_carrier_off(netdev);
2990         netif_device_detach(netdev);
2991 
2992         clk_disable_unprepare(bp->tx_clk);
2993         clk_disable_unprepare(bp->hclk);
2994         clk_disable_unprepare(bp->pclk);
2995 
2996         return 0;
2997 }
2998 
2999 static int __maybe_unused macb_resume(struct device *dev)
3000 {
3001         struct platform_device *pdev = to_platform_device(dev);
3002         struct net_device *netdev = platform_get_drvdata(pdev);
3003         struct macb *bp = netdev_priv(netdev);
3004 
3005         clk_prepare_enable(bp->pclk);
3006         clk_prepare_enable(bp->hclk);
3007         clk_prepare_enable(bp->tx_clk);
3008 
3009         netif_device_attach(netdev);
3010 
3011         return 0;
3012 }
3013 
3014 static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
3015 
3016 static struct platform_driver macb_driver = {
3017         .probe          = macb_probe,
3018         .remove         = macb_remove,
3019         .driver         = {
3020                 .name           = "macb",
3021                 .of_match_table = of_match_ptr(macb_dt_ids),
3022                 .pm     = &macb_pm_ops,
3023         },
3024 };
3025 
3026 module_platform_driver(macb_driver);
3027 
3028 MODULE_LICENSE("GPL");
3029 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
3030 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
3031 MODULE_ALIAS("platform:macb");
3032 

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