Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/drivers/net/ethernet/broadcom/sb1250-mac.c

  1 /*
  2  * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation
  3  * Copyright (c) 2006, 2007  Maciej W. Rozycki
  4  *
  5  * This program is free software; you can redistribute it and/or
  6  * modify it under the terms of the GNU General Public License
  7  * as published by the Free Software Foundation; either version 2
  8  * of the License, or (at your option) any later version.
  9  *
 10  * This program is distributed in the hope that it will be useful,
 11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  *
 15  * You should have received a copy of the GNU General Public License
 16  * along with this program; if not, see <http://www.gnu.org/licenses/>.
 17  *
 18  *
 19  * This driver is designed for the Broadcom SiByte SOC built-in
 20  * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp.
 21  *
 22  * Updated to the driver model and the PHY abstraction layer
 23  * by Maciej W. Rozycki.
 24  */
 25 
 26 #include <linux/bug.h>
 27 #include <linux/module.h>
 28 #include <linux/kernel.h>
 29 #include <linux/string.h>
 30 #include <linux/timer.h>
 31 #include <linux/errno.h>
 32 #include <linux/ioport.h>
 33 #include <linux/slab.h>
 34 #include <linux/interrupt.h>
 35 #include <linux/netdevice.h>
 36 #include <linux/etherdevice.h>
 37 #include <linux/skbuff.h>
 38 #include <linux/bitops.h>
 39 #include <linux/err.h>
 40 #include <linux/ethtool.h>
 41 #include <linux/mii.h>
 42 #include <linux/phy.h>
 43 #include <linux/platform_device.h>
 44 #include <linux/prefetch.h>
 45 
 46 #include <asm/cache.h>
 47 #include <asm/io.h>
 48 #include <asm/processor.h>      /* Processor type for cache alignment. */
 49 
 50 /* Operational parameters that usually are not changed. */
 51 
 52 #define CONFIG_SBMAC_COALESCE
 53 
 54 /* Time in jiffies before concluding the transmitter is hung. */
 55 #define TX_TIMEOUT  (2*HZ)
 56 
 57 
 58 MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)");
 59 MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver");
 60 
 61 /* A few user-configurable values which may be modified when a driver
 62    module is loaded. */
 63 
 64 /* 1 normal messages, 0 quiet .. 7 verbose. */
 65 static int debug = 1;
 66 module_param(debug, int, S_IRUGO);
 67 MODULE_PARM_DESC(debug, "Debug messages");
 68 
 69 #ifdef CONFIG_SBMAC_COALESCE
 70 static int int_pktcnt_tx = 255;
 71 module_param(int_pktcnt_tx, int, S_IRUGO);
 72 MODULE_PARM_DESC(int_pktcnt_tx, "TX packet count");
 73 
 74 static int int_timeout_tx = 255;
 75 module_param(int_timeout_tx, int, S_IRUGO);
 76 MODULE_PARM_DESC(int_timeout_tx, "TX timeout value");
 77 
 78 static int int_pktcnt_rx = 64;
 79 module_param(int_pktcnt_rx, int, S_IRUGO);
 80 MODULE_PARM_DESC(int_pktcnt_rx, "RX packet count");
 81 
 82 static int int_timeout_rx = 64;
 83 module_param(int_timeout_rx, int, S_IRUGO);
 84 MODULE_PARM_DESC(int_timeout_rx, "RX timeout value");
 85 #endif
 86 
 87 #include <asm/sibyte/board.h>
 88 #include <asm/sibyte/sb1250.h>
 89 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
 90 #include <asm/sibyte/bcm1480_regs.h>
 91 #include <asm/sibyte/bcm1480_int.h>
 92 #define R_MAC_DMA_OODPKTLOST_RX R_MAC_DMA_OODPKTLOST
 93 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
 94 #include <asm/sibyte/sb1250_regs.h>
 95 #include <asm/sibyte/sb1250_int.h>
 96 #else
 97 #error invalid SiByte MAC configuration
 98 #endif
 99 #include <asm/sibyte/sb1250_scd.h>
100 #include <asm/sibyte/sb1250_mac.h>
101 #include <asm/sibyte/sb1250_dma.h>
102 
103 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
104 #define UNIT_INT(n)             (K_BCM1480_INT_MAC_0 + ((n) * 2))
105 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
106 #define UNIT_INT(n)             (K_INT_MAC_0 + (n))
107 #else
108 #error invalid SiByte MAC configuration
109 #endif
110 
111 #ifdef K_INT_PHY
112 #define SBMAC_PHY_INT                   K_INT_PHY
113 #else
114 #define SBMAC_PHY_INT                   PHY_POLL
115 #endif
116 
117 /**********************************************************************
118  *  Simple types
119  ********************************************************************* */
120 
121 enum sbmac_speed {
122         sbmac_speed_none = 0,
123         sbmac_speed_10 = SPEED_10,
124         sbmac_speed_100 = SPEED_100,
125         sbmac_speed_1000 = SPEED_1000,
126 };
127 
128 enum sbmac_duplex {
129         sbmac_duplex_none = -1,
130         sbmac_duplex_half = DUPLEX_HALF,
131         sbmac_duplex_full = DUPLEX_FULL,
132 };
133 
134 enum sbmac_fc {
135         sbmac_fc_none,
136         sbmac_fc_disabled,
137         sbmac_fc_frame,
138         sbmac_fc_collision,
139         sbmac_fc_carrier,
140 };
141 
142 enum sbmac_state {
143         sbmac_state_uninit,
144         sbmac_state_off,
145         sbmac_state_on,
146         sbmac_state_broken,
147 };
148 
149 
150 /**********************************************************************
151  *  Macros
152  ********************************************************************* */
153 
154 
155 #define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \
156                           (d)->sbdma_dscrtable : (d)->f+1)
157 
158 
159 #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
160 
161 #define SBMAC_MAX_TXDESCR       256
162 #define SBMAC_MAX_RXDESCR       256
163 
164 #define ENET_PACKET_SIZE        1518
165 /*#define ENET_PACKET_SIZE      9216 */
166 
167 /**********************************************************************
168  *  DMA Descriptor structure
169  ********************************************************************* */
170 
171 struct sbdmadscr {
172         uint64_t  dscr_a;
173         uint64_t  dscr_b;
174 };
175 
176 /**********************************************************************
177  *  DMA Controller structure
178  ********************************************************************* */
179 
180 struct sbmacdma {
181 
182         /*
183          * This stuff is used to identify the channel and the registers
184          * associated with it.
185          */
186         struct sbmac_softc      *sbdma_eth;     /* back pointer to associated
187                                                    MAC */
188         int                     sbdma_channel;  /* channel number */
189         int                     sbdma_txdir;    /* direction (1=transmit) */
190         int                     sbdma_maxdescr; /* total # of descriptors
191                                                    in ring */
192 #ifdef CONFIG_SBMAC_COALESCE
193         int                     sbdma_int_pktcnt;
194                                                 /* # descriptors rx/tx
195                                                    before interrupt */
196         int                     sbdma_int_timeout;
197                                                 /* # usec rx/tx interrupt */
198 #endif
199         void __iomem            *sbdma_config0; /* DMA config register 0 */
200         void __iomem            *sbdma_config1; /* DMA config register 1 */
201         void __iomem            *sbdma_dscrbase;
202                                                 /* descriptor base address */
203         void __iomem            *sbdma_dscrcnt; /* descriptor count register */
204         void __iomem            *sbdma_curdscr; /* current descriptor
205                                                    address */
206         void __iomem            *sbdma_oodpktlost;
207                                                 /* pkt drop (rx only) */
208 
209         /*
210          * This stuff is for maintenance of the ring
211          */
212         void                    *sbdma_dscrtable_unaligned;
213         struct sbdmadscr        *sbdma_dscrtable;
214                                                 /* base of descriptor table */
215         struct sbdmadscr        *sbdma_dscrtable_end;
216                                                 /* end of descriptor table */
217         struct sk_buff          **sbdma_ctxtable;
218                                                 /* context table, one
219                                                    per descr */
220         dma_addr_t              sbdma_dscrtable_phys;
221                                                 /* and also the phys addr */
222         struct sbdmadscr        *sbdma_addptr;  /* next dscr for sw to add */
223         struct sbdmadscr        *sbdma_remptr;  /* next dscr for sw
224                                                    to remove */
225 };
226 
227 
228 /**********************************************************************
229  *  Ethernet softc structure
230  ********************************************************************* */
231 
232 struct sbmac_softc {
233 
234         /*
235          * Linux-specific things
236          */
237         struct net_device       *sbm_dev;       /* pointer to linux device */
238         struct napi_struct      napi;
239         struct phy_device       *phy_dev;       /* the associated PHY device */
240         struct mii_bus          *mii_bus;       /* the MII bus */
241         int                     phy_irq[PHY_MAX_ADDR];
242         spinlock_t              sbm_lock;       /* spin lock */
243         int                     sbm_devflags;   /* current device flags */
244 
245         /*
246          * Controller-specific things
247          */
248         void __iomem            *sbm_base;      /* MAC's base address */
249         enum sbmac_state        sbm_state;      /* current state */
250 
251         void __iomem            *sbm_macenable; /* MAC Enable Register */
252         void __iomem            *sbm_maccfg;    /* MAC Config Register */
253         void __iomem            *sbm_fifocfg;   /* FIFO Config Register */
254         void __iomem            *sbm_framecfg;  /* Frame Config Register */
255         void __iomem            *sbm_rxfilter;  /* Receive Filter Register */
256         void __iomem            *sbm_isr;       /* Interrupt Status Register */
257         void __iomem            *sbm_imr;       /* Interrupt Mask Register */
258         void __iomem            *sbm_mdio;      /* MDIO Register */
259 
260         enum sbmac_speed        sbm_speed;      /* current speed */
261         enum sbmac_duplex       sbm_duplex;     /* current duplex */
262         enum sbmac_fc           sbm_fc;         /* cur. flow control setting */
263         int                     sbm_pause;      /* current pause setting */
264         int                     sbm_link;       /* current link state */
265 
266         unsigned char           sbm_hwaddr[ETH_ALEN];
267 
268         struct sbmacdma         sbm_txdma;      /* only channel 0 for now */
269         struct sbmacdma         sbm_rxdma;
270         int                     rx_hw_checksum;
271         int                     sbe_idx;
272 };
273 
274 
275 /**********************************************************************
276  *  Externs
277  ********************************************************************* */
278 
279 /**********************************************************************
280  *  Prototypes
281  ********************************************************************* */
282 
283 static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan,
284                           int txrx, int maxdescr);
285 static void sbdma_channel_start(struct sbmacdma *d, int rxtx);
286 static int sbdma_add_rcvbuffer(struct sbmac_softc *sc, struct sbmacdma *d,
287                                struct sk_buff *m);
288 static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *m);
289 static void sbdma_emptyring(struct sbmacdma *d);
290 static void sbdma_fillring(struct sbmac_softc *sc, struct sbmacdma *d);
291 static int sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d,
292                             int work_to_do, int poll);
293 static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d,
294                              int poll);
295 static int sbmac_initctx(struct sbmac_softc *s);
296 static void sbmac_channel_start(struct sbmac_softc *s);
297 static void sbmac_channel_stop(struct sbmac_softc *s);
298 static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *,
299                                                 enum sbmac_state);
300 static void sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff);
301 static uint64_t sbmac_addr2reg(unsigned char *ptr);
302 static irqreturn_t sbmac_intr(int irq, void *dev_instance);
303 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev);
304 static void sbmac_setmulti(struct sbmac_softc *sc);
305 static int sbmac_init(struct platform_device *pldev, long long base);
306 static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed);
307 static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex,
308                             enum sbmac_fc fc);
309 
310 static int sbmac_open(struct net_device *dev);
311 static void sbmac_tx_timeout (struct net_device *dev);
312 static void sbmac_set_rx_mode(struct net_device *dev);
313 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
314 static int sbmac_close(struct net_device *dev);
315 static int sbmac_poll(struct napi_struct *napi, int budget);
316 
317 static void sbmac_mii_poll(struct net_device *dev);
318 static int sbmac_mii_probe(struct net_device *dev);
319 
320 static void sbmac_mii_sync(void __iomem *sbm_mdio);
321 static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data,
322                                int bitcnt);
323 static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx);
324 static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
325                            u16 val);
326 
327 
328 /**********************************************************************
329  *  Globals
330  ********************************************************************* */
331 
332 static char sbmac_string[] = "sb1250-mac";
333 
334 static char sbmac_mdio_string[] = "sb1250-mac-mdio";
335 
336 
337 /**********************************************************************
338  *  MDIO constants
339  ********************************************************************* */
340 
341 #define MII_COMMAND_START       0x01
342 #define MII_COMMAND_READ        0x02
343 #define MII_COMMAND_WRITE       0x01
344 #define MII_COMMAND_ACK         0x02
345 
346 #define M_MAC_MDIO_DIR_OUTPUT   0               /* for clarity */
347 
348 #define ENABLE          1
349 #define DISABLE         0
350 
351 /**********************************************************************
352  *  SBMAC_MII_SYNC(sbm_mdio)
353  *
354  *  Synchronize with the MII - send a pattern of bits to the MII
355  *  that will guarantee that it is ready to accept a command.
356  *
357  *  Input parameters:
358  *         sbm_mdio - address of the MAC's MDIO register
359  *
360  *  Return value:
361  *         nothing
362  ********************************************************************* */
363 
364 static void sbmac_mii_sync(void __iomem *sbm_mdio)
365 {
366         int cnt;
367         uint64_t bits;
368         int mac_mdio_genc;
369 
370         mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
371 
372         bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT;
373 
374         __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
375 
376         for (cnt = 0; cnt < 32; cnt++) {
377                 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio);
378                 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
379         }
380 }
381 
382 /**********************************************************************
383  *  SBMAC_MII_SENDDATA(sbm_mdio, data, bitcnt)
384  *
385  *  Send some bits to the MII.  The bits to be sent are right-
386  *  justified in the 'data' parameter.
387  *
388  *  Input parameters:
389  *         sbm_mdio - address of the MAC's MDIO register
390  *         data     - data to send
391  *         bitcnt   - number of bits to send
392  ********************************************************************* */
393 
394 static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data,
395                                int bitcnt)
396 {
397         int i;
398         uint64_t bits;
399         unsigned int curmask;
400         int mac_mdio_genc;
401 
402         mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
403 
404         bits = M_MAC_MDIO_DIR_OUTPUT;
405         __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
406 
407         curmask = 1 << (bitcnt - 1);
408 
409         for (i = 0; i < bitcnt; i++) {
410                 if (data & curmask)
411                         bits |= M_MAC_MDIO_OUT;
412                 else bits &= ~M_MAC_MDIO_OUT;
413                 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
414                 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio);
415                 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
416                 curmask >>= 1;
417         }
418 }
419 
420 
421 
422 /**********************************************************************
423  *  SBMAC_MII_READ(bus, phyaddr, regidx)
424  *  Read a PHY register.
425  *
426  *  Input parameters:
427  *         bus     - MDIO bus handle
428  *         phyaddr - PHY's address
429  *         regnum  - index of register to read
430  *
431  *  Return value:
432  *         value read, or 0xffff if an error occurred.
433  ********************************************************************* */
434 
435 static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
436 {
437         struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv;
438         void __iomem *sbm_mdio = sc->sbm_mdio;
439         int idx;
440         int error;
441         int regval;
442         int mac_mdio_genc;
443 
444         /*
445          * Synchronize ourselves so that the PHY knows the next
446          * thing coming down is a command
447          */
448         sbmac_mii_sync(sbm_mdio);
449 
450         /*
451          * Send the data to the PHY.  The sequence is
452          * a "start" command (2 bits)
453          * a "read" command (2 bits)
454          * the PHY addr (5 bits)
455          * the register index (5 bits)
456          */
457         sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2);
458         sbmac_mii_senddata(sbm_mdio, MII_COMMAND_READ, 2);
459         sbmac_mii_senddata(sbm_mdio, phyaddr, 5);
460         sbmac_mii_senddata(sbm_mdio, regidx, 5);
461 
462         mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
463 
464         /*
465          * Switch the port around without a clock transition.
466          */
467         __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
468 
469         /*
470          * Send out a clock pulse to signal we want the status
471          */
472         __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
473                      sbm_mdio);
474         __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
475 
476         /*
477          * If an error occurred, the PHY will signal '1' back
478          */
479         error = __raw_readq(sbm_mdio) & M_MAC_MDIO_IN;
480 
481         /*
482          * Issue an 'idle' clock pulse, but keep the direction
483          * the same.
484          */
485         __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
486                      sbm_mdio);
487         __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
488 
489         regval = 0;
490 
491         for (idx = 0; idx < 16; idx++) {
492                 regval <<= 1;
493 
494                 if (error == 0) {
495                         if (__raw_readq(sbm_mdio) & M_MAC_MDIO_IN)
496                                 regval |= 1;
497                 }
498 
499                 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
500                              sbm_mdio);
501                 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
502         }
503 
504         /* Switch back to output */
505         __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio);
506 
507         if (error == 0)
508                 return regval;
509         return 0xffff;
510 }
511 
512 
513 /**********************************************************************
514  *  SBMAC_MII_WRITE(bus, phyaddr, regidx, regval)
515  *
516  *  Write a value to a PHY register.
517  *
518  *  Input parameters:
519  *         bus     - MDIO bus handle
520  *         phyaddr - PHY to use
521  *         regidx  - register within the PHY
522  *         regval  - data to write to register
523  *
524  *  Return value:
525  *         0 for success
526  ********************************************************************* */
527 
528 static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
529                            u16 regval)
530 {
531         struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv;
532         void __iomem *sbm_mdio = sc->sbm_mdio;
533         int mac_mdio_genc;
534 
535         sbmac_mii_sync(sbm_mdio);
536 
537         sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2);
538         sbmac_mii_senddata(sbm_mdio, MII_COMMAND_WRITE, 2);
539         sbmac_mii_senddata(sbm_mdio, phyaddr, 5);
540         sbmac_mii_senddata(sbm_mdio, regidx, 5);
541         sbmac_mii_senddata(sbm_mdio, MII_COMMAND_ACK, 2);
542         sbmac_mii_senddata(sbm_mdio, regval, 16);
543 
544         mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
545 
546         __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio);
547 
548         return 0;
549 }
550 
551 
552 
553 /**********************************************************************
554  *  SBDMA_INITCTX(d,s,chan,txrx,maxdescr)
555  *
556  *  Initialize a DMA channel context.  Since there are potentially
557  *  eight DMA channels per MAC, it's nice to do this in a standard
558  *  way.
559  *
560  *  Input parameters:
561  *         d - struct sbmacdma (DMA channel context)
562  *         s - struct sbmac_softc (pointer to a MAC)
563  *         chan - channel number (0..1 right now)
564  *         txrx - Identifies DMA_TX or DMA_RX for channel direction
565  *      maxdescr - number of descriptors
566  *
567  *  Return value:
568  *         nothing
569  ********************************************************************* */
570 
571 static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan,
572                           int txrx, int maxdescr)
573 {
574 #ifdef CONFIG_SBMAC_COALESCE
575         int int_pktcnt, int_timeout;
576 #endif
577 
578         /*
579          * Save away interesting stuff in the structure
580          */
581 
582         d->sbdma_eth       = s;
583         d->sbdma_channel   = chan;
584         d->sbdma_txdir     = txrx;
585 
586 #if 0
587         /* RMON clearing */
588         s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
589 #endif
590 
591         __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BYTES);
592         __raw_writeq(0, s->sbm_base + R_MAC_RMON_COLLISIONS);
593         __raw_writeq(0, s->sbm_base + R_MAC_RMON_LATE_COL);
594         __raw_writeq(0, s->sbm_base + R_MAC_RMON_EX_COL);
595         __raw_writeq(0, s->sbm_base + R_MAC_RMON_FCS_ERROR);
596         __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_ABORT);
597         __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BAD);
598         __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_GOOD);
599         __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_RUNT);
600         __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_OVERSIZE);
601         __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BYTES);
602         __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_MCAST);
603         __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BCAST);
604         __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BAD);
605         __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_GOOD);
606         __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_RUNT);
607         __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_OVERSIZE);
608         __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_FCS_ERROR);
609         __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_LENGTH_ERROR);
610         __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_CODE_ERROR);
611         __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_ALIGN_ERROR);
612 
613         /*
614          * initialize register pointers
615          */
616 
617         d->sbdma_config0 =
618                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0);
619         d->sbdma_config1 =
620                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1);
621         d->sbdma_dscrbase =
622                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE);
623         d->sbdma_dscrcnt =
624                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT);
625         d->sbdma_curdscr =
626                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR);
627         if (d->sbdma_txdir)
628                 d->sbdma_oodpktlost = NULL;
629         else
630                 d->sbdma_oodpktlost =
631                         s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_OODPKTLOST_RX);
632 
633         /*
634          * Allocate memory for the ring
635          */
636 
637         d->sbdma_maxdescr = maxdescr;
638 
639         d->sbdma_dscrtable_unaligned = kcalloc(d->sbdma_maxdescr + 1,
640                                                sizeof(*d->sbdma_dscrtable),
641                                                GFP_KERNEL);
642 
643         /*
644          * The descriptor table must be aligned to at least 16 bytes or the
645          * MAC will corrupt it.
646          */
647         d->sbdma_dscrtable = (struct sbdmadscr *)
648                              ALIGN((unsigned long)d->sbdma_dscrtable_unaligned,
649                                    sizeof(*d->sbdma_dscrtable));
650 
651         d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr;
652 
653         d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable);
654 
655         /*
656          * And context table
657          */
658 
659         d->sbdma_ctxtable = kcalloc(d->sbdma_maxdescr,
660                                     sizeof(*d->sbdma_ctxtable), GFP_KERNEL);
661 
662 #ifdef CONFIG_SBMAC_COALESCE
663         /*
664          * Setup Rx/Tx DMA coalescing defaults
665          */
666 
667         int_pktcnt = (txrx == DMA_TX) ? int_pktcnt_tx : int_pktcnt_rx;
668         if ( int_pktcnt ) {
669                 d->sbdma_int_pktcnt = int_pktcnt;
670         } else {
671                 d->sbdma_int_pktcnt = 1;
672         }
673 
674         int_timeout = (txrx == DMA_TX) ? int_timeout_tx : int_timeout_rx;
675         if ( int_timeout ) {
676                 d->sbdma_int_timeout = int_timeout;
677         } else {
678                 d->sbdma_int_timeout = 0;
679         }
680 #endif
681 
682 }
683 
684 /**********************************************************************
685  *  SBDMA_CHANNEL_START(d)
686  *
687  *  Initialize the hardware registers for a DMA channel.
688  *
689  *  Input parameters:
690  *         d - DMA channel to init (context must be previously init'd
691  *         rxtx - DMA_RX or DMA_TX depending on what type of channel
692  *
693  *  Return value:
694  *         nothing
695  ********************************************************************* */
696 
697 static void sbdma_channel_start(struct sbmacdma *d, int rxtx)
698 {
699         /*
700          * Turn on the DMA channel
701          */
702 
703 #ifdef CONFIG_SBMAC_COALESCE
704         __raw_writeq(V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) |
705                        0, d->sbdma_config1);
706         __raw_writeq(M_DMA_EOP_INT_EN |
707                        V_DMA_RINGSZ(d->sbdma_maxdescr) |
708                        V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) |
709                        0, d->sbdma_config0);
710 #else
711         __raw_writeq(0, d->sbdma_config1);
712         __raw_writeq(V_DMA_RINGSZ(d->sbdma_maxdescr) |
713                        0, d->sbdma_config0);
714 #endif
715 
716         __raw_writeq(d->sbdma_dscrtable_phys, d->sbdma_dscrbase);
717 
718         /*
719          * Initialize ring pointers
720          */
721 
722         d->sbdma_addptr = d->sbdma_dscrtable;
723         d->sbdma_remptr = d->sbdma_dscrtable;
724 }
725 
726 /**********************************************************************
727  *  SBDMA_CHANNEL_STOP(d)
728  *
729  *  Initialize the hardware registers for a DMA channel.
730  *
731  *  Input parameters:
732  *         d - DMA channel to init (context must be previously init'd
733  *
734  *  Return value:
735  *         nothing
736  ********************************************************************* */
737 
738 static void sbdma_channel_stop(struct sbmacdma *d)
739 {
740         /*
741          * Turn off the DMA channel
742          */
743 
744         __raw_writeq(0, d->sbdma_config1);
745 
746         __raw_writeq(0, d->sbdma_dscrbase);
747 
748         __raw_writeq(0, d->sbdma_config0);
749 
750         /*
751          * Zero ring pointers
752          */
753 
754         d->sbdma_addptr = NULL;
755         d->sbdma_remptr = NULL;
756 }
757 
758 static inline void sbdma_align_skb(struct sk_buff *skb,
759                                    unsigned int power2, unsigned int offset)
760 {
761         unsigned char *addr = skb->data;
762         unsigned char *newaddr = PTR_ALIGN(addr, power2);
763 
764         skb_reserve(skb, newaddr - addr + offset);
765 }
766 
767 
768 /**********************************************************************
769  *  SBDMA_ADD_RCVBUFFER(d,sb)
770  *
771  *  Add a buffer to the specified DMA channel.   For receive channels,
772  *  this queues a buffer for inbound packets.
773  *
774  *  Input parameters:
775  *         sc - softc structure
776  *          d - DMA channel descriptor
777  *         sb - sk_buff to add, or NULL if we should allocate one
778  *
779  *  Return value:
780  *         0 if buffer could not be added (ring is full)
781  *         1 if buffer added successfully
782  ********************************************************************* */
783 
784 
785 static int sbdma_add_rcvbuffer(struct sbmac_softc *sc, struct sbmacdma *d,
786                                struct sk_buff *sb)
787 {
788         struct net_device *dev = sc->sbm_dev;
789         struct sbdmadscr *dsc;
790         struct sbdmadscr *nextdsc;
791         struct sk_buff *sb_new = NULL;
792         int pktsize = ENET_PACKET_SIZE;
793 
794         /* get pointer to our current place in the ring */
795 
796         dsc = d->sbdma_addptr;
797         nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
798 
799         /*
800          * figure out if the ring is full - if the next descriptor
801          * is the same as the one that we're going to remove from
802          * the ring, the ring is full
803          */
804 
805         if (nextdsc == d->sbdma_remptr) {
806                 return -ENOSPC;
807         }
808 
809         /*
810          * Allocate a sk_buff if we don't already have one.
811          * If we do have an sk_buff, reset it so that it's empty.
812          *
813          * Note: sk_buffs don't seem to be guaranteed to have any sort
814          * of alignment when they are allocated.  Therefore, allocate enough
815          * extra space to make sure that:
816          *
817          *    1. the data does not start in the middle of a cache line.
818          *    2. The data does not end in the middle of a cache line
819          *    3. The buffer can be aligned such that the IP addresses are
820          *       naturally aligned.
821          *
822          *  Remember, the SOCs MAC writes whole cache lines at a time,
823          *  without reading the old contents first.  So, if the sk_buff's
824          *  data portion starts in the middle of a cache line, the SOC
825          *  DMA will trash the beginning (and ending) portions.
826          */
827 
828         if (sb == NULL) {
829                 sb_new = netdev_alloc_skb(dev, ENET_PACKET_SIZE +
830                                                SMP_CACHE_BYTES * 2 +
831                                                NET_IP_ALIGN);
832                 if (sb_new == NULL)
833                         return -ENOBUFS;
834 
835                 sbdma_align_skb(sb_new, SMP_CACHE_BYTES, NET_IP_ALIGN);
836         }
837         else {
838                 sb_new = sb;
839                 /*
840                  * nothing special to reinit buffer, it's already aligned
841                  * and sb->data already points to a good place.
842                  */
843         }
844 
845         /*
846          * fill in the descriptor
847          */
848 
849 #ifdef CONFIG_SBMAC_COALESCE
850         /*
851          * Do not interrupt per DMA transfer.
852          */
853         dsc->dscr_a = virt_to_phys(sb_new->data) |
854                 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize + NET_IP_ALIGN)) | 0;
855 #else
856         dsc->dscr_a = virt_to_phys(sb_new->data) |
857                 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize + NET_IP_ALIGN)) |
858                 M_DMA_DSCRA_INTERRUPT;
859 #endif
860 
861         /* receiving: no options */
862         dsc->dscr_b = 0;
863 
864         /*
865          * fill in the context
866          */
867 
868         d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new;
869 
870         /*
871          * point at next packet
872          */
873 
874         d->sbdma_addptr = nextdsc;
875 
876         /*
877          * Give the buffer to the DMA engine.
878          */
879 
880         __raw_writeq(1, d->sbdma_dscrcnt);
881 
882         return 0;                                       /* we did it */
883 }
884 
885 /**********************************************************************
886  *  SBDMA_ADD_TXBUFFER(d,sb)
887  *
888  *  Add a transmit buffer to the specified DMA channel, causing a
889  *  transmit to start.
890  *
891  *  Input parameters:
892  *         d - DMA channel descriptor
893  *         sb - sk_buff to add
894  *
895  *  Return value:
896  *         0 transmit queued successfully
897  *         otherwise error code
898  ********************************************************************* */
899 
900 
901 static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *sb)
902 {
903         struct sbdmadscr *dsc;
904         struct sbdmadscr *nextdsc;
905         uint64_t phys;
906         uint64_t ncb;
907         int length;
908 
909         /* get pointer to our current place in the ring */
910 
911         dsc = d->sbdma_addptr;
912         nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
913 
914         /*
915          * figure out if the ring is full - if the next descriptor
916          * is the same as the one that we're going to remove from
917          * the ring, the ring is full
918          */
919 
920         if (nextdsc == d->sbdma_remptr) {
921                 return -ENOSPC;
922         }
923 
924         /*
925          * Under Linux, it's not necessary to copy/coalesce buffers
926          * like it is on NetBSD.  We think they're all contiguous,
927          * but that may not be true for GBE.
928          */
929 
930         length = sb->len;
931 
932         /*
933          * fill in the descriptor.  Note that the number of cache
934          * blocks in the descriptor is the number of blocks
935          * *spanned*, so we need to add in the offset (if any)
936          * while doing the calculation.
937          */
938 
939         phys = virt_to_phys(sb->data);
940         ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1)));
941 
942         dsc->dscr_a = phys |
943                 V_DMA_DSCRA_A_SIZE(ncb) |
944 #ifndef CONFIG_SBMAC_COALESCE
945                 M_DMA_DSCRA_INTERRUPT |
946 #endif
947                 M_DMA_ETHTX_SOP;
948 
949         /* transmitting: set outbound options and length */
950 
951         dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) |
952                 V_DMA_DSCRB_PKT_SIZE(length);
953 
954         /*
955          * fill in the context
956          */
957 
958         d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb;
959 
960         /*
961          * point at next packet
962          */
963 
964         d->sbdma_addptr = nextdsc;
965 
966         /*
967          * Give the buffer to the DMA engine.
968          */
969 
970         __raw_writeq(1, d->sbdma_dscrcnt);
971 
972         return 0;                                       /* we did it */
973 }
974 
975 
976 
977 
978 /**********************************************************************
979  *  SBDMA_EMPTYRING(d)
980  *
981  *  Free all allocated sk_buffs on the specified DMA channel;
982  *
983  *  Input parameters:
984  *         d  - DMA channel
985  *
986  *  Return value:
987  *         nothing
988  ********************************************************************* */
989 
990 static void sbdma_emptyring(struct sbmacdma *d)
991 {
992         int idx;
993         struct sk_buff *sb;
994 
995         for (idx = 0; idx < d->sbdma_maxdescr; idx++) {
996                 sb = d->sbdma_ctxtable[idx];
997                 if (sb) {
998                         dev_kfree_skb(sb);
999                         d->sbdma_ctxtable[idx] = NULL;
1000                 }
1001         }
1002 }
1003 
1004 
1005 /**********************************************************************
1006  *  SBDMA_FILLRING(d)
1007  *
1008  *  Fill the specified DMA channel (must be receive channel)
1009  *  with sk_buffs
1010  *
1011  *  Input parameters:
1012  *         sc - softc structure
1013  *          d - DMA channel
1014  *
1015  *  Return value:
1016  *         nothing
1017  ********************************************************************* */
1018 
1019 static void sbdma_fillring(struct sbmac_softc *sc, struct sbmacdma *d)
1020 {
1021         int idx;
1022 
1023         for (idx = 0; idx < SBMAC_MAX_RXDESCR - 1; idx++) {
1024                 if (sbdma_add_rcvbuffer(sc, d, NULL) != 0)
1025                         break;
1026         }
1027 }
1028 
1029 #ifdef CONFIG_NET_POLL_CONTROLLER
1030 static void sbmac_netpoll(struct net_device *netdev)
1031 {
1032         struct sbmac_softc *sc = netdev_priv(netdev);
1033         int irq = sc->sbm_dev->irq;
1034 
1035         __raw_writeq(0, sc->sbm_imr);
1036 
1037         sbmac_intr(irq, netdev);
1038 
1039 #ifdef CONFIG_SBMAC_COALESCE
1040         __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1041         ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0),
1042         sc->sbm_imr);
1043 #else
1044         __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1045         (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr);
1046 #endif
1047 }
1048 #endif
1049 
1050 /**********************************************************************
1051  *  SBDMA_RX_PROCESS(sc,d,work_to_do,poll)
1052  *
1053  *  Process "completed" receive buffers on the specified DMA channel.
1054  *
1055  *  Input parameters:
1056  *            sc - softc structure
1057  *             d - DMA channel context
1058  *    work_to_do - no. of packets to process before enabling interrupt
1059  *                 again (for NAPI)
1060  *          poll - 1: using polling (for NAPI)
1061  *
1062  *  Return value:
1063  *         nothing
1064  ********************************************************************* */
1065 
1066 static int sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d,
1067                             int work_to_do, int poll)
1068 {
1069         struct net_device *dev = sc->sbm_dev;
1070         int curidx;
1071         int hwidx;
1072         struct sbdmadscr *dsc;
1073         struct sk_buff *sb;
1074         int len;
1075         int work_done = 0;
1076         int dropped = 0;
1077 
1078         prefetch(d);
1079 
1080 again:
1081         /* Check if the HW dropped any frames */
1082         dev->stats.rx_fifo_errors
1083             += __raw_readq(sc->sbm_rxdma.sbdma_oodpktlost) & 0xffff;
1084         __raw_writeq(0, sc->sbm_rxdma.sbdma_oodpktlost);
1085 
1086         while (work_to_do-- > 0) {
1087                 /*
1088                  * figure out where we are (as an index) and where
1089                  * the hardware is (also as an index)
1090                  *
1091                  * This could be done faster if (for example) the
1092                  * descriptor table was page-aligned and contiguous in
1093                  * both virtual and physical memory -- you could then
1094                  * just compare the low-order bits of the virtual address
1095                  * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1096                  */
1097 
1098                 dsc = d->sbdma_remptr;
1099                 curidx = dsc - d->sbdma_dscrtable;
1100 
1101                 prefetch(dsc);
1102                 prefetch(&d->sbdma_ctxtable[curidx]);
1103 
1104                 hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1105                          d->sbdma_dscrtable_phys) /
1106                         sizeof(*d->sbdma_dscrtable);
1107 
1108                 /*
1109                  * If they're the same, that means we've processed all
1110                  * of the descriptors up to (but not including) the one that
1111                  * the hardware is working on right now.
1112                  */
1113 
1114                 if (curidx == hwidx)
1115                         goto done;
1116 
1117                 /*
1118                  * Otherwise, get the packet's sk_buff ptr back
1119                  */
1120 
1121                 sb = d->sbdma_ctxtable[curidx];
1122                 d->sbdma_ctxtable[curidx] = NULL;
1123 
1124                 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4;
1125 
1126                 /*
1127                  * Check packet status.  If good, process it.
1128                  * If not, silently drop it and put it back on the
1129                  * receive ring.
1130                  */
1131 
1132                 if (likely (!(dsc->dscr_a & M_DMA_ETHRX_BAD))) {
1133 
1134                         /*
1135                          * Add a new buffer to replace the old one.  If we fail
1136                          * to allocate a buffer, we're going to drop this
1137                          * packet and put it right back on the receive ring.
1138                          */
1139 
1140                         if (unlikely(sbdma_add_rcvbuffer(sc, d, NULL) ==
1141                                      -ENOBUFS)) {
1142                                 dev->stats.rx_dropped++;
1143                                 /* Re-add old buffer */
1144                                 sbdma_add_rcvbuffer(sc, d, sb);
1145                                 /* No point in continuing at the moment */
1146                                 printk(KERN_ERR "dropped packet (1)\n");
1147                                 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1148                                 goto done;
1149                         } else {
1150                                 /*
1151                                  * Set length into the packet
1152                                  */
1153                                 skb_put(sb,len);
1154 
1155                                 /*
1156                                  * Buffer has been replaced on the
1157                                  * receive ring.  Pass the buffer to
1158                                  * the kernel
1159                                  */
1160                                 sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev);
1161                                 /* Check hw IPv4/TCP checksum if supported */
1162                                 if (sc->rx_hw_checksum == ENABLE) {
1163                                         if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) &&
1164                                             !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) {
1165                                                 sb->ip_summed = CHECKSUM_UNNECESSARY;
1166                                                 /* don't need to set sb->csum */
1167                                         } else {
1168                                                 skb_checksum_none_assert(sb);
1169                                         }
1170                                 }
1171                                 prefetch(sb->data);
1172                                 prefetch((const void *)(((char *)sb->data)+32));
1173                                 if (poll)
1174                                         dropped = netif_receive_skb(sb);
1175                                 else
1176                                         dropped = netif_rx(sb);
1177 
1178                                 if (dropped == NET_RX_DROP) {
1179                                         dev->stats.rx_dropped++;
1180                                         d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1181                                         goto done;
1182                                 }
1183                                 else {
1184                                         dev->stats.rx_bytes += len;
1185                                         dev->stats.rx_packets++;
1186                                 }
1187                         }
1188                 } else {
1189                         /*
1190                          * Packet was mangled somehow.  Just drop it and
1191                          * put it back on the receive ring.
1192                          */
1193                         dev->stats.rx_errors++;
1194                         sbdma_add_rcvbuffer(sc, d, sb);
1195                 }
1196 
1197 
1198                 /*
1199                  * .. and advance to the next buffer.
1200                  */
1201 
1202                 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1203                 work_done++;
1204         }
1205         if (!poll) {
1206                 work_to_do = 32;
1207                 goto again; /* collect fifo drop statistics again */
1208         }
1209 done:
1210         return work_done;
1211 }
1212 
1213 /**********************************************************************
1214  *  SBDMA_TX_PROCESS(sc,d)
1215  *
1216  *  Process "completed" transmit buffers on the specified DMA channel.
1217  *  This is normally called within the interrupt service routine.
1218  *  Note that this isn't really ideal for priority channels, since
1219  *  it processes all of the packets on a given channel before
1220  *  returning.
1221  *
1222  *  Input parameters:
1223  *      sc - softc structure
1224  *       d - DMA channel context
1225  *    poll - 1: using polling (for NAPI)
1226  *
1227  *  Return value:
1228  *         nothing
1229  ********************************************************************* */
1230 
1231 static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d,
1232                              int poll)
1233 {
1234         struct net_device *dev = sc->sbm_dev;
1235         int curidx;
1236         int hwidx;
1237         struct sbdmadscr *dsc;
1238         struct sk_buff *sb;
1239         unsigned long flags;
1240         int packets_handled = 0;
1241 
1242         spin_lock_irqsave(&(sc->sbm_lock), flags);
1243 
1244         if (d->sbdma_remptr == d->sbdma_addptr)
1245           goto end_unlock;
1246 
1247         hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1248                  d->sbdma_dscrtable_phys) / sizeof(*d->sbdma_dscrtable);
1249 
1250         for (;;) {
1251                 /*
1252                  * figure out where we are (as an index) and where
1253                  * the hardware is (also as an index)
1254                  *
1255                  * This could be done faster if (for example) the
1256                  * descriptor table was page-aligned and contiguous in
1257                  * both virtual and physical memory -- you could then
1258                  * just compare the low-order bits of the virtual address
1259                  * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1260                  */
1261 
1262                 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1263 
1264                 /*
1265                  * If they're the same, that means we've processed all
1266                  * of the descriptors up to (but not including) the one that
1267                  * the hardware is working on right now.
1268                  */
1269 
1270                 if (curidx == hwidx)
1271                         break;
1272 
1273                 /*
1274                  * Otherwise, get the packet's sk_buff ptr back
1275                  */
1276 
1277                 dsc = &(d->sbdma_dscrtable[curidx]);
1278                 sb = d->sbdma_ctxtable[curidx];
1279                 d->sbdma_ctxtable[curidx] = NULL;
1280 
1281                 /*
1282                  * Stats
1283                  */
1284 
1285                 dev->stats.tx_bytes += sb->len;
1286                 dev->stats.tx_packets++;
1287 
1288                 /*
1289                  * for transmits, we just free buffers.
1290                  */
1291 
1292                 dev_kfree_skb_irq(sb);
1293 
1294                 /*
1295                  * .. and advance to the next buffer.
1296                  */
1297 
1298                 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1299 
1300                 packets_handled++;
1301 
1302         }
1303 
1304         /*
1305          * Decide if we should wake up the protocol or not.
1306          * Other drivers seem to do this when we reach a low
1307          * watermark on the transmit queue.
1308          */
1309 
1310         if (packets_handled)
1311                 netif_wake_queue(d->sbdma_eth->sbm_dev);
1312 
1313 end_unlock:
1314         spin_unlock_irqrestore(&(sc->sbm_lock), flags);
1315 
1316 }
1317 
1318 
1319 
1320 /**********************************************************************
1321  *  SBMAC_INITCTX(s)
1322  *
1323  *  Initialize an Ethernet context structure - this is called
1324  *  once per MAC on the 1250.  Memory is allocated here, so don't
1325  *  call it again from inside the ioctl routines that bring the
1326  *  interface up/down
1327  *
1328  *  Input parameters:
1329  *         s - sbmac context structure
1330  *
1331  *  Return value:
1332  *         0
1333  ********************************************************************* */
1334 
1335 static int sbmac_initctx(struct sbmac_softc *s)
1336 {
1337 
1338         /*
1339          * figure out the addresses of some ports
1340          */
1341 
1342         s->sbm_macenable = s->sbm_base + R_MAC_ENABLE;
1343         s->sbm_maccfg    = s->sbm_base + R_MAC_CFG;
1344         s->sbm_fifocfg   = s->sbm_base + R_MAC_THRSH_CFG;
1345         s->sbm_framecfg  = s->sbm_base + R_MAC_FRAMECFG;
1346         s->sbm_rxfilter  = s->sbm_base + R_MAC_ADFILTER_CFG;
1347         s->sbm_isr       = s->sbm_base + R_MAC_STATUS;
1348         s->sbm_imr       = s->sbm_base + R_MAC_INT_MASK;
1349         s->sbm_mdio      = s->sbm_base + R_MAC_MDIO;
1350 
1351         /*
1352          * Initialize the DMA channels.  Right now, only one per MAC is used
1353          * Note: Only do this _once_, as it allocates memory from the kernel!
1354          */
1355 
1356         sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR);
1357         sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR);
1358 
1359         /*
1360          * initial state is OFF
1361          */
1362 
1363         s->sbm_state = sbmac_state_off;
1364 
1365         return 0;
1366 }
1367 
1368 
1369 static void sbdma_uninitctx(struct sbmacdma *d)
1370 {
1371         if (d->sbdma_dscrtable_unaligned) {
1372                 kfree(d->sbdma_dscrtable_unaligned);
1373                 d->sbdma_dscrtable_unaligned = d->sbdma_dscrtable = NULL;
1374         }
1375 
1376         if (d->sbdma_ctxtable) {
1377                 kfree(d->sbdma_ctxtable);
1378                 d->sbdma_ctxtable = NULL;
1379         }
1380 }
1381 
1382 
1383 static void sbmac_uninitctx(struct sbmac_softc *sc)
1384 {
1385         sbdma_uninitctx(&(sc->sbm_txdma));
1386         sbdma_uninitctx(&(sc->sbm_rxdma));
1387 }
1388 
1389 
1390 /**********************************************************************
1391  *  SBMAC_CHANNEL_START(s)
1392  *
1393  *  Start packet processing on this MAC.
1394  *
1395  *  Input parameters:
1396  *         s - sbmac structure
1397  *
1398  *  Return value:
1399  *         nothing
1400  ********************************************************************* */
1401 
1402 static void sbmac_channel_start(struct sbmac_softc *s)
1403 {
1404         uint64_t reg;
1405         void __iomem *port;
1406         uint64_t cfg,fifo,framecfg;
1407         int idx, th_value;
1408 
1409         /*
1410          * Don't do this if running
1411          */
1412 
1413         if (s->sbm_state == sbmac_state_on)
1414                 return;
1415 
1416         /*
1417          * Bring the controller out of reset, but leave it off.
1418          */
1419 
1420         __raw_writeq(0, s->sbm_macenable);
1421 
1422         /*
1423          * Ignore all received packets
1424          */
1425 
1426         __raw_writeq(0, s->sbm_rxfilter);
1427 
1428         /*
1429          * Calculate values for various control registers.
1430          */
1431 
1432         cfg = M_MAC_RETRY_EN |
1433                 M_MAC_TX_HOLD_SOP_EN |
1434                 V_MAC_TX_PAUSE_CNT_16K |
1435                 M_MAC_AP_STAT_EN |
1436                 M_MAC_FAST_SYNC |
1437                 M_MAC_SS_EN |
1438                 0;
1439 
1440         /*
1441          * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars
1442          * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above
1443          * Use a larger RD_THRSH for gigabit
1444          */
1445         if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2)
1446                 th_value = 28;
1447         else
1448                 th_value = 64;
1449 
1450         fifo = V_MAC_TX_WR_THRSH(4) |   /* Must be '4' or '8' */
1451                 ((s->sbm_speed == sbmac_speed_1000)
1452                  ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) |
1453                 V_MAC_TX_RL_THRSH(4) |
1454                 V_MAC_RX_PL_THRSH(4) |
1455                 V_MAC_RX_RD_THRSH(4) |  /* Must be '4' */
1456                 V_MAC_RX_RL_THRSH(8) |
1457                 0;
1458 
1459         framecfg = V_MAC_MIN_FRAMESZ_DEFAULT |
1460                 V_MAC_MAX_FRAMESZ_DEFAULT |
1461                 V_MAC_BACKOFF_SEL(1);
1462 
1463         /*
1464          * Clear out the hash address map
1465          */
1466 
1467         port = s->sbm_base + R_MAC_HASH_BASE;
1468         for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
1469                 __raw_writeq(0, port);
1470                 port += sizeof(uint64_t);
1471         }
1472 
1473         /*
1474          * Clear out the exact-match table
1475          */
1476 
1477         port = s->sbm_base + R_MAC_ADDR_BASE;
1478         for (idx = 0; idx < MAC_ADDR_COUNT; idx++) {
1479                 __raw_writeq(0, port);
1480                 port += sizeof(uint64_t);
1481         }
1482 
1483         /*
1484          * Clear out the DMA Channel mapping table registers
1485          */
1486 
1487         port = s->sbm_base + R_MAC_CHUP0_BASE;
1488         for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1489                 __raw_writeq(0, port);
1490                 port += sizeof(uint64_t);
1491         }
1492 
1493 
1494         port = s->sbm_base + R_MAC_CHLO0_BASE;
1495         for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1496                 __raw_writeq(0, port);
1497                 port += sizeof(uint64_t);
1498         }
1499 
1500         /*
1501          * Program the hardware address.  It goes into the hardware-address
1502          * register as well as the first filter register.
1503          */
1504 
1505         reg = sbmac_addr2reg(s->sbm_hwaddr);
1506 
1507         port = s->sbm_base + R_MAC_ADDR_BASE;
1508         __raw_writeq(reg, port);
1509         port = s->sbm_base + R_MAC_ETHERNET_ADDR;
1510 
1511 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
1512         /*
1513          * Pass1 SOCs do not receive packets addressed to the
1514          * destination address in the R_MAC_ETHERNET_ADDR register.
1515          * Set the value to zero.
1516          */
1517         __raw_writeq(0, port);
1518 #else
1519         __raw_writeq(reg, port);
1520 #endif
1521 
1522         /*
1523          * Set the receive filter for no packets, and write values
1524          * to the various config registers
1525          */
1526 
1527         __raw_writeq(0, s->sbm_rxfilter);
1528         __raw_writeq(0, s->sbm_imr);
1529         __raw_writeq(framecfg, s->sbm_framecfg);
1530         __raw_writeq(fifo, s->sbm_fifocfg);
1531         __raw_writeq(cfg, s->sbm_maccfg);
1532 
1533         /*
1534          * Initialize DMA channels (rings should be ok now)
1535          */
1536 
1537         sbdma_channel_start(&(s->sbm_rxdma), DMA_RX);
1538         sbdma_channel_start(&(s->sbm_txdma), DMA_TX);
1539 
1540         /*
1541          * Configure the speed, duplex, and flow control
1542          */
1543 
1544         sbmac_set_speed(s,s->sbm_speed);
1545         sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc);
1546 
1547         /*
1548          * Fill the receive ring
1549          */
1550 
1551         sbdma_fillring(s, &(s->sbm_rxdma));
1552 
1553         /*
1554          * Turn on the rest of the bits in the enable register
1555          */
1556 
1557 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
1558         __raw_writeq(M_MAC_RXDMA_EN0 |
1559                        M_MAC_TXDMA_EN0, s->sbm_macenable);
1560 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
1561         __raw_writeq(M_MAC_RXDMA_EN0 |
1562                        M_MAC_TXDMA_EN0 |
1563                        M_MAC_RX_ENABLE |
1564                        M_MAC_TX_ENABLE, s->sbm_macenable);
1565 #else
1566 #error invalid SiByte MAC configuration
1567 #endif
1568 
1569 #ifdef CONFIG_SBMAC_COALESCE
1570         __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1571                        ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), s->sbm_imr);
1572 #else
1573         __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1574                        (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), s->sbm_imr);
1575 #endif
1576 
1577         /*
1578          * Enable receiving unicasts and broadcasts
1579          */
1580 
1581         __raw_writeq(M_MAC_UCAST_EN | M_MAC_BCAST_EN, s->sbm_rxfilter);
1582 
1583         /*
1584          * we're running now.
1585          */
1586 
1587         s->sbm_state = sbmac_state_on;
1588 
1589         /*
1590          * Program multicast addresses
1591          */
1592 
1593         sbmac_setmulti(s);
1594 
1595         /*
1596          * If channel was in promiscuous mode before, turn that on
1597          */
1598 
1599         if (s->sbm_devflags & IFF_PROMISC) {
1600                 sbmac_promiscuous_mode(s,1);
1601         }
1602 
1603 }
1604 
1605 
1606 /**********************************************************************
1607  *  SBMAC_CHANNEL_STOP(s)
1608  *
1609  *  Stop packet processing on this MAC.
1610  *
1611  *  Input parameters:
1612  *         s - sbmac structure
1613  *
1614  *  Return value:
1615  *         nothing
1616  ********************************************************************* */
1617 
1618 static void sbmac_channel_stop(struct sbmac_softc *s)
1619 {
1620         /* don't do this if already stopped */
1621 
1622         if (s->sbm_state == sbmac_state_off)
1623                 return;
1624 
1625         /* don't accept any packets, disable all interrupts */
1626 
1627         __raw_writeq(0, s->sbm_rxfilter);
1628         __raw_writeq(0, s->sbm_imr);
1629 
1630         /* Turn off ticker */
1631 
1632         /* XXX */
1633 
1634         /* turn off receiver and transmitter */
1635 
1636         __raw_writeq(0, s->sbm_macenable);
1637 
1638         /* We're stopped now. */
1639 
1640         s->sbm_state = sbmac_state_off;
1641 
1642         /*
1643          * Stop DMA channels (rings should be ok now)
1644          */
1645 
1646         sbdma_channel_stop(&(s->sbm_rxdma));
1647         sbdma_channel_stop(&(s->sbm_txdma));
1648 
1649         /* Empty the receive and transmit rings */
1650 
1651         sbdma_emptyring(&(s->sbm_rxdma));
1652         sbdma_emptyring(&(s->sbm_txdma));
1653 
1654 }
1655 
1656 /**********************************************************************
1657  *  SBMAC_SET_CHANNEL_STATE(state)
1658  *
1659  *  Set the channel's state ON or OFF
1660  *
1661  *  Input parameters:
1662  *         state - new state
1663  *
1664  *  Return value:
1665  *         old state
1666  ********************************************************************* */
1667 static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *sc,
1668                                                 enum sbmac_state state)
1669 {
1670         enum sbmac_state oldstate = sc->sbm_state;
1671 
1672         /*
1673          * If same as previous state, return
1674          */
1675 
1676         if (state == oldstate) {
1677                 return oldstate;
1678         }
1679 
1680         /*
1681          * If new state is ON, turn channel on
1682          */
1683 
1684         if (state == sbmac_state_on) {
1685                 sbmac_channel_start(sc);
1686         }
1687         else {
1688                 sbmac_channel_stop(sc);
1689         }
1690 
1691         /*
1692          * Return previous state
1693          */
1694 
1695         return oldstate;
1696 }
1697 
1698 
1699 /**********************************************************************
1700  *  SBMAC_PROMISCUOUS_MODE(sc,onoff)
1701  *
1702  *  Turn on or off promiscuous mode
1703  *
1704  *  Input parameters:
1705  *         sc - softc
1706  *      onoff - 1 to turn on, 0 to turn off
1707  *
1708  *  Return value:
1709  *         nothing
1710  ********************************************************************* */
1711 
1712 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff)
1713 {
1714         uint64_t reg;
1715 
1716         if (sc->sbm_state != sbmac_state_on)
1717                 return;
1718 
1719         if (onoff) {
1720                 reg = __raw_readq(sc->sbm_rxfilter);
1721                 reg |= M_MAC_ALLPKT_EN;
1722                 __raw_writeq(reg, sc->sbm_rxfilter);
1723         }
1724         else {
1725                 reg = __raw_readq(sc->sbm_rxfilter);
1726                 reg &= ~M_MAC_ALLPKT_EN;
1727                 __raw_writeq(reg, sc->sbm_rxfilter);
1728         }
1729 }
1730 
1731 /**********************************************************************
1732  *  SBMAC_SETIPHDR_OFFSET(sc,onoff)
1733  *
1734  *  Set the iphdr offset as 15 assuming ethernet encapsulation
1735  *
1736  *  Input parameters:
1737  *         sc - softc
1738  *
1739  *  Return value:
1740  *         nothing
1741  ********************************************************************* */
1742 
1743 static void sbmac_set_iphdr_offset(struct sbmac_softc *sc)
1744 {
1745         uint64_t reg;
1746 
1747         /* Hard code the off set to 15 for now */
1748         reg = __raw_readq(sc->sbm_rxfilter);
1749         reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15);
1750         __raw_writeq(reg, sc->sbm_rxfilter);
1751 
1752         /* BCM1250 pass1 didn't have hardware checksum.  Everything
1753            later does.  */
1754         if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) {
1755                 sc->rx_hw_checksum = DISABLE;
1756         } else {
1757                 sc->rx_hw_checksum = ENABLE;
1758         }
1759 }
1760 
1761 
1762 /**********************************************************************
1763  *  SBMAC_ADDR2REG(ptr)
1764  *
1765  *  Convert six bytes into the 64-bit register value that
1766  *  we typically write into the SBMAC's address/mcast registers
1767  *
1768  *  Input parameters:
1769  *         ptr - pointer to 6 bytes
1770  *
1771  *  Return value:
1772  *         register value
1773  ********************************************************************* */
1774 
1775 static uint64_t sbmac_addr2reg(unsigned char *ptr)
1776 {
1777         uint64_t reg = 0;
1778 
1779         ptr += 6;
1780 
1781         reg |= (uint64_t) *(--ptr);
1782         reg <<= 8;
1783         reg |= (uint64_t) *(--ptr);
1784         reg <<= 8;
1785         reg |= (uint64_t) *(--ptr);
1786         reg <<= 8;
1787         reg |= (uint64_t) *(--ptr);
1788         reg <<= 8;
1789         reg |= (uint64_t) *(--ptr);
1790         reg <<= 8;
1791         reg |= (uint64_t) *(--ptr);
1792 
1793         return reg;
1794 }
1795 
1796 
1797 /**********************************************************************
1798  *  SBMAC_SET_SPEED(s,speed)
1799  *
1800  *  Configure LAN speed for the specified MAC.
1801  *  Warning: must be called when MAC is off!
1802  *
1803  *  Input parameters:
1804  *         s - sbmac structure
1805  *         speed - speed to set MAC to (see enum sbmac_speed)
1806  *
1807  *  Return value:
1808  *         1 if successful
1809  *      0 indicates invalid parameters
1810  ********************************************************************* */
1811 
1812 static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed)
1813 {
1814         uint64_t cfg;
1815         uint64_t framecfg;
1816 
1817         /*
1818          * Save new current values
1819          */
1820 
1821         s->sbm_speed = speed;
1822 
1823         if (s->sbm_state == sbmac_state_on)
1824                 return 0;       /* save for next restart */
1825 
1826         /*
1827          * Read current register values
1828          */
1829 
1830         cfg = __raw_readq(s->sbm_maccfg);
1831         framecfg = __raw_readq(s->sbm_framecfg);
1832 
1833         /*
1834          * Mask out the stuff we want to change
1835          */
1836 
1837         cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL);
1838         framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH |
1839                       M_MAC_SLOT_SIZE);
1840 
1841         /*
1842          * Now add in the new bits
1843          */
1844 
1845         switch (speed) {
1846         case sbmac_speed_10:
1847                 framecfg |= V_MAC_IFG_RX_10 |
1848                         V_MAC_IFG_TX_10 |
1849                         K_MAC_IFG_THRSH_10 |
1850                         V_MAC_SLOT_SIZE_10;
1851                 cfg |= V_MAC_SPEED_SEL_10MBPS;
1852                 break;
1853 
1854         case sbmac_speed_100:
1855                 framecfg |= V_MAC_IFG_RX_100 |
1856                         V_MAC_IFG_TX_100 |
1857                         V_MAC_IFG_THRSH_100 |
1858                         V_MAC_SLOT_SIZE_100;
1859                 cfg |= V_MAC_SPEED_SEL_100MBPS ;
1860                 break;
1861 
1862         case sbmac_speed_1000:
1863                 framecfg |= V_MAC_IFG_RX_1000 |
1864                         V_MAC_IFG_TX_1000 |
1865                         V_MAC_IFG_THRSH_1000 |
1866                         V_MAC_SLOT_SIZE_1000;
1867                 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN;
1868                 break;
1869 
1870         default:
1871                 return 0;
1872         }
1873 
1874         /*
1875          * Send the bits back to the hardware
1876          */
1877 
1878         __raw_writeq(framecfg, s->sbm_framecfg);
1879         __raw_writeq(cfg, s->sbm_maccfg);
1880 
1881         return 1;
1882 }
1883 
1884 /**********************************************************************
1885  *  SBMAC_SET_DUPLEX(s,duplex,fc)
1886  *
1887  *  Set Ethernet duplex and flow control options for this MAC
1888  *  Warning: must be called when MAC is off!
1889  *
1890  *  Input parameters:
1891  *         s - sbmac structure
1892  *         duplex - duplex setting (see enum sbmac_duplex)
1893  *         fc - flow control setting (see enum sbmac_fc)
1894  *
1895  *  Return value:
1896  *         1 if ok
1897  *         0 if an invalid parameter combination was specified
1898  ********************************************************************* */
1899 
1900 static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex,
1901                             enum sbmac_fc fc)
1902 {
1903         uint64_t cfg;
1904 
1905         /*
1906          * Save new current values
1907          */
1908 
1909         s->sbm_duplex = duplex;
1910         s->sbm_fc = fc;
1911 
1912         if (s->sbm_state == sbmac_state_on)
1913                 return 0;       /* save for next restart */
1914 
1915         /*
1916          * Read current register values
1917          */
1918 
1919         cfg = __raw_readq(s->sbm_maccfg);
1920 
1921         /*
1922          * Mask off the stuff we're about to change
1923          */
1924 
1925         cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN);
1926 
1927 
1928         switch (duplex) {
1929         case sbmac_duplex_half:
1930                 switch (fc) {
1931                 case sbmac_fc_disabled:
1932                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED;
1933                         break;
1934 
1935                 case sbmac_fc_collision:
1936                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED;
1937                         break;
1938 
1939                 case sbmac_fc_carrier:
1940                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR;
1941                         break;
1942 
1943                 case sbmac_fc_frame:            /* not valid in half duplex */
1944                 default:                        /* invalid selection */
1945                         return 0;
1946                 }
1947                 break;
1948 
1949         case sbmac_duplex_full:
1950                 switch (fc) {
1951                 case sbmac_fc_disabled:
1952                         cfg |= V_MAC_FC_CMD_DISABLED;
1953                         break;
1954 
1955                 case sbmac_fc_frame:
1956                         cfg |= V_MAC_FC_CMD_ENABLED;
1957                         break;
1958 
1959                 case sbmac_fc_collision:        /* not valid in full duplex */
1960                 case sbmac_fc_carrier:          /* not valid in full duplex */
1961                 default:
1962                         return 0;
1963                 }
1964                 break;
1965         default:
1966                 return 0;
1967         }
1968 
1969         /*
1970          * Send the bits back to the hardware
1971          */
1972 
1973         __raw_writeq(cfg, s->sbm_maccfg);
1974 
1975         return 1;
1976 }
1977 
1978 
1979 
1980 
1981 /**********************************************************************
1982  *  SBMAC_INTR()
1983  *
1984  *  Interrupt handler for MAC interrupts
1985  *
1986  *  Input parameters:
1987  *         MAC structure
1988  *
1989  *  Return value:
1990  *         nothing
1991  ********************************************************************* */
1992 static irqreturn_t sbmac_intr(int irq,void *dev_instance)
1993 {
1994         struct net_device *dev = (struct net_device *) dev_instance;
1995         struct sbmac_softc *sc = netdev_priv(dev);
1996         uint64_t isr;
1997         int handled = 0;
1998 
1999         /*
2000          * Read the ISR (this clears the bits in the real
2001          * register, except for counter addr)
2002          */
2003 
2004         isr = __raw_readq(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;
2005 
2006         if (isr == 0)
2007                 return IRQ_RETVAL(0);
2008         handled = 1;
2009 
2010         /*
2011          * Transmits on channel 0
2012          */
2013 
2014         if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0))
2015                 sbdma_tx_process(sc,&(sc->sbm_txdma), 0);
2016 
2017         if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {
2018                 if (napi_schedule_prep(&sc->napi)) {
2019                         __raw_writeq(0, sc->sbm_imr);
2020                         __napi_schedule(&sc->napi);
2021                         /* Depend on the exit from poll to reenable intr */
2022                 }
2023                 else {
2024                         /* may leave some packets behind */
2025                         sbdma_rx_process(sc,&(sc->sbm_rxdma),
2026                                          SBMAC_MAX_RXDESCR * 2, 0);
2027                 }
2028         }
2029         return IRQ_RETVAL(handled);
2030 }
2031 
2032 /**********************************************************************
2033  *  SBMAC_START_TX(skb,dev)
2034  *
2035  *  Start output on the specified interface.  Basically, we
2036  *  queue as many buffers as we can until the ring fills up, or
2037  *  we run off the end of the queue, whichever comes first.
2038  *
2039  *  Input parameters:
2040  *
2041  *
2042  *  Return value:
2043  *         nothing
2044  ********************************************************************* */
2045 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev)
2046 {
2047         struct sbmac_softc *sc = netdev_priv(dev);
2048         unsigned long flags;
2049 
2050         /* lock eth irq */
2051         spin_lock_irqsave(&sc->sbm_lock, flags);
2052 
2053         /*
2054          * Put the buffer on the transmit ring.  If we
2055          * don't have room, stop the queue.
2056          */
2057 
2058         if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) {
2059                 /* XXX save skb that we could not send */
2060                 netif_stop_queue(dev);
2061                 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2062 
2063                 return NETDEV_TX_BUSY;
2064         }
2065 
2066         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2067 
2068         return NETDEV_TX_OK;
2069 }
2070 
2071 /**********************************************************************
2072  *  SBMAC_SETMULTI(sc)
2073  *
2074  *  Reprogram the multicast table into the hardware, given
2075  *  the list of multicasts associated with the interface
2076  *  structure.
2077  *
2078  *  Input parameters:
2079  *         sc - softc
2080  *
2081  *  Return value:
2082  *         nothing
2083  ********************************************************************* */
2084 
2085 static void sbmac_setmulti(struct sbmac_softc *sc)
2086 {
2087         uint64_t reg;
2088         void __iomem *port;
2089         int idx;
2090         struct netdev_hw_addr *ha;
2091         struct net_device *dev = sc->sbm_dev;
2092 
2093         /*
2094          * Clear out entire multicast table.  We do this by nuking
2095          * the entire hash table and all the direct matches except
2096          * the first one, which is used for our station address
2097          */
2098 
2099         for (idx = 1; idx < MAC_ADDR_COUNT; idx++) {
2100                 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t));
2101                 __raw_writeq(0, port);
2102         }
2103 
2104         for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
2105                 port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t));
2106                 __raw_writeq(0, port);
2107         }
2108 
2109         /*
2110          * Clear the filter to say we don't want any multicasts.
2111          */
2112 
2113         reg = __raw_readq(sc->sbm_rxfilter);
2114         reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2115         __raw_writeq(reg, sc->sbm_rxfilter);
2116 
2117         if (dev->flags & IFF_ALLMULTI) {
2118                 /*
2119                  * Enable ALL multicasts.  Do this by inverting the
2120                  * multicast enable bit.
2121                  */
2122                 reg = __raw_readq(sc->sbm_rxfilter);
2123                 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2124                 __raw_writeq(reg, sc->sbm_rxfilter);
2125                 return;
2126         }
2127 
2128 
2129         /*
2130          * Progam new multicast entries.  For now, only use the
2131          * perfect filter.  In the future we'll need to use the
2132          * hash filter if the perfect filter overflows
2133          */
2134 
2135         /* XXX only using perfect filter for now, need to use hash
2136          * XXX if the table overflows */
2137 
2138         idx = 1;                /* skip station address */
2139         netdev_for_each_mc_addr(ha, dev) {
2140                 if (idx == MAC_ADDR_COUNT)
2141                         break;
2142                 reg = sbmac_addr2reg(ha->addr);
2143                 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t));
2144                 __raw_writeq(reg, port);
2145                 idx++;
2146         }
2147 
2148         /*
2149          * Enable the "accept multicast bits" if we programmed at least one
2150          * multicast.
2151          */
2152 
2153         if (idx > 1) {
2154                 reg = __raw_readq(sc->sbm_rxfilter);
2155                 reg |= M_MAC_MCAST_EN;
2156                 __raw_writeq(reg, sc->sbm_rxfilter);
2157         }
2158 }
2159 
2160 static int sb1250_change_mtu(struct net_device *_dev, int new_mtu)
2161 {
2162         if (new_mtu >  ENET_PACKET_SIZE)
2163                 return -EINVAL;
2164         _dev->mtu = new_mtu;
2165         pr_info("changing the mtu to %d\n", new_mtu);
2166         return 0;
2167 }
2168 
2169 static const struct net_device_ops sbmac_netdev_ops = {
2170         .ndo_open               = sbmac_open,
2171         .ndo_stop               = sbmac_close,
2172         .ndo_start_xmit         = sbmac_start_tx,
2173         .ndo_set_rx_mode        = sbmac_set_rx_mode,
2174         .ndo_tx_timeout         = sbmac_tx_timeout,
2175         .ndo_do_ioctl           = sbmac_mii_ioctl,
2176         .ndo_change_mtu         = sb1250_change_mtu,
2177         .ndo_validate_addr      = eth_validate_addr,
2178         .ndo_set_mac_address    = eth_mac_addr,
2179 #ifdef CONFIG_NET_POLL_CONTROLLER
2180         .ndo_poll_controller    = sbmac_netpoll,
2181 #endif
2182 };
2183 
2184 /**********************************************************************
2185  *  SBMAC_INIT(dev)
2186  *
2187  *  Attach routine - init hardware and hook ourselves into linux
2188  *
2189  *  Input parameters:
2190  *         dev - net_device structure
2191  *
2192  *  Return value:
2193  *         status
2194  ********************************************************************* */
2195 
2196 static int sbmac_init(struct platform_device *pldev, long long base)
2197 {
2198         struct net_device *dev = platform_get_drvdata(pldev);
2199         int idx = pldev->id;
2200         struct sbmac_softc *sc = netdev_priv(dev);
2201         unsigned char *eaddr;
2202         uint64_t ea_reg;
2203         int i;
2204         int err;
2205 
2206         sc->sbm_dev = dev;
2207         sc->sbe_idx = idx;
2208 
2209         eaddr = sc->sbm_hwaddr;
2210 
2211         /*
2212          * Read the ethernet address.  The firmware left this programmed
2213          * for us in the ethernet address register for each mac.
2214          */
2215 
2216         ea_reg = __raw_readq(sc->sbm_base + R_MAC_ETHERNET_ADDR);
2217         __raw_writeq(0, sc->sbm_base + R_MAC_ETHERNET_ADDR);
2218         for (i = 0; i < 6; i++) {
2219                 eaddr[i] = (uint8_t) (ea_reg & 0xFF);
2220                 ea_reg >>= 8;
2221         }
2222 
2223         for (i = 0; i < 6; i++) {
2224                 dev->dev_addr[i] = eaddr[i];
2225         }
2226 
2227         /*
2228          * Initialize context (get pointers to registers and stuff), then
2229          * allocate the memory for the descriptor tables.
2230          */
2231 
2232         sbmac_initctx(sc);
2233 
2234         /*
2235          * Set up Linux device callins
2236          */
2237 
2238         spin_lock_init(&(sc->sbm_lock));
2239 
2240         dev->netdev_ops = &sbmac_netdev_ops;
2241         dev->watchdog_timeo = TX_TIMEOUT;
2242 
2243         netif_napi_add(dev, &sc->napi, sbmac_poll, 16);
2244 
2245         dev->irq                = UNIT_INT(idx);
2246 
2247         /* This is needed for PASS2 for Rx H/W checksum feature */
2248         sbmac_set_iphdr_offset(sc);
2249 
2250         sc->mii_bus = mdiobus_alloc();
2251         if (sc->mii_bus == NULL) {
2252                 err = -ENOMEM;
2253                 goto uninit_ctx;
2254         }
2255 
2256         sc->mii_bus->name = sbmac_mdio_string;
2257         snprintf(sc->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2258                 pldev->name, idx);
2259         sc->mii_bus->priv = sc;
2260         sc->mii_bus->read = sbmac_mii_read;
2261         sc->mii_bus->write = sbmac_mii_write;
2262         sc->mii_bus->irq = sc->phy_irq;
2263         for (i = 0; i < PHY_MAX_ADDR; ++i)
2264                 sc->mii_bus->irq[i] = SBMAC_PHY_INT;
2265 
2266         sc->mii_bus->parent = &pldev->dev;
2267         /*
2268          * Probe PHY address
2269          */
2270         err = mdiobus_register(sc->mii_bus);
2271         if (err) {
2272                 printk(KERN_ERR "%s: unable to register MDIO bus\n",
2273                        dev->name);
2274                 goto free_mdio;
2275         }
2276         platform_set_drvdata(pldev, sc->mii_bus);
2277 
2278         err = register_netdev(dev);
2279         if (err) {
2280                 printk(KERN_ERR "%s.%d: unable to register netdev\n",
2281                        sbmac_string, idx);
2282                 goto unreg_mdio;
2283         }
2284 
2285         pr_info("%s.%d: registered as %s\n", sbmac_string, idx, dev->name);
2286 
2287         if (sc->rx_hw_checksum == ENABLE)
2288                 pr_info("%s: enabling TCP rcv checksum\n", dev->name);
2289 
2290         /*
2291          * Display Ethernet address (this is called during the config
2292          * process so we need to finish off the config message that
2293          * was being displayed)
2294          */
2295         pr_info("%s: SiByte Ethernet at 0x%08Lx, address: %pM\n",
2296                dev->name, base, eaddr);
2297 
2298         return 0;
2299 unreg_mdio:
2300         mdiobus_unregister(sc->mii_bus);
2301 free_mdio:
2302         mdiobus_free(sc->mii_bus);
2303 uninit_ctx:
2304         sbmac_uninitctx(sc);
2305         return err;
2306 }
2307 
2308 
2309 static int sbmac_open(struct net_device *dev)
2310 {
2311         struct sbmac_softc *sc = netdev_priv(dev);
2312         int err;
2313 
2314         if (debug > 1)
2315                 pr_debug("%s: sbmac_open() irq %d.\n", dev->name, dev->irq);
2316 
2317         /*
2318          * map/route interrupt (clear status first, in case something
2319          * weird is pending; we haven't initialized the mac registers
2320          * yet)
2321          */
2322 
2323         __raw_readq(sc->sbm_isr);
2324         err = request_irq(dev->irq, sbmac_intr, IRQF_SHARED, dev->name, dev);
2325         if (err) {
2326                 printk(KERN_ERR "%s: unable to get IRQ %d\n", dev->name,
2327                        dev->irq);
2328                 goto out_err;
2329         }
2330 
2331         sc->sbm_speed = sbmac_speed_none;
2332         sc->sbm_duplex = sbmac_duplex_none;
2333         sc->sbm_fc = sbmac_fc_none;
2334         sc->sbm_pause = -1;
2335         sc->sbm_link = 0;
2336 
2337         /*
2338          * Attach to the PHY
2339          */
2340         err = sbmac_mii_probe(dev);
2341         if (err)
2342                 goto out_unregister;
2343 
2344         /*
2345          * Turn on the channel
2346          */
2347 
2348         sbmac_set_channel_state(sc,sbmac_state_on);
2349 
2350         netif_start_queue(dev);
2351 
2352         sbmac_set_rx_mode(dev);
2353 
2354         phy_start(sc->phy_dev);
2355 
2356         napi_enable(&sc->napi);
2357 
2358         return 0;
2359 
2360 out_unregister:
2361         free_irq(dev->irq, dev);
2362 out_err:
2363         return err;
2364 }
2365 
2366 static int sbmac_mii_probe(struct net_device *dev)
2367 {
2368         struct sbmac_softc *sc = netdev_priv(dev);
2369         struct phy_device *phy_dev;
2370         int i;
2371 
2372         for (i = 0; i < PHY_MAX_ADDR; i++) {
2373                 phy_dev = sc->mii_bus->phy_map[i];
2374                 if (phy_dev)
2375                         break;
2376         }
2377         if (!phy_dev) {
2378                 printk(KERN_ERR "%s: no PHY found\n", dev->name);
2379                 return -ENXIO;
2380         }
2381 
2382         phy_dev = phy_connect(dev, dev_name(&phy_dev->dev), &sbmac_mii_poll,
2383                               PHY_INTERFACE_MODE_GMII);
2384         if (IS_ERR(phy_dev)) {
2385                 printk(KERN_ERR "%s: could not attach to PHY\n", dev->name);
2386                 return PTR_ERR(phy_dev);
2387         }
2388 
2389         /* Remove any features not supported by the controller */
2390         phy_dev->supported &= SUPPORTED_10baseT_Half |
2391                               SUPPORTED_10baseT_Full |
2392                               SUPPORTED_100baseT_Half |
2393                               SUPPORTED_100baseT_Full |
2394                               SUPPORTED_1000baseT_Half |
2395                               SUPPORTED_1000baseT_Full |
2396                               SUPPORTED_Autoneg |
2397                               SUPPORTED_MII |
2398                               SUPPORTED_Pause |
2399                               SUPPORTED_Asym_Pause;
2400         phy_dev->advertising = phy_dev->supported;
2401 
2402         pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
2403                 dev->name, phy_dev->drv->name,
2404                 dev_name(&phy_dev->dev), phy_dev->irq);
2405 
2406         sc->phy_dev = phy_dev;
2407 
2408         return 0;
2409 }
2410 
2411 
2412 static void sbmac_mii_poll(struct net_device *dev)
2413 {
2414         struct sbmac_softc *sc = netdev_priv(dev);
2415         struct phy_device *phy_dev = sc->phy_dev;
2416         unsigned long flags;
2417         enum sbmac_fc fc;
2418         int link_chg, speed_chg, duplex_chg, pause_chg, fc_chg;
2419 
2420         link_chg = (sc->sbm_link != phy_dev->link);
2421         speed_chg = (sc->sbm_speed != phy_dev->speed);
2422         duplex_chg = (sc->sbm_duplex != phy_dev->duplex);
2423         pause_chg = (sc->sbm_pause != phy_dev->pause);
2424 
2425         if (!link_chg && !speed_chg && !duplex_chg && !pause_chg)
2426                 return;                                 /* Hmmm... */
2427 
2428         if (!phy_dev->link) {
2429                 if (link_chg) {
2430                         sc->sbm_link = phy_dev->link;
2431                         sc->sbm_speed = sbmac_speed_none;
2432                         sc->sbm_duplex = sbmac_duplex_none;
2433                         sc->sbm_fc = sbmac_fc_disabled;
2434                         sc->sbm_pause = -1;
2435                         pr_info("%s: link unavailable\n", dev->name);
2436                 }
2437                 return;
2438         }
2439 
2440         if (phy_dev->duplex == DUPLEX_FULL) {
2441                 if (phy_dev->pause)
2442                         fc = sbmac_fc_frame;
2443                 else
2444                         fc = sbmac_fc_disabled;
2445         } else
2446                 fc = sbmac_fc_collision;
2447         fc_chg = (sc->sbm_fc != fc);
2448 
2449         pr_info("%s: link available: %dbase-%cD\n", dev->name, phy_dev->speed,
2450                 phy_dev->duplex == DUPLEX_FULL ? 'F' : 'H');
2451 
2452         spin_lock_irqsave(&sc->sbm_lock, flags);
2453 
2454         sc->sbm_speed = phy_dev->speed;
2455         sc->sbm_duplex = phy_dev->duplex;
2456         sc->sbm_fc = fc;
2457         sc->sbm_pause = phy_dev->pause;
2458         sc->sbm_link = phy_dev->link;
2459 
2460         if ((speed_chg || duplex_chg || fc_chg) &&
2461             sc->sbm_state != sbmac_state_off) {
2462                 /*
2463                  * something changed, restart the channel
2464                  */
2465                 if (debug > 1)
2466                         pr_debug("%s: restarting channel "
2467                                  "because PHY state changed\n", dev->name);
2468                 sbmac_channel_stop(sc);
2469                 sbmac_channel_start(sc);
2470         }
2471 
2472         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2473 }
2474 
2475 
2476 static void sbmac_tx_timeout (struct net_device *dev)
2477 {
2478         struct sbmac_softc *sc = netdev_priv(dev);
2479         unsigned long flags;
2480 
2481         spin_lock_irqsave(&sc->sbm_lock, flags);
2482 
2483 
2484         dev->trans_start = jiffies; /* prevent tx timeout */
2485         dev->stats.tx_errors++;
2486 
2487         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2488 
2489         printk (KERN_WARNING "%s: Transmit timed out\n",dev->name);
2490 }
2491 
2492 
2493 
2494 
2495 static void sbmac_set_rx_mode(struct net_device *dev)
2496 {
2497         unsigned long flags;
2498         struct sbmac_softc *sc = netdev_priv(dev);
2499 
2500         spin_lock_irqsave(&sc->sbm_lock, flags);
2501         if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) {
2502                 /*
2503                  * Promiscuous changed.
2504                  */
2505 
2506                 if (dev->flags & IFF_PROMISC) {
2507                         sbmac_promiscuous_mode(sc,1);
2508                 }
2509                 else {
2510                         sbmac_promiscuous_mode(sc,0);
2511                 }
2512         }
2513         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2514 
2515         /*
2516          * Program the multicasts.  Do this every time.
2517          */
2518 
2519         sbmac_setmulti(sc);
2520 
2521 }
2522 
2523 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2524 {
2525         struct sbmac_softc *sc = netdev_priv(dev);
2526 
2527         if (!netif_running(dev) || !sc->phy_dev)
2528                 return -EINVAL;
2529 
2530         return phy_mii_ioctl(sc->phy_dev, rq, cmd);
2531 }
2532 
2533 static int sbmac_close(struct net_device *dev)
2534 {
2535         struct sbmac_softc *sc = netdev_priv(dev);
2536 
2537         napi_disable(&sc->napi);
2538 
2539         phy_stop(sc->phy_dev);
2540 
2541         sbmac_set_channel_state(sc, sbmac_state_off);
2542 
2543         netif_stop_queue(dev);
2544 
2545         if (debug > 1)
2546                 pr_debug("%s: Shutting down ethercard\n", dev->name);
2547 
2548         phy_disconnect(sc->phy_dev);
2549         sc->phy_dev = NULL;
2550         free_irq(dev->irq, dev);
2551 
2552         sbdma_emptyring(&(sc->sbm_txdma));
2553         sbdma_emptyring(&(sc->sbm_rxdma));
2554 
2555         return 0;
2556 }
2557 
2558 static int sbmac_poll(struct napi_struct *napi, int budget)
2559 {
2560         struct sbmac_softc *sc = container_of(napi, struct sbmac_softc, napi);
2561         int work_done;
2562 
2563         work_done = sbdma_rx_process(sc, &(sc->sbm_rxdma), budget, 1);
2564         sbdma_tx_process(sc, &(sc->sbm_txdma), 1);
2565 
2566         if (work_done < budget) {
2567                 napi_complete(napi);
2568 
2569 #ifdef CONFIG_SBMAC_COALESCE
2570                 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
2571                              ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0),
2572                              sc->sbm_imr);
2573 #else
2574                 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
2575                              (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr);
2576 #endif
2577         }
2578 
2579         return work_done;
2580 }
2581 
2582 
2583 static int sbmac_probe(struct platform_device *pldev)
2584 {
2585         struct net_device *dev;
2586         struct sbmac_softc *sc;
2587         void __iomem *sbm_base;
2588         struct resource *res;
2589         u64 sbmac_orig_hwaddr;
2590         int err;
2591 
2592         res = platform_get_resource(pldev, IORESOURCE_MEM, 0);
2593         BUG_ON(!res);
2594         sbm_base = ioremap_nocache(res->start, resource_size(res));
2595         if (!sbm_base) {
2596                 printk(KERN_ERR "%s: unable to map device registers\n",
2597                        dev_name(&pldev->dev));
2598                 err = -ENOMEM;
2599                 goto out_out;
2600         }
2601 
2602         /*
2603          * The R_MAC_ETHERNET_ADDR register will be set to some nonzero
2604          * value for us by the firmware if we're going to use this MAC.
2605          * If we find a zero, skip this MAC.
2606          */
2607         sbmac_orig_hwaddr = __raw_readq(sbm_base + R_MAC_ETHERNET_ADDR);
2608         pr_debug("%s: %sconfiguring MAC at 0x%08Lx\n", dev_name(&pldev->dev),
2609                  sbmac_orig_hwaddr ? "" : "not ", (long long)res->start);
2610         if (sbmac_orig_hwaddr == 0) {
2611                 err = 0;
2612                 goto out_unmap;
2613         }
2614 
2615         /*
2616          * Okay, cool.  Initialize this MAC.
2617          */
2618         dev = alloc_etherdev(sizeof(struct sbmac_softc));
2619         if (!dev) {
2620                 err = -ENOMEM;
2621                 goto out_unmap;
2622         }
2623 
2624         platform_set_drvdata(pldev, dev);
2625         SET_NETDEV_DEV(dev, &pldev->dev);
2626 
2627         sc = netdev_priv(dev);
2628         sc->sbm_base = sbm_base;
2629 
2630         err = sbmac_init(pldev, res->start);
2631         if (err)
2632                 goto out_kfree;
2633 
2634         return 0;
2635 
2636 out_kfree:
2637         free_netdev(dev);
2638         __raw_writeq(sbmac_orig_hwaddr, sbm_base + R_MAC_ETHERNET_ADDR);
2639 
2640 out_unmap:
2641         iounmap(sbm_base);
2642 
2643 out_out:
2644         return err;
2645 }
2646 
2647 static int __exit sbmac_remove(struct platform_device *pldev)
2648 {
2649         struct net_device *dev = platform_get_drvdata(pldev);
2650         struct sbmac_softc *sc = netdev_priv(dev);
2651 
2652         unregister_netdev(dev);
2653         sbmac_uninitctx(sc);
2654         mdiobus_unregister(sc->mii_bus);
2655         mdiobus_free(sc->mii_bus);
2656         iounmap(sc->sbm_base);
2657         free_netdev(dev);
2658 
2659         return 0;
2660 }
2661 
2662 static struct platform_driver sbmac_driver = {
2663         .probe = sbmac_probe,
2664         .remove = __exit_p(sbmac_remove),
2665         .driver = {
2666                 .name = sbmac_string,
2667                 .owner  = THIS_MODULE,
2668         },
2669 };
2670 
2671 module_platform_driver(sbmac_driver);
2672 

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