Version:  2.0.40 2.2.26 2.4.37 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15

Linux/drivers/net/ethernet/broadcom/genet/bcmgenet.c

  1 /*
  2  * Broadcom GENET (Gigabit Ethernet) controller driver
  3  *
  4  * Copyright (c) 2014 Broadcom Corporation
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License version 2 as
  8  * published by the Free Software Foundation.
  9  *
 10  * This program is distributed in the hope that it will be useful,
 11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 13  * GNU General Public License for more details.
 14  *
 15  * You should have received a copy of the GNU General Public License
 16  * along with this program; if not, write to the Free Software
 17  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 18  */
 19 
 20 #define pr_fmt(fmt)                             "bcmgenet: " fmt
 21 
 22 #include <linux/kernel.h>
 23 #include <linux/module.h>
 24 #include <linux/sched.h>
 25 #include <linux/types.h>
 26 #include <linux/fcntl.h>
 27 #include <linux/interrupt.h>
 28 #include <linux/string.h>
 29 #include <linux/if_ether.h>
 30 #include <linux/init.h>
 31 #include <linux/errno.h>
 32 #include <linux/delay.h>
 33 #include <linux/platform_device.h>
 34 #include <linux/dma-mapping.h>
 35 #include <linux/pm.h>
 36 #include <linux/clk.h>
 37 #include <linux/of.h>
 38 #include <linux/of_address.h>
 39 #include <linux/of_irq.h>
 40 #include <linux/of_net.h>
 41 #include <linux/of_platform.h>
 42 #include <net/arp.h>
 43 
 44 #include <linux/mii.h>
 45 #include <linux/ethtool.h>
 46 #include <linux/netdevice.h>
 47 #include <linux/inetdevice.h>
 48 #include <linux/etherdevice.h>
 49 #include <linux/skbuff.h>
 50 #include <linux/in.h>
 51 #include <linux/ip.h>
 52 #include <linux/ipv6.h>
 53 #include <linux/phy.h>
 54 
 55 #include <asm/unaligned.h>
 56 
 57 #include "bcmgenet.h"
 58 
 59 /* Maximum number of hardware queues, downsized if needed */
 60 #define GENET_MAX_MQ_CNT        4
 61 
 62 /* Default highest priority queue for multi queue support */
 63 #define GENET_Q0_PRIORITY       0
 64 
 65 #define GENET_DEFAULT_BD_CNT    \
 66         (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->bds_cnt)
 67 
 68 #define RX_BUF_LENGTH           2048
 69 #define SKB_ALIGNMENT           32
 70 
 71 /* Tx/Rx DMA register offset, skip 256 descriptors */
 72 #define WORDS_PER_BD(p)         (p->hw_params->words_per_bd)
 73 #define DMA_DESC_SIZE           (WORDS_PER_BD(priv) * sizeof(u32))
 74 
 75 #define GENET_TDMA_REG_OFF      (priv->hw_params->tdma_offset + \
 76                                 TOTAL_DESC * DMA_DESC_SIZE)
 77 
 78 #define GENET_RDMA_REG_OFF      (priv->hw_params->rdma_offset + \
 79                                 TOTAL_DESC * DMA_DESC_SIZE)
 80 
 81 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
 82                                                 void __iomem *d, u32 value)
 83 {
 84         __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
 85 }
 86 
 87 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
 88                                                 void __iomem *d)
 89 {
 90         return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
 91 }
 92 
 93 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
 94                                     void __iomem *d,
 95                                     dma_addr_t addr)
 96 {
 97         __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
 98 
 99         /* Register writes to GISB bus can take couple hundred nanoseconds
100          * and are done for each packet, save these expensive writes unless
101          * the platform is explicitely configured for 64-bits/LPAE.
102          */
103 #ifdef CONFIG_PHYS_ADDR_T_64BIT
104         if (priv->hw_params->flags & GENET_HAS_40BITS)
105                 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
106 #endif
107 }
108 
109 /* Combined address + length/status setter */
110 static inline void dmadesc_set(struct bcmgenet_priv *priv,
111                                 void __iomem *d, dma_addr_t addr, u32 val)
112 {
113         dmadesc_set_length_status(priv, d, val);
114         dmadesc_set_addr(priv, d, addr);
115 }
116 
117 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
118                                           void __iomem *d)
119 {
120         dma_addr_t addr;
121 
122         addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
123 
124         /* Register writes to GISB bus can take couple hundred nanoseconds
125          * and are done for each packet, save these expensive writes unless
126          * the platform is explicitely configured for 64-bits/LPAE.
127          */
128 #ifdef CONFIG_PHYS_ADDR_T_64BIT
129         if (priv->hw_params->flags & GENET_HAS_40BITS)
130                 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
131 #endif
132         return addr;
133 }
134 
135 #define GENET_VER_FMT   "%1d.%1d EPHY: 0x%04x"
136 
137 #define GENET_MSG_DEFAULT       (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
138                                 NETIF_MSG_LINK)
139 
140 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
141 {
142         if (GENET_IS_V1(priv))
143                 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
144         else
145                 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
146 }
147 
148 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
149 {
150         if (GENET_IS_V1(priv))
151                 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
152         else
153                 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
154 }
155 
156 /* These macros are defined to deal with register map change
157  * between GENET1.1 and GENET2. Only those currently being used
158  * by driver are defined.
159  */
160 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
161 {
162         if (GENET_IS_V1(priv))
163                 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
164         else
165                 return __raw_readl(priv->base +
166                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
167 }
168 
169 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
170 {
171         if (GENET_IS_V1(priv))
172                 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
173         else
174                 __raw_writel(val, priv->base +
175                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
176 }
177 
178 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
179 {
180         if (GENET_IS_V1(priv))
181                 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
182         else
183                 return __raw_readl(priv->base +
184                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
185 }
186 
187 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
188 {
189         if (GENET_IS_V1(priv))
190                 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
191         else
192                 __raw_writel(val, priv->base +
193                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
194 }
195 
196 /* RX/TX DMA register accessors */
197 enum dma_reg {
198         DMA_RING_CFG = 0,
199         DMA_CTRL,
200         DMA_STATUS,
201         DMA_SCB_BURST_SIZE,
202         DMA_ARB_CTRL,
203         DMA_PRIORITY,
204         DMA_RING_PRIORITY,
205 };
206 
207 static const u8 bcmgenet_dma_regs_v3plus[] = {
208         [DMA_RING_CFG]          = 0x00,
209         [DMA_CTRL]              = 0x04,
210         [DMA_STATUS]            = 0x08,
211         [DMA_SCB_BURST_SIZE]    = 0x0C,
212         [DMA_ARB_CTRL]          = 0x2C,
213         [DMA_PRIORITY]          = 0x30,
214         [DMA_RING_PRIORITY]     = 0x38,
215 };
216 
217 static const u8 bcmgenet_dma_regs_v2[] = {
218         [DMA_RING_CFG]          = 0x00,
219         [DMA_CTRL]              = 0x04,
220         [DMA_STATUS]            = 0x08,
221         [DMA_SCB_BURST_SIZE]    = 0x0C,
222         [DMA_ARB_CTRL]          = 0x30,
223         [DMA_PRIORITY]          = 0x34,
224         [DMA_RING_PRIORITY]     = 0x3C,
225 };
226 
227 static const u8 bcmgenet_dma_regs_v1[] = {
228         [DMA_CTRL]              = 0x00,
229         [DMA_STATUS]            = 0x04,
230         [DMA_SCB_BURST_SIZE]    = 0x0C,
231         [DMA_ARB_CTRL]          = 0x30,
232         [DMA_PRIORITY]          = 0x34,
233         [DMA_RING_PRIORITY]     = 0x3C,
234 };
235 
236 /* Set at runtime once bcmgenet version is known */
237 static const u8 *bcmgenet_dma_regs;
238 
239 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
240 {
241         return netdev_priv(dev_get_drvdata(dev));
242 }
243 
244 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
245                                         enum dma_reg r)
246 {
247         return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
248                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
249 }
250 
251 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
252                                         u32 val, enum dma_reg r)
253 {
254         __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
255                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
256 }
257 
258 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
259                                         enum dma_reg r)
260 {
261         return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
262                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
263 }
264 
265 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
266                                         u32 val, enum dma_reg r)
267 {
268         __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
269                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
270 }
271 
272 /* RDMA/TDMA ring registers and accessors
273  * we merge the common fields and just prefix with T/D the registers
274  * having different meaning depending on the direction
275  */
276 enum dma_ring_reg {
277         TDMA_READ_PTR = 0,
278         RDMA_WRITE_PTR = TDMA_READ_PTR,
279         TDMA_READ_PTR_HI,
280         RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
281         TDMA_CONS_INDEX,
282         RDMA_PROD_INDEX = TDMA_CONS_INDEX,
283         TDMA_PROD_INDEX,
284         RDMA_CONS_INDEX = TDMA_PROD_INDEX,
285         DMA_RING_BUF_SIZE,
286         DMA_START_ADDR,
287         DMA_START_ADDR_HI,
288         DMA_END_ADDR,
289         DMA_END_ADDR_HI,
290         DMA_MBUF_DONE_THRESH,
291         TDMA_FLOW_PERIOD,
292         RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
293         TDMA_WRITE_PTR,
294         RDMA_READ_PTR = TDMA_WRITE_PTR,
295         TDMA_WRITE_PTR_HI,
296         RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
297 };
298 
299 /* GENET v4 supports 40-bits pointer addressing
300  * for obvious reasons the LO and HI word parts
301  * are contiguous, but this offsets the other
302  * registers.
303  */
304 static const u8 genet_dma_ring_regs_v4[] = {
305         [TDMA_READ_PTR]                 = 0x00,
306         [TDMA_READ_PTR_HI]              = 0x04,
307         [TDMA_CONS_INDEX]               = 0x08,
308         [TDMA_PROD_INDEX]               = 0x0C,
309         [DMA_RING_BUF_SIZE]             = 0x10,
310         [DMA_START_ADDR]                = 0x14,
311         [DMA_START_ADDR_HI]             = 0x18,
312         [DMA_END_ADDR]                  = 0x1C,
313         [DMA_END_ADDR_HI]               = 0x20,
314         [DMA_MBUF_DONE_THRESH]          = 0x24,
315         [TDMA_FLOW_PERIOD]              = 0x28,
316         [TDMA_WRITE_PTR]                = 0x2C,
317         [TDMA_WRITE_PTR_HI]             = 0x30,
318 };
319 
320 static const u8 genet_dma_ring_regs_v123[] = {
321         [TDMA_READ_PTR]                 = 0x00,
322         [TDMA_CONS_INDEX]               = 0x04,
323         [TDMA_PROD_INDEX]               = 0x08,
324         [DMA_RING_BUF_SIZE]             = 0x0C,
325         [DMA_START_ADDR]                = 0x10,
326         [DMA_END_ADDR]                  = 0x14,
327         [DMA_MBUF_DONE_THRESH]          = 0x18,
328         [TDMA_FLOW_PERIOD]              = 0x1C,
329         [TDMA_WRITE_PTR]                = 0x20,
330 };
331 
332 /* Set at runtime once GENET version is known */
333 static const u8 *genet_dma_ring_regs;
334 
335 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
336                                                 unsigned int ring,
337                                                 enum dma_ring_reg r)
338 {
339         return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
340                         (DMA_RING_SIZE * ring) +
341                         genet_dma_ring_regs[r]);
342 }
343 
344 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
345                                                 unsigned int ring,
346                                                 u32 val,
347                                                 enum dma_ring_reg r)
348 {
349         __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
350                         (DMA_RING_SIZE * ring) +
351                         genet_dma_ring_regs[r]);
352 }
353 
354 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
355                                                 unsigned int ring,
356                                                 enum dma_ring_reg r)
357 {
358         return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
359                         (DMA_RING_SIZE * ring) +
360                         genet_dma_ring_regs[r]);
361 }
362 
363 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
364                                                 unsigned int ring,
365                                                 u32 val,
366                                                 enum dma_ring_reg r)
367 {
368         __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
369                         (DMA_RING_SIZE * ring) +
370                         genet_dma_ring_regs[r]);
371 }
372 
373 static int bcmgenet_get_settings(struct net_device *dev,
374                 struct ethtool_cmd *cmd)
375 {
376         struct bcmgenet_priv *priv = netdev_priv(dev);
377 
378         if (!netif_running(dev))
379                 return -EINVAL;
380 
381         if (!priv->phydev)
382                 return -ENODEV;
383 
384         return phy_ethtool_gset(priv->phydev, cmd);
385 }
386 
387 static int bcmgenet_set_settings(struct net_device *dev,
388                 struct ethtool_cmd *cmd)
389 {
390         struct bcmgenet_priv *priv = netdev_priv(dev);
391 
392         if (!netif_running(dev))
393                 return -EINVAL;
394 
395         if (!priv->phydev)
396                 return -ENODEV;
397 
398         return phy_ethtool_sset(priv->phydev, cmd);
399 }
400 
401 static int bcmgenet_set_rx_csum(struct net_device *dev,
402                                 netdev_features_t wanted)
403 {
404         struct bcmgenet_priv *priv = netdev_priv(dev);
405         u32 rbuf_chk_ctrl;
406         bool rx_csum_en;
407 
408         rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
409 
410         rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
411 
412         /* enable rx checksumming */
413         if (rx_csum_en)
414                 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
415         else
416                 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
417         priv->desc_rxchk_en = rx_csum_en;
418 
419         /* If UniMAC forwards CRC, we need to skip over it to get
420          * a valid CHK bit to be set in the per-packet status word
421         */
422         if (rx_csum_en && priv->crc_fwd_en)
423                 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
424         else
425                 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
426 
427         bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
428 
429         return 0;
430 }
431 
432 static int bcmgenet_set_tx_csum(struct net_device *dev,
433                                 netdev_features_t wanted)
434 {
435         struct bcmgenet_priv *priv = netdev_priv(dev);
436         bool desc_64b_en;
437         u32 tbuf_ctrl, rbuf_ctrl;
438 
439         tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
440         rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
441 
442         desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
443 
444         /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
445         if (desc_64b_en) {
446                 tbuf_ctrl |= RBUF_64B_EN;
447                 rbuf_ctrl |= RBUF_64B_EN;
448         } else {
449                 tbuf_ctrl &= ~RBUF_64B_EN;
450                 rbuf_ctrl &= ~RBUF_64B_EN;
451         }
452         priv->desc_64b_en = desc_64b_en;
453 
454         bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
455         bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
456 
457         return 0;
458 }
459 
460 static int bcmgenet_set_features(struct net_device *dev,
461                 netdev_features_t features)
462 {
463         netdev_features_t changed = features ^ dev->features;
464         netdev_features_t wanted = dev->wanted_features;
465         int ret = 0;
466 
467         if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
468                 ret = bcmgenet_set_tx_csum(dev, wanted);
469         if (changed & (NETIF_F_RXCSUM))
470                 ret = bcmgenet_set_rx_csum(dev, wanted);
471 
472         return ret;
473 }
474 
475 static u32 bcmgenet_get_msglevel(struct net_device *dev)
476 {
477         struct bcmgenet_priv *priv = netdev_priv(dev);
478 
479         return priv->msg_enable;
480 }
481 
482 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
483 {
484         struct bcmgenet_priv *priv = netdev_priv(dev);
485 
486         priv->msg_enable = level;
487 }
488 
489 /* standard ethtool support functions. */
490 enum bcmgenet_stat_type {
491         BCMGENET_STAT_NETDEV = -1,
492         BCMGENET_STAT_MIB_RX,
493         BCMGENET_STAT_MIB_TX,
494         BCMGENET_STAT_RUNT,
495         BCMGENET_STAT_MISC,
496 };
497 
498 struct bcmgenet_stats {
499         char stat_string[ETH_GSTRING_LEN];
500         int stat_sizeof;
501         int stat_offset;
502         enum bcmgenet_stat_type type;
503         /* reg offset from UMAC base for misc counters */
504         u16 reg_offset;
505 };
506 
507 #define STAT_NETDEV(m) { \
508         .stat_string = __stringify(m), \
509         .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
510         .stat_offset = offsetof(struct net_device_stats, m), \
511         .type = BCMGENET_STAT_NETDEV, \
512 }
513 
514 #define STAT_GENET_MIB(str, m, _type) { \
515         .stat_string = str, \
516         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
517         .stat_offset = offsetof(struct bcmgenet_priv, m), \
518         .type = _type, \
519 }
520 
521 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
522 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
523 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
524 
525 #define STAT_GENET_MISC(str, m, offset) { \
526         .stat_string = str, \
527         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
528         .stat_offset = offsetof(struct bcmgenet_priv, m), \
529         .type = BCMGENET_STAT_MISC, \
530         .reg_offset = offset, \
531 }
532 
533 
534 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
535  * between the end of TX stats and the beginning of the RX RUNT
536  */
537 #define BCMGENET_STAT_OFFSET    0xc
538 
539 /* Hardware counters must be kept in sync because the order/offset
540  * is important here (order in structure declaration = order in hardware)
541  */
542 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
543         /* general stats */
544         STAT_NETDEV(rx_packets),
545         STAT_NETDEV(tx_packets),
546         STAT_NETDEV(rx_bytes),
547         STAT_NETDEV(tx_bytes),
548         STAT_NETDEV(rx_errors),
549         STAT_NETDEV(tx_errors),
550         STAT_NETDEV(rx_dropped),
551         STAT_NETDEV(tx_dropped),
552         STAT_NETDEV(multicast),
553         /* UniMAC RSV counters */
554         STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
555         STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
556         STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
557         STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
558         STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
559         STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
560         STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
561         STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
562         STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
563         STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
564         STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
565         STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
566         STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
567         STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
568         STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
569         STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
570         STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
571         STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
572         STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
573         STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
574         STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
575         STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
576         STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
577         STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
578         STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
579         STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
580         STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
581         STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
582         STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
583         /* UniMAC TSV counters */
584         STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
585         STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
586         STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
587         STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
588         STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
589         STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
590         STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
591         STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
592         STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
593         STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
594         STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
595         STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
596         STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
597         STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
598         STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
599         STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
600         STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
601         STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
602         STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
603         STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
604         STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
605         STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
606         STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
607         STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
608         STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
609         STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
610         STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
611         STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
612         STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
613         /* UniMAC RUNT counters */
614         STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
615         STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
616         STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
617         STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
618         /* Misc UniMAC counters */
619         STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
620                         UMAC_RBUF_OVFL_CNT),
621         STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
622         STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
623 };
624 
625 #define BCMGENET_STATS_LEN      ARRAY_SIZE(bcmgenet_gstrings_stats)
626 
627 static void bcmgenet_get_drvinfo(struct net_device *dev,
628                 struct ethtool_drvinfo *info)
629 {
630         strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
631         strlcpy(info->version, "v2.0", sizeof(info->version));
632         info->n_stats = BCMGENET_STATS_LEN;
633 
634 }
635 
636 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
637 {
638         switch (string_set) {
639         case ETH_SS_STATS:
640                 return BCMGENET_STATS_LEN;
641         default:
642                 return -EOPNOTSUPP;
643         }
644 }
645 
646 static void bcmgenet_get_strings(struct net_device *dev,
647                                 u32 stringset, u8 *data)
648 {
649         int i;
650 
651         switch (stringset) {
652         case ETH_SS_STATS:
653                 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
654                         memcpy(data + i * ETH_GSTRING_LEN,
655                                 bcmgenet_gstrings_stats[i].stat_string,
656                                 ETH_GSTRING_LEN);
657                 }
658                 break;
659         }
660 }
661 
662 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
663 {
664         int i, j = 0;
665 
666         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
667                 const struct bcmgenet_stats *s;
668                 u8 offset = 0;
669                 u32 val = 0;
670                 char *p;
671 
672                 s = &bcmgenet_gstrings_stats[i];
673                 switch (s->type) {
674                 case BCMGENET_STAT_NETDEV:
675                         continue;
676                 case BCMGENET_STAT_MIB_RX:
677                 case BCMGENET_STAT_MIB_TX:
678                 case BCMGENET_STAT_RUNT:
679                         if (s->type != BCMGENET_STAT_MIB_RX)
680                                 offset = BCMGENET_STAT_OFFSET;
681                         val = bcmgenet_umac_readl(priv, UMAC_MIB_START +
682                                                                 j + offset);
683                         break;
684                 case BCMGENET_STAT_MISC:
685                         val = bcmgenet_umac_readl(priv, s->reg_offset);
686                         /* clear if overflowed */
687                         if (val == ~0)
688                                 bcmgenet_umac_writel(priv, 0, s->reg_offset);
689                         break;
690                 }
691 
692                 j += s->stat_sizeof;
693                 p = (char *)priv + s->stat_offset;
694                 *(u32 *)p = val;
695         }
696 }
697 
698 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
699                                         struct ethtool_stats *stats,
700                                         u64 *data)
701 {
702         struct bcmgenet_priv *priv = netdev_priv(dev);
703         int i;
704 
705         if (netif_running(dev))
706                 bcmgenet_update_mib_counters(priv);
707 
708         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
709                 const struct bcmgenet_stats *s;
710                 char *p;
711 
712                 s = &bcmgenet_gstrings_stats[i];
713                 if (s->type == BCMGENET_STAT_NETDEV)
714                         p = (char *)&dev->stats;
715                 else
716                         p = (char *)priv;
717                 p += s->stat_offset;
718                 data[i] = *(u32 *)p;
719         }
720 }
721 
722 /* standard ethtool support functions. */
723 static struct ethtool_ops bcmgenet_ethtool_ops = {
724         .get_strings            = bcmgenet_get_strings,
725         .get_sset_count         = bcmgenet_get_sset_count,
726         .get_ethtool_stats      = bcmgenet_get_ethtool_stats,
727         .get_settings           = bcmgenet_get_settings,
728         .set_settings           = bcmgenet_set_settings,
729         .get_drvinfo            = bcmgenet_get_drvinfo,
730         .get_link               = ethtool_op_get_link,
731         .get_msglevel           = bcmgenet_get_msglevel,
732         .set_msglevel           = bcmgenet_set_msglevel,
733 };
734 
735 /* Power down the unimac, based on mode. */
736 static void bcmgenet_power_down(struct bcmgenet_priv *priv,
737                                 enum bcmgenet_power_mode mode)
738 {
739         u32 reg;
740 
741         switch (mode) {
742         case GENET_POWER_CABLE_SENSE:
743                 phy_detach(priv->phydev);
744                 break;
745 
746         case GENET_POWER_PASSIVE:
747                 /* Power down LED */
748                 bcmgenet_mii_reset(priv->dev);
749                 if (priv->hw_params->flags & GENET_HAS_EXT) {
750                         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
751                         reg |= (EXT_PWR_DOWN_PHY |
752                                 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
753                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
754                 }
755                 break;
756         default:
757                 break;
758         }
759 }
760 
761 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
762                                 enum bcmgenet_power_mode mode)
763 {
764         u32 reg;
765 
766         if (!(priv->hw_params->flags & GENET_HAS_EXT))
767                 return;
768 
769         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
770 
771         switch (mode) {
772         case GENET_POWER_PASSIVE:
773                 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
774                                 EXT_PWR_DOWN_BIAS);
775                 /* fallthrough */
776         case GENET_POWER_CABLE_SENSE:
777                 /* enable APD */
778                 reg |= EXT_PWR_DN_EN_LD;
779                 break;
780         default:
781                 break;
782         }
783 
784         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
785         bcmgenet_mii_reset(priv->dev);
786 }
787 
788 /* ioctl handle special commands that are not present in ethtool. */
789 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
790 {
791         struct bcmgenet_priv *priv = netdev_priv(dev);
792         int val = 0;
793 
794         if (!netif_running(dev))
795                 return -EINVAL;
796 
797         switch (cmd) {
798         case SIOCGMIIPHY:
799         case SIOCGMIIREG:
800         case SIOCSMIIREG:
801                 if (!priv->phydev)
802                         val = -ENODEV;
803                 else
804                         val = phy_mii_ioctl(priv->phydev, rq, cmd);
805                 break;
806 
807         default:
808                 val = -EINVAL;
809                 break;
810         }
811 
812         return val;
813 }
814 
815 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
816                                          struct bcmgenet_tx_ring *ring)
817 {
818         struct enet_cb *tx_cb_ptr;
819 
820         tx_cb_ptr = ring->cbs;
821         tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
822         tx_cb_ptr->bd_addr = priv->tx_bds + ring->write_ptr * DMA_DESC_SIZE;
823         /* Advancing local write pointer */
824         if (ring->write_ptr == ring->end_ptr)
825                 ring->write_ptr = ring->cb_ptr;
826         else
827                 ring->write_ptr++;
828 
829         return tx_cb_ptr;
830 }
831 
832 /* Simple helper to free a control block's resources */
833 static void bcmgenet_free_cb(struct enet_cb *cb)
834 {
835         dev_kfree_skb_any(cb->skb);
836         cb->skb = NULL;
837         dma_unmap_addr_set(cb, dma_addr, 0);
838 }
839 
840 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_priv *priv,
841                                                   struct bcmgenet_tx_ring *ring)
842 {
843         bcmgenet_intrl2_0_writel(priv,
844                         UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
845                         INTRL2_CPU_MASK_SET);
846 }
847 
848 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_priv *priv,
849                                                  struct bcmgenet_tx_ring *ring)
850 {
851         bcmgenet_intrl2_0_writel(priv,
852                         UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
853                         INTRL2_CPU_MASK_CLEAR);
854 }
855 
856 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_priv *priv,
857                                                 struct bcmgenet_tx_ring *ring)
858 {
859         bcmgenet_intrl2_1_writel(priv,
860                         (1 << ring->index), INTRL2_CPU_MASK_CLEAR);
861         priv->int1_mask &= ~(1 << ring->index);
862 }
863 
864 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_priv *priv,
865                                                 struct bcmgenet_tx_ring *ring)
866 {
867         bcmgenet_intrl2_1_writel(priv,
868                         (1 << ring->index), INTRL2_CPU_MASK_SET);
869         priv->int1_mask |= (1 << ring->index);
870 }
871 
872 /* Unlocked version of the reclaim routine */
873 static void __bcmgenet_tx_reclaim(struct net_device *dev,
874                                 struct bcmgenet_tx_ring *ring)
875 {
876         struct bcmgenet_priv *priv = netdev_priv(dev);
877         int last_tx_cn, last_c_index, num_tx_bds;
878         struct enet_cb *tx_cb_ptr;
879         struct netdev_queue *txq;
880         unsigned int c_index;
881 
882         /* Compute how many buffers are transmited since last xmit call */
883         c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
884         txq = netdev_get_tx_queue(dev, ring->queue);
885 
886         last_c_index = ring->c_index;
887         num_tx_bds = ring->size;
888 
889         c_index &= (num_tx_bds - 1);
890 
891         if (c_index >= last_c_index)
892                 last_tx_cn = c_index - last_c_index;
893         else
894                 last_tx_cn = num_tx_bds - last_c_index + c_index;
895 
896         netif_dbg(priv, tx_done, dev,
897                         "%s ring=%d index=%d last_tx_cn=%d last_index=%d\n",
898                         __func__, ring->index,
899                         c_index, last_tx_cn, last_c_index);
900 
901         /* Reclaim transmitted buffers */
902         while (last_tx_cn-- > 0) {
903                 tx_cb_ptr = ring->cbs + last_c_index;
904                 if (tx_cb_ptr->skb) {
905                         dev->stats.tx_bytes += tx_cb_ptr->skb->len;
906                         dma_unmap_single(&dev->dev,
907                                         dma_unmap_addr(tx_cb_ptr, dma_addr),
908                                         tx_cb_ptr->skb->len,
909                                         DMA_TO_DEVICE);
910                         bcmgenet_free_cb(tx_cb_ptr);
911                 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
912                         dev->stats.tx_bytes +=
913                                 dma_unmap_len(tx_cb_ptr, dma_len);
914                         dma_unmap_page(&dev->dev,
915                                         dma_unmap_addr(tx_cb_ptr, dma_addr),
916                                         dma_unmap_len(tx_cb_ptr, dma_len),
917                                         DMA_TO_DEVICE);
918                         dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
919                 }
920                 dev->stats.tx_packets++;
921                 ring->free_bds += 1;
922 
923                 last_c_index++;
924                 last_c_index &= (num_tx_bds - 1);
925         }
926 
927         if (ring->free_bds > (MAX_SKB_FRAGS + 1))
928                 ring->int_disable(priv, ring);
929 
930         if (netif_tx_queue_stopped(txq))
931                 netif_tx_wake_queue(txq);
932 
933         ring->c_index = c_index;
934 }
935 
936 static void bcmgenet_tx_reclaim(struct net_device *dev,
937                 struct bcmgenet_tx_ring *ring)
938 {
939         unsigned long flags;
940 
941         spin_lock_irqsave(&ring->lock, flags);
942         __bcmgenet_tx_reclaim(dev, ring);
943         spin_unlock_irqrestore(&ring->lock, flags);
944 }
945 
946 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
947 {
948         struct bcmgenet_priv *priv = netdev_priv(dev);
949         int i;
950 
951         if (netif_is_multiqueue(dev)) {
952                 for (i = 0; i < priv->hw_params->tx_queues; i++)
953                         bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
954         }
955 
956         bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
957 }
958 
959 /* Transmits a single SKB (either head of a fragment or a single SKB)
960  * caller must hold priv->lock
961  */
962 static int bcmgenet_xmit_single(struct net_device *dev,
963                                 struct sk_buff *skb,
964                                 u16 dma_desc_flags,
965                                 struct bcmgenet_tx_ring *ring)
966 {
967         struct bcmgenet_priv *priv = netdev_priv(dev);
968         struct device *kdev = &priv->pdev->dev;
969         struct enet_cb *tx_cb_ptr;
970         unsigned int skb_len;
971         dma_addr_t mapping;
972         u32 length_status;
973         int ret;
974 
975         tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
976 
977         if (unlikely(!tx_cb_ptr))
978                 BUG();
979 
980         tx_cb_ptr->skb = skb;
981 
982         skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
983 
984         mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
985         ret = dma_mapping_error(kdev, mapping);
986         if (ret) {
987                 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
988                 dev_kfree_skb(skb);
989                 return ret;
990         }
991 
992         dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
993         dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
994         length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
995                         (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
996                         DMA_TX_APPEND_CRC;
997 
998         if (skb->ip_summed == CHECKSUM_PARTIAL)
999                 length_status |= DMA_TX_DO_CSUM;
1000 
1001         dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1002 
1003         /* Decrement total BD count and advance our write pointer */
1004         ring->free_bds -= 1;
1005         ring->prod_index += 1;
1006         ring->prod_index &= DMA_P_INDEX_MASK;
1007 
1008         return 0;
1009 }
1010 
1011 /* Transmit a SKB fragement */
1012 static int bcmgenet_xmit_frag(struct net_device *dev,
1013                                 skb_frag_t *frag,
1014                                 u16 dma_desc_flags,
1015                                 struct bcmgenet_tx_ring *ring)
1016 {
1017         struct bcmgenet_priv *priv = netdev_priv(dev);
1018         struct device *kdev = &priv->pdev->dev;
1019         struct enet_cb *tx_cb_ptr;
1020         dma_addr_t mapping;
1021         int ret;
1022 
1023         tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1024 
1025         if (unlikely(!tx_cb_ptr))
1026                 BUG();
1027         tx_cb_ptr->skb = NULL;
1028 
1029         mapping = skb_frag_dma_map(kdev, frag, 0,
1030                 skb_frag_size(frag), DMA_TO_DEVICE);
1031         ret = dma_mapping_error(kdev, mapping);
1032         if (ret) {
1033                 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
1034                                 __func__);
1035                 return ret;
1036         }
1037 
1038         dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1039         dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1040 
1041         dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
1042                         (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1043                         (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1044 
1045 
1046         ring->free_bds -= 1;
1047         ring->prod_index += 1;
1048         ring->prod_index &= DMA_P_INDEX_MASK;
1049 
1050         return 0;
1051 }
1052 
1053 /* Reallocate the SKB to put enough headroom in front of it and insert
1054  * the transmit checksum offsets in the descriptors
1055  */
1056 static int bcmgenet_put_tx_csum(struct net_device *dev, struct sk_buff *skb)
1057 {
1058         struct status_64 *status = NULL;
1059         struct sk_buff *new_skb;
1060         u16 offset;
1061         u8 ip_proto;
1062         u16 ip_ver;
1063         u32 tx_csum_info;
1064 
1065         if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1066                 /* If 64 byte status block enabled, must make sure skb has
1067                  * enough headroom for us to insert 64B status block.
1068                  */
1069                 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1070                 dev_kfree_skb(skb);
1071                 if (!new_skb) {
1072                         dev->stats.tx_errors++;
1073                         dev->stats.tx_dropped++;
1074                         return -ENOMEM;
1075                 }
1076                 skb = new_skb;
1077         }
1078 
1079         skb_push(skb, sizeof(*status));
1080         status = (struct status_64 *)skb->data;
1081 
1082         if (skb->ip_summed  == CHECKSUM_PARTIAL) {
1083                 ip_ver = htons(skb->protocol);
1084                 switch (ip_ver) {
1085                 case ETH_P_IP:
1086                         ip_proto = ip_hdr(skb)->protocol;
1087                         break;
1088                 case ETH_P_IPV6:
1089                         ip_proto = ipv6_hdr(skb)->nexthdr;
1090                         break;
1091                 default:
1092                         return 0;
1093                 }
1094 
1095                 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1096                 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1097                                 (offset + skb->csum_offset);
1098 
1099                 /* Set the length valid bit for TCP and UDP and just set
1100                  * the special UDP flag for IPv4, else just set to 0.
1101                  */
1102                 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1103                         tx_csum_info |= STATUS_TX_CSUM_LV;
1104                         if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1105                                 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1106                 } else
1107                         tx_csum_info = 0;
1108 
1109                 status->tx_csum_info = tx_csum_info;
1110         }
1111 
1112         return 0;
1113 }
1114 
1115 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1116 {
1117         struct bcmgenet_priv *priv = netdev_priv(dev);
1118         struct bcmgenet_tx_ring *ring = NULL;
1119         struct netdev_queue *txq;
1120         unsigned long flags = 0;
1121         int nr_frags, index;
1122         u16 dma_desc_flags;
1123         int ret;
1124         int i;
1125 
1126         index = skb_get_queue_mapping(skb);
1127         /* Mapping strategy:
1128          * queue_mapping = 0, unclassified, packet xmited through ring16
1129          * queue_mapping = 1, goes to ring 0. (highest priority queue
1130          * queue_mapping = 2, goes to ring 1.
1131          * queue_mapping = 3, goes to ring 2.
1132          * queue_mapping = 4, goes to ring 3.
1133          */
1134         if (index == 0)
1135                 index = DESC_INDEX;
1136         else
1137                 index -= 1;
1138 
1139         nr_frags = skb_shinfo(skb)->nr_frags;
1140         ring = &priv->tx_rings[index];
1141         txq = netdev_get_tx_queue(dev, ring->queue);
1142 
1143         spin_lock_irqsave(&ring->lock, flags);
1144         if (ring->free_bds <= nr_frags + 1) {
1145                 netif_tx_stop_queue(txq);
1146                 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
1147                                 __func__, index, ring->queue);
1148                 ret = NETDEV_TX_BUSY;
1149                 goto out;
1150         }
1151 
1152         /* set the SKB transmit checksum */
1153         if (priv->desc_64b_en) {
1154                 ret = bcmgenet_put_tx_csum(dev, skb);
1155                 if (ret) {
1156                         ret = NETDEV_TX_OK;
1157                         goto out;
1158                 }
1159         }
1160 
1161         dma_desc_flags = DMA_SOP;
1162         if (nr_frags == 0)
1163                 dma_desc_flags |= DMA_EOP;
1164 
1165         /* Transmit single SKB or head of fragment list */
1166         ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1167         if (ret) {
1168                 ret = NETDEV_TX_OK;
1169                 goto out;
1170         }
1171 
1172         /* xmit fragment */
1173         for (i = 0; i < nr_frags; i++) {
1174                 ret = bcmgenet_xmit_frag(dev,
1175                                 &skb_shinfo(skb)->frags[i],
1176                                 (i == nr_frags - 1) ? DMA_EOP : 0, ring);
1177                 if (ret) {
1178                         ret = NETDEV_TX_OK;
1179                         goto out;
1180                 }
1181         }
1182 
1183         skb_tx_timestamp(skb);
1184 
1185         /* we kept a software copy of how much we should advance the TDMA
1186          * producer index, now write it down to the hardware
1187          */
1188         bcmgenet_tdma_ring_writel(priv, ring->index,
1189                         ring->prod_index, TDMA_PROD_INDEX);
1190 
1191         if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) {
1192                 netif_tx_stop_queue(txq);
1193                 ring->int_enable(priv, ring);
1194         }
1195 
1196 out:
1197         spin_unlock_irqrestore(&ring->lock, flags);
1198 
1199         return ret;
1200 }
1201 
1202 
1203 static int bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1204                                 struct enet_cb *cb)
1205 {
1206         struct device *kdev = &priv->pdev->dev;
1207         struct sk_buff *skb;
1208         dma_addr_t mapping;
1209         int ret;
1210 
1211         skb = netdev_alloc_skb(priv->dev,
1212                                 priv->rx_buf_len + SKB_ALIGNMENT);
1213         if (!skb)
1214                 return -ENOMEM;
1215 
1216         /* a caller did not release this control block */
1217         WARN_ON(cb->skb != NULL);
1218         cb->skb = skb;
1219         mapping = dma_map_single(kdev, skb->data,
1220                         priv->rx_buf_len, DMA_FROM_DEVICE);
1221         ret = dma_mapping_error(kdev, mapping);
1222         if (ret) {
1223                 bcmgenet_free_cb(cb);
1224                 netif_err(priv, rx_err, priv->dev,
1225                                 "%s DMA map failed\n", __func__);
1226                 return ret;
1227         }
1228 
1229         dma_unmap_addr_set(cb, dma_addr, mapping);
1230         /* assign packet, prepare descriptor, and advance pointer */
1231 
1232         dmadesc_set_addr(priv, priv->rx_bd_assign_ptr, mapping);
1233 
1234         /* turn on the newly assigned BD for DMA to use */
1235         priv->rx_bd_assign_index++;
1236         priv->rx_bd_assign_index &= (priv->num_rx_bds - 1);
1237 
1238         priv->rx_bd_assign_ptr = priv->rx_bds +
1239                 (priv->rx_bd_assign_index * DMA_DESC_SIZE);
1240 
1241         return 0;
1242 }
1243 
1244 /* bcmgenet_desc_rx - descriptor based rx process.
1245  * this could be called from bottom half, or from NAPI polling method.
1246  */
1247 static unsigned int bcmgenet_desc_rx(struct bcmgenet_priv *priv,
1248                                      unsigned int budget)
1249 {
1250         struct net_device *dev = priv->dev;
1251         struct enet_cb *cb;
1252         struct sk_buff *skb;
1253         u32 dma_length_status;
1254         unsigned long dma_flag;
1255         int len, err;
1256         unsigned int rxpktprocessed = 0, rxpkttoprocess;
1257         unsigned int p_index;
1258         unsigned int chksum_ok = 0;
1259 
1260         p_index = bcmgenet_rdma_ring_readl(priv,
1261                         DESC_INDEX, RDMA_PROD_INDEX);
1262         p_index &= DMA_P_INDEX_MASK;
1263 
1264         if (p_index < priv->rx_c_index)
1265                 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) -
1266                         priv->rx_c_index + p_index;
1267         else
1268                 rxpkttoprocess = p_index - priv->rx_c_index;
1269 
1270         netif_dbg(priv, rx_status, dev,
1271                 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1272 
1273         while ((rxpktprocessed < rxpkttoprocess) &&
1274                         (rxpktprocessed < budget)) {
1275 
1276                 /* Unmap the packet contents such that we can use the
1277                  * RSV from the 64 bytes descriptor when enabled and save
1278                  * a 32-bits register read
1279                  */
1280                 cb = &priv->rx_cbs[priv->rx_read_ptr];
1281                 skb = cb->skb;
1282                 dma_unmap_single(&dev->dev, dma_unmap_addr(cb, dma_addr),
1283                                 priv->rx_buf_len, DMA_FROM_DEVICE);
1284 
1285                 if (!priv->desc_64b_en) {
1286                         dma_length_status = dmadesc_get_length_status(priv,
1287                                                         priv->rx_bds +
1288                                                         (priv->rx_read_ptr *
1289                                                          DMA_DESC_SIZE));
1290                 } else {
1291                         struct status_64 *status;
1292                         status = (struct status_64 *)skb->data;
1293                         dma_length_status = status->length_status;
1294                 }
1295 
1296                 /* DMA flags and length are still valid no matter how
1297                  * we got the Receive Status Vector (64B RSB or register)
1298                  */
1299                 dma_flag = dma_length_status & 0xffff;
1300                 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1301 
1302                 netif_dbg(priv, rx_status, dev,
1303                         "%s: p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1304                         __func__, p_index, priv->rx_c_index, priv->rx_read_ptr,
1305                         dma_length_status);
1306 
1307                 rxpktprocessed++;
1308 
1309                 priv->rx_read_ptr++;
1310                 priv->rx_read_ptr &= (priv->num_rx_bds - 1);
1311 
1312                 /* out of memory, just drop packets at the hardware level */
1313                 if (unlikely(!skb)) {
1314                         dev->stats.rx_dropped++;
1315                         dev->stats.rx_errors++;
1316                         goto refill;
1317                 }
1318 
1319                 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1320                         netif_err(priv, rx_status, dev,
1321                                         "Droping fragmented packet!\n");
1322                         dev->stats.rx_dropped++;
1323                         dev->stats.rx_errors++;
1324                         dev_kfree_skb_any(cb->skb);
1325                         cb->skb = NULL;
1326                         goto refill;
1327                 }
1328                 /* report errors */
1329                 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1330                                                 DMA_RX_OV |
1331                                                 DMA_RX_NO |
1332                                                 DMA_RX_LG |
1333                                                 DMA_RX_RXER))) {
1334                         netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1335                                                 (unsigned int)dma_flag);
1336                         if (dma_flag & DMA_RX_CRC_ERROR)
1337                                 dev->stats.rx_crc_errors++;
1338                         if (dma_flag & DMA_RX_OV)
1339                                 dev->stats.rx_over_errors++;
1340                         if (dma_flag & DMA_RX_NO)
1341                                 dev->stats.rx_frame_errors++;
1342                         if (dma_flag & DMA_RX_LG)
1343                                 dev->stats.rx_length_errors++;
1344                         dev->stats.rx_dropped++;
1345                         dev->stats.rx_errors++;
1346 
1347                         /* discard the packet and advance consumer index.*/
1348                         dev_kfree_skb_any(cb->skb);
1349                         cb->skb = NULL;
1350                         goto refill;
1351                 } /* error packet */
1352 
1353                 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1354                                 priv->desc_rxchk_en;
1355 
1356                 skb_put(skb, len);
1357                 if (priv->desc_64b_en) {
1358                         skb_pull(skb, 64);
1359                         len -= 64;
1360                 }
1361 
1362                 if (likely(chksum_ok))
1363                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1364 
1365                 /* remove hardware 2bytes added for IP alignment */
1366                 skb_pull(skb, 2);
1367                 len -= 2;
1368 
1369                 if (priv->crc_fwd_en) {
1370                         skb_trim(skb, len - ETH_FCS_LEN);
1371                         len -= ETH_FCS_LEN;
1372                 }
1373 
1374                 /*Finish setting up the received SKB and send it to the kernel*/
1375                 skb->protocol = eth_type_trans(skb, priv->dev);
1376                 dev->stats.rx_packets++;
1377                 dev->stats.rx_bytes += len;
1378                 if (dma_flag & DMA_RX_MULT)
1379                         dev->stats.multicast++;
1380 
1381                 /* Notify kernel */
1382                 napi_gro_receive(&priv->napi, skb);
1383                 cb->skb = NULL;
1384                 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1385 
1386                 /* refill RX path on the current control block */
1387 refill:
1388                 err = bcmgenet_rx_refill(priv, cb);
1389                 if (err)
1390                         netif_err(priv, rx_err, dev, "Rx refill failed\n");
1391         }
1392 
1393         return rxpktprocessed;
1394 }
1395 
1396 /* Assign skb to RX DMA descriptor. */
1397 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv)
1398 {
1399         struct enet_cb *cb;
1400         int ret = 0;
1401         int i;
1402 
1403         netif_dbg(priv, hw, priv->dev, "%s:\n", __func__);
1404 
1405         /* loop here for each buffer needing assign */
1406         for (i = 0; i < priv->num_rx_bds; i++) {
1407                 cb = &priv->rx_cbs[priv->rx_bd_assign_index];
1408                 if (cb->skb)
1409                         continue;
1410 
1411                 /* set the DMA descriptor length once and for all
1412                  * it will only change if we support dynamically sizing
1413                  * priv->rx_buf_len, but we do not
1414                  */
1415                 dmadesc_set_length_status(priv, priv->rx_bd_assign_ptr,
1416                                 priv->rx_buf_len << DMA_BUFLENGTH_SHIFT);
1417 
1418                 ret = bcmgenet_rx_refill(priv, cb);
1419                 if (ret)
1420                         break;
1421 
1422         }
1423 
1424         return ret;
1425 }
1426 
1427 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1428 {
1429         struct enet_cb *cb;
1430         int i;
1431 
1432         for (i = 0; i < priv->num_rx_bds; i++) {
1433                 cb = &priv->rx_cbs[i];
1434 
1435                 if (dma_unmap_addr(cb, dma_addr)) {
1436                         dma_unmap_single(&priv->dev->dev,
1437                                         dma_unmap_addr(cb, dma_addr),
1438                                         priv->rx_buf_len, DMA_FROM_DEVICE);
1439                         dma_unmap_addr_set(cb, dma_addr, 0);
1440                 }
1441 
1442                 if (cb->skb)
1443                         bcmgenet_free_cb(cb);
1444         }
1445 }
1446 
1447 static int reset_umac(struct bcmgenet_priv *priv)
1448 {
1449         struct device *kdev = &priv->pdev->dev;
1450         unsigned int timeout = 0;
1451         u32 reg;
1452 
1453         /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1454         bcmgenet_rbuf_ctrl_set(priv, 0);
1455         udelay(10);
1456 
1457         /* disable MAC while updating its registers */
1458         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1459 
1460         /* issue soft reset, wait for it to complete */
1461         bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1462         while (timeout++ < 1000) {
1463                 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1464                 if (!(reg & CMD_SW_RESET))
1465                         return 0;
1466 
1467                 udelay(1);
1468         }
1469 
1470         if (timeout == 1000) {
1471                 dev_err(kdev,
1472                         "timeout waiting for MAC to come out of resetn\n");
1473                 return -ETIMEDOUT;
1474         }
1475 
1476         return 0;
1477 }
1478 
1479 static int init_umac(struct bcmgenet_priv *priv)
1480 {
1481         struct device *kdev = &priv->pdev->dev;
1482         int ret;
1483         u32 reg, cpu_mask_clear;
1484 
1485         dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1486 
1487         ret = reset_umac(priv);
1488         if (ret)
1489                 return ret;
1490 
1491         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1492         /* clear tx/rx counter */
1493         bcmgenet_umac_writel(priv,
1494                 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, UMAC_MIB_CTRL);
1495         bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1496 
1497         bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1498 
1499         /* init rx registers, enable ip header optimization */
1500         reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1501         reg |= RBUF_ALIGN_2B;
1502         bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1503 
1504         if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1505                 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1506 
1507         /* Mask all interrupts.*/
1508         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1509         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1510         bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1511 
1512         cpu_mask_clear = UMAC_IRQ_RXDMA_BDONE;
1513 
1514         dev_dbg(kdev, "%s:Enabling RXDMA_BDONE interrupt\n", __func__);
1515 
1516         /* Monitor cable plug/unpluged event for internal PHY */
1517         if (phy_is_internal(priv->phydev))
1518                 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
1519         else if (priv->ext_phy)
1520                 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
1521         else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1522                 reg = bcmgenet_bp_mc_get(priv);
1523                 reg |= BIT(priv->hw_params->bp_in_en_shift);
1524 
1525                 /* bp_mask: back pressure mask */
1526                 if (netif_is_multiqueue(priv->dev))
1527                         reg |= priv->hw_params->bp_in_mask;
1528                 else
1529                         reg &= ~priv->hw_params->bp_in_mask;
1530                 bcmgenet_bp_mc_set(priv, reg);
1531         }
1532 
1533         /* Enable MDIO interrupts on GENET v3+ */
1534         if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1535                 cpu_mask_clear |= UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR;
1536 
1537         bcmgenet_intrl2_0_writel(priv, cpu_mask_clear,
1538                 INTRL2_CPU_MASK_CLEAR);
1539 
1540         /* Enable rx/tx engine.*/
1541         dev_dbg(kdev, "done init umac\n");
1542 
1543         return 0;
1544 }
1545 
1546 /* Initialize all house-keeping variables for a TX ring, along
1547  * with corresponding hardware registers
1548  */
1549 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1550                                   unsigned int index, unsigned int size,
1551                                   unsigned int write_ptr, unsigned int end_ptr)
1552 {
1553         struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1554         u32 words_per_bd = WORDS_PER_BD(priv);
1555         u32 flow_period_val = 0;
1556         unsigned int first_bd;
1557 
1558         spin_lock_init(&ring->lock);
1559         ring->index = index;
1560         if (index == DESC_INDEX) {
1561                 ring->queue = 0;
1562                 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1563                 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1564         } else {
1565                 ring->queue = index + 1;
1566                 ring->int_enable = bcmgenet_tx_ring_int_enable;
1567                 ring->int_disable = bcmgenet_tx_ring_int_disable;
1568         }
1569         ring->cbs = priv->tx_cbs + write_ptr;
1570         ring->size = size;
1571         ring->c_index = 0;
1572         ring->free_bds = size;
1573         ring->write_ptr = write_ptr;
1574         ring->cb_ptr = write_ptr;
1575         ring->end_ptr = end_ptr - 1;
1576         ring->prod_index = 0;
1577 
1578         /* Set flow period for ring != 16 */
1579         if (index != DESC_INDEX)
1580                 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1581 
1582         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1583         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1584         bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1585         /* Disable rate control for now */
1586         bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
1587                         TDMA_FLOW_PERIOD);
1588         /* Unclassified traffic goes to ring 16 */
1589         bcmgenet_tdma_ring_writel(priv, index,
1590                         ((size << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH),
1591                         DMA_RING_BUF_SIZE);
1592 
1593         first_bd = write_ptr;
1594 
1595         /* Set start and end address, read and write pointers */
1596         bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
1597                         DMA_START_ADDR);
1598         bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
1599                         TDMA_READ_PTR);
1600         bcmgenet_tdma_ring_writel(priv, index, first_bd,
1601                         TDMA_WRITE_PTR);
1602         bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
1603                         DMA_END_ADDR);
1604 }
1605 
1606 /* Initialize a RDMA ring */
1607 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
1608                                   unsigned int index, unsigned int size)
1609 {
1610         u32 words_per_bd = WORDS_PER_BD(priv);
1611         int ret;
1612 
1613         priv->num_rx_bds = TOTAL_DESC;
1614         priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
1615         priv->rx_bd_assign_ptr = priv->rx_bds;
1616         priv->rx_bd_assign_index = 0;
1617         priv->rx_c_index = 0;
1618         priv->rx_read_ptr = 0;
1619         priv->rx_cbs = kzalloc(priv->num_rx_bds * sizeof(struct enet_cb),
1620                                 GFP_KERNEL);
1621         if (!priv->rx_cbs)
1622                 return -ENOMEM;
1623 
1624         ret = bcmgenet_alloc_rx_buffers(priv);
1625         if (ret) {
1626                 kfree(priv->rx_cbs);
1627                 return ret;
1628         }
1629 
1630         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_WRITE_PTR);
1631         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
1632         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
1633         bcmgenet_rdma_ring_writel(priv, index,
1634                 ((size << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH),
1635                 DMA_RING_BUF_SIZE);
1636         bcmgenet_rdma_ring_writel(priv, index, 0, DMA_START_ADDR);
1637         bcmgenet_rdma_ring_writel(priv, index,
1638                 words_per_bd * size - 1, DMA_END_ADDR);
1639         bcmgenet_rdma_ring_writel(priv, index,
1640                         (DMA_FC_THRESH_LO << DMA_XOFF_THRESHOLD_SHIFT) |
1641                         DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
1642         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_READ_PTR);
1643 
1644         return ret;
1645 }
1646 
1647 /* init multi xmit queues, only available for GENET2+
1648  * the queue is partitioned as follows:
1649  *
1650  * queue 0 - 3 is priority based, each one has 32 descriptors,
1651  * with queue 0 being the highest priority queue.
1652  *
1653  * queue 16 is the default tx queue with GENET_DEFAULT_BD_CNT
1654  * descriptors: 256 - (number of tx queues * bds per queues) = 128
1655  * descriptors.
1656  *
1657  * The transmit control block pool is then partitioned as following:
1658  * - tx_cbs[0...127] are for queue 16
1659  * - tx_ring_cbs[0] points to tx_cbs[128..159]
1660  * - tx_ring_cbs[1] points to tx_cbs[160..191]
1661  * - tx_ring_cbs[2] points to tx_cbs[192..223]
1662  * - tx_ring_cbs[3] points to tx_cbs[224..255]
1663  */
1664 static void bcmgenet_init_multiq(struct net_device *dev)
1665 {
1666         struct bcmgenet_priv *priv = netdev_priv(dev);
1667         unsigned int i, dma_enable;
1668         u32 reg, dma_ctrl, ring_cfg = 0, dma_priority = 0;
1669 
1670         if (!netif_is_multiqueue(dev)) {
1671                 netdev_warn(dev, "called with non multi queue aware HW\n");
1672                 return;
1673         }
1674 
1675         dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
1676         dma_enable = dma_ctrl & DMA_EN;
1677         dma_ctrl &= ~DMA_EN;
1678         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1679 
1680         /* Enable strict priority arbiter mode */
1681         bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
1682 
1683         for (i = 0; i < priv->hw_params->tx_queues; i++) {
1684                 /* first 64 tx_cbs are reserved for default tx queue
1685                  * (ring 16)
1686                  */
1687                 bcmgenet_init_tx_ring(priv, i, priv->hw_params->bds_cnt,
1688                                         i * priv->hw_params->bds_cnt,
1689                                         (i + 1) * priv->hw_params->bds_cnt);
1690 
1691                 /* Configure ring as decriptor ring and setup priority */
1692                 ring_cfg |= 1 << i;
1693                 dma_priority |= ((GENET_Q0_PRIORITY + i) <<
1694                                 (GENET_MAX_MQ_CNT + 1) * i);
1695                 dma_ctrl |= 1 << (i + DMA_RING_BUF_EN_SHIFT);
1696         }
1697 
1698         /* Enable rings */
1699         reg = bcmgenet_tdma_readl(priv, DMA_RING_CFG);
1700         reg |= ring_cfg;
1701         bcmgenet_tdma_writel(priv, reg, DMA_RING_CFG);
1702 
1703         /* Use configured rings priority and set ring #16 priority */
1704         reg = bcmgenet_tdma_readl(priv, DMA_RING_PRIORITY);
1705         reg |= ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 20);
1706         reg |= dma_priority;
1707         bcmgenet_tdma_writel(priv, reg, DMA_PRIORITY);
1708 
1709         /* Configure ring as descriptor ring and re-enable DMA if enabled */
1710         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1711         reg |= dma_ctrl;
1712         if (dma_enable)
1713                 reg |= DMA_EN;
1714         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1715 }
1716 
1717 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1718 {
1719         int i;
1720 
1721         /* disable DMA */
1722         bcmgenet_rdma_writel(priv, 0, DMA_CTRL);
1723         bcmgenet_tdma_writel(priv, 0, DMA_CTRL);
1724 
1725         for (i = 0; i < priv->num_tx_bds; i++) {
1726                 if (priv->tx_cbs[i].skb != NULL) {
1727                         dev_kfree_skb(priv->tx_cbs[i].skb);
1728                         priv->tx_cbs[i].skb = NULL;
1729                 }
1730         }
1731 
1732         bcmgenet_free_rx_buffers(priv);
1733         kfree(priv->rx_cbs);
1734         kfree(priv->tx_cbs);
1735 }
1736 
1737 /* init_edma: Initialize DMA control register */
1738 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
1739 {
1740         int ret;
1741 
1742         netif_dbg(priv, hw, priv->dev, "bcmgenet: init_edma\n");
1743 
1744         /* by default, enable ring 16 (descriptor based) */
1745         ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, TOTAL_DESC);
1746         if (ret) {
1747                 netdev_err(priv->dev, "failed to initialize RX ring\n");
1748                 return ret;
1749         }
1750 
1751         /* init rDma */
1752         bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1753 
1754         /* Init tDma */
1755         bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1756 
1757         /* Initialize commont TX ring structures */
1758         priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
1759         priv->num_tx_bds = TOTAL_DESC;
1760         priv->tx_cbs = kzalloc(priv->num_tx_bds * sizeof(struct enet_cb),
1761                                 GFP_KERNEL);
1762         if (!priv->tx_cbs) {
1763                 bcmgenet_fini_dma(priv);
1764                 return -ENOMEM;
1765         }
1766 
1767         /* initialize multi xmit queue */
1768         bcmgenet_init_multiq(priv->dev);
1769 
1770         /* initialize special ring 16 */
1771         bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_DEFAULT_BD_CNT,
1772                         priv->hw_params->tx_queues * priv->hw_params->bds_cnt,
1773                         TOTAL_DESC);
1774 
1775         return 0;
1776 }
1777 
1778 /* NAPI polling method*/
1779 static int bcmgenet_poll(struct napi_struct *napi, int budget)
1780 {
1781         struct bcmgenet_priv *priv = container_of(napi,
1782                         struct bcmgenet_priv, napi);
1783         unsigned int work_done;
1784 
1785         /* tx reclaim */
1786         bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
1787 
1788         work_done = bcmgenet_desc_rx(priv, budget);
1789 
1790         /* Advancing our consumer index*/
1791         priv->rx_c_index += work_done;
1792         priv->rx_c_index &= DMA_C_INDEX_MASK;
1793         bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
1794                                 priv->rx_c_index, RDMA_CONS_INDEX);
1795         if (work_done < budget) {
1796                 napi_complete(napi);
1797                 bcmgenet_intrl2_0_writel(priv,
1798                         UMAC_IRQ_RXDMA_BDONE, INTRL2_CPU_MASK_CLEAR);
1799         }
1800 
1801         return work_done;
1802 }
1803 
1804 /* Interrupt bottom half */
1805 static void bcmgenet_irq_task(struct work_struct *work)
1806 {
1807         struct bcmgenet_priv *priv = container_of(
1808                         work, struct bcmgenet_priv, bcmgenet_irq_work);
1809 
1810         netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
1811 
1812         /* Link UP/DOWN event */
1813         if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
1814                 (priv->irq0_stat & (UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN))) {
1815                 phy_mac_interrupt(priv->phydev,
1816                         priv->irq0_stat & UMAC_IRQ_LINK_UP);
1817                 priv->irq0_stat &= ~(UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN);
1818         }
1819 }
1820 
1821 /* bcmgenet_isr1: interrupt handler for ring buffer. */
1822 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
1823 {
1824         struct bcmgenet_priv *priv = dev_id;
1825         unsigned int index;
1826 
1827         /* Save irq status for bottom-half processing. */
1828         priv->irq1_stat =
1829                 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
1830                 ~priv->int1_mask;
1831         /* clear inerrupts*/
1832         bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
1833 
1834         netif_dbg(priv, intr, priv->dev,
1835                 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
1836         /* Check the MBDONE interrupts.
1837          * packet is done, reclaim descriptors
1838          */
1839         if (priv->irq1_stat & 0x0000ffff) {
1840                 index = 0;
1841                 for (index = 0; index < 16; index++) {
1842                         if (priv->irq1_stat & (1 << index))
1843                                 bcmgenet_tx_reclaim(priv->dev,
1844                                                 &priv->tx_rings[index]);
1845                 }
1846         }
1847         return IRQ_HANDLED;
1848 }
1849 
1850 /* bcmgenet_isr0: Handle various interrupts. */
1851 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
1852 {
1853         struct bcmgenet_priv *priv = dev_id;
1854 
1855         /* Save irq status for bottom-half processing. */
1856         priv->irq0_stat =
1857                 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
1858                 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
1859         /* clear inerrupts*/
1860         bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
1861 
1862         netif_dbg(priv, intr, priv->dev,
1863                 "IRQ=0x%x\n", priv->irq0_stat);
1864 
1865         if (priv->irq0_stat & (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE)) {
1866                 /* We use NAPI(software interrupt throttling, if
1867                  * Rx Descriptor throttling is not used.
1868                  * Disable interrupt, will be enabled in the poll method.
1869                  */
1870                 if (likely(napi_schedule_prep(&priv->napi))) {
1871                         bcmgenet_intrl2_0_writel(priv,
1872                                 UMAC_IRQ_RXDMA_BDONE, INTRL2_CPU_MASK_SET);
1873                         __napi_schedule(&priv->napi);
1874                 }
1875         }
1876         if (priv->irq0_stat &
1877                         (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE)) {
1878                 /* Tx reclaim */
1879                 bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
1880         }
1881         if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
1882                                 UMAC_IRQ_PHY_DET_F |
1883                                 UMAC_IRQ_LINK_UP |
1884                                 UMAC_IRQ_LINK_DOWN |
1885                                 UMAC_IRQ_HFB_SM |
1886                                 UMAC_IRQ_HFB_MM |
1887                                 UMAC_IRQ_MPD_R)) {
1888                 /* all other interested interrupts handled in bottom half */
1889                 schedule_work(&priv->bcmgenet_irq_work);
1890         }
1891 
1892         if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
1893                 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1894                 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1895                 wake_up(&priv->wq);
1896         }
1897 
1898         return IRQ_HANDLED;
1899 }
1900 
1901 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
1902 {
1903         u32 reg;
1904 
1905         reg = bcmgenet_rbuf_ctrl_get(priv);
1906         reg |= BIT(1);
1907         bcmgenet_rbuf_ctrl_set(priv, reg);
1908         udelay(10);
1909 
1910         reg &= ~BIT(1);
1911         bcmgenet_rbuf_ctrl_set(priv, reg);
1912         udelay(10);
1913 }
1914 
1915 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
1916                                   unsigned char *addr)
1917 {
1918         bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
1919                         (addr[2] << 8) | addr[3], UMAC_MAC0);
1920         bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
1921 }
1922 
1923 static int bcmgenet_wol_resume(struct bcmgenet_priv *priv)
1924 {
1925         int ret;
1926 
1927         /* From WOL-enabled suspend, switch to regular clock */
1928         clk_disable(priv->clk_wol);
1929         /* init umac registers to synchronize s/w with h/w */
1930         ret = init_umac(priv);
1931         if (ret)
1932                 return ret;
1933 
1934         phy_init_hw(priv->phydev);
1935         /* Speed settings must be restored */
1936         bcmgenet_mii_config(priv->dev);
1937 
1938         return 0;
1939 }
1940 
1941 /* Returns a reusable dma control register value */
1942 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
1943 {
1944         u32 reg;
1945         u32 dma_ctrl;
1946 
1947         /* disable DMA */
1948         dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
1949         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1950         reg &= ~dma_ctrl;
1951         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1952 
1953         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
1954         reg &= ~dma_ctrl;
1955         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
1956 
1957         bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
1958         udelay(10);
1959         bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
1960 
1961         return dma_ctrl;
1962 }
1963 
1964 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
1965 {
1966         u32 reg;
1967 
1968         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
1969         reg |= dma_ctrl;
1970         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
1971 
1972         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1973         reg |= dma_ctrl;
1974         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1975 }
1976 
1977 static int bcmgenet_open(struct net_device *dev)
1978 {
1979         struct bcmgenet_priv *priv = netdev_priv(dev);
1980         unsigned long dma_ctrl;
1981         u32 reg;
1982         int ret;
1983 
1984         netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
1985 
1986         /* Turn on the clock */
1987         if (!IS_ERR(priv->clk))
1988                 clk_prepare_enable(priv->clk);
1989 
1990         /* take MAC out of reset */
1991         bcmgenet_umac_reset(priv);
1992 
1993         ret = init_umac(priv);
1994         if (ret)
1995                 goto err_clk_disable;
1996 
1997         /* disable ethernet MAC while updating its registers */
1998         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1999         reg &= ~(CMD_TX_EN | CMD_RX_EN);
2000         bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2001 
2002         bcmgenet_set_hw_addr(priv, dev->dev_addr);
2003 
2004         if (priv->wol_enabled) {
2005                 ret = bcmgenet_wol_resume(priv);
2006                 if (ret)
2007                         return ret;
2008         }
2009 
2010         if (phy_is_internal(priv->phydev)) {
2011                 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2012                 reg |= EXT_ENERGY_DET_MASK;
2013                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2014         }
2015 
2016         /* Disable RX/TX DMA and flush TX queues */
2017         dma_ctrl = bcmgenet_dma_disable(priv);
2018 
2019         /* Reinitialize TDMA and RDMA and SW housekeeping */
2020         ret = bcmgenet_init_dma(priv);
2021         if (ret) {
2022                 netdev_err(dev, "failed to initialize DMA\n");
2023                 goto err_fini_dma;
2024         }
2025 
2026         /* Always enable ring 16 - descriptor ring */
2027         bcmgenet_enable_dma(priv, dma_ctrl);
2028 
2029         ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2030                         dev->name, priv);
2031         if (ret < 0) {
2032                 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2033                 goto err_fini_dma;
2034         }
2035 
2036         ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2037                                 dev->name, priv);
2038         if (ret < 0) {
2039                 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2040                 goto err_irq0;
2041         }
2042 
2043         /* Start the network engine */
2044         napi_enable(&priv->napi);
2045 
2046         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2047         reg |= (CMD_TX_EN | CMD_RX_EN);
2048         bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2049 
2050         /* Make sure we reflect the value of CRC_CMD_FWD */
2051         priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2052 
2053         device_set_wakeup_capable(&dev->dev, 1);
2054 
2055         if (phy_is_internal(priv->phydev))
2056                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2057 
2058         netif_tx_start_all_queues(dev);
2059 
2060         phy_start(priv->phydev);
2061 
2062         return 0;
2063 
2064 err_irq0:
2065         free_irq(priv->irq0, dev);
2066 err_fini_dma:
2067         bcmgenet_fini_dma(priv);
2068 err_clk_disable:
2069         if (!IS_ERR(priv->clk))
2070                 clk_disable_unprepare(priv->clk);
2071         return ret;
2072 }
2073 
2074 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2075 {
2076         int ret = 0;
2077         int timeout = 0;
2078         u32 reg;
2079 
2080         /* Disable TDMA to stop add more frames in TX DMA */
2081         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2082         reg &= ~DMA_EN;
2083         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2084 
2085         /* Check TDMA status register to confirm TDMA is disabled */
2086         while (timeout++ < DMA_TIMEOUT_VAL) {
2087                 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2088                 if (reg & DMA_DISABLED)
2089                         break;
2090 
2091                 udelay(1);
2092         }
2093 
2094         if (timeout == DMA_TIMEOUT_VAL) {
2095                 netdev_warn(priv->dev,
2096                         "Timed out while disabling TX DMA\n");
2097                 ret = -ETIMEDOUT;
2098         }
2099 
2100         /* Wait 10ms for packet drain in both tx and rx dma */
2101         usleep_range(10000, 20000);
2102 
2103         /* Disable RDMA */
2104         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2105         reg &= ~DMA_EN;
2106         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2107 
2108         timeout = 0;
2109         /* Check RDMA status register to confirm RDMA is disabled */
2110         while (timeout++ < DMA_TIMEOUT_VAL) {
2111                 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2112                 if (reg & DMA_DISABLED)
2113                         break;
2114 
2115                 udelay(1);
2116         }
2117 
2118         if (timeout == DMA_TIMEOUT_VAL) {
2119                 netdev_warn(priv->dev,
2120                         "Timed out while disabling RX DMA\n");
2121                         ret = -ETIMEDOUT;
2122         }
2123 
2124         return ret;
2125 }
2126 
2127 static int bcmgenet_close(struct net_device *dev)
2128 {
2129         struct bcmgenet_priv *priv = netdev_priv(dev);
2130         int ret;
2131         u32 reg;
2132 
2133         netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2134 
2135         phy_stop(priv->phydev);
2136 
2137         /* Disable MAC receive */
2138         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2139         reg &= ~CMD_RX_EN;
2140         bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2141 
2142         netif_tx_stop_all_queues(dev);
2143 
2144         ret = bcmgenet_dma_teardown(priv);
2145         if (ret)
2146                 return ret;
2147 
2148         /* Disable MAC transmit. TX DMA disabled have to done before this */
2149         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2150         reg &= ~CMD_TX_EN;
2151         bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2152 
2153         napi_disable(&priv->napi);
2154 
2155         /* tx reclaim */
2156         bcmgenet_tx_reclaim_all(dev);
2157         bcmgenet_fini_dma(priv);
2158 
2159         free_irq(priv->irq0, priv);
2160         free_irq(priv->irq1, priv);
2161 
2162         /* Wait for pending work items to complete - we are stopping
2163          * the clock now. Since interrupts are disabled, no new work
2164          * will be scheduled.
2165          */
2166         cancel_work_sync(&priv->bcmgenet_irq_work);
2167 
2168         if (phy_is_internal(priv->phydev))
2169                 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2170 
2171         if (priv->wol_enabled)
2172                 clk_enable(priv->clk_wol);
2173 
2174         if (!IS_ERR(priv->clk))
2175                 clk_disable_unprepare(priv->clk);
2176 
2177         return 0;
2178 }
2179 
2180 static void bcmgenet_timeout(struct net_device *dev)
2181 {
2182         struct bcmgenet_priv *priv = netdev_priv(dev);
2183 
2184         netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2185 
2186         dev->trans_start = jiffies;
2187 
2188         dev->stats.tx_errors++;
2189 
2190         netif_tx_wake_all_queues(dev);
2191 }
2192 
2193 #define MAX_MC_COUNT    16
2194 
2195 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2196                                          unsigned char *addr,
2197                                          int *i,
2198                                          int *mc)
2199 {
2200         u32 reg;
2201 
2202         bcmgenet_umac_writel(priv,
2203                         addr[0] << 8 | addr[1], UMAC_MDF_ADDR + (*i * 4));
2204         bcmgenet_umac_writel(priv,
2205                         addr[2] << 24 | addr[3] << 16 |
2206                         addr[4] << 8 | addr[5],
2207                         UMAC_MDF_ADDR + ((*i + 1) * 4));
2208         reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2209         reg |= (1 << (MAX_MC_COUNT - *mc));
2210         bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2211         *i += 2;
2212         (*mc)++;
2213 }
2214 
2215 static void bcmgenet_set_rx_mode(struct net_device *dev)
2216 {
2217         struct bcmgenet_priv *priv = netdev_priv(dev);
2218         struct netdev_hw_addr *ha;
2219         int i, mc;
2220         u32 reg;
2221 
2222         netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2223 
2224         /* Promiscous mode */
2225         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2226         if (dev->flags & IFF_PROMISC) {
2227                 reg |= CMD_PROMISC;
2228                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2229                 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2230                 return;
2231         } else {
2232                 reg &= ~CMD_PROMISC;
2233                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2234         }
2235 
2236         /* UniMac doesn't support ALLMULTI */
2237         if (dev->flags & IFF_ALLMULTI) {
2238                 netdev_warn(dev, "ALLMULTI is not supported\n");
2239                 return;
2240         }
2241 
2242         /* update MDF filter */
2243         i = 0;
2244         mc = 0;
2245         /* Broadcast */
2246         bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
2247         /* my own address.*/
2248         bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
2249         /* Unicast list*/
2250         if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
2251                 return;
2252 
2253         if (!netdev_uc_empty(dev))
2254                 netdev_for_each_uc_addr(ha, dev)
2255                         bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2256         /* Multicast */
2257         if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
2258                 return;
2259 
2260         netdev_for_each_mc_addr(ha, dev)
2261                 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2262 }
2263 
2264 /* Set the hardware MAC address. */
2265 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
2266 {
2267         struct sockaddr *addr = p;
2268 
2269         /* Setting the MAC address at the hardware level is not possible
2270          * without disabling the UniMAC RX/TX enable bits.
2271          */
2272         if (netif_running(dev))
2273                 return -EBUSY;
2274 
2275         ether_addr_copy(dev->dev_addr, addr->sa_data);
2276 
2277         return 0;
2278 }
2279 
2280 static const struct net_device_ops bcmgenet_netdev_ops = {
2281         .ndo_open               = bcmgenet_open,
2282         .ndo_stop               = bcmgenet_close,
2283         .ndo_start_xmit         = bcmgenet_xmit,
2284         .ndo_tx_timeout         = bcmgenet_timeout,
2285         .ndo_set_rx_mode        = bcmgenet_set_rx_mode,
2286         .ndo_set_mac_address    = bcmgenet_set_mac_addr,
2287         .ndo_do_ioctl           = bcmgenet_ioctl,
2288         .ndo_set_features       = bcmgenet_set_features,
2289 };
2290 
2291 /* Array of GENET hardware parameters/characteristics */
2292 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
2293         [GENET_V1] = {
2294                 .tx_queues = 0,
2295                 .rx_queues = 0,
2296                 .bds_cnt = 0,
2297                 .bp_in_en_shift = 16,
2298                 .bp_in_mask = 0xffff,
2299                 .hfb_filter_cnt = 16,
2300                 .qtag_mask = 0x1F,
2301                 .hfb_offset = 0x1000,
2302                 .rdma_offset = 0x2000,
2303                 .tdma_offset = 0x3000,
2304                 .words_per_bd = 2,
2305         },
2306         [GENET_V2] = {
2307                 .tx_queues = 4,
2308                 .rx_queues = 4,
2309                 .bds_cnt = 32,
2310                 .bp_in_en_shift = 16,
2311                 .bp_in_mask = 0xffff,
2312                 .hfb_filter_cnt = 16,
2313                 .qtag_mask = 0x1F,
2314                 .tbuf_offset = 0x0600,
2315                 .hfb_offset = 0x1000,
2316                 .hfb_reg_offset = 0x2000,
2317                 .rdma_offset = 0x3000,
2318                 .tdma_offset = 0x4000,
2319                 .words_per_bd = 2,
2320                 .flags = GENET_HAS_EXT,
2321         },
2322         [GENET_V3] = {
2323                 .tx_queues = 4,
2324                 .rx_queues = 4,
2325                 .bds_cnt = 32,
2326                 .bp_in_en_shift = 17,
2327                 .bp_in_mask = 0x1ffff,
2328                 .hfb_filter_cnt = 48,
2329                 .qtag_mask = 0x3F,
2330                 .tbuf_offset = 0x0600,
2331                 .hfb_offset = 0x8000,
2332                 .hfb_reg_offset = 0xfc00,
2333                 .rdma_offset = 0x10000,
2334                 .tdma_offset = 0x11000,
2335                 .words_per_bd = 2,
2336                 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2337         },
2338         [GENET_V4] = {
2339                 .tx_queues = 4,
2340                 .rx_queues = 4,
2341                 .bds_cnt = 32,
2342                 .bp_in_en_shift = 17,
2343                 .bp_in_mask = 0x1ffff,
2344                 .hfb_filter_cnt = 48,
2345                 .qtag_mask = 0x3F,
2346                 .tbuf_offset = 0x0600,
2347                 .hfb_offset = 0x8000,
2348                 .hfb_reg_offset = 0xfc00,
2349                 .rdma_offset = 0x2000,
2350                 .tdma_offset = 0x4000,
2351                 .words_per_bd = 3,
2352                 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2353         },
2354 };
2355 
2356 /* Infer hardware parameters from the detected GENET version */
2357 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
2358 {
2359         struct bcmgenet_hw_params *params;
2360         u32 reg;
2361         u8 major;
2362 
2363         if (GENET_IS_V4(priv)) {
2364                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2365                 genet_dma_ring_regs = genet_dma_ring_regs_v4;
2366                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2367                 priv->version = GENET_V4;
2368         } else if (GENET_IS_V3(priv)) {
2369                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2370                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2371                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2372                 priv->version = GENET_V3;
2373         } else if (GENET_IS_V2(priv)) {
2374                 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
2375                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2376                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2377                 priv->version = GENET_V2;
2378         } else if (GENET_IS_V1(priv)) {
2379                 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
2380                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2381                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2382                 priv->version = GENET_V1;
2383         }
2384 
2385         /* enum genet_version starts at 1 */
2386         priv->hw_params = &bcmgenet_hw_params[priv->version];
2387         params = priv->hw_params;
2388 
2389         /* Read GENET HW version */
2390         reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
2391         major = (reg >> 24 & 0x0f);
2392         if (major == 5)
2393                 major = 4;
2394         else if (major == 0)
2395                 major = 1;
2396         if (major != priv->version) {
2397                 dev_err(&priv->pdev->dev,
2398                         "GENET version mismatch, got: %d, configured for: %d\n",
2399                         major, priv->version);
2400         }
2401 
2402         /* Print the GENET core version */
2403         dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
2404                 major, (reg >> 16) & 0x0f, reg & 0xffff);
2405 
2406 #ifdef CONFIG_PHYS_ADDR_T_64BIT
2407         if (!(params->flags & GENET_HAS_40BITS))
2408                 pr_warn("GENET does not support 40-bits PA\n");
2409 #endif
2410 
2411         pr_debug("Configuration for version: %d\n"
2412                 "TXq: %1d, RXq: %1d, BDs: %1d\n"
2413                 "BP << en: %2d, BP msk: 0x%05x\n"
2414                 "HFB count: %2d, QTAQ msk: 0x%05x\n"
2415                 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
2416                 "RDMA: 0x%05x, TDMA: 0x%05x\n"
2417                 "Words/BD: %d\n",
2418                 priv->version,
2419                 params->tx_queues, params->rx_queues, params->bds_cnt,
2420                 params->bp_in_en_shift, params->bp_in_mask,
2421                 params->hfb_filter_cnt, params->qtag_mask,
2422                 params->tbuf_offset, params->hfb_offset,
2423                 params->hfb_reg_offset,
2424                 params->rdma_offset, params->tdma_offset,
2425                 params->words_per_bd);
2426 }
2427 
2428 static const struct of_device_id bcmgenet_match[] = {
2429         { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
2430         { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
2431         { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
2432         { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
2433         { },
2434 };
2435 
2436 static int bcmgenet_probe(struct platform_device *pdev)
2437 {
2438         struct device_node *dn = pdev->dev.of_node;
2439         const struct of_device_id *of_id;
2440         struct bcmgenet_priv *priv;
2441         struct net_device *dev;
2442         const void *macaddr;
2443         struct resource *r;
2444         int err = -EIO;
2445 
2446         /* Up to GENET_MAX_MQ_CNT + 1 TX queues and a single RX queue */
2447         dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 1);
2448         if (!dev) {
2449                 dev_err(&pdev->dev, "can't allocate net device\n");
2450                 return -ENOMEM;
2451         }
2452 
2453         of_id = of_match_node(bcmgenet_match, dn);
2454         if (!of_id)
2455                 return -EINVAL;
2456 
2457         priv = netdev_priv(dev);
2458         priv->irq0 = platform_get_irq(pdev, 0);
2459         priv->irq1 = platform_get_irq(pdev, 1);
2460         if (!priv->irq0 || !priv->irq1) {
2461                 dev_err(&pdev->dev, "can't find IRQs\n");
2462                 err = -EINVAL;
2463                 goto err;
2464         }
2465 
2466         macaddr = of_get_mac_address(dn);
2467         if (!macaddr) {
2468                 dev_err(&pdev->dev, "can't find MAC address\n");
2469                 err = -EINVAL;
2470                 goto err;
2471         }
2472 
2473         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2474         priv->base = devm_ioremap_resource(&pdev->dev, r);
2475         if (IS_ERR(priv->base)) {
2476                 err = PTR_ERR(priv->base);
2477                 goto err;
2478         }
2479 
2480         SET_NETDEV_DEV(dev, &pdev->dev);
2481         dev_set_drvdata(&pdev->dev, dev);
2482         ether_addr_copy(dev->dev_addr, macaddr);
2483         dev->watchdog_timeo = 2 * HZ;
2484         SET_ETHTOOL_OPS(dev, &bcmgenet_ethtool_ops);
2485         dev->netdev_ops = &bcmgenet_netdev_ops;
2486         netif_napi_add(dev, &priv->napi, bcmgenet_poll, 64);
2487 
2488         priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
2489 
2490         /* Set hardware features */
2491         dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
2492                 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
2493 
2494         /* Set the needed headroom to account for any possible
2495          * features enabling/disabling at runtime
2496          */
2497         dev->needed_headroom += 64;
2498 
2499         netdev_boot_setup_check(dev);
2500 
2501         priv->dev = dev;
2502         priv->pdev = pdev;
2503         priv->version = (enum bcmgenet_version)of_id->data;
2504 
2505         bcmgenet_set_hw_params(priv);
2506 
2507         /* Mii wait queue */
2508         init_waitqueue_head(&priv->wq);
2509         /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
2510         priv->rx_buf_len = RX_BUF_LENGTH;
2511         INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
2512 
2513         priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
2514         if (IS_ERR(priv->clk))
2515                 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
2516 
2517         priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
2518         if (IS_ERR(priv->clk_wol))
2519                 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
2520 
2521         if (!IS_ERR(priv->clk))
2522                 clk_prepare_enable(priv->clk);
2523 
2524         err = reset_umac(priv);
2525         if (err)
2526                 goto err_clk_disable;
2527 
2528         err = bcmgenet_mii_init(dev);
2529         if (err)
2530                 goto err_clk_disable;
2531 
2532         /* setup number of real queues  + 1 (GENET_V1 has 0 hardware queues
2533          * just the ring 16 descriptor based TX
2534          */
2535         netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
2536         netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
2537 
2538         err = register_netdev(dev);
2539         if (err)
2540                 goto err_clk_disable;
2541 
2542         /* Turn off the main clock, WOL clock is handled separately */
2543         if (!IS_ERR(priv->clk))
2544                 clk_disable_unprepare(priv->clk);
2545 
2546         return err;
2547 
2548 err_clk_disable:
2549         if (!IS_ERR(priv->clk))
2550                 clk_disable_unprepare(priv->clk);
2551 err:
2552         free_netdev(dev);
2553         return err;
2554 }
2555 
2556 static int bcmgenet_remove(struct platform_device *pdev)
2557 {
2558         struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
2559 
2560         dev_set_drvdata(&pdev->dev, NULL);
2561         unregister_netdev(priv->dev);
2562         bcmgenet_mii_exit(priv->dev);
2563         free_netdev(priv->dev);
2564 
2565         return 0;
2566 }
2567 
2568 
2569 static struct platform_driver bcmgenet_driver = {
2570         .probe  = bcmgenet_probe,
2571         .remove = bcmgenet_remove,
2572         .driver = {
2573                 .name   = "bcmgenet",
2574                 .owner  = THIS_MODULE,
2575                 .of_match_table = bcmgenet_match,
2576         },
2577 };
2578 module_platform_driver(bcmgenet_driver);
2579 
2580 MODULE_AUTHOR("Broadcom Corporation");
2581 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
2582 MODULE_ALIAS("platform:bcmgenet");
2583 MODULE_LICENSE("GPL");
2584 

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