Version:  2.0.40 2.2.26 2.4.37 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9

Linux/drivers/net/ethernet/broadcom/genet/bcmgenet.c

  1 /*
  2  * Broadcom GENET (Gigabit Ethernet) controller driver
  3  *
  4  * Copyright (c) 2014 Broadcom Corporation
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License version 2 as
  8  * published by the Free Software Foundation.
  9  */
 10 
 11 #define pr_fmt(fmt)                             "bcmgenet: " fmt
 12 
 13 #include <linux/kernel.h>
 14 #include <linux/module.h>
 15 #include <linux/sched.h>
 16 #include <linux/types.h>
 17 #include <linux/fcntl.h>
 18 #include <linux/interrupt.h>
 19 #include <linux/string.h>
 20 #include <linux/if_ether.h>
 21 #include <linux/init.h>
 22 #include <linux/errno.h>
 23 #include <linux/delay.h>
 24 #include <linux/platform_device.h>
 25 #include <linux/dma-mapping.h>
 26 #include <linux/pm.h>
 27 #include <linux/clk.h>
 28 #include <linux/of.h>
 29 #include <linux/of_address.h>
 30 #include <linux/of_irq.h>
 31 #include <linux/of_net.h>
 32 #include <linux/of_platform.h>
 33 #include <net/arp.h>
 34 
 35 #include <linux/mii.h>
 36 #include <linux/ethtool.h>
 37 #include <linux/netdevice.h>
 38 #include <linux/inetdevice.h>
 39 #include <linux/etherdevice.h>
 40 #include <linux/skbuff.h>
 41 #include <linux/in.h>
 42 #include <linux/ip.h>
 43 #include <linux/ipv6.h>
 44 #include <linux/phy.h>
 45 #include <linux/platform_data/bcmgenet.h>
 46 
 47 #include <asm/unaligned.h>
 48 
 49 #include "bcmgenet.h"
 50 
 51 /* Maximum number of hardware queues, downsized if needed */
 52 #define GENET_MAX_MQ_CNT        4
 53 
 54 /* Default highest priority queue for multi queue support */
 55 #define GENET_Q0_PRIORITY       0
 56 
 57 #define GENET_Q16_RX_BD_CNT     \
 58         (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
 59 #define GENET_Q16_TX_BD_CNT     \
 60         (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
 61 
 62 #define RX_BUF_LENGTH           2048
 63 #define SKB_ALIGNMENT           32
 64 
 65 /* Tx/Rx DMA register offset, skip 256 descriptors */
 66 #define WORDS_PER_BD(p)         (p->hw_params->words_per_bd)
 67 #define DMA_DESC_SIZE           (WORDS_PER_BD(priv) * sizeof(u32))
 68 
 69 #define GENET_TDMA_REG_OFF      (priv->hw_params->tdma_offset + \
 70                                 TOTAL_DESC * DMA_DESC_SIZE)
 71 
 72 #define GENET_RDMA_REG_OFF      (priv->hw_params->rdma_offset + \
 73                                 TOTAL_DESC * DMA_DESC_SIZE)
 74 
 75 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
 76                                              void __iomem *d, u32 value)
 77 {
 78         __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
 79 }
 80 
 81 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
 82                                             void __iomem *d)
 83 {
 84         return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
 85 }
 86 
 87 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
 88                                     void __iomem *d,
 89                                     dma_addr_t addr)
 90 {
 91         __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
 92 
 93         /* Register writes to GISB bus can take couple hundred nanoseconds
 94          * and are done for each packet, save these expensive writes unless
 95          * the platform is explicitly configured for 64-bits/LPAE.
 96          */
 97 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 98         if (priv->hw_params->flags & GENET_HAS_40BITS)
 99                 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
100 #endif
101 }
102 
103 /* Combined address + length/status setter */
104 static inline void dmadesc_set(struct bcmgenet_priv *priv,
105                                void __iomem *d, dma_addr_t addr, u32 val)
106 {
107         dmadesc_set_addr(priv, d, addr);
108         dmadesc_set_length_status(priv, d, val);
109 }
110 
111 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
112                                           void __iomem *d)
113 {
114         dma_addr_t addr;
115 
116         addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
117 
118         /* Register writes to GISB bus can take couple hundred nanoseconds
119          * and are done for each packet, save these expensive writes unless
120          * the platform is explicitly configured for 64-bits/LPAE.
121          */
122 #ifdef CONFIG_PHYS_ADDR_T_64BIT
123         if (priv->hw_params->flags & GENET_HAS_40BITS)
124                 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
125 #endif
126         return addr;
127 }
128 
129 #define GENET_VER_FMT   "%1d.%1d EPHY: 0x%04x"
130 
131 #define GENET_MSG_DEFAULT       (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
132                                 NETIF_MSG_LINK)
133 
134 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
135 {
136         if (GENET_IS_V1(priv))
137                 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
138         else
139                 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
140 }
141 
142 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
143 {
144         if (GENET_IS_V1(priv))
145                 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
146         else
147                 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
148 }
149 
150 /* These macros are defined to deal with register map change
151  * between GENET1.1 and GENET2. Only those currently being used
152  * by driver are defined.
153  */
154 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
155 {
156         if (GENET_IS_V1(priv))
157                 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
158         else
159                 return __raw_readl(priv->base +
160                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
161 }
162 
163 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
164 {
165         if (GENET_IS_V1(priv))
166                 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
167         else
168                 __raw_writel(val, priv->base +
169                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
170 }
171 
172 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
173 {
174         if (GENET_IS_V1(priv))
175                 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
176         else
177                 return __raw_readl(priv->base +
178                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
179 }
180 
181 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
182 {
183         if (GENET_IS_V1(priv))
184                 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
185         else
186                 __raw_writel(val, priv->base +
187                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
188 }
189 
190 /* RX/TX DMA register accessors */
191 enum dma_reg {
192         DMA_RING_CFG = 0,
193         DMA_CTRL,
194         DMA_STATUS,
195         DMA_SCB_BURST_SIZE,
196         DMA_ARB_CTRL,
197         DMA_PRIORITY_0,
198         DMA_PRIORITY_1,
199         DMA_PRIORITY_2,
200         DMA_INDEX2RING_0,
201         DMA_INDEX2RING_1,
202         DMA_INDEX2RING_2,
203         DMA_INDEX2RING_3,
204         DMA_INDEX2RING_4,
205         DMA_INDEX2RING_5,
206         DMA_INDEX2RING_6,
207         DMA_INDEX2RING_7,
208         DMA_RING0_TIMEOUT,
209         DMA_RING1_TIMEOUT,
210         DMA_RING2_TIMEOUT,
211         DMA_RING3_TIMEOUT,
212         DMA_RING4_TIMEOUT,
213         DMA_RING5_TIMEOUT,
214         DMA_RING6_TIMEOUT,
215         DMA_RING7_TIMEOUT,
216         DMA_RING8_TIMEOUT,
217         DMA_RING9_TIMEOUT,
218         DMA_RING10_TIMEOUT,
219         DMA_RING11_TIMEOUT,
220         DMA_RING12_TIMEOUT,
221         DMA_RING13_TIMEOUT,
222         DMA_RING14_TIMEOUT,
223         DMA_RING15_TIMEOUT,
224         DMA_RING16_TIMEOUT,
225 };
226 
227 static const u8 bcmgenet_dma_regs_v3plus[] = {
228         [DMA_RING_CFG]          = 0x00,
229         [DMA_CTRL]              = 0x04,
230         [DMA_STATUS]            = 0x08,
231         [DMA_SCB_BURST_SIZE]    = 0x0C,
232         [DMA_ARB_CTRL]          = 0x2C,
233         [DMA_PRIORITY_0]        = 0x30,
234         [DMA_PRIORITY_1]        = 0x34,
235         [DMA_PRIORITY_2]        = 0x38,
236         [DMA_RING0_TIMEOUT]     = 0x2C,
237         [DMA_RING1_TIMEOUT]     = 0x30,
238         [DMA_RING2_TIMEOUT]     = 0x34,
239         [DMA_RING3_TIMEOUT]     = 0x38,
240         [DMA_RING4_TIMEOUT]     = 0x3c,
241         [DMA_RING5_TIMEOUT]     = 0x40,
242         [DMA_RING6_TIMEOUT]     = 0x44,
243         [DMA_RING7_TIMEOUT]     = 0x48,
244         [DMA_RING8_TIMEOUT]     = 0x4c,
245         [DMA_RING9_TIMEOUT]     = 0x50,
246         [DMA_RING10_TIMEOUT]    = 0x54,
247         [DMA_RING11_TIMEOUT]    = 0x58,
248         [DMA_RING12_TIMEOUT]    = 0x5c,
249         [DMA_RING13_TIMEOUT]    = 0x60,
250         [DMA_RING14_TIMEOUT]    = 0x64,
251         [DMA_RING15_TIMEOUT]    = 0x68,
252         [DMA_RING16_TIMEOUT]    = 0x6C,
253         [DMA_INDEX2RING_0]      = 0x70,
254         [DMA_INDEX2RING_1]      = 0x74,
255         [DMA_INDEX2RING_2]      = 0x78,
256         [DMA_INDEX2RING_3]      = 0x7C,
257         [DMA_INDEX2RING_4]      = 0x80,
258         [DMA_INDEX2RING_5]      = 0x84,
259         [DMA_INDEX2RING_6]      = 0x88,
260         [DMA_INDEX2RING_7]      = 0x8C,
261 };
262 
263 static const u8 bcmgenet_dma_regs_v2[] = {
264         [DMA_RING_CFG]          = 0x00,
265         [DMA_CTRL]              = 0x04,
266         [DMA_STATUS]            = 0x08,
267         [DMA_SCB_BURST_SIZE]    = 0x0C,
268         [DMA_ARB_CTRL]          = 0x30,
269         [DMA_PRIORITY_0]        = 0x34,
270         [DMA_PRIORITY_1]        = 0x38,
271         [DMA_PRIORITY_2]        = 0x3C,
272         [DMA_RING0_TIMEOUT]     = 0x2C,
273         [DMA_RING1_TIMEOUT]     = 0x30,
274         [DMA_RING2_TIMEOUT]     = 0x34,
275         [DMA_RING3_TIMEOUT]     = 0x38,
276         [DMA_RING4_TIMEOUT]     = 0x3c,
277         [DMA_RING5_TIMEOUT]     = 0x40,
278         [DMA_RING6_TIMEOUT]     = 0x44,
279         [DMA_RING7_TIMEOUT]     = 0x48,
280         [DMA_RING8_TIMEOUT]     = 0x4c,
281         [DMA_RING9_TIMEOUT]     = 0x50,
282         [DMA_RING10_TIMEOUT]    = 0x54,
283         [DMA_RING11_TIMEOUT]    = 0x58,
284         [DMA_RING12_TIMEOUT]    = 0x5c,
285         [DMA_RING13_TIMEOUT]    = 0x60,
286         [DMA_RING14_TIMEOUT]    = 0x64,
287         [DMA_RING15_TIMEOUT]    = 0x68,
288         [DMA_RING16_TIMEOUT]    = 0x6C,
289 };
290 
291 static const u8 bcmgenet_dma_regs_v1[] = {
292         [DMA_CTRL]              = 0x00,
293         [DMA_STATUS]            = 0x04,
294         [DMA_SCB_BURST_SIZE]    = 0x0C,
295         [DMA_ARB_CTRL]          = 0x30,
296         [DMA_PRIORITY_0]        = 0x34,
297         [DMA_PRIORITY_1]        = 0x38,
298         [DMA_PRIORITY_2]        = 0x3C,
299         [DMA_RING0_TIMEOUT]     = 0x2C,
300         [DMA_RING1_TIMEOUT]     = 0x30,
301         [DMA_RING2_TIMEOUT]     = 0x34,
302         [DMA_RING3_TIMEOUT]     = 0x38,
303         [DMA_RING4_TIMEOUT]     = 0x3c,
304         [DMA_RING5_TIMEOUT]     = 0x40,
305         [DMA_RING6_TIMEOUT]     = 0x44,
306         [DMA_RING7_TIMEOUT]     = 0x48,
307         [DMA_RING8_TIMEOUT]     = 0x4c,
308         [DMA_RING9_TIMEOUT]     = 0x50,
309         [DMA_RING10_TIMEOUT]    = 0x54,
310         [DMA_RING11_TIMEOUT]    = 0x58,
311         [DMA_RING12_TIMEOUT]    = 0x5c,
312         [DMA_RING13_TIMEOUT]    = 0x60,
313         [DMA_RING14_TIMEOUT]    = 0x64,
314         [DMA_RING15_TIMEOUT]    = 0x68,
315         [DMA_RING16_TIMEOUT]    = 0x6C,
316 };
317 
318 /* Set at runtime once bcmgenet version is known */
319 static const u8 *bcmgenet_dma_regs;
320 
321 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
322 {
323         return netdev_priv(dev_get_drvdata(dev));
324 }
325 
326 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
327                                       enum dma_reg r)
328 {
329         return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
330                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
331 }
332 
333 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
334                                         u32 val, enum dma_reg r)
335 {
336         __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
337                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
338 }
339 
340 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
341                                       enum dma_reg r)
342 {
343         return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
344                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
345 }
346 
347 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
348                                         u32 val, enum dma_reg r)
349 {
350         __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
351                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
352 }
353 
354 /* RDMA/TDMA ring registers and accessors
355  * we merge the common fields and just prefix with T/D the registers
356  * having different meaning depending on the direction
357  */
358 enum dma_ring_reg {
359         TDMA_READ_PTR = 0,
360         RDMA_WRITE_PTR = TDMA_READ_PTR,
361         TDMA_READ_PTR_HI,
362         RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
363         TDMA_CONS_INDEX,
364         RDMA_PROD_INDEX = TDMA_CONS_INDEX,
365         TDMA_PROD_INDEX,
366         RDMA_CONS_INDEX = TDMA_PROD_INDEX,
367         DMA_RING_BUF_SIZE,
368         DMA_START_ADDR,
369         DMA_START_ADDR_HI,
370         DMA_END_ADDR,
371         DMA_END_ADDR_HI,
372         DMA_MBUF_DONE_THRESH,
373         TDMA_FLOW_PERIOD,
374         RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
375         TDMA_WRITE_PTR,
376         RDMA_READ_PTR = TDMA_WRITE_PTR,
377         TDMA_WRITE_PTR_HI,
378         RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
379 };
380 
381 /* GENET v4 supports 40-bits pointer addressing
382  * for obvious reasons the LO and HI word parts
383  * are contiguous, but this offsets the other
384  * registers.
385  */
386 static const u8 genet_dma_ring_regs_v4[] = {
387         [TDMA_READ_PTR]                 = 0x00,
388         [TDMA_READ_PTR_HI]              = 0x04,
389         [TDMA_CONS_INDEX]               = 0x08,
390         [TDMA_PROD_INDEX]               = 0x0C,
391         [DMA_RING_BUF_SIZE]             = 0x10,
392         [DMA_START_ADDR]                = 0x14,
393         [DMA_START_ADDR_HI]             = 0x18,
394         [DMA_END_ADDR]                  = 0x1C,
395         [DMA_END_ADDR_HI]               = 0x20,
396         [DMA_MBUF_DONE_THRESH]          = 0x24,
397         [TDMA_FLOW_PERIOD]              = 0x28,
398         [TDMA_WRITE_PTR]                = 0x2C,
399         [TDMA_WRITE_PTR_HI]             = 0x30,
400 };
401 
402 static const u8 genet_dma_ring_regs_v123[] = {
403         [TDMA_READ_PTR]                 = 0x00,
404         [TDMA_CONS_INDEX]               = 0x04,
405         [TDMA_PROD_INDEX]               = 0x08,
406         [DMA_RING_BUF_SIZE]             = 0x0C,
407         [DMA_START_ADDR]                = 0x10,
408         [DMA_END_ADDR]                  = 0x14,
409         [DMA_MBUF_DONE_THRESH]          = 0x18,
410         [TDMA_FLOW_PERIOD]              = 0x1C,
411         [TDMA_WRITE_PTR]                = 0x20,
412 };
413 
414 /* Set at runtime once GENET version is known */
415 static const u8 *genet_dma_ring_regs;
416 
417 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
418                                            unsigned int ring,
419                                            enum dma_ring_reg r)
420 {
421         return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
422                         (DMA_RING_SIZE * ring) +
423                         genet_dma_ring_regs[r]);
424 }
425 
426 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
427                                              unsigned int ring, u32 val,
428                                              enum dma_ring_reg r)
429 {
430         __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
431                         (DMA_RING_SIZE * ring) +
432                         genet_dma_ring_regs[r]);
433 }
434 
435 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
436                                            unsigned int ring,
437                                            enum dma_ring_reg r)
438 {
439         return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
440                         (DMA_RING_SIZE * ring) +
441                         genet_dma_ring_regs[r]);
442 }
443 
444 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
445                                              unsigned int ring, u32 val,
446                                              enum dma_ring_reg r)
447 {
448         __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
449                         (DMA_RING_SIZE * ring) +
450                         genet_dma_ring_regs[r]);
451 }
452 
453 static int bcmgenet_get_link_ksettings(struct net_device *dev,
454                                        struct ethtool_link_ksettings *cmd)
455 {
456         struct bcmgenet_priv *priv = netdev_priv(dev);
457 
458         if (!netif_running(dev))
459                 return -EINVAL;
460 
461         if (!priv->phydev)
462                 return -ENODEV;
463 
464         return phy_ethtool_ksettings_get(priv->phydev, cmd);
465 }
466 
467 static int bcmgenet_set_link_ksettings(struct net_device *dev,
468                                        const struct ethtool_link_ksettings *cmd)
469 {
470         struct bcmgenet_priv *priv = netdev_priv(dev);
471 
472         if (!netif_running(dev))
473                 return -EINVAL;
474 
475         if (!priv->phydev)
476                 return -ENODEV;
477 
478         return phy_ethtool_ksettings_set(priv->phydev, cmd);
479 }
480 
481 static int bcmgenet_set_rx_csum(struct net_device *dev,
482                                 netdev_features_t wanted)
483 {
484         struct bcmgenet_priv *priv = netdev_priv(dev);
485         u32 rbuf_chk_ctrl;
486         bool rx_csum_en;
487 
488         rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
489 
490         rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
491 
492         /* enable rx checksumming */
493         if (rx_csum_en)
494                 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
495         else
496                 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
497         priv->desc_rxchk_en = rx_csum_en;
498 
499         /* If UniMAC forwards CRC, we need to skip over it to get
500          * a valid CHK bit to be set in the per-packet status word
501         */
502         if (rx_csum_en && priv->crc_fwd_en)
503                 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
504         else
505                 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
506 
507         bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
508 
509         return 0;
510 }
511 
512 static int bcmgenet_set_tx_csum(struct net_device *dev,
513                                 netdev_features_t wanted)
514 {
515         struct bcmgenet_priv *priv = netdev_priv(dev);
516         bool desc_64b_en;
517         u32 tbuf_ctrl, rbuf_ctrl;
518 
519         tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
520         rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
521 
522         desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
523 
524         /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
525         if (desc_64b_en) {
526                 tbuf_ctrl |= RBUF_64B_EN;
527                 rbuf_ctrl |= RBUF_64B_EN;
528         } else {
529                 tbuf_ctrl &= ~RBUF_64B_EN;
530                 rbuf_ctrl &= ~RBUF_64B_EN;
531         }
532         priv->desc_64b_en = desc_64b_en;
533 
534         bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
535         bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
536 
537         return 0;
538 }
539 
540 static int bcmgenet_set_features(struct net_device *dev,
541                                  netdev_features_t features)
542 {
543         netdev_features_t changed = features ^ dev->features;
544         netdev_features_t wanted = dev->wanted_features;
545         int ret = 0;
546 
547         if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
548                 ret = bcmgenet_set_tx_csum(dev, wanted);
549         if (changed & (NETIF_F_RXCSUM))
550                 ret = bcmgenet_set_rx_csum(dev, wanted);
551 
552         return ret;
553 }
554 
555 static u32 bcmgenet_get_msglevel(struct net_device *dev)
556 {
557         struct bcmgenet_priv *priv = netdev_priv(dev);
558 
559         return priv->msg_enable;
560 }
561 
562 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
563 {
564         struct bcmgenet_priv *priv = netdev_priv(dev);
565 
566         priv->msg_enable = level;
567 }
568 
569 static int bcmgenet_get_coalesce(struct net_device *dev,
570                                  struct ethtool_coalesce *ec)
571 {
572         struct bcmgenet_priv *priv = netdev_priv(dev);
573 
574         ec->tx_max_coalesced_frames =
575                 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
576                                          DMA_MBUF_DONE_THRESH);
577         ec->rx_max_coalesced_frames =
578                 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
579                                          DMA_MBUF_DONE_THRESH);
580         ec->rx_coalesce_usecs =
581                 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
582 
583         return 0;
584 }
585 
586 static int bcmgenet_set_coalesce(struct net_device *dev,
587                                  struct ethtool_coalesce *ec)
588 {
589         struct bcmgenet_priv *priv = netdev_priv(dev);
590         unsigned int i;
591         u32 reg;
592 
593         /* Base system clock is 125Mhz, DMA timeout is this reference clock
594          * divided by 1024, which yields roughly 8.192us, our maximum value
595          * has to fit in the DMA_TIMEOUT_MASK (16 bits)
596          */
597         if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
598             ec->tx_max_coalesced_frames == 0 ||
599             ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
600             ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
601                 return -EINVAL;
602 
603         if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
604                 return -EINVAL;
605 
606         /* GENET TDMA hardware does not support a configurable timeout, but will
607          * always generate an interrupt either after MBDONE packets have been
608          * transmitted, or when the ring is emtpy.
609          */
610         if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high ||
611             ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low)
612                 return -EOPNOTSUPP;
613 
614         /* Program all TX queues with the same values, as there is no
615          * ethtool knob to do coalescing on a per-queue basis
616          */
617         for (i = 0; i < priv->hw_params->tx_queues; i++)
618                 bcmgenet_tdma_ring_writel(priv, i,
619                                           ec->tx_max_coalesced_frames,
620                                           DMA_MBUF_DONE_THRESH);
621         bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
622                                   ec->tx_max_coalesced_frames,
623                                   DMA_MBUF_DONE_THRESH);
624 
625         for (i = 0; i < priv->hw_params->rx_queues; i++) {
626                 bcmgenet_rdma_ring_writel(priv, i,
627                                           ec->rx_max_coalesced_frames,
628                                           DMA_MBUF_DONE_THRESH);
629 
630                 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
631                 reg &= ~DMA_TIMEOUT_MASK;
632                 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
633                 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
634         }
635 
636         bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
637                                   ec->rx_max_coalesced_frames,
638                                   DMA_MBUF_DONE_THRESH);
639 
640         reg = bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT);
641         reg &= ~DMA_TIMEOUT_MASK;
642         reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
643         bcmgenet_rdma_writel(priv, reg, DMA_RING16_TIMEOUT);
644 
645         return 0;
646 }
647 
648 /* standard ethtool support functions. */
649 enum bcmgenet_stat_type {
650         BCMGENET_STAT_NETDEV = -1,
651         BCMGENET_STAT_MIB_RX,
652         BCMGENET_STAT_MIB_TX,
653         BCMGENET_STAT_RUNT,
654         BCMGENET_STAT_MISC,
655         BCMGENET_STAT_SOFT,
656 };
657 
658 struct bcmgenet_stats {
659         char stat_string[ETH_GSTRING_LEN];
660         int stat_sizeof;
661         int stat_offset;
662         enum bcmgenet_stat_type type;
663         /* reg offset from UMAC base for misc counters */
664         u16 reg_offset;
665 };
666 
667 #define STAT_NETDEV(m) { \
668         .stat_string = __stringify(m), \
669         .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
670         .stat_offset = offsetof(struct net_device_stats, m), \
671         .type = BCMGENET_STAT_NETDEV, \
672 }
673 
674 #define STAT_GENET_MIB(str, m, _type) { \
675         .stat_string = str, \
676         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
677         .stat_offset = offsetof(struct bcmgenet_priv, m), \
678         .type = _type, \
679 }
680 
681 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
682 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
683 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
684 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
685 
686 #define STAT_GENET_MISC(str, m, offset) { \
687         .stat_string = str, \
688         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
689         .stat_offset = offsetof(struct bcmgenet_priv, m), \
690         .type = BCMGENET_STAT_MISC, \
691         .reg_offset = offset, \
692 }
693 
694 
695 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
696  * between the end of TX stats and the beginning of the RX RUNT
697  */
698 #define BCMGENET_STAT_OFFSET    0xc
699 
700 /* Hardware counters must be kept in sync because the order/offset
701  * is important here (order in structure declaration = order in hardware)
702  */
703 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
704         /* general stats */
705         STAT_NETDEV(rx_packets),
706         STAT_NETDEV(tx_packets),
707         STAT_NETDEV(rx_bytes),
708         STAT_NETDEV(tx_bytes),
709         STAT_NETDEV(rx_errors),
710         STAT_NETDEV(tx_errors),
711         STAT_NETDEV(rx_dropped),
712         STAT_NETDEV(tx_dropped),
713         STAT_NETDEV(multicast),
714         /* UniMAC RSV counters */
715         STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
716         STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
717         STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
718         STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
719         STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
720         STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
721         STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
722         STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
723         STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
724         STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
725         STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
726         STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
727         STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
728         STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
729         STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
730         STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
731         STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
732         STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
733         STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
734         STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
735         STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
736         STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
737         STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
738         STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
739         STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
740         STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
741         STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
742         STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
743         STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
744         /* UniMAC TSV counters */
745         STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
746         STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
747         STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
748         STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
749         STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
750         STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
751         STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
752         STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
753         STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
754         STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
755         STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
756         STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
757         STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
758         STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
759         STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
760         STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
761         STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
762         STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
763         STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
764         STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
765         STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
766         STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
767         STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
768         STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
769         STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
770         STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
771         STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
772         STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
773         STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
774         /* UniMAC RUNT counters */
775         STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
776         STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
777         STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
778         STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
779         /* Misc UniMAC counters */
780         STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
781                         UMAC_RBUF_OVFL_CNT),
782         STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
783         STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
784         STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
785         STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
786         STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
787 };
788 
789 #define BCMGENET_STATS_LEN      ARRAY_SIZE(bcmgenet_gstrings_stats)
790 
791 static void bcmgenet_get_drvinfo(struct net_device *dev,
792                                  struct ethtool_drvinfo *info)
793 {
794         strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
795         strlcpy(info->version, "v2.0", sizeof(info->version));
796 }
797 
798 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
799 {
800         switch (string_set) {
801         case ETH_SS_STATS:
802                 return BCMGENET_STATS_LEN;
803         default:
804                 return -EOPNOTSUPP;
805         }
806 }
807 
808 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
809                                  u8 *data)
810 {
811         int i;
812 
813         switch (stringset) {
814         case ETH_SS_STATS:
815                 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
816                         memcpy(data + i * ETH_GSTRING_LEN,
817                                bcmgenet_gstrings_stats[i].stat_string,
818                                ETH_GSTRING_LEN);
819                 }
820                 break;
821         }
822 }
823 
824 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
825 {
826         int i, j = 0;
827 
828         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
829                 const struct bcmgenet_stats *s;
830                 u8 offset = 0;
831                 u32 val = 0;
832                 char *p;
833 
834                 s = &bcmgenet_gstrings_stats[i];
835                 switch (s->type) {
836                 case BCMGENET_STAT_NETDEV:
837                 case BCMGENET_STAT_SOFT:
838                         continue;
839                 case BCMGENET_STAT_MIB_RX:
840                 case BCMGENET_STAT_MIB_TX:
841                 case BCMGENET_STAT_RUNT:
842                         if (s->type != BCMGENET_STAT_MIB_RX)
843                                 offset = BCMGENET_STAT_OFFSET;
844                         val = bcmgenet_umac_readl(priv,
845                                                   UMAC_MIB_START + j + offset);
846                         break;
847                 case BCMGENET_STAT_MISC:
848                         val = bcmgenet_umac_readl(priv, s->reg_offset);
849                         /* clear if overflowed */
850                         if (val == ~0)
851                                 bcmgenet_umac_writel(priv, 0, s->reg_offset);
852                         break;
853                 }
854 
855                 j += s->stat_sizeof;
856                 p = (char *)priv + s->stat_offset;
857                 *(u32 *)p = val;
858         }
859 }
860 
861 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
862                                        struct ethtool_stats *stats,
863                                        u64 *data)
864 {
865         struct bcmgenet_priv *priv = netdev_priv(dev);
866         int i;
867 
868         if (netif_running(dev))
869                 bcmgenet_update_mib_counters(priv);
870 
871         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
872                 const struct bcmgenet_stats *s;
873                 char *p;
874 
875                 s = &bcmgenet_gstrings_stats[i];
876                 if (s->type == BCMGENET_STAT_NETDEV)
877                         p = (char *)&dev->stats;
878                 else
879                         p = (char *)priv;
880                 p += s->stat_offset;
881                 if (sizeof(unsigned long) != sizeof(u32) &&
882                     s->stat_sizeof == sizeof(unsigned long))
883                         data[i] = *(unsigned long *)p;
884                 else
885                         data[i] = *(u32 *)p;
886         }
887 }
888 
889 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
890 {
891         struct bcmgenet_priv *priv = netdev_priv(dev);
892         u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
893         u32 reg;
894 
895         if (enable && !priv->clk_eee_enabled) {
896                 clk_prepare_enable(priv->clk_eee);
897                 priv->clk_eee_enabled = true;
898         }
899 
900         reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
901         if (enable)
902                 reg |= EEE_EN;
903         else
904                 reg &= ~EEE_EN;
905         bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
906 
907         /* Enable EEE and switch to a 27Mhz clock automatically */
908         reg = __raw_readl(priv->base + off);
909         if (enable)
910                 reg |= TBUF_EEE_EN | TBUF_PM_EN;
911         else
912                 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
913         __raw_writel(reg, priv->base + off);
914 
915         /* Do the same for thing for RBUF */
916         reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
917         if (enable)
918                 reg |= RBUF_EEE_EN | RBUF_PM_EN;
919         else
920                 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
921         bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
922 
923         if (!enable && priv->clk_eee_enabled) {
924                 clk_disable_unprepare(priv->clk_eee);
925                 priv->clk_eee_enabled = false;
926         }
927 
928         priv->eee.eee_enabled = enable;
929         priv->eee.eee_active = enable;
930 }
931 
932 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
933 {
934         struct bcmgenet_priv *priv = netdev_priv(dev);
935         struct ethtool_eee *p = &priv->eee;
936 
937         if (GENET_IS_V1(priv))
938                 return -EOPNOTSUPP;
939 
940         e->eee_enabled = p->eee_enabled;
941         e->eee_active = p->eee_active;
942         e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
943 
944         return phy_ethtool_get_eee(priv->phydev, e);
945 }
946 
947 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
948 {
949         struct bcmgenet_priv *priv = netdev_priv(dev);
950         struct ethtool_eee *p = &priv->eee;
951         int ret = 0;
952 
953         if (GENET_IS_V1(priv))
954                 return -EOPNOTSUPP;
955 
956         p->eee_enabled = e->eee_enabled;
957 
958         if (!p->eee_enabled) {
959                 bcmgenet_eee_enable_set(dev, false);
960         } else {
961                 ret = phy_init_eee(priv->phydev, 0);
962                 if (ret) {
963                         netif_err(priv, hw, dev, "EEE initialization failed\n");
964                         return ret;
965                 }
966 
967                 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
968                 bcmgenet_eee_enable_set(dev, true);
969         }
970 
971         return phy_ethtool_set_eee(priv->phydev, e);
972 }
973 
974 static int bcmgenet_nway_reset(struct net_device *dev)
975 {
976         struct bcmgenet_priv *priv = netdev_priv(dev);
977 
978         return genphy_restart_aneg(priv->phydev);
979 }
980 
981 /* standard ethtool support functions. */
982 static const struct ethtool_ops bcmgenet_ethtool_ops = {
983         .get_strings            = bcmgenet_get_strings,
984         .get_sset_count         = bcmgenet_get_sset_count,
985         .get_ethtool_stats      = bcmgenet_get_ethtool_stats,
986         .get_drvinfo            = bcmgenet_get_drvinfo,
987         .get_link               = ethtool_op_get_link,
988         .get_msglevel           = bcmgenet_get_msglevel,
989         .set_msglevel           = bcmgenet_set_msglevel,
990         .get_wol                = bcmgenet_get_wol,
991         .set_wol                = bcmgenet_set_wol,
992         .get_eee                = bcmgenet_get_eee,
993         .set_eee                = bcmgenet_set_eee,
994         .nway_reset             = bcmgenet_nway_reset,
995         .get_coalesce           = bcmgenet_get_coalesce,
996         .set_coalesce           = bcmgenet_set_coalesce,
997         .get_link_ksettings     = bcmgenet_get_link_ksettings,
998         .set_link_ksettings     = bcmgenet_set_link_ksettings,
999 };
1000 
1001 /* Power down the unimac, based on mode. */
1002 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1003                                 enum bcmgenet_power_mode mode)
1004 {
1005         int ret = 0;
1006         u32 reg;
1007 
1008         switch (mode) {
1009         case GENET_POWER_CABLE_SENSE:
1010                 phy_detach(priv->phydev);
1011                 break;
1012 
1013         case GENET_POWER_WOL_MAGIC:
1014                 ret = bcmgenet_wol_power_down_cfg(priv, mode);
1015                 break;
1016 
1017         case GENET_POWER_PASSIVE:
1018                 /* Power down LED */
1019                 if (priv->hw_params->flags & GENET_HAS_EXT) {
1020                         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1021                         reg |= (EXT_PWR_DOWN_PHY |
1022                                 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1023                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1024 
1025                         bcmgenet_phy_power_set(priv->dev, false);
1026                 }
1027                 break;
1028         default:
1029                 break;
1030         }
1031 
1032         return 0;
1033 }
1034 
1035 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
1036                               enum bcmgenet_power_mode mode)
1037 {
1038         u32 reg;
1039 
1040         if (!(priv->hw_params->flags & GENET_HAS_EXT))
1041                 return;
1042 
1043         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1044 
1045         switch (mode) {
1046         case GENET_POWER_PASSIVE:
1047                 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
1048                                 EXT_PWR_DOWN_BIAS);
1049                 /* fallthrough */
1050         case GENET_POWER_CABLE_SENSE:
1051                 /* enable APD */
1052                 reg |= EXT_PWR_DN_EN_LD;
1053                 break;
1054         case GENET_POWER_WOL_MAGIC:
1055                 bcmgenet_wol_power_up_cfg(priv, mode);
1056                 return;
1057         default:
1058                 break;
1059         }
1060 
1061         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1062         if (mode == GENET_POWER_PASSIVE) {
1063                 bcmgenet_phy_power_set(priv->dev, true);
1064                 bcmgenet_mii_reset(priv->dev);
1065         }
1066 }
1067 
1068 /* ioctl handle special commands that are not present in ethtool. */
1069 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1070 {
1071         struct bcmgenet_priv *priv = netdev_priv(dev);
1072         int val = 0;
1073 
1074         if (!netif_running(dev))
1075                 return -EINVAL;
1076 
1077         switch (cmd) {
1078         case SIOCGMIIPHY:
1079         case SIOCGMIIREG:
1080         case SIOCSMIIREG:
1081                 if (!priv->phydev)
1082                         val = -ENODEV;
1083                 else
1084                         val = phy_mii_ioctl(priv->phydev, rq, cmd);
1085                 break;
1086 
1087         default:
1088                 val = -EINVAL;
1089                 break;
1090         }
1091 
1092         return val;
1093 }
1094 
1095 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1096                                          struct bcmgenet_tx_ring *ring)
1097 {
1098         struct enet_cb *tx_cb_ptr;
1099 
1100         tx_cb_ptr = ring->cbs;
1101         tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1102 
1103         /* Advancing local write pointer */
1104         if (ring->write_ptr == ring->end_ptr)
1105                 ring->write_ptr = ring->cb_ptr;
1106         else
1107                 ring->write_ptr++;
1108 
1109         return tx_cb_ptr;
1110 }
1111 
1112 /* Simple helper to free a control block's resources */
1113 static void bcmgenet_free_cb(struct enet_cb *cb)
1114 {
1115         dev_kfree_skb_any(cb->skb);
1116         cb->skb = NULL;
1117         dma_unmap_addr_set(cb, dma_addr, 0);
1118 }
1119 
1120 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1121 {
1122         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1123                                  INTRL2_CPU_MASK_SET);
1124 }
1125 
1126 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1127 {
1128         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1129                                  INTRL2_CPU_MASK_CLEAR);
1130 }
1131 
1132 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1133 {
1134         bcmgenet_intrl2_1_writel(ring->priv,
1135                                  1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1136                                  INTRL2_CPU_MASK_SET);
1137 }
1138 
1139 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1140 {
1141         bcmgenet_intrl2_1_writel(ring->priv,
1142                                  1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1143                                  INTRL2_CPU_MASK_CLEAR);
1144 }
1145 
1146 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1147 {
1148         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1149                                  INTRL2_CPU_MASK_SET);
1150 }
1151 
1152 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1153 {
1154         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1155                                  INTRL2_CPU_MASK_CLEAR);
1156 }
1157 
1158 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1159 {
1160         bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1161                                  INTRL2_CPU_MASK_CLEAR);
1162 }
1163 
1164 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1165 {
1166         bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1167                                  INTRL2_CPU_MASK_SET);
1168 }
1169 
1170 /* Unlocked version of the reclaim routine */
1171 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1172                                           struct bcmgenet_tx_ring *ring)
1173 {
1174         struct bcmgenet_priv *priv = netdev_priv(dev);
1175         struct device *kdev = &priv->pdev->dev;
1176         struct enet_cb *tx_cb_ptr;
1177         struct netdev_queue *txq;
1178         unsigned int pkts_compl = 0;
1179         unsigned int bytes_compl = 0;
1180         unsigned int c_index;
1181         unsigned int txbds_ready;
1182         unsigned int txbds_processed = 0;
1183 
1184         /* Compute how many buffers are transmitted since last xmit call */
1185         c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
1186         c_index &= DMA_C_INDEX_MASK;
1187 
1188         if (likely(c_index >= ring->c_index))
1189                 txbds_ready = c_index - ring->c_index;
1190         else
1191                 txbds_ready = (DMA_C_INDEX_MASK + 1) - ring->c_index + c_index;
1192 
1193         netif_dbg(priv, tx_done, dev,
1194                   "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1195                   __func__, ring->index, ring->c_index, c_index, txbds_ready);
1196 
1197         /* Reclaim transmitted buffers */
1198         while (txbds_processed < txbds_ready) {
1199                 tx_cb_ptr = &priv->tx_cbs[ring->clean_ptr];
1200                 if (tx_cb_ptr->skb) {
1201                         pkts_compl++;
1202                         bytes_compl += GENET_CB(tx_cb_ptr->skb)->bytes_sent;
1203                         dma_unmap_single(kdev,
1204                                          dma_unmap_addr(tx_cb_ptr, dma_addr),
1205                                          dma_unmap_len(tx_cb_ptr, dma_len),
1206                                          DMA_TO_DEVICE);
1207                         bcmgenet_free_cb(tx_cb_ptr);
1208                 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
1209                         dma_unmap_page(kdev,
1210                                        dma_unmap_addr(tx_cb_ptr, dma_addr),
1211                                        dma_unmap_len(tx_cb_ptr, dma_len),
1212                                        DMA_TO_DEVICE);
1213                         dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1214                 }
1215 
1216                 txbds_processed++;
1217                 if (likely(ring->clean_ptr < ring->end_ptr))
1218                         ring->clean_ptr++;
1219                 else
1220                         ring->clean_ptr = ring->cb_ptr;
1221         }
1222 
1223         ring->free_bds += txbds_processed;
1224         ring->c_index = (ring->c_index + txbds_processed) & DMA_C_INDEX_MASK;
1225 
1226         dev->stats.tx_packets += pkts_compl;
1227         dev->stats.tx_bytes += bytes_compl;
1228 
1229         txq = netdev_get_tx_queue(dev, ring->queue);
1230         netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
1231 
1232         if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1233                 if (netif_tx_queue_stopped(txq))
1234                         netif_tx_wake_queue(txq);
1235         }
1236 
1237         return pkts_compl;
1238 }
1239 
1240 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1241                                 struct bcmgenet_tx_ring *ring)
1242 {
1243         unsigned int released;
1244         unsigned long flags;
1245 
1246         spin_lock_irqsave(&ring->lock, flags);
1247         released = __bcmgenet_tx_reclaim(dev, ring);
1248         spin_unlock_irqrestore(&ring->lock, flags);
1249 
1250         return released;
1251 }
1252 
1253 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1254 {
1255         struct bcmgenet_tx_ring *ring =
1256                 container_of(napi, struct bcmgenet_tx_ring, napi);
1257         unsigned int work_done = 0;
1258 
1259         work_done = bcmgenet_tx_reclaim(ring->priv->dev, ring);
1260 
1261         if (work_done == 0) {
1262                 napi_complete(napi);
1263                 ring->int_enable(ring);
1264 
1265                 return 0;
1266         }
1267 
1268         return budget;
1269 }
1270 
1271 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1272 {
1273         struct bcmgenet_priv *priv = netdev_priv(dev);
1274         int i;
1275 
1276         if (netif_is_multiqueue(dev)) {
1277                 for (i = 0; i < priv->hw_params->tx_queues; i++)
1278                         bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1279         }
1280 
1281         bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1282 }
1283 
1284 /* Transmits a single SKB (either head of a fragment or a single SKB)
1285  * caller must hold priv->lock
1286  */
1287 static int bcmgenet_xmit_single(struct net_device *dev,
1288                                 struct sk_buff *skb,
1289                                 u16 dma_desc_flags,
1290                                 struct bcmgenet_tx_ring *ring)
1291 {
1292         struct bcmgenet_priv *priv = netdev_priv(dev);
1293         struct device *kdev = &priv->pdev->dev;
1294         struct enet_cb *tx_cb_ptr;
1295         unsigned int skb_len;
1296         dma_addr_t mapping;
1297         u32 length_status;
1298         int ret;
1299 
1300         tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1301 
1302         if (unlikely(!tx_cb_ptr))
1303                 BUG();
1304 
1305         tx_cb_ptr->skb = skb;
1306 
1307         skb_len = skb_headlen(skb);
1308 
1309         mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1310         ret = dma_mapping_error(kdev, mapping);
1311         if (ret) {
1312                 priv->mib.tx_dma_failed++;
1313                 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1314                 dev_kfree_skb(skb);
1315                 return ret;
1316         }
1317 
1318         dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1319         dma_unmap_len_set(tx_cb_ptr, dma_len, skb_len);
1320         length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1321                         (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1322                         DMA_TX_APPEND_CRC;
1323 
1324         if (skb->ip_summed == CHECKSUM_PARTIAL)
1325                 length_status |= DMA_TX_DO_CSUM;
1326 
1327         dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1328 
1329         return 0;
1330 }
1331 
1332 /* Transmit a SKB fragment */
1333 static int bcmgenet_xmit_frag(struct net_device *dev,
1334                               skb_frag_t *frag,
1335                               u16 dma_desc_flags,
1336                               struct bcmgenet_tx_ring *ring)
1337 {
1338         struct bcmgenet_priv *priv = netdev_priv(dev);
1339         struct device *kdev = &priv->pdev->dev;
1340         struct enet_cb *tx_cb_ptr;
1341         unsigned int frag_size;
1342         dma_addr_t mapping;
1343         int ret;
1344 
1345         tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1346 
1347         if (unlikely(!tx_cb_ptr))
1348                 BUG();
1349 
1350         tx_cb_ptr->skb = NULL;
1351 
1352         frag_size = skb_frag_size(frag);
1353 
1354         mapping = skb_frag_dma_map(kdev, frag, 0, frag_size, DMA_TO_DEVICE);
1355         ret = dma_mapping_error(kdev, mapping);
1356         if (ret) {
1357                 priv->mib.tx_dma_failed++;
1358                 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
1359                           __func__);
1360                 return ret;
1361         }
1362 
1363         dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1364         dma_unmap_len_set(tx_cb_ptr, dma_len, frag_size);
1365 
1366         dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
1367                     (frag_size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1368                     (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1369 
1370         return 0;
1371 }
1372 
1373 /* Reallocate the SKB to put enough headroom in front of it and insert
1374  * the transmit checksum offsets in the descriptors
1375  */
1376 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1377                                             struct sk_buff *skb)
1378 {
1379         struct status_64 *status = NULL;
1380         struct sk_buff *new_skb;
1381         u16 offset;
1382         u8 ip_proto;
1383         u16 ip_ver;
1384         u32 tx_csum_info;
1385 
1386         if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1387                 /* If 64 byte status block enabled, must make sure skb has
1388                  * enough headroom for us to insert 64B status block.
1389                  */
1390                 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1391                 dev_kfree_skb(skb);
1392                 if (!new_skb) {
1393                         dev->stats.tx_dropped++;
1394                         return NULL;
1395                 }
1396                 skb = new_skb;
1397         }
1398 
1399         skb_push(skb, sizeof(*status));
1400         status = (struct status_64 *)skb->data;
1401 
1402         if (skb->ip_summed  == CHECKSUM_PARTIAL) {
1403                 ip_ver = htons(skb->protocol);
1404                 switch (ip_ver) {
1405                 case ETH_P_IP:
1406                         ip_proto = ip_hdr(skb)->protocol;
1407                         break;
1408                 case ETH_P_IPV6:
1409                         ip_proto = ipv6_hdr(skb)->nexthdr;
1410                         break;
1411                 default:
1412                         return skb;
1413                 }
1414 
1415                 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1416                 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1417                                 (offset + skb->csum_offset);
1418 
1419                 /* Set the length valid bit for TCP and UDP and just set
1420                  * the special UDP flag for IPv4, else just set to 0.
1421                  */
1422                 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1423                         tx_csum_info |= STATUS_TX_CSUM_LV;
1424                         if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1425                                 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1426                 } else {
1427                         tx_csum_info = 0;
1428                 }
1429 
1430                 status->tx_csum_info = tx_csum_info;
1431         }
1432 
1433         return skb;
1434 }
1435 
1436 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1437 {
1438         struct bcmgenet_priv *priv = netdev_priv(dev);
1439         struct bcmgenet_tx_ring *ring = NULL;
1440         struct netdev_queue *txq;
1441         unsigned long flags = 0;
1442         int nr_frags, index;
1443         u16 dma_desc_flags;
1444         int ret;
1445         int i;
1446 
1447         index = skb_get_queue_mapping(skb);
1448         /* Mapping strategy:
1449          * queue_mapping = 0, unclassified, packet xmited through ring16
1450          * queue_mapping = 1, goes to ring 0. (highest priority queue
1451          * queue_mapping = 2, goes to ring 1.
1452          * queue_mapping = 3, goes to ring 2.
1453          * queue_mapping = 4, goes to ring 3.
1454          */
1455         if (index == 0)
1456                 index = DESC_INDEX;
1457         else
1458                 index -= 1;
1459 
1460         ring = &priv->tx_rings[index];
1461         txq = netdev_get_tx_queue(dev, ring->queue);
1462 
1463         nr_frags = skb_shinfo(skb)->nr_frags;
1464 
1465         spin_lock_irqsave(&ring->lock, flags);
1466         if (ring->free_bds <= (nr_frags + 1)) {
1467                 if (!netif_tx_queue_stopped(txq)) {
1468                         netif_tx_stop_queue(txq);
1469                         netdev_err(dev,
1470                                    "%s: tx ring %d full when queue %d awake\n",
1471                                    __func__, index, ring->queue);
1472                 }
1473                 ret = NETDEV_TX_BUSY;
1474                 goto out;
1475         }
1476 
1477         if (skb_padto(skb, ETH_ZLEN)) {
1478                 ret = NETDEV_TX_OK;
1479                 goto out;
1480         }
1481 
1482         /* Retain how many bytes will be sent on the wire, without TSB inserted
1483          * by transmit checksum offload
1484          */
1485         GENET_CB(skb)->bytes_sent = skb->len;
1486 
1487         /* set the SKB transmit checksum */
1488         if (priv->desc_64b_en) {
1489                 skb = bcmgenet_put_tx_csum(dev, skb);
1490                 if (!skb) {
1491                         ret = NETDEV_TX_OK;
1492                         goto out;
1493                 }
1494         }
1495 
1496         dma_desc_flags = DMA_SOP;
1497         if (nr_frags == 0)
1498                 dma_desc_flags |= DMA_EOP;
1499 
1500         /* Transmit single SKB or head of fragment list */
1501         ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1502         if (ret) {
1503                 ret = NETDEV_TX_OK;
1504                 goto out;
1505         }
1506 
1507         /* xmit fragment */
1508         for (i = 0; i < nr_frags; i++) {
1509                 ret = bcmgenet_xmit_frag(dev,
1510                                          &skb_shinfo(skb)->frags[i],
1511                                          (i == nr_frags - 1) ? DMA_EOP : 0,
1512                                          ring);
1513                 if (ret) {
1514                         ret = NETDEV_TX_OK;
1515                         goto out;
1516                 }
1517         }
1518 
1519         skb_tx_timestamp(skb);
1520 
1521         /* Decrement total BD count and advance our write pointer */
1522         ring->free_bds -= nr_frags + 1;
1523         ring->prod_index += nr_frags + 1;
1524         ring->prod_index &= DMA_P_INDEX_MASK;
1525 
1526         netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
1527 
1528         if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
1529                 netif_tx_stop_queue(txq);
1530 
1531         if (!skb->xmit_more || netif_xmit_stopped(txq))
1532                 /* Packets are ready, update producer index */
1533                 bcmgenet_tdma_ring_writel(priv, ring->index,
1534                                           ring->prod_index, TDMA_PROD_INDEX);
1535 out:
1536         spin_unlock_irqrestore(&ring->lock, flags);
1537 
1538         return ret;
1539 }
1540 
1541 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1542                                           struct enet_cb *cb)
1543 {
1544         struct device *kdev = &priv->pdev->dev;
1545         struct sk_buff *skb;
1546         struct sk_buff *rx_skb;
1547         dma_addr_t mapping;
1548 
1549         /* Allocate a new Rx skb */
1550         skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1551         if (!skb) {
1552                 priv->mib.alloc_rx_buff_failed++;
1553                 netif_err(priv, rx_err, priv->dev,
1554                           "%s: Rx skb allocation failed\n", __func__);
1555                 return NULL;
1556         }
1557 
1558         /* DMA-map the new Rx skb */
1559         mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1560                                  DMA_FROM_DEVICE);
1561         if (dma_mapping_error(kdev, mapping)) {
1562                 priv->mib.rx_dma_failed++;
1563                 dev_kfree_skb_any(skb);
1564                 netif_err(priv, rx_err, priv->dev,
1565                           "%s: Rx skb DMA mapping failed\n", __func__);
1566                 return NULL;
1567         }
1568 
1569         /* Grab the current Rx skb from the ring and DMA-unmap it */
1570         rx_skb = cb->skb;
1571         if (likely(rx_skb))
1572                 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
1573                                  priv->rx_buf_len, DMA_FROM_DEVICE);
1574 
1575         /* Put the new Rx skb on the ring */
1576         cb->skb = skb;
1577         dma_unmap_addr_set(cb, dma_addr, mapping);
1578         dmadesc_set_addr(priv, cb->bd_addr, mapping);
1579 
1580         /* Return the current Rx skb to caller */
1581         return rx_skb;
1582 }
1583 
1584 /* bcmgenet_desc_rx - descriptor based rx process.
1585  * this could be called from bottom half, or from NAPI polling method.
1586  */
1587 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1588                                      unsigned int budget)
1589 {
1590         struct bcmgenet_priv *priv = ring->priv;
1591         struct net_device *dev = priv->dev;
1592         struct enet_cb *cb;
1593         struct sk_buff *skb;
1594         u32 dma_length_status;
1595         unsigned long dma_flag;
1596         int len;
1597         unsigned int rxpktprocessed = 0, rxpkttoprocess;
1598         unsigned int p_index;
1599         unsigned int discards;
1600         unsigned int chksum_ok = 0;
1601 
1602         p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
1603 
1604         discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1605                    DMA_P_INDEX_DISCARD_CNT_MASK;
1606         if (discards > ring->old_discards) {
1607                 discards = discards - ring->old_discards;
1608                 dev->stats.rx_missed_errors += discards;
1609                 dev->stats.rx_errors += discards;
1610                 ring->old_discards += discards;
1611 
1612                 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1613                 if (ring->old_discards >= 0xC000) {
1614                         ring->old_discards = 0;
1615                         bcmgenet_rdma_ring_writel(priv, ring->index, 0,
1616                                                   RDMA_PROD_INDEX);
1617                 }
1618         }
1619 
1620         p_index &= DMA_P_INDEX_MASK;
1621 
1622         if (likely(p_index >= ring->c_index))
1623                 rxpkttoprocess = p_index - ring->c_index;
1624         else
1625                 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) - ring->c_index +
1626                                  p_index;
1627 
1628         netif_dbg(priv, rx_status, dev,
1629                   "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1630 
1631         while ((rxpktprocessed < rxpkttoprocess) &&
1632                (rxpktprocessed < budget)) {
1633                 cb = &priv->rx_cbs[ring->read_ptr];
1634                 skb = bcmgenet_rx_refill(priv, cb);
1635 
1636                 if (unlikely(!skb)) {
1637                         dev->stats.rx_dropped++;
1638                         goto next;
1639                 }
1640 
1641                 if (!priv->desc_64b_en) {
1642                         dma_length_status =
1643                                 dmadesc_get_length_status(priv, cb->bd_addr);
1644                 } else {
1645                         struct status_64 *status;
1646 
1647                         status = (struct status_64 *)skb->data;
1648                         dma_length_status = status->length_status;
1649                 }
1650 
1651                 /* DMA flags and length are still valid no matter how
1652                  * we got the Receive Status Vector (64B RSB or register)
1653                  */
1654                 dma_flag = dma_length_status & 0xffff;
1655                 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1656 
1657                 netif_dbg(priv, rx_status, dev,
1658                           "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1659                           __func__, p_index, ring->c_index,
1660                           ring->read_ptr, dma_length_status);
1661 
1662                 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1663                         netif_err(priv, rx_status, dev,
1664                                   "dropping fragmented packet!\n");
1665                         dev->stats.rx_errors++;
1666                         dev_kfree_skb_any(skb);
1667                         goto next;
1668                 }
1669 
1670                 /* report errors */
1671                 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1672                                                 DMA_RX_OV |
1673                                                 DMA_RX_NO |
1674                                                 DMA_RX_LG |
1675                                                 DMA_RX_RXER))) {
1676                         netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1677                                   (unsigned int)dma_flag);
1678                         if (dma_flag & DMA_RX_CRC_ERROR)
1679                                 dev->stats.rx_crc_errors++;
1680                         if (dma_flag & DMA_RX_OV)
1681                                 dev->stats.rx_over_errors++;
1682                         if (dma_flag & DMA_RX_NO)
1683                                 dev->stats.rx_frame_errors++;
1684                         if (dma_flag & DMA_RX_LG)
1685                                 dev->stats.rx_length_errors++;
1686                         dev->stats.rx_errors++;
1687                         dev_kfree_skb_any(skb);
1688                         goto next;
1689                 } /* error packet */
1690 
1691                 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1692                              priv->desc_rxchk_en;
1693 
1694                 skb_put(skb, len);
1695                 if (priv->desc_64b_en) {
1696                         skb_pull(skb, 64);
1697                         len -= 64;
1698                 }
1699 
1700                 if (likely(chksum_ok))
1701                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1702 
1703                 /* remove hardware 2bytes added for IP alignment */
1704                 skb_pull(skb, 2);
1705                 len -= 2;
1706 
1707                 if (priv->crc_fwd_en) {
1708                         skb_trim(skb, len - ETH_FCS_LEN);
1709                         len -= ETH_FCS_LEN;
1710                 }
1711 
1712                 /*Finish setting up the received SKB and send it to the kernel*/
1713                 skb->protocol = eth_type_trans(skb, priv->dev);
1714                 dev->stats.rx_packets++;
1715                 dev->stats.rx_bytes += len;
1716                 if (dma_flag & DMA_RX_MULT)
1717                         dev->stats.multicast++;
1718 
1719                 /* Notify kernel */
1720                 napi_gro_receive(&ring->napi, skb);
1721                 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1722 
1723 next:
1724                 rxpktprocessed++;
1725                 if (likely(ring->read_ptr < ring->end_ptr))
1726                         ring->read_ptr++;
1727                 else
1728                         ring->read_ptr = ring->cb_ptr;
1729 
1730                 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
1731                 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1732         }
1733 
1734         return rxpktprocessed;
1735 }
1736 
1737 /* Rx NAPI polling method */
1738 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1739 {
1740         struct bcmgenet_rx_ring *ring = container_of(napi,
1741                         struct bcmgenet_rx_ring, napi);
1742         unsigned int work_done;
1743 
1744         work_done = bcmgenet_desc_rx(ring, budget);
1745 
1746         if (work_done < budget) {
1747                 napi_complete_done(napi, work_done);
1748                 ring->int_enable(ring);
1749         }
1750 
1751         return work_done;
1752 }
1753 
1754 /* Assign skb to RX DMA descriptor. */
1755 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1756                                      struct bcmgenet_rx_ring *ring)
1757 {
1758         struct enet_cb *cb;
1759         struct sk_buff *skb;
1760         int i;
1761 
1762         netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1763 
1764         /* loop here for each buffer needing assign */
1765         for (i = 0; i < ring->size; i++) {
1766                 cb = ring->cbs + i;
1767                 skb = bcmgenet_rx_refill(priv, cb);
1768                 if (skb)
1769                         dev_kfree_skb_any(skb);
1770                 if (!cb->skb)
1771                         return -ENOMEM;
1772         }
1773 
1774         return 0;
1775 }
1776 
1777 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1778 {
1779         struct device *kdev = &priv->pdev->dev;
1780         struct enet_cb *cb;
1781         int i;
1782 
1783         for (i = 0; i < priv->num_rx_bds; i++) {
1784                 cb = &priv->rx_cbs[i];
1785 
1786                 if (dma_unmap_addr(cb, dma_addr)) {
1787                         dma_unmap_single(kdev,
1788                                          dma_unmap_addr(cb, dma_addr),
1789                                          priv->rx_buf_len, DMA_FROM_DEVICE);
1790                         dma_unmap_addr_set(cb, dma_addr, 0);
1791                 }
1792 
1793                 if (cb->skb)
1794                         bcmgenet_free_cb(cb);
1795         }
1796 }
1797 
1798 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
1799 {
1800         u32 reg;
1801 
1802         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1803         if (enable)
1804                 reg |= mask;
1805         else
1806                 reg &= ~mask;
1807         bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1808 
1809         /* UniMAC stops on a packet boundary, wait for a full-size packet
1810          * to be processed
1811          */
1812         if (enable == 0)
1813                 usleep_range(1000, 2000);
1814 }
1815 
1816 static int reset_umac(struct bcmgenet_priv *priv)
1817 {
1818         struct device *kdev = &priv->pdev->dev;
1819         unsigned int timeout = 0;
1820         u32 reg;
1821 
1822         /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1823         bcmgenet_rbuf_ctrl_set(priv, 0);
1824         udelay(10);
1825 
1826         /* disable MAC while updating its registers */
1827         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1828 
1829         /* issue soft reset, wait for it to complete */
1830         bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1831         while (timeout++ < 1000) {
1832                 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1833                 if (!(reg & CMD_SW_RESET))
1834                         return 0;
1835 
1836                 udelay(1);
1837         }
1838 
1839         if (timeout == 1000) {
1840                 dev_err(kdev,
1841                         "timeout waiting for MAC to come out of reset\n");
1842                 return -ETIMEDOUT;
1843         }
1844 
1845         return 0;
1846 }
1847 
1848 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1849 {
1850         /* Mask all interrupts.*/
1851         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1852         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1853         bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1854         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1855         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1856         bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1857 }
1858 
1859 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
1860 {
1861         u32 int0_enable = 0;
1862 
1863         /* Monitor cable plug/unplugged event for internal PHY, external PHY
1864          * and MoCA PHY
1865          */
1866         if (priv->internal_phy) {
1867                 int0_enable |= UMAC_IRQ_LINK_EVENT;
1868         } else if (priv->ext_phy) {
1869                 int0_enable |= UMAC_IRQ_LINK_EVENT;
1870         } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1871                 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
1872                         int0_enable |= UMAC_IRQ_LINK_EVENT;
1873         }
1874         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1875 }
1876 
1877 static int init_umac(struct bcmgenet_priv *priv)
1878 {
1879         struct device *kdev = &priv->pdev->dev;
1880         int ret;
1881         u32 reg;
1882         u32 int0_enable = 0;
1883         u32 int1_enable = 0;
1884         int i;
1885 
1886         dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1887 
1888         ret = reset_umac(priv);
1889         if (ret)
1890                 return ret;
1891 
1892         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1893         /* clear tx/rx counter */
1894         bcmgenet_umac_writel(priv,
1895                              MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1896                              UMAC_MIB_CTRL);
1897         bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1898 
1899         bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1900 
1901         /* init rx registers, enable ip header optimization */
1902         reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1903         reg |= RBUF_ALIGN_2B;
1904         bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1905 
1906         if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1907                 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1908 
1909         bcmgenet_intr_disable(priv);
1910 
1911         /* Enable Rx default queue 16 interrupts */
1912         int0_enable |= UMAC_IRQ_RXDMA_DONE;
1913 
1914         /* Enable Tx default queue 16 interrupts */
1915         int0_enable |= UMAC_IRQ_TXDMA_DONE;
1916 
1917         /* Configure backpressure vectors for MoCA */
1918         if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1919                 reg = bcmgenet_bp_mc_get(priv);
1920                 reg |= BIT(priv->hw_params->bp_in_en_shift);
1921 
1922                 /* bp_mask: back pressure mask */
1923                 if (netif_is_multiqueue(priv->dev))
1924                         reg |= priv->hw_params->bp_in_mask;
1925                 else
1926                         reg &= ~priv->hw_params->bp_in_mask;
1927                 bcmgenet_bp_mc_set(priv, reg);
1928         }
1929 
1930         /* Enable MDIO interrupts on GENET v3+ */
1931         if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1932                 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1933 
1934         /* Enable Rx priority queue interrupts */
1935         for (i = 0; i < priv->hw_params->rx_queues; ++i)
1936                 int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i));
1937 
1938         /* Enable Tx priority queue interrupts */
1939         for (i = 0; i < priv->hw_params->tx_queues; ++i)
1940                 int1_enable |= (1 << i);
1941 
1942         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1943         bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
1944 
1945         /* Enable rx/tx engine.*/
1946         dev_dbg(kdev, "done init umac\n");
1947 
1948         return 0;
1949 }
1950 
1951 /* Initialize a Tx ring along with corresponding hardware registers */
1952 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1953                                   unsigned int index, unsigned int size,
1954                                   unsigned int start_ptr, unsigned int end_ptr)
1955 {
1956         struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1957         u32 words_per_bd = WORDS_PER_BD(priv);
1958         u32 flow_period_val = 0;
1959 
1960         spin_lock_init(&ring->lock);
1961         ring->priv = priv;
1962         ring->index = index;
1963         if (index == DESC_INDEX) {
1964                 ring->queue = 0;
1965                 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1966                 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1967         } else {
1968                 ring->queue = index + 1;
1969                 ring->int_enable = bcmgenet_tx_ring_int_enable;
1970                 ring->int_disable = bcmgenet_tx_ring_int_disable;
1971         }
1972         ring->cbs = priv->tx_cbs + start_ptr;
1973         ring->size = size;
1974         ring->clean_ptr = start_ptr;
1975         ring->c_index = 0;
1976         ring->free_bds = size;
1977         ring->write_ptr = start_ptr;
1978         ring->cb_ptr = start_ptr;
1979         ring->end_ptr = end_ptr - 1;
1980         ring->prod_index = 0;
1981 
1982         /* Set flow period for ring != 16 */
1983         if (index != DESC_INDEX)
1984                 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1985 
1986         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1987         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1988         bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1989         /* Disable rate control for now */
1990         bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
1991                                   TDMA_FLOW_PERIOD);
1992         bcmgenet_tdma_ring_writel(priv, index,
1993                                   ((size << DMA_RING_SIZE_SHIFT) |
1994                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1995 
1996         /* Set start and end address, read and write pointers */
1997         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
1998                                   DMA_START_ADDR);
1999         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2000                                   TDMA_READ_PTR);
2001         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2002                                   TDMA_WRITE_PTR);
2003         bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2004                                   DMA_END_ADDR);
2005 }
2006 
2007 /* Initialize a RDMA ring */
2008 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
2009                                  unsigned int index, unsigned int size,
2010                                  unsigned int start_ptr, unsigned int end_ptr)
2011 {
2012         struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
2013         u32 words_per_bd = WORDS_PER_BD(priv);
2014         int ret;
2015 
2016         ring->priv = priv;
2017         ring->index = index;
2018         if (index == DESC_INDEX) {
2019                 ring->int_enable = bcmgenet_rx_ring16_int_enable;
2020                 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2021         } else {
2022                 ring->int_enable = bcmgenet_rx_ring_int_enable;
2023                 ring->int_disable = bcmgenet_rx_ring_int_disable;
2024         }
2025         ring->cbs = priv->rx_cbs + start_ptr;
2026         ring->size = size;
2027         ring->c_index = 0;
2028         ring->read_ptr = start_ptr;
2029         ring->cb_ptr = start_ptr;
2030         ring->end_ptr = end_ptr - 1;
2031 
2032         ret = bcmgenet_alloc_rx_buffers(priv, ring);
2033         if (ret)
2034                 return ret;
2035 
2036         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2037         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2038         bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2039         bcmgenet_rdma_ring_writel(priv, index,
2040                                   ((size << DMA_RING_SIZE_SHIFT) |
2041                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2042         bcmgenet_rdma_ring_writel(priv, index,
2043                                   (DMA_FC_THRESH_LO <<
2044                                    DMA_XOFF_THRESHOLD_SHIFT) |
2045                                    DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
2046 
2047         /* Set start and end address, read and write pointers */
2048         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2049                                   DMA_START_ADDR);
2050         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2051                                   RDMA_READ_PTR);
2052         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2053                                   RDMA_WRITE_PTR);
2054         bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2055                                   DMA_END_ADDR);
2056 
2057         return ret;
2058 }
2059 
2060 static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv)
2061 {
2062         unsigned int i;
2063         struct bcmgenet_tx_ring *ring;
2064 
2065         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2066                 ring = &priv->tx_rings[i];
2067                 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
2068         }
2069 
2070         ring = &priv->tx_rings[DESC_INDEX];
2071         netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
2072 }
2073 
2074 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2075 {
2076         unsigned int i;
2077         struct bcmgenet_tx_ring *ring;
2078 
2079         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2080                 ring = &priv->tx_rings[i];
2081                 napi_enable(&ring->napi);
2082         }
2083 
2084         ring = &priv->tx_rings[DESC_INDEX];
2085         napi_enable(&ring->napi);
2086 }
2087 
2088 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2089 {
2090         unsigned int i;
2091         struct bcmgenet_tx_ring *ring;
2092 
2093         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2094                 ring = &priv->tx_rings[i];
2095                 napi_disable(&ring->napi);
2096         }
2097 
2098         ring = &priv->tx_rings[DESC_INDEX];
2099         napi_disable(&ring->napi);
2100 }
2101 
2102 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2103 {
2104         unsigned int i;
2105         struct bcmgenet_tx_ring *ring;
2106 
2107         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2108                 ring = &priv->tx_rings[i];
2109                 netif_napi_del(&ring->napi);
2110         }
2111 
2112         ring = &priv->tx_rings[DESC_INDEX];
2113         netif_napi_del(&ring->napi);
2114 }
2115 
2116 /* Initialize Tx queues
2117  *
2118  * Queues 0-3 are priority-based, each one has 32 descriptors,
2119  * with queue 0 being the highest priority queue.
2120  *
2121  * Queue 16 is the default Tx queue with
2122  * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
2123  *
2124  * The transmit control block pool is then partitioned as follows:
2125  * - Tx queue 0 uses tx_cbs[0..31]
2126  * - Tx queue 1 uses tx_cbs[32..63]
2127  * - Tx queue 2 uses tx_cbs[64..95]
2128  * - Tx queue 3 uses tx_cbs[96..127]
2129  * - Tx queue 16 uses tx_cbs[128..255]
2130  */
2131 static void bcmgenet_init_tx_queues(struct net_device *dev)
2132 {
2133         struct bcmgenet_priv *priv = netdev_priv(dev);
2134         u32 i, dma_enable;
2135         u32 dma_ctrl, ring_cfg;
2136         u32 dma_priority[3] = {0, 0, 0};
2137 
2138         dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2139         dma_enable = dma_ctrl & DMA_EN;
2140         dma_ctrl &= ~DMA_EN;
2141         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2142 
2143         dma_ctrl = 0;
2144         ring_cfg = 0;
2145 
2146         /* Enable strict priority arbiter mode */
2147         bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2148 
2149         /* Initialize Tx priority queues */
2150         for (i = 0; i < priv->hw_params->tx_queues; i++) {
2151                 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2152                                       i * priv->hw_params->tx_bds_per_q,
2153                                       (i + 1) * priv->hw_params->tx_bds_per_q);
2154                 ring_cfg |= (1 << i);
2155                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2156                 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2157                         ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
2158         }
2159 
2160         /* Initialize Tx default queue 16 */
2161         bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
2162                               priv->hw_params->tx_queues *
2163                               priv->hw_params->tx_bds_per_q,
2164                               TOTAL_DESC);
2165         ring_cfg |= (1 << DESC_INDEX);
2166         dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2167         dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2168                 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2169                  DMA_PRIO_REG_SHIFT(DESC_INDEX));
2170 
2171         /* Set Tx queue priorities */
2172         bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2173         bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2174         bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2175 
2176         /* Initialize Tx NAPI */
2177         bcmgenet_init_tx_napi(priv);
2178 
2179         /* Enable Tx queues */
2180         bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
2181 
2182         /* Enable Tx DMA */
2183         if (dma_enable)
2184                 dma_ctrl |= DMA_EN;
2185         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2186 }
2187 
2188 static void bcmgenet_init_rx_napi(struct bcmgenet_priv *priv)
2189 {
2190         unsigned int i;
2191         struct bcmgenet_rx_ring *ring;
2192 
2193         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2194                 ring = &priv->rx_rings[i];
2195                 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2196         }
2197 
2198         ring = &priv->rx_rings[DESC_INDEX];
2199         netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2200 }
2201 
2202 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2203 {
2204         unsigned int i;
2205         struct bcmgenet_rx_ring *ring;
2206 
2207         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2208                 ring = &priv->rx_rings[i];
2209                 napi_enable(&ring->napi);
2210         }
2211 
2212         ring = &priv->rx_rings[DESC_INDEX];
2213         napi_enable(&ring->napi);
2214 }
2215 
2216 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2217 {
2218         unsigned int i;
2219         struct bcmgenet_rx_ring *ring;
2220 
2221         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2222                 ring = &priv->rx_rings[i];
2223                 napi_disable(&ring->napi);
2224         }
2225 
2226         ring = &priv->rx_rings[DESC_INDEX];
2227         napi_disable(&ring->napi);
2228 }
2229 
2230 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2231 {
2232         unsigned int i;
2233         struct bcmgenet_rx_ring *ring;
2234 
2235         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2236                 ring = &priv->rx_rings[i];
2237                 netif_napi_del(&ring->napi);
2238         }
2239 
2240         ring = &priv->rx_rings[DESC_INDEX];
2241         netif_napi_del(&ring->napi);
2242 }
2243 
2244 /* Initialize Rx queues
2245  *
2246  * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2247  * used to direct traffic to these queues.
2248  *
2249  * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2250  */
2251 static int bcmgenet_init_rx_queues(struct net_device *dev)
2252 {
2253         struct bcmgenet_priv *priv = netdev_priv(dev);
2254         u32 i;
2255         u32 dma_enable;
2256         u32 dma_ctrl;
2257         u32 ring_cfg;
2258         int ret;
2259 
2260         dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2261         dma_enable = dma_ctrl & DMA_EN;
2262         dma_ctrl &= ~DMA_EN;
2263         bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2264 
2265         dma_ctrl = 0;
2266         ring_cfg = 0;
2267 
2268         /* Initialize Rx priority queues */
2269         for (i = 0; i < priv->hw_params->rx_queues; i++) {
2270                 ret = bcmgenet_init_rx_ring(priv, i,
2271                                             priv->hw_params->rx_bds_per_q,
2272                                             i * priv->hw_params->rx_bds_per_q,
2273                                             (i + 1) *
2274                                             priv->hw_params->rx_bds_per_q);
2275                 if (ret)
2276                         return ret;
2277 
2278                 ring_cfg |= (1 << i);
2279                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2280         }
2281 
2282         /* Initialize Rx default queue 16 */
2283         ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2284                                     priv->hw_params->rx_queues *
2285                                     priv->hw_params->rx_bds_per_q,
2286                                     TOTAL_DESC);
2287         if (ret)
2288                 return ret;
2289 
2290         ring_cfg |= (1 << DESC_INDEX);
2291         dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2292 
2293         /* Initialize Rx NAPI */
2294         bcmgenet_init_rx_napi(priv);
2295 
2296         /* Enable rings */
2297         bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2298 
2299         /* Configure ring as descriptor ring and re-enable DMA if enabled */
2300         if (dma_enable)
2301                 dma_ctrl |= DMA_EN;
2302         bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2303 
2304         return 0;
2305 }
2306 
2307 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2308 {
2309         int ret = 0;
2310         int timeout = 0;
2311         u32 reg;
2312         u32 dma_ctrl;
2313         int i;
2314 
2315         /* Disable TDMA to stop add more frames in TX DMA */
2316         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2317         reg &= ~DMA_EN;
2318         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2319 
2320         /* Check TDMA status register to confirm TDMA is disabled */
2321         while (timeout++ < DMA_TIMEOUT_VAL) {
2322                 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2323                 if (reg & DMA_DISABLED)
2324                         break;
2325 
2326                 udelay(1);
2327         }
2328 
2329         if (timeout == DMA_TIMEOUT_VAL) {
2330                 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2331                 ret = -ETIMEDOUT;
2332         }
2333 
2334         /* Wait 10ms for packet drain in both tx and rx dma */
2335         usleep_range(10000, 20000);
2336 
2337         /* Disable RDMA */
2338         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2339         reg &= ~DMA_EN;
2340         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2341 
2342         timeout = 0;
2343         /* Check RDMA status register to confirm RDMA is disabled */
2344         while (timeout++ < DMA_TIMEOUT_VAL) {
2345                 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2346                 if (reg & DMA_DISABLED)
2347                         break;
2348 
2349                 udelay(1);
2350         }
2351 
2352         if (timeout == DMA_TIMEOUT_VAL) {
2353                 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2354                 ret = -ETIMEDOUT;
2355         }
2356 
2357         dma_ctrl = 0;
2358         for (i = 0; i < priv->hw_params->rx_queues; i++)
2359                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2360         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2361         reg &= ~dma_ctrl;
2362         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2363 
2364         dma_ctrl = 0;
2365         for (i = 0; i < priv->hw_params->tx_queues; i++)
2366                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2367         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2368         reg &= ~dma_ctrl;
2369         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2370 
2371         return ret;
2372 }
2373 
2374 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2375 {
2376         int i;
2377         struct netdev_queue *txq;
2378 
2379         bcmgenet_fini_rx_napi(priv);
2380         bcmgenet_fini_tx_napi(priv);
2381 
2382         /* disable DMA */
2383         bcmgenet_dma_teardown(priv);
2384 
2385         for (i = 0; i < priv->num_tx_bds; i++) {
2386                 if (priv->tx_cbs[i].skb != NULL) {
2387                         dev_kfree_skb(priv->tx_cbs[i].skb);
2388                         priv->tx_cbs[i].skb = NULL;
2389                 }
2390         }
2391 
2392         for (i = 0; i < priv->hw_params->tx_queues; i++) {
2393                 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue);
2394                 netdev_tx_reset_queue(txq);
2395         }
2396 
2397         txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue);
2398         netdev_tx_reset_queue(txq);
2399 
2400         bcmgenet_free_rx_buffers(priv);
2401         kfree(priv->rx_cbs);
2402         kfree(priv->tx_cbs);
2403 }
2404 
2405 /* init_edma: Initialize DMA control register */
2406 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2407 {
2408         int ret;
2409         unsigned int i;
2410         struct enet_cb *cb;
2411 
2412         netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2413 
2414         /* Initialize common Rx ring structures */
2415         priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2416         priv->num_rx_bds = TOTAL_DESC;
2417         priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2418                                GFP_KERNEL);
2419         if (!priv->rx_cbs)
2420                 return -ENOMEM;
2421 
2422         for (i = 0; i < priv->num_rx_bds; i++) {
2423                 cb = priv->rx_cbs + i;
2424                 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2425         }
2426 
2427         /* Initialize common TX ring structures */
2428         priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2429         priv->num_tx_bds = TOTAL_DESC;
2430         priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
2431                                GFP_KERNEL);
2432         if (!priv->tx_cbs) {
2433                 kfree(priv->rx_cbs);
2434                 return -ENOMEM;
2435         }
2436 
2437         for (i = 0; i < priv->num_tx_bds; i++) {
2438                 cb = priv->tx_cbs + i;
2439                 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2440         }
2441 
2442         /* Init rDma */
2443         bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2444 
2445         /* Initialize Rx queues */
2446         ret = bcmgenet_init_rx_queues(priv->dev);
2447         if (ret) {
2448                 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2449                 bcmgenet_free_rx_buffers(priv);
2450                 kfree(priv->rx_cbs);
2451                 kfree(priv->tx_cbs);
2452                 return ret;
2453         }
2454 
2455         /* Init tDma */
2456         bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2457 
2458         /* Initialize Tx queues */
2459         bcmgenet_init_tx_queues(priv->dev);
2460 
2461         return 0;
2462 }
2463 
2464 /* Interrupt bottom half */
2465 static void bcmgenet_irq_task(struct work_struct *work)
2466 {
2467         struct bcmgenet_priv *priv = container_of(
2468                         work, struct bcmgenet_priv, bcmgenet_irq_work);
2469 
2470         netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2471 
2472         if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
2473                 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
2474                 netif_dbg(priv, wol, priv->dev,
2475                           "magic packet detected, waking up\n");
2476                 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2477         }
2478 
2479         /* Link UP/DOWN event */
2480         if (priv->irq0_stat & UMAC_IRQ_LINK_EVENT) {
2481                 phy_mac_interrupt(priv->phydev,
2482                                   !!(priv->irq0_stat & UMAC_IRQ_LINK_UP));
2483                 priv->irq0_stat &= ~UMAC_IRQ_LINK_EVENT;
2484         }
2485 }
2486 
2487 /* bcmgenet_isr1: handle Rx and Tx priority queues */
2488 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2489 {
2490         struct bcmgenet_priv *priv = dev_id;
2491         struct bcmgenet_rx_ring *rx_ring;
2492         struct bcmgenet_tx_ring *tx_ring;
2493         unsigned int index;
2494 
2495         /* Save irq status for bottom-half processing. */
2496         priv->irq1_stat =
2497                 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
2498                 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2499 
2500         /* clear interrupts */
2501         bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
2502 
2503         netif_dbg(priv, intr, priv->dev,
2504                   "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
2505 
2506         /* Check Rx priority queue interrupts */
2507         for (index = 0; index < priv->hw_params->rx_queues; index++) {
2508                 if (!(priv->irq1_stat & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2509                         continue;
2510 
2511                 rx_ring = &priv->rx_rings[index];
2512 
2513                 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2514                         rx_ring->int_disable(rx_ring);
2515                         __napi_schedule_irqoff(&rx_ring->napi);
2516                 }
2517         }
2518 
2519         /* Check Tx priority queue interrupts */
2520         for (index = 0; index < priv->hw_params->tx_queues; index++) {
2521                 if (!(priv->irq1_stat & BIT(index)))
2522                         continue;
2523 
2524                 tx_ring = &priv->tx_rings[index];
2525 
2526                 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2527                         tx_ring->int_disable(tx_ring);
2528                         __napi_schedule_irqoff(&tx_ring->napi);
2529                 }
2530         }
2531 
2532         return IRQ_HANDLED;
2533 }
2534 
2535 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
2536 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2537 {
2538         struct bcmgenet_priv *priv = dev_id;
2539         struct bcmgenet_rx_ring *rx_ring;
2540         struct bcmgenet_tx_ring *tx_ring;
2541 
2542         /* Save irq status for bottom-half processing. */
2543         priv->irq0_stat =
2544                 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2545                 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2546 
2547         /* clear interrupts */
2548         bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
2549 
2550         netif_dbg(priv, intr, priv->dev,
2551                   "IRQ=0x%x\n", priv->irq0_stat);
2552 
2553         if (priv->irq0_stat & UMAC_IRQ_RXDMA_DONE) {
2554                 rx_ring = &priv->rx_rings[DESC_INDEX];
2555 
2556                 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2557                         rx_ring->int_disable(rx_ring);
2558                         __napi_schedule_irqoff(&rx_ring->napi);
2559                 }
2560         }
2561 
2562         if (priv->irq0_stat & UMAC_IRQ_TXDMA_DONE) {
2563                 tx_ring = &priv->tx_rings[DESC_INDEX];
2564 
2565                 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2566                         tx_ring->int_disable(tx_ring);
2567                         __napi_schedule_irqoff(&tx_ring->napi);
2568                 }
2569         }
2570 
2571         if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2572                                 UMAC_IRQ_PHY_DET_F |
2573                                 UMAC_IRQ_LINK_EVENT |
2574                                 UMAC_IRQ_HFB_SM |
2575                                 UMAC_IRQ_HFB_MM |
2576                                 UMAC_IRQ_MPD_R)) {
2577                 /* all other interested interrupts handled in bottom half */
2578                 schedule_work(&priv->bcmgenet_irq_work);
2579         }
2580 
2581         if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2582             priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
2583                 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2584                 wake_up(&priv->wq);
2585         }
2586 
2587         return IRQ_HANDLED;
2588 }
2589 
2590 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2591 {
2592         struct bcmgenet_priv *priv = dev_id;
2593 
2594         pm_wakeup_event(&priv->pdev->dev, 0);
2595 
2596         return IRQ_HANDLED;
2597 }
2598 
2599 #ifdef CONFIG_NET_POLL_CONTROLLER
2600 static void bcmgenet_poll_controller(struct net_device *dev)
2601 {
2602         struct bcmgenet_priv *priv = netdev_priv(dev);
2603 
2604         /* Invoke the main RX/TX interrupt handler */
2605         disable_irq(priv->irq0);
2606         bcmgenet_isr0(priv->irq0, priv);
2607         enable_irq(priv->irq0);
2608 
2609         /* And the interrupt handler for RX/TX priority queues */
2610         disable_irq(priv->irq1);
2611         bcmgenet_isr1(priv->irq1, priv);
2612         enable_irq(priv->irq1);
2613 }
2614 #endif
2615 
2616 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2617 {
2618         u32 reg;
2619 
2620         reg = bcmgenet_rbuf_ctrl_get(priv);
2621         reg |= BIT(1);
2622         bcmgenet_rbuf_ctrl_set(priv, reg);
2623         udelay(10);
2624 
2625         reg &= ~BIT(1);
2626         bcmgenet_rbuf_ctrl_set(priv, reg);
2627         udelay(10);
2628 }
2629 
2630 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
2631                                  unsigned char *addr)
2632 {
2633         bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2634                         (addr[2] << 8) | addr[3], UMAC_MAC0);
2635         bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2636 }
2637 
2638 /* Returns a reusable dma control register value */
2639 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2640 {
2641         u32 reg;
2642         u32 dma_ctrl;
2643 
2644         /* disable DMA */
2645         dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2646         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2647         reg &= ~dma_ctrl;
2648         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2649 
2650         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2651         reg &= ~dma_ctrl;
2652         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2653 
2654         bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2655         udelay(10);
2656         bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2657 
2658         return dma_ctrl;
2659 }
2660 
2661 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2662 {
2663         u32 reg;
2664 
2665         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2666         reg |= dma_ctrl;
2667         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2668 
2669         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2670         reg |= dma_ctrl;
2671         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2672 }
2673 
2674 /* bcmgenet_hfb_clear
2675  *
2676  * Clear Hardware Filter Block and disable all filtering.
2677  */
2678 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2679 {
2680         u32 i;
2681 
2682         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2683         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2684         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2685 
2686         for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2687                 bcmgenet_rdma_writel(priv, 0x0, i);
2688 
2689         for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2690                 bcmgenet_hfb_reg_writel(priv, 0x0,
2691                                         HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2692 
2693         for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2694                         priv->hw_params->hfb_filter_size; i++)
2695                 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2696 }
2697 
2698 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2699 {
2700         if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2701                 return;
2702 
2703         bcmgenet_hfb_clear(priv);
2704 }
2705 
2706 static void bcmgenet_netif_start(struct net_device *dev)
2707 {
2708         struct bcmgenet_priv *priv = netdev_priv(dev);
2709 
2710         /* Start the network engine */
2711         bcmgenet_enable_rx_napi(priv);
2712         bcmgenet_enable_tx_napi(priv);
2713 
2714         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2715 
2716         netif_tx_start_all_queues(dev);
2717 
2718         /* Monitor link interrupts now */
2719         bcmgenet_link_intr_enable(priv);
2720 
2721         phy_start(priv->phydev);
2722 }
2723 
2724 static int bcmgenet_open(struct net_device *dev)
2725 {
2726         struct bcmgenet_priv *priv = netdev_priv(dev);
2727         unsigned long dma_ctrl;
2728         u32 reg;
2729         int ret;
2730 
2731         netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2732 
2733         /* Turn on the clock */
2734         clk_prepare_enable(priv->clk);
2735 
2736         /* If this is an internal GPHY, power it back on now, before UniMAC is
2737          * brought out of reset as absolutely no UniMAC activity is allowed
2738          */
2739         if (priv->internal_phy)
2740                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2741 
2742         /* take MAC out of reset */
2743         bcmgenet_umac_reset(priv);
2744 
2745         ret = init_umac(priv);
2746         if (ret)
2747                 goto err_clk_disable;
2748 
2749         /* disable ethernet MAC while updating its registers */
2750         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2751 
2752         /* Make sure we reflect the value of CRC_CMD_FWD */
2753         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2754         priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2755 
2756         bcmgenet_set_hw_addr(priv, dev->dev_addr);
2757 
2758         if (priv->internal_phy) {
2759                 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2760                 reg |= EXT_ENERGY_DET_MASK;
2761                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2762         }
2763 
2764         /* Disable RX/TX DMA and flush TX queues */
2765         dma_ctrl = bcmgenet_dma_disable(priv);
2766 
2767         /* Reinitialize TDMA and RDMA and SW housekeeping */
2768         ret = bcmgenet_init_dma(priv);
2769         if (ret) {
2770                 netdev_err(dev, "failed to initialize DMA\n");
2771                 goto err_clk_disable;
2772         }
2773 
2774         /* Always enable ring 16 - descriptor ring */
2775         bcmgenet_enable_dma(priv, dma_ctrl);
2776 
2777         /* HFB init */
2778         bcmgenet_hfb_init(priv);
2779 
2780         ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2781                           dev->name, priv);
2782         if (ret < 0) {
2783                 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2784                 goto err_fini_dma;
2785         }
2786 
2787         ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2788                           dev->name, priv);
2789         if (ret < 0) {
2790                 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2791                 goto err_irq0;
2792         }
2793 
2794         ret = bcmgenet_mii_probe(dev);
2795         if (ret) {
2796                 netdev_err(dev, "failed to connect to PHY\n");
2797                 goto err_irq1;
2798         }
2799 
2800         bcmgenet_netif_start(dev);
2801 
2802         return 0;
2803 
2804 err_irq1:
2805         free_irq(priv->irq1, priv);
2806 err_irq0:
2807         free_irq(priv->irq0, priv);
2808 err_fini_dma:
2809         bcmgenet_fini_dma(priv);
2810 err_clk_disable:
2811         clk_disable_unprepare(priv->clk);
2812         return ret;
2813 }
2814 
2815 static void bcmgenet_netif_stop(struct net_device *dev)
2816 {
2817         struct bcmgenet_priv *priv = netdev_priv(dev);
2818 
2819         netif_tx_stop_all_queues(dev);
2820         phy_stop(priv->phydev);
2821         bcmgenet_intr_disable(priv);
2822         bcmgenet_disable_rx_napi(priv);
2823         bcmgenet_disable_tx_napi(priv);
2824 
2825         /* Wait for pending work items to complete. Since interrupts are
2826          * disabled no new work will be scheduled.
2827          */
2828         cancel_work_sync(&priv->bcmgenet_irq_work);
2829 
2830         priv->old_link = -1;
2831         priv->old_speed = -1;
2832         priv->old_duplex = -1;
2833         priv->old_pause = -1;
2834 }
2835 
2836 static int bcmgenet_close(struct net_device *dev)
2837 {
2838         struct bcmgenet_priv *priv = netdev_priv(dev);
2839         int ret;
2840 
2841         netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2842 
2843         bcmgenet_netif_stop(dev);
2844 
2845         /* Really kill the PHY state machine and disconnect from it */
2846         phy_disconnect(priv->phydev);
2847 
2848         /* Disable MAC receive */
2849         umac_enable_set(priv, CMD_RX_EN, false);
2850 
2851         ret = bcmgenet_dma_teardown(priv);
2852         if (ret)
2853                 return ret;
2854 
2855         /* Disable MAC transmit. TX DMA disabled have to done before this */
2856         umac_enable_set(priv, CMD_TX_EN, false);
2857 
2858         /* tx reclaim */
2859         bcmgenet_tx_reclaim_all(dev);
2860         bcmgenet_fini_dma(priv);
2861 
2862         free_irq(priv->irq0, priv);
2863         free_irq(priv->irq1, priv);
2864 
2865         if (priv->internal_phy)
2866                 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2867 
2868         clk_disable_unprepare(priv->clk);
2869 
2870         return ret;
2871 }
2872 
2873 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
2874 {
2875         struct bcmgenet_priv *priv = ring->priv;
2876         u32 p_index, c_index, intsts, intmsk;
2877         struct netdev_queue *txq;
2878         unsigned int free_bds;
2879         unsigned long flags;
2880         bool txq_stopped;
2881 
2882         if (!netif_msg_tx_err(priv))
2883                 return;
2884 
2885         txq = netdev_get_tx_queue(priv->dev, ring->queue);
2886 
2887         spin_lock_irqsave(&ring->lock, flags);
2888         if (ring->index == DESC_INDEX) {
2889                 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2890                 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
2891         } else {
2892                 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2893                 intmsk = 1 << ring->index;
2894         }
2895         c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
2896         p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
2897         txq_stopped = netif_tx_queue_stopped(txq);
2898         free_bds = ring->free_bds;
2899         spin_unlock_irqrestore(&ring->lock, flags);
2900 
2901         netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
2902                   "TX queue status: %s, interrupts: %s\n"
2903                   "(sw)free_bds: %d (sw)size: %d\n"
2904                   "(sw)p_index: %d (hw)p_index: %d\n"
2905                   "(sw)c_index: %d (hw)c_index: %d\n"
2906                   "(sw)clean_p: %d (sw)write_p: %d\n"
2907                   "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
2908                   ring->index, ring->queue,
2909                   txq_stopped ? "stopped" : "active",
2910                   intsts & intmsk ? "enabled" : "disabled",
2911                   free_bds, ring->size,
2912                   ring->prod_index, p_index & DMA_P_INDEX_MASK,
2913                   ring->c_index, c_index & DMA_C_INDEX_MASK,
2914                   ring->clean_ptr, ring->write_ptr,
2915                   ring->cb_ptr, ring->end_ptr);
2916 }
2917 
2918 static void bcmgenet_timeout(struct net_device *dev)
2919 {
2920         struct bcmgenet_priv *priv = netdev_priv(dev);
2921         u32 int0_enable = 0;
2922         u32 int1_enable = 0;
2923         unsigned int q;
2924 
2925         netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2926 
2927         for (q = 0; q < priv->hw_params->tx_queues; q++)
2928                 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
2929         bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
2930 
2931         bcmgenet_tx_reclaim_all(dev);
2932 
2933         for (q = 0; q < priv->hw_params->tx_queues; q++)
2934                 int1_enable |= (1 << q);
2935 
2936         int0_enable = UMAC_IRQ_TXDMA_DONE;
2937 
2938         /* Re-enable TX interrupts if disabled */
2939         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2940         bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
2941 
2942         netif_trans_update(dev);
2943 
2944         dev->stats.tx_errors++;
2945 
2946         netif_tx_wake_all_queues(dev);
2947 }
2948 
2949 #define MAX_MC_COUNT    16
2950 
2951 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2952                                          unsigned char *addr,
2953                                          int *i,
2954                                          int *mc)
2955 {
2956         u32 reg;
2957 
2958         bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
2959                              UMAC_MDF_ADDR + (*i * 4));
2960         bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
2961                              addr[4] << 8 | addr[5],
2962                              UMAC_MDF_ADDR + ((*i + 1) * 4));
2963         reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2964         reg |= (1 << (MAX_MC_COUNT - *mc));
2965         bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2966         *i += 2;
2967         (*mc)++;
2968 }
2969 
2970 static void bcmgenet_set_rx_mode(struct net_device *dev)
2971 {
2972         struct bcmgenet_priv *priv = netdev_priv(dev);
2973         struct netdev_hw_addr *ha;
2974         int i, mc;
2975         u32 reg;
2976 
2977         netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2978 
2979         /* Promiscuous mode */
2980         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2981         if (dev->flags & IFF_PROMISC) {
2982                 reg |= CMD_PROMISC;
2983                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2984                 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2985                 return;
2986         } else {
2987                 reg &= ~CMD_PROMISC;
2988                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2989         }
2990 
2991         /* UniMac doesn't support ALLMULTI */
2992         if (dev->flags & IFF_ALLMULTI) {
2993                 netdev_warn(dev, "ALLMULTI is not supported\n");
2994                 return;
2995         }
2996 
2997         /* update MDF filter */
2998         i = 0;
2999         mc = 0;
3000         /* Broadcast */
3001         bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
3002         /* my own address.*/
3003         bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
3004         /* Unicast list*/
3005         if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
3006                 return;
3007 
3008         if (!netdev_uc_empty(dev))
3009                 netdev_for_each_uc_addr(ha, dev)
3010                         bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3011         /* Multicast */
3012         if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
3013                 return;
3014 
3015         netdev_for_each_mc_addr(ha, dev)
3016                 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3017 }
3018 
3019 /* Set the hardware MAC address. */
3020 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3021 {
3022         struct sockaddr *addr = p;
3023 
3024         /* Setting the MAC address at the hardware level is not possible
3025          * without disabling the UniMAC RX/TX enable bits.
3026          */
3027         if (netif_running(dev))
3028                 return -EBUSY;
3029 
3030         ether_addr_copy(dev->dev_addr, addr->sa_data);
3031 
3032         return 0;
3033 }
3034 
3035 static const struct net_device_ops bcmgenet_netdev_ops = {
3036         .ndo_open               = bcmgenet_open,
3037         .ndo_stop               = bcmgenet_close,
3038         .ndo_start_xmit         = bcmgenet_xmit,
3039         .ndo_tx_timeout         = bcmgenet_timeout,
3040         .ndo_set_rx_mode        = bcmgenet_set_rx_mode,
3041         .ndo_set_mac_address    = bcmgenet_set_mac_addr,
3042         .ndo_do_ioctl           = bcmgenet_ioctl,
3043         .ndo_set_features       = bcmgenet_set_features,
3044 #ifdef CONFIG_NET_POLL_CONTROLLER
3045         .ndo_poll_controller    = bcmgenet_poll_controller,
3046 #endif
3047 };
3048 
3049 /* Array of GENET hardware parameters/characteristics */
3050 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3051         [GENET_V1] = {
3052                 .tx_queues = 0,
3053                 .tx_bds_per_q = 0,
3054                 .rx_queues = 0,
3055                 .rx_bds_per_q = 0,
3056                 .bp_in_en_shift = 16,
3057                 .bp_in_mask = 0xffff,
3058                 .hfb_filter_cnt = 16,
3059                 .qtag_mask = 0x1F,
3060                 .hfb_offset = 0x1000,
3061                 .rdma_offset = 0x2000,
3062                 .tdma_offset = 0x3000,
3063                 .words_per_bd = 2,
3064         },
3065         [GENET_V2] = {
3066                 .tx_queues = 4,
3067                 .tx_bds_per_q = 32,
3068                 .rx_queues = 0,
3069                 .rx_bds_per_q = 0,
3070                 .bp_in_en_shift = 16,
3071                 .bp_in_mask = 0xffff,
3072                 .hfb_filter_cnt = 16,
3073                 .qtag_mask = 0x1F,
3074                 .tbuf_offset = 0x0600,
3075                 .hfb_offset = 0x1000,
3076                 .hfb_reg_offset = 0x2000,
3077                 .rdma_offset = 0x3000,
3078                 .tdma_offset = 0x4000,
3079                 .words_per_bd = 2,
3080                 .flags = GENET_HAS_EXT,
3081         },
3082         [GENET_V3] = {
3083                 .tx_queues = 4,
3084                 .tx_bds_per_q = 32,
3085                 .rx_queues = 0,
3086                 .rx_bds_per_q = 0,
3087                 .bp_in_en_shift = 17,
3088                 .bp_in_mask = 0x1ffff,
3089                 .hfb_filter_cnt = 48,
3090                 .hfb_filter_size = 128,
3091                 .qtag_mask = 0x3F,
3092                 .tbuf_offset = 0x0600,
3093                 .hfb_offset = 0x8000,
3094                 .hfb_reg_offset = 0xfc00,
3095                 .rdma_offset = 0x10000,
3096                 .tdma_offset = 0x11000,
3097                 .words_per_bd = 2,
3098                 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3099                          GENET_HAS_MOCA_LINK_DET,
3100         },
3101         [GENET_V4] = {
3102                 .tx_queues = 4,
3103                 .tx_bds_per_q = 32,
3104                 .rx_queues = 0,
3105                 .rx_bds_per_q = 0,
3106                 .bp_in_en_shift = 17,
3107                 .bp_in_mask = 0x1ffff,
3108                 .hfb_filter_cnt = 48,
3109                 .hfb_filter_size = 128,
3110                 .qtag_mask = 0x3F,
3111                 .tbuf_offset = 0x0600,
3112                 .hfb_offset = 0x8000,
3113                 .hfb_reg_offset = 0xfc00,
3114                 .rdma_offset = 0x2000,
3115                 .tdma_offset = 0x4000,
3116                 .words_per_bd = 3,
3117                 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3118                          GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3119         },
3120 };
3121 
3122 /* Infer hardware parameters from the detected GENET version */
3123 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3124 {
3125         struct bcmgenet_hw_params *params;
3126         u32 reg;
3127         u8 major;
3128         u16 gphy_rev;
3129 
3130         if (GENET_IS_V4(priv)) {
3131                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3132                 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3133                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3134                 priv->version = GENET_V4;
3135         } else if (GENET_IS_V3(priv)) {
3136                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3137                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3138                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3139                 priv->version = GENET_V3;
3140         } else if (GENET_IS_V2(priv)) {
3141                 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3142                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3143                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3144                 priv->version = GENET_V2;
3145         } else if (GENET_IS_V1(priv)) {
3146                 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3147                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3148                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3149                 priv->version = GENET_V1;
3150         }
3151 
3152         /* enum genet_version starts at 1 */
3153         priv->hw_params = &bcmgenet_hw_params[priv->version];
3154         params = priv->hw_params;
3155 
3156         /* Read GENET HW version */
3157         reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3158         major = (reg >> 24 & 0x0f);
3159         if (major == 5)
3160                 major = 4;
3161         else if (major == 0)
3162                 major = 1;
3163         if (major != priv->version) {
3164                 dev_err(&priv->pdev->dev,
3165                         "GENET version mismatch, got: %d, configured for: %d\n",
3166                         major, priv->version);
3167         }
3168 
3169         /* Print the GENET core version */
3170         dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3171                  major, (reg >> 16) & 0x0f, reg & 0xffff);
3172 
3173         /* Store the integrated PHY revision for the MDIO probing function
3174          * to pass this information to the PHY driver. The PHY driver expects
3175          * to find the PHY major revision in bits 15:8 while the GENET register
3176          * stores that information in bits 7:0, account for that.
3177          *
3178          * On newer chips, starting with PHY revision G0, a new scheme is
3179          * deployed similar to the Starfighter 2 switch with GPHY major
3180          * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3181          * is reserved as well as special value 0x01ff, we have a small
3182          * heuristic to check for the new GPHY revision and re-arrange things
3183          * so the GPHY driver is happy.
3184          */
3185         gphy_rev = reg & 0xffff;
3186 
3187         /* This is the good old scheme, just GPHY major, no minor nor patch */
3188         if ((gphy_rev & 0xf0) != 0)
3189                 priv->gphy_rev = gphy_rev << 8;
3190 
3191         /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3192         else if ((gphy_rev & 0xff00) != 0)
3193                 priv->gphy_rev = gphy_rev;
3194 
3195         /* This is reserved so should require special treatment */
3196         else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3197                 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3198                 return;
3199         }
3200 
3201 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3202         if (!(params->flags & GENET_HAS_40BITS))
3203                 pr_warn("GENET does not support 40-bits PA\n");
3204 #endif
3205 
3206         pr_debug("Configuration for version: %d\n"
3207                 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3208                 "BP << en: %2d, BP msk: 0x%05x\n"
3209                 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3210                 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3211                 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3212                 "Words/BD: %d\n",
3213                 priv->version,
3214                 params->tx_queues, params->tx_bds_per_q,
3215                 params->rx_queues, params->rx_bds_per_q,
3216                 params->bp_in_en_shift, params->bp_in_mask,
3217                 params->hfb_filter_cnt, params->qtag_mask,
3218                 params->tbuf_offset, params->hfb_offset,
3219                 params->hfb_reg_offset,
3220                 params->rdma_offset, params->tdma_offset,
3221                 params->words_per_bd);
3222 }
3223 
3224 static const struct of_device_id bcmgenet_match[] = {
3225         { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3226         { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3227         { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3228         { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3229         { },
3230 };
3231 MODULE_DEVICE_TABLE(of, bcmgenet_match);
3232 
3233 static int bcmgenet_probe(struct platform_device *pdev)
3234 {
3235         struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3236         struct device_node *dn = pdev->dev.of_node;
3237         const struct of_device_id *of_id = NULL;
3238         struct bcmgenet_priv *priv;
3239         struct net_device *dev;
3240         const void *macaddr;
3241         struct resource *r;
3242         int err = -EIO;
3243 
3244         /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3245         dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3246                                  GENET_MAX_MQ_CNT + 1);
3247         if (!dev) {
3248                 dev_err(&pdev->dev, "can't allocate net device\n");
3249                 return -ENOMEM;
3250         }
3251 
3252         if (dn) {
3253                 of_id = of_match_node(bcmgenet_match, dn);
3254                 if (!of_id)
3255                         return -EINVAL;
3256         }
3257 
3258         priv = netdev_priv(dev);
3259         priv->irq0 = platform_get_irq(pdev, 0);
3260         priv->irq1 = platform_get_irq(pdev, 1);
3261         priv->wol_irq = platform_get_irq(pdev, 2);
3262         if (!priv->irq0 || !priv->irq1) {
3263                 dev_err(&pdev->dev, "can't find IRQs\n");
3264                 err = -EINVAL;
3265                 goto err;
3266         }
3267 
3268         if (dn) {
3269                 macaddr = of_get_mac_address(dn);
3270                 if (!macaddr) {
3271                         dev_err(&pdev->dev, "can't find MAC address\n");
3272                         err = -EINVAL;
3273                         goto err;
3274                 }
3275         } else {
3276                 macaddr = pd->mac_address;
3277         }
3278 
3279         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3280         priv->base = devm_ioremap_resource(&pdev->dev, r);
3281         if (IS_ERR(priv->base)) {
3282                 err = PTR_ERR(priv->base);
3283                 goto err;
3284         }
3285 
3286         SET_NETDEV_DEV(dev, &pdev->dev);
3287         dev_set_drvdata(&pdev->dev, dev);
3288         ether_addr_copy(dev->dev_addr, macaddr);
3289         dev->watchdog_timeo = 2 * HZ;
3290         dev->ethtool_ops = &bcmgenet_ethtool_ops;
3291         dev->netdev_ops = &bcmgenet_netdev_ops;
3292 
3293         priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3294 
3295         /* Set hardware features */
3296         dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3297                 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3298 
3299         /* Request the WOL interrupt and advertise suspend if available */
3300         priv->wol_irq_disabled = true;
3301         err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3302                                dev->name, priv);
3303         if (!err)
3304                 device_set_wakeup_capable(&pdev->dev, 1);
3305 
3306         /* Set the needed headroom to account for any possible
3307          * features enabling/disabling at runtime
3308          */
3309         dev->needed_headroom += 64;
3310 
3311         netdev_boot_setup_check(dev);
3312 
3313         priv->dev = dev;
3314         priv->pdev = pdev;
3315         if (of_id)
3316                 priv->version = (enum bcmgenet_version)of_id->data;
3317         else
3318                 priv->version = pd->genet_version;
3319 
3320         priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
3321         if (IS_ERR(priv->clk)) {
3322                 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
3323                 priv->clk = NULL;
3324         }
3325 
3326         clk_prepare_enable(priv->clk);
3327 
3328         bcmgenet_set_hw_params(priv);
3329 
3330         /* Mii wait queue */
3331         init_waitqueue_head(&priv->wq);
3332         /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3333         priv->rx_buf_len = RX_BUF_LENGTH;
3334         INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3335 
3336         priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
3337         if (IS_ERR(priv->clk_wol)) {
3338                 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
3339                 priv->clk_wol = NULL;
3340         }
3341 
3342         priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3343         if (IS_ERR(priv->clk_eee)) {
3344                 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3345                 priv->clk_eee = NULL;
3346         }
3347 
3348         err = reset_umac(priv);
3349         if (err)
3350                 goto err_clk_disable;
3351 
3352         err = bcmgenet_mii_init(dev);
3353         if (err)
3354                 goto err_clk_disable;
3355 
3356         /* setup number of real queues  + 1 (GENET_V1 has 0 hardware queues
3357          * just the ring 16 descriptor based TX
3358          */
3359         netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3360         netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3361 
3362         /* libphy will determine the link state */
3363         netif_carrier_off(dev);
3364 
3365         /* Turn off the main clock, WOL clock is handled separately */
3366         clk_disable_unprepare(priv->clk);
3367 
3368         err = register_netdev(dev);
3369         if (err)
3370                 goto err;
3371 
3372         return err;
3373 
3374 err_clk_disable:
3375         clk_disable_unprepare(priv->clk);
3376 err:
3377         free_netdev(dev);
3378         return err;
3379 }
3380 
3381 static int bcmgenet_remove(struct platform_device *pdev)
3382 {
3383         struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3384 
3385         dev_set_drvdata(&pdev->dev, NULL);
3386         unregister_netdev(priv->dev);
3387         bcmgenet_mii_exit(priv->dev);
3388         free_netdev(priv->dev);
3389 
3390         return 0;
3391 }
3392 
3393 #ifdef CONFIG_PM_SLEEP
3394 static int bcmgenet_suspend(struct device *d)
3395 {
3396         struct net_device *dev = dev_get_drvdata(d);
3397         struct bcmgenet_priv *priv = netdev_priv(dev);
3398         int ret;
3399 
3400         if (!netif_running(dev))
3401                 return 0;
3402 
3403         bcmgenet_netif_stop(dev);
3404 
3405         phy_suspend(priv->phydev);
3406 
3407         netif_device_detach(dev);
3408 
3409         /* Disable MAC receive */
3410         umac_enable_set(priv, CMD_RX_EN, false);
3411 
3412         ret = bcmgenet_dma_teardown(priv);
3413         if (ret)
3414                 return ret;
3415 
3416         /* Disable MAC transmit. TX DMA disabled have to done before this */
3417         umac_enable_set(priv, CMD_TX_EN, false);
3418 
3419         /* tx reclaim */
3420         bcmgenet_tx_reclaim_all(dev);
3421         bcmgenet_fini_dma(priv);
3422 
3423         /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3424         if (device_may_wakeup(d) && priv->wolopts) {
3425                 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
3426                 clk_prepare_enable(priv->clk_wol);
3427         } else if (priv->internal_phy) {
3428                 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3429         }
3430 
3431         /* Turn off the clocks */
3432         clk_disable_unprepare(priv->clk);
3433 
3434         return ret;
3435 }
3436 
3437 static int bcmgenet_resume(struct device *d)
3438 {
3439         struct net_device *dev = dev_get_drvdata(d);
3440         struct bcmgenet_priv *priv = netdev_priv(dev);
3441         unsigned long dma_ctrl;
3442         int ret;
3443         u32 reg;
3444 
3445         if (!netif_running(dev))
3446                 return 0;
3447 
3448         /* Turn on the clock */
3449         ret = clk_prepare_enable(priv->clk);
3450         if (ret)
3451                 return ret;
3452 
3453         /* If this is an internal GPHY, power it back on now, before UniMAC is
3454          * brought out of reset as absolutely no UniMAC activity is allowed
3455          */
3456         if (priv->internal_phy)
3457                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3458 
3459         bcmgenet_umac_reset(priv);
3460 
3461         ret = init_umac(priv);
3462         if (ret)
3463                 goto out_clk_disable;
3464 
3465         /* From WOL-enabled suspend, switch to regular clock */
3466         if (priv->wolopts)
3467                 clk_disable_unprepare(priv->clk_wol);
3468 
3469         phy_init_hw(priv->phydev);
3470         /* Speed settings must be restored */
3471         bcmgenet_mii_config(priv->dev);
3472 
3473         /* disable ethernet MAC while updating its registers */
3474         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
3475 
3476         bcmgenet_set_hw_addr(priv, dev->dev_addr);
3477 
3478         if (priv->internal_phy) {
3479                 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3480                 reg |= EXT_ENERGY_DET_MASK;
3481                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3482         }
3483 
3484         if (priv->wolopts)
3485                 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3486 
3487         /* Disable RX/TX DMA and flush TX queues */
3488         dma_ctrl = bcmgenet_dma_disable(priv);
3489 
3490         /* Reinitialize TDMA and RDMA and SW housekeeping */
3491         ret = bcmgenet_init_dma(priv);
3492         if (ret) {
3493                 netdev_err(dev, "failed to initialize DMA\n");
3494                 goto out_clk_disable;
3495         }
3496 
3497         /* Always enable ring 16 - descriptor ring */
3498         bcmgenet_enable_dma(priv, dma_ctrl);
3499 
3500         netif_device_attach(dev);
3501 
3502         phy_resume(priv->phydev);
3503 
3504         if (priv->eee.eee_enabled)
3505                 bcmgenet_eee_enable_set(dev, true);
3506 
3507         bcmgenet_netif_start(dev);
3508 
3509         return 0;
3510 
3511 out_clk_disable:
3512         clk_disable_unprepare(priv->clk);
3513         return ret;
3514 }
3515 #endif /* CONFIG_PM_SLEEP */
3516 
3517 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3518 
3519 static struct platform_driver bcmgenet_driver = {
3520         .probe  = bcmgenet_probe,
3521         .remove = bcmgenet_remove,
3522         .driver = {
3523                 .name   = "bcmgenet",
3524                 .of_match_table = bcmgenet_match,
3525                 .pm     = &bcmgenet_pm_ops,
3526         },
3527 };
3528 module_platform_driver(bcmgenet_driver);
3529 
3530 MODULE_AUTHOR("Broadcom Corporation");
3531 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3532 MODULE_ALIAS("platform:bcmgenet");
3533 MODULE_LICENSE("GPL");
3534 

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