Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

  1 /* bnx2x_main.c: Broadcom Everest network driver.
  2  *
  3  * Copyright (c) 2007-2013 Broadcom Corporation
  4  *
  5  * This program is free software; you can redistribute it and/or modify
  6  * it under the terms of the GNU General Public License as published by
  7  * the Free Software Foundation.
  8  *
  9  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
 10  * Written by: Eliezer Tamir
 11  * Based on code from Michael Chan's bnx2 driver
 12  * UDP CSUM errata workaround by Arik Gendelman
 13  * Slowpath and fastpath rework by Vladislav Zolotarov
 14  * Statistics and Link management by Yitchak Gertner
 15  *
 16  */
 17 
 18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 19 
 20 #include <linux/module.h>
 21 #include <linux/moduleparam.h>
 22 #include <linux/kernel.h>
 23 #include <linux/device.h>  /* for dev_info() */
 24 #include <linux/timer.h>
 25 #include <linux/errno.h>
 26 #include <linux/ioport.h>
 27 #include <linux/slab.h>
 28 #include <linux/interrupt.h>
 29 #include <linux/pci.h>
 30 #include <linux/aer.h>
 31 #include <linux/init.h>
 32 #include <linux/netdevice.h>
 33 #include <linux/etherdevice.h>
 34 #include <linux/skbuff.h>
 35 #include <linux/dma-mapping.h>
 36 #include <linux/bitops.h>
 37 #include <linux/irq.h>
 38 #include <linux/delay.h>
 39 #include <asm/byteorder.h>
 40 #include <linux/time.h>
 41 #include <linux/ethtool.h>
 42 #include <linux/mii.h>
 43 #include <linux/if_vlan.h>
 44 #include <net/ip.h>
 45 #include <net/ipv6.h>
 46 #include <net/tcp.h>
 47 #include <net/checksum.h>
 48 #include <net/ip6_checksum.h>
 49 #include <linux/workqueue.h>
 50 #include <linux/crc32.h>
 51 #include <linux/crc32c.h>
 52 #include <linux/prefetch.h>
 53 #include <linux/zlib.h>
 54 #include <linux/io.h>
 55 #include <linux/semaphore.h>
 56 #include <linux/stringify.h>
 57 #include <linux/vmalloc.h>
 58 
 59 #include "bnx2x.h"
 60 #include "bnx2x_init.h"
 61 #include "bnx2x_init_ops.h"
 62 #include "bnx2x_cmn.h"
 63 #include "bnx2x_vfpf.h"
 64 #include "bnx2x_dcb.h"
 65 #include "bnx2x_sp.h"
 66 
 67 #include <linux/firmware.h>
 68 #include "bnx2x_fw_file_hdr.h"
 69 /* FW files */
 70 #define FW_FILE_VERSION                                 \
 71         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
 72         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
 73         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
 74         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
 75 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
 76 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
 77 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
 78 
 79 /* Time in jiffies before concluding the transmitter is hung */
 80 #define TX_TIMEOUT              (5*HZ)
 81 
 82 static char version[] =
 83         "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
 84         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 85 
 86 MODULE_AUTHOR("Eliezer Tamir");
 87 MODULE_DESCRIPTION("Broadcom NetXtreme II "
 88                    "BCM57710/57711/57711E/"
 89                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
 90                    "57840/57840_MF Driver");
 91 MODULE_LICENSE("GPL");
 92 MODULE_VERSION(DRV_MODULE_VERSION);
 93 MODULE_FIRMWARE(FW_FILE_NAME_E1);
 94 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
 95 MODULE_FIRMWARE(FW_FILE_NAME_E2);
 96 
 97 int bnx2x_num_queues;
 98 module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
 99 MODULE_PARM_DESC(num_queues,
100                  " Set number of queues (default is as a number of CPUs)");
101 
102 static int disable_tpa;
103 module_param(disable_tpa, int, S_IRUGO);
104 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
105 
106 static int int_mode;
107 module_param(int_mode, int, S_IRUGO);
108 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
109                                 "(1 INT#x; 2 MSI)");
110 
111 static int dropless_fc;
112 module_param(dropless_fc, int, S_IRUGO);
113 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
114 
115 static int mrrs = -1;
116 module_param(mrrs, int, S_IRUGO);
117 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
118 
119 static int debug;
120 module_param(debug, int, S_IRUGO);
121 MODULE_PARM_DESC(debug, " Default debug msglevel");
122 
123 static struct workqueue_struct *bnx2x_wq;
124 struct workqueue_struct *bnx2x_iov_wq;
125 
126 struct bnx2x_mac_vals {
127         u32 xmac_addr;
128         u32 xmac_val;
129         u32 emac_addr;
130         u32 emac_val;
131         u32 umac_addr;
132         u32 umac_val;
133         u32 bmac_addr;
134         u32 bmac_val[2];
135 };
136 
137 enum bnx2x_board_type {
138         BCM57710 = 0,
139         BCM57711,
140         BCM57711E,
141         BCM57712,
142         BCM57712_MF,
143         BCM57712_VF,
144         BCM57800,
145         BCM57800_MF,
146         BCM57800_VF,
147         BCM57810,
148         BCM57810_MF,
149         BCM57810_VF,
150         BCM57840_4_10,
151         BCM57840_2_20,
152         BCM57840_MF,
153         BCM57840_VF,
154         BCM57811,
155         BCM57811_MF,
156         BCM57840_O,
157         BCM57840_MFO,
158         BCM57811_VF
159 };
160 
161 /* indexed by board_type, above */
162 static struct {
163         char *name;
164 } board_info[] = {
165         [BCM57710]      = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
166         [BCM57711]      = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
167         [BCM57711E]     = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
168         [BCM57712]      = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
169         [BCM57712_MF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
170         [BCM57712_VF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
171         [BCM57800]      = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
172         [BCM57800_MF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
173         [BCM57800_VF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
174         [BCM57810]      = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
175         [BCM57810_MF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
176         [BCM57810_VF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
177         [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
178         [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
179         [BCM57840_MF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
180         [BCM57840_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
181         [BCM57811]      = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
182         [BCM57811_MF]   = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
183         [BCM57840_O]    = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
184         [BCM57840_MFO]  = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
185         [BCM57811_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
186 };
187 
188 #ifndef PCI_DEVICE_ID_NX2_57710
189 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
190 #endif
191 #ifndef PCI_DEVICE_ID_NX2_57711
192 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
193 #endif
194 #ifndef PCI_DEVICE_ID_NX2_57711E
195 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
196 #endif
197 #ifndef PCI_DEVICE_ID_NX2_57712
198 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
199 #endif
200 #ifndef PCI_DEVICE_ID_NX2_57712_MF
201 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
202 #endif
203 #ifndef PCI_DEVICE_ID_NX2_57712_VF
204 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
205 #endif
206 #ifndef PCI_DEVICE_ID_NX2_57800
207 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
208 #endif
209 #ifndef PCI_DEVICE_ID_NX2_57800_MF
210 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
211 #endif
212 #ifndef PCI_DEVICE_ID_NX2_57800_VF
213 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
214 #endif
215 #ifndef PCI_DEVICE_ID_NX2_57810
216 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
217 #endif
218 #ifndef PCI_DEVICE_ID_NX2_57810_MF
219 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
220 #endif
221 #ifndef PCI_DEVICE_ID_NX2_57840_O
222 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
223 #endif
224 #ifndef PCI_DEVICE_ID_NX2_57810_VF
225 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
226 #endif
227 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
228 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
229 #endif
230 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
231 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
232 #endif
233 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
234 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
235 #endif
236 #ifndef PCI_DEVICE_ID_NX2_57840_MF
237 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
238 #endif
239 #ifndef PCI_DEVICE_ID_NX2_57840_VF
240 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
241 #endif
242 #ifndef PCI_DEVICE_ID_NX2_57811
243 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
244 #endif
245 #ifndef PCI_DEVICE_ID_NX2_57811_MF
246 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
247 #endif
248 #ifndef PCI_DEVICE_ID_NX2_57811_VF
249 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
250 #endif
251 
252 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
253         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
254         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
255         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
272         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
273         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
274         { 0 }
275 };
276 
277 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
278 
279 /* Global resources for unloading a previously loaded device */
280 #define BNX2X_PREV_WAIT_NEEDED 1
281 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
282 static LIST_HEAD(bnx2x_prev_list);
283 
284 /* Forward declaration */
285 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
286 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
287 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
288 
289 /****************************************************************************
290 * General service functions
291 ****************************************************************************/
292 
293 static void __storm_memset_dma_mapping(struct bnx2x *bp,
294                                        u32 addr, dma_addr_t mapping)
295 {
296         REG_WR(bp,  addr, U64_LO(mapping));
297         REG_WR(bp,  addr + 4, U64_HI(mapping));
298 }
299 
300 static void storm_memset_spq_addr(struct bnx2x *bp,
301                                   dma_addr_t mapping, u16 abs_fid)
302 {
303         u32 addr = XSEM_REG_FAST_MEMORY +
304                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
305 
306         __storm_memset_dma_mapping(bp, addr, mapping);
307 }
308 
309 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
310                                   u16 pf_id)
311 {
312         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
313                 pf_id);
314         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
315                 pf_id);
316         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
317                 pf_id);
318         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
319                 pf_id);
320 }
321 
322 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
323                                  u8 enable)
324 {
325         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
326                 enable);
327         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
328                 enable);
329         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
330                 enable);
331         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
332                 enable);
333 }
334 
335 static void storm_memset_eq_data(struct bnx2x *bp,
336                                  struct event_ring_data *eq_data,
337                                 u16 pfid)
338 {
339         size_t size = sizeof(struct event_ring_data);
340 
341         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
342 
343         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
344 }
345 
346 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
347                                  u16 pfid)
348 {
349         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
350         REG_WR16(bp, addr, eq_prod);
351 }
352 
353 /* used only at init
354  * locking is done by mcp
355  */
356 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
357 {
358         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
359         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
360         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
361                                PCICFG_VENDOR_ID_OFFSET);
362 }
363 
364 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
365 {
366         u32 val;
367 
368         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
369         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
370         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
371                                PCICFG_VENDOR_ID_OFFSET);
372 
373         return val;
374 }
375 
376 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
377 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
378 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
379 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
380 #define DMAE_DP_DST_NONE        "dst_addr [none]"
381 
382 static void bnx2x_dp_dmae(struct bnx2x *bp,
383                           struct dmae_command *dmae, int msglvl)
384 {
385         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
386         int i;
387 
388         switch (dmae->opcode & DMAE_COMMAND_DST) {
389         case DMAE_CMD_DST_PCI:
390                 if (src_type == DMAE_CMD_SRC_PCI)
391                         DP(msglvl, "DMAE: opcode 0x%08x\n"
392                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
393                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
394                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
395                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
396                            dmae->comp_addr_hi, dmae->comp_addr_lo,
397                            dmae->comp_val);
398                 else
399                         DP(msglvl, "DMAE: opcode 0x%08x\n"
400                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
401                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
402                            dmae->opcode, dmae->src_addr_lo >> 2,
403                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
404                            dmae->comp_addr_hi, dmae->comp_addr_lo,
405                            dmae->comp_val);
406                 break;
407         case DMAE_CMD_DST_GRC:
408                 if (src_type == DMAE_CMD_SRC_PCI)
409                         DP(msglvl, "DMAE: opcode 0x%08x\n"
410                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
411                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
412                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
413                            dmae->len, dmae->dst_addr_lo >> 2,
414                            dmae->comp_addr_hi, dmae->comp_addr_lo,
415                            dmae->comp_val);
416                 else
417                         DP(msglvl, "DMAE: opcode 0x%08x\n"
418                            "src [%08x], len [%d*4], dst [%08x]\n"
419                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
420                            dmae->opcode, dmae->src_addr_lo >> 2,
421                            dmae->len, dmae->dst_addr_lo >> 2,
422                            dmae->comp_addr_hi, dmae->comp_addr_lo,
423                            dmae->comp_val);
424                 break;
425         default:
426                 if (src_type == DMAE_CMD_SRC_PCI)
427                         DP(msglvl, "DMAE: opcode 0x%08x\n"
428                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
429                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
430                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
431                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
432                            dmae->comp_val);
433                 else
434                         DP(msglvl, "DMAE: opcode 0x%08x\n"
435                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
436                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
437                            dmae->opcode, dmae->src_addr_lo >> 2,
438                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
439                            dmae->comp_val);
440                 break;
441         }
442 
443         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
444                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
445                    i, *(((u32 *)dmae) + i));
446 }
447 
448 /* copy command into DMAE command memory and set DMAE command go */
449 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
450 {
451         u32 cmd_offset;
452         int i;
453 
454         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
455         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
456                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
457         }
458         REG_WR(bp, dmae_reg_go_c[idx], 1);
459 }
460 
461 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
462 {
463         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
464                            DMAE_CMD_C_ENABLE);
465 }
466 
467 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
468 {
469         return opcode & ~DMAE_CMD_SRC_RESET;
470 }
471 
472 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
473                              bool with_comp, u8 comp_type)
474 {
475         u32 opcode = 0;
476 
477         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
478                    (dst_type << DMAE_COMMAND_DST_SHIFT));
479 
480         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
481 
482         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
483         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
484                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
485         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
486 
487 #ifdef __BIG_ENDIAN
488         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
489 #else
490         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
491 #endif
492         if (with_comp)
493                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
494         return opcode;
495 }
496 
497 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
498                                       struct dmae_command *dmae,
499                                       u8 src_type, u8 dst_type)
500 {
501         memset(dmae, 0, sizeof(struct dmae_command));
502 
503         /* set the opcode */
504         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
505                                          true, DMAE_COMP_PCI);
506 
507         /* fill in the completion parameters */
508         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
509         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
510         dmae->comp_val = DMAE_COMP_VAL;
511 }
512 
513 /* issue a dmae command over the init-channel and wait for completion */
514 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
515                                u32 *comp)
516 {
517         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
518         int rc = 0;
519 
520         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
521 
522         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
523          * as long as this code is called both from syscall context and
524          * from ndo_set_rx_mode() flow that may be called from BH.
525          */
526         spin_lock_bh(&bp->dmae_lock);
527 
528         /* reset completion */
529         *comp = 0;
530 
531         /* post the command on the channel used for initializations */
532         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
533 
534         /* wait for completion */
535         udelay(5);
536         while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
537 
538                 if (!cnt ||
539                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
540                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
541                         BNX2X_ERR("DMAE timeout!\n");
542                         rc = DMAE_TIMEOUT;
543                         goto unlock;
544                 }
545                 cnt--;
546                 udelay(50);
547         }
548         if (*comp & DMAE_PCI_ERR_FLAG) {
549                 BNX2X_ERR("DMAE PCI error!\n");
550                 rc = DMAE_PCI_ERROR;
551         }
552 
553 unlock:
554         spin_unlock_bh(&bp->dmae_lock);
555         return rc;
556 }
557 
558 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
559                       u32 len32)
560 {
561         int rc;
562         struct dmae_command dmae;
563 
564         if (!bp->dmae_ready) {
565                 u32 *data = bnx2x_sp(bp, wb_data[0]);
566 
567                 if (CHIP_IS_E1(bp))
568                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
569                 else
570                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
571                 return;
572         }
573 
574         /* set opcode and fixed command fields */
575         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
576 
577         /* fill in addresses and len */
578         dmae.src_addr_lo = U64_LO(dma_addr);
579         dmae.src_addr_hi = U64_HI(dma_addr);
580         dmae.dst_addr_lo = dst_addr >> 2;
581         dmae.dst_addr_hi = 0;
582         dmae.len = len32;
583 
584         /* issue the command and wait for completion */
585         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
586         if (rc) {
587                 BNX2X_ERR("DMAE returned failure %d\n", rc);
588 #ifdef BNX2X_STOP_ON_ERROR
589                 bnx2x_panic();
590 #endif
591         }
592 }
593 
594 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
595 {
596         int rc;
597         struct dmae_command dmae;
598 
599         if (!bp->dmae_ready) {
600                 u32 *data = bnx2x_sp(bp, wb_data[0]);
601                 int i;
602 
603                 if (CHIP_IS_E1(bp))
604                         for (i = 0; i < len32; i++)
605                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
606                 else
607                         for (i = 0; i < len32; i++)
608                                 data[i] = REG_RD(bp, src_addr + i*4);
609 
610                 return;
611         }
612 
613         /* set opcode and fixed command fields */
614         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
615 
616         /* fill in addresses and len */
617         dmae.src_addr_lo = src_addr >> 2;
618         dmae.src_addr_hi = 0;
619         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
620         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
621         dmae.len = len32;
622 
623         /* issue the command and wait for completion */
624         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
625         if (rc) {
626                 BNX2X_ERR("DMAE returned failure %d\n", rc);
627 #ifdef BNX2X_STOP_ON_ERROR
628                 bnx2x_panic();
629 #endif
630         }
631 }
632 
633 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
634                                       u32 addr, u32 len)
635 {
636         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
637         int offset = 0;
638 
639         while (len > dmae_wr_max) {
640                 bnx2x_write_dmae(bp, phys_addr + offset,
641                                  addr + offset, dmae_wr_max);
642                 offset += dmae_wr_max * 4;
643                 len -= dmae_wr_max;
644         }
645 
646         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
647 }
648 
649 static int bnx2x_mc_assert(struct bnx2x *bp)
650 {
651         char last_idx;
652         int i, rc = 0;
653         u32 row0, row1, row2, row3;
654 
655         /* XSTORM */
656         last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
657                            XSTORM_ASSERT_LIST_INDEX_OFFSET);
658         if (last_idx)
659                 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
660 
661         /* print the asserts */
662         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
663 
664                 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
665                               XSTORM_ASSERT_LIST_OFFSET(i));
666                 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
667                               XSTORM_ASSERT_LIST_OFFSET(i) + 4);
668                 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
669                               XSTORM_ASSERT_LIST_OFFSET(i) + 8);
670                 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
671                               XSTORM_ASSERT_LIST_OFFSET(i) + 12);
672 
673                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
674                         BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
675                                   i, row3, row2, row1, row0);
676                         rc++;
677                 } else {
678                         break;
679                 }
680         }
681 
682         /* TSTORM */
683         last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
684                            TSTORM_ASSERT_LIST_INDEX_OFFSET);
685         if (last_idx)
686                 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
687 
688         /* print the asserts */
689         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
690 
691                 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
692                               TSTORM_ASSERT_LIST_OFFSET(i));
693                 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
694                               TSTORM_ASSERT_LIST_OFFSET(i) + 4);
695                 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
696                               TSTORM_ASSERT_LIST_OFFSET(i) + 8);
697                 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
698                               TSTORM_ASSERT_LIST_OFFSET(i) + 12);
699 
700                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
701                         BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
702                                   i, row3, row2, row1, row0);
703                         rc++;
704                 } else {
705                         break;
706                 }
707         }
708 
709         /* CSTORM */
710         last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
711                            CSTORM_ASSERT_LIST_INDEX_OFFSET);
712         if (last_idx)
713                 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
714 
715         /* print the asserts */
716         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
717 
718                 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
719                               CSTORM_ASSERT_LIST_OFFSET(i));
720                 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
721                               CSTORM_ASSERT_LIST_OFFSET(i) + 4);
722                 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
723                               CSTORM_ASSERT_LIST_OFFSET(i) + 8);
724                 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
725                               CSTORM_ASSERT_LIST_OFFSET(i) + 12);
726 
727                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
728                         BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
729                                   i, row3, row2, row1, row0);
730                         rc++;
731                 } else {
732                         break;
733                 }
734         }
735 
736         /* USTORM */
737         last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
738                            USTORM_ASSERT_LIST_INDEX_OFFSET);
739         if (last_idx)
740                 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
741 
742         /* print the asserts */
743         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
744 
745                 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
746                               USTORM_ASSERT_LIST_OFFSET(i));
747                 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
748                               USTORM_ASSERT_LIST_OFFSET(i) + 4);
749                 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
750                               USTORM_ASSERT_LIST_OFFSET(i) + 8);
751                 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
752                               USTORM_ASSERT_LIST_OFFSET(i) + 12);
753 
754                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
755                         BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
756                                   i, row3, row2, row1, row0);
757                         rc++;
758                 } else {
759                         break;
760                 }
761         }
762 
763         return rc;
764 }
765 
766 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
767 #define SCRATCH_BUFFER_SIZE(bp) \
768         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
769 
770 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
771 {
772         u32 addr, val;
773         u32 mark, offset;
774         __be32 data[9];
775         int word;
776         u32 trace_shmem_base;
777         if (BP_NOMCP(bp)) {
778                 BNX2X_ERR("NO MCP - can not dump\n");
779                 return;
780         }
781         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
782                 (bp->common.bc_ver & 0xff0000) >> 16,
783                 (bp->common.bc_ver & 0xff00) >> 8,
784                 (bp->common.bc_ver & 0xff));
785 
786         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
787         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
788                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
789 
790         if (BP_PATH(bp) == 0)
791                 trace_shmem_base = bp->common.shmem_base;
792         else
793                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
794 
795         /* sanity */
796         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
797             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
798                                 SCRATCH_BUFFER_SIZE(bp)) {
799                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
800                           trace_shmem_base);
801                 return;
802         }
803 
804         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
805 
806         /* validate TRCB signature */
807         mark = REG_RD(bp, addr);
808         if (mark != MFW_TRACE_SIGNATURE) {
809                 BNX2X_ERR("Trace buffer signature is missing.");
810                 return ;
811         }
812 
813         /* read cyclic buffer pointer */
814         addr += 4;
815         mark = REG_RD(bp, addr);
816         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
817         if (mark >= trace_shmem_base || mark < addr + 4) {
818                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
819                 return;
820         }
821         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
822 
823         printk("%s", lvl);
824 
825         /* dump buffer after the mark */
826         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
827                 for (word = 0; word < 8; word++)
828                         data[word] = htonl(REG_RD(bp, offset + 4*word));
829                 data[8] = 0x0;
830                 pr_cont("%s", (char *)data);
831         }
832 
833         /* dump buffer before the mark */
834         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
835                 for (word = 0; word < 8; word++)
836                         data[word] = htonl(REG_RD(bp, offset + 4*word));
837                 data[8] = 0x0;
838                 pr_cont("%s", (char *)data);
839         }
840         printk("%s" "end of fw dump\n", lvl);
841 }
842 
843 static void bnx2x_fw_dump(struct bnx2x *bp)
844 {
845         bnx2x_fw_dump_lvl(bp, KERN_ERR);
846 }
847 
848 static void bnx2x_hc_int_disable(struct bnx2x *bp)
849 {
850         int port = BP_PORT(bp);
851         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
852         u32 val = REG_RD(bp, addr);
853 
854         /* in E1 we must use only PCI configuration space to disable
855          * MSI/MSIX capability
856          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
857          */
858         if (CHIP_IS_E1(bp)) {
859                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
860                  * Use mask register to prevent from HC sending interrupts
861                  * after we exit the function
862                  */
863                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
864 
865                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
866                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
867                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
868         } else
869                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
870                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
871                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
872                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
873 
874         DP(NETIF_MSG_IFDOWN,
875            "write %x to HC %d (addr 0x%x)\n",
876            val, port, addr);
877 
878         /* flush all outstanding writes */
879         mmiowb();
880 
881         REG_WR(bp, addr, val);
882         if (REG_RD(bp, addr) != val)
883                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
884 }
885 
886 static void bnx2x_igu_int_disable(struct bnx2x *bp)
887 {
888         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
889 
890         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
891                  IGU_PF_CONF_INT_LINE_EN |
892                  IGU_PF_CONF_ATTN_BIT_EN);
893 
894         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
895 
896         /* flush all outstanding writes */
897         mmiowb();
898 
899         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
900         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
901                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
902 }
903 
904 static void bnx2x_int_disable(struct bnx2x *bp)
905 {
906         if (bp->common.int_block == INT_BLOCK_HC)
907                 bnx2x_hc_int_disable(bp);
908         else
909                 bnx2x_igu_int_disable(bp);
910 }
911 
912 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
913 {
914         int i;
915         u16 j;
916         struct hc_sp_status_block_data sp_sb_data;
917         int func = BP_FUNC(bp);
918 #ifdef BNX2X_STOP_ON_ERROR
919         u16 start = 0, end = 0;
920         u8 cos;
921 #endif
922         if (IS_PF(bp) && disable_int)
923                 bnx2x_int_disable(bp);
924 
925         bp->stats_state = STATS_STATE_DISABLED;
926         bp->eth_stats.unrecoverable_error++;
927         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
928 
929         BNX2X_ERR("begin crash dump -----------------\n");
930 
931         /* Indices */
932         /* Common */
933         if (IS_PF(bp)) {
934                 struct host_sp_status_block *def_sb = bp->def_status_blk;
935                 int data_size, cstorm_offset;
936 
937                 BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
938                           bp->def_idx, bp->def_att_idx, bp->attn_state,
939                           bp->spq_prod_idx, bp->stats_counter);
940                 BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
941                           def_sb->atten_status_block.attn_bits,
942                           def_sb->atten_status_block.attn_bits_ack,
943                           def_sb->atten_status_block.status_block_id,
944                           def_sb->atten_status_block.attn_bits_index);
945                 BNX2X_ERR("     def (");
946                 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
947                         pr_cont("0x%x%s",
948                                 def_sb->sp_sb.index_values[i],
949                                 (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
950 
951                 data_size = sizeof(struct hc_sp_status_block_data) /
952                             sizeof(u32);
953                 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
954                 for (i = 0; i < data_size; i++)
955                         *((u32 *)&sp_sb_data + i) =
956                                 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
957                                            i * sizeof(u32));
958 
959                 pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
960                         sp_sb_data.igu_sb_id,
961                         sp_sb_data.igu_seg_id,
962                         sp_sb_data.p_func.pf_id,
963                         sp_sb_data.p_func.vnic_id,
964                         sp_sb_data.p_func.vf_id,
965                         sp_sb_data.p_func.vf_valid,
966                         sp_sb_data.state);
967         }
968 
969         for_each_eth_queue(bp, i) {
970                 struct bnx2x_fastpath *fp = &bp->fp[i];
971                 int loop;
972                 struct hc_status_block_data_e2 sb_data_e2;
973                 struct hc_status_block_data_e1x sb_data_e1x;
974                 struct hc_status_block_sm  *hc_sm_p =
975                         CHIP_IS_E1x(bp) ?
976                         sb_data_e1x.common.state_machine :
977                         sb_data_e2.common.state_machine;
978                 struct hc_index_data *hc_index_p =
979                         CHIP_IS_E1x(bp) ?
980                         sb_data_e1x.index_data :
981                         sb_data_e2.index_data;
982                 u8 data_size, cos;
983                 u32 *sb_data_p;
984                 struct bnx2x_fp_txdata txdata;
985 
986                 /* Rx */
987                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
988                           i, fp->rx_bd_prod, fp->rx_bd_cons,
989                           fp->rx_comp_prod,
990                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
991                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
992                           fp->rx_sge_prod, fp->last_max_sge,
993                           le16_to_cpu(fp->fp_hc_idx));
994 
995                 /* Tx */
996                 for_each_cos_in_tx_queue(fp, cos)
997                 {
998                         txdata = *fp->txdata_ptr[cos];
999                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
1000                                   i, txdata.tx_pkt_prod,
1001                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
1002                                   txdata.tx_bd_cons,
1003                                   le16_to_cpu(*txdata.tx_cons_sb));
1004                 }
1005 
1006                 loop = CHIP_IS_E1x(bp) ?
1007                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1008 
1009                 /* host sb data */
1010 
1011                 if (IS_FCOE_FP(fp))
1012                         continue;
1013 
1014                 BNX2X_ERR("     run indexes (");
1015                 for (j = 0; j < HC_SB_MAX_SM; j++)
1016                         pr_cont("0x%x%s",
1017                                fp->sb_running_index[j],
1018                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1019 
1020                 BNX2X_ERR("     indexes (");
1021                 for (j = 0; j < loop; j++)
1022                         pr_cont("0x%x%s",
1023                                fp->sb_index_values[j],
1024                                (j == loop - 1) ? ")" : " ");
1025 
1026                 /* VF cannot access FW refelection for status block */
1027                 if (IS_VF(bp))
1028                         continue;
1029 
1030                 /* fw sb data */
1031                 data_size = CHIP_IS_E1x(bp) ?
1032                         sizeof(struct hc_status_block_data_e1x) :
1033                         sizeof(struct hc_status_block_data_e2);
1034                 data_size /= sizeof(u32);
1035                 sb_data_p = CHIP_IS_E1x(bp) ?
1036                         (u32 *)&sb_data_e1x :
1037                         (u32 *)&sb_data_e2;
1038                 /* copy sb data in here */
1039                 for (j = 0; j < data_size; j++)
1040                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1041                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1042                                 j * sizeof(u32));
1043 
1044                 if (!CHIP_IS_E1x(bp)) {
1045                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1046                                 sb_data_e2.common.p_func.pf_id,
1047                                 sb_data_e2.common.p_func.vf_id,
1048                                 sb_data_e2.common.p_func.vf_valid,
1049                                 sb_data_e2.common.p_func.vnic_id,
1050                                 sb_data_e2.common.same_igu_sb_1b,
1051                                 sb_data_e2.common.state);
1052                 } else {
1053                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1054                                 sb_data_e1x.common.p_func.pf_id,
1055                                 sb_data_e1x.common.p_func.vf_id,
1056                                 sb_data_e1x.common.p_func.vf_valid,
1057                                 sb_data_e1x.common.p_func.vnic_id,
1058                                 sb_data_e1x.common.same_igu_sb_1b,
1059                                 sb_data_e1x.common.state);
1060                 }
1061 
1062                 /* SB_SMs data */
1063                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1064                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1065                                 j, hc_sm_p[j].__flags,
1066                                 hc_sm_p[j].igu_sb_id,
1067                                 hc_sm_p[j].igu_seg_id,
1068                                 hc_sm_p[j].time_to_expire,
1069                                 hc_sm_p[j].timer_value);
1070                 }
1071 
1072                 /* Indices data */
1073                 for (j = 0; j < loop; j++) {
1074                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1075                                hc_index_p[j].flags,
1076                                hc_index_p[j].timeout);
1077                 }
1078         }
1079 
1080 #ifdef BNX2X_STOP_ON_ERROR
1081         if (IS_PF(bp)) {
1082                 /* event queue */
1083                 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1084                 for (i = 0; i < NUM_EQ_DESC; i++) {
1085                         u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1086 
1087                         BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1088                                   i, bp->eq_ring[i].message.opcode,
1089                                   bp->eq_ring[i].message.error);
1090                         BNX2X_ERR("data: %x %x %x\n",
1091                                   data[0], data[1], data[2]);
1092                 }
1093         }
1094 
1095         /* Rings */
1096         /* Rx */
1097         for_each_valid_rx_queue(bp, i) {
1098                 struct bnx2x_fastpath *fp = &bp->fp[i];
1099 
1100                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1101                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1102                 for (j = start; j != end; j = RX_BD(j + 1)) {
1103                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1104                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1105 
1106                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1107                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1108                 }
1109 
1110                 start = RX_SGE(fp->rx_sge_prod);
1111                 end = RX_SGE(fp->last_max_sge);
1112                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1113                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1114                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1115 
1116                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1117                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1118                 }
1119 
1120                 start = RCQ_BD(fp->rx_comp_cons - 10);
1121                 end = RCQ_BD(fp->rx_comp_cons + 503);
1122                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1123                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1124 
1125                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1126                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1127                 }
1128         }
1129 
1130         /* Tx */
1131         for_each_valid_tx_queue(bp, i) {
1132                 struct bnx2x_fastpath *fp = &bp->fp[i];
1133                 for_each_cos_in_tx_queue(fp, cos) {
1134                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1135 
1136                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1137                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1138                         for (j = start; j != end; j = TX_BD(j + 1)) {
1139                                 struct sw_tx_bd *sw_bd =
1140                                         &txdata->tx_buf_ring[j];
1141 
1142                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1143                                           i, cos, j, sw_bd->skb,
1144                                           sw_bd->first_bd);
1145                         }
1146 
1147                         start = TX_BD(txdata->tx_bd_cons - 10);
1148                         end = TX_BD(txdata->tx_bd_cons + 254);
1149                         for (j = start; j != end; j = TX_BD(j + 1)) {
1150                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1151 
1152                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1153                                           i, cos, j, tx_bd[0], tx_bd[1],
1154                                           tx_bd[2], tx_bd[3]);
1155                         }
1156                 }
1157         }
1158 #endif
1159         if (IS_PF(bp)) {
1160                 bnx2x_fw_dump(bp);
1161                 bnx2x_mc_assert(bp);
1162         }
1163         BNX2X_ERR("end crash dump -----------------\n");
1164 }
1165 
1166 /*
1167  * FLR Support for E2
1168  *
1169  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1170  * initialization.
1171  */
1172 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1173 #define FLR_WAIT_INTERVAL       50      /* usec */
1174 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1175 
1176 struct pbf_pN_buf_regs {
1177         int pN;
1178         u32 init_crd;
1179         u32 crd;
1180         u32 crd_freed;
1181 };
1182 
1183 struct pbf_pN_cmd_regs {
1184         int pN;
1185         u32 lines_occup;
1186         u32 lines_freed;
1187 };
1188 
1189 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1190                                      struct pbf_pN_buf_regs *regs,
1191                                      u32 poll_count)
1192 {
1193         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1194         u32 cur_cnt = poll_count;
1195 
1196         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1197         crd = crd_start = REG_RD(bp, regs->crd);
1198         init_crd = REG_RD(bp, regs->init_crd);
1199 
1200         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1201         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1202         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1203 
1204         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1205                (init_crd - crd_start))) {
1206                 if (cur_cnt--) {
1207                         udelay(FLR_WAIT_INTERVAL);
1208                         crd = REG_RD(bp, regs->crd);
1209                         crd_freed = REG_RD(bp, regs->crd_freed);
1210                 } else {
1211                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1212                            regs->pN);
1213                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1214                            regs->pN, crd);
1215                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1216                            regs->pN, crd_freed);
1217                         break;
1218                 }
1219         }
1220         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1221            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1222 }
1223 
1224 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1225                                      struct pbf_pN_cmd_regs *regs,
1226                                      u32 poll_count)
1227 {
1228         u32 occup, to_free, freed, freed_start;
1229         u32 cur_cnt = poll_count;
1230 
1231         occup = to_free = REG_RD(bp, regs->lines_occup);
1232         freed = freed_start = REG_RD(bp, regs->lines_freed);
1233 
1234         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1235         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1236 
1237         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1238                 if (cur_cnt--) {
1239                         udelay(FLR_WAIT_INTERVAL);
1240                         occup = REG_RD(bp, regs->lines_occup);
1241                         freed = REG_RD(bp, regs->lines_freed);
1242                 } else {
1243                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1244                            regs->pN);
1245                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1246                            regs->pN, occup);
1247                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1248                            regs->pN, freed);
1249                         break;
1250                 }
1251         }
1252         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1253            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1254 }
1255 
1256 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1257                                     u32 expected, u32 poll_count)
1258 {
1259         u32 cur_cnt = poll_count;
1260         u32 val;
1261 
1262         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1263                 udelay(FLR_WAIT_INTERVAL);
1264 
1265         return val;
1266 }
1267 
1268 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1269                                     char *msg, u32 poll_cnt)
1270 {
1271         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1272         if (val != 0) {
1273                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1274                 return 1;
1275         }
1276         return 0;
1277 }
1278 
1279 /* Common routines with VF FLR cleanup */
1280 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1281 {
1282         /* adjust polling timeout */
1283         if (CHIP_REV_IS_EMUL(bp))
1284                 return FLR_POLL_CNT * 2000;
1285 
1286         if (CHIP_REV_IS_FPGA(bp))
1287                 return FLR_POLL_CNT * 120;
1288 
1289         return FLR_POLL_CNT;
1290 }
1291 
1292 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1293 {
1294         struct pbf_pN_cmd_regs cmd_regs[] = {
1295                 {0, (CHIP_IS_E3B0(bp)) ?
1296                         PBF_REG_TQ_OCCUPANCY_Q0 :
1297                         PBF_REG_P0_TQ_OCCUPANCY,
1298                     (CHIP_IS_E3B0(bp)) ?
1299                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1300                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1301                 {1, (CHIP_IS_E3B0(bp)) ?
1302                         PBF_REG_TQ_OCCUPANCY_Q1 :
1303                         PBF_REG_P1_TQ_OCCUPANCY,
1304                     (CHIP_IS_E3B0(bp)) ?
1305                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1306                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1307                 {4, (CHIP_IS_E3B0(bp)) ?
1308                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1309                         PBF_REG_P4_TQ_OCCUPANCY,
1310                     (CHIP_IS_E3B0(bp)) ?
1311                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1312                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1313         };
1314 
1315         struct pbf_pN_buf_regs buf_regs[] = {
1316                 {0, (CHIP_IS_E3B0(bp)) ?
1317                         PBF_REG_INIT_CRD_Q0 :
1318                         PBF_REG_P0_INIT_CRD ,
1319                     (CHIP_IS_E3B0(bp)) ?
1320                         PBF_REG_CREDIT_Q0 :
1321                         PBF_REG_P0_CREDIT,
1322                     (CHIP_IS_E3B0(bp)) ?
1323                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1324                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1325                 {1, (CHIP_IS_E3B0(bp)) ?
1326                         PBF_REG_INIT_CRD_Q1 :
1327                         PBF_REG_P1_INIT_CRD,
1328                     (CHIP_IS_E3B0(bp)) ?
1329                         PBF_REG_CREDIT_Q1 :
1330                         PBF_REG_P1_CREDIT,
1331                     (CHIP_IS_E3B0(bp)) ?
1332                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1333                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1334                 {4, (CHIP_IS_E3B0(bp)) ?
1335                         PBF_REG_INIT_CRD_LB_Q :
1336                         PBF_REG_P4_INIT_CRD,
1337                     (CHIP_IS_E3B0(bp)) ?
1338                         PBF_REG_CREDIT_LB_Q :
1339                         PBF_REG_P4_CREDIT,
1340                     (CHIP_IS_E3B0(bp)) ?
1341                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1342                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1343         };
1344 
1345         int i;
1346 
1347         /* Verify the command queues are flushed P0, P1, P4 */
1348         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1349                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1350 
1351         /* Verify the transmission buffers are flushed P0, P1, P4 */
1352         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1353                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1354 }
1355 
1356 #define OP_GEN_PARAM(param) \
1357         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1358 
1359 #define OP_GEN_TYPE(type) \
1360         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1361 
1362 #define OP_GEN_AGG_VECT(index) \
1363         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1364 
1365 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1366 {
1367         u32 op_gen_command = 0;
1368         u32 comp_addr = BAR_CSTRORM_INTMEM +
1369                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1370         int ret = 0;
1371 
1372         if (REG_RD(bp, comp_addr)) {
1373                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1374                 return 1;
1375         }
1376 
1377         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1378         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1379         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1380         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1381 
1382         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1383         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1384 
1385         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1386                 BNX2X_ERR("FW final cleanup did not succeed\n");
1387                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1388                    (REG_RD(bp, comp_addr)));
1389                 bnx2x_panic();
1390                 return 1;
1391         }
1392         /* Zero completion for next FLR */
1393         REG_WR(bp, comp_addr, 0);
1394 
1395         return ret;
1396 }
1397 
1398 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1399 {
1400         u16 status;
1401 
1402         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1403         return status & PCI_EXP_DEVSTA_TRPND;
1404 }
1405 
1406 /* PF FLR specific routines
1407 */
1408 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1409 {
1410         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1411         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1412                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1413                         "CFC PF usage counter timed out",
1414                         poll_cnt))
1415                 return 1;
1416 
1417         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1418         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1419                         DORQ_REG_PF_USAGE_CNT,
1420                         "DQ PF usage counter timed out",
1421                         poll_cnt))
1422                 return 1;
1423 
1424         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1425         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1426                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1427                         "QM PF usage counter timed out",
1428                         poll_cnt))
1429                 return 1;
1430 
1431         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1432         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1433                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1434                         "Timers VNIC usage counter timed out",
1435                         poll_cnt))
1436                 return 1;
1437         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1438                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1439                         "Timers NUM_SCANS usage counter timed out",
1440                         poll_cnt))
1441                 return 1;
1442 
1443         /* Wait DMAE PF usage counter to zero */
1444         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1445                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1446                         "DMAE command register timed out",
1447                         poll_cnt))
1448                 return 1;
1449 
1450         return 0;
1451 }
1452 
1453 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1454 {
1455         u32 val;
1456 
1457         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1458         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1459 
1460         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1461         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1462 
1463         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1464         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1465 
1466         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1467         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1468 
1469         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1470         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1471 
1472         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1473         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1474 
1475         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1476         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1477 
1478         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1479         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1480            val);
1481 }
1482 
1483 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1484 {
1485         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1486 
1487         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1488 
1489         /* Re-enable PF target read access */
1490         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1491 
1492         /* Poll HW usage counters */
1493         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1494         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1495                 return -EBUSY;
1496 
1497         /* Zero the igu 'trailing edge' and 'leading edge' */
1498 
1499         /* Send the FW cleanup command */
1500         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1501                 return -EBUSY;
1502 
1503         /* ATC cleanup */
1504 
1505         /* Verify TX hw is flushed */
1506         bnx2x_tx_hw_flushed(bp, poll_cnt);
1507 
1508         /* Wait 100ms (not adjusted according to platform) */
1509         msleep(100);
1510 
1511         /* Verify no pending pci transactions */
1512         if (bnx2x_is_pcie_pending(bp->pdev))
1513                 BNX2X_ERR("PCIE Transactions still pending\n");
1514 
1515         /* Debug */
1516         bnx2x_hw_enable_status(bp);
1517 
1518         /*
1519          * Master enable - Due to WB DMAE writes performed before this
1520          * register is re-initialized as part of the regular function init
1521          */
1522         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1523 
1524         return 0;
1525 }
1526 
1527 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1528 {
1529         int port = BP_PORT(bp);
1530         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1531         u32 val = REG_RD(bp, addr);
1532         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1533         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1534         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1535 
1536         if (msix) {
1537                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1538                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1539                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1540                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1541                 if (single_msix)
1542                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1543         } else if (msi) {
1544                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1545                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1546                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1547                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1548         } else {
1549                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1550                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1551                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1552                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1553 
1554                 if (!CHIP_IS_E1(bp)) {
1555                         DP(NETIF_MSG_IFUP,
1556                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1557 
1558                         REG_WR(bp, addr, val);
1559 
1560                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1561                 }
1562         }
1563 
1564         if (CHIP_IS_E1(bp))
1565                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1566 
1567         DP(NETIF_MSG_IFUP,
1568            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1569            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1570 
1571         REG_WR(bp, addr, val);
1572         /*
1573          * Ensure that HC_CONFIG is written before leading/trailing edge config
1574          */
1575         mmiowb();
1576         barrier();
1577 
1578         if (!CHIP_IS_E1(bp)) {
1579                 /* init leading/trailing edge */
1580                 if (IS_MF(bp)) {
1581                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1582                         if (bp->port.pmf)
1583                                 /* enable nig and gpio3 attention */
1584                                 val |= 0x1100;
1585                 } else
1586                         val = 0xffff;
1587 
1588                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1589                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1590         }
1591 
1592         /* Make sure that interrupts are indeed enabled from here on */
1593         mmiowb();
1594 }
1595 
1596 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1597 {
1598         u32 val;
1599         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1600         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1601         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1602 
1603         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1604 
1605         if (msix) {
1606                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1607                          IGU_PF_CONF_SINGLE_ISR_EN);
1608                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1609                         IGU_PF_CONF_ATTN_BIT_EN);
1610 
1611                 if (single_msix)
1612                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1613         } else if (msi) {
1614                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1615                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1616                         IGU_PF_CONF_ATTN_BIT_EN |
1617                         IGU_PF_CONF_SINGLE_ISR_EN);
1618         } else {
1619                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1620                 val |= (IGU_PF_CONF_INT_LINE_EN |
1621                         IGU_PF_CONF_ATTN_BIT_EN |
1622                         IGU_PF_CONF_SINGLE_ISR_EN);
1623         }
1624 
1625         /* Clean previous status - need to configure igu prior to ack*/
1626         if ((!msix) || single_msix) {
1627                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1628                 bnx2x_ack_int(bp);
1629         }
1630 
1631         val |= IGU_PF_CONF_FUNC_EN;
1632 
1633         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1634            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1635 
1636         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1637 
1638         if (val & IGU_PF_CONF_INT_LINE_EN)
1639                 pci_intx(bp->pdev, true);
1640 
1641         barrier();
1642 
1643         /* init leading/trailing edge */
1644         if (IS_MF(bp)) {
1645                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1646                 if (bp->port.pmf)
1647                         /* enable nig and gpio3 attention */
1648                         val |= 0x1100;
1649         } else
1650                 val = 0xffff;
1651 
1652         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1653         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1654 
1655         /* Make sure that interrupts are indeed enabled from here on */
1656         mmiowb();
1657 }
1658 
1659 void bnx2x_int_enable(struct bnx2x *bp)
1660 {
1661         if (bp->common.int_block == INT_BLOCK_HC)
1662                 bnx2x_hc_int_enable(bp);
1663         else
1664                 bnx2x_igu_int_enable(bp);
1665 }
1666 
1667 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1668 {
1669         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1670         int i, offset;
1671 
1672         if (disable_hw)
1673                 /* prevent the HW from sending interrupts */
1674                 bnx2x_int_disable(bp);
1675 
1676         /* make sure all ISRs are done */
1677         if (msix) {
1678                 synchronize_irq(bp->msix_table[0].vector);
1679                 offset = 1;
1680                 if (CNIC_SUPPORT(bp))
1681                         offset++;
1682                 for_each_eth_queue(bp, i)
1683                         synchronize_irq(bp->msix_table[offset++].vector);
1684         } else
1685                 synchronize_irq(bp->pdev->irq);
1686 
1687         /* make sure sp_task is not running */
1688         cancel_delayed_work(&bp->sp_task);
1689         cancel_delayed_work(&bp->period_task);
1690         flush_workqueue(bnx2x_wq);
1691 }
1692 
1693 /* fast path */
1694 
1695 /*
1696  * General service functions
1697  */
1698 
1699 /* Return true if succeeded to acquire the lock */
1700 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1701 {
1702         u32 lock_status;
1703         u32 resource_bit = (1 << resource);
1704         int func = BP_FUNC(bp);
1705         u32 hw_lock_control_reg;
1706 
1707         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1708            "Trying to take a lock on resource %d\n", resource);
1709 
1710         /* Validating that the resource is within range */
1711         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1712                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1713                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1714                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1715                 return false;
1716         }
1717 
1718         if (func <= 5)
1719                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1720         else
1721                 hw_lock_control_reg =
1722                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1723 
1724         /* Try to acquire the lock */
1725         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1726         lock_status = REG_RD(bp, hw_lock_control_reg);
1727         if (lock_status & resource_bit)
1728                 return true;
1729 
1730         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1731            "Failed to get a lock on resource %d\n", resource);
1732         return false;
1733 }
1734 
1735 /**
1736  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1737  *
1738  * @bp: driver handle
1739  *
1740  * Returns the recovery leader resource id according to the engine this function
1741  * belongs to. Currently only only 2 engines is supported.
1742  */
1743 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1744 {
1745         if (BP_PATH(bp))
1746                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1747         else
1748                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1749 }
1750 
1751 /**
1752  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1753  *
1754  * @bp: driver handle
1755  *
1756  * Tries to acquire a leader lock for current engine.
1757  */
1758 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1759 {
1760         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1761 }
1762 
1763 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1764 
1765 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1766 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1767 {
1768         /* Set the interrupt occurred bit for the sp-task to recognize it
1769          * must ack the interrupt and transition according to the IGU
1770          * state machine.
1771          */
1772         atomic_set(&bp->interrupt_occurred, 1);
1773 
1774         /* The sp_task must execute only after this bit
1775          * is set, otherwise we will get out of sync and miss all
1776          * further interrupts. Hence, the barrier.
1777          */
1778         smp_wmb();
1779 
1780         /* schedule sp_task to workqueue */
1781         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1782 }
1783 
1784 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1785 {
1786         struct bnx2x *bp = fp->bp;
1787         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1788         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1789         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1790         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1791 
1792         DP(BNX2X_MSG_SP,
1793            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1794            fp->index, cid, command, bp->state,
1795            rr_cqe->ramrod_cqe.ramrod_type);
1796 
1797         /* If cid is within VF range, replace the slowpath object with the
1798          * one corresponding to this VF
1799          */
1800         if (cid >= BNX2X_FIRST_VF_CID  &&
1801             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1802                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1803 
1804         switch (command) {
1805         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1806                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1807                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1808                 break;
1809 
1810         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1811                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1812                 drv_cmd = BNX2X_Q_CMD_SETUP;
1813                 break;
1814 
1815         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1816                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1817                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1818                 break;
1819 
1820         case (RAMROD_CMD_ID_ETH_HALT):
1821                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1822                 drv_cmd = BNX2X_Q_CMD_HALT;
1823                 break;
1824 
1825         case (RAMROD_CMD_ID_ETH_TERMINATE):
1826                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1827                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1828                 break;
1829 
1830         case (RAMROD_CMD_ID_ETH_EMPTY):
1831                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1832                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1833                 break;
1834 
1835         case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1836                 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1837                 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1838                 break;
1839 
1840         default:
1841                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1842                           command, fp->index);
1843                 return;
1844         }
1845 
1846         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1847             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1848                 /* q_obj->complete_cmd() failure means that this was
1849                  * an unexpected completion.
1850                  *
1851                  * In this case we don't want to increase the bp->spq_left
1852                  * because apparently we haven't sent this command the first
1853                  * place.
1854                  */
1855 #ifdef BNX2X_STOP_ON_ERROR
1856                 bnx2x_panic();
1857 #else
1858                 return;
1859 #endif
1860 
1861         smp_mb__before_atomic();
1862         atomic_inc(&bp->cq_spq_left);
1863         /* push the change in bp->spq_left and towards the memory */
1864         smp_mb__after_atomic();
1865 
1866         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1867 
1868         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1869             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1870                 /* if Q update ramrod is completed for last Q in AFEX vif set
1871                  * flow, then ACK MCP at the end
1872                  *
1873                  * mark pending ACK to MCP bit.
1874                  * prevent case that both bits are cleared.
1875                  * At the end of load/unload driver checks that
1876                  * sp_state is cleared, and this order prevents
1877                  * races
1878                  */
1879                 smp_mb__before_atomic();
1880                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1881                 wmb();
1882                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1883                 smp_mb__after_atomic();
1884 
1885                 /* schedule the sp task as mcp ack is required */
1886                 bnx2x_schedule_sp_task(bp);
1887         }
1888 
1889         return;
1890 }
1891 
1892 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1893 {
1894         struct bnx2x *bp = netdev_priv(dev_instance);
1895         u16 status = bnx2x_ack_int(bp);
1896         u16 mask;
1897         int i;
1898         u8 cos;
1899 
1900         /* Return here if interrupt is shared and it's not for us */
1901         if (unlikely(status == 0)) {
1902                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1903                 return IRQ_NONE;
1904         }
1905         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1906 
1907 #ifdef BNX2X_STOP_ON_ERROR
1908         if (unlikely(bp->panic))
1909                 return IRQ_HANDLED;
1910 #endif
1911 
1912         for_each_eth_queue(bp, i) {
1913                 struct bnx2x_fastpath *fp = &bp->fp[i];
1914 
1915                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1916                 if (status & mask) {
1917                         /* Handle Rx or Tx according to SB id */
1918                         for_each_cos_in_tx_queue(fp, cos)
1919                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1920                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1921                         napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1922                         status &= ~mask;
1923                 }
1924         }
1925 
1926         if (CNIC_SUPPORT(bp)) {
1927                 mask = 0x2;
1928                 if (status & (mask | 0x1)) {
1929                         struct cnic_ops *c_ops = NULL;
1930 
1931                         rcu_read_lock();
1932                         c_ops = rcu_dereference(bp->cnic_ops);
1933                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1934                                       CNIC_DRV_STATE_HANDLES_IRQ))
1935                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1936                         rcu_read_unlock();
1937 
1938                         status &= ~mask;
1939                 }
1940         }
1941 
1942         if (unlikely(status & 0x1)) {
1943 
1944                 /* schedule sp task to perform default status block work, ack
1945                  * attentions and enable interrupts.
1946                  */
1947                 bnx2x_schedule_sp_task(bp);
1948 
1949                 status &= ~0x1;
1950                 if (!status)
1951                         return IRQ_HANDLED;
1952         }
1953 
1954         if (unlikely(status))
1955                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1956                    status);
1957 
1958         return IRQ_HANDLED;
1959 }
1960 
1961 /* Link */
1962 
1963 /*
1964  * General service functions
1965  */
1966 
1967 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1968 {
1969         u32 lock_status;
1970         u32 resource_bit = (1 << resource);
1971         int func = BP_FUNC(bp);
1972         u32 hw_lock_control_reg;
1973         int cnt;
1974 
1975         /* Validating that the resource is within range */
1976         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1977                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1978                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1979                 return -EINVAL;
1980         }
1981 
1982         if (func <= 5) {
1983                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1984         } else {
1985                 hw_lock_control_reg =
1986                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1987         }
1988 
1989         /* Validating that the resource is not already taken */
1990         lock_status = REG_RD(bp, hw_lock_control_reg);
1991         if (lock_status & resource_bit) {
1992                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
1993                    lock_status, resource_bit);
1994                 return -EEXIST;
1995         }
1996 
1997         /* Try for 5 second every 5ms */
1998         for (cnt = 0; cnt < 1000; cnt++) {
1999                 /* Try to acquire the lock */
2000                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2001                 lock_status = REG_RD(bp, hw_lock_control_reg);
2002                 if (lock_status & resource_bit)
2003                         return 0;
2004 
2005                 usleep_range(5000, 10000);
2006         }
2007         BNX2X_ERR("Timeout\n");
2008         return -EAGAIN;
2009 }
2010 
2011 int bnx2x_release_leader_lock(struct bnx2x *bp)
2012 {
2013         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2014 }
2015 
2016 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2017 {
2018         u32 lock_status;
2019         u32 resource_bit = (1 << resource);
2020         int func = BP_FUNC(bp);
2021         u32 hw_lock_control_reg;
2022 
2023         /* Validating that the resource is within range */
2024         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2025                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2026                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
2027                 return -EINVAL;
2028         }
2029 
2030         if (func <= 5) {
2031                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2032         } else {
2033                 hw_lock_control_reg =
2034                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2035         }
2036 
2037         /* Validating that the resource is currently taken */
2038         lock_status = REG_RD(bp, hw_lock_control_reg);
2039         if (!(lock_status & resource_bit)) {
2040                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2041                           lock_status, resource_bit);
2042                 return -EFAULT;
2043         }
2044 
2045         REG_WR(bp, hw_lock_control_reg, resource_bit);
2046         return 0;
2047 }
2048 
2049 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2050 {
2051         /* The GPIO should be swapped if swap register is set and active */
2052         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2053                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2054         int gpio_shift = gpio_num +
2055                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2056         u32 gpio_mask = (1 << gpio_shift);
2057         u32 gpio_reg;
2058         int value;
2059 
2060         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2061                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2062                 return -EINVAL;
2063         }
2064 
2065         /* read GPIO value */
2066         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2067 
2068         /* get the requested pin value */
2069         if ((gpio_reg & gpio_mask) == gpio_mask)
2070                 value = 1;
2071         else
2072                 value = 0;
2073 
2074         DP(NETIF_MSG_LINK, "pin %d  value 0x%x\n", gpio_num, value);
2075 
2076         return value;
2077 }
2078 
2079 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2080 {
2081         /* The GPIO should be swapped if swap register is set and active */
2082         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2083                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2084         int gpio_shift = gpio_num +
2085                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2086         u32 gpio_mask = (1 << gpio_shift);
2087         u32 gpio_reg;
2088 
2089         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2090                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2091                 return -EINVAL;
2092         }
2093 
2094         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2095         /* read GPIO and mask except the float bits */
2096         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2097 
2098         switch (mode) {
2099         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2100                 DP(NETIF_MSG_LINK,
2101                    "Set GPIO %d (shift %d) -> output low\n",
2102                    gpio_num, gpio_shift);
2103                 /* clear FLOAT and set CLR */
2104                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2105                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2106                 break;
2107 
2108         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2109                 DP(NETIF_MSG_LINK,
2110                    "Set GPIO %d (shift %d) -> output high\n",
2111                    gpio_num, gpio_shift);
2112                 /* clear FLOAT and set SET */
2113                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2114                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2115                 break;
2116 
2117         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2118                 DP(NETIF_MSG_LINK,
2119                    "Set GPIO %d (shift %d) -> input\n",
2120                    gpio_num, gpio_shift);
2121                 /* set FLOAT */
2122                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2123                 break;
2124 
2125         default:
2126                 break;
2127         }
2128 
2129         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2130         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2131 
2132         return 0;
2133 }
2134 
2135 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2136 {
2137         u32 gpio_reg = 0;
2138         int rc = 0;
2139 
2140         /* Any port swapping should be handled by caller. */
2141 
2142         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2143         /* read GPIO and mask except the float bits */
2144         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2145         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2146         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2147         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2148 
2149         switch (mode) {
2150         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2151                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2152                 /* set CLR */
2153                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2154                 break;
2155 
2156         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2157                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2158                 /* set SET */
2159                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2160                 break;
2161 
2162         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2163                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2164                 /* set FLOAT */
2165                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2166                 break;
2167 
2168         default:
2169                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2170                 rc = -EINVAL;
2171                 break;
2172         }
2173 
2174         if (rc == 0)
2175                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2176 
2177         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2178 
2179         return rc;
2180 }
2181 
2182 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2183 {
2184         /* The GPIO should be swapped if swap register is set and active */
2185         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2186                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2187         int gpio_shift = gpio_num +
2188                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2189         u32 gpio_mask = (1 << gpio_shift);
2190         u32 gpio_reg;
2191 
2192         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2193                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2194                 return -EINVAL;
2195         }
2196 
2197         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2198         /* read GPIO int */
2199         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2200 
2201         switch (mode) {
2202         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2203                 DP(NETIF_MSG_LINK,
2204                    "Clear GPIO INT %d (shift %d) -> output low\n",
2205                    gpio_num, gpio_shift);
2206                 /* clear SET and set CLR */
2207                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2208                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2209                 break;
2210 
2211         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2212                 DP(NETIF_MSG_LINK,
2213                    "Set GPIO INT %d (shift %d) -> output high\n",
2214                    gpio_num, gpio_shift);
2215                 /* clear CLR and set SET */
2216                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2217                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2218                 break;
2219 
2220         default:
2221                 break;
2222         }
2223 
2224         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2225         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2226 
2227         return 0;
2228 }
2229 
2230 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2231 {
2232         u32 spio_reg;
2233 
2234         /* Only 2 SPIOs are configurable */
2235         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2236                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2237                 return -EINVAL;
2238         }
2239 
2240         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2241         /* read SPIO and mask except the float bits */
2242         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2243 
2244         switch (mode) {
2245         case MISC_SPIO_OUTPUT_LOW:
2246                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2247                 /* clear FLOAT and set CLR */
2248                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2249                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2250                 break;
2251 
2252         case MISC_SPIO_OUTPUT_HIGH:
2253                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2254                 /* clear FLOAT and set SET */
2255                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2256                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2257                 break;
2258 
2259         case MISC_SPIO_INPUT_HI_Z:
2260                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2261                 /* set FLOAT */
2262                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2263                 break;
2264 
2265         default:
2266                 break;
2267         }
2268 
2269         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2270         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2271 
2272         return 0;
2273 }
2274 
2275 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2276 {
2277         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2278         switch (bp->link_vars.ieee_fc &
2279                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2280         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2281                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2282                                                    ADVERTISED_Pause);
2283                 break;
2284 
2285         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2286                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2287                                                   ADVERTISED_Pause);
2288                 break;
2289 
2290         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2291                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2292                 break;
2293 
2294         default:
2295                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2296                                                    ADVERTISED_Pause);
2297                 break;
2298         }
2299 }
2300 
2301 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2302 {
2303         /* Initialize link parameters structure variables
2304          * It is recommended to turn off RX FC for jumbo frames
2305          *  for better performance
2306          */
2307         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2308                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2309         else
2310                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2311 }
2312 
2313 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2314 {
2315         u32 pause_enabled = 0;
2316 
2317         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2318                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2319                         pause_enabled = 1;
2320 
2321                 REG_WR(bp, BAR_USTRORM_INTMEM +
2322                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2323                        pause_enabled);
2324         }
2325 
2326         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2327            pause_enabled ? "enabled" : "disabled");
2328 }
2329 
2330 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2331 {
2332         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2333         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2334 
2335         if (!BP_NOMCP(bp)) {
2336                 bnx2x_set_requested_fc(bp);
2337                 bnx2x_acquire_phy_lock(bp);
2338 
2339                 if (load_mode == LOAD_DIAG) {
2340                         struct link_params *lp = &bp->link_params;
2341                         lp->loopback_mode = LOOPBACK_XGXS;
2342                         /* do PHY loopback at 10G speed, if possible */
2343                         if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2344                                 if (lp->speed_cap_mask[cfx_idx] &
2345                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2346                                         lp->req_line_speed[cfx_idx] =
2347                                         SPEED_10000;
2348                                 else
2349                                         lp->req_line_speed[cfx_idx] =
2350                                         SPEED_1000;
2351                         }
2352                 }
2353 
2354                 if (load_mode == LOAD_LOOPBACK_EXT) {
2355                         struct link_params *lp = &bp->link_params;
2356                         lp->loopback_mode = LOOPBACK_EXT;
2357                 }
2358 
2359                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2360 
2361                 bnx2x_release_phy_lock(bp);
2362 
2363                 bnx2x_init_dropless_fc(bp);
2364 
2365                 bnx2x_calc_fc_adv(bp);
2366 
2367                 if (bp->link_vars.link_up) {
2368                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2369                         bnx2x_link_report(bp);
2370                 }
2371                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2372                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2373                 return rc;
2374         }
2375         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2376         return -EINVAL;
2377 }
2378 
2379 void bnx2x_link_set(struct bnx2x *bp)
2380 {
2381         if (!BP_NOMCP(bp)) {
2382                 bnx2x_acquire_phy_lock(bp);
2383                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2384                 bnx2x_release_phy_lock(bp);
2385 
2386                 bnx2x_init_dropless_fc(bp);
2387 
2388                 bnx2x_calc_fc_adv(bp);
2389         } else
2390                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2391 }
2392 
2393 static void bnx2x__link_reset(struct bnx2x *bp)
2394 {
2395         if (!BP_NOMCP(bp)) {
2396                 bnx2x_acquire_phy_lock(bp);
2397                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2398                 bnx2x_release_phy_lock(bp);
2399         } else
2400                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2401 }
2402 
2403 void bnx2x_force_link_reset(struct bnx2x *bp)
2404 {
2405         bnx2x_acquire_phy_lock(bp);
2406         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2407         bnx2x_release_phy_lock(bp);
2408 }
2409 
2410 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2411 {
2412         u8 rc = 0;
2413 
2414         if (!BP_NOMCP(bp)) {
2415                 bnx2x_acquire_phy_lock(bp);
2416                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2417                                      is_serdes);
2418                 bnx2x_release_phy_lock(bp);
2419         } else
2420                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2421 
2422         return rc;
2423 }
2424 
2425 /* Calculates the sum of vn_min_rates.
2426    It's needed for further normalizing of the min_rates.
2427    Returns:
2428      sum of vn_min_rates.
2429        or
2430      0 - if all the min_rates are 0.
2431      In the later case fairness algorithm should be deactivated.
2432      If not all min_rates are zero then those that are zeroes will be set to 1.
2433  */
2434 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2435                                       struct cmng_init_input *input)
2436 {
2437         int all_zero = 1;
2438         int vn;
2439 
2440         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2441                 u32 vn_cfg = bp->mf_config[vn];
2442                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2443                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2444 
2445                 /* Skip hidden vns */
2446                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2447                         vn_min_rate = 0;
2448                 /* If min rate is zero - set it to 1 */
2449                 else if (!vn_min_rate)
2450                         vn_min_rate = DEF_MIN_RATE;
2451                 else
2452                         all_zero = 0;
2453 
2454                 input->vnic_min_rate[vn] = vn_min_rate;
2455         }
2456 
2457         /* if ETS or all min rates are zeros - disable fairness */
2458         if (BNX2X_IS_ETS_ENABLED(bp)) {
2459                 input->flags.cmng_enables &=
2460                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2461                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2462         } else if (all_zero) {
2463                 input->flags.cmng_enables &=
2464                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2465                 DP(NETIF_MSG_IFUP,
2466                    "All MIN values are zeroes fairness will be disabled\n");
2467         } else
2468                 input->flags.cmng_enables |=
2469                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2470 }
2471 
2472 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2473                                     struct cmng_init_input *input)
2474 {
2475         u16 vn_max_rate;
2476         u32 vn_cfg = bp->mf_config[vn];
2477 
2478         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2479                 vn_max_rate = 0;
2480         else {
2481                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2482 
2483                 if (IS_MF_SI(bp)) {
2484                         /* maxCfg in percents of linkspeed */
2485                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2486                 } else /* SD modes */
2487                         /* maxCfg is absolute in 100Mb units */
2488                         vn_max_rate = maxCfg * 100;
2489         }
2490 
2491         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2492 
2493         input->vnic_max_rate[vn] = vn_max_rate;
2494 }
2495 
2496 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2497 {
2498         if (CHIP_REV_IS_SLOW(bp))
2499                 return CMNG_FNS_NONE;
2500         if (IS_MF(bp))
2501                 return CMNG_FNS_MINMAX;
2502 
2503         return CMNG_FNS_NONE;
2504 }
2505 
2506 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2507 {
2508         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2509 
2510         if (BP_NOMCP(bp))
2511                 return; /* what should be the default value in this case */
2512 
2513         /* For 2 port configuration the absolute function number formula
2514          * is:
2515          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2516          *
2517          *      and there are 4 functions per port
2518          *
2519          * For 4 port configuration it is
2520          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2521          *
2522          *      and there are 2 functions per port
2523          */
2524         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2525                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2526 
2527                 if (func >= E1H_FUNC_MAX)
2528                         break;
2529 
2530                 bp->mf_config[vn] =
2531                         MF_CFG_RD(bp, func_mf_config[func].config);
2532         }
2533         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2534                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2535                 bp->flags |= MF_FUNC_DIS;
2536         } else {
2537                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2538                 bp->flags &= ~MF_FUNC_DIS;
2539         }
2540 }
2541 
2542 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2543 {
2544         struct cmng_init_input input;
2545         memset(&input, 0, sizeof(struct cmng_init_input));
2546 
2547         input.port_rate = bp->link_vars.line_speed;
2548 
2549         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2550                 int vn;
2551 
2552                 /* read mf conf from shmem */
2553                 if (read_cfg)
2554                         bnx2x_read_mf_cfg(bp);
2555 
2556                 /* vn_weight_sum and enable fairness if not 0 */
2557                 bnx2x_calc_vn_min(bp, &input);
2558 
2559                 /* calculate and set min-max rate for each vn */
2560                 if (bp->port.pmf)
2561                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2562                                 bnx2x_calc_vn_max(bp, vn, &input);
2563 
2564                 /* always enable rate shaping and fairness */
2565                 input.flags.cmng_enables |=
2566                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2567 
2568                 bnx2x_init_cmng(&input, &bp->cmng);
2569                 return;
2570         }
2571 
2572         /* rate shaping and fairness are disabled */
2573         DP(NETIF_MSG_IFUP,
2574            "rate shaping and fairness are disabled\n");
2575 }
2576 
2577 static void storm_memset_cmng(struct bnx2x *bp,
2578                               struct cmng_init *cmng,
2579                               u8 port)
2580 {
2581         int vn;
2582         size_t size = sizeof(struct cmng_struct_per_port);
2583 
2584         u32 addr = BAR_XSTRORM_INTMEM +
2585                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2586 
2587         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2588 
2589         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2590                 int func = func_by_vn(bp, vn);
2591 
2592                 addr = BAR_XSTRORM_INTMEM +
2593                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2594                 size = sizeof(struct rate_shaping_vars_per_vn);
2595                 __storm_memset_struct(bp, addr, size,
2596                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2597 
2598                 addr = BAR_XSTRORM_INTMEM +
2599                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2600                 size = sizeof(struct fairness_vars_per_vn);
2601                 __storm_memset_struct(bp, addr, size,
2602                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2603         }
2604 }
2605 
2606 /* init cmng mode in HW according to local configuration */
2607 void bnx2x_set_local_cmng(struct bnx2x *bp)
2608 {
2609         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2610 
2611         if (cmng_fns != CMNG_FNS_NONE) {
2612                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2613                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2614         } else {
2615                 /* rate shaping and fairness are disabled */
2616                 DP(NETIF_MSG_IFUP,
2617                    "single function mode without fairness\n");
2618         }
2619 }
2620 
2621 /* This function is called upon link interrupt */
2622 static void bnx2x_link_attn(struct bnx2x *bp)
2623 {
2624         /* Make sure that we are synced with the current statistics */
2625         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2626 
2627         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2628 
2629         bnx2x_init_dropless_fc(bp);
2630 
2631         if (bp->link_vars.link_up) {
2632 
2633                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2634                         struct host_port_stats *pstats;
2635 
2636                         pstats = bnx2x_sp(bp, port_stats);
2637                         /* reset old mac stats */
2638                         memset(&(pstats->mac_stx[0]), 0,
2639                                sizeof(struct mac_stx));
2640                 }
2641                 if (bp->state == BNX2X_STATE_OPEN)
2642                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2643         }
2644 
2645         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2646                 bnx2x_set_local_cmng(bp);
2647 
2648         __bnx2x_link_report(bp);
2649 
2650         if (IS_MF(bp))
2651                 bnx2x_link_sync_notify(bp);
2652 }
2653 
2654 void bnx2x__link_status_update(struct bnx2x *bp)
2655 {
2656         if (bp->state != BNX2X_STATE_OPEN)
2657                 return;
2658 
2659         /* read updated dcb configuration */
2660         if (IS_PF(bp)) {
2661                 bnx2x_dcbx_pmf_update(bp);
2662                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2663                 if (bp->link_vars.link_up)
2664                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2665                 else
2666                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2667                         /* indicate link status */
2668                 bnx2x_link_report(bp);
2669 
2670         } else { /* VF */
2671                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2672                                           SUPPORTED_10baseT_Full |
2673                                           SUPPORTED_100baseT_Half |
2674                                           SUPPORTED_100baseT_Full |
2675                                           SUPPORTED_1000baseT_Full |
2676                                           SUPPORTED_2500baseX_Full |
2677                                           SUPPORTED_10000baseT_Full |
2678                                           SUPPORTED_TP |
2679                                           SUPPORTED_FIBRE |
2680                                           SUPPORTED_Autoneg |
2681                                           SUPPORTED_Pause |
2682                                           SUPPORTED_Asym_Pause);
2683                 bp->port.advertising[0] = bp->port.supported[0];
2684 
2685                 bp->link_params.bp = bp;
2686                 bp->link_params.port = BP_PORT(bp);
2687                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2688                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2689                 bp->link_params.req_line_speed[0] = SPEED_10000;
2690                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2691                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2692                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2693                 bp->link_vars.line_speed = SPEED_10000;
2694                 bp->link_vars.link_status =
2695                         (LINK_STATUS_LINK_UP |
2696                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2697                 bp->link_vars.link_up = 1;
2698                 bp->link_vars.duplex = DUPLEX_FULL;
2699                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2700                 __bnx2x_link_report(bp);
2701                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2702         }
2703 }
2704 
2705 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2706                                   u16 vlan_val, u8 allowed_prio)
2707 {
2708         struct bnx2x_func_state_params func_params = {NULL};
2709         struct bnx2x_func_afex_update_params *f_update_params =
2710                 &func_params.params.afex_update;
2711 
2712         func_params.f_obj = &bp->func_obj;
2713         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2714 
2715         /* no need to wait for RAMROD completion, so don't
2716          * set RAMROD_COMP_WAIT flag
2717          */
2718 
2719         f_update_params->vif_id = vifid;
2720         f_update_params->afex_default_vlan = vlan_val;
2721         f_update_params->allowed_priorities = allowed_prio;
2722 
2723         /* if ramrod can not be sent, response to MCP immediately */
2724         if (bnx2x_func_state_change(bp, &func_params) < 0)
2725                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2726 
2727         return 0;
2728 }
2729 
2730 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2731                                           u16 vif_index, u8 func_bit_map)
2732 {
2733         struct bnx2x_func_state_params func_params = {NULL};
2734         struct bnx2x_func_afex_viflists_params *update_params =
2735                 &func_params.params.afex_viflists;
2736         int rc;
2737         u32 drv_msg_code;
2738 
2739         /* validate only LIST_SET and LIST_GET are received from switch */
2740         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2741                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2742                           cmd_type);
2743 
2744         func_params.f_obj = &bp->func_obj;
2745         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2746 
2747         /* set parameters according to cmd_type */
2748         update_params->afex_vif_list_command = cmd_type;
2749         update_params->vif_list_index = vif_index;
2750         update_params->func_bit_map =
2751                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2752         update_params->func_to_clear = 0;
2753         drv_msg_code =
2754                 (cmd_type == VIF_LIST_RULE_GET) ?
2755                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2756                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2757 
2758         /* if ramrod can not be sent, respond to MCP immediately for
2759          * SET and GET requests (other are not triggered from MCP)
2760          */
2761         rc = bnx2x_func_state_change(bp, &func_params);
2762         if (rc < 0)
2763                 bnx2x_fw_command(bp, drv_msg_code, 0);
2764 
2765         return 0;
2766 }
2767 
2768 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2769 {
2770         struct afex_stats afex_stats;
2771         u32 func = BP_ABS_FUNC(bp);
2772         u32 mf_config;
2773         u16 vlan_val;
2774         u32 vlan_prio;
2775         u16 vif_id;
2776         u8 allowed_prio;
2777         u8 vlan_mode;
2778         u32 addr_to_write, vifid, addrs, stats_type, i;
2779 
2780         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2781                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2782                 DP(BNX2X_MSG_MCP,
2783                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2784                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2785         }
2786 
2787         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2788                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2789                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2790                 DP(BNX2X_MSG_MCP,
2791                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2792                    vifid, addrs);
2793                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2794                                                addrs);
2795         }
2796 
2797         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2798                 addr_to_write = SHMEM2_RD(bp,
2799                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2800                 stats_type = SHMEM2_RD(bp,
2801                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2802 
2803                 DP(BNX2X_MSG_MCP,
2804                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2805                    addr_to_write);
2806 
2807                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2808 
2809                 /* write response to scratchpad, for MCP */
2810                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2811                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2812                                *(((u32 *)(&afex_stats))+i));
2813 
2814                 /* send ack message to MCP */
2815                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2816         }
2817 
2818         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2819                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2820                 bp->mf_config[BP_VN(bp)] = mf_config;
2821                 DP(BNX2X_MSG_MCP,
2822                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2823                    mf_config);
2824 
2825                 /* if VIF_SET is "enabled" */
2826                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2827                         /* set rate limit directly to internal RAM */
2828                         struct cmng_init_input cmng_input;
2829                         struct rate_shaping_vars_per_vn m_rs_vn;
2830                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2831                         u32 addr = BAR_XSTRORM_INTMEM +
2832                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2833 
2834                         bp->mf_config[BP_VN(bp)] = mf_config;
2835 
2836                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2837                         m_rs_vn.vn_counter.rate =
2838                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2839                         m_rs_vn.vn_counter.quota =
2840                                 (m_rs_vn.vn_counter.rate *
2841                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2842 
2843                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2844 
2845                         /* read relevant values from mf_cfg struct in shmem */
2846                         vif_id =
2847                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2848                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2849                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2850                         vlan_val =
2851                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2852                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2853                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2854                         vlan_prio = (mf_config &
2855                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2856                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2857                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2858                         vlan_mode =
2859                                 (MF_CFG_RD(bp,
2860                                            func_mf_config[func].afex_config) &
2861                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2862                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2863                         allowed_prio =
2864                                 (MF_CFG_RD(bp,
2865                                            func_mf_config[func].afex_config) &
2866                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2867                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2868 
2869                         /* send ramrod to FW, return in case of failure */
2870                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2871                                                    allowed_prio))
2872                                 return;
2873 
2874                         bp->afex_def_vlan_tag = vlan_val;
2875                         bp->afex_vlan_mode = vlan_mode;
2876                 } else {
2877                         /* notify link down because BP->flags is disabled */
2878                         bnx2x_link_report(bp);
2879 
2880                         /* send INVALID VIF ramrod to FW */
2881                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2882 
2883                         /* Reset the default afex VLAN */
2884                         bp->afex_def_vlan_tag = -1;
2885                 }
2886         }
2887 }
2888 
2889 static void bnx2x_pmf_update(struct bnx2x *bp)
2890 {
2891         int port = BP_PORT(bp);
2892         u32 val;
2893 
2894         bp->port.pmf = 1;
2895         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2896 
2897         /*
2898          * We need the mb() to ensure the ordering between the writing to
2899          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2900          */
2901         smp_mb();
2902 
2903         /* queue a periodic task */
2904         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2905 
2906         bnx2x_dcbx_pmf_update(bp);
2907 
2908         /* enable nig attention */
2909         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2910         if (bp->common.int_block == INT_BLOCK_HC) {
2911                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2912                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2913         } else if (!CHIP_IS_E1x(bp)) {
2914                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2915                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2916         }
2917 
2918         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2919 }
2920 
2921 /* end of Link */
2922 
2923 /* slow path */
2924 
2925 /*
2926  * General service functions
2927  */
2928 
2929 /* send the MCP a request, block until there is a reply */
2930 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2931 {
2932         int mb_idx = BP_FW_MB_IDX(bp);
2933         u32 seq;
2934         u32 rc = 0;
2935         u32 cnt = 1;
2936         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2937 
2938         mutex_lock(&bp->fw_mb_mutex);
2939         seq = ++bp->fw_seq;
2940         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2941         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2942 
2943         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2944                         (command | seq), param);
2945 
2946         do {
2947                 /* let the FW do it's magic ... */
2948                 msleep(delay);
2949 
2950                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2951 
2952                 /* Give the FW up to 5 second (500*10ms) */
2953         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2954 
2955         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2956            cnt*delay, rc, seq);
2957 
2958         /* is this a reply to our command? */
2959         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2960                 rc &= FW_MSG_CODE_MASK;
2961         else {
2962                 /* FW BUG! */
2963                 BNX2X_ERR("FW failed to respond!\n");
2964                 bnx2x_fw_dump(bp);
2965                 rc = 0;
2966         }
2967         mutex_unlock(&bp->fw_mb_mutex);
2968 
2969         return rc;
2970 }
2971 
2972 static void storm_memset_func_cfg(struct bnx2x *bp,
2973                                  struct tstorm_eth_function_common_config *tcfg,
2974                                  u16 abs_fid)
2975 {
2976         size_t size = sizeof(struct tstorm_eth_function_common_config);
2977 
2978         u32 addr = BAR_TSTRORM_INTMEM +
2979                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2980 
2981         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2982 }
2983 
2984 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2985 {
2986         if (CHIP_IS_E1x(bp)) {
2987                 struct tstorm_eth_function_common_config tcfg = {0};
2988 
2989                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2990         }
2991 
2992         /* Enable the function in the FW */
2993         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2994         storm_memset_func_en(bp, p->func_id, 1);
2995 
2996         /* spq */
2997         if (p->func_flgs & FUNC_FLG_SPQ) {
2998                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2999                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3000                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3001         }
3002 }
3003 
3004 /**
3005  * bnx2x_get_common_flags - Return common flags
3006  *
3007  * @bp          device handle
3008  * @fp          queue handle
3009  * @zero_stats  TRUE if statistics zeroing is needed
3010  *
3011  * Return the flags that are common for the Tx-only and not normal connections.
3012  */
3013 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3014                                             struct bnx2x_fastpath *fp,
3015                                             bool zero_stats)
3016 {
3017         unsigned long flags = 0;
3018 
3019         /* PF driver will always initialize the Queue to an ACTIVE state */
3020         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3021 
3022         /* tx only connections collect statistics (on the same index as the
3023          * parent connection). The statistics are zeroed when the parent
3024          * connection is initialized.
3025          */
3026 
3027         __set_bit(BNX2X_Q_FLG_STATS, &flags);
3028         if (zero_stats)
3029                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3030 
3031         if (bp->flags & TX_SWITCHING)
3032                 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3033 
3034         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3035         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3036 
3037 #ifdef BNX2X_STOP_ON_ERROR
3038         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3039 #endif
3040 
3041         return flags;
3042 }
3043 
3044 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3045                                        struct bnx2x_fastpath *fp,
3046                                        bool leading)
3047 {
3048         unsigned long flags = 0;
3049 
3050         /* calculate other queue flags */
3051         if (IS_MF_SD(bp))
3052                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3053 
3054         if (IS_FCOE_FP(fp)) {
3055                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3056                 /* For FCoE - force usage of default priority (for afex) */
3057                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3058         }
3059 
3060         if (!fp->disable_tpa) {
3061                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3062                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3063                 if (fp->mode == TPA_MODE_GRO)
3064                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3065         }
3066 
3067         if (leading) {
3068                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3069                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3070         }
3071 
3072         /* Always set HW VLAN stripping */
3073         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3074 
3075         /* configure silent vlan removal */
3076         if (IS_MF_AFEX(bp))
3077                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3078 
3079         return flags | bnx2x_get_common_flags(bp, fp, true);
3080 }
3081 
3082 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3083         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3084         u8 cos)
3085 {
3086         gen_init->stat_id = bnx2x_stats_id(fp);
3087         gen_init->spcl_id = fp->cl_id;
3088 
3089         /* Always use mini-jumbo MTU for FCoE L2 ring */
3090         if (IS_FCOE_FP(fp))
3091                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3092         else
3093                 gen_init->mtu = bp->dev->mtu;
3094 
3095         gen_init->cos = cos;
3096 }
3097 
3098 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3099         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3100         struct bnx2x_rxq_setup_params *rxq_init)
3101 {
3102         u8 max_sge = 0;
3103         u16 sge_sz = 0;
3104         u16 tpa_agg_size = 0;
3105 
3106         if (!fp->disable_tpa) {
3107                 pause->sge_th_lo = SGE_TH_LO(bp);
3108                 pause->sge_th_hi = SGE_TH_HI(bp);
3109 
3110                 /* validate SGE ring has enough to cross high threshold */
3111                 WARN_ON(bp->dropless_fc &&
3112                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3113                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3114 
3115                 tpa_agg_size = TPA_AGG_SIZE;
3116                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3117                         SGE_PAGE_SHIFT;
3118                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3119                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3120                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3121         }
3122 
3123         /* pause - not for e1 */
3124         if (!CHIP_IS_E1(bp)) {
3125                 pause->bd_th_lo = BD_TH_LO(bp);
3126                 pause->bd_th_hi = BD_TH_HI(bp);
3127 
3128                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3129                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3130                 /*
3131                  * validate that rings have enough entries to cross
3132                  * high thresholds
3133                  */
3134                 WARN_ON(bp->dropless_fc &&
3135                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3136                                 bp->rx_ring_size);
3137                 WARN_ON(bp->dropless_fc &&
3138                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3139                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3140 
3141                 pause->pri_map = 1;
3142         }
3143 
3144         /* rxq setup */
3145         rxq_init->dscr_map = fp->rx_desc_mapping;
3146         rxq_init->sge_map = fp->rx_sge_mapping;
3147         rxq_init->rcq_map = fp->rx_comp_mapping;
3148         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3149 
3150         /* This should be a maximum number of data bytes that may be
3151          * placed on the BD (not including paddings).
3152          */
3153         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3154                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3155 
3156         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3157         rxq_init->tpa_agg_sz = tpa_agg_size;
3158         rxq_init->sge_buf_sz = sge_sz;
3159         rxq_init->max_sges_pkt = max_sge;
3160         rxq_init->rss_engine_id = BP_FUNC(bp);
3161         rxq_init->mcast_engine_id = BP_FUNC(bp);
3162 
3163         /* Maximum number or simultaneous TPA aggregation for this Queue.
3164          *
3165          * For PF Clients it should be the maximum available number.
3166          * VF driver(s) may want to define it to a smaller value.
3167          */
3168         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3169 
3170         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3171         rxq_init->fw_sb_id = fp->fw_sb_id;
3172 
3173         if (IS_FCOE_FP(fp))
3174                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3175         else
3176                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3177         /* configure silent vlan removal
3178          * if multi function mode is afex, then mask default vlan
3179          */
3180         if (IS_MF_AFEX(bp)) {
3181                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3182                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3183         }
3184 }
3185 
3186 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3187         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3188         u8 cos)
3189 {
3190         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3191         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3192         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3193         txq_init->fw_sb_id = fp->fw_sb_id;
3194 
3195         /*
3196          * set the tss leading client id for TX classification ==
3197          * leading RSS client id
3198          */
3199         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3200 
3201         if (IS_FCOE_FP(fp)) {
3202                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3203                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3204         }
3205 }
3206 
3207 static void bnx2x_pf_init(struct bnx2x *bp)
3208 {
3209         struct bnx2x_func_init_params func_init = {0};
3210         struct event_ring_data eq_data = { {0} };
3211         u16 flags;
3212 
3213         if (!CHIP_IS_E1x(bp)) {
3214                 /* reset IGU PF statistics: MSIX + ATTN */
3215                 /* PF */
3216                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3217                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3218                            (CHIP_MODE_IS_4_PORT(bp) ?
3219                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3220                 /* ATTN */
3221                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3222                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3223                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3224                            (CHIP_MODE_IS_4_PORT(bp) ?
3225                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3226         }
3227 
3228         /* function setup flags */
3229         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3230 
3231         /* This flag is relevant for E1x only.
3232          * E2 doesn't have a TPA configuration in a function level.
3233          */
3234         flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3235 
3236         func_init.func_flgs = flags;
3237         func_init.pf_id = BP_FUNC(bp);
3238         func_init.func_id = BP_FUNC(bp);
3239         func_init.spq_map = bp->spq_mapping;
3240         func_init.spq_prod = bp->spq_prod_idx;
3241 
3242         bnx2x_func_init(bp, &func_init);
3243 
3244         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3245 
3246         /*
3247          * Congestion management values depend on the link rate
3248          * There is no active link so initial link rate is set to 10 Gbps.
3249          * When the link comes up The congestion management values are
3250          * re-calculated according to the actual link rate.
3251          */
3252         bp->link_vars.line_speed = SPEED_10000;
3253         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3254 
3255         /* Only the PMF sets the HW */
3256         if (bp->port.pmf)
3257                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3258 
3259         /* init Event Queue - PCI bus guarantees correct endianity*/
3260         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3261         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3262         eq_data.producer = bp->eq_prod;
3263         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3264         eq_data.sb_id = DEF_SB_ID;
3265         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3266 }
3267 
3268 static void bnx2x_e1h_disable(struct bnx2x *bp)
3269 {
3270         int port = BP_PORT(bp);
3271 
3272         bnx2x_tx_disable(bp);
3273 
3274         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3275 }
3276 
3277 static void bnx2x_e1h_enable(struct bnx2x *bp)
3278 {
3279         int port = BP_PORT(bp);
3280 
3281         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3282 
3283         /* Tx queue should be only re-enabled */
3284         netif_tx_wake_all_queues(bp->dev);
3285 
3286         /*
3287          * Should not call netif_carrier_on since it will be called if the link
3288          * is up when checking for link state
3289          */
3290 }
3291 
3292 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3293 
3294 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3295 {
3296         struct eth_stats_info *ether_stat =
3297                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3298         struct bnx2x_vlan_mac_obj *mac_obj =
3299                 &bp->sp_objs->mac_obj;
3300         int i;
3301 
3302         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3303                 ETH_STAT_INFO_VERSION_LEN);
3304 
3305         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3306          * mac_local field in ether_stat struct. The base address is offset by 2
3307          * bytes to account for the field being 8 bytes but a mac address is
3308          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3309          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3310          * allocated by the ether_stat struct, so the macs will land in their
3311          * proper positions.
3312          */
3313         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3314                 memset(ether_stat->mac_local + i, 0,
3315                        sizeof(ether_stat->mac_local[0]));
3316         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3317                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3318                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3319                                 ETH_ALEN);
3320         ether_stat->mtu_size = bp->dev->mtu;
3321         if (bp->dev->features & NETIF_F_RXCSUM)
3322                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3323         if (bp->dev->features & NETIF_F_TSO)
3324                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3325         ether_stat->feature_flags |= bp->common.boot_mode;
3326 
3327         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3328 
3329         ether_stat->txq_size = bp->tx_ring_size;
3330         ether_stat->rxq_size = bp->rx_ring_size;
3331 
3332 #ifdef CONFIG_BNX2X_SRIOV
3333         ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3334 #endif
3335 }
3336 
3337 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3338 {
3339         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3340         struct fcoe_stats_info *fcoe_stat =
3341                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3342 
3343         if (!CNIC_LOADED(bp))
3344                 return;
3345 
3346         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3347 
3348         fcoe_stat->qos_priority =
3349                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3350 
3351         /* insert FCoE stats from ramrod response */
3352         if (!NO_FCOE(bp)) {
3353                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3354                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3355                         tstorm_queue_statistics;
3356 
3357                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3358                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3359                         xstorm_queue_statistics;
3360 
3361                 struct fcoe_statistics_params *fw_fcoe_stat =
3362                         &bp->fw_stats_data->fcoe;
3363 
3364                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3365                           fcoe_stat->rx_bytes_lo,
3366                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3367 
3368                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3369                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3370                           fcoe_stat->rx_bytes_lo,
3371                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3372 
3373                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3374                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3375                           fcoe_stat->rx_bytes_lo,
3376                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3377 
3378                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3379                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3380                           fcoe_stat->rx_bytes_lo,
3381                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3382 
3383                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3384                           fcoe_stat->rx_frames_lo,
3385                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3386 
3387                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3388                           fcoe_stat->rx_frames_lo,
3389                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3390 
3391                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3392                           fcoe_stat->rx_frames_lo,
3393                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3394 
3395                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3396                           fcoe_stat->rx_frames_lo,
3397                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3398 
3399                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3400                           fcoe_stat->tx_bytes_lo,
3401                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3402 
3403                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3404                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3405                           fcoe_stat->tx_bytes_lo,
3406                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3407 
3408                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3409                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3410                           fcoe_stat->tx_bytes_lo,
3411                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3412 
3413                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3414                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3415                           fcoe_stat->tx_bytes_lo,
3416                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3417 
3418                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3419                           fcoe_stat->tx_frames_lo,
3420                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3421 
3422                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3423                           fcoe_stat->tx_frames_lo,
3424                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3425 
3426                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3427                           fcoe_stat->tx_frames_lo,
3428                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3429 
3430                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3431                           fcoe_stat->tx_frames_lo,
3432                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3433         }
3434 
3435         /* ask L5 driver to add data to the struct */
3436         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3437 }
3438 
3439 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3440 {
3441         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3442         struct iscsi_stats_info *iscsi_stat =
3443                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3444 
3445         if (!CNIC_LOADED(bp))
3446                 return;
3447 
3448         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3449                ETH_ALEN);
3450 
3451         iscsi_stat->qos_priority =
3452                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3453 
3454         /* ask L5 driver to add data to the struct */
3455         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3456 }
3457 
3458 /* called due to MCP event (on pmf):
3459  *      reread new bandwidth configuration
3460  *      configure FW
3461  *      notify others function about the change
3462  */
3463 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3464 {
3465         if (bp->link_vars.link_up) {
3466                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3467                 bnx2x_link_sync_notify(bp);
3468         }
3469         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3470 }
3471 
3472 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3473 {
3474         bnx2x_config_mf_bw(bp);
3475         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3476 }
3477 
3478 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3479 {
3480         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3481         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3482 }
3483 
3484 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH        (20)
3485 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT         (25)
3486 
3487 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3488 {
3489         enum drv_info_opcode op_code;
3490         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3491         bool release = false;
3492         int wait;
3493 
3494         /* if drv_info version supported by MFW doesn't match - send NACK */
3495         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3496                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3497                 return;
3498         }
3499 
3500         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3501                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3502 
3503         /* Must prevent other flows from accessing drv_info_to_mcp */
3504         mutex_lock(&bp->drv_info_mutex);
3505 
3506         memset(&bp->slowpath->drv_info_to_mcp, 0,
3507                sizeof(union drv_info_to_mcp));
3508 
3509         switch (op_code) {
3510         case ETH_STATS_OPCODE:
3511                 bnx2x_drv_info_ether_stat(bp);
3512                 break;
3513         case FCOE_STATS_OPCODE:
3514                 bnx2x_drv_info_fcoe_stat(bp);
3515                 break;
3516         case ISCSI_STATS_OPCODE:
3517                 bnx2x_drv_info_iscsi_stat(bp);
3518                 break;
3519         default:
3520                 /* if op code isn't supported - send NACK */
3521                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3522                 goto out;
3523         }
3524 
3525         /* if we got drv_info attn from MFW then these fields are defined in
3526          * shmem2 for sure
3527          */
3528         SHMEM2_WR(bp, drv_info_host_addr_lo,
3529                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3530         SHMEM2_WR(bp, drv_info_host_addr_hi,
3531                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3532 
3533         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3534 
3535         /* Since possible management wants both this and get_driver_version
3536          * need to wait until management notifies us it finished utilizing
3537          * the buffer.
3538          */
3539         if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3540                 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3541         } else if (!bp->drv_info_mng_owner) {
3542                 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3543 
3544                 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3545                         u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3546 
3547                         /* Management is done; need to clear indication */
3548                         if (indication & bit) {
3549                                 SHMEM2_WR(bp, mfw_drv_indication,
3550                                           indication & ~bit);
3551                                 release = true;
3552                                 break;
3553                         }
3554 
3555                         msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3556                 }
3557         }
3558         if (!release) {
3559                 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3560                 bp->drv_info_mng_owner = true;
3561         }
3562 
3563 out:
3564         mutex_unlock(&bp->drv_info_mutex);
3565 }
3566 
3567 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3568 {
3569         u8 vals[4];
3570         int i = 0;
3571 
3572         if (bnx2x_format) {
3573                 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3574                            &vals[0], &vals[1], &vals[2], &vals[3]);
3575                 if (i > 0)
3576                         vals[0] -= '';
3577         } else {
3578                 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3579                            &vals[0], &vals[1], &vals[2], &vals[3]);
3580         }
3581 
3582         while (i < 4)
3583                 vals[i++] = 0;
3584 
3585         return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3586 }
3587 
3588 void bnx2x_update_mng_version(struct bnx2x *bp)
3589 {
3590         u32 iscsiver = DRV_VER_NOT_LOADED;
3591         u32 fcoever = DRV_VER_NOT_LOADED;
3592         u32 ethver = DRV_VER_NOT_LOADED;
3593         int idx = BP_FW_MB_IDX(bp);
3594         u8 *version;
3595 
3596         if (!SHMEM2_HAS(bp, func_os_drv_ver))
3597                 return;
3598 
3599         mutex_lock(&bp->drv_info_mutex);
3600         /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3601         if (bp->drv_info_mng_owner)
3602                 goto out;
3603 
3604         if (bp->state != BNX2X_STATE_OPEN)
3605                 goto out;
3606 
3607         /* Parse ethernet driver version */
3608         ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3609         if (!CNIC_LOADED(bp))
3610                 goto out;
3611 
3612         /* Try getting storage driver version via cnic */
3613         memset(&bp->slowpath->drv_info_to_mcp, 0,
3614                sizeof(union drv_info_to_mcp));
3615         bnx2x_drv_info_iscsi_stat(bp);
3616         version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3617         iscsiver = bnx2x_update_mng_version_utility(version, false);
3618 
3619         memset(&bp->slowpath->drv_info_to_mcp, 0,
3620                sizeof(union drv_info_to_mcp));
3621         bnx2x_drv_info_fcoe_stat(bp);
3622         version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3623         fcoever = bnx2x_update_mng_version_utility(version, false);
3624 
3625 out:
3626         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3627         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3628         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3629 
3630         mutex_unlock(&bp->drv_info_mutex);
3631 
3632         DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3633            ethver, iscsiver, fcoever);
3634 }
3635 
3636 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3637 {
3638         DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3639 
3640         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3641 
3642                 /*
3643                  * This is the only place besides the function initialization
3644                  * where the bp->flags can change so it is done without any
3645                  * locks
3646                  */
3647                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3648                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3649                         bp->flags |= MF_FUNC_DIS;
3650 
3651                         bnx2x_e1h_disable(bp);
3652                 } else {
3653                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3654                         bp->flags &= ~MF_FUNC_DIS;
3655 
3656                         bnx2x_e1h_enable(bp);
3657                 }
3658                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3659         }
3660         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3661                 bnx2x_config_mf_bw(bp);
3662                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3663         }
3664 
3665         /* Report results to MCP */
3666         if (dcc_event)
3667                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3668         else
3669                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3670 }
3671 
3672 /* must be called under the spq lock */
3673 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3674 {
3675         struct eth_spe *next_spe = bp->spq_prod_bd;
3676 
3677         if (bp->spq_prod_bd == bp->spq_last_bd) {
3678                 bp->spq_prod_bd = bp->spq;
3679                 bp->spq_prod_idx = 0;
3680                 DP(BNX2X_MSG_SP, "end of spq\n");
3681         } else {
3682                 bp->spq_prod_bd++;
3683                 bp->spq_prod_idx++;
3684         }
3685         return next_spe;
3686 }
3687 
3688 /* must be called under the spq lock */
3689 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3690 {
3691         int func = BP_FUNC(bp);
3692 
3693         /*
3694          * Make sure that BD data is updated before writing the producer:
3695          * BD data is written to the memory, the producer is read from the
3696          * memory, thus we need a full memory barrier to ensure the ordering.
3697          */
3698         mb();
3699 
3700         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3701                  bp->spq_prod_idx);
3702         mmiowb();
3703 }
3704 
3705 /**
3706  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3707  *
3708  * @cmd:        command to check
3709  * @cmd_type:   command type
3710  */
3711 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3712 {
3713         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3714             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3715             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3716             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3717             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3718             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3719             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3720                 return true;
3721         else
3722                 return false;
3723 }
3724 
3725 /**
3726  * bnx2x_sp_post - place a single command on an SP ring
3727  *
3728  * @bp:         driver handle
3729  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3730  * @cid:        SW CID the command is related to
3731  * @data_hi:    command private data address (high 32 bits)
3732  * @data_lo:    command private data address (low 32 bits)
3733  * @cmd_type:   command type (e.g. NONE, ETH)
3734  *
3735  * SP data is handled as if it's always an address pair, thus data fields are
3736  * not swapped to little endian in upper functions. Instead this function swaps
3737  * data as if it's two u32 fields.
3738  */
3739 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3740                   u32 data_hi, u32 data_lo, int cmd_type)
3741 {
3742         struct eth_spe *spe;
3743         u16 type;
3744         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3745 
3746 #ifdef BNX2X_STOP_ON_ERROR
3747         if (unlikely(bp->panic)) {
3748                 BNX2X_ERR("Can't post SP when there is panic\n");
3749                 return -EIO;
3750         }
3751 #endif
3752 
3753         spin_lock_bh(&bp->spq_lock);
3754 
3755         if (common) {
3756                 if (!atomic_read(&bp->eq_spq_left)) {
3757                         BNX2X_ERR("BUG! EQ ring full!\n");
3758                         spin_unlock_bh(&bp->spq_lock);
3759                         bnx2x_panic();
3760                         return -EBUSY;
3761                 }
3762         } else if (!atomic_read(&bp->cq_spq_left)) {
3763                         BNX2X_ERR("BUG! SPQ ring full!\n");
3764                         spin_unlock_bh(&bp->spq_lock);
3765                         bnx2x_panic();
3766                         return -EBUSY;
3767         }
3768 
3769         spe = bnx2x_sp_get_next(bp);
3770 
3771         /* CID needs port number to be encoded int it */
3772         spe->hdr.conn_and_cmd_data =
3773                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3774                                     HW_CID(bp, cid));
3775 
3776         /* In some cases, type may already contain the func-id
3777          * mainly in SRIOV related use cases, so we add it here only
3778          * if it's not already set.
3779          */
3780         if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3781                 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3782                         SPE_HDR_CONN_TYPE;
3783                 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3784                          SPE_HDR_FUNCTION_ID);
3785         } else {
3786                 type = cmd_type;
3787         }
3788 
3789         spe->hdr.type = cpu_to_le16(type);
3790 
3791         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3792         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3793 
3794         /*
3795          * It's ok if the actual decrement is issued towards the memory
3796          * somewhere between the spin_lock and spin_unlock. Thus no
3797          * more explicit memory barrier is needed.
3798          */
3799         if (common)
3800                 atomic_dec(&bp->eq_spq_left);
3801         else
3802                 atomic_dec(&bp->cq_spq_left);
3803 
3804         DP(BNX2X_MSG_SP,
3805            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3806            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3807            (u32)(U64_LO(bp->spq_mapping) +
3808            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3809            HW_CID(bp, cid), data_hi, data_lo, type,
3810            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3811 
3812         bnx2x_sp_prod_update(bp);
3813         spin_unlock_bh(&bp->spq_lock);
3814         return 0;
3815 }
3816 
3817 /* acquire split MCP access lock register */
3818 static int bnx2x_acquire_alr(struct bnx2x *bp)
3819 {
3820         u32 j, val;
3821         int rc = 0;
3822 
3823         might_sleep();
3824         for (j = 0; j < 1000; j++) {
3825                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3826                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3827                 if (val & MCPR_ACCESS_LOCK_LOCK)
3828                         break;
3829 
3830                 usleep_range(5000, 10000);
3831         }
3832         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3833                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3834                 rc = -EBUSY;
3835         }
3836 
3837         return rc;
3838 }
3839 
3840 /* release split MCP access lock register */
3841 static void bnx2x_release_alr(struct bnx2x *bp)
3842 {
3843         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3844 }
3845 
3846 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3847 #define BNX2X_DEF_SB_IDX        0x0002
3848 
3849 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3850 {
3851         struct host_sp_status_block *def_sb = bp->def_status_blk;
3852         u16 rc = 0;
3853 
3854         barrier(); /* status block is written to by the chip */
3855         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3856                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3857                 rc |= BNX2X_DEF_SB_ATT_IDX;
3858         }
3859 
3860         if (bp->def_idx != def_sb->sp_sb.running_index) {
3861                 bp->def_idx = def_sb->sp_sb.running_index;
3862                 rc |= BNX2X_DEF_SB_IDX;
3863         }
3864 
3865         /* Do not reorder: indices reading should complete before handling */
3866         barrier();
3867         return rc;
3868 }
3869 
3870 /*
3871  * slow path service functions
3872  */
3873 
3874 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3875 {
3876         int port = BP_PORT(bp);
3877         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3878                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3879         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3880                                        NIG_REG_MASK_INTERRUPT_PORT0;
3881         u32 aeu_mask;
3882         u32 nig_mask = 0;
3883         u32 reg_addr;
3884 
3885         if (bp->attn_state & asserted)
3886                 BNX2X_ERR("IGU ERROR\n");
3887 
3888         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3889         aeu_mask = REG_RD(bp, aeu_addr);
3890 
3891         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
3892            aeu_mask, asserted);
3893         aeu_mask &= ~(asserted & 0x3ff);
3894         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3895 
3896         REG_WR(bp, aeu_addr, aeu_mask);
3897         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3898 
3899         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3900         bp->attn_state |= asserted;
3901         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3902 
3903         if (asserted & ATTN_HARD_WIRED_MASK) {
3904                 if (asserted & ATTN_NIG_FOR_FUNC) {
3905 
3906                         bnx2x_acquire_phy_lock(bp);
3907 
3908                         /* save nig interrupt mask */
3909                         nig_mask = REG_RD(bp, nig_int_mask_addr);
3910 
3911                         /* If nig_mask is not set, no need to call the update
3912                          * function.
3913                          */
3914                         if (nig_mask) {
3915                                 REG_WR(bp, nig_int_mask_addr, 0);
3916 
3917                                 bnx2x_link_attn(bp);
3918                         }
3919 
3920                         /* handle unicore attn? */
3921                 }
3922                 if (asserted & ATTN_SW_TIMER_4_FUNC)
3923                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3924 
3925                 if (asserted & GPIO_2_FUNC)
3926                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3927 
3928                 if (asserted & GPIO_3_FUNC)
3929                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3930 
3931                 if (asserted & GPIO_4_FUNC)
3932                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3933 
3934                 if (port == 0) {
3935                         if (asserted & ATTN_GENERAL_ATTN_1) {
3936                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3937                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3938                         }
3939                         if (asserted & ATTN_GENERAL_ATTN_2) {
3940                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3941                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3942                         }
3943                         if (asserted & ATTN_GENERAL_ATTN_3) {
3944                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3945                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3946                         }
3947                 } else {
3948                         if (asserted & ATTN_GENERAL_ATTN_4) {
3949                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3950                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3951                         }
3952                         if (asserted & ATTN_GENERAL_ATTN_5) {
3953                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3954                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3955                         }
3956                         if (asserted & ATTN_GENERAL_ATTN_6) {
3957                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3958                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3959                         }
3960                 }
3961 
3962         } /* if hardwired */
3963 
3964         if (bp->common.int_block == INT_BLOCK_HC)
3965                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3966                             COMMAND_REG_ATTN_BITS_SET);
3967         else
3968                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3969 
3970         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3971            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3972         REG_WR(bp, reg_addr, asserted);
3973 
3974         /* now set back the mask */
3975         if (asserted & ATTN_NIG_FOR_FUNC) {
3976                 /* Verify that IGU ack through BAR was written before restoring
3977                  * NIG mask. This loop should exit after 2-3 iterations max.
3978                  */
3979                 if (bp->common.int_block != INT_BLOCK_HC) {
3980                         u32 cnt = 0, igu_acked;
3981                         do {
3982                                 igu_acked = REG_RD(bp,
3983                                                    IGU_REG_ATTENTION_ACK_BITS);
3984                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3985                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
3986                         if (!igu_acked)
3987                                 DP(NETIF_MSG_HW,
3988                                    "Failed to verify IGU ack on time\n");
3989                         barrier();
3990                 }
3991                 REG_WR(bp, nig_int_mask_addr, nig_mask);
3992                 bnx2x_release_phy_lock(bp);
3993         }
3994 }
3995 
3996 static void bnx2x_fan_failure(struct bnx2x *bp)
3997 {
3998         int port = BP_PORT(bp);
3999         u32 ext_phy_config;
4000         /* mark the failure */
4001         ext_phy_config =
4002                 SHMEM_RD(bp,
4003                          dev_info.port_hw_config[port].external_phy_config);
4004 
4005         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4006         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4007         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4008                  ext_phy_config);
4009 
4010         /* log the failure */
4011         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4012                             "Please contact OEM Support for assistance\n");
4013 
4014         /* Schedule device reset (unload)
4015          * This is due to some boards consuming sufficient power when driver is
4016          * up to overheat if fan fails.
4017          */
4018         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4019 }
4020 
4021 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4022 {
4023         int port = BP_PORT(bp);
4024         int reg_offset;
4025         u32 val;
4026 
4027         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4028                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4029 
4030         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4031 
4032                 val = REG_RD(bp, reg_offset);
4033                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4034                 REG_WR(bp, reg_offset, val);
4035 
4036                 BNX2X_ERR("SPIO5 hw attention\n");
4037 
4038                 /* Fan failure attention */
4039                 bnx2x_hw_reset_phy(&bp->link_params);
4040                 bnx2x_fan_failure(bp);
4041         }
4042 
4043         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4044                 bnx2x_acquire_phy_lock(bp);
4045                 bnx2x_handle_module_detect_int(&bp->link_params);
4046                 bnx2x_release_phy_lock(bp);
4047         }
4048 
4049         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4050 
4051                 val = REG_RD(bp, reg_offset);
4052                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4053                 REG_WR(bp, reg_offset, val);
4054 
4055                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4056                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
4057                 bnx2x_panic();
4058         }
4059 }
4060 
4061 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4062 {
4063         u32 val;
4064 
4065         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4066 
4067                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4068                 BNX2X_ERR("DB hw attention 0x%x\n", val);
4069                 /* DORQ discard attention */
4070                 if (val & 0x2)
4071                         BNX2X_ERR("FATAL error from DORQ\n");
4072         }
4073 
4074         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4075 
4076                 int port = BP_PORT(bp);
4077                 int reg_offset;
4078 
4079                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4080                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4081 
4082                 val = REG_RD(bp, reg_offset);
4083                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4084                 REG_WR(bp, reg_offset, val);
4085 
4086                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4087                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
4088                 bnx2x_panic();
4089         }
4090 }
4091 
4092 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4093 {
4094         u32 val;
4095 
4096         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4097 
4098                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4099                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4100                 /* CFC error attention */
4101                 if (val & 0x2)
4102                         BNX2X_ERR("FATAL error from CFC\n");
4103         }
4104 
4105         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4106                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4107                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4108                 /* RQ_USDMDP_FIFO_OVERFLOW */
4109                 if (val & 0x18000)
4110                         BNX2X_ERR("FATAL error from PXP\n");
4111 
4112                 if (!CHIP_IS_E1x(bp)) {
4113                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4114                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4115                 }
4116         }
4117 
4118         if (attn & HW_INTERRUT_ASSERT_SET_2) {
4119 
4120                 int port = BP_PORT(bp);
4121                 int reg_offset;
4122 
4123                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4124                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4125 
4126                 val = REG_RD(bp, reg_offset);
4127                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4128                 REG_WR(bp, reg_offset, val);
4129 
4130                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4131                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
4132                 bnx2x_panic();
4133         }
4134 }
4135 
4136 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4137 {
4138         u32 val;
4139 
4140         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4141 
4142                 if (attn & BNX2X_PMF_LINK_ASSERT) {
4143                         int func = BP_FUNC(bp);
4144 
4145                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4146                         bnx2x_read_mf_cfg(bp);
4147                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4148                                         func_mf_config[BP_ABS_FUNC(bp)].config);
4149                         val = SHMEM_RD(bp,
4150                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
4151                         if (val & DRV_STATUS_DCC_EVENT_MASK)
4152                                 bnx2x_dcc_event(bp,
4153                                             (val & DRV_STATUS_DCC_EVENT_MASK));
4154 
4155                         if (val & DRV_STATUS_SET_MF_BW)
4156                                 bnx2x_set_mf_bw(bp);
4157 
4158                         if (val & DRV_STATUS_DRV_INFO_REQ)
4159                                 bnx2x_handle_drv_info_req(bp);
4160 
4161                         if (val & DRV_STATUS_VF_DISABLED)
4162                                 bnx2x_schedule_iov_task(bp,
4163                                                         BNX2X_IOV_HANDLE_FLR);
4164 
4165                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4166                                 bnx2x_pmf_update(bp);
4167 
4168                         if (bp->port.pmf &&
4169                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4170                                 bp->dcbx_enabled > 0)
4171                                 /* start dcbx state machine */
4172                                 bnx2x_dcbx_set_params(bp,
4173                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4174                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4175                                 bnx2x_handle_afex_cmd(bp,
4176                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4177                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4178                                 bnx2x_handle_eee_event(bp);
4179                         if (bp->link_vars.periodic_flags &
4180                             PERIODIC_FLAGS_LINK_EVENT) {
4181                                 /*  sync with link */
4182                                 bnx2x_acquire_phy_lock(bp);
4183                                 bp->link_vars.periodic_flags &=
4184                                         ~PERIODIC_FLAGS_LINK_EVENT;
4185                                 bnx2x_release_phy_lock(bp);
4186                                 if (IS_MF(bp))
4187                                         bnx2x_link_sync_notify(bp);
4188                                 bnx2x_link_report(bp);
4189                         }
4190                         /* Always call it here: bnx2x_link_report() will
4191                          * prevent the link indication duplication.
4192                          */
4193                         bnx2x__link_status_update(bp);
4194                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4195 
4196                         BNX2X_ERR("MC assert!\n");
4197                         bnx2x_mc_assert(bp);
4198                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4199                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4200                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4201                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4202                         bnx2x_panic();
4203 
4204                 } else if (attn & BNX2X_MCP_ASSERT) {
4205 
4206                         BNX2X_ERR("MCP assert!\n");
4207                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4208                         bnx2x_fw_dump(bp);
4209 
4210                 } else
4211                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4212         }
4213 
4214         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4215                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4216                 if (attn & BNX2X_GRC_TIMEOUT) {
4217                         val = CHIP_IS_E1(bp) ? 0 :
4218                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4219                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4220                 }
4221                 if (attn & BNX2X_GRC_RSV) {
4222                         val = CHIP_IS_E1(bp) ? 0 :
4223                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4224                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4225                 }
4226                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4227         }
4228 }
4229 
4230 /*
4231  * Bits map:
4232  * 0-7   - Engine0 load counter.
4233  * 8-15  - Engine1 load counter.
4234  * 16    - Engine0 RESET_IN_PROGRESS bit.
4235  * 17    - Engine1 RESET_IN_PROGRESS bit.
4236  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4237  *         on the engine
4238  * 19    - Engine1 ONE_IS_LOADED.
4239  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4240  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4241  *         just the one belonging to its engine).
4242  *
4243  */
4244 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4245 
4246 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4247 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4248 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4249 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4250 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4251 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4252 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4253 
4254 /*
4255  * Set the GLOBAL_RESET bit.
4256  *
4257  * Should be run under rtnl lock
4258  */
4259 void bnx2x_set_reset_global(struct bnx2x *bp)
4260 {
4261         u32 val;
4262         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4263         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4264         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4265         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4266 }
4267 
4268 /*
4269  * Clear the GLOBAL_RESET bit.
4270  *
4271  * Should be run under rtnl lock
4272  */
4273 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4274 {
4275         u32 val;
4276         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4277         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4278         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4279         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4280 }
4281 
4282 /*
4283  * Checks the GLOBAL_RESET bit.
4284  *
4285  * should be run under rtnl lock
4286  */
4287 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4288 {
4289         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4290 
4291         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4292         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4293 }
4294 
4295 /*
4296  * Clear RESET_IN_PROGRESS bit for the current engine.
4297  *
4298  * Should be run under rtnl lock
4299  */
4300 static void bnx2x_set_reset_done(struct bnx2x *bp)
4301 {
4302         u32 val;
4303         u32 bit = BP_PATH(bp) ?
4304                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4305         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4306         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4307 
4308         /* Clear the bit */
4309         val &= ~bit;
4310         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4311 
4312         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4313 }
4314 
4315 /*
4316  * Set RESET_IN_PROGRESS for the current engine.
4317  *
4318  * should be run under rtnl lock
4319  */
4320 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4321 {
4322         u32 val;
4323         u32 bit = BP_PATH(bp) ?
4324                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4325         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4326         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4327 
4328         /* Set the bit */
4329         val |= bit;
4330         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4331         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4332 }
4333 
4334 /*
4335  * Checks the RESET_IN_PROGRESS bit for the given engine.
4336  * should be run under rtnl lock
4337  */
4338 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4339 {
4340         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4341         u32 bit = engine ?
4342                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4343 
4344         /* return false if bit is set */
4345         return (val & bit) ? false : true;
4346 }
4347 
4348 /*
4349  * set pf load for the current pf.
4350  *
4351  * should be run under rtnl lock
4352  */
4353 void bnx2x_set_pf_load(struct bnx2x *bp)
4354 {
4355         u32 val1, val;
4356         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4357                              BNX2X_PATH0_LOAD_CNT_MASK;
4358         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4359                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4360 
4361         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4362         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4363 
4364         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4365 
4366         /* get the current counter value */
4367         val1 = (val & mask) >> shift;
4368 
4369         /* set bit of that PF */
4370         val1 |= (1 << bp->pf_num);
4371 
4372         /* clear the old value */
4373         val &= ~mask;
4374 
4375         /* set the new one */
4376         val |= ((val1 << shift) & mask);
4377 
4378         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4379         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4380 }
4381 
4382 /**
4383  * bnx2x_clear_pf_load - clear pf load mark
4384  *
4385  * @bp:         driver handle
4386  *
4387  * Should be run under rtnl lock.
4388  * Decrements the load counter for the current engine. Returns
4389  * whether other functions are still loaded
4390  */
4391 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4392 {
4393         u32 val1, val;
4394         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4395                              BNX2X_PATH0_LOAD_CNT_MASK;
4396         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4397                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4398 
4399         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4400         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4401         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4402 
4403         /* get the current counter value */
4404         val1 = (val & mask) >> shift;
4405 
4406         /* clear bit of that PF */
4407         val1 &= ~(1 << bp->pf_num);
4408 
4409         /* clear the old value */
4410         val &= ~mask;
4411 
4412         /* set the new one */
4413         val |= ((val1 << shift) & mask);
4414 
4415         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4416         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4417         return val1 != 0;
4418 }
4419 
4420 /*
4421  * Read the load status for the current engine.
4422  *
4423  * should be run under rtnl lock
4424  */
4425 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4426 {
4427         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4428                              BNX2X_PATH0_LOAD_CNT_MASK);
4429         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4430                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4431         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4432 
4433         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4434 
4435         val = (val & mask) >> shift;
4436 
4437         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4438            engine, val);
4439 
4440         return val != 0;
4441 }
4442 
4443 static void _print_parity(struct bnx2x *bp, u32 reg)
4444 {
4445         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4446 }
4447 
4448 static void _print_next_block(int idx, const char *blk)
4449 {
4450         pr_cont("%s%s", idx ? ", " : "", blk);
4451 }
4452 
4453 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4454                                             int *par_num, bool print)
4455 {
4456         u32 cur_bit;
4457         bool res;
4458         int i;
4459 
4460         res = false;
4461 
4462         for (i = 0; sig; i++) {
4463                 cur_bit = (0x1UL << i);
4464                 if (sig & cur_bit) {
4465                         res |= true; /* Each bit is real error! */
4466 
4467                         if (print) {
4468                                 switch (cur_bit) {
4469                                 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4470                                         _print_next_block((*par_num)++, "BRB");
4471                                         _print_parity(bp,
4472                                                       BRB1_REG_BRB1_PRTY_STS);
4473                                         break;
4474                                 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4475                                         _print_next_block((*par_num)++,
4476                                                           "PARSER");
4477                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4478                                         break;
4479                                 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4480                                         _print_next_block((*par_num)++, "TSDM");
4481                                         _print_parity(bp,
4482                                                       TSDM_REG_TSDM_PRTY_STS);
4483                                         break;
4484                                 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4485                                         _print_next_block((*par_num)++,
4486                                                           "SEARCHER");
4487                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4488                                         break;
4489                                 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4490                                         _print_next_block((*par_num)++, "TCM");
4491                                         _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4492                                         break;
4493                                 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4494                                         _print_next_block((*par_num)++,
4495                                                           "TSEMI");
4496                                         _print_parity(bp,
4497                                                       TSEM_REG_TSEM_PRTY_STS_0);
4498                                         _print_parity(bp,
4499                                                       TSEM_REG_TSEM_PRTY_STS_1);
4500                                         break;
4501                                 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4502                                         _print_next_block((*par_num)++, "XPB");
4503                                         _print_parity(bp, GRCBASE_XPB +
4504                                                           PB_REG_PB_PRTY_STS);
4505                                         break;
4506                                 }
4507                         }
4508 
4509                         /* Clear the bit */
4510                         sig &= ~cur_bit;
4511                 }
4512         }
4513 
4514         return res;
4515 }
4516 
4517 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4518                                             int *par_num, bool *global,
4519                                             bool print)
4520 {
4521         u32 cur_bit;
4522         bool res;
4523         int i;
4524 
4525         res = false;
4526 
4527         for (i = 0; sig; i++) {
4528                 cur_bit = (0x1UL << i);
4529                 if (sig & cur_bit) {
4530                         res |= true; /* Each bit is real error! */
4531                         switch (cur_bit) {
4532                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4533                                 if (print) {
4534                                         _print_next_block((*par_num)++, "PBF");
4535                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4536                                 }
4537                                 break;
4538                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4539                                 if (print) {
4540                                         _print_next_block((*par_num)++, "QM");
4541                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4542                                 }
4543                                 break;
4544                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4545                                 if (print) {
4546                                         _print_next_block((*par_num)++, "TM");
4547                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4548                                 }
4549                                 break;
4550                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4551                                 if (print) {
4552                                         _print_next_block((*par_num)++, "XSDM");
4553                                         _print_parity(bp,
4554                                                       XSDM_REG_XSDM_PRTY_STS);
4555                                 }
4556                                 break;
4557                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4558                                 if (print) {
4559                                         _print_next_block((*par_num)++, "XCM");
4560                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4561                                 }
4562                                 break;
4563                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4564                                 if (print) {
4565                                         _print_next_block((*par_num)++,
4566                                                           "XSEMI");
4567                                         _print_parity(bp,
4568                                                       XSEM_REG_XSEM_PRTY_STS_0);
4569                                         _print_parity(bp,
4570                                                       XSEM_REG_XSEM_PRTY_STS_1);
4571                                 }
4572                                 break;
4573                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4574                                 if (print) {
4575                                         _print_next_block((*par_num)++,
4576                                                           "DOORBELLQ");
4577                                         _print_parity(bp,
4578                                                       DORQ_REG_DORQ_PRTY_STS);
4579                                 }
4580                                 break;
4581                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4582                                 if (print) {
4583                                         _print_next_block((*par_num)++, "NIG");
4584                                         if (CHIP_IS_E1x(bp)) {
4585                                                 _print_parity(bp,
4586                                                         NIG_REG_NIG_PRTY_STS);
4587                                         } else {
4588                                                 _print_parity(bp,
4589                                                         NIG_REG_NIG_PRTY_STS_0);
4590                                                 _print_parity(bp,
4591                                                         NIG_REG_NIG_PRTY_STS_1);
4592                                         }
4593                                 }
4594                                 break;
4595                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4596                                 if (print)
4597                                         _print_next_block((*par_num)++,
4598                                                           "VAUX PCI CORE");
4599                                 *global = true;
4600                                 break;
4601                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4602                                 if (print) {
4603                                         _print_next_block((*par_num)++,
4604                                                           "DEBUG");
4605                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4606                                 }
4607                                 break;
4608                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4609                                 if (print) {
4610                                         _print_next_block((*par_num)++, "USDM");
4611                                         _print_parity(bp,
4612                                                       USDM_REG_USDM_PRTY_STS);
4613                                 }
4614                                 break;
4615                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4616                                 if (print) {
4617                                         _print_next_block((*par_num)++, "UCM");
4618                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4619                                 }
4620                                 break;
4621                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4622                                 if (print) {
4623                                         _print_next_block((*par_num)++,
4624                                                           "USEMI");
4625                                         _print_parity(bp,
4626                                                       USEM_REG_USEM_PRTY_STS_0);
4627                                         _print_parity(bp,
4628                                                       USEM_REG_USEM_PRTY_STS_1);
4629                                 }
4630                                 break;
4631                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4632                                 if (print) {
4633                                         _print_next_block((*par_num)++, "UPB");
4634                                         _print_parity(bp, GRCBASE_UPB +
4635                                                           PB_REG_PB_PRTY_STS);
4636                                 }
4637                                 break;
4638                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4639                                 if (print) {
4640                                         _print_next_block((*par_num)++, "CSDM");
4641                                         _print_parity(bp,
4642                                                       CSDM_REG_CSDM_PRTY_STS);
4643                                 }
4644                                 break;
4645                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4646                                 if (print) {
4647                                         _print_next_block((*par_num)++, "CCM");
4648                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4649                                 }
4650                                 break;
4651                         }
4652 
4653                         /* Clear the bit */
4654                         sig &= ~cur_bit;
4655                 }
4656         }
4657 
4658         return res;
4659 }
4660 
4661 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4662                                             int *par_num, bool print)
4663 {
4664         u32 cur_bit;
4665         bool res;
4666         int i;
4667 
4668         res = false;
4669 
4670         for (i = 0; sig; i++) {
4671                 cur_bit = (0x1UL << i);
4672                 if (sig & cur_bit) {
4673                         res |= true; /* Each bit is real error! */
4674                         if (print) {
4675                                 switch (cur_bit) {
4676                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4677                                         _print_next_block((*par_num)++,
4678                                                           "CSEMI");
4679                                         _print_parity(bp,
4680                                                       CSEM_REG_CSEM_PRTY_STS_0);
4681                                         _print_parity(bp,
4682                                                       CSEM_REG_CSEM_PRTY_STS_1);
4683                                         break;
4684                                 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4685                                         _print_next_block((*par_num)++, "PXP");
4686                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4687                                         _print_parity(bp,
4688                                                       PXP2_REG_PXP2_PRTY_STS_0);
4689                                         _print_parity(bp,
4690                                                       PXP2_REG_PXP2_PRTY_STS_1);
4691                                         break;
4692                                 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4693                                         _print_next_block((*par_num)++,
4694                                                           "PXPPCICLOCKCLIENT");
4695                                         break;
4696                                 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4697                                         _print_next_block((*par_num)++, "CFC");
4698                                         _print_parity(bp,
4699                                                       CFC_REG_CFC_PRTY_STS);
4700                                         break;
4701                                 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4702                                         _print_next_block((*par_num)++, "CDU");
4703                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4704                                         break;
4705                                 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4706                                         _print_next_block((*par_num)++, "DMAE");
4707                                         _print_parity(bp,
4708                                                       DMAE_REG_DMAE_PRTY_STS);
4709                                         break;
4710                                 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4711                                         _print_next_block((*par_num)++, "IGU");
4712                                         if (CHIP_IS_E1x(bp))
4713                                                 _print_parity(bp,
4714                                                         HC_REG_HC_PRTY_STS);
4715                                         else
4716                                                 _print_parity(bp,
4717                                                         IGU_REG_IGU_PRTY_STS);
4718                                         break;
4719                                 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4720                                         _print_next_block((*par_num)++, "MISC");
4721                                         _print_parity(bp,
4722                                                       MISC_REG_MISC_PRTY_STS);
4723                                         break;
4724                                 }
4725                         }
4726 
4727                         /* Clear the bit */
4728                         sig &= ~cur_bit;
4729                 }
4730         }
4731 
4732         return res;
4733 }
4734 
4735 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4736                                             int *par_num, bool *global,
4737                                             bool print)
4738 {
4739         bool res = false;
4740         u32 cur_bit;
4741         int i;
4742 
4743         for (i = 0; sig; i++) {
4744                 cur_bit = (0x1UL << i);
4745                 if (sig & cur_bit) {
4746                         switch (cur_bit) {
4747                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4748                                 if (print)
4749                                         _print_next_block((*par_num)++,
4750                                                           "MCP ROM");
4751                                 *global = true;
4752                                 res |= true;
4753                                 break;
4754                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4755                                 if (print)
4756                                         _print_next_block((*par_num)++,
4757                                                           "MCP UMP RX");
4758                                 *global = true;
4759                                 res |= true;
4760                                 break;
4761                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4762                                 if (print)
4763                                         _print_next_block((*par_num)++,
4764                                                           "MCP UMP TX");
4765                                 *global = true;
4766                                 res |= true;
4767                                 break;
4768                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4769                                 if (print)
4770                                         _print_next_block((*par_num)++,
4771                                                           "MCP SCPAD");
4772                                 /* clear latched SCPAD PATIRY from MCP */
4773                                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4774                                        1UL << 10);
4775                                 break;
4776                         }
4777 
4778                         /* Clear the bit */
4779                         sig &= ~cur_bit;
4780                 }
4781         }
4782 
4783         return res;
4784 }
4785 
4786 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4787                                             int *par_num, bool print)
4788 {
4789         u32 cur_bit;
4790         bool res;
4791         int i;
4792 
4793         res = false;
4794 
4795         for (i = 0; sig; i++) {
4796                 cur_bit = (0x1UL << i);
4797                 if (sig & cur_bit) {
4798                         res |= true; /* Each bit is real error! */
4799                         if (print) {
4800                                 switch (cur_bit) {
4801                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4802                                         _print_next_block((*par_num)++,
4803                                                           "PGLUE_B");
4804                                         _print_parity(bp,
4805                                                       PGLUE_B_REG_PGLUE_B_PRTY_STS);
4806                                         break;
4807                                 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4808                                         _print_next_block((*par_num)++, "ATC");
4809                                         _print_parity(bp,
4810                                                       ATC_REG_ATC_PRTY_STS);
4811                                         break;
4812                                 }
4813                         }
4814                         /* Clear the bit */
4815                         sig &= ~cur_bit;
4816                 }
4817         }
4818 
4819         return res;
4820 }
4821 
4822 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4823                               u32 *sig)
4824 {
4825         bool res = false;
4826 
4827         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4828             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4829             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4830             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4831             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4832                 int par_num = 0;
4833                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4834                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4835                           sig[0] & HW_PRTY_ASSERT_SET_0,
4836                           sig[1] & HW_PRTY_ASSERT_SET_1,
4837                           sig[2] & HW_PRTY_ASSERT_SET_2,
4838                           sig[3] & HW_PRTY_ASSERT_SET_3,
4839                           sig[4] & HW_PRTY_ASSERT_SET_4);
4840                 if (print)
4841                         netdev_err(bp->dev,
4842                                    "Parity errors detected in blocks: ");
4843                 res |= bnx2x_check_blocks_with_parity0(bp,
4844                         sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4845                 res |= bnx2x_check_blocks_with_parity1(bp,
4846                         sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4847                 res |= bnx2x_check_blocks_with_parity2(bp,
4848                         sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4849                 res |= bnx2x_check_blocks_with_parity3(bp,
4850                         sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4851                 res |= bnx2x_check_blocks_with_parity4(bp,
4852                         sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4853 
4854                 if (print)
4855                         pr_cont("\n");
4856         }
4857 
4858         return res;
4859 }
4860 
4861 /**
4862  * bnx2x_chk_parity_attn - checks for parity attentions.
4863  *
4864  * @bp:         driver handle
4865  * @global:     true if there was a global attention
4866  * @print:      show parity attention in syslog
4867  */
4868 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4869 {
4870         struct attn_route attn = { {0} };
4871         int port = BP_PORT(bp);
4872 
4873         attn.sig[0] = REG_RD(bp,
4874                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4875                              port*4);
4876         attn.sig[1] = REG_RD(bp,
4877                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4878                              port*4);
4879         attn.sig[2] = REG_RD(bp,
4880                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4881                              port*4);
4882         attn.sig[3] = REG_RD(bp,
4883                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4884                              port*4);
4885         /* Since MCP attentions can't be disabled inside the block, we need to
4886          * read AEU registers to see whether they're currently disabled
4887          */
4888         attn.sig[3] &= ((REG_RD(bp,
4889                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4890                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
4891                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
4892                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
4893 
4894         if (!CHIP_IS_E1x(bp))
4895                 attn.sig[4] = REG_RD(bp,
4896                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4897                                      port*4);
4898 
4899         return bnx2x_parity_attn(bp, global, print, attn.sig);
4900 }
4901 
4902 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4903 {
4904         u32 val;
4905         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4906 
4907                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4908                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4909                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4910                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4911                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4912                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4913                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4914                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4915                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4916                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4917                 if (val &
4918                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4919                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4920                 if (val &
4921                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4922                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4923                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4924                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4925                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4926                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4927                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4928                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4929         }
4930         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4931                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4932                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4933                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4934                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4935                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4936                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4937                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4938                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4939                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4940                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4941                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4942                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4943                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4944                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4945         }
4946 
4947         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4948                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4949                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4950                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4951                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4952         }
4953 }
4954 
4955 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4956 {
4957         struct attn_route attn, *group_mask;
4958         int port = BP_PORT(bp);
4959         int index;
4960         u32 reg_addr;
4961         u32 val;
4962         u32 aeu_mask;
4963         bool global = false;
4964 
4965         /* need to take HW lock because MCP or other port might also
4966            try to handle this event */
4967         bnx2x_acquire_alr(bp);
4968 
4969         if (bnx2x_chk_parity_attn(bp, &global, true)) {
4970 #ifndef BNX2X_STOP_ON_ERROR
4971                 bp->recovery_state = BNX2X_RECOVERY_INIT;
4972                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4973                 /* Disable HW interrupts */
4974                 bnx2x_int_disable(bp);
4975                 /* In case of parity errors don't handle attentions so that
4976                  * other function would "see" parity errors.
4977                  */
4978 #else
4979                 bnx2x_panic();
4980 #endif
4981                 bnx2x_release_alr(bp);
4982                 return;
4983         }
4984 
4985         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4986         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4987         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4988         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4989         if (!CHIP_IS_E1x(bp))
4990                 attn.sig[4] =
4991                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4992         else
4993                 attn.sig[4] = 0;
4994 
4995         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4996            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4997 
4998         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4999                 if (deasserted & (1 << index)) {
5000                         group_mask = &bp->attn_group[index];
5001 
5002                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5003                            index,
5004                            group_mask->sig[0], group_mask->sig[1],
5005                            group_mask->sig[2], group_mask->sig[3],
5006                            group_mask->sig[4]);
5007 
5008                         bnx2x_attn_int_deasserted4(bp,
5009                                         attn.sig[4] & group_mask->sig[4]);
5010                         bnx2x_attn_int_deasserted3(bp,
5011                                         attn.sig[3] & group_mask->sig[3]);
5012                         bnx2x_attn_int_deasserted1(bp,
5013                                         attn.sig[1] & group_mask->sig[1]);
5014                         bnx2x_attn_int_deasserted2(bp,
5015                                         attn.sig[2] & group_mask->sig[2]);
5016                         bnx2x_attn_int_deasserted0(bp,
5017                                         attn.sig[0] & group_mask->sig[0]);
5018                 }
5019         }
5020 
5021         bnx2x_release_alr(bp);
5022 
5023         if (bp->common.int_block == INT_BLOCK_HC)
5024                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5025                             COMMAND_REG_ATTN_BITS_CLR);
5026         else
5027                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5028 
5029         val = ~deasserted;
5030         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5031            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5032         REG_WR(bp, reg_addr, val);
5033 
5034         if (~bp->attn_state & deasserted)
5035                 BNX2X_ERR("IGU ERROR\n");
5036 
5037         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5038                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
5039 
5040         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5041         aeu_mask = REG_RD(bp, reg_addr);
5042 
5043         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
5044            aeu_mask, deasserted);
5045         aeu_mask |= (deasserted & 0x3ff);
5046         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5047 
5048         REG_WR(bp, reg_addr, aeu_mask);
5049         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5050 
5051         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5052         bp->attn_state &= ~deasserted;
5053         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5054 }
5055 
5056 static void bnx2x_attn_int(struct bnx2x *bp)
5057 {
5058         /* read local copy of bits */
5059         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5060                                                                 attn_bits);
5061         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5062                                                                 attn_bits_ack);
5063         u32 attn_state = bp->attn_state;
5064 
5065         /* look for changed bits */
5066         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
5067         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
5068 
5069         DP(NETIF_MSG_HW,
5070            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
5071            attn_bits, attn_ack, asserted, deasserted);
5072 
5073         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5074                 BNX2X_ERR("BAD attention state\n");
5075 
5076         /* handle bits that were raised */
5077         if (asserted)
5078                 bnx2x_attn_int_asserted(bp, asserted);
5079 
5080         if (deasserted)
5081                 bnx2x_attn_int_deasserted(bp, deasserted);
5082 }
5083 
5084 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5085                       u16 index, u8 op, u8 update)
5086 {
5087         u32 igu_addr = bp->igu_base_addr;
5088         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5089         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5090                              igu_addr);
5091 }
5092 
5093 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5094 {
5095         /* No memory barriers */
5096         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5097         mmiowb(); /* keep prod updates ordered */
5098 }
5099 
5100 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5101                                       union event_ring_elem *elem)
5102 {
5103         u8 err = elem->message.error;
5104 
5105         if (!bp->cnic_eth_dev.starting_cid  ||
5106             (cid < bp->cnic_eth_dev.starting_cid &&
5107             cid != bp->cnic_eth_dev.iscsi_l2_cid))
5108                 return 1;
5109 
5110         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5111 
5112         if (unlikely(err)) {
5113 
5114                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5115                           cid);
5116                 bnx2x_panic_dump(bp, false);
5117         }
5118         bnx2x_cnic_cfc_comp(bp, cid, err);
5119         return 0;
5120 }
5121 
5122 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5123 {
5124         struct bnx2x_mcast_ramrod_params rparam;
5125         int rc;
5126 
5127         memset(&rparam, 0, sizeof(rparam));
5128 
5129         rparam.mcast_obj = &bp->mcast_obj;
5130 
5131         netif_addr_lock_bh(bp->dev);
5132 
5133         /* Clear pending state for the last command */
5134         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5135 
5136         /* If there are pending mcast commands - send them */
5137         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5138                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5139                 if (rc < 0)
5140                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5141                                   rc);
5142         }
5143 
5144         netif_addr_unlock_bh(bp->dev);
5145 }
5146 
5147 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5148                                             union event_ring_elem *elem)
5149 {
5150         unsigned long ramrod_flags = 0;
5151         int rc = 0;
5152         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5153         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5154 
5155         /* Always push next commands out, don't wait here */
5156         __set_bit(RAMROD_CONT, &ramrod_flags);
5157 
5158         switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5159                             >> BNX2X_SWCID_SHIFT) {
5160         case BNX2X_FILTER_MAC_PENDING:
5161                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5162                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5163                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5164                 else
5165                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5166 
5167                 break;
5168         case BNX2X_FILTER_MCAST_PENDING:
5169                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5170                 /* This is only relevant for 57710 where multicast MACs are
5171                  * configured as unicast MACs using the same ramrod.
5172                  */
5173                 bnx2x_handle_mcast_eqe(bp);
5174                 return;
5175         default:
5176                 BNX2X_ERR("Unsupported classification command: %d\n",
5177                           elem->message.data.eth_event.echo);
5178                 return;
5179         }
5180 
5181         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5182 
5183         if (rc < 0)
5184                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5185         else if (rc > 0)
5186                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5187 }
5188 
5189 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5190 
5191 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5192 {
5193         netif_addr_lock_bh(bp->dev);
5194 
5195         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5196 
5197         /* Send rx_mode command again if was requested */
5198         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5199                 bnx2x_set_storm_rx_mode(bp);
5200         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5201                                     &bp->sp_state))
5202                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5203         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5204                                     &bp->sp_state))
5205                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5206 
5207         netif_addr_unlock_bh(bp->dev);
5208 }
5209 
5210 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5211                                               union event_ring_elem *elem)
5212 {
5213         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5214                 DP(BNX2X_MSG_SP,
5215                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5216                    elem->message.data.vif_list_event.func_bit_map);
5217                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5218                         elem->message.data.vif_list_event.func_bit_map);
5219         } else if (elem->message.data.vif_list_event.echo ==
5220                    VIF_LIST_RULE_SET) {
5221                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5222                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5223         }
5224 }
5225 
5226 /* called with rtnl_lock */
5227 static void bnx2x_after_function_update(struct bnx2x *bp)
5228 {
5229         int q, rc;
5230         struct bnx2x_fastpath *fp;
5231         struct bnx2x_queue_state_params queue_params = {NULL};
5232         struct bnx2x_queue_update_params *q_update_params =
5233                 &queue_params.params.update;
5234 
5235         /* Send Q update command with afex vlan removal values for all Qs */
5236         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5237 
5238         /* set silent vlan removal values according to vlan mode */
5239         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5240                   &q_update_params->update_flags);
5241         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5242                   &q_update_params->update_flags);
5243         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5244 
5245         /* in access mode mark mask and value are 0 to strip all vlans */
5246         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5247                 q_update_params->silent_removal_value = 0;
5248                 q_update_params->silent_removal_mask = 0;
5249         } else {
5250                 q_update_params->silent_removal_value =
5251                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5252                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5253         }
5254 
5255         for_each_eth_queue(bp, q) {
5256                 /* Set the appropriate Queue object */
5257                 fp = &bp->fp[q];
5258                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5259 
5260                 /* send the ramrod */
5261                 rc = bnx2x_queue_state_change(bp, &queue_params);
5262                 if (rc < 0)
5263                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5264                                   q);
5265         }
5266 
5267         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5268                 fp = &bp->fp[FCOE_IDX(bp)];
5269                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5270 
5271                 /* clear pending completion bit */
5272                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5273 
5274                 /* mark latest Q bit */
5275                 smp_mb__before_atomic();
5276                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5277                 smp_mb__after_atomic();
5278 
5279                 /* send Q update ramrod for FCoE Q */
5280                 rc = bnx2x_queue_state_change(bp, &queue_params);
5281                 if (rc < 0)
5282                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5283                                   q);
5284         } else {
5285                 /* If no FCoE ring - ACK MCP now */
5286                 bnx2x_link_report(bp);
5287                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5288         }
5289 }
5290 
5291 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5292         struct bnx2x *bp, u32 cid)
5293 {
5294         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5295 
5296         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5297                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5298         else
5299                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5300 }
5301 
5302 static void bnx2x_eq_int(struct bnx2x *bp)
5303 {
5304         u16 hw_cons, sw_cons, sw_prod;
5305         union event_ring_elem *elem;
5306         u8 echo;
5307         u32 cid;
5308         u8 opcode;
5309         int rc, spqe_cnt = 0;
5310         struct bnx2x_queue_sp_obj *q_obj;
5311         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5312         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5313 
5314         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5315 
5316         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5317          * when we get the next-page we need to adjust so the loop
5318          * condition below will be met. The next element is the size of a
5319          * regular element and hence incrementing by 1
5320          */
5321         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5322                 hw_cons++;
5323 
5324         /* This function may never run in parallel with itself for a
5325          * specific bp, thus there is no need in "paired" read memory
5326          * barrier here.
5327          */
5328         sw_cons = bp->eq_cons;
5329         sw_prod = bp->eq_prod;
5330 
5331         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5332                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5333 
5334         for (; sw_cons != hw_cons;
5335               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5336 
5337                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5338 
5339                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5340                 if (!rc) {
5341                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5342                            rc);
5343                         goto next_spqe;
5344                 }
5345 
5346                 /* elem CID originates from FW; actually LE */
5347                 cid = SW_CID((__force __le32)
5348                              elem->message.data.cfc_del_event.cid);
5349                 opcode = elem->message.opcode;
5350 
5351                 /* handle eq element */
5352                 switch (opcode) {
5353                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5354                         bnx2x_vf_mbx_schedule(bp,
5355                                               &elem->message.data.vf_pf_event);
5356                         continue;
5357 
5358                 case EVENT_RING_OPCODE_STAT_QUERY:
5359                         DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5360                                "got statistics comp event %d\n",
5361                                bp->stats_comp++);
5362                         /* nothing to do with stats comp */
5363                         goto next_spqe;
5364 
5365                 case EVENT_RING_OPCODE_CFC_DEL:
5366                         /* handle according to cid range */
5367                         /*
5368                          * we may want to verify here that the bp state is
5369                          * HALTING
5370                          */
5371                         DP(BNX2X_MSG_SP,
5372                            "got delete ramrod for MULTI[%d]\n", cid);
5373 
5374                         if (CNIC_LOADED(bp) &&
5375                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5376                                 goto next_spqe;
5377 
5378                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5379 
5380                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5381                                 break;
5382 
5383                         goto next_spqe;
5384 
5385                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5386                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5387                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5388                         if (f_obj->complete_cmd(bp, f_obj,
5389                                                 BNX2X_F_CMD_TX_STOP))
5390                                 break;
5391                         goto next_spqe;
5392 
5393                 case EVENT_RING_OPCODE_START_TRAFFIC:
5394                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5395                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5396                         if (f_obj->complete_cmd(bp, f_obj,
5397                                                 BNX2X_F_CMD_TX_START))
5398                                 break;
5399                         goto next_spqe;
5400 
5401                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5402                         echo = elem->message.data.function_update_event.echo;
5403                         if (echo == SWITCH_UPDATE) {
5404                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5405                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5406                                 if (f_obj->complete_cmd(
5407                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5408                                         break;
5409 
5410                         } else {
5411                                 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5412 
5413                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5414                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5415                                 f_obj->complete_cmd(bp, f_obj,
5416                                                     BNX2X_F_CMD_AFEX_UPDATE);
5417 
5418                                 /* We will perform the Queues update from
5419                                  * sp_rtnl task as all Queue SP operations
5420                                  * should run under rtnl_lock.
5421                                  */
5422                                 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5423                         }
5424 
5425                         goto next_spqe;
5426 
5427                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5428                         f_obj->complete_cmd(bp, f_obj,
5429                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5430                         bnx2x_after_afex_vif_lists(bp, elem);
5431                         goto next_spqe;
5432                 case EVENT_RING_OPCODE_FUNCTION_START:
5433                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5434                            "got FUNC_START ramrod\n");
5435                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5436                                 break;
5437 
5438                         goto next_spqe;
5439 
5440                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5441                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5442                            "got FUNC_STOP ramrod\n");
5443                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5444                                 break;
5445 
5446                         goto next_spqe;
5447                 }
5448 
5449                 switch (opcode | bp->state) {
5450                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5451                       BNX2X_STATE_OPEN):
5452                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5453                       BNX2X_STATE_OPENING_WAIT4_PORT):
5454                         cid = elem->message.data.eth_event.echo &
5455                                 BNX2X_SWCID_MASK;
5456                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5457                            cid);
5458                         rss_raw->clear_pending(rss_raw);
5459                         break;
5460 
5461                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5462                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5463                 case (EVENT_RING_OPCODE_SET_MAC |
5464                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5465                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5466                       BNX2X_STATE_OPEN):
5467                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5468                       BNX2X_STATE_DIAG):
5469                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5470                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5471                         DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5472                         bnx2x_handle_classification_eqe(bp, elem);
5473                         break;
5474 
5475                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5476                       BNX2X_STATE_OPEN):
5477                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5478                       BNX2X_STATE_DIAG):
5479                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5480                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5481                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5482                         bnx2x_handle_mcast_eqe(bp);
5483                         break;
5484 
5485                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5486                       BNX2X_STATE_OPEN):
5487                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5488                       BNX2X_STATE_DIAG):
5489                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5490                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5491                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5492                         bnx2x_handle_rx_mode_eqe(bp);
5493                         break;
5494                 default:
5495                         /* unknown event log error and continue */
5496                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5497                                   elem->message.opcode, bp->state);
5498                 }
5499 next_spqe:
5500                 spqe_cnt++;
5501         } /* for */
5502 
5503         smp_mb__before_atomic();
5504         atomic_add(spqe_cnt, &bp->eq_spq_left);
5505 
5506         bp->eq_cons = sw_cons;
5507         bp->eq_prod = sw_prod;
5508         /* Make sure that above mem writes were issued towards the memory */
5509         smp_wmb();
5510 
5511         /* update producer */
5512         bnx2x_update_eq_prod(bp, bp->eq_prod);
5513 }
5514 
5515 static void bnx2x_sp_task(struct work_struct *work)
5516 {
5517         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5518 
5519         DP(BNX2X_MSG_SP, "sp task invoked\n");
5520 
5521         /* make sure the atomic interrupt_occurred has been written */
5522         smp_rmb();
5523         if (atomic_read(&bp->interrupt_occurred)) {
5524 
5525                 /* what work needs to be performed? */
5526                 u16 status = bnx2x_update_dsb_idx(bp);
5527 
5528                 DP(BNX2X_MSG_SP, "status %x\n", status);
5529                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5530                 atomic_set(&bp->interrupt_occurred, 0);
5531 
5532                 /* HW attentions */
5533                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5534                         bnx2x_attn_int(bp);
5535                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5536                 }
5537 
5538                 /* SP events: STAT_QUERY and others */
5539                 if (status & BNX2X_DEF_SB_IDX) {
5540                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5541 
5542                 if (FCOE_INIT(bp) &&
5543                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5544                                 /* Prevent local bottom-halves from running as
5545                                  * we are going to change the local NAPI list.
5546                                  */
5547                                 local_bh_disable();
5548                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5549                                 local_bh_enable();
5550                         }
5551 
5552                         /* Handle EQ completions */
5553                         bnx2x_eq_int(bp);
5554                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5555                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5556 
5557                         status &= ~BNX2X_DEF_SB_IDX;
5558                 }
5559 
5560                 /* if status is non zero then perhaps something went wrong */
5561                 if (unlikely(status))
5562                         DP(BNX2X_MSG_SP,
5563                            "got an unknown interrupt! (status 0x%x)\n", status);
5564 
5565                 /* ack status block only if something was actually handled */
5566                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5567                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5568         }
5569 
5570         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5571         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5572                                &bp->sp_state)) {
5573                 bnx2x_link_report(bp);
5574                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5575         }
5576 }
5577 
5578 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5579 {
5580         struct net_device *dev = dev_instance;
5581         struct bnx2x *bp = netdev_priv(dev);
5582 
5583         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5584                      IGU_INT_DISABLE, 0);
5585 
5586 #ifdef BNX2X_STOP_ON_ERROR
5587         if (unlikely(bp->panic))
5588                 return IRQ_HANDLED;
5589 #endif
5590 
5591         if (CNIC_LOADED(bp)) {
5592                 struct cnic_ops *c_ops;
5593 
5594                 rcu_read_lock();
5595                 c_ops = rcu_dereference(bp->cnic_ops);
5596                 if (c_ops)
5597                         c_ops->cnic_handler(bp->cnic_data, NULL);
5598                 rcu_read_unlock();
5599         }
5600 
5601         /* schedule sp task to perform default status block work, ack
5602          * attentions and enable interrupts.
5603          */
5604         bnx2x_schedule_sp_task(bp);
5605 
5606         return IRQ_HANDLED;
5607 }
5608 
5609 /* end of slow path */
5610 
5611 void bnx2x_drv_pulse(struct bnx2x *bp)
5612 {
5613         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5614                  bp->fw_drv_pulse_wr_seq);
5615 }
5616 
5617 static void bnx2x_timer(unsigned long data)
5618 {
5619         struct bnx2x *bp = (struct bnx2x *) data;
5620 
5621         if (!netif_running(bp->dev))
5622                 return;
5623 
5624         if (IS_PF(bp) &&
5625             !BP_NOMCP(bp)) {
5626                 int mb_idx = BP_FW_MB_IDX(bp);
5627                 u16 drv_pulse;
5628                 u16 mcp_pulse;
5629 
5630                 ++bp->fw_drv_pulse_wr_seq;
5631                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5632                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5633                 bnx2x_drv_pulse(bp);
5634 
5635                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5636                              MCP_PULSE_SEQ_MASK);
5637                 /* The delta between driver pulse and mcp response
5638                  * should not get too big. If the MFW is more than 5 pulses
5639                  * behind, we should worry about it enough to generate an error
5640                  * log.
5641                  */
5642                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5643                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5644                                   drv_pulse, mcp_pulse);
5645         }
5646 
5647         if (bp->state == BNX2X_STATE_OPEN)
5648                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5649 
5650         /* sample pf vf bulletin board for new posts from pf */
5651         if (IS_VF(bp))
5652                 bnx2x_timer_sriov(bp);
5653 
5654         mod_timer(&bp->timer, jiffies + bp->current_interval);
5655 }
5656 
5657 /* end of Statistics */
5658 
5659 /* nic init */
5660 
5661 /*
5662  * nic init service functions
5663  */
5664 
5665 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5666 {
5667         u32 i;
5668         if (!(len%4) && !(addr%4))
5669                 for (i = 0; i < len; i += 4)
5670                         REG_WR(bp, addr + i, fill);
5671         else
5672                 for (i = 0; i < len; i++)
5673                         REG_WR8(bp, addr + i, fill);
5674 }
5675 
5676 /* helper: writes FP SP data to FW - data_size in dwords */
5677 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5678                                 int fw_sb_id,
5679                                 u32 *sb_data_p,
5680                                 u32 data_size)
5681 {
5682         int index;
5683         for (index = 0; index < data_size; index++)
5684                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5685                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5686                         sizeof(u32)*index,
5687                         *(sb_data_p + index));
5688 }
5689 
5690 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5691 {
5692         u32 *sb_data_p;
5693         u32 data_size = 0;
5694         struct hc_status_block_data_e2 sb_data_e2;
5695         struct hc_status_block_data_e1x sb_data_e1x;
5696 
5697         /* disable the function first */
5698         if (!CHIP_IS_E1x(bp)) {
5699                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5700                 sb_data_e2.common.state = SB_DISABLED;
5701                 sb_data_e2.common.p_func.vf_valid = false;
5702                 sb_data_p = (u32 *)&sb_data_e2;
5703                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5704         } else {
5705                 memset(&sb_data_e1x, 0,
5706                        sizeof(struct hc_status_block_data_e1x));
5707                 sb_data_e1x.common.state = SB_DISABLED;
5708                 sb_data_e1x.common.p_func.vf_valid = false;
5709                 sb_data_p = (u32 *)&sb_data_e1x;
5710                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5711         }
5712         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5713 
5714         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5715                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5716                         CSTORM_STATUS_BLOCK_SIZE);
5717         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5718                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5719                         CSTORM_SYNC_BLOCK_SIZE);
5720 }
5721 
5722 /* helper:  writes SP SB data to FW */
5723 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5724                 struct hc_sp_status_block_data *sp_sb_data)
5725 {
5726         int func = BP_FUNC(bp);
5727         int i;
5728         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5729                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5730                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5731                         i*sizeof(u32),
5732                         *((u32 *)sp_sb_data + i));
5733 }
5734 
5735 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5736 {
5737         int func = BP_FUNC(bp);
5738         struct hc_sp_status_block_data sp_sb_data;
5739         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5740 
5741         sp_sb_data.state = SB_DISABLED;
5742         sp_sb_data.p_func.vf_valid = false;
5743 
5744         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5745 
5746         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5747                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5748                         CSTORM_SP_STATUS_BLOCK_SIZE);
5749         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5750                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5751                         CSTORM_SP_SYNC_BLOCK_SIZE);
5752 }
5753 
5754 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5755                                            int igu_sb_id, int igu_seg_id)
5756 {
5757         hc_sm->igu_sb_id = igu_sb_id;
5758         hc_sm->igu_seg_id = igu_seg_id;
5759         hc_sm->timer_value = 0xFF;
5760         hc_sm->time_to_expire = 0xFFFFFFFF;
5761 }
5762 
5763 /* allocates state machine ids. */
5764 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5765 {
5766         /* zero out state machine indices */
5767         /* rx indices */
5768         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5769 
5770         /* tx indices */
5771         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5772         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5773         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5774         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5775 
5776         /* map indices */
5777         /* rx indices */
5778         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5779                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5780 
5781         /* tx indices */
5782         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5783                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5784         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5785                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5786         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5787                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5788         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5789                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5790 }
5791 
5792 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5793                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5794 {
5795         int igu_seg_id;
5796 
5797         struct hc_status_block_data_e2 sb_data_e2;
5798         struct hc_status_block_data_e1x sb_data_e1x;
5799         struct hc_status_block_sm  *hc_sm_p;
5800         int data_size;
5801         u32 *sb_data_p;
5802 
5803         if (CHIP_INT_MODE_IS_BC(bp))
5804                 igu_seg_id = HC_SEG_ACCESS_NORM;
5805         else
5806                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5807 
5808         bnx2x_zero_fp_sb(bp, fw_sb_id);
5809 
5810         if (!CHIP_IS_E1x(bp)) {
5811                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5812                 sb_data_e2.common.state = SB_ENABLED;
5813                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5814                 sb_data_e2.common.p_func.vf_id = vfid;
5815                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5816                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5817                 sb_data_e2.common.same_igu_sb_1b = true;
5818                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5819                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5820                 hc_sm_p = sb_data_e2.common.state_machine;
5821                 sb_data_p = (u32 *)&sb_data_e2;
5822                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5823                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5824         } else {
5825                 memset(&sb_data_e1x, 0,
5826                        sizeof(struct hc_status_block_data_e1x));
5827                 sb_data_e1x.common.state = SB_ENABLED;
5828                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5829                 sb_data_e1x.common.p_func.vf_id = 0xff;
5830                 sb_data_e1x.common.p_func.vf_valid = false;
5831                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5832                 sb_data_e1x.common.same_igu_sb_1b = true;
5833                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5834                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5835                 hc_sm_p = sb_data_e1x.common.state_machine;
5836                 sb_data_p = (u32 *)&sb_data_e1x;
5837                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5838                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5839         }
5840 
5841         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5842                                        igu_sb_id, igu_seg_id);
5843         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5844                                        igu_sb_id, igu_seg_id);
5845 
5846         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5847 
5848         /* write indices to HW - PCI guarantees endianity of regpairs */
5849         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5850 }
5851 
5852 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5853                                      u16 tx_usec, u16 rx_usec)
5854 {
5855         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5856                                     false, rx_usec);
5857         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5858                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5859                                        tx_usec);
5860         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5861                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5862                                        tx_usec);
5863         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5864                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5865                                        tx_usec);
5866 }
5867 
5868 static void bnx2x_init_def_sb(struct bnx2x *bp)
5869 {
5870         struct host_sp_status_block *def_sb = bp->def_status_blk;
5871         dma_addr_t mapping = bp->def_status_blk_mapping;
5872         int igu_sp_sb_index;
5873         int igu_seg_id;
5874         int port = BP_PORT(bp);
5875         int func = BP_FUNC(bp);
5876         int reg_offset, reg_offset_en5;
5877         u64 section;
5878         int index;
5879         struct hc_sp_status_block_data sp_sb_data;
5880         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5881 
5882         if (CHIP_INT_MODE_IS_BC(bp)) {
5883                 igu_sp_sb_index = DEF_SB_IGU_ID;
5884                 igu_seg_id = HC_SEG_ACCESS_DEF;
5885         } else {
5886                 igu_sp_sb_index = bp->igu_dsb_id;
5887                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5888         }
5889 
5890         /* ATTN */
5891         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5892                                             atten_status_block);
5893         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5894 
5895         bp->attn_state = 0;
5896 
5897         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5898                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5899         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5900                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5901         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5902                 int sindex;
5903                 /* take care of sig[0]..sig[4] */
5904                 for (sindex = 0; sindex < 4; sindex++)
5905                         bp->attn_group[index].sig[sindex] =
5906                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5907 
5908                 if (!CHIP_IS_E1x(bp))
5909                         /*
5910                          * enable5 is separate from the rest of the registers,
5911                          * and therefore the address skip is 4
5912                          * and not 16 between the different groups
5913                          */
5914                         bp->attn_group[index].sig[4] = REG_RD(bp,
5915                                         reg_offset_en5 + 0x4*index);
5916                 else
5917                         bp->attn_group[index].sig[4] = 0;
5918         }
5919 
5920         if (bp->common.int_block == INT_BLOCK_HC) {
5921                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5922                                      HC_REG_ATTN_MSG0_ADDR_L);
5923 
5924                 REG_WR(bp, reg_offset, U64_LO(section));
5925                 REG_WR(bp, reg_offset + 4, U64_HI(section));
5926         } else if (!CHIP_IS_E1x(bp)) {
5927                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5928                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5929         }
5930 
5931         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5932                                             sp_sb);
5933 
5934         bnx2x_zero_sp_sb(bp);
5935 
5936         /* PCI guarantees endianity of regpairs */
5937         sp_sb_data.state                = SB_ENABLED;
5938         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
5939         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
5940         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
5941         sp_sb_data.igu_seg_id           = igu_seg_id;
5942         sp_sb_data.p_func.pf_id         = func;
5943         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
5944         sp_sb_data.p_func.vf_id         = 0xff;
5945 
5946         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5947 
5948         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5949 }
5950 
5951 void bnx2x_update_coalesce(struct bnx2x *bp)
5952 {
5953         int i;
5954 
5955         for_each_eth_queue(bp, i)
5956                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5957                                          bp->tx_ticks, bp->rx_ticks);
5958 }
5959 
5960 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5961 {
5962         spin_lock_init(&bp->spq_lock);
5963         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5964 
5965         bp->spq_prod_idx = 0;
5966         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5967         bp->spq_prod_bd = bp->spq;
5968         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5969 }
5970 
5971 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5972 {
5973         int i;
5974         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5975                 union event_ring_elem *elem =
5976                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5977 
5978                 elem->next_page.addr.hi =
5979                         cpu_to_le32(U64_HI(bp->eq_mapping +
5980                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5981                 elem->next_page.addr.lo =
5982                         cpu_to_le32(U64_LO(bp->eq_mapping +
5983                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5984         }
5985         bp->eq_cons = 0;
5986         bp->eq_prod = NUM_EQ_DESC;
5987         bp->eq_cons_sb = BNX2X_EQ_INDEX;
5988         /* we want a warning message before it gets wrought... */
5989         atomic_set(&bp->eq_spq_left,
5990                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5991 }
5992 
5993 /* called with netif_addr_lock_bh() */
5994 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5995                                unsigned long rx_mode_flags,
5996                                unsigned long rx_accept_flags,
5997                                unsigned long tx_accept_flags,
5998                                unsigned long ramrod_flags)
5999 {
6000         struct bnx2x_rx_mode_ramrod_params ramrod_param;
6001         int rc;
6002 
6003         memset(&ramrod_param, 0, sizeof(ramrod_param));
6004 
6005         /* Prepare ramrod parameters */
6006         ramrod_param.cid = 0;
6007         ramrod_param.cl_id = cl_id;
6008         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6009         ramrod_param.func_id = BP_FUNC(bp);
6010 
6011         ramrod_param.pstate = &bp->sp_state;
6012         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6013 
6014         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6015         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6016 
6017         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6018 
6019         ramrod_param.ramrod_flags = ramrod_flags;
6020         ramrod_param.rx_mode_flags = rx_mode_flags;
6021 
6022         ramrod_param.rx_accept_flags = rx_accept_flags;
6023         ramrod_param.tx_accept_flags = tx_accept_flags;
6024 
6025         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6026         if (rc < 0) {
6027                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6028                 return rc;
6029         }
6030 
6031         return 0;
6032 }
6033 
6034 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6035                                    unsigned long *rx_accept_flags,
6036                                    unsigned long *tx_accept_flags)
6037 {
6038         /* Clear the flags first */
6039         *rx_accept_flags = 0;
6040         *tx_accept_flags = 0;
6041 
6042         switch (rx_mode) {
6043         case BNX2X_RX_MODE_NONE:
6044                 /*
6045                  * 'drop all' supersedes any accept flags that may have been
6046                  * passed to the function.
6047                  */
6048                 break;
6049         case BNX2X_RX_MODE_NORMAL:
6050                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6051                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6052                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6053 
6054                 /* internal switching mode */
6055                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6056                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6057                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6058 
6059                 break;
6060         case BNX2X_RX_MODE_ALLMULTI:
6061                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6062                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6063                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6064 
6065                 /* internal switching mode */
6066                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6067                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6068                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6069 
6070                 break;
6071         case BNX2X_RX_MODE_PROMISC:
6072                 /* According to definition of SI mode, iface in promisc mode
6073                  * should receive matched and unmatched (in resolution of port)
6074                  * unicast packets.
6075                  */
6076                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6077                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6078                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6079                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6080 
6081                 /* internal switching mode */
6082                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6083                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6084 
6085                 if (IS_MF_SI(bp))
6086                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6087                 else
6088                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6089 
6090                 break;
6091         default:
6092                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6093                 return -EINVAL;
6094         }
6095 
6096         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
6097         if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
6098                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6099                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6100         }
6101 
6102         return 0;
6103 }
6104 
6105 /* called with netif_addr_lock_bh() */
6106 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6107 {
6108         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6109         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6110         int rc;
6111 
6112         if (!NO_FCOE(bp))
6113                 /* Configure rx_mode of FCoE Queue */
6114                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6115 
6116         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6117                                      &tx_accept_flags);
6118         if (rc)
6119                 return rc;
6120 
6121         __set_bit(RAMROD_RX, &ramrod_flags);
6122         __set_bit(RAMROD_TX, &ramrod_flags);
6123 
6124         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6125                                    rx_accept_flags, tx_accept_flags,
6126                                    ramrod_flags);
6127 }
6128 
6129 static void bnx2x_init_internal_common(struct bnx2x *bp)
6130 {
6131         int i;
6132 
6133         /* Zero this manually as its initialization is
6134            currently missing in the initTool */
6135         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6136                 REG_WR(bp, BAR_USTRORM_INTMEM +
6137                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
6138         if (!CHIP_IS_E1x(bp)) {
6139                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6140                         CHIP_INT_MODE_IS_BC(bp) ?
6141                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6142         }
6143 }
6144 
6145 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6146 {
6147         switch (load_code) {
6148         case FW_MSG_CODE_DRV_LOAD_COMMON:
6149         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6150                 bnx2x_init_internal_common(bp);
6151                 /* no break */
6152 
6153         case FW_MSG_CODE_DRV_LOAD_PORT:
6154                 /* nothing to do */
6155                 /* no break */
6156 
6157         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6158                 /* internal memory per function is
6159                    initialized inside bnx2x_pf_init */
6160                 break;
6161 
6162         default:
6163                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6164                 break;
6165         }
6166 }
6167 
6168 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6169 {
6170         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6171 }
6172 
6173 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6174 {
6175         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6176 }
6177 
6178 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6179 {
6180         if (CHIP_IS_E1x(fp->bp))
6181                 return BP_L_ID(fp->bp) + fp->index;
6182         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6183                 return bnx2x_fp_igu_sb_id(fp);
6184 }
6185 
6186 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6187 {
6188         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6189         u8 cos;
6190         unsigned long q_type = 0;
6191         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6192         fp->rx_queue = fp_idx;
6193         fp->cid = fp_idx;
6194         fp->cl_id = bnx2x_fp_cl_id(fp);
6195         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6196         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6197         /* qZone id equals to FW (per path) client id */
6198         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
6199 
6200         /* init shortcut */
6201         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6202 
6203         /* Setup SB indices */
6204         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6205 
6206         /* Configure Queue State object */
6207         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6208         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6209 
6210         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6211 
6212         /* init tx data */
6213         for_each_cos_in_tx_queue(fp, cos) {
6214                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6215                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6216                                   FP_COS_TO_TXQ(fp, cos, bp),
6217                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
6218                 cids[cos] = fp->txdata_ptr[cos]->cid;
6219         }
6220 
6221         /* nothing more for vf to do here */
6222         if (IS_VF(bp))
6223                 return;
6224 
6225         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6226                       fp->fw_sb_id, fp->igu_sb_id);
6227         bnx2x_update_fpsb_idx(fp);
6228         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6229                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6230                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6231 
6232         /**
6233          * Configure classification DBs: Always enable Tx switching
6234          */
6235         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6236 
6237         DP(NETIF_MSG_IFUP,
6238            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
6239            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6240            fp->igu_sb_id);
6241 }
6242 
6243 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6244 {
6245         int i;
6246 
6247         for (i = 1; i <= NUM_TX_RINGS; i++) {
6248                 struct eth_tx_next_bd *tx_next_bd =
6249                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6250 
6251                 tx_next_bd->addr_hi =
6252                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6253                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6254                 tx_next_bd->addr_lo =
6255                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6256                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6257         }
6258 
6259         *txdata->tx_cons_sb = cpu_to_le16(0);
6260 
6261         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6262         txdata->tx_db.data.zero_fill1 = 0;
6263         txdata->tx_db.data.prod = 0;
6264 
6265         txdata->tx_pkt_prod = 0;
6266         txdata->tx_pkt_cons = 0;
6267         txdata->tx_bd_prod = 0;
6268         txdata->tx_bd_cons = 0;
6269         txdata->tx_pkt = 0;
6270 }
6271 
6272 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6273 {
6274         int i;
6275 
6276         for_each_tx_queue_cnic(bp, i)
6277                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6278 }
6279 
6280 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6281 {
6282         int i;
6283         u8 cos;
6284 
6285         for_each_eth_queue(bp, i)
6286                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6287                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6288 }
6289 
6290 static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6291 {
6292         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6293         unsigned long q_type = 0;
6294 
6295         bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6296         bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6297                                                      BNX2X_FCOE_ETH_CL_ID_IDX);
6298         bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6299         bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6300         bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6301         bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6302         bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6303                           fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6304                           fp);
6305 
6306         DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6307 
6308         /* qZone id equals to FW (per path) client id */
6309         bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6310         /* init shortcut */
6311         bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6312                 bnx2x_rx_ustorm_prods_offset(fp);
6313 
6314         /* Configure Queue State object */
6315         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6316         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6317 
6318         /* No multi-CoS for FCoE L2 client */
6319         BUG_ON(fp->max_cos != 1);
6320 
6321         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6322                              &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6323                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6324 
6325         DP(NETIF_MSG_IFUP,
6326            "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6327            fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6328            fp->igu_sb_id);
6329 }