Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

  1 /* bnx2x_main.c: Broadcom Everest network driver.
  2  *
  3  * Copyright (c) 2007-2013 Broadcom Corporation
  4  *
  5  * This program is free software; you can redistribute it and/or modify
  6  * it under the terms of the GNU General Public License as published by
  7  * the Free Software Foundation.
  8  *
  9  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
 10  * Written by: Eliezer Tamir
 11  * Based on code from Michael Chan's bnx2 driver
 12  * UDP CSUM errata workaround by Arik Gendelman
 13  * Slowpath and fastpath rework by Vladislav Zolotarov
 14  * Statistics and Link management by Yitchak Gertner
 15  *
 16  */
 17 
 18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 19 
 20 #include <linux/module.h>
 21 #include <linux/moduleparam.h>
 22 #include <linux/kernel.h>
 23 #include <linux/device.h>  /* for dev_info() */
 24 #include <linux/timer.h>
 25 #include <linux/errno.h>
 26 #include <linux/ioport.h>
 27 #include <linux/slab.h>
 28 #include <linux/interrupt.h>
 29 #include <linux/pci.h>
 30 #include <linux/aer.h>
 31 #include <linux/init.h>
 32 #include <linux/netdevice.h>
 33 #include <linux/etherdevice.h>
 34 #include <linux/skbuff.h>
 35 #include <linux/dma-mapping.h>
 36 #include <linux/bitops.h>
 37 #include <linux/irq.h>
 38 #include <linux/delay.h>
 39 #include <asm/byteorder.h>
 40 #include <linux/time.h>
 41 #include <linux/ethtool.h>
 42 #include <linux/mii.h>
 43 #include <linux/if_vlan.h>
 44 #include <net/ip.h>
 45 #include <net/ipv6.h>
 46 #include <net/tcp.h>
 47 #include <net/checksum.h>
 48 #include <net/ip6_checksum.h>
 49 #include <linux/workqueue.h>
 50 #include <linux/crc32.h>
 51 #include <linux/crc32c.h>
 52 #include <linux/prefetch.h>
 53 #include <linux/zlib.h>
 54 #include <linux/io.h>
 55 #include <linux/semaphore.h>
 56 #include <linux/stringify.h>
 57 #include <linux/vmalloc.h>
 58 
 59 #include "bnx2x.h"
 60 #include "bnx2x_init.h"
 61 #include "bnx2x_init_ops.h"
 62 #include "bnx2x_cmn.h"
 63 #include "bnx2x_vfpf.h"
 64 #include "bnx2x_dcb.h"
 65 #include "bnx2x_sp.h"
 66 
 67 #include <linux/firmware.h>
 68 #include "bnx2x_fw_file_hdr.h"
 69 /* FW files */
 70 #define FW_FILE_VERSION                                 \
 71         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
 72         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
 73         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
 74         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
 75 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
 76 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
 77 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
 78 
 79 /* Time in jiffies before concluding the transmitter is hung */
 80 #define TX_TIMEOUT              (5*HZ)
 81 
 82 static char version[] =
 83         "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
 84         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 85 
 86 MODULE_AUTHOR("Eliezer Tamir");
 87 MODULE_DESCRIPTION("Broadcom NetXtreme II "
 88                    "BCM57710/57711/57711E/"
 89                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
 90                    "57840/57840_MF Driver");
 91 MODULE_LICENSE("GPL");
 92 MODULE_VERSION(DRV_MODULE_VERSION);
 93 MODULE_FIRMWARE(FW_FILE_NAME_E1);
 94 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
 95 MODULE_FIRMWARE(FW_FILE_NAME_E2);
 96 
 97 int bnx2x_num_queues;
 98 module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
 99 MODULE_PARM_DESC(num_queues,
100                  " Set number of queues (default is as a number of CPUs)");
101 
102 static int disable_tpa;
103 module_param(disable_tpa, int, S_IRUGO);
104 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
105 
106 static int int_mode;
107 module_param(int_mode, int, S_IRUGO);
108 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
109                                 "(1 INT#x; 2 MSI)");
110 
111 static int dropless_fc;
112 module_param(dropless_fc, int, S_IRUGO);
113 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
114 
115 static int mrrs = -1;
116 module_param(mrrs, int, S_IRUGO);
117 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
118 
119 static int debug;
120 module_param(debug, int, S_IRUGO);
121 MODULE_PARM_DESC(debug, " Default debug msglevel");
122 
123 static struct workqueue_struct *bnx2x_wq;
124 struct workqueue_struct *bnx2x_iov_wq;
125 
126 struct bnx2x_mac_vals {
127         u32 xmac_addr;
128         u32 xmac_val;
129         u32 emac_addr;
130         u32 emac_val;
131         u32 umac_addr;
132         u32 umac_val;
133         u32 bmac_addr;
134         u32 bmac_val[2];
135 };
136 
137 enum bnx2x_board_type {
138         BCM57710 = 0,
139         BCM57711,
140         BCM57711E,
141         BCM57712,
142         BCM57712_MF,
143         BCM57712_VF,
144         BCM57800,
145         BCM57800_MF,
146         BCM57800_VF,
147         BCM57810,
148         BCM57810_MF,
149         BCM57810_VF,
150         BCM57840_4_10,
151         BCM57840_2_20,
152         BCM57840_MF,
153         BCM57840_VF,
154         BCM57811,
155         BCM57811_MF,
156         BCM57840_O,
157         BCM57840_MFO,
158         BCM57811_VF
159 };
160 
161 /* indexed by board_type, above */
162 static struct {
163         char *name;
164 } board_info[] = {
165         [BCM57710]      = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
166         [BCM57711]      = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
167         [BCM57711E]     = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
168         [BCM57712]      = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
169         [BCM57712_MF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
170         [BCM57712_VF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
171         [BCM57800]      = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
172         [BCM57800_MF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
173         [BCM57800_VF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
174         [BCM57810]      = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
175         [BCM57810_MF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
176         [BCM57810_VF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
177         [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
178         [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
179         [BCM57840_MF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
180         [BCM57840_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
181         [BCM57811]      = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
182         [BCM57811_MF]   = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
183         [BCM57840_O]    = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
184         [BCM57840_MFO]  = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
185         [BCM57811_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
186 };
187 
188 #ifndef PCI_DEVICE_ID_NX2_57710
189 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
190 #endif
191 #ifndef PCI_DEVICE_ID_NX2_57711
192 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
193 #endif
194 #ifndef PCI_DEVICE_ID_NX2_57711E
195 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
196 #endif
197 #ifndef PCI_DEVICE_ID_NX2_57712
198 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
199 #endif
200 #ifndef PCI_DEVICE_ID_NX2_57712_MF
201 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
202 #endif
203 #ifndef PCI_DEVICE_ID_NX2_57712_VF
204 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
205 #endif
206 #ifndef PCI_DEVICE_ID_NX2_57800
207 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
208 #endif
209 #ifndef PCI_DEVICE_ID_NX2_57800_MF
210 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
211 #endif
212 #ifndef PCI_DEVICE_ID_NX2_57800_VF
213 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
214 #endif
215 #ifndef PCI_DEVICE_ID_NX2_57810
216 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
217 #endif
218 #ifndef PCI_DEVICE_ID_NX2_57810_MF
219 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
220 #endif
221 #ifndef PCI_DEVICE_ID_NX2_57840_O
222 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
223 #endif
224 #ifndef PCI_DEVICE_ID_NX2_57810_VF
225 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
226 #endif
227 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
228 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
229 #endif
230 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
231 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
232 #endif
233 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
234 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
235 #endif
236 #ifndef PCI_DEVICE_ID_NX2_57840_MF
237 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
238 #endif
239 #ifndef PCI_DEVICE_ID_NX2_57840_VF
240 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
241 #endif
242 #ifndef PCI_DEVICE_ID_NX2_57811
243 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
244 #endif
245 #ifndef PCI_DEVICE_ID_NX2_57811_MF
246 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
247 #endif
248 #ifndef PCI_DEVICE_ID_NX2_57811_VF
249 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
250 #endif
251 
252 static const struct pci_device_id bnx2x_pci_tbl[] = {
253         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
254         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
255         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
272         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
273         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
274         { 0 }
275 };
276 
277 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
278 
279 /* Global resources for unloading a previously loaded device */
280 #define BNX2X_PREV_WAIT_NEEDED 1
281 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
282 static LIST_HEAD(bnx2x_prev_list);
283 
284 /* Forward declaration */
285 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
286 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
287 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
288 
289 /****************************************************************************
290 * General service functions
291 ****************************************************************************/
292 
293 static void __storm_memset_dma_mapping(struct bnx2x *bp,
294                                        u32 addr, dma_addr_t mapping)
295 {
296         REG_WR(bp,  addr, U64_LO(mapping));
297         REG_WR(bp,  addr + 4, U64_HI(mapping));
298 }
299 
300 static void storm_memset_spq_addr(struct bnx2x *bp,
301                                   dma_addr_t mapping, u16 abs_fid)
302 {
303         u32 addr = XSEM_REG_FAST_MEMORY +
304                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
305 
306         __storm_memset_dma_mapping(bp, addr, mapping);
307 }
308 
309 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
310                                   u16 pf_id)
311 {
312         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
313                 pf_id);
314         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
315                 pf_id);
316         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
317                 pf_id);
318         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
319                 pf_id);
320 }
321 
322 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
323                                  u8 enable)
324 {
325         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
326                 enable);
327         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
328                 enable);
329         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
330                 enable);
331         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
332                 enable);
333 }
334 
335 static void storm_memset_eq_data(struct bnx2x *bp,
336                                  struct event_ring_data *eq_data,
337                                 u16 pfid)
338 {
339         size_t size = sizeof(struct event_ring_data);
340 
341         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
342 
343         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
344 }
345 
346 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
347                                  u16 pfid)
348 {
349         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
350         REG_WR16(bp, addr, eq_prod);
351 }
352 
353 /* used only at init
354  * locking is done by mcp
355  */
356 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
357 {
358         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
359         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
360         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
361                                PCICFG_VENDOR_ID_OFFSET);
362 }
363 
364 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
365 {
366         u32 val;
367 
368         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
369         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
370         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
371                                PCICFG_VENDOR_ID_OFFSET);
372 
373         return val;
374 }
375 
376 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
377 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
378 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
379 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
380 #define DMAE_DP_DST_NONE        "dst_addr [none]"
381 
382 static void bnx2x_dp_dmae(struct bnx2x *bp,
383                           struct dmae_command *dmae, int msglvl)
384 {
385         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
386         int i;
387 
388         switch (dmae->opcode & DMAE_COMMAND_DST) {
389         case DMAE_CMD_DST_PCI:
390                 if (src_type == DMAE_CMD_SRC_PCI)
391                         DP(msglvl, "DMAE: opcode 0x%08x\n"
392                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
393                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
394                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
395                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
396                            dmae->comp_addr_hi, dmae->comp_addr_lo,
397                            dmae->comp_val);
398                 else
399                         DP(msglvl, "DMAE: opcode 0x%08x\n"
400                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
401                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
402                            dmae->opcode, dmae->src_addr_lo >> 2,
403                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
404                            dmae->comp_addr_hi, dmae->comp_addr_lo,
405                            dmae->comp_val);
406                 break;
407         case DMAE_CMD_DST_GRC:
408                 if (src_type == DMAE_CMD_SRC_PCI)
409                         DP(msglvl, "DMAE: opcode 0x%08x\n"
410                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
411                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
412                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
413                            dmae->len, dmae->dst_addr_lo >> 2,
414                            dmae->comp_addr_hi, dmae->comp_addr_lo,
415                            dmae->comp_val);
416                 else
417                         DP(msglvl, "DMAE: opcode 0x%08x\n"
418                            "src [%08x], len [%d*4], dst [%08x]\n"
419                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
420                            dmae->opcode, dmae->src_addr_lo >> 2,
421                            dmae->len, dmae->dst_addr_lo >> 2,
422                            dmae->comp_addr_hi, dmae->comp_addr_lo,
423                            dmae->comp_val);
424                 break;
425         default:
426                 if (src_type == DMAE_CMD_SRC_PCI)
427                         DP(msglvl, "DMAE: opcode 0x%08x\n"
428                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
429                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
430                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
431                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
432                            dmae->comp_val);
433                 else
434                         DP(msglvl, "DMAE: opcode 0x%08x\n"
435                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
436                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
437                            dmae->opcode, dmae->src_addr_lo >> 2,
438                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
439                            dmae->comp_val);
440                 break;
441         }
442 
443         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
444                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
445                    i, *(((u32 *)dmae) + i));
446 }
447 
448 /* copy command into DMAE command memory and set DMAE command go */
449 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
450 {
451         u32 cmd_offset;
452         int i;
453 
454         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
455         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
456                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
457         }
458         REG_WR(bp, dmae_reg_go_c[idx], 1);
459 }
460 
461 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
462 {
463         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
464                            DMAE_CMD_C_ENABLE);
465 }
466 
467 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
468 {
469         return opcode & ~DMAE_CMD_SRC_RESET;
470 }
471 
472 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
473                              bool with_comp, u8 comp_type)
474 {
475         u32 opcode = 0;
476 
477         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
478                    (dst_type << DMAE_COMMAND_DST_SHIFT));
479 
480         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
481 
482         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
483         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
484                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
485         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
486 
487 #ifdef __BIG_ENDIAN
488         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
489 #else
490         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
491 #endif
492         if (with_comp)
493                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
494         return opcode;
495 }
496 
497 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
498                                       struct dmae_command *dmae,
499                                       u8 src_type, u8 dst_type)
500 {
501         memset(dmae, 0, sizeof(struct dmae_command));
502 
503         /* set the opcode */
504         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
505                                          true, DMAE_COMP_PCI);
506 
507         /* fill in the completion parameters */
508         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
509         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
510         dmae->comp_val = DMAE_COMP_VAL;
511 }
512 
513 /* issue a dmae command over the init-channel and wait for completion */
514 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
515                                u32 *comp)
516 {
517         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
518         int rc = 0;
519 
520         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
521 
522         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
523          * as long as this code is called both from syscall context and
524          * from ndo_set_rx_mode() flow that may be called from BH.
525          */
526         spin_lock_bh(&bp->dmae_lock);
527 
528         /* reset completion */
529         *comp = 0;
530 
531         /* post the command on the channel used for initializations */
532         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
533 
534         /* wait for completion */
535         udelay(5);
536         while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
537 
538                 if (!cnt ||
539                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
540                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
541                         BNX2X_ERR("DMAE timeout!\n");
542                         rc = DMAE_TIMEOUT;
543                         goto unlock;
544                 }
545                 cnt--;
546                 udelay(50);
547         }
548         if (*comp & DMAE_PCI_ERR_FLAG) {
549                 BNX2X_ERR("DMAE PCI error!\n");
550                 rc = DMAE_PCI_ERROR;
551         }
552 
553 unlock:
554         spin_unlock_bh(&bp->dmae_lock);
555         return rc;
556 }
557 
558 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
559                       u32 len32)
560 {
561         int rc;
562         struct dmae_command dmae;
563 
564         if (!bp->dmae_ready) {
565                 u32 *data = bnx2x_sp(bp, wb_data[0]);
566 
567                 if (CHIP_IS_E1(bp))
568                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
569                 else
570                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
571                 return;
572         }
573 
574         /* set opcode and fixed command fields */
575         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
576 
577         /* fill in addresses and len */
578         dmae.src_addr_lo = U64_LO(dma_addr);
579         dmae.src_addr_hi = U64_HI(dma_addr);
580         dmae.dst_addr_lo = dst_addr >> 2;
581         dmae.dst_addr_hi = 0;
582         dmae.len = len32;
583 
584         /* issue the command and wait for completion */
585         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
586         if (rc) {
587                 BNX2X_ERR("DMAE returned failure %d\n", rc);
588 #ifdef BNX2X_STOP_ON_ERROR
589                 bnx2x_panic();
590 #endif
591         }
592 }
593 
594 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
595 {
596         int rc;
597         struct dmae_command dmae;
598 
599         if (!bp->dmae_ready) {
600                 u32 *data = bnx2x_sp(bp, wb_data[0]);
601                 int i;
602 
603                 if (CHIP_IS_E1(bp))
604                         for (i = 0; i < len32; i++)
605                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
606                 else
607                         for (i = 0; i < len32; i++)
608                                 data[i] = REG_RD(bp, src_addr + i*4);
609 
610                 return;
611         }
612 
613         /* set opcode and fixed command fields */
614         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
615 
616         /* fill in addresses and len */
617         dmae.src_addr_lo = src_addr >> 2;
618         dmae.src_addr_hi = 0;
619         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
620         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
621         dmae.len = len32;
622 
623         /* issue the command and wait for completion */
624         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
625         if (rc) {
626                 BNX2X_ERR("DMAE returned failure %d\n", rc);
627 #ifdef BNX2X_STOP_ON_ERROR
628                 bnx2x_panic();
629 #endif
630         }
631 }
632 
633 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
634                                       u32 addr, u32 len)
635 {
636         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
637         int offset = 0;
638 
639         while (len > dmae_wr_max) {
640                 bnx2x_write_dmae(bp, phys_addr + offset,
641                                  addr + offset, dmae_wr_max);
642                 offset += dmae_wr_max * 4;
643                 len -= dmae_wr_max;
644         }
645 
646         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
647 }
648 
649 static int bnx2x_mc_assert(struct bnx2x *bp)
650 {
651         char last_idx;
652         int i, rc = 0;
653         u32 row0, row1, row2, row3;
654 
655         /* XSTORM */
656         last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
657                            XSTORM_ASSERT_LIST_INDEX_OFFSET);
658         if (last_idx)
659                 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
660 
661         /* print the asserts */
662         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
663 
664                 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
665                               XSTORM_ASSERT_LIST_OFFSET(i));
666                 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
667                               XSTORM_ASSERT_LIST_OFFSET(i) + 4);
668                 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
669                               XSTORM_ASSERT_LIST_OFFSET(i) + 8);
670                 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
671                               XSTORM_ASSERT_LIST_OFFSET(i) + 12);
672 
673                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
674                         BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
675                                   i, row3, row2, row1, row0);
676                         rc++;
677                 } else {
678                         break;
679                 }
680         }
681 
682         /* TSTORM */
683         last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
684                            TSTORM_ASSERT_LIST_INDEX_OFFSET);
685         if (last_idx)
686                 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
687 
688         /* print the asserts */
689         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
690 
691                 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
692                               TSTORM_ASSERT_LIST_OFFSET(i));
693                 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
694                               TSTORM_ASSERT_LIST_OFFSET(i) + 4);
695                 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
696                               TSTORM_ASSERT_LIST_OFFSET(i) + 8);
697                 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
698                               TSTORM_ASSERT_LIST_OFFSET(i) + 12);
699 
700                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
701                         BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
702                                   i, row3, row2, row1, row0);
703                         rc++;
704                 } else {
705                         break;
706                 }
707         }
708 
709         /* CSTORM */
710         last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
711                            CSTORM_ASSERT_LIST_INDEX_OFFSET);
712         if (last_idx)
713                 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
714 
715         /* print the asserts */
716         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
717 
718                 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
719                               CSTORM_ASSERT_LIST_OFFSET(i));
720                 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
721                               CSTORM_ASSERT_LIST_OFFSET(i) + 4);
722                 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
723                               CSTORM_ASSERT_LIST_OFFSET(i) + 8);
724                 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
725                               CSTORM_ASSERT_LIST_OFFSET(i) + 12);
726 
727                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
728                         BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
729                                   i, row3, row2, row1, row0);
730                         rc++;
731                 } else {
732                         break;
733                 }
734         }
735 
736         /* USTORM */
737         last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
738                            USTORM_ASSERT_LIST_INDEX_OFFSET);
739         if (last_idx)
740                 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
741 
742         /* print the asserts */
743         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
744 
745                 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
746                               USTORM_ASSERT_LIST_OFFSET(i));
747                 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
748                               USTORM_ASSERT_LIST_OFFSET(i) + 4);
749                 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
750                               USTORM_ASSERT_LIST_OFFSET(i) + 8);
751                 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
752                               USTORM_ASSERT_LIST_OFFSET(i) + 12);
753 
754                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
755                         BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
756                                   i, row3, row2, row1, row0);
757                         rc++;
758                 } else {
759                         break;
760                 }
761         }
762 
763         return rc;
764 }
765 
766 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
767 #define SCRATCH_BUFFER_SIZE(bp) \
768         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
769 
770 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
771 {
772         u32 addr, val;
773         u32 mark, offset;
774         __be32 data[9];
775         int word;
776         u32 trace_shmem_base;
777         if (BP_NOMCP(bp)) {
778                 BNX2X_ERR("NO MCP - can not dump\n");
779                 return;
780         }
781         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
782                 (bp->common.bc_ver & 0xff0000) >> 16,
783                 (bp->common.bc_ver & 0xff00) >> 8,
784                 (bp->common.bc_ver & 0xff));
785 
786         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
787         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
788                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
789 
790         if (BP_PATH(bp) == 0)
791                 trace_shmem_base = bp->common.shmem_base;
792         else
793                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
794 
795         /* sanity */
796         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
797             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
798                                 SCRATCH_BUFFER_SIZE(bp)) {
799                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
800                           trace_shmem_base);
801                 return;
802         }
803 
804         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
805 
806         /* validate TRCB signature */
807         mark = REG_RD(bp, addr);
808         if (mark != MFW_TRACE_SIGNATURE) {
809                 BNX2X_ERR("Trace buffer signature is missing.");
810                 return ;
811         }
812 
813         /* read cyclic buffer pointer */
814         addr += 4;
815         mark = REG_RD(bp, addr);
816         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
817         if (mark >= trace_shmem_base || mark < addr + 4) {
818                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
819                 return;
820         }
821         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
822 
823         printk("%s", lvl);
824 
825         /* dump buffer after the mark */
826         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
827                 for (word = 0; word < 8; word++)
828                         data[word] = htonl(REG_RD(bp, offset + 4*word));
829                 data[8] = 0x0;
830                 pr_cont("%s", (char *)data);
831         }
832 
833         /* dump buffer before the mark */
834         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
835                 for (word = 0; word < 8; word++)
836                         data[word] = htonl(REG_RD(bp, offset + 4*word));
837                 data[8] = 0x0;
838                 pr_cont("%s", (char *)data);
839         }
840         printk("%s" "end of fw dump\n", lvl);
841 }
842 
843 static void bnx2x_fw_dump(struct bnx2x *bp)
844 {
845         bnx2x_fw_dump_lvl(bp, KERN_ERR);
846 }
847 
848 static void bnx2x_hc_int_disable(struct bnx2x *bp)
849 {
850         int port = BP_PORT(bp);
851         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
852         u32 val = REG_RD(bp, addr);
853 
854         /* in E1 we must use only PCI configuration space to disable
855          * MSI/MSIX capability
856          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
857          */
858         if (CHIP_IS_E1(bp)) {
859                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
860                  * Use mask register to prevent from HC sending interrupts
861                  * after we exit the function
862                  */
863                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
864 
865                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
866                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
867                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
868         } else
869                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
870                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
871                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
872                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
873 
874         DP(NETIF_MSG_IFDOWN,
875            "write %x to HC %d (addr 0x%x)\n",
876            val, port, addr);
877 
878         /* flush all outstanding writes */
879         mmiowb();
880 
881         REG_WR(bp, addr, val);
882         if (REG_RD(bp, addr) != val)
883                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
884 }
885 
886 static void bnx2x_igu_int_disable(struct bnx2x *bp)
887 {
888         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
889 
890         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
891                  IGU_PF_CONF_INT_LINE_EN |
892                  IGU_PF_CONF_ATTN_BIT_EN);
893 
894         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
895 
896         /* flush all outstanding writes */
897         mmiowb();
898 
899         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
900         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
901                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
902 }
903 
904 static void bnx2x_int_disable(struct bnx2x *bp)
905 {
906         if (bp->common.int_block == INT_BLOCK_HC)
907                 bnx2x_hc_int_disable(bp);
908         else
909                 bnx2x_igu_int_disable(bp);
910 }
911 
912 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
913 {
914         int i;
915         u16 j;
916         struct hc_sp_status_block_data sp_sb_data;
917         int func = BP_FUNC(bp);
918 #ifdef BNX2X_STOP_ON_ERROR
919         u16 start = 0, end = 0;
920         u8 cos;
921 #endif
922         if (IS_PF(bp) && disable_int)
923                 bnx2x_int_disable(bp);
924 
925         bp->stats_state = STATS_STATE_DISABLED;
926         bp->eth_stats.unrecoverable_error++;
927         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
928 
929         BNX2X_ERR("begin crash dump -----------------\n");
930 
931         /* Indices */
932         /* Common */
933         if (IS_PF(bp)) {
934                 struct host_sp_status_block *def_sb = bp->def_status_blk;
935                 int data_size, cstorm_offset;
936 
937                 BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
938                           bp->def_idx, bp->def_att_idx, bp->attn_state,
939                           bp->spq_prod_idx, bp->stats_counter);
940                 BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
941                           def_sb->atten_status_block.attn_bits,
942                           def_sb->atten_status_block.attn_bits_ack,
943                           def_sb->atten_status_block.status_block_id,
944                           def_sb->atten_status_block.attn_bits_index);
945                 BNX2X_ERR("     def (");
946                 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
947                         pr_cont("0x%x%s",
948                                 def_sb->sp_sb.index_values[i],
949                                 (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
950 
951                 data_size = sizeof(struct hc_sp_status_block_data) /
952                             sizeof(u32);
953                 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
954                 for (i = 0; i < data_size; i++)
955                         *((u32 *)&sp_sb_data + i) =
956                                 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
957                                            i * sizeof(u32));
958 
959                 pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
960                         sp_sb_data.igu_sb_id,
961                         sp_sb_data.igu_seg_id,
962                         sp_sb_data.p_func.pf_id,
963                         sp_sb_data.p_func.vnic_id,
964                         sp_sb_data.p_func.vf_id,
965                         sp_sb_data.p_func.vf_valid,
966                         sp_sb_data.state);
967         }
968 
969         for_each_eth_queue(bp, i) {
970                 struct bnx2x_fastpath *fp = &bp->fp[i];
971                 int loop;
972                 struct hc_status_block_data_e2 sb_data_e2;
973                 struct hc_status_block_data_e1x sb_data_e1x;
974                 struct hc_status_block_sm  *hc_sm_p =
975                         CHIP_IS_E1x(bp) ?
976                         sb_data_e1x.common.state_machine :
977                         sb_data_e2.common.state_machine;
978                 struct hc_index_data *hc_index_p =
979                         CHIP_IS_E1x(bp) ?
980                         sb_data_e1x.index_data :
981                         sb_data_e2.index_data;
982                 u8 data_size, cos;
983                 u32 *sb_data_p;
984                 struct bnx2x_fp_txdata txdata;
985 
986                 /* Rx */
987                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
988                           i, fp->rx_bd_prod, fp->rx_bd_cons,
989                           fp->rx_comp_prod,
990                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
991                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
992                           fp->rx_sge_prod, fp->last_max_sge,
993                           le16_to_cpu(fp->fp_hc_idx));
994 
995                 /* Tx */
996                 for_each_cos_in_tx_queue(fp, cos)
997                 {
998                         txdata = *fp->txdata_ptr[cos];
999                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
1000                                   i, txdata.tx_pkt_prod,
1001                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
1002                                   txdata.tx_bd_cons,
1003                                   le16_to_cpu(*txdata.tx_cons_sb));
1004                 }
1005 
1006                 loop = CHIP_IS_E1x(bp) ?
1007                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1008 
1009                 /* host sb data */
1010 
1011                 if (IS_FCOE_FP(fp))
1012                         continue;
1013 
1014                 BNX2X_ERR("     run indexes (");
1015                 for (j = 0; j < HC_SB_MAX_SM; j++)
1016                         pr_cont("0x%x%s",
1017                                fp->sb_running_index[j],
1018                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1019 
1020                 BNX2X_ERR("     indexes (");
1021                 for (j = 0; j < loop; j++)
1022                         pr_cont("0x%x%s",
1023                                fp->sb_index_values[j],
1024                                (j == loop - 1) ? ")" : " ");
1025 
1026                 /* VF cannot access FW refelection for status block */
1027                 if (IS_VF(bp))
1028                         continue;
1029 
1030                 /* fw sb data */
1031                 data_size = CHIP_IS_E1x(bp) ?
1032                         sizeof(struct hc_status_block_data_e1x) :
1033                         sizeof(struct hc_status_block_data_e2);
1034                 data_size /= sizeof(u32);
1035                 sb_data_p = CHIP_IS_E1x(bp) ?
1036                         (u32 *)&sb_data_e1x :
1037                         (u32 *)&sb_data_e2;
1038                 /* copy sb data in here */
1039                 for (j = 0; j < data_size; j++)
1040                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1041                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1042                                 j * sizeof(u32));
1043 
1044                 if (!CHIP_IS_E1x(bp)) {
1045                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1046                                 sb_data_e2.common.p_func.pf_id,
1047                                 sb_data_e2.common.p_func.vf_id,
1048                                 sb_data_e2.common.p_func.vf_valid,
1049                                 sb_data_e2.common.p_func.vnic_id,
1050                                 sb_data_e2.common.same_igu_sb_1b,
1051                                 sb_data_e2.common.state);
1052                 } else {
1053                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1054                                 sb_data_e1x.common.p_func.pf_id,
1055                                 sb_data_e1x.common.p_func.vf_id,
1056                                 sb_data_e1x.common.p_func.vf_valid,
1057                                 sb_data_e1x.common.p_func.vnic_id,
1058                                 sb_data_e1x.common.same_igu_sb_1b,
1059                                 sb_data_e1x.common.state);
1060                 }
1061 
1062                 /* SB_SMs data */
1063                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1064                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1065                                 j, hc_sm_p[j].__flags,
1066                                 hc_sm_p[j].igu_sb_id,
1067                                 hc_sm_p[j].igu_seg_id,
1068                                 hc_sm_p[j].time_to_expire,
1069                                 hc_sm_p[j].timer_value);
1070                 }
1071 
1072                 /* Indices data */
1073                 for (j = 0; j < loop; j++) {
1074                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1075                                hc_index_p[j].flags,
1076                                hc_index_p[j].timeout);
1077                 }
1078         }
1079 
1080 #ifdef BNX2X_STOP_ON_ERROR
1081         if (IS_PF(bp)) {
1082                 /* event queue */
1083                 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1084                 for (i = 0; i < NUM_EQ_DESC; i++) {
1085                         u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1086 
1087                         BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1088                                   i, bp->eq_ring[i].message.opcode,
1089                                   bp->eq_ring[i].message.error);
1090                         BNX2X_ERR("data: %x %x %x\n",
1091                                   data[0], data[1], data[2]);
1092                 }
1093         }
1094 
1095         /* Rings */
1096         /* Rx */
1097         for_each_valid_rx_queue(bp, i) {
1098                 struct bnx2x_fastpath *fp = &bp->fp[i];
1099 
1100                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1101                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1102                 for (j = start; j != end; j = RX_BD(j + 1)) {
1103                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1104                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1105 
1106                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1107                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1108                 }
1109 
1110                 start = RX_SGE(fp->rx_sge_prod);
1111                 end = RX_SGE(fp->last_max_sge);
1112                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1113                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1114                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1115 
1116                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1117                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1118                 }
1119 
1120                 start = RCQ_BD(fp->rx_comp_cons - 10);
1121                 end = RCQ_BD(fp->rx_comp_cons + 503);
1122                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1123                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1124 
1125                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1126                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1127                 }
1128         }
1129 
1130         /* Tx */
1131         for_each_valid_tx_queue(bp, i) {
1132                 struct bnx2x_fastpath *fp = &bp->fp[i];
1133                 for_each_cos_in_tx_queue(fp, cos) {
1134                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1135 
1136                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1137                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1138                         for (j = start; j != end; j = TX_BD(j + 1)) {
1139                                 struct sw_tx_bd *sw_bd =
1140                                         &txdata->tx_buf_ring[j];
1141 
1142                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1143                                           i, cos, j, sw_bd->skb,
1144                                           sw_bd->first_bd);
1145                         }
1146 
1147                         start = TX_BD(txdata->tx_bd_cons - 10);
1148                         end = TX_BD(txdata->tx_bd_cons + 254);
1149                         for (j = start; j != end; j = TX_BD(j + 1)) {
1150                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1151 
1152                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1153                                           i, cos, j, tx_bd[0], tx_bd[1],
1154                                           tx_bd[2], tx_bd[3]);
1155                         }
1156                 }
1157         }
1158 #endif
1159         if (IS_PF(bp)) {
1160                 bnx2x_fw_dump(bp);
1161                 bnx2x_mc_assert(bp);
1162         }
1163         BNX2X_ERR("end crash dump -----------------\n");
1164 }
1165 
1166 /*
1167  * FLR Support for E2
1168  *
1169  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1170  * initialization.
1171  */
1172 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1173 #define FLR_WAIT_INTERVAL       50      /* usec */
1174 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1175 
1176 struct pbf_pN_buf_regs {
1177         int pN;
1178         u32 init_crd;
1179         u32 crd;
1180         u32 crd_freed;
1181 };
1182 
1183 struct pbf_pN_cmd_regs {
1184         int pN;
1185         u32 lines_occup;
1186         u32 lines_freed;
1187 };
1188 
1189 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1190                                      struct pbf_pN_buf_regs *regs,
1191                                      u32 poll_count)
1192 {
1193         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1194         u32 cur_cnt = poll_count;
1195 
1196         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1197         crd = crd_start = REG_RD(bp, regs->crd);
1198         init_crd = REG_RD(bp, regs->init_crd);
1199 
1200         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1201         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1202         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1203 
1204         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1205                (init_crd - crd_start))) {
1206                 if (cur_cnt--) {
1207                         udelay(FLR_WAIT_INTERVAL);
1208                         crd = REG_RD(bp, regs->crd);
1209                         crd_freed = REG_RD(bp, regs->crd_freed);
1210                 } else {
1211                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1212                            regs->pN);
1213                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1214                            regs->pN, crd);
1215                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1216                            regs->pN, crd_freed);
1217                         break;
1218                 }
1219         }
1220         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1221            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1222 }
1223 
1224 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1225                                      struct pbf_pN_cmd_regs *regs,
1226                                      u32 poll_count)
1227 {
1228         u32 occup, to_free, freed, freed_start;
1229         u32 cur_cnt = poll_count;
1230 
1231         occup = to_free = REG_RD(bp, regs->lines_occup);
1232         freed = freed_start = REG_RD(bp, regs->lines_freed);
1233 
1234         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1235         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1236 
1237         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1238                 if (cur_cnt--) {
1239                         udelay(FLR_WAIT_INTERVAL);
1240                         occup = REG_RD(bp, regs->lines_occup);
1241                         freed = REG_RD(bp, regs->lines_freed);
1242                 } else {
1243                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1244                            regs->pN);
1245                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1246                            regs->pN, occup);
1247                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1248                            regs->pN, freed);
1249                         break;
1250                 }
1251         }
1252         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1253            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1254 }
1255 
1256 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1257                                     u32 expected, u32 poll_count)
1258 {
1259         u32 cur_cnt = poll_count;
1260         u32 val;
1261 
1262         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1263                 udelay(FLR_WAIT_INTERVAL);
1264 
1265         return val;
1266 }
1267 
1268 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1269                                     char *msg, u32 poll_cnt)
1270 {
1271         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1272         if (val != 0) {
1273                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1274                 return 1;
1275         }
1276         return 0;
1277 }
1278 
1279 /* Common routines with VF FLR cleanup */
1280 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1281 {
1282         /* adjust polling timeout */
1283         if (CHIP_REV_IS_EMUL(bp))
1284                 return FLR_POLL_CNT * 2000;
1285 
1286         if (CHIP_REV_IS_FPGA(bp))
1287                 return FLR_POLL_CNT * 120;
1288 
1289         return FLR_POLL_CNT;
1290 }
1291 
1292 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1293 {
1294         struct pbf_pN_cmd_regs cmd_regs[] = {
1295                 {0, (CHIP_IS_E3B0(bp)) ?
1296                         PBF_REG_TQ_OCCUPANCY_Q0 :
1297                         PBF_REG_P0_TQ_OCCUPANCY,
1298                     (CHIP_IS_E3B0(bp)) ?
1299                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1300                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1301                 {1, (CHIP_IS_E3B0(bp)) ?
1302                         PBF_REG_TQ_OCCUPANCY_Q1 :
1303                         PBF_REG_P1_TQ_OCCUPANCY,
1304                     (CHIP_IS_E3B0(bp)) ?
1305                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1306                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1307                 {4, (CHIP_IS_E3B0(bp)) ?
1308                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1309                         PBF_REG_P4_TQ_OCCUPANCY,
1310                     (CHIP_IS_E3B0(bp)) ?
1311                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1312                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1313         };
1314 
1315         struct pbf_pN_buf_regs buf_regs[] = {
1316                 {0, (CHIP_IS_E3B0(bp)) ?
1317                         PBF_REG_INIT_CRD_Q0 :
1318                         PBF_REG_P0_INIT_CRD ,
1319                     (CHIP_IS_E3B0(bp)) ?
1320                         PBF_REG_CREDIT_Q0 :
1321                         PBF_REG_P0_CREDIT,
1322                     (CHIP_IS_E3B0(bp)) ?
1323                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1324                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1325                 {1, (CHIP_IS_E3B0(bp)) ?
1326                         PBF_REG_INIT_CRD_Q1 :
1327                         PBF_REG_P1_INIT_CRD,
1328                     (CHIP_IS_E3B0(bp)) ?
1329                         PBF_REG_CREDIT_Q1 :
1330                         PBF_REG_P1_CREDIT,
1331                     (CHIP_IS_E3B0(bp)) ?
1332                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1333                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1334                 {4, (CHIP_IS_E3B0(bp)) ?
1335                         PBF_REG_INIT_CRD_LB_Q :
1336                         PBF_REG_P4_INIT_CRD,
1337                     (CHIP_IS_E3B0(bp)) ?
1338                         PBF_REG_CREDIT_LB_Q :
1339                         PBF_REG_P4_CREDIT,
1340                     (CHIP_IS_E3B0(bp)) ?
1341                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1342                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1343         };
1344 
1345         int i;
1346 
1347         /* Verify the command queues are flushed P0, P1, P4 */
1348         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1349                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1350 
1351         /* Verify the transmission buffers are flushed P0, P1, P4 */
1352         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1353                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1354 }
1355 
1356 #define OP_GEN_PARAM(param) \
1357         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1358 
1359 #define OP_GEN_TYPE(type) \
1360         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1361 
1362 #define OP_GEN_AGG_VECT(index) \
1363         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1364 
1365 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1366 {
1367         u32 op_gen_command = 0;
1368         u32 comp_addr = BAR_CSTRORM_INTMEM +
1369                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1370         int ret = 0;
1371 
1372         if (REG_RD(bp, comp_addr)) {
1373                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1374                 return 1;
1375         }
1376 
1377         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1378         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1379         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1380         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1381 
1382         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1383         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1384 
1385         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1386                 BNX2X_ERR("FW final cleanup did not succeed\n");
1387                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1388                    (REG_RD(bp, comp_addr)));
1389                 bnx2x_panic();
1390                 return 1;
1391         }
1392         /* Zero completion for next FLR */
1393         REG_WR(bp, comp_addr, 0);
1394 
1395         return ret;
1396 }
1397 
1398 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1399 {
1400         u16 status;
1401 
1402         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1403         return status & PCI_EXP_DEVSTA_TRPND;
1404 }
1405 
1406 /* PF FLR specific routines
1407 */
1408 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1409 {
1410         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1411         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1412                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1413                         "CFC PF usage counter timed out",
1414                         poll_cnt))
1415                 return 1;
1416 
1417         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1418         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1419                         DORQ_REG_PF_USAGE_CNT,
1420                         "DQ PF usage counter timed out",
1421                         poll_cnt))
1422                 return 1;
1423 
1424         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1425         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1426                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1427                         "QM PF usage counter timed out",
1428                         poll_cnt))
1429                 return 1;
1430 
1431         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1432         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1433                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1434                         "Timers VNIC usage counter timed out",
1435                         poll_cnt))
1436                 return 1;
1437         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1438                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1439                         "Timers NUM_SCANS usage counter timed out",
1440                         poll_cnt))
1441                 return 1;
1442 
1443         /* Wait DMAE PF usage counter to zero */
1444         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1445                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1446                         "DMAE command register timed out",
1447                         poll_cnt))
1448                 return 1;
1449 
1450         return 0;
1451 }
1452 
1453 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1454 {
1455         u32 val;
1456 
1457         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1458         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1459 
1460         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1461         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1462 
1463         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1464         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1465 
1466         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1467         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1468 
1469         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1470         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1471 
1472         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1473         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1474 
1475         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1476         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1477 
1478         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1479         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1480            val);
1481 }
1482 
1483 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1484 {
1485         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1486 
1487         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1488 
1489         /* Re-enable PF target read access */
1490         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1491 
1492         /* Poll HW usage counters */
1493         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1494         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1495                 return -EBUSY;
1496 
1497         /* Zero the igu 'trailing edge' and 'leading edge' */
1498 
1499         /* Send the FW cleanup command */
1500         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1501                 return -EBUSY;
1502 
1503         /* ATC cleanup */
1504 
1505         /* Verify TX hw is flushed */
1506         bnx2x_tx_hw_flushed(bp, poll_cnt);
1507 
1508         /* Wait 100ms (not adjusted according to platform) */
1509         msleep(100);
1510 
1511         /* Verify no pending pci transactions */
1512         if (bnx2x_is_pcie_pending(bp->pdev))
1513                 BNX2X_ERR("PCIE Transactions still pending\n");
1514 
1515         /* Debug */
1516         bnx2x_hw_enable_status(bp);
1517 
1518         /*
1519          * Master enable - Due to WB DMAE writes performed before this
1520          * register is re-initialized as part of the regular function init
1521          */
1522         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1523 
1524         return 0;
1525 }
1526 
1527 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1528 {
1529         int port = BP_PORT(bp);
1530         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1531         u32 val = REG_RD(bp, addr);
1532         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1533         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1534         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1535 
1536         if (msix) {
1537                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1538                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1539                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1540                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1541                 if (single_msix)
1542                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1543         } else if (msi) {
1544                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1545                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1546                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1547                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1548         } else {
1549                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1550                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1551                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1552                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1553 
1554                 if (!CHIP_IS_E1(bp)) {
1555                         DP(NETIF_MSG_IFUP,
1556                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1557 
1558                         REG_WR(bp, addr, val);
1559 
1560                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1561                 }
1562         }
1563 
1564         if (CHIP_IS_E1(bp))
1565                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1566 
1567         DP(NETIF_MSG_IFUP,
1568            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1569            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1570 
1571         REG_WR(bp, addr, val);
1572         /*
1573          * Ensure that HC_CONFIG is written before leading/trailing edge config
1574          */
1575         mmiowb();
1576         barrier();
1577 
1578         if (!CHIP_IS_E1(bp)) {
1579                 /* init leading/trailing edge */
1580                 if (IS_MF(bp)) {
1581                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1582                         if (bp->port.pmf)
1583                                 /* enable nig and gpio3 attention */
1584                                 val |= 0x1100;
1585                 } else
1586                         val = 0xffff;
1587 
1588                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1589                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1590         }
1591 
1592         /* Make sure that interrupts are indeed enabled from here on */
1593         mmiowb();
1594 }
1595 
1596 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1597 {
1598         u32 val;
1599         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1600         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1601         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1602 
1603         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1604 
1605         if (msix) {
1606                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1607                          IGU_PF_CONF_SINGLE_ISR_EN);
1608                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1609                         IGU_PF_CONF_ATTN_BIT_EN);
1610 
1611                 if (single_msix)
1612                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1613         } else if (msi) {
1614                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1615                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1616                         IGU_PF_CONF_ATTN_BIT_EN |
1617                         IGU_PF_CONF_SINGLE_ISR_EN);
1618         } else {
1619                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1620                 val |= (IGU_PF_CONF_INT_LINE_EN |
1621                         IGU_PF_CONF_ATTN_BIT_EN |
1622                         IGU_PF_CONF_SINGLE_ISR_EN);
1623         }
1624 
1625         /* Clean previous status - need to configure igu prior to ack*/
1626         if ((!msix) || single_msix) {
1627                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1628                 bnx2x_ack_int(bp);
1629         }
1630 
1631         val |= IGU_PF_CONF_FUNC_EN;
1632 
1633         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1634            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1635 
1636         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1637 
1638         if (val & IGU_PF_CONF_INT_LINE_EN)
1639                 pci_intx(bp->pdev, true);
1640 
1641         barrier();
1642 
1643         /* init leading/trailing edge */
1644         if (IS_MF(bp)) {
1645                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1646                 if (bp->port.pmf)
1647                         /* enable nig and gpio3 attention */
1648                         val |= 0x1100;
1649         } else
1650                 val = 0xffff;
1651 
1652         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1653         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1654 
1655         /* Make sure that interrupts are indeed enabled from here on */
1656         mmiowb();
1657 }
1658 
1659 void bnx2x_int_enable(struct bnx2x *bp)
1660 {
1661         if (bp->common.int_block == INT_BLOCK_HC)
1662                 bnx2x_hc_int_enable(bp);
1663         else
1664                 bnx2x_igu_int_enable(bp);
1665 }
1666 
1667 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1668 {
1669         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1670         int i, offset;
1671 
1672         if (disable_hw)
1673                 /* prevent the HW from sending interrupts */
1674                 bnx2x_int_disable(bp);
1675 
1676         /* make sure all ISRs are done */
1677         if (msix) {
1678                 synchronize_irq(bp->msix_table[0].vector);
1679                 offset = 1;
1680                 if (CNIC_SUPPORT(bp))
1681                         offset++;
1682                 for_each_eth_queue(bp, i)
1683                         synchronize_irq(bp->msix_table[offset++].vector);
1684         } else
1685                 synchronize_irq(bp->pdev->irq);
1686 
1687         /* make sure sp_task is not running */
1688         cancel_delayed_work(&bp->sp_task);
1689         cancel_delayed_work(&bp->period_task);
1690         flush_workqueue(bnx2x_wq);
1691 }
1692 
1693 /* fast path */
1694 
1695 /*
1696  * General service functions
1697  */
1698 
1699 /* Return true if succeeded to acquire the lock */
1700 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1701 {
1702         u32 lock_status;
1703         u32 resource_bit = (1 << resource);
1704         int func = BP_FUNC(bp);
1705         u32 hw_lock_control_reg;
1706 
1707         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1708            "Trying to take a lock on resource %d\n", resource);
1709 
1710         /* Validating that the resource is within range */
1711         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1712                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1713                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1714                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1715                 return false;
1716         }
1717 
1718         if (func <= 5)
1719                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1720         else
1721                 hw_lock_control_reg =
1722                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1723 
1724         /* Try to acquire the lock */
1725         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1726         lock_status = REG_RD(bp, hw_lock_control_reg);
1727         if (lock_status & resource_bit)
1728                 return true;
1729 
1730         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1731            "Failed to get a lock on resource %d\n", resource);
1732         return false;
1733 }
1734 
1735 /**
1736  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1737  *
1738  * @bp: driver handle
1739  *
1740  * Returns the recovery leader resource id according to the engine this function
1741  * belongs to. Currently only only 2 engines is supported.
1742  */
1743 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1744 {
1745         if (BP_PATH(bp))
1746                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1747         else
1748                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1749 }
1750 
1751 /**
1752  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1753  *
1754  * @bp: driver handle
1755  *
1756  * Tries to acquire a leader lock for current engine.
1757  */
1758 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1759 {
1760         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1761 }
1762 
1763 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1764 
1765 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1766 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1767 {
1768         /* Set the interrupt occurred bit for the sp-task to recognize it
1769          * must ack the interrupt and transition according to the IGU
1770          * state machine.
1771          */
1772         atomic_set(&bp->interrupt_occurred, 1);
1773 
1774         /* The sp_task must execute only after this bit
1775          * is set, otherwise we will get out of sync and miss all
1776          * further interrupts. Hence, the barrier.
1777          */
1778         smp_wmb();
1779 
1780         /* schedule sp_task to workqueue */
1781         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1782 }
1783 
1784 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1785 {
1786         struct bnx2x *bp = fp->bp;
1787         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1788         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1789         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1790         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1791 
1792         DP(BNX2X_MSG_SP,
1793            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1794            fp->index, cid, command, bp->state,
1795            rr_cqe->ramrod_cqe.ramrod_type);
1796 
1797         /* If cid is within VF range, replace the slowpath object with the
1798          * one corresponding to this VF
1799          */
1800         if (cid >= BNX2X_FIRST_VF_CID  &&
1801             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1802                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1803 
1804         switch (command) {
1805         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1806                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1807                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1808                 break;
1809 
1810         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1811                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1812                 drv_cmd = BNX2X_Q_CMD_SETUP;
1813                 break;
1814 
1815         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1816                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1817                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1818                 break;
1819 
1820         case (RAMROD_CMD_ID_ETH_HALT):
1821                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1822                 drv_cmd = BNX2X_Q_CMD_HALT;
1823                 break;
1824 
1825         case (RAMROD_CMD_ID_ETH_TERMINATE):
1826                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1827                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1828                 break;
1829 
1830         case (RAMROD_CMD_ID_ETH_EMPTY):
1831                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1832                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1833                 break;
1834 
1835         case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1836                 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1837                 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1838                 break;
1839 
1840         default:
1841                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1842                           command, fp->index);
1843                 return;
1844         }
1845 
1846         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1847             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1848                 /* q_obj->complete_cmd() failure means that this was
1849                  * an unexpected completion.
1850                  *
1851                  * In this case we don't want to increase the bp->spq_left
1852                  * because apparently we haven't sent this command the first
1853                  * place.
1854                  */
1855 #ifdef BNX2X_STOP_ON_ERROR
1856                 bnx2x_panic();
1857 #else
1858                 return;
1859 #endif
1860 
1861         smp_mb__before_atomic();
1862         atomic_inc(&bp->cq_spq_left);
1863         /* push the change in bp->spq_left and towards the memory */
1864         smp_mb__after_atomic();
1865 
1866         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1867 
1868         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1869             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1870                 /* if Q update ramrod is completed for last Q in AFEX vif set
1871                  * flow, then ACK MCP at the end
1872                  *
1873                  * mark pending ACK to MCP bit.
1874                  * prevent case that both bits are cleared.
1875                  * At the end of load/unload driver checks that
1876                  * sp_state is cleared, and this order prevents
1877                  * races
1878                  */
1879                 smp_mb__before_atomic();
1880                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1881                 wmb();
1882                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1883                 smp_mb__after_atomic();
1884 
1885                 /* schedule the sp task as mcp ack is required */
1886                 bnx2x_schedule_sp_task(bp);
1887         }
1888 
1889         return;
1890 }
1891 
1892 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1893 {
1894         struct bnx2x *bp = netdev_priv(dev_instance);
1895         u16 status = bnx2x_ack_int(bp);
1896         u16 mask;
1897         int i;
1898         u8 cos;
1899 
1900         /* Return here if interrupt is shared and it's not for us */
1901         if (unlikely(status == 0)) {
1902                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1903                 return IRQ_NONE;
1904         }
1905         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1906 
1907 #ifdef BNX2X_STOP_ON_ERROR
1908         if (unlikely(bp->panic))
1909                 return IRQ_HANDLED;
1910 #endif
1911 
1912         for_each_eth_queue(bp, i) {
1913                 struct bnx2x_fastpath *fp = &bp->fp[i];
1914 
1915                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1916                 if (status & mask) {
1917                         /* Handle Rx or Tx according to SB id */
1918                         for_each_cos_in_tx_queue(fp, cos)
1919                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1920                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1921                         napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1922                         status &= ~mask;
1923                 }
1924         }
1925 
1926         if (CNIC_SUPPORT(bp)) {
1927                 mask = 0x2;
1928                 if (status & (mask | 0x1)) {
1929                         struct cnic_ops *c_ops = NULL;
1930 
1931                         rcu_read_lock();
1932                         c_ops = rcu_dereference(bp->cnic_ops);
1933                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1934                                       CNIC_DRV_STATE_HANDLES_IRQ))
1935                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1936                         rcu_read_unlock();
1937 
1938                         status &= ~mask;
1939                 }
1940         }
1941 
1942         if (unlikely(status & 0x1)) {
1943 
1944                 /* schedule sp task to perform default status block work, ack
1945                  * attentions and enable interrupts.
1946                  */
1947                 bnx2x_schedule_sp_task(bp);
1948 
1949                 status &= ~0x1;
1950                 if (!status)
1951                         return IRQ_HANDLED;
1952         }
1953 
1954         if (unlikely(status))
1955                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1956                    status);
1957 
1958         return IRQ_HANDLED;
1959 }
1960 
1961 /* Link */
1962 
1963 /*
1964  * General service functions
1965  */
1966 
1967 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1968 {
1969         u32 lock_status;
1970         u32 resource_bit = (1 << resource);
1971         int func = BP_FUNC(bp);
1972         u32 hw_lock_control_reg;
1973         int cnt;
1974 
1975         /* Validating that the resource is within range */
1976         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1977                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1978                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1979                 return -EINVAL;
1980         }
1981 
1982         if (func <= 5) {
1983                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1984         } else {
1985                 hw_lock_control_reg =
1986                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1987         }
1988 
1989         /* Validating that the resource is not already taken */
1990         lock_status = REG_RD(bp, hw_lock_control_reg);
1991         if (lock_status & resource_bit) {
1992                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
1993                    lock_status, resource_bit);
1994                 return -EEXIST;
1995         }
1996 
1997         /* Try for 5 second every 5ms */
1998         for (cnt = 0; cnt < 1000; cnt++) {
1999                 /* Try to acquire the lock */
2000                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2001                 lock_status = REG_RD(bp, hw_lock_control_reg);
2002                 if (lock_status & resource_bit)
2003                         return 0;
2004 
2005                 usleep_range(5000, 10000);
2006         }
2007         BNX2X_ERR("Timeout\n");
2008         return -EAGAIN;
2009 }
2010 
2011 int bnx2x_release_leader_lock(struct bnx2x *bp)
2012 {
2013         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2014 }
2015 
2016 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2017 {
2018         u32 lock_status;
2019         u32 resource_bit = (1 << resource);
2020         int func = BP_FUNC(bp);
2021         u32 hw_lock_control_reg;
2022 
2023         /* Validating that the resource is within range */
2024         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2025                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2026                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
2027                 return -EINVAL;
2028         }
2029 
2030         if (func <= 5) {
2031                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2032         } else {
2033                 hw_lock_control_reg =
2034                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2035         }
2036 
2037         /* Validating that the resource is currently taken */
2038         lock_status = REG_RD(bp, hw_lock_control_reg);
2039         if (!(lock_status & resource_bit)) {
2040                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2041                           lock_status, resource_bit);
2042                 return -EFAULT;
2043         }
2044 
2045         REG_WR(bp, hw_lock_control_reg, resource_bit);
2046         return 0;
2047 }
2048 
2049 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2050 {
2051         /* The GPIO should be swapped if swap register is set and active */
2052         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2053                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2054         int gpio_shift = gpio_num +
2055                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2056         u32 gpio_mask = (1 << gpio_shift);
2057         u32 gpio_reg;
2058         int value;
2059 
2060         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2061                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2062                 return -EINVAL;
2063         }
2064 
2065         /* read GPIO value */
2066         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2067 
2068         /* get the requested pin value */
2069         if ((gpio_reg & gpio_mask) == gpio_mask)
2070                 value = 1;
2071         else
2072                 value = 0;
2073 
2074         DP(NETIF_MSG_LINK, "pin %d  value 0x%x\n", gpio_num, value);
2075 
2076         return value;
2077 }
2078 
2079 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2080 {
2081         /* The GPIO should be swapped if swap register is set and active */
2082         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2083                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2084         int gpio_shift = gpio_num +
2085                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2086         u32 gpio_mask = (1 << gpio_shift);
2087         u32 gpio_reg;
2088 
2089         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2090                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2091                 return -EINVAL;
2092         }
2093 
2094         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2095         /* read GPIO and mask except the float bits */
2096         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2097 
2098         switch (mode) {
2099         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2100                 DP(NETIF_MSG_LINK,
2101                    "Set GPIO %d (shift %d) -> output low\n",
2102                    gpio_num, gpio_shift);
2103                 /* clear FLOAT and set CLR */
2104                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2105                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2106                 break;
2107 
2108         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2109                 DP(NETIF_MSG_LINK,
2110                    "Set GPIO %d (shift %d) -> output high\n",
2111                    gpio_num, gpio_shift);
2112                 /* clear FLOAT and set SET */
2113                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2114                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2115                 break;
2116 
2117         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2118                 DP(NETIF_MSG_LINK,
2119                    "Set GPIO %d (shift %d) -> input\n",
2120                    gpio_num, gpio_shift);
2121                 /* set FLOAT */
2122                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2123                 break;
2124 
2125         default:
2126                 break;
2127         }
2128 
2129         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2130         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2131 
2132         return 0;
2133 }
2134 
2135 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2136 {
2137         u32 gpio_reg = 0;
2138         int rc = 0;
2139 
2140         /* Any port swapping should be handled by caller. */
2141 
2142         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2143         /* read GPIO and mask except the float bits */
2144         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2145         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2146         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2147         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2148 
2149         switch (mode) {
2150         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2151                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2152                 /* set CLR */
2153                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2154                 break;
2155 
2156         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2157                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2158                 /* set SET */
2159                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2160                 break;
2161 
2162         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2163                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2164                 /* set FLOAT */
2165                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2166                 break;
2167 
2168         default:
2169                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2170                 rc = -EINVAL;
2171                 break;
2172         }
2173 
2174         if (rc == 0)
2175                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2176 
2177         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2178 
2179         return rc;
2180 }
2181 
2182 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2183 {
2184         /* The GPIO should be swapped if swap register is set and active */
2185         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2186                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2187         int gpio_shift = gpio_num +
2188                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2189         u32 gpio_mask = (1 << gpio_shift);
2190         u32 gpio_reg;
2191 
2192         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2193                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2194                 return -EINVAL;
2195         }
2196 
2197         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2198         /* read GPIO int */
2199         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2200 
2201         switch (mode) {
2202         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2203                 DP(NETIF_MSG_LINK,
2204                    "Clear GPIO INT %d (shift %d) -> output low\n",
2205                    gpio_num, gpio_shift);
2206                 /* clear SET and set CLR */
2207                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2208                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2209                 break;
2210 
2211         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2212                 DP(NETIF_MSG_LINK,
2213                    "Set GPIO INT %d (shift %d) -> output high\n",
2214                    gpio_num, gpio_shift);
2215                 /* clear CLR and set SET */
2216                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2217                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2218                 break;
2219 
2220         default:
2221                 break;
2222         }
2223 
2224         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2225         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2226 
2227         return 0;
2228 }
2229 
2230 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2231 {
2232         u32 spio_reg;
2233 
2234         /* Only 2 SPIOs are configurable */
2235         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2236                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2237                 return -EINVAL;
2238         }
2239 
2240         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2241         /* read SPIO and mask except the float bits */
2242         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2243 
2244         switch (mode) {
2245         case MISC_SPIO_OUTPUT_LOW:
2246                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2247                 /* clear FLOAT and set CLR */
2248                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2249                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2250                 break;
2251 
2252         case MISC_SPIO_OUTPUT_HIGH:
2253                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2254                 /* clear FLOAT and set SET */
2255                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2256                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2257                 break;
2258 
2259         case MISC_SPIO_INPUT_HI_Z:
2260                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2261                 /* set FLOAT */
2262                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2263                 break;
2264 
2265         default:
2266                 break;
2267         }
2268 
2269         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2270         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2271 
2272         return 0;
2273 }
2274 
2275 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2276 {
2277         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2278         switch (bp->link_vars.ieee_fc &
2279                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2280         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2281                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2282                                                    ADVERTISED_Pause);
2283                 break;
2284 
2285         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2286                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2287                                                   ADVERTISED_Pause);
2288                 break;
2289 
2290         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2291                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2292                 break;
2293 
2294         default:
2295                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2296                                                    ADVERTISED_Pause);
2297                 break;
2298         }
2299 }
2300 
2301 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2302 {
2303         /* Initialize link parameters structure variables
2304          * It is recommended to turn off RX FC for jumbo frames
2305          *  for better performance
2306          */
2307         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2308                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2309         else
2310                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2311 }
2312 
2313 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2314 {
2315         u32 pause_enabled = 0;
2316 
2317         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2318                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2319                         pause_enabled = 1;
2320 
2321                 REG_WR(bp, BAR_USTRORM_INTMEM +
2322                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2323                        pause_enabled);
2324         }
2325 
2326         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2327            pause_enabled ? "enabled" : "disabled");
2328 }
2329 
2330 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2331 {
2332         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2333         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2334 
2335         if (!BP_NOMCP(bp)) {
2336                 bnx2x_set_requested_fc(bp);
2337                 bnx2x_acquire_phy_lock(bp);
2338 
2339                 if (load_mode == LOAD_DIAG) {
2340                         struct link_params *lp = &bp->link_params;
2341                         lp->loopback_mode = LOOPBACK_XGXS;
2342                         /* do PHY loopback at 10G speed, if possible */
2343                         if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2344                                 if (lp->speed_cap_mask[cfx_idx] &
2345                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2346                                         lp->req_line_speed[cfx_idx] =
2347                                         SPEED_10000;
2348                                 else
2349                                         lp->req_line_speed[cfx_idx] =
2350                                         SPEED_1000;
2351                         }
2352                 }
2353 
2354                 if (load_mode == LOAD_LOOPBACK_EXT) {
2355                         struct link_params *lp = &bp->link_params;
2356                         lp->loopback_mode = LOOPBACK_EXT;
2357                 }
2358 
2359                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2360 
2361                 bnx2x_release_phy_lock(bp);
2362 
2363                 bnx2x_init_dropless_fc(bp);
2364 
2365                 bnx2x_calc_fc_adv(bp);
2366 
2367                 if (bp->link_vars.link_up) {
2368                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2369                         bnx2x_link_report(bp);
2370                 }
2371                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2372                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2373                 return rc;
2374         }
2375         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2376         return -EINVAL;
2377 }
2378 
2379 void bnx2x_link_set(struct bnx2x *bp)
2380 {
2381         if (!BP_NOMCP(bp)) {
2382                 bnx2x_acquire_phy_lock(bp);
2383                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2384                 bnx2x_release_phy_lock(bp);
2385 
2386                 bnx2x_init_dropless_fc(bp);
2387 
2388                 bnx2x_calc_fc_adv(bp);
2389         } else
2390                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2391 }
2392 
2393 static void bnx2x__link_reset(struct bnx2x *bp)
2394 {
2395         if (!BP_NOMCP(bp)) {
2396                 bnx2x_acquire_phy_lock(bp);
2397                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2398                 bnx2x_release_phy_lock(bp);
2399         } else
2400                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2401 }
2402 
2403 void bnx2x_force_link_reset(struct bnx2x *bp)
2404 {
2405         bnx2x_acquire_phy_lock(bp);
2406         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2407         bnx2x_release_phy_lock(bp);
2408 }
2409 
2410 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2411 {
2412         u8 rc = 0;
2413 
2414         if (!BP_NOMCP(bp)) {
2415                 bnx2x_acquire_phy_lock(bp);
2416                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2417                                      is_serdes);
2418                 bnx2x_release_phy_lock(bp);
2419         } else
2420                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2421 
2422         return rc;
2423 }
2424 
2425 /* Calculates the sum of vn_min_rates.
2426    It's needed for further normalizing of the min_rates.
2427    Returns:
2428      sum of vn_min_rates.
2429        or
2430      0 - if all the min_rates are 0.
2431      In the later case fairness algorithm should be deactivated.
2432      If not all min_rates are zero then those that are zeroes will be set to 1.
2433  */
2434 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2435                                       struct cmng_init_input *input)
2436 {
2437         int all_zero = 1;
2438         int vn;
2439 
2440         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2441                 u32 vn_cfg = bp->mf_config[vn];
2442                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2443                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2444 
2445                 /* Skip hidden vns */
2446                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2447                         vn_min_rate = 0;
2448                 /* If min rate is zero - set it to 1 */
2449                 else if (!vn_min_rate)
2450                         vn_min_rate = DEF_MIN_RATE;
2451                 else
2452                         all_zero = 0;
2453 
2454                 input->vnic_min_rate[vn] = vn_min_rate;
2455         }
2456 
2457         /* if ETS or all min rates are zeros - disable fairness */
2458         if (BNX2X_IS_ETS_ENABLED(bp)) {
2459                 input->flags.cmng_enables &=
2460                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2461                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2462         } else if (all_zero) {
2463                 input->flags.cmng_enables &=
2464                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2465                 DP(NETIF_MSG_IFUP,
2466                    "All MIN values are zeroes fairness will be disabled\n");
2467         } else
2468                 input->flags.cmng_enables |=
2469                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2470 }
2471 
2472 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2473                                     struct cmng_init_input *input)
2474 {
2475         u16 vn_max_rate;
2476         u32 vn_cfg = bp->mf_config[vn];
2477 
2478         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2479                 vn_max_rate = 0;
2480         else {
2481                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2482 
2483                 if (IS_MF_SI(bp)) {
2484                         /* maxCfg in percents of linkspeed */
2485                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2486                 } else /* SD modes */
2487                         /* maxCfg is absolute in 100Mb units */
2488                         vn_max_rate = maxCfg * 100;
2489         }
2490 
2491         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2492 
2493         input->vnic_max_rate[vn] = vn_max_rate;
2494 }
2495 
2496 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2497 {
2498         if (CHIP_REV_IS_SLOW(bp))
2499                 return CMNG_FNS_NONE;
2500         if (IS_MF(bp))
2501                 return CMNG_FNS_MINMAX;
2502 
2503         return CMNG_FNS_NONE;
2504 }
2505 
2506 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2507 {
2508         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2509 
2510         if (BP_NOMCP(bp))
2511                 return; /* what should be the default value in this case */
2512 
2513         /* For 2 port configuration the absolute function number formula
2514          * is:
2515          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2516          *
2517          *      and there are 4 functions per port
2518          *
2519          * For 4 port configuration it is
2520          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2521          *
2522          *      and there are 2 functions per port
2523          */
2524         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2525                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2526 
2527                 if (func >= E1H_FUNC_MAX)
2528                         break;
2529 
2530                 bp->mf_config[vn] =
2531                         MF_CFG_RD(bp, func_mf_config[func].config);
2532         }
2533         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2534                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2535                 bp->flags |= MF_FUNC_DIS;
2536         } else {
2537                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2538                 bp->flags &= ~MF_FUNC_DIS;
2539         }
2540 }
2541 
2542 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2543 {
2544         struct cmng_init_input input;
2545         memset(&input, 0, sizeof(struct cmng_init_input));
2546 
2547         input.port_rate = bp->link_vars.line_speed;
2548 
2549         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2550                 int vn;
2551 
2552                 /* read mf conf from shmem */
2553                 if (read_cfg)
2554                         bnx2x_read_mf_cfg(bp);
2555 
2556                 /* vn_weight_sum and enable fairness if not 0 */
2557                 bnx2x_calc_vn_min(bp, &input);
2558 
2559                 /* calculate and set min-max rate for each vn */
2560                 if (bp->port.pmf)
2561                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2562                                 bnx2x_calc_vn_max(bp, vn, &input);
2563 
2564                 /* always enable rate shaping and fairness */
2565                 input.flags.cmng_enables |=
2566                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2567 
2568                 bnx2x_init_cmng(&input, &bp->cmng);
2569                 return;
2570         }
2571 
2572         /* rate shaping and fairness are disabled */
2573         DP(NETIF_MSG_IFUP,
2574            "rate shaping and fairness are disabled\n");
2575 }
2576 
2577 static void storm_memset_cmng(struct bnx2x *bp,
2578                               struct cmng_init *cmng,
2579                               u8 port)
2580 {
2581         int vn;
2582         size_t size = sizeof(struct cmng_struct_per_port);
2583 
2584         u32 addr = BAR_XSTRORM_INTMEM +
2585                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2586 
2587         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2588 
2589         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2590                 int func = func_by_vn(bp, vn);
2591 
2592                 addr = BAR_XSTRORM_INTMEM +
2593                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2594                 size = sizeof(struct rate_shaping_vars_per_vn);
2595                 __storm_memset_struct(bp, addr, size,
2596                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2597 
2598                 addr = BAR_XSTRORM_INTMEM +
2599                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2600                 size = sizeof(struct fairness_vars_per_vn);
2601                 __storm_memset_struct(bp, addr, size,
2602                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2603         }
2604 }
2605 
2606 /* init cmng mode in HW according to local configuration */
2607 void bnx2x_set_local_cmng(struct bnx2x *bp)
2608 {
2609         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2610 
2611         if (cmng_fns != CMNG_FNS_NONE) {
2612                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2613                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2614         } else {
2615                 /* rate shaping and fairness are disabled */
2616                 DP(NETIF_MSG_IFUP,
2617                    "single function mode without fairness\n");
2618         }
2619 }
2620 
2621 /* This function is called upon link interrupt */
2622 static void bnx2x_link_attn(struct bnx2x *bp)
2623 {
2624         /* Make sure that we are synced with the current statistics */
2625         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2626 
2627         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2628 
2629         bnx2x_init_dropless_fc(bp);
2630 
2631         if (bp->link_vars.link_up) {
2632 
2633                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2634                         struct host_port_stats *pstats;
2635 
2636                         pstats = bnx2x_sp(bp, port_stats);
2637                         /* reset old mac stats */
2638                         memset(&(pstats->mac_stx[0]), 0,
2639                                sizeof(struct mac_stx));
2640                 }
2641                 if (bp->state == BNX2X_STATE_OPEN)
2642                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2643         }
2644 
2645         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2646                 bnx2x_set_local_cmng(bp);
2647 
2648         __bnx2x_link_report(bp);
2649 
2650         if (IS_MF(bp))
2651                 bnx2x_link_sync_notify(bp);
2652 }
2653 
2654 void bnx2x__link_status_update(struct bnx2x *bp)
2655 {
2656         if (bp->state != BNX2X_STATE_OPEN)
2657                 return;
2658 
2659         /* read updated dcb configuration */
2660         if (IS_PF(bp)) {
2661                 bnx2x_dcbx_pmf_update(bp);
2662                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2663                 if (bp->link_vars.link_up)
2664                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2665                 else
2666                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2667                         /* indicate link status */
2668                 bnx2x_link_report(bp);
2669 
2670         } else { /* VF */
2671                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2672                                           SUPPORTED_10baseT_Full |
2673                                           SUPPORTED_100baseT_Half |
2674                                           SUPPORTED_100baseT_Full |
2675                                           SUPPORTED_1000baseT_Full |
2676                                           SUPPORTED_2500baseX_Full |
2677                                           SUPPORTED_10000baseT_Full |
2678                                           SUPPORTED_TP |
2679                                           SUPPORTED_FIBRE |
2680                                           SUPPORTED_Autoneg |
2681                                           SUPPORTED_Pause |
2682                                           SUPPORTED_Asym_Pause);
2683                 bp->port.advertising[0] = bp->port.supported[0];
2684 
2685                 bp->link_params.bp = bp;
2686                 bp->link_params.port = BP_PORT(bp);
2687                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2688                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2689                 bp->link_params.req_line_speed[0] = SPEED_10000;
2690                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2691                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2692                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2693                 bp->link_vars.line_speed = SPEED_10000;
2694                 bp->link_vars.link_status =
2695                         (LINK_STATUS_LINK_UP |
2696                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2697                 bp->link_vars.link_up = 1;
2698                 bp->link_vars.duplex = DUPLEX_FULL;
2699                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2700                 __bnx2x_link_report(bp);
2701 
2702                 bnx2x_sample_bulletin(bp);
2703 
2704                 /* if bulletin board did not have an update for link status
2705                  * __bnx2x_link_report will report current status
2706                  * but it will NOT duplicate report in case of already reported
2707                  * during sampling bulletin board.
2708                  */
2709                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2710         }
2711 }
2712 
2713 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2714                                   u16 vlan_val, u8 allowed_prio)
2715 {
2716         struct bnx2x_func_state_params func_params = {NULL};
2717         struct bnx2x_func_afex_update_params *f_update_params =
2718                 &func_params.params.afex_update;
2719 
2720         func_params.f_obj = &bp->func_obj;
2721         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2722 
2723         /* no need to wait for RAMROD completion, so don't
2724          * set RAMROD_COMP_WAIT flag
2725          */
2726 
2727         f_update_params->vif_id = vifid;
2728         f_update_params->afex_default_vlan = vlan_val;
2729         f_update_params->allowed_priorities = allowed_prio;
2730 
2731         /* if ramrod can not be sent, response to MCP immediately */
2732         if (bnx2x_func_state_change(bp, &func_params) < 0)
2733                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2734 
2735         return 0;
2736 }
2737 
2738 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2739                                           u16 vif_index, u8 func_bit_map)
2740 {
2741         struct bnx2x_func_state_params func_params = {NULL};
2742         struct bnx2x_func_afex_viflists_params *update_params =
2743                 &func_params.params.afex_viflists;
2744         int rc;
2745         u32 drv_msg_code;
2746 
2747         /* validate only LIST_SET and LIST_GET are received from switch */
2748         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2749                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2750                           cmd_type);
2751 
2752         func_params.f_obj = &bp->func_obj;
2753         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2754 
2755         /* set parameters according to cmd_type */
2756         update_params->afex_vif_list_command = cmd_type;
2757         update_params->vif_list_index = vif_index;
2758         update_params->func_bit_map =
2759                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2760         update_params->func_to_clear = 0;
2761         drv_msg_code =
2762                 (cmd_type == VIF_LIST_RULE_GET) ?
2763                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2764                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2765 
2766         /* if ramrod can not be sent, respond to MCP immediately for
2767          * SET and GET requests (other are not triggered from MCP)
2768          */
2769         rc = bnx2x_func_state_change(bp, &func_params);
2770         if (rc < 0)
2771                 bnx2x_fw_command(bp, drv_msg_code, 0);
2772 
2773         return 0;
2774 }
2775 
2776 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2777 {
2778         struct afex_stats afex_stats;
2779         u32 func = BP_ABS_FUNC(bp);
2780         u32 mf_config;
2781         u16 vlan_val;
2782         u32 vlan_prio;
2783         u16 vif_id;
2784         u8 allowed_prio;
2785         u8 vlan_mode;
2786         u32 addr_to_write, vifid, addrs, stats_type, i;
2787 
2788         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2789                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2790                 DP(BNX2X_MSG_MCP,
2791                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2792                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2793         }
2794 
2795         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2796                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2797                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2798                 DP(BNX2X_MSG_MCP,
2799                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2800                    vifid, addrs);
2801                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2802                                                addrs);
2803         }
2804 
2805         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2806                 addr_to_write = SHMEM2_RD(bp,
2807                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2808                 stats_type = SHMEM2_RD(bp,
2809                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2810 
2811                 DP(BNX2X_MSG_MCP,
2812                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2813                    addr_to_write);
2814 
2815                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2816 
2817                 /* write response to scratchpad, for MCP */
2818                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2819                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2820                                *(((u32 *)(&afex_stats))+i));
2821 
2822                 /* send ack message to MCP */
2823                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2824         }
2825 
2826         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2827                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2828                 bp->mf_config[BP_VN(bp)] = mf_config;
2829                 DP(BNX2X_MSG_MCP,
2830                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2831                    mf_config);
2832 
2833                 /* if VIF_SET is "enabled" */
2834                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2835                         /* set rate limit directly to internal RAM */
2836                         struct cmng_init_input cmng_input;
2837                         struct rate_shaping_vars_per_vn m_rs_vn;
2838                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2839                         u32 addr = BAR_XSTRORM_INTMEM +
2840                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2841 
2842                         bp->mf_config[BP_VN(bp)] = mf_config;
2843 
2844                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2845                         m_rs_vn.vn_counter.rate =
2846                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2847                         m_rs_vn.vn_counter.quota =
2848                                 (m_rs_vn.vn_counter.rate *
2849                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2850 
2851                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2852 
2853                         /* read relevant values from mf_cfg struct in shmem */
2854                         vif_id =
2855                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2856                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2857                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2858                         vlan_val =
2859                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2860                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2861                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2862                         vlan_prio = (mf_config &
2863                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2864                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2865                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2866                         vlan_mode =
2867                                 (MF_CFG_RD(bp,
2868                                            func_mf_config[func].afex_config) &
2869                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2870                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2871                         allowed_prio =
2872                                 (MF_CFG_RD(bp,
2873                                            func_mf_config[func].afex_config) &
2874                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2875                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2876 
2877                         /* send ramrod to FW, return in case of failure */
2878                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2879                                                    allowed_prio))
2880                                 return;
2881 
2882                         bp->afex_def_vlan_tag = vlan_val;
2883                         bp->afex_vlan_mode = vlan_mode;
2884                 } else {
2885                         /* notify link down because BP->flags is disabled */
2886                         bnx2x_link_report(bp);
2887 
2888                         /* send INVALID VIF ramrod to FW */
2889                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2890 
2891                         /* Reset the default afex VLAN */
2892                         bp->afex_def_vlan_tag = -1;
2893                 }
2894         }
2895 }
2896 
2897 static void bnx2x_pmf_update(struct bnx2x *bp)
2898 {
2899         int port = BP_PORT(bp);
2900         u32 val;
2901 
2902         bp->port.pmf = 1;
2903         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2904 
2905         /*
2906          * We need the mb() to ensure the ordering between the writing to
2907          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2908          */
2909         smp_mb();
2910 
2911         /* queue a periodic task */
2912         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2913 
2914         bnx2x_dcbx_pmf_update(bp);
2915 
2916         /* enable nig attention */
2917         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2918         if (bp->common.int_block == INT_BLOCK_HC) {
2919                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2920                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2921         } else if (!CHIP_IS_E1x(bp)) {
2922                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2923                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2924         }
2925 
2926         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2927 }
2928 
2929 /* end of Link */
2930 
2931 /* slow path */
2932 
2933 /*
2934  * General service functions
2935  */
2936 
2937 /* send the MCP a request, block until there is a reply */
2938 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2939 {
2940         int mb_idx = BP_FW_MB_IDX(bp);
2941         u32 seq;
2942         u32 rc = 0;
2943         u32 cnt = 1;
2944         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2945 
2946         mutex_lock(&bp->fw_mb_mutex);
2947         seq = ++bp->fw_seq;
2948         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2949         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2950 
2951         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2952                         (command | seq), param);
2953 
2954         do {
2955                 /* let the FW do it's magic ... */
2956                 msleep(delay);
2957 
2958                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2959 
2960                 /* Give the FW up to 5 second (500*10ms) */
2961         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2962 
2963         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2964            cnt*delay, rc, seq);
2965 
2966         /* is this a reply to our command? */
2967         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2968                 rc &= FW_MSG_CODE_MASK;
2969         else {
2970                 /* FW BUG! */
2971                 BNX2X_ERR("FW failed to respond!\n");
2972                 bnx2x_fw_dump(bp);
2973                 rc = 0;
2974         }
2975         mutex_unlock(&bp->fw_mb_mutex);
2976 
2977         return rc;
2978 }
2979 
2980 static void storm_memset_func_cfg(struct bnx2x *bp,
2981                                  struct tstorm_eth_function_common_config *tcfg,
2982                                  u16 abs_fid)
2983 {
2984         size_t size = sizeof(struct tstorm_eth_function_common_config);
2985 
2986         u32 addr = BAR_TSTRORM_INTMEM +
2987                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2988 
2989         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2990 }
2991 
2992 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2993 {
2994         if (CHIP_IS_E1x(bp)) {
2995                 struct tstorm_eth_function_common_config tcfg = {0};
2996 
2997                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2998         }
2999 
3000         /* Enable the function in the FW */
3001         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3002         storm_memset_func_en(bp, p->func_id, 1);
3003 
3004         /* spq */
3005         if (p->func_flgs & FUNC_FLG_SPQ) {
3006                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3007                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3008                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3009         }
3010 }
3011 
3012 /**
3013  * bnx2x_get_common_flags - Return common flags
3014  *
3015  * @bp          device handle
3016  * @fp          queue handle
3017  * @zero_stats  TRUE if statistics zeroing is needed
3018  *
3019  * Return the flags that are common for the Tx-only and not normal connections.
3020  */
3021 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3022                                             struct bnx2x_fastpath *fp,
3023                                             bool zero_stats)
3024 {
3025         unsigned long flags = 0;
3026 
3027         /* PF driver will always initialize the Queue to an ACTIVE state */
3028         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3029 
3030         /* tx only connections collect statistics (on the same index as the
3031          * parent connection). The statistics are zeroed when the parent
3032          * connection is initialized.
3033          */
3034 
3035         __set_bit(BNX2X_Q_FLG_STATS, &flags);
3036         if (zero_stats)
3037                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3038 
3039         if (bp->flags & TX_SWITCHING)
3040                 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3041 
3042         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3043         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3044 
3045 #ifdef BNX2X_STOP_ON_ERROR
3046         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3047 #endif
3048 
3049         return flags;
3050 }
3051 
3052 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3053                                        struct bnx2x_fastpath *fp,
3054                                        bool leading)
3055 {
3056         unsigned long flags = 0;
3057 
3058         /* calculate other queue flags */
3059         if (IS_MF_SD(bp))
3060                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3061 
3062         if (IS_FCOE_FP(fp)) {
3063                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3064                 /* For FCoE - force usage of default priority (for afex) */
3065                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3066         }
3067 
3068         if (!fp->disable_tpa) {
3069                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3070                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3071                 if (fp->mode == TPA_MODE_GRO)
3072                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3073         }
3074 
3075         if (leading) {
3076                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3077                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3078         }
3079 
3080         /* Always set HW VLAN stripping */
3081         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3082 
3083         /* configure silent vlan removal */
3084         if (IS_MF_AFEX(bp))
3085                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3086 
3087         return flags | bnx2x_get_common_flags(bp, fp, true);
3088 }
3089 
3090 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3091         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3092         u8 cos)
3093 {
3094         gen_init->stat_id = bnx2x_stats_id(fp);
3095         gen_init->spcl_id = fp->cl_id;
3096 
3097         /* Always use mini-jumbo MTU for FCoE L2 ring */
3098         if (IS_FCOE_FP(fp))
3099                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3100         else
3101                 gen_init->mtu = bp->dev->mtu;
3102 
3103         gen_init->cos = cos;
3104 }
3105 
3106 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3107         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3108         struct bnx2x_rxq_setup_params *rxq_init)
3109 {
3110         u8 max_sge = 0;
3111         u16 sge_sz = 0;
3112         u16 tpa_agg_size = 0;
3113 
3114         if (!fp->disable_tpa) {
3115                 pause->sge_th_lo = SGE_TH_LO(bp);
3116                 pause->sge_th_hi = SGE_TH_HI(bp);
3117 
3118                 /* validate SGE ring has enough to cross high threshold */
3119                 WARN_ON(bp->dropless_fc &&
3120                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3121                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3122 
3123                 tpa_agg_size = TPA_AGG_SIZE;
3124                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3125                         SGE_PAGE_SHIFT;
3126                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3127                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3128                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3129         }
3130 
3131         /* pause - not for e1 */
3132         if (!CHIP_IS_E1(bp)) {
3133                 pause->bd_th_lo = BD_TH_LO(bp);
3134                 pause->bd_th_hi = BD_TH_HI(bp);
3135 
3136                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3137                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3138                 /*
3139                  * validate that rings have enough entries to cross
3140                  * high thresholds
3141                  */
3142                 WARN_ON(bp->dropless_fc &&
3143                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3144                                 bp->rx_ring_size);
3145                 WARN_ON(bp->dropless_fc &&
3146                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3147                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3148 
3149                 pause->pri_map = 1;
3150         }
3151 
3152         /* rxq setup */
3153         rxq_init->dscr_map = fp->rx_desc_mapping;
3154         rxq_init->sge_map = fp->rx_sge_mapping;
3155         rxq_init->rcq_map = fp->rx_comp_mapping;
3156         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3157 
3158         /* This should be a maximum number of data bytes that may be
3159          * placed on the BD (not including paddings).
3160          */
3161         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3162                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3163 
3164         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3165         rxq_init->tpa_agg_sz = tpa_agg_size;
3166         rxq_init->sge_buf_sz = sge_sz;
3167         rxq_init->max_sges_pkt = max_sge;
3168         rxq_init->rss_engine_id = BP_FUNC(bp);
3169         rxq_init->mcast_engine_id = BP_FUNC(bp);
3170 
3171         /* Maximum number or simultaneous TPA aggregation for this Queue.
3172          *
3173          * For PF Clients it should be the maximum available number.
3174          * VF driver(s) may want to define it to a smaller value.
3175          */
3176         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3177 
3178         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3179         rxq_init->fw_sb_id = fp->fw_sb_id;
3180 
3181         if (IS_FCOE_FP(fp))
3182                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3183         else
3184                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3185         /* configure silent vlan removal
3186          * if multi function mode is afex, then mask default vlan
3187          */
3188         if (IS_MF_AFEX(bp)) {
3189                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3190                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3191         }
3192 }
3193 
3194 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3195         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3196         u8 cos)
3197 {
3198         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3199         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3200         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3201         txq_init->fw_sb_id = fp->fw_sb_id;
3202 
3203         /*
3204          * set the tss leading client id for TX classification ==
3205          * leading RSS client id
3206          */
3207         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3208 
3209         if (IS_FCOE_FP(fp)) {
3210                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3211                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3212         }
3213 }
3214 
3215 static void bnx2x_pf_init(struct bnx2x *bp)
3216 {
3217         struct bnx2x_func_init_params func_init = {0};
3218         struct event_ring_data eq_data = { {0} };
3219         u16 flags;
3220 
3221         if (!CHIP_IS_E1x(bp)) {
3222                 /* reset IGU PF statistics: MSIX + ATTN */
3223                 /* PF */
3224                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3225                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3226                            (CHIP_MODE_IS_4_PORT(bp) ?
3227                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3228                 /* ATTN */
3229                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3230                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3231                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3232                            (CHIP_MODE_IS_4_PORT(bp) ?
3233                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3234         }
3235 
3236         /* function setup flags */
3237         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3238 
3239         /* This flag is relevant for E1x only.
3240          * E2 doesn't have a TPA configuration in a function level.
3241          */
3242         flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3243 
3244         func_init.func_flgs = flags;
3245         func_init.pf_id = BP_FUNC(bp);
3246         func_init.func_id = BP_FUNC(bp);
3247         func_init.spq_map = bp->spq_mapping;
3248         func_init.spq_prod = bp->spq_prod_idx;
3249 
3250         bnx2x_func_init(bp, &func_init);
3251 
3252         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3253 
3254         /*
3255          * Congestion management values depend on the link rate
3256          * There is no active link so initial link rate is set to 10 Gbps.
3257          * When the link comes up The congestion management values are
3258          * re-calculated according to the actual link rate.
3259          */
3260         bp->link_vars.line_speed = SPEED_10000;
3261         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3262 
3263         /* Only the PMF sets the HW */
3264         if (bp->port.pmf)
3265                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3266 
3267         /* init Event Queue - PCI bus guarantees correct endianity*/
3268         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3269         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3270         eq_data.producer = bp->eq_prod;
3271         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3272         eq_data.sb_id = DEF_SB_ID;
3273         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3274 }
3275 
3276 static void bnx2x_e1h_disable(struct bnx2x *bp)
3277 {
3278         int port = BP_PORT(bp);
3279 
3280         bnx2x_tx_disable(bp);
3281 
3282         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3283 }
3284 
3285 static void bnx2x_e1h_enable(struct bnx2x *bp)
3286 {
3287         int port = BP_PORT(bp);
3288 
3289         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3290 
3291         /* Tx queue should be only re-enabled */
3292         netif_tx_wake_all_queues(bp->dev);
3293 
3294         /*
3295          * Should not call netif_carrier_on since it will be called if the link
3296          * is up when checking for link state
3297          */
3298 }
3299 
3300 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3301 
3302 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3303 {
3304         struct eth_stats_info *ether_stat =
3305                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3306         struct bnx2x_vlan_mac_obj *mac_obj =
3307                 &bp->sp_objs->mac_obj;
3308         int i;
3309 
3310         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3311                 ETH_STAT_INFO_VERSION_LEN);
3312 
3313         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3314          * mac_local field in ether_stat struct. The base address is offset by 2
3315          * bytes to account for the field being 8 bytes but a mac address is
3316          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3317          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3318          * allocated by the ether_stat struct, so the macs will land in their
3319          * proper positions.
3320          */
3321         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3322                 memset(ether_stat->mac_local + i, 0,
3323                        sizeof(ether_stat->mac_local[0]));
3324         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3325                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3326                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3327                                 ETH_ALEN);
3328         ether_stat->mtu_size = bp->dev->mtu;
3329         if (bp->dev->features & NETIF_F_RXCSUM)
3330                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3331         if (bp->dev->features & NETIF_F_TSO)
3332                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3333         ether_stat->feature_flags |= bp->common.boot_mode;
3334 
3335         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3336 
3337         ether_stat->txq_size = bp->tx_ring_size;
3338         ether_stat->rxq_size = bp->rx_ring_size;
3339 
3340 #ifdef CONFIG_BNX2X_SRIOV
3341         ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3342 #endif
3343 }
3344 
3345 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3346 {
3347         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3348         struct fcoe_stats_info *fcoe_stat =
3349                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3350 
3351         if (!CNIC_LOADED(bp))
3352                 return;
3353 
3354         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3355 
3356         fcoe_stat->qos_priority =
3357                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3358 
3359         /* insert FCoE stats from ramrod response */
3360         if (!NO_FCOE(bp)) {
3361                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3362                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3363                         tstorm_queue_statistics;
3364 
3365                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3366                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3367                         xstorm_queue_statistics;
3368 
3369                 struct fcoe_statistics_params *fw_fcoe_stat =
3370                         &bp->fw_stats_data->fcoe;
3371 
3372                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3373                           fcoe_stat->rx_bytes_lo,
3374                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3375 
3376                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3377                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3378                           fcoe_stat->rx_bytes_lo,
3379                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3380 
3381                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3382                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3383                           fcoe_stat->rx_bytes_lo,
3384                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3385 
3386                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3387                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3388                           fcoe_stat->rx_bytes_lo,
3389                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3390 
3391                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3392                           fcoe_stat->rx_frames_lo,
3393                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3394 
3395                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3396                           fcoe_stat->rx_frames_lo,
3397                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3398 
3399                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3400                           fcoe_stat->rx_frames_lo,
3401                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3402 
3403                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3404                           fcoe_stat->rx_frames_lo,
3405                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3406 
3407                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3408                           fcoe_stat->tx_bytes_lo,
3409                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3410 
3411                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3412                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3413                           fcoe_stat->tx_bytes_lo,
3414                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3415 
3416                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3417                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3418                           fcoe_stat->tx_bytes_lo,
3419                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3420 
3421                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3422                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3423                           fcoe_stat->tx_bytes_lo,
3424                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3425 
3426                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3427                           fcoe_stat->tx_frames_lo,
3428                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3429 
3430                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3431                           fcoe_stat->tx_frames_lo,
3432                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3433 
3434                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3435                           fcoe_stat->tx_frames_lo,
3436                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3437 
3438                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3439                           fcoe_stat->tx_frames_lo,
3440                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3441         }
3442 
3443         /* ask L5 driver to add data to the struct */
3444         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3445 }
3446 
3447 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3448 {
3449         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3450         struct iscsi_stats_info *iscsi_stat =
3451                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3452 
3453         if (!CNIC_LOADED(bp))
3454                 return;
3455 
3456         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3457                ETH_ALEN);
3458 
3459         iscsi_stat->qos_priority =
3460                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3461 
3462         /* ask L5 driver to add data to the struct */
3463         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3464 }
3465 
3466 /* called due to MCP event (on pmf):
3467  *      reread new bandwidth configuration
3468  *      configure FW
3469  *      notify others function about the change
3470  */
3471 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3472 {
3473         if (bp->link_vars.link_up) {
3474                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3475                 bnx2x_link_sync_notify(bp);
3476         }
3477         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3478 }
3479 
3480 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3481 {
3482         bnx2x_config_mf_bw(bp);
3483         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3484 }
3485 
3486 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3487 {
3488         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3489         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3490 }
3491 
3492 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH        (20)
3493 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT         (25)
3494 
3495 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3496 {
3497         enum drv_info_opcode op_code;
3498         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3499         bool release = false;
3500         int wait;
3501 
3502         /* if drv_info version supported by MFW doesn't match - send NACK */
3503         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3504                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3505                 return;
3506         }
3507 
3508         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3509                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3510 
3511         /* Must prevent other flows from accessing drv_info_to_mcp */
3512         mutex_lock(&bp->drv_info_mutex);
3513 
3514         memset(&bp->slowpath->drv_info_to_mcp, 0,
3515                sizeof(union drv_info_to_mcp));
3516 
3517         switch (op_code) {
3518         case ETH_STATS_OPCODE:
3519                 bnx2x_drv_info_ether_stat(bp);
3520                 break;
3521         case FCOE_STATS_OPCODE:
3522                 bnx2x_drv_info_fcoe_stat(bp);
3523                 break;
3524         case ISCSI_STATS_OPCODE:
3525                 bnx2x_drv_info_iscsi_stat(bp);
3526                 break;
3527         default:
3528                 /* if op code isn't supported - send NACK */
3529                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3530                 goto out;
3531         }
3532 
3533         /* if we got drv_info attn from MFW then these fields are defined in
3534          * shmem2 for sure
3535          */
3536         SHMEM2_WR(bp, drv_info_host_addr_lo,
3537                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3538         SHMEM2_WR(bp, drv_info_host_addr_hi,
3539                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3540 
3541         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3542 
3543         /* Since possible management wants both this and get_driver_version
3544          * need to wait until management notifies us it finished utilizing
3545          * the buffer.
3546          */
3547         if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3548                 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3549         } else if (!bp->drv_info_mng_owner) {
3550                 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3551 
3552                 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3553                         u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3554 
3555                         /* Management is done; need to clear indication */
3556                         if (indication & bit) {
3557                                 SHMEM2_WR(bp, mfw_drv_indication,
3558                                           indication & ~bit);
3559                                 release = true;
3560                                 break;
3561                         }
3562 
3563                         msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3564                 }
3565         }
3566         if (!release) {
3567                 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3568                 bp->drv_info_mng_owner = true;
3569         }
3570 
3571 out:
3572         mutex_unlock(&bp->drv_info_mutex);
3573 }
3574 
3575 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3576 {
3577         u8 vals[4];
3578         int i = 0;
3579 
3580         if (bnx2x_format) {
3581                 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3582                            &vals[0], &vals[1], &vals[2], &vals[3]);
3583                 if (i > 0)
3584                         vals[0] -= '';
3585         } else {
3586                 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3587                            &vals[0], &vals[1], &vals[2], &vals[3]);
3588         }
3589 
3590         while (i < 4)
3591                 vals[i++] = 0;
3592 
3593         return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3594 }
3595 
3596 void bnx2x_update_mng_version(struct bnx2x *bp)
3597 {
3598         u32 iscsiver = DRV_VER_NOT_LOADED;
3599         u32 fcoever = DRV_VER_NOT_LOADED;
3600         u32 ethver = DRV_VER_NOT_LOADED;
3601         int idx = BP_FW_MB_IDX(bp);
3602         u8 *version;
3603 
3604         if (!SHMEM2_HAS(bp, func_os_drv_ver))
3605                 return;
3606 
3607         mutex_lock(&bp->drv_info_mutex);
3608         /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3609         if (bp->drv_info_mng_owner)
3610                 goto out;
3611 
3612         if (bp->state != BNX2X_STATE_OPEN)
3613                 goto out;
3614 
3615         /* Parse ethernet driver version */
3616         ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3617         if (!CNIC_LOADED(bp))
3618                 goto out;
3619 
3620         /* Try getting storage driver version via cnic */
3621         memset(&bp->slowpath->drv_info_to_mcp, 0,
3622                sizeof(union drv_info_to_mcp));
3623         bnx2x_drv_info_iscsi_stat(bp);
3624         version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3625         iscsiver = bnx2x_update_mng_version_utility(version, false);
3626 
3627         memset(&bp->slowpath->drv_info_to_mcp, 0,
3628                sizeof(union drv_info_to_mcp));
3629         bnx2x_drv_info_fcoe_stat(bp);
3630         version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3631         fcoever = bnx2x_update_mng_version_utility(version, false);
3632 
3633 out:
3634         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3635         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3636         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3637 
3638         mutex_unlock(&bp->drv_info_mutex);
3639 
3640         DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3641            ethver, iscsiver, fcoever);
3642 }
3643 
3644 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3645 {
3646         DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3647 
3648         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3649 
3650                 /*
3651                  * This is the only place besides the function initialization
3652                  * where the bp->flags can change so it is done without any
3653                  * locks
3654                  */
3655                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3656                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3657                         bp->flags |= MF_FUNC_DIS;
3658 
3659                         bnx2x_e1h_disable(bp);
3660                 } else {
3661                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3662                         bp->flags &= ~MF_FUNC_DIS;
3663 
3664                         bnx2x_e1h_enable(bp);
3665                 }
3666                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3667         }
3668         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3669                 bnx2x_config_mf_bw(bp);
3670                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3671         }
3672 
3673         /* Report results to MCP */
3674         if (dcc_event)
3675                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3676         else
3677                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3678 }
3679 
3680 /* must be called under the spq lock */
3681 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3682 {
3683         struct eth_spe *next_spe = bp->spq_prod_bd;
3684 
3685         if (bp->spq_prod_bd == bp->spq_last_bd) {
3686                 bp->spq_prod_bd = bp->spq;
3687                 bp->spq_prod_idx = 0;
3688                 DP(BNX2X_MSG_SP, "end of spq\n");
3689         } else {
3690                 bp->spq_prod_bd++;
3691                 bp->spq_prod_idx++;
3692         }
3693         return next_spe;
3694 }
3695 
3696 /* must be called under the spq lock */
3697 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3698 {
3699         int func = BP_FUNC(bp);
3700 
3701         /*
3702          * Make sure that BD data is updated before writing the producer:
3703          * BD data is written to the memory, the producer is read from the
3704          * memory, thus we need a full memory barrier to ensure the ordering.
3705          */
3706         mb();
3707 
3708         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3709                  bp->spq_prod_idx);
3710         mmiowb();
3711 }
3712 
3713 /**
3714  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3715  *
3716  * @cmd:        command to check
3717  * @cmd_type:   command type
3718  */
3719 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3720 {
3721         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3722             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3723             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3724             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3725             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3726             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3727             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3728                 return true;
3729         else
3730                 return false;
3731 }
3732 
3733 /**
3734  * bnx2x_sp_post - place a single command on an SP ring
3735  *
3736  * @bp:         driver handle
3737  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3738  * @cid:        SW CID the command is related to
3739  * @data_hi:    command private data address (high 32 bits)
3740  * @data_lo:    command private data address (low 32 bits)
3741  * @cmd_type:   command type (e.g. NONE, ETH)
3742  *
3743  * SP data is handled as if it's always an address pair, thus data fields are
3744  * not swapped to little endian in upper functions. Instead this function swaps
3745  * data as if it's two u32 fields.
3746  */
3747 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3748                   u32 data_hi, u32 data_lo, int cmd_type)
3749 {
3750         struct eth_spe *spe;
3751         u16 type;
3752         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3753 
3754 #ifdef BNX2X_STOP_ON_ERROR
3755         if (unlikely(bp->panic)) {
3756                 BNX2X_ERR("Can't post SP when there is panic\n");
3757                 return -EIO;
3758         }
3759 #endif
3760 
3761         spin_lock_bh(&bp->spq_lock);
3762 
3763         if (common) {
3764                 if (!atomic_read(&bp->eq_spq_left)) {
3765                         BNX2X_ERR("BUG! EQ ring full!\n");
3766                         spin_unlock_bh(&bp->spq_lock);
3767                         bnx2x_panic();
3768                         return -EBUSY;
3769                 }
3770         } else if (!atomic_read(&bp->cq_spq_left)) {
3771                         BNX2X_ERR("BUG! SPQ ring full!\n");
3772                         spin_unlock_bh(&bp->spq_lock);
3773                         bnx2x_panic();
3774                         return -EBUSY;
3775         }
3776 
3777         spe = bnx2x_sp_get_next(bp);
3778 
3779         /* CID needs port number to be encoded int it */
3780         spe->hdr.conn_and_cmd_data =
3781                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3782                                     HW_CID(bp, cid));
3783 
3784         /* In some cases, type may already contain the func-id
3785          * mainly in SRIOV related use cases, so we add it here only
3786          * if it's not already set.
3787          */
3788         if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3789                 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3790                         SPE_HDR_CONN_TYPE;
3791                 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3792                          SPE_HDR_FUNCTION_ID);
3793         } else {
3794                 type = cmd_type;
3795         }
3796 
3797         spe->hdr.type = cpu_to_le16(type);
3798 
3799         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3800         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3801 
3802         /*
3803          * It's ok if the actual decrement is issued towards the memory
3804          * somewhere between the spin_lock and spin_unlock. Thus no
3805          * more explicit memory barrier is needed.
3806          */
3807         if (common)
3808                 atomic_dec(&bp->eq_spq_left);
3809         else
3810                 atomic_dec(&bp->cq_spq_left);
3811 
3812         DP(BNX2X_MSG_SP,
3813            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3814            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3815            (u32)(U64_LO(bp->spq_mapping) +
3816            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3817            HW_CID(bp, cid), data_hi, data_lo, type,
3818            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3819 
3820         bnx2x_sp_prod_update(bp);
3821         spin_unlock_bh(&bp->spq_lock);
3822         return 0;
3823 }
3824 
3825 /* acquire split MCP access lock register */
3826 static int bnx2x_acquire_alr(struct bnx2x *bp)
3827 {
3828         u32 j, val;
3829         int rc = 0;
3830 
3831         might_sleep();
3832         for (j = 0; j < 1000; j++) {
3833                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3834                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3835                 if (val & MCPR_ACCESS_LOCK_LOCK)
3836                         break;
3837 
3838                 usleep_range(5000, 10000);
3839         }
3840         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3841                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3842                 rc = -EBUSY;
3843         }
3844 
3845         return rc;
3846 }
3847 
3848 /* release split MCP access lock register */
3849 static void bnx2x_release_alr(struct bnx2x *bp)
3850 {
3851         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3852 }
3853 
3854 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3855 #define BNX2X_DEF_SB_IDX        0x0002
3856 
3857 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3858 {
3859         struct host_sp_status_block *def_sb = bp->def_status_blk;
3860         u16 rc = 0;
3861 
3862         barrier(); /* status block is written to by the chip */
3863         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3864                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3865                 rc |= BNX2X_DEF_SB_ATT_IDX;
3866         }
3867 
3868         if (bp->def_idx != def_sb->sp_sb.running_index) {
3869                 bp->def_idx = def_sb->sp_sb.running_index;
3870                 rc |= BNX2X_DEF_SB_IDX;
3871         }
3872 
3873         /* Do not reorder: indices reading should complete before handling */
3874         barrier();
3875         return rc;
3876 }
3877 
3878 /*
3879  * slow path service functions
3880  */
3881 
3882 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3883 {
3884         int port = BP_PORT(bp);
3885         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3886                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3887         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3888                                        NIG_REG_MASK_INTERRUPT_PORT0;
3889         u32 aeu_mask;
3890         u32 nig_mask = 0;
3891         u32 reg_addr;
3892 
3893         if (bp->attn_state & asserted)
3894                 BNX2X_ERR("IGU ERROR\n");
3895 
3896         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3897         aeu_mask = REG_RD(bp, aeu_addr);
3898 
3899         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
3900            aeu_mask, asserted);
3901         aeu_mask &= ~(asserted & 0x3ff);
3902         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3903 
3904         REG_WR(bp, aeu_addr, aeu_mask);
3905         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3906 
3907         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3908         bp->attn_state |= asserted;
3909         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3910 
3911         if (asserted & ATTN_HARD_WIRED_MASK) {
3912                 if (asserted & ATTN_NIG_FOR_FUNC) {
3913 
3914                         bnx2x_acquire_phy_lock(bp);
3915 
3916                         /* save nig interrupt mask */
3917                         nig_mask = REG_RD(bp, nig_int_mask_addr);
3918 
3919                         /* If nig_mask is not set, no need to call the update
3920                          * function.
3921                          */
3922                         if (nig_mask) {
3923                                 REG_WR(bp, nig_int_mask_addr, 0);
3924 
3925                                 bnx2x_link_attn(bp);
3926                         }
3927 
3928                         /* handle unicore attn? */
3929                 }
3930                 if (asserted & ATTN_SW_TIMER_4_FUNC)
3931                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3932 
3933                 if (asserted & GPIO_2_FUNC)
3934                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3935 
3936                 if (asserted & GPIO_3_FUNC)
3937                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3938 
3939                 if (asserted & GPIO_4_FUNC)
3940                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3941 
3942                 if (port == 0) {
3943                         if (asserted & ATTN_GENERAL_ATTN_1) {
3944                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3945                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3946                         }
3947                         if (asserted & ATTN_GENERAL_ATTN_2) {
3948                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3949                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3950                         }
3951                         if (asserted & ATTN_GENERAL_ATTN_3) {
3952                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3953                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3954                         }
3955                 } else {
3956                         if (asserted & ATTN_GENERAL_ATTN_4) {
3957                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3958                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3959                         }
3960                         if (asserted & ATTN_GENERAL_ATTN_5) {
3961                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3962                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3963                         }
3964                         if (asserted & ATTN_GENERAL_ATTN_6) {
3965                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3966                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3967                         }
3968                 }
3969 
3970         } /* if hardwired */
3971 
3972         if (bp->common.int_block == INT_BLOCK_HC)
3973                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3974                             COMMAND_REG_ATTN_BITS_SET);
3975         else
3976                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3977 
3978         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3979            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3980         REG_WR(bp, reg_addr, asserted);
3981 
3982         /* now set back the mask */
3983         if (asserted & ATTN_NIG_FOR_FUNC) {
3984                 /* Verify that IGU ack through BAR was written before restoring
3985                  * NIG mask. This loop should exit after 2-3 iterations max.
3986                  */
3987                 if (bp->common.int_block != INT_BLOCK_HC) {
3988                         u32 cnt = 0, igu_acked;
3989                         do {
3990                                 igu_acked = REG_RD(bp,
3991                                                    IGU_REG_ATTENTION_ACK_BITS);
3992                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3993                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
3994                         if (!igu_acked)
3995                                 DP(NETIF_MSG_HW,
3996                                    "Failed to verify IGU ack on time\n");
3997                         barrier();
3998                 }
3999                 REG_WR(bp, nig_int_mask_addr, nig_mask);
4000                 bnx2x_release_phy_lock(bp);
4001         }
4002 }
4003 
4004 static void bnx2x_fan_failure(struct bnx2x *bp)
4005 {
4006         int port = BP_PORT(bp);
4007         u32 ext_phy_config;
4008         /* mark the failure */
4009         ext_phy_config =
4010                 SHMEM_RD(bp,
4011                          dev_info.port_hw_config[port].external_phy_config);
4012 
4013         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4014         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4015         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4016                  ext_phy_config);
4017 
4018         /* log the failure */
4019         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4020                             "Please contact OEM Support for assistance\n");
4021 
4022         /* Schedule device reset (unload)
4023          * This is due to some boards consuming sufficient power when driver is
4024          * up to overheat if fan fails.
4025          */
4026         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4027 }
4028 
4029 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4030 {
4031         int port = BP_PORT(bp);
4032         int reg_offset;
4033         u32 val;
4034 
4035         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4036                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4037 
4038         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4039 
4040                 val = REG_RD(bp, reg_offset);
4041                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4042                 REG_WR(bp, reg_offset, val);
4043 
4044                 BNX2X_ERR("SPIO5 hw attention\n");
4045 
4046                 /* Fan failure attention */
4047                 bnx2x_hw_reset_phy(&bp->link_params);
4048                 bnx2x_fan_failure(bp);
4049         }
4050 
4051         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4052                 bnx2x_acquire_phy_lock(bp);
4053                 bnx2x_handle_module_detect_int(&bp->link_params);
4054                 bnx2x_release_phy_lock(bp);
4055         }
4056 
4057         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4058 
4059                 val = REG_RD(bp, reg_offset);
4060                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4061                 REG_WR(bp, reg_offset, val);
4062 
4063                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4064                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
4065                 bnx2x_panic();
4066         }
4067 }
4068 
4069 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4070 {
4071         u32 val;
4072 
4073         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4074 
4075                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4076                 BNX2X_ERR("DB hw attention 0x%x\n", val);
4077                 /* DORQ discard attention */
4078                 if (val & 0x2)
4079                         BNX2X_ERR("FATAL error from DORQ\n");
4080         }
4081 
4082         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4083 
4084                 int port = BP_PORT(bp);
4085                 int reg_offset;
4086 
4087                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4088                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4089 
4090                 val = REG_RD(bp, reg_offset);
4091                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4092                 REG_WR(bp, reg_offset, val);
4093 
4094                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4095                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
4096                 bnx2x_panic();
4097         }
4098 }
4099 
4100 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4101 {
4102         u32 val;
4103 
4104         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4105 
4106                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4107                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4108                 /* CFC error attention */
4109                 if (val & 0x2)
4110                         BNX2X_ERR("FATAL error from CFC\n");
4111         }
4112 
4113         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4114                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4115                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4116                 /* RQ_USDMDP_FIFO_OVERFLOW */
4117                 if (val & 0x18000)
4118                         BNX2X_ERR("FATAL error from PXP\n");
4119 
4120                 if (!CHIP_IS_E1x(bp)) {
4121                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4122                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4123                 }
4124         }
4125 
4126         if (attn & HW_INTERRUT_ASSERT_SET_2) {
4127 
4128                 int port = BP_PORT(bp);
4129                 int reg_offset;
4130 
4131                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4132                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4133 
4134                 val = REG_RD(bp, reg_offset);
4135                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4136                 REG_WR(bp, reg_offset, val);
4137 
4138                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4139                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
4140                 bnx2x_panic();
4141         }
4142 }
4143 
4144 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4145 {
4146         u32 val;
4147 
4148         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4149 
4150                 if (attn & BNX2X_PMF_LINK_ASSERT) {
4151                         int func = BP_FUNC(bp);
4152 
4153                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4154                         bnx2x_read_mf_cfg(bp);
4155                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4156                                         func_mf_config[BP_ABS_FUNC(bp)].config);
4157                         val = SHMEM_RD(bp,
4158                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
4159                         if (val & DRV_STATUS_DCC_EVENT_MASK)
4160                                 bnx2x_dcc_event(bp,
4161                                             (val & DRV_STATUS_DCC_EVENT_MASK));
4162 
4163                         if (val & DRV_STATUS_SET_MF_BW)
4164                                 bnx2x_set_mf_bw(bp);
4165 
4166                         if (val & DRV_STATUS_DRV_INFO_REQ)
4167                                 bnx2x_handle_drv_info_req(bp);
4168 
4169                         if (val & DRV_STATUS_VF_DISABLED)
4170                                 bnx2x_schedule_iov_task(bp,
4171                                                         BNX2X_IOV_HANDLE_FLR);
4172 
4173                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4174                                 bnx2x_pmf_update(bp);
4175 
4176                         if (bp->port.pmf &&
4177                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4178                                 bp->dcbx_enabled > 0)
4179                                 /* start dcbx state machine */
4180                                 bnx2x_dcbx_set_params(bp,
4181                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4182                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4183                                 bnx2x_handle_afex_cmd(bp,
4184                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4185                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4186                                 bnx2x_handle_eee_event(bp);
4187                         if (bp->link_vars.periodic_flags &
4188                             PERIODIC_FLAGS_LINK_EVENT) {
4189                                 /*  sync with link */
4190                                 bnx2x_acquire_phy_lock(bp);
4191                                 bp->link_vars.periodic_flags &=
4192                                         ~PERIODIC_FLAGS_LINK_EVENT;
4193                                 bnx2x_release_phy_lock(bp);
4194                                 if (IS_MF(bp))
4195                                         bnx2x_link_sync_notify(bp);
4196                                 bnx2x_link_report(bp);
4197                         }
4198                         /* Always call it here: bnx2x_link_report() will
4199                          * prevent the link indication duplication.
4200                          */
4201                         bnx2x__link_status_update(bp);
4202                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4203 
4204                         BNX2X_ERR("MC assert!\n");
4205                         bnx2x_mc_assert(bp);
4206                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4207                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4208                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4209                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4210                         bnx2x_panic();
4211 
4212                 } else if (attn & BNX2X_MCP_ASSERT) {
4213 
4214                         BNX2X_ERR("MCP assert!\n");
4215                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4216                         bnx2x_fw_dump(bp);
4217 
4218                 } else
4219                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4220         }
4221 
4222         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4223                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4224                 if (attn & BNX2X_GRC_TIMEOUT) {
4225                         val = CHIP_IS_E1(bp) ? 0 :
4226                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4227                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4228                 }
4229                 if (attn & BNX2X_GRC_RSV) {
4230                         val = CHIP_IS_E1(bp) ? 0 :
4231                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4232                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4233                 }
4234                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4235         }
4236 }
4237 
4238 /*
4239  * Bits map:
4240  * 0-7   - Engine0 load counter.
4241  * 8-15  - Engine1 load counter.
4242  * 16    - Engine0 RESET_IN_PROGRESS bit.
4243  * 17    - Engine1 RESET_IN_PROGRESS bit.
4244  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4245  *         on the engine
4246  * 19    - Engine1 ONE_IS_LOADED.
4247  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4248  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4249  *         just the one belonging to its engine).
4250  *
4251  */
4252 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4253 
4254 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4255 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4256 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4257 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4258 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4259 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4260 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4261 
4262 /*
4263  * Set the GLOBAL_RESET bit.
4264  *
4265  * Should be run under rtnl lock
4266  */
4267 void bnx2x_set_reset_global(struct bnx2x *bp)
4268 {
4269         u32 val;
4270         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4271         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4272         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4273         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4274 }
4275 
4276 /*
4277  * Clear the GLOBAL_RESET bit.
4278  *
4279  * Should be run under rtnl lock
4280  */
4281 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4282 {
4283         u32 val;
4284         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4285         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4286         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4287         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4288 }
4289 
4290 /*
4291  * Checks the GLOBAL_RESET bit.
4292  *
4293  * should be run under rtnl lock
4294  */
4295 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4296 {
4297         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4298 
4299         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4300         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4301 }
4302 
4303 /*
4304  * Clear RESET_IN_PROGRESS bit for the current engine.
4305  *
4306  * Should be run under rtnl lock
4307  */
4308 static void bnx2x_set_reset_done(struct bnx2x *bp)
4309 {
4310         u32 val;
4311         u32 bit = BP_PATH(bp) ?
4312                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4313         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4314         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4315 
4316         /* Clear the bit */
4317         val &= ~bit;
4318         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4319 
4320         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4321 }
4322 
4323 /*
4324  * Set RESET_IN_PROGRESS for the current engine.
4325  *
4326  * should be run under rtnl lock
4327  */
4328 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4329 {
4330         u32 val;
4331         u32 bit = BP_PATH(bp) ?
4332                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4333         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4334         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4335 
4336         /* Set the bit */
4337         val |= bit;
4338         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4339         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4340 }
4341 
4342 /*
4343  * Checks the RESET_IN_PROGRESS bit for the given engine.
4344  * should be run under rtnl lock
4345  */
4346 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4347 {
4348         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4349         u32 bit = engine ?
4350                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4351 
4352         /* return false if bit is set */
4353         return (val & bit) ? false : true;
4354 }
4355 
4356 /*
4357  * set pf load for the current pf.
4358  *
4359  * should be run under rtnl lock
4360  */
4361 void bnx2x_set_pf_load(struct bnx2x *bp)
4362 {
4363         u32 val1, val;
4364         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4365                              BNX2X_PATH0_LOAD_CNT_MASK;
4366         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4367                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4368 
4369         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4370         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4371 
4372         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4373 
4374         /* get the current counter value */
4375         val1 = (val & mask) >> shift;
4376 
4377         /* set bit of that PF */
4378         val1 |= (1 << bp->pf_num);
4379 
4380         /* clear the old value */
4381         val &= ~mask;
4382 
4383         /* set the new one */
4384         val |= ((val1 << shift) & mask);
4385 
4386         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4387         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4388 }
4389 
4390 /**
4391  * bnx2x_clear_pf_load - clear pf load mark
4392  *
4393  * @bp:         driver handle
4394  *
4395  * Should be run under rtnl lock.
4396  * Decrements the load counter for the current engine. Returns
4397  * whether other functions are still loaded
4398  */
4399 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4400 {
4401         u32 val1, val;
4402         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4403                              BNX2X_PATH0_LOAD_CNT_MASK;
4404         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4405                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4406 
4407         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4408         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4409         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4410 
4411         /* get the current counter value */
4412         val1 = (val & mask) >> shift;
4413 
4414         /* clear bit of that PF */
4415         val1 &= ~(1 << bp->pf_num);
4416 
4417         /* clear the old value */
4418         val &= ~mask;
4419 
4420         /* set the new one */
4421         val |= ((val1 << shift) & mask);
4422 
4423         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4424         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4425         return val1 != 0;
4426 }
4427 
4428 /*
4429  * Read the load status for the current engine.
4430  *
4431  * should be run under rtnl lock
4432  */
4433 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4434 {
4435         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4436                              BNX2X_PATH0_LOAD_CNT_MASK);
4437         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4438                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4439         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4440 
4441         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4442 
4443         val = (val & mask) >> shift;
4444 
4445         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4446            engine, val);
4447 
4448         return val != 0;
4449 }
4450 
4451 static void _print_parity(struct bnx2x *bp, u32 reg)
4452 {
4453         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4454 }
4455 
4456 static void _print_next_block(int idx, const char *blk)
4457 {
4458         pr_cont("%s%s", idx ? ", " : "", blk);
4459 }
4460 
4461 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4462                                             int *par_num, bool print)
4463 {
4464         u32 cur_bit;
4465         bool res;
4466         int i;
4467 
4468         res = false;
4469 
4470         for (i = 0; sig; i++) {
4471                 cur_bit = (0x1UL << i);
4472                 if (sig & cur_bit) {
4473                         res |= true; /* Each bit is real error! */
4474 
4475                         if (print) {
4476                                 switch (cur_bit) {
4477                                 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4478                                         _print_next_block((*par_num)++, "BRB");
4479                                         _print_parity(bp,
4480                                                       BRB1_REG_BRB1_PRTY_STS);
4481                                         break;
4482                                 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4483                                         _print_next_block((*par_num)++,
4484                                                           "PARSER");
4485                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4486                                         break;
4487                                 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4488                                         _print_next_block((*par_num)++, "TSDM");
4489                                         _print_parity(bp,
4490                                                       TSDM_REG_TSDM_PRTY_STS);
4491                                         break;
4492                                 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4493                                         _print_next_block((*par_num)++,
4494                                                           "SEARCHER");
4495                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4496                                         break;
4497                                 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4498                                         _print_next_block((*par_num)++, "TCM");
4499                                         _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4500                                         break;
4501                                 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4502                                         _print_next_block((*par_num)++,
4503                                                           "TSEMI");
4504                                         _print_parity(bp,
4505                                                       TSEM_REG_TSEM_PRTY_STS_0);
4506                                         _print_parity(bp,
4507                                                       TSEM_REG_TSEM_PRTY_STS_1);
4508                                         break;
4509                                 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4510                                         _print_next_block((*par_num)++, "XPB");
4511                                         _print_parity(bp, GRCBASE_XPB +
4512                                                           PB_REG_PB_PRTY_STS);
4513                                         break;
4514                                 }
4515                         }
4516 
4517                         /* Clear the bit */
4518                         sig &= ~cur_bit;
4519                 }
4520         }
4521 
4522         return res;
4523 }
4524 
4525 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4526                                             int *par_num, bool *global,
4527                                             bool print)
4528 {
4529         u32 cur_bit;
4530         bool res;
4531         int i;
4532 
4533         res = false;
4534 
4535         for (i = 0; sig; i++) {
4536                 cur_bit = (0x1UL << i);
4537                 if (sig & cur_bit) {
4538                         res |= true; /* Each bit is real error! */
4539                         switch (cur_bit) {
4540                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4541                                 if (print) {
4542                                         _print_next_block((*par_num)++, "PBF");
4543                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4544                                 }
4545                                 break;
4546                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4547                                 if (print) {
4548                                         _print_next_block((*par_num)++, "QM");
4549                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4550                                 }
4551                                 break;
4552                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4553                                 if (print) {
4554                                         _print_next_block((*par_num)++, "TM");
4555                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4556                                 }
4557                                 break;
4558                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4559                                 if (print) {
4560                                         _print_next_block((*par_num)++, "XSDM");
4561                                         _print_parity(bp,
4562                                                       XSDM_REG_XSDM_PRTY_STS);
4563                                 }
4564                                 break;
4565                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4566                                 if (print) {
4567                                         _print_next_block((*par_num)++, "XCM");
4568                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4569                                 }
4570                                 break;
4571                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4572                                 if (print) {
4573                                         _print_next_block((*par_num)++,
4574                                                           "XSEMI");
4575                                         _print_parity(bp,
4576                                                       XSEM_REG_XSEM_PRTY_STS_0);
4577                                         _print_parity(bp,
4578                                                       XSEM_REG_XSEM_PRTY_STS_1);
4579                                 }
4580                                 break;
4581                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4582                                 if (print) {
4583                                         _print_next_block((*par_num)++,
4584                                                           "DOORBELLQ");
4585                                         _print_parity(bp,
4586                                                       DORQ_REG_DORQ_PRTY_STS);
4587                                 }
4588                                 break;
4589                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4590                                 if (print) {
4591                                         _print_next_block((*par_num)++, "NIG");
4592                                         if (CHIP_IS_E1x(bp)) {
4593                                                 _print_parity(bp,
4594                                                         NIG_REG_NIG_PRTY_STS);
4595                                         } else {
4596                                                 _print_parity(bp,
4597                                                         NIG_REG_NIG_PRTY_STS_0);
4598                                                 _print_parity(bp,
4599                                                         NIG_REG_NIG_PRTY_STS_1);
4600                                         }
4601                                 }
4602                                 break;
4603                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4604                                 if (print)
4605                                         _print_next_block((*par_num)++,
4606                                                           "VAUX PCI CORE");
4607                                 *global = true;
4608                                 break;
4609                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4610                                 if (print) {
4611                                         _print_next_block((*par_num)++,
4612                                                           "DEBUG");
4613                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4614                                 }
4615                                 break;
4616                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4617                                 if (print) {
4618                                         _print_next_block((*par_num)++, "USDM");
4619                                         _print_parity(bp,
4620                                                       USDM_REG_USDM_PRTY_STS);
4621                                 }
4622                                 break;
4623                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4624                                 if (print) {
4625                                         _print_next_block((*par_num)++, "UCM");
4626                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4627                                 }
4628                                 break;
4629                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4630                                 if (print) {
4631                                         _print_next_block((*par_num)++,
4632                                                           "USEMI");
4633                                         _print_parity(bp,
4634                                                       USEM_REG_USEM_PRTY_STS_0);
4635                                         _print_parity(bp,
4636                                                       USEM_REG_USEM_PRTY_STS_1);
4637                                 }
4638                                 break;
4639                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4640                                 if (print) {
4641                                         _print_next_block((*par_num)++, "UPB");
4642                                         _print_parity(bp, GRCBASE_UPB +
4643                                                           PB_REG_PB_PRTY_STS);
4644                                 }
4645                                 break;
4646                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4647                                 if (print) {
4648                                         _print_next_block((*par_num)++, "CSDM");
4649                                         _print_parity(bp,
4650                                                       CSDM_REG_CSDM_PRTY_STS);
4651                                 }
4652                                 break;
4653                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4654                                 if (print) {
4655                                         _print_next_block((*par_num)++, "CCM");
4656                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4657                                 }
4658                                 break;
4659                         }
4660 
4661                         /* Clear the bit */
4662                         sig &= ~cur_bit;
4663                 }
4664         }
4665 
4666         return res;
4667 }
4668 
4669 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4670                                             int *par_num, bool print)
4671 {
4672         u32 cur_bit;
4673         bool res;
4674         int i;
4675 
4676         res = false;
4677 
4678         for (i = 0; sig; i++) {
4679                 cur_bit = (0x1UL << i);
4680                 if (sig & cur_bit) {
4681                         res |= true; /* Each bit is real error! */
4682                         if (print) {
4683                                 switch (cur_bit) {
4684                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4685                                         _print_next_block((*par_num)++,
4686                                                           "CSEMI");
4687                                         _print_parity(bp,
4688                                                       CSEM_REG_CSEM_PRTY_STS_0);
4689                                         _print_parity(bp,
4690                                                       CSEM_REG_CSEM_PRTY_STS_1);
4691                                         break;
4692                                 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4693                                         _print_next_block((*par_num)++, "PXP");
4694                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4695                                         _print_parity(bp,
4696                                                       PXP2_REG_PXP2_PRTY_STS_0);
4697                                         _print_parity(bp,
4698                                                       PXP2_REG_PXP2_PRTY_STS_1);
4699                                         break;
4700                                 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4701                                         _print_next_block((*par_num)++,
4702                                                           "PXPPCICLOCKCLIENT");
4703                                         break;
4704                                 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4705                                         _print_next_block((*par_num)++, "CFC");
4706                                         _print_parity(bp,
4707                                                       CFC_REG_CFC_PRTY_STS);
4708                                         break;
4709                                 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4710                                         _print_next_block((*par_num)++, "CDU");
4711                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4712                                         break;
4713                                 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4714                                         _print_next_block((*par_num)++, "DMAE");
4715                                         _print_parity(bp,
4716                                                       DMAE_REG_DMAE_PRTY_STS);
4717                                         break;
4718                                 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4719                                         _print_next_block((*par_num)++, "IGU");
4720                                         if (CHIP_IS_E1x(bp))
4721                                                 _print_parity(bp,
4722                                                         HC_REG_HC_PRTY_STS);
4723                                         else
4724                                                 _print_parity(bp,
4725                                                         IGU_REG_IGU_PRTY_STS);
4726                                         break;
4727                                 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4728                                         _print_next_block((*par_num)++, "MISC");
4729                                         _print_parity(bp,
4730                                                       MISC_REG_MISC_PRTY_STS);
4731                                         break;
4732                                 }
4733                         }
4734 
4735                         /* Clear the bit */
4736                         sig &= ~cur_bit;
4737                 }
4738         }
4739 
4740         return res;
4741 }
4742 
4743 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4744                                             int *par_num, bool *global,
4745                                             bool print)
4746 {
4747         bool res = false;
4748         u32 cur_bit;
4749         int i;
4750 
4751         for (i = 0; sig; i++) {
4752                 cur_bit = (0x1UL << i);
4753                 if (sig & cur_bit) {
4754                         switch (cur_bit) {
4755                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4756                                 if (print)
4757                                         _print_next_block((*par_num)++,
4758                                                           "MCP ROM");
4759                                 *global = true;
4760                                 res |= true;
4761                                 break;
4762                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4763                                 if (print)
4764                                         _print_next_block((*par_num)++,
4765                                                           "MCP UMP RX");
4766                                 *global = true;
4767                                 res |= true;
4768                                 break;
4769                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4770                                 if (print)
4771                                         _print_next_block((*par_num)++,
4772                                                           "MCP UMP TX");
4773                                 *global = true;
4774                                 res |= true;
4775                                 break;
4776                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4777                                 if (print)
4778                                         _print_next_block((*par_num)++,
4779                                                           "MCP SCPAD");
4780                                 /* clear latched SCPAD PATIRY from MCP */
4781                                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4782                                        1UL << 10);
4783                                 break;
4784                         }
4785 
4786                         /* Clear the bit */
4787                         sig &= ~cur_bit;
4788                 }
4789         }
4790 
4791         return res;
4792 }
4793 
4794 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4795                                             int *par_num, bool print)
4796 {
4797         u32 cur_bit;
4798         bool res;
4799         int i;
4800 
4801         res = false;
4802 
4803         for (i = 0; sig; i++) {
4804                 cur_bit = (0x1UL << i);
4805                 if (sig & cur_bit) {
4806                         res |= true; /* Each bit is real error! */
4807                         if (print) {
4808                                 switch (cur_bit) {
4809                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4810                                         _print_next_block((*par_num)++,
4811                                                           "PGLUE_B");
4812                                         _print_parity(bp,
4813                                                       PGLUE_B_REG_PGLUE_B_PRTY_STS);
4814                                         break;
4815                                 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4816                                         _print_next_block((*par_num)++, "ATC");
4817                                         _print_parity(bp,
4818                                                       ATC_REG_ATC_PRTY_STS);
4819                                         break;
4820                                 }
4821                         }
4822                         /* Clear the bit */
4823                         sig &= ~cur_bit;
4824                 }
4825         }
4826 
4827         return res;
4828 }
4829 
4830 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4831                               u32 *sig)
4832 {
4833         bool res = false;
4834 
4835         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4836             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4837             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4838             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4839             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4840                 int par_num = 0;
4841                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4842                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4843                           sig[0] & HW_PRTY_ASSERT_SET_0,
4844                           sig[1] & HW_PRTY_ASSERT_SET_1,
4845                           sig[2] & HW_PRTY_ASSERT_SET_2,
4846                           sig[3] & HW_PRTY_ASSERT_SET_3,
4847                           sig[4] & HW_PRTY_ASSERT_SET_4);
4848                 if (print)
4849                         netdev_err(bp->dev,
4850                                    "Parity errors detected in blocks: ");
4851                 res |= bnx2x_check_blocks_with_parity0(bp,
4852                         sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4853                 res |= bnx2x_check_blocks_with_parity1(bp,
4854                         sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4855                 res |= bnx2x_check_blocks_with_parity2(bp,
4856                         sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4857                 res |= bnx2x_check_blocks_with_parity3(bp,
4858                         sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4859                 res |= bnx2x_check_blocks_with_parity4(bp,
4860                         sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4861 
4862                 if (print)
4863                         pr_cont("\n");
4864         }
4865 
4866         return res;
4867 }
4868 
4869 /**
4870  * bnx2x_chk_parity_attn - checks for parity attentions.
4871  *
4872  * @bp:         driver handle
4873  * @global:     true if there was a global attention
4874  * @print:      show parity attention in syslog
4875  */
4876 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4877 {
4878         struct attn_route attn = { {0} };
4879         int port = BP_PORT(bp);
4880 
4881         attn.sig[0] = REG_RD(bp,
4882                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4883                              port*4);
4884         attn.sig[1] = REG_RD(bp,
4885                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4886                              port*4);
4887         attn.sig[2] = REG_RD(bp,
4888                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4889                              port*4);
4890         attn.sig[3] = REG_RD(bp,
4891                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4892                              port*4);
4893         /* Since MCP attentions can't be disabled inside the block, we need to
4894          * read AEU registers to see whether they're currently disabled
4895          */
4896         attn.sig[3] &= ((REG_RD(bp,
4897                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4898                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
4899                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
4900                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
4901 
4902         if (!CHIP_IS_E1x(bp))
4903                 attn.sig[4] = REG_RD(bp,
4904                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4905                                      port*4);
4906 
4907         return bnx2x_parity_attn(bp, global, print, attn.sig);
4908 }
4909 
4910 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4911 {
4912         u32 val;
4913         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4914 
4915                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4916                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4917                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4918                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4919                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4920                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4921                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4922                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4923                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4924                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4925                 if (val &
4926                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4927                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4928                 if (val &
4929                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4930                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4931                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4932                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4933                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4934                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4935                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4936                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4937         }
4938         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4939                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4940                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4941                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4942                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4943                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4944                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4945                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4946                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4947                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4948                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4949                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4950                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4951                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4952                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4953         }
4954 
4955         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4956                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4957                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4958                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4959                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4960         }
4961 }
4962 
4963 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4964 {
4965         struct attn_route attn, *group_mask;
4966         int port = BP_PORT(bp);
4967         int index;
4968         u32 reg_addr;
4969         u32 val;
4970         u32 aeu_mask;
4971         bool global = false;
4972 
4973         /* need to take HW lock because MCP or other port might also
4974            try to handle this event */
4975         bnx2x_acquire_alr(bp);
4976 
4977         if (bnx2x_chk_parity_attn(bp, &global, true)) {
4978 #ifndef BNX2X_STOP_ON_ERROR
4979                 bp->recovery_state = BNX2X_RECOVERY_INIT;
4980                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4981                 /* Disable HW interrupts */
4982                 bnx2x_int_disable(bp);
4983                 /* In case of parity errors don't handle attentions so that
4984                  * other function would "see" parity errors.
4985                  */
4986 #else
4987                 bnx2x_panic();
4988 #endif
4989                 bnx2x_release_alr(bp);
4990                 return;
4991         }
4992 
4993         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4994         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4995         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4996         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4997         if (!CHIP_IS_E1x(bp))
4998                 attn.sig[4] =
4999                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5000         else
5001                 attn.sig[4] = 0;
5002 
5003         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5004            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5005 
5006         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5007                 if (deasserted & (1 << index)) {
5008                         group_mask = &bp->attn_group[index];
5009 
5010                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5011                            index,
5012                            group_mask->sig[0], group_mask->sig[1],
5013                            group_mask->sig[2], group_mask->sig[3],
5014                            group_mask->sig[4]);
5015 
5016                         bnx2x_attn_int_deasserted4(bp,
5017                                         attn.sig[4] & group_mask->sig[4]);
5018                         bnx2x_attn_int_deasserted3(bp,
5019                                         attn.sig[3] & group_mask->sig[3]);
5020                         bnx2x_attn_int_deasserted1(bp,
5021                                         attn.sig[1] & group_mask->sig[1]);
5022                         bnx2x_attn_int_deasserted2(bp,
5023                                         attn.sig[2] & group_mask->sig[2]);
5024                         bnx2x_attn_int_deasserted0(bp,
5025                                         attn.sig[0] & group_mask->sig[0]);
5026                 }
5027         }
5028 
5029         bnx2x_release_alr(bp);
5030 
5031         if (bp->common.int_block == INT_BLOCK_HC)
5032                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5033                             COMMAND_REG_ATTN_BITS_CLR);
5034         else
5035                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5036 
5037         val = ~deasserted;
5038         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5039            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5040         REG_WR(bp, reg_addr, val);
5041 
5042         if (~bp->attn_state & deasserted)
5043                 BNX2X_ERR("IGU ERROR\n");
5044 
5045         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5046                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
5047 
5048         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5049         aeu_mask = REG_RD(bp, reg_addr);
5050 
5051         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
5052            aeu_mask, deasserted);
5053         aeu_mask |= (deasserted & 0x3ff);
5054         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5055 
5056         REG_WR(bp, reg_addr, aeu_mask);
5057         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5058 
5059         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5060         bp->attn_state &= ~deasserted;
5061         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5062 }
5063 
5064 static void bnx2x_attn_int(struct bnx2x *bp)
5065 {
5066         /* read local copy of bits */
5067         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5068                                                                 attn_bits);
5069         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5070                                                                 attn_bits_ack);
5071         u32 attn_state = bp->attn_state;
5072 
5073         /* look for changed bits */
5074         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
5075         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
5076 
5077         DP(NETIF_MSG_HW,
5078            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
5079            attn_bits, attn_ack, asserted, deasserted);
5080 
5081         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5082                 BNX2X_ERR("BAD attention state\n");
5083 
5084         /* handle bits that were raised */
5085         if (asserted)
5086                 bnx2x_attn_int_asserted(bp, asserted);
5087 
5088         if (deasserted)
5089                 bnx2x_attn_int_deasserted(bp, deasserted);
5090 }
5091 
5092 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5093                       u16 index, u8 op, u8 update)
5094 {
5095         u32 igu_addr = bp->igu_base_addr;
5096         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5097         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5098                              igu_addr);
5099 }
5100 
5101 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5102 {
5103         /* No memory barriers */
5104         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5105         mmiowb(); /* keep prod updates ordered */
5106 }
5107 
5108 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5109                                       union event_ring_elem *elem)
5110 {
5111         u8 err = elem->message.error;
5112 
5113         if (!bp->cnic_eth_dev.starting_cid  ||
5114             (cid < bp->cnic_eth_dev.starting_cid &&
5115             cid != bp->cnic_eth_dev.iscsi_l2_cid))
5116                 return 1;
5117 
5118         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5119 
5120         if (unlikely(err)) {
5121 
5122                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5123                           cid);
5124                 bnx2x_panic_dump(bp, false);
5125         }
5126         bnx2x_cnic_cfc_comp(bp, cid, err);
5127         return 0;
5128 }
5129 
5130 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5131 {
5132         struct bnx2x_mcast_ramrod_params rparam;
5133         int rc;
5134 
5135         memset(&rparam, 0, sizeof(rparam));
5136 
5137         rparam.mcast_obj = &bp->mcast_obj;
5138 
5139         netif_addr_lock_bh(bp->dev);
5140 
5141         /* Clear pending state for the last command */
5142         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5143 
5144         /* If there are pending mcast commands - send them */
5145         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5146                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5147                 if (rc < 0)
5148                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5149                                   rc);
5150         }
5151 
5152         netif_addr_unlock_bh(bp->dev);
5153 }
5154 
5155 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5156                                             union event_ring_elem *elem)
5157 {
5158         unsigned long ramrod_flags = 0;
5159         int rc = 0;
5160         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5161         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5162 
5163         /* Always push next commands out, don't wait here */
5164         __set_bit(RAMROD_CONT, &ramrod_flags);
5165 
5166         switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5167                             >> BNX2X_SWCID_SHIFT) {
5168         case BNX2X_FILTER_MAC_PENDING:
5169                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5170                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5171                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5172                 else
5173                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5174 
5175                 break;
5176         case BNX2X_FILTER_MCAST_PENDING:
5177                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5178                 /* This is only relevant for 57710 where multicast MACs are
5179                  * configured as unicast MACs using the same ramrod.
5180                  */
5181                 bnx2x_handle_mcast_eqe(bp);
5182                 return;
5183         default:
5184                 BNX2X_ERR("Unsupported classification command: %d\n",
5185                           elem->message.data.eth_event.echo);
5186                 return;
5187         }
5188 
5189         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5190 
5191         if (rc < 0)
5192                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5193         else if (rc > 0)
5194                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5195 }
5196 
5197 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5198 
5199 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5200 {
5201         netif_addr_lock_bh(bp->dev);
5202 
5203         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5204 
5205         /* Send rx_mode command again if was requested */
5206         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5207                 bnx2x_set_storm_rx_mode(bp);
5208         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5209                                     &bp->sp_state))
5210                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5211         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5212                                     &bp->sp_state))
5213                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5214 
5215         netif_addr_unlock_bh(bp->dev);
5216 }
5217 
5218 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5219                                               union event_ring_elem *elem)
5220 {
5221         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5222                 DP(BNX2X_MSG_SP,
5223                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5224                    elem->message.data.vif_list_event.func_bit_map);
5225                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5226                         elem->message.data.vif_list_event.func_bit_map);
5227         } else if (elem->message.data.vif_list_event.echo ==
5228                    VIF_LIST_RULE_SET) {
5229                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5230                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5231         }
5232 }
5233 
5234 /* called with rtnl_lock */
5235 static void bnx2x_after_function_update(struct bnx2x *bp)
5236 {
5237         int q, rc;
5238         struct bnx2x_fastpath *fp;
5239         struct bnx2x_queue_state_params queue_params = {NULL};
5240         struct bnx2x_queue_update_params *q_update_params =
5241                 &queue_params.params.update;
5242 
5243         /* Send Q update command with afex vlan removal values for all Qs */
5244         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5245 
5246         /* set silent vlan removal values according to vlan mode */
5247         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5248                   &q_update_params->update_flags);
5249         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5250                   &q_update_params->update_flags);
5251         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5252 
5253         /* in access mode mark mask and value are 0 to strip all vlans */
5254         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5255                 q_update_params->silent_removal_value = 0;
5256                 q_update_params->silent_removal_mask = 0;
5257         } else {
5258                 q_update_params->silent_removal_value =
5259                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5260                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5261         }
5262 
5263         for_each_eth_queue(bp, q) {
5264                 /* Set the appropriate Queue object */
5265                 fp = &bp->fp[q];
5266                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5267 
5268                 /* send the ramrod */
5269                 rc = bnx2x_queue_state_change(bp, &queue_params);
5270                 if (rc < 0)
5271                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5272                                   q);
5273         }
5274 
5275         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5276                 fp = &bp->fp[FCOE_IDX(bp)];
5277                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5278 
5279                 /* clear pending completion bit */
5280                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5281 
5282                 /* mark latest Q bit */
5283                 smp_mb__before_atomic();
5284                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5285                 smp_mb__after_atomic();
5286 
5287                 /* send Q update ramrod for FCoE Q */
5288                 rc = bnx2x_queue_state_change(bp, &queue_params);
5289                 if (rc < 0)
5290                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5291                                   q);
5292         } else {
5293                 /* If no FCoE ring - ACK MCP now */
5294                 bnx2x_link_report(bp);
5295                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5296         }
5297 }
5298 
5299 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5300         struct bnx2x *bp, u32 cid)
5301 {
5302         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5303 
5304         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5305                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5306         else
5307                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5308 }
5309 
5310 static void bnx2x_eq_int(struct bnx2x *bp)
5311 {
5312         u16 hw_cons, sw_cons, sw_prod;
5313         union event_ring_elem *elem;
5314         u8 echo;
5315         u32 cid;
5316         u8 opcode;
5317         int rc, spqe_cnt = 0;
5318         struct bnx2x_queue_sp_obj *q_obj;
5319         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5320         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5321 
5322         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5323 
5324         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5325          * when we get the next-page we need to adjust so the loop
5326          * condition below will be met. The next element is the size of a
5327          * regular element and hence incrementing by 1
5328          */
5329         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5330                 hw_cons++;
5331 
5332         /* This function may never run in parallel with itself for a
5333          * specific bp, thus there is no need in "paired" read memory
5334          * barrier here.
5335          */
5336         sw_cons = bp->eq_cons;
5337         sw_prod = bp->eq_prod;
5338 
5339         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5340                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5341 
5342         for (; sw_cons != hw_cons;
5343               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5344 
5345                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5346 
5347                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5348                 if (!rc) {
5349                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5350                            rc);
5351                         goto next_spqe;
5352                 }
5353 
5354                 /* elem CID originates from FW; actually LE */
5355                 cid = SW_CID((__force __le32)
5356                              elem->message.data.cfc_del_event.cid);
5357                 opcode = elem->message.opcode;
5358 
5359                 /* handle eq element */
5360                 switch (opcode) {
5361                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5362                         bnx2x_vf_mbx_schedule(bp,
5363                                               &elem->message.data.vf_pf_event);
5364                         continue;
5365 
5366                 case EVENT_RING_OPCODE_STAT_QUERY:
5367                         DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5368                                "got statistics comp event %d\n",
5369                                bp->stats_comp++);
5370                         /* nothing to do with stats comp */
5371                         goto next_spqe;
5372 
5373                 case EVENT_RING_OPCODE_CFC_DEL:
5374                         /* handle according to cid range */
5375                         /*
5376                          * we may want to verify here that the bp state is
5377                          * HALTING
5378                          */
5379                         DP(BNX2X_MSG_SP,
5380                            "got delete ramrod for MULTI[%d]\n", cid);
5381 
5382                         if (CNIC_LOADED(bp) &&
5383                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5384                                 goto next_spqe;
5385 
5386                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5387 
5388                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5389                                 break;
5390 
5391                         goto next_spqe;
5392 
5393                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5394                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5395                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5396                         if (f_obj->complete_cmd(bp, f_obj,
5397                                                 BNX2X_F_CMD_TX_STOP))
5398                                 break;
5399                         goto next_spqe;
5400 
5401                 case EVENT_RING_OPCODE_START_TRAFFIC:
5402                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5403                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5404                         if (f_obj->complete_cmd(bp, f_obj,
5405                                                 BNX2X_F_CMD_TX_START))
5406                                 break;
5407                         goto next_spqe;
5408 
5409                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5410                         echo = elem->message.data.function_update_event.echo;
5411                         if (echo == SWITCH_UPDATE) {
5412                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5413                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5414                                 if (f_obj->complete_cmd(
5415                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5416                                         break;
5417 
5418                         } else {
5419                                 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5420 
5421                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5422                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5423                                 f_obj->complete_cmd(bp, f_obj,
5424                                                     BNX2X_F_CMD_AFEX_UPDATE);
5425 
5426                                 /* We will perform the Queues update from
5427                                  * sp_rtnl task as all Queue SP operations
5428                                  * should run under rtnl_lock.
5429                                  */
5430                                 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5431                         }
5432 
5433                         goto next_spqe;
5434 
5435                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5436                         f_obj->complete_cmd(bp, f_obj,
5437                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5438                         bnx2x_after_afex_vif_lists(bp, elem);
5439                         goto next_spqe;
5440                 case EVENT_RING_OPCODE_FUNCTION_START:
5441                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5442                            "got FUNC_START ramrod\n");
5443                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5444                                 break;
5445 
5446                         goto next_spqe;
5447 
5448                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5449                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5450                            "got FUNC_STOP ramrod\n");
5451                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5452                                 break;
5453 
5454                         goto next_spqe;
5455                 }
5456 
5457                 switch (opcode | bp->state) {
5458                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5459                       BNX2X_STATE_OPEN):
5460                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5461                       BNX2X_STATE_OPENING_WAIT4_PORT):
5462                         cid = elem->message.data.eth_event.echo &
5463                                 BNX2X_SWCID_MASK;
5464                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5465                            cid);
5466                         rss_raw->clear_pending(rss_raw);
5467                         break;
5468 
5469                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5470                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5471                 case (EVENT_RING_OPCODE_SET_MAC |
5472                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5473                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5474                       BNX2X_STATE_OPEN):
5475                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5476                       BNX2X_STATE_DIAG):
5477                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5478                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5479                         DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5480                         bnx2x_handle_classification_eqe(bp, elem);
5481                         break;
5482 
5483                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5484                       BNX2X_STATE_OPEN):
5485                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5486                       BNX2X_STATE_DIAG):
5487                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5488                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5489                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5490                         bnx2x_handle_mcast_eqe(bp);
5491                         break;
5492 
5493                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5494                       BNX2X_STATE_OPEN):
5495                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5496                       BNX2X_STATE_DIAG):
5497                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5498                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5499                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5500                         bnx2x_handle_rx_mode_eqe(bp);
5501                         break;
5502                 default:
5503                         /* unknown event log error and continue */
5504                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5505                                   elem->message.opcode, bp->state);
5506                 }
5507 next_spqe:
5508                 spqe_cnt++;
5509         } /* for */
5510 
5511         smp_mb__before_atomic();
5512         atomic_add(spqe_cnt, &bp->eq_spq_left);
5513 
5514         bp->eq_cons = sw_cons;
5515         bp->eq_prod = sw_prod;
5516         /* Make sure that above mem writes were issued towards the memory */
5517         smp_wmb();
5518 
5519         /* update producer */
5520         bnx2x_update_eq_prod(bp, bp->eq_prod);
5521 }
5522 
5523 static void bnx2x_sp_task(struct work_struct *work)
5524 {
5525         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5526 
5527         DP(BNX2X_MSG_SP, "sp task invoked\n");
5528 
5529         /* make sure the atomic interrupt_occurred has been written */
5530         smp_rmb();
5531         if (atomic_read(&bp->interrupt_occurred)) {
5532 
5533                 /* what work needs to be performed? */
5534                 u16 status = bnx2x_update_dsb_idx(bp);
5535 
5536                 DP(BNX2X_MSG_SP, "status %x\n", status);
5537                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5538                 atomic_set(&bp->interrupt_occurred, 0);
5539 
5540                 /* HW attentions */
5541                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5542                         bnx2x_attn_int(bp);
5543                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5544                 }
5545 
5546                 /* SP events: STAT_QUERY and others */
5547                 if (status & BNX2X_DEF_SB_IDX) {
5548                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5549 
5550                 if (FCOE_INIT(bp) &&
5551                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5552                                 /* Prevent local bottom-halves from running as
5553                                  * we are going to change the local NAPI list.
5554                                  */
5555                                 local_bh_disable();
5556                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5557                                 local_bh_enable();
5558                         }
5559 
5560                         /* Handle EQ completions */
5561                         bnx2x_eq_int(bp);
5562                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5563                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5564 
5565                         status &= ~BNX2X_DEF_SB_IDX;
5566                 }
5567 
5568                 /* if status is non zero then perhaps something went wrong */
5569                 if (unlikely(status))
5570                         DP(BNX2X_MSG_SP,
5571                            "got an unknown interrupt! (status 0x%x)\n", status);
5572 
5573                 /* ack status block only if something was actually handled */
5574                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5575                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5576         }
5577 
5578         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5579         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5580                                &bp->sp_state)) {
5581                 bnx2x_link_report(bp);
5582                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5583         }
5584 }
5585 
5586 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5587 {
5588         struct net_device *dev = dev_instance;
5589         struct bnx2x *bp = netdev_priv(dev);
5590 
5591         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5592                      IGU_INT_DISABLE, 0);
5593 
5594 #ifdef BNX2X_STOP_ON_ERROR
5595         if (unlikely(bp->panic))
5596                 return IRQ_HANDLED;
5597 #endif
5598 
5599         if (CNIC_LOADED(bp)) {
5600                 struct cnic_ops *c_ops;
5601 
5602                 rcu_read_lock();
5603                 c_ops = rcu_dereference(bp->cnic_ops);
5604                 if (c_ops)
5605                         c_ops->cnic_handler(bp->cnic_data, NULL);
5606                 rcu_read_unlock();
5607         }
5608 
5609         /* schedule sp task to perform default status block work, ack
5610          * attentions and enable interrupts.
5611          */
5612         bnx2x_schedule_sp_task(bp);
5613 
5614         return IRQ_HANDLED;
5615 }
5616 
5617 /* end of slow path */
5618 
5619 void bnx2x_drv_pulse(struct bnx2x *bp)
5620 {
5621         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5622                  bp->fw_drv_pulse_wr_seq);
5623 }
5624 
5625 static void bnx2x_timer(unsigned long data)
5626 {
5627         struct bnx2x *bp = (struct bnx2x *) data;
5628 
5629         if (!netif_running(bp->dev))
5630                 return;
5631 
5632         if (IS_PF(bp) &&
5633             !BP_NOMCP(bp)) {
5634                 int mb_idx = BP_FW_MB_IDX(bp);
5635                 u16 drv_pulse;
5636                 u16 mcp_pulse;
5637 
5638                 ++bp->fw_drv_pulse_wr_seq;
5639                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5640                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5641                 bnx2x_drv_pulse(bp);
5642 
5643                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5644                              MCP_PULSE_SEQ_MASK);
5645                 /* The delta between driver pulse and mcp response
5646                  * should not get too big. If the MFW is more than 5 pulses
5647                  * behind, we should worry about it enough to generate an error
5648                  * log.
5649                  */
5650                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5651                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5652                                   drv_pulse, mcp_pulse);
5653         }
5654 
5655         if (bp->state == BNX2X_STATE_OPEN)
5656                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5657 
5658         /* sample pf vf bulletin board for new posts from pf */
5659         if (IS_VF(bp))
5660                 bnx2x_timer_sriov(bp);
5661 
5662         mod_timer(&bp->timer, jiffies + bp->current_interval);
5663 }
5664 
5665 /* end of Statistics */
5666 
5667 /* nic init */
5668 
5669 /*
5670  * nic init service functions
5671  */
5672 
5673 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5674 {
5675         u32 i;
5676         if (!(len%4) && !(addr%4))
5677                 for (i = 0; i < len; i += 4)
5678                         REG_WR(bp, addr + i, fill);
5679         else
5680                 for (i = 0; i < len; i++)
5681                         REG_WR8(bp, addr + i, fill);
5682 }
5683 
5684 /* helper: writes FP SP data to FW - data_size in dwords */
5685 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5686                                 int fw_sb_id,
5687                                 u32 *sb_data_p,
5688                                 u32 data_size)
5689 {
5690         int index;
5691         for (index = 0; index < data_size; index++)
5692                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5693                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5694                         sizeof(u32)*index,
5695                         *(sb_data_p + index));
5696 }
5697 
5698 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5699 {
5700         u32 *sb_data_p;
5701         u32 data_size = 0;
5702         struct hc_status_block_data_e2 sb_data_e2;
5703         struct hc_status_block_data_e1x sb_data_e1x;
5704 
5705         /* disable the function first */
5706         if (!CHIP_IS_E1x(bp)) {
5707                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5708                 sb_data_e2.common.state = SB_DISABLED;
5709                 sb_data_e2.common.p_func.vf_valid = false;
5710                 sb_data_p = (u32 *)&sb_data_e2;
5711                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5712         } else {
5713                 memset(&sb_data_e1x, 0,
5714                        sizeof(struct hc_status_block_data_e1x));
5715                 sb_data_e1x.common.state = SB_DISABLED;
5716                 sb_data_e1x.common.p_func.vf_valid = false;
5717                 sb_data_p = (u32 *)&sb_data_e1x;
5718                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5719         }
5720         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5721 
5722         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5723                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5724                         CSTORM_STATUS_BLOCK_SIZE);
5725         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5726                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5727                         CSTORM_SYNC_BLOCK_SIZE);
5728 }
5729 
5730 /* helper:  writes SP SB data to FW */
5731 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5732                 struct hc_sp_status_block_data *sp_sb_data)
5733 {
5734         int func = BP_FUNC(bp);
5735         int i;
5736         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5737                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5738                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5739                         i*sizeof(u32),
5740                         *((u32 *)sp_sb_data + i));
5741 }
5742 
5743 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5744 {
5745         int func = BP_FUNC(bp);
5746         struct hc_sp_status_block_data sp_sb_data;
5747         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5748 
5749         sp_sb_data.state = SB_DISABLED;
5750         sp_sb_data.p_func.vf_valid = false;
5751 
5752         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5753 
5754         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5755                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5756                         CSTORM_SP_STATUS_BLOCK_SIZE);
5757         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5758                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5759                         CSTORM_SP_SYNC_BLOCK_SIZE);
5760 }
5761 
5762 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5763                                            int igu_sb_id, int igu_seg_id)
5764 {
5765         hc_sm->igu_sb_id = igu_sb_id;
5766         hc_sm->igu_seg_id = igu_seg_id;
5767         hc_sm->timer_value = 0xFF;
5768         hc_sm->time_to_expire = 0xFFFFFFFF;
5769 }
5770 
5771 /* allocates state machine ids. */
5772 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5773 {
5774         /* zero out state machine indices */
5775         /* rx indices */
5776         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5777 
5778         /* tx indices */
5779         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5780         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5781         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5782         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5783 
5784         /* map indices */
5785         /* rx indices */
5786         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5787                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5788 
5789         /* tx indices */
5790         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5791                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5792         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5793                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5794         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5795                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5796         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5797                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5798 }
5799 
5800 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5801                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5802 {
5803         int igu_seg_id;
5804 
5805         struct hc_status_block_data_e2 sb_data_e2;
5806         struct hc_status_block_data_e1x sb_data_e1x;
5807         struct hc_status_block_sm  *hc_sm_p;
5808         int data_size;
5809         u32 *sb_data_p;
5810 
5811         if (CHIP_INT_MODE_IS_BC(bp))
5812                 igu_seg_id = HC_SEG_ACCESS_NORM;
5813         else
5814                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5815 
5816         bnx2x_zero_fp_sb(bp, fw_sb_id);
5817 
5818         if (!CHIP_IS_E1x(bp)) {
5819                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5820                 sb_data_e2.common.state = SB_ENABLED;
5821                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5822                 sb_data_e2.common.p_func.vf_id = vfid;
5823                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5824                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5825                 sb_data_e2.common.same_igu_sb_1b = true;
5826                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5827                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5828                 hc_sm_p = sb_data_e2.common.state_machine;
5829                 sb_data_p = (u32 *)&sb_data_e2;
5830                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5831                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5832         } else {
5833                 memset(&sb_data_e1x, 0,
5834                        sizeof(struct hc_status_block_data_e1x));
5835                 sb_data_e1x.common.state = SB_ENABLED;
5836                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5837                 sb_data_e1x.common.p_func.vf_id = 0xff;
5838                 sb_data_e1x.common.p_func.vf_valid = false;
5839                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5840                 sb_data_e1x.common.same_igu_sb_1b = true;
5841                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5842                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5843                 hc_sm_p = sb_data_e1x.common.state_machine;
5844                 sb_data_p = (u32 *)&sb_data_e1x;
5845                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5846                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5847         }
5848 
5849         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5850                                        igu_sb_id, igu_seg_id);
5851         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5852                                        igu_sb_id, igu_seg_id);
5853 
5854         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5855 
5856         /* write indices to HW - PCI guarantees endianity of regpairs */
5857         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5858 }
5859 
5860 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5861                                      u16 tx_usec, u16 rx_usec)
5862 {
5863         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5864                                     false, rx_usec);
5865         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5866                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5867                                        tx_usec);
5868         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5869                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5870                                        tx_usec);
5871         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5872                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5873                                        tx_usec);
5874 }
5875 
5876 static void bnx2x_init_def_sb(struct bnx2x *bp)
5877 {
5878         struct host_sp_status_block *def_sb = bp->def_status_blk;
5879         dma_addr_t mapping = bp->def_status_blk_mapping;
5880         int igu_sp_sb_index;
5881         int igu_seg_id;
5882         int port = BP_PORT(bp);
5883         int func = BP_FUNC(bp);
5884         int reg_offset, reg_offset_en5;
5885         u64 section;
5886         int index;
5887         struct hc_sp_status_block_data sp_sb_data;
5888         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5889 
5890         if (CHIP_INT_MODE_IS_BC(bp)) {
5891                 igu_sp_sb_index = DEF_SB_IGU_ID;
5892                 igu_seg_id = HC_SEG_ACCESS_DEF;
5893         } else {
5894                 igu_sp_sb_index = bp->igu_dsb_id;
5895                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5896         }
5897 
5898         /* ATTN */
5899         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5900                                             atten_status_block);
5901         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5902 
5903         bp->attn_state = 0;
5904 
5905         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5906                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5907         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5908                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5909         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5910                 int sindex;
5911                 /* take care of sig[0]..sig[4] */
5912                 for (sindex = 0; sindex < 4; sindex++)
5913                         bp->attn_group[index].sig[sindex] =
5914                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5915 
5916                 if (!CHIP_IS_E1x(bp))
5917                         /*
5918                          * enable5 is separate from the rest of the registers,
5919                          * and therefore the address skip is 4
5920                          * and not 16 between the different groups
5921                          */
5922                         bp->attn_group[index].sig[4] = REG_RD(bp,
5923                                         reg_offset_en5 + 0x4*index);
5924                 else
5925                         bp->attn_group[index].sig[4] = 0;
5926         }
5927 
5928         if (bp->common.int_block == INT_BLOCK_HC) {
5929                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5930                                      HC_REG_ATTN_MSG0_ADDR_L);
5931 
5932                 REG_WR(bp, reg_offset, U64_LO(section));
5933                 REG_WR(bp, reg_offset + 4, U64_HI(section));
5934         } else if (!CHIP_IS_E1x(bp)) {
5935                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5936                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5937         }
5938 
5939         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5940                                             sp_sb);
5941 
5942         bnx2x_zero_sp_sb(bp);
5943 
5944         /* PCI guarantees endianity of regpairs */
5945         sp_sb_data.state                = SB_ENABLED;
5946         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
5947         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
5948         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
5949         sp_sb_data.igu_seg_id           = igu_seg_id;
5950         sp_sb_data.p_func.pf_id         = func;
5951         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
5952         sp_sb_data.p_func.vf_id         = 0xff;
5953 
5954         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5955 
5956         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5957 }
5958 
5959 void bnx2x_update_coalesce(struct bnx2x *bp)
5960 {
5961         int i;
5962 
5963         for_each_eth_queue(bp, i)
5964                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5965                                          bp->tx_ticks, bp->rx_ticks);
5966 }
5967 
5968 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5969 {
5970         spin_lock_init(&bp->spq_lock);
5971         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5972 
5973         bp->spq_prod_idx = 0;
5974         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5975         bp->spq_prod_bd = bp->spq;
5976         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5977 }
5978 
5979 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5980 {
5981         int i;
5982         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5983                 union event_ring_elem *elem =
5984                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5985 
5986                 elem->next_page.addr.hi =
5987                         cpu_to_le32(U64_HI(bp->eq_mapping +
5988                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5989                 elem->next_page.addr.lo =
5990                         cpu_to_le32(U64_LO(bp->eq_mapping +
5991                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5992         }
5993         bp->eq_cons = 0;
5994         bp->eq_prod = NUM_EQ_DESC;
5995         bp->eq_cons_sb = BNX2X_EQ_INDEX;
5996         /* we want a warning message before it gets wrought... */
5997         atomic_set(&bp->eq_spq_left,
5998                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5999 }
6000 
6001 /* called with netif_addr_lock_bh() */
6002 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6003                                unsigned long rx_mode_flags,
6004                                unsigned long rx_accept_flags,
6005                                unsigned long tx_accept_flags,
6006                                unsigned long ramrod_flags)
6007 {
6008         struct bnx2x_rx_mode_ramrod_params ramrod_param;
6009         int rc;
6010 
6011         memset(&ramrod_param, 0, sizeof(ramrod_param));
6012 
6013         /* Prepare ramrod parameters */
6014         ramrod_param.cid = 0;
6015         ramrod_param.cl_id = cl_id;
6016         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6017         ramrod_param.func_id = BP_FUNC(bp);
6018 
6019         ramrod_param.pstate = &bp->sp_state;
6020         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6021 
6022         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6023         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6024 
6025         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6026 
6027         ramrod_param.ramrod_flags = ramrod_flags;
6028         ramrod_param.rx_mode_flags = rx_mode_flags;
6029 
6030         ramrod_param.rx_accept_flags = rx_accept_flags;
6031         ramrod_param.tx_accept_flags = tx_accept_flags;
6032 
6033         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6034         if (rc < 0) {
6035                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6036                 return rc;
6037         }
6038 
6039         return 0;
6040 }
6041 
6042 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6043                                    unsigned long *rx_accept_flags,
6044                                    unsigned long *tx_accept_flags)
6045 {
6046         /* Clear the flags first */
6047         *rx_accept_flags = 0;
6048         *tx_accept_flags = 0;
6049 
6050         switch (rx_mode) {
6051         case BNX2X_RX_MODE_NONE:
6052                 /*
6053                  * 'drop all' supersedes any accept flags that may have been
6054                  * passed to the function.
6055                  */
6056                 break;
6057         case BNX2X_RX_MODE_NORMAL:
6058                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6059                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6060                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6061 
6062                 /* internal switching mode */
6063                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6064                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6065                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6066 
6067                 break;
6068         case BNX2X_RX_MODE_ALLMULTI:
6069                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6070                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6071                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6072 
6073                 /* internal switching mode */
6074                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6075                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6076                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6077 
6078                 break;
6079         case BNX2X_RX_MODE_PROMISC:
6080                 /* According to definition of SI mode, iface in promisc mode
6081                  * should receive matched and unmatched (in resolution of port)
6082                  * unicast packets.
6083                  */
6084                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6085                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6086                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6087                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6088 
6089                 /* internal switching mode */
6090                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6091                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6092 
6093                 if (IS_MF_SI(bp))
6094                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6095                 else
6096                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6097 
6098                 break;
6099         default:
6100                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6101                 return -EINVAL;
6102         }
6103 
6104         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
6105         if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
6106                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6107                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6108         }
6109 
6110         return 0;
6111 }
6112 
6113 /* called with netif_addr_lock_bh() */
6114 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6115 {
6116         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6117         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6118         int rc;
6119 
6120         if (!NO_FCOE(bp))
6121                 /* Configure rx_mode of FCoE Queue */
6122                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6123 
6124         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6125                                      &tx_accept_flags);
6126         if (rc)
6127                 return rc;
6128 
6129         __set_bit(RAMROD_RX, &ramrod_flags);
6130         __set_bit(RAMROD_TX, &ramrod_flags);
6131 
6132         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6133                                    rx_accept_flags, tx_accept_flags,
6134                                    ramrod_flags);
6135 }
6136 
6137 static void bnx2x_init_internal_common(struct bnx2x *bp)
6138 {
6139         int i;
6140 
6141         /* Zero this manually as its initialization is
6142            currently missing in the initTool */
6143         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6144                 REG_WR(bp, BAR_USTRORM_INTMEM +
6145                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
6146         if (!CHIP_IS_E1x(bp)) {
6147                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6148                         CHIP_INT_MODE_IS_BC(bp) ?
6149                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6150         }
6151 }
6152 
6153 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6154 {
6155         switch (load_code) {
6156         case FW_MSG_CODE_DRV_LOAD_COMMON:
6157         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6158                 bnx2x_init_internal_common(bp);
6159                 /* no break */
6160 
6161         case FW_MSG_CODE_DRV_LOAD_PORT:
6162                 /* nothing to do */
6163                 /* no break */
6164 
6165         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6166                 /* internal memory per function is
6167                    initialized inside bnx2x_pf_init */
6168                 break;
6169 
6170         default:
6171                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6172                 break;
6173         }
6174 }
6175 
6176 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6177 {
6178         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6179 }
6180 
6181 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6182 {
6183         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6184 }
6185 
6186 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6187 {
6188         if (CHIP_IS_E1x(fp->bp))
6189                 return BP_L_ID(fp->bp) + fp->index;
6190         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6191                 return bnx2x_fp_igu_sb_id(fp);
6192 }
6193 
6194 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6195 {
6196         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6197         u8 cos;
6198         unsigned long q_type = 0;
6199         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6200         fp->rx_queue = fp_idx;
6201         fp->cid = fp_idx;
6202         fp->cl_id = bnx2x_fp_cl_id(fp);
6203         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6204         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6205         /* qZone id equals to FW (per path) client id */
6206         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
6207 
6208         /* init shortcut */
6209         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6210 
6211         /* Setup SB indices */
6212         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6213 
6214         /* Configure Queue State object */
6215         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6216         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6217 
6218         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6219 
6220         /* init tx data */
6221         for_each_cos_in_tx_queue(fp, cos) {
6222                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6223                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6224                                   FP_COS_TO_TXQ(fp, cos, bp),
6225                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
6226                 cids[cos] = fp->txdata_ptr[cos]->cid;
6227         }
6228 
6229         /* nothing more for vf to do here */
6230         if (IS_VF(bp))
6231                 return;
6232 
6233         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6234                       fp->fw_sb_id, fp->igu_sb_id);
6235         bnx2x_update_fpsb_idx(fp);
6236         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6237                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6238                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6239 
6240         /**
6241          * Configure classification DBs: Always enable Tx switching
6242          */
6243         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6244 
6245         DP(NETIF_MSG_IFUP,
6246            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
6247            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6248            fp->igu_sb_id);
6249 }
6250 
6251 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6252 {
6253         int i;
6254 
6255         for (i = 1; i <= NUM_TX_RINGS; i++) {
6256                 struct eth_tx_next_bd *tx_next_bd =
6257                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6258 
6259                 tx_next_bd->addr_hi =
6260                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6261                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6262                 tx_next_bd->addr_lo =
6263                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6264                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6265         }
6266 
6267         *txdata->tx_cons_sb = cpu_to_le16(0);
6268 
6269         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6270         txdata->tx_db.data.zero_fill1 = 0;
6271         txdata->tx_db.data.prod = 0;
6272 
6273         txdata->tx_pkt_prod = 0;
6274         txdata->tx_pkt_cons = 0;
6275         txdata->tx_bd_prod = 0;
6276         txdata->tx_bd_cons = 0;
6277         txdata->tx_pkt = 0;
6278 }
6279 
6280 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6281 {
6282         int i;
6283 
6284         for_each_tx_queue_cnic(bp, i)
6285                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6286 }
6287 
6288 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6289 {
6290         int i;
6291         u8 cos;
6292 
6293         for_each_eth_queue(bp, i)
6294                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6295                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6296 }
6297 
6298 static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6299 {
6300         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6301         unsigned long q_type = 0;
6302 
6303         bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6304         bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6305                                                      BNX2X_FCOE_ETH_CL_ID_IDX);
6306         bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6307         bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6308         bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6309         bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6310         bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6311                           fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6312                           fp);
6313 
6314         DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6315 
6316         /* qZone id equals to FW (per path) client id */
6317         bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6318         /* init shortcut */
6319         bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6320                 bnx2x_rx_ustorm_prods_offset(fp);
6321 
6322         /* Configure Queue State object */
6323         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6324         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6325 
6326         /* No multi-CoS for FCoE L2 client */
6327         BUG_ON(fp->max_cos != 1);
6328 
6329         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6330                              &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6331                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6332 
6333         DP(NETIF_MSG_IFUP,
6334            "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %