Version:  2.0.40 2.2.26 2.4.37 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1

Linux/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

  1 /* bnx2x_main.c: Broadcom Everest network driver.
  2  *
  3  * Copyright (c) 2007-2013 Broadcom Corporation
  4  *
  5  * This program is free software; you can redistribute it and/or modify
  6  * it under the terms of the GNU General Public License as published by
  7  * the Free Software Foundation.
  8  *
  9  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
 10  * Written by: Eliezer Tamir
 11  * Based on code from Michael Chan's bnx2 driver
 12  * UDP CSUM errata workaround by Arik Gendelman
 13  * Slowpath and fastpath rework by Vladislav Zolotarov
 14  * Statistics and Link management by Yitchak Gertner
 15  *
 16  */
 17 
 18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 19 
 20 #include <linux/module.h>
 21 #include <linux/moduleparam.h>
 22 #include <linux/kernel.h>
 23 #include <linux/device.h>  /* for dev_info() */
 24 #include <linux/timer.h>
 25 #include <linux/errno.h>
 26 #include <linux/ioport.h>
 27 #include <linux/slab.h>
 28 #include <linux/interrupt.h>
 29 #include <linux/pci.h>
 30 #include <linux/aer.h>
 31 #include <linux/init.h>
 32 #include <linux/netdevice.h>
 33 #include <linux/etherdevice.h>
 34 #include <linux/skbuff.h>
 35 #include <linux/dma-mapping.h>
 36 #include <linux/bitops.h>
 37 #include <linux/irq.h>
 38 #include <linux/delay.h>
 39 #include <asm/byteorder.h>
 40 #include <linux/time.h>
 41 #include <linux/ethtool.h>
 42 #include <linux/mii.h>
 43 #include <linux/if_vlan.h>
 44 #include <linux/crash_dump.h>
 45 #include <net/ip.h>
 46 #include <net/ipv6.h>
 47 #include <net/tcp.h>
 48 #include <net/vxlan.h>
 49 #include <net/checksum.h>
 50 #include <net/ip6_checksum.h>
 51 #include <linux/workqueue.h>
 52 #include <linux/crc32.h>
 53 #include <linux/crc32c.h>
 54 #include <linux/prefetch.h>
 55 #include <linux/zlib.h>
 56 #include <linux/io.h>
 57 #include <linux/semaphore.h>
 58 #include <linux/stringify.h>
 59 #include <linux/vmalloc.h>
 60 
 61 #include "bnx2x.h"
 62 #include "bnx2x_init.h"
 63 #include "bnx2x_init_ops.h"
 64 #include "bnx2x_cmn.h"
 65 #include "bnx2x_vfpf.h"
 66 #include "bnx2x_dcb.h"
 67 #include "bnx2x_sp.h"
 68 #include <linux/firmware.h>
 69 #include "bnx2x_fw_file_hdr.h"
 70 /* FW files */
 71 #define FW_FILE_VERSION                                 \
 72         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
 73         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
 74         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
 75         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
 76 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
 77 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
 78 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
 79 
 80 /* Time in jiffies before concluding the transmitter is hung */
 81 #define TX_TIMEOUT              (5*HZ)
 82 
 83 static char version[] =
 84         "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
 85         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 86 
 87 MODULE_AUTHOR("Eliezer Tamir");
 88 MODULE_DESCRIPTION("Broadcom NetXtreme II "
 89                    "BCM57710/57711/57711E/"
 90                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
 91                    "57840/57840_MF Driver");
 92 MODULE_LICENSE("GPL");
 93 MODULE_VERSION(DRV_MODULE_VERSION);
 94 MODULE_FIRMWARE(FW_FILE_NAME_E1);
 95 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
 96 MODULE_FIRMWARE(FW_FILE_NAME_E2);
 97 
 98 int bnx2x_num_queues;
 99 module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
100 MODULE_PARM_DESC(num_queues,
101                  " Set number of queues (default is as a number of CPUs)");
102 
103 static int disable_tpa;
104 module_param(disable_tpa, int, S_IRUGO);
105 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
106 
107 static int int_mode;
108 module_param(int_mode, int, S_IRUGO);
109 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
110                                 "(1 INT#x; 2 MSI)");
111 
112 static int dropless_fc;
113 module_param(dropless_fc, int, S_IRUGO);
114 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
115 
116 static int mrrs = -1;
117 module_param(mrrs, int, S_IRUGO);
118 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
119 
120 static int debug;
121 module_param(debug, int, S_IRUGO);
122 MODULE_PARM_DESC(debug, " Default debug msglevel");
123 
124 static struct workqueue_struct *bnx2x_wq;
125 struct workqueue_struct *bnx2x_iov_wq;
126 
127 struct bnx2x_mac_vals {
128         u32 xmac_addr;
129         u32 xmac_val;
130         u32 emac_addr;
131         u32 emac_val;
132         u32 umac_addr[2];
133         u32 umac_val[2];
134         u32 bmac_addr;
135         u32 bmac_val[2];
136 };
137 
138 enum bnx2x_board_type {
139         BCM57710 = 0,
140         BCM57711,
141         BCM57711E,
142         BCM57712,
143         BCM57712_MF,
144         BCM57712_VF,
145         BCM57800,
146         BCM57800_MF,
147         BCM57800_VF,
148         BCM57810,
149         BCM57810_MF,
150         BCM57810_VF,
151         BCM57840_4_10,
152         BCM57840_2_20,
153         BCM57840_MF,
154         BCM57840_VF,
155         BCM57811,
156         BCM57811_MF,
157         BCM57840_O,
158         BCM57840_MFO,
159         BCM57811_VF
160 };
161 
162 /* indexed by board_type, above */
163 static struct {
164         char *name;
165 } board_info[] = {
166         [BCM57710]      = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
167         [BCM57711]      = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
168         [BCM57711E]     = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
169         [BCM57712]      = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
170         [BCM57712_MF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
171         [BCM57712_VF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
172         [BCM57800]      = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
173         [BCM57800_MF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
174         [BCM57800_VF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
175         [BCM57810]      = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
176         [BCM57810_MF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
177         [BCM57810_VF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
178         [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
179         [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
180         [BCM57840_MF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
181         [BCM57840_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
182         [BCM57811]      = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
183         [BCM57811_MF]   = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
184         [BCM57840_O]    = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
185         [BCM57840_MFO]  = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
186         [BCM57811_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
187 };
188 
189 #ifndef PCI_DEVICE_ID_NX2_57710
190 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
191 #endif
192 #ifndef PCI_DEVICE_ID_NX2_57711
193 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
194 #endif
195 #ifndef PCI_DEVICE_ID_NX2_57711E
196 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
197 #endif
198 #ifndef PCI_DEVICE_ID_NX2_57712
199 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
200 #endif
201 #ifndef PCI_DEVICE_ID_NX2_57712_MF
202 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
203 #endif
204 #ifndef PCI_DEVICE_ID_NX2_57712_VF
205 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
206 #endif
207 #ifndef PCI_DEVICE_ID_NX2_57800
208 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
209 #endif
210 #ifndef PCI_DEVICE_ID_NX2_57800_MF
211 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
212 #endif
213 #ifndef PCI_DEVICE_ID_NX2_57800_VF
214 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
215 #endif
216 #ifndef PCI_DEVICE_ID_NX2_57810
217 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
218 #endif
219 #ifndef PCI_DEVICE_ID_NX2_57810_MF
220 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
221 #endif
222 #ifndef PCI_DEVICE_ID_NX2_57840_O
223 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
224 #endif
225 #ifndef PCI_DEVICE_ID_NX2_57810_VF
226 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
227 #endif
228 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
229 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
230 #endif
231 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
232 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
233 #endif
234 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
235 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
236 #endif
237 #ifndef PCI_DEVICE_ID_NX2_57840_MF
238 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
239 #endif
240 #ifndef PCI_DEVICE_ID_NX2_57840_VF
241 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
242 #endif
243 #ifndef PCI_DEVICE_ID_NX2_57811
244 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
245 #endif
246 #ifndef PCI_DEVICE_ID_NX2_57811_MF
247 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
248 #endif
249 #ifndef PCI_DEVICE_ID_NX2_57811_VF
250 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
251 #endif
252 
253 static const struct pci_device_id bnx2x_pci_tbl[] = {
254         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
255         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
272         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
273         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
274         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
275         { 0 }
276 };
277 
278 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
279 
280 /* Global resources for unloading a previously loaded device */
281 #define BNX2X_PREV_WAIT_NEEDED 1
282 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
283 static LIST_HEAD(bnx2x_prev_list);
284 
285 /* Forward declaration */
286 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
287 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
288 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
289 
290 /****************************************************************************
291 * General service functions
292 ****************************************************************************/
293 
294 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
295 
296 static void __storm_memset_dma_mapping(struct bnx2x *bp,
297                                        u32 addr, dma_addr_t mapping)
298 {
299         REG_WR(bp,  addr, U64_LO(mapping));
300         REG_WR(bp,  addr + 4, U64_HI(mapping));
301 }
302 
303 static void storm_memset_spq_addr(struct bnx2x *bp,
304                                   dma_addr_t mapping, u16 abs_fid)
305 {
306         u32 addr = XSEM_REG_FAST_MEMORY +
307                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
308 
309         __storm_memset_dma_mapping(bp, addr, mapping);
310 }
311 
312 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
313                                   u16 pf_id)
314 {
315         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
316                 pf_id);
317         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
318                 pf_id);
319         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
320                 pf_id);
321         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
322                 pf_id);
323 }
324 
325 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
326                                  u8 enable)
327 {
328         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
329                 enable);
330         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
331                 enable);
332         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
333                 enable);
334         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
335                 enable);
336 }
337 
338 static void storm_memset_eq_data(struct bnx2x *bp,
339                                  struct event_ring_data *eq_data,
340                                 u16 pfid)
341 {
342         size_t size = sizeof(struct event_ring_data);
343 
344         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
345 
346         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
347 }
348 
349 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
350                                  u16 pfid)
351 {
352         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
353         REG_WR16(bp, addr, eq_prod);
354 }
355 
356 /* used only at init
357  * locking is done by mcp
358  */
359 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
360 {
361         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
362         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
363         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
364                                PCICFG_VENDOR_ID_OFFSET);
365 }
366 
367 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
368 {
369         u32 val;
370 
371         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
372         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
373         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
374                                PCICFG_VENDOR_ID_OFFSET);
375 
376         return val;
377 }
378 
379 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
380 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
381 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
382 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
383 #define DMAE_DP_DST_NONE        "dst_addr [none]"
384 
385 static void bnx2x_dp_dmae(struct bnx2x *bp,
386                           struct dmae_command *dmae, int msglvl)
387 {
388         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
389         int i;
390 
391         switch (dmae->opcode & DMAE_COMMAND_DST) {
392         case DMAE_CMD_DST_PCI:
393                 if (src_type == DMAE_CMD_SRC_PCI)
394                         DP(msglvl, "DMAE: opcode 0x%08x\n"
395                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
396                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
397                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
398                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
399                            dmae->comp_addr_hi, dmae->comp_addr_lo,
400                            dmae->comp_val);
401                 else
402                         DP(msglvl, "DMAE: opcode 0x%08x\n"
403                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
404                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
405                            dmae->opcode, dmae->src_addr_lo >> 2,
406                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
407                            dmae->comp_addr_hi, dmae->comp_addr_lo,
408                            dmae->comp_val);
409                 break;
410         case DMAE_CMD_DST_GRC:
411                 if (src_type == DMAE_CMD_SRC_PCI)
412                         DP(msglvl, "DMAE: opcode 0x%08x\n"
413                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
414                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
415                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
416                            dmae->len, dmae->dst_addr_lo >> 2,
417                            dmae->comp_addr_hi, dmae->comp_addr_lo,
418                            dmae->comp_val);
419                 else
420                         DP(msglvl, "DMAE: opcode 0x%08x\n"
421                            "src [%08x], len [%d*4], dst [%08x]\n"
422                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
423                            dmae->opcode, dmae->src_addr_lo >> 2,
424                            dmae->len, dmae->dst_addr_lo >> 2,
425                            dmae->comp_addr_hi, dmae->comp_addr_lo,
426                            dmae->comp_val);
427                 break;
428         default:
429                 if (src_type == DMAE_CMD_SRC_PCI)
430                         DP(msglvl, "DMAE: opcode 0x%08x\n"
431                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
432                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
433                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
434                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
435                            dmae->comp_val);
436                 else
437                         DP(msglvl, "DMAE: opcode 0x%08x\n"
438                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
439                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
440                            dmae->opcode, dmae->src_addr_lo >> 2,
441                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
442                            dmae->comp_val);
443                 break;
444         }
445 
446         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
447                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
448                    i, *(((u32 *)dmae) + i));
449 }
450 
451 /* copy command into DMAE command memory and set DMAE command go */
452 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
453 {
454         u32 cmd_offset;
455         int i;
456 
457         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
458         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
459                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
460         }
461         REG_WR(bp, dmae_reg_go_c[idx], 1);
462 }
463 
464 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
465 {
466         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
467                            DMAE_CMD_C_ENABLE);
468 }
469 
470 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
471 {
472         return opcode & ~DMAE_CMD_SRC_RESET;
473 }
474 
475 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
476                              bool with_comp, u8 comp_type)
477 {
478         u32 opcode = 0;
479 
480         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
481                    (dst_type << DMAE_COMMAND_DST_SHIFT));
482 
483         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
484 
485         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
486         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
487                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
488         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
489 
490 #ifdef __BIG_ENDIAN
491         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
492 #else
493         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
494 #endif
495         if (with_comp)
496                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
497         return opcode;
498 }
499 
500 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
501                                       struct dmae_command *dmae,
502                                       u8 src_type, u8 dst_type)
503 {
504         memset(dmae, 0, sizeof(struct dmae_command));
505 
506         /* set the opcode */
507         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
508                                          true, DMAE_COMP_PCI);
509 
510         /* fill in the completion parameters */
511         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
512         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
513         dmae->comp_val = DMAE_COMP_VAL;
514 }
515 
516 /* issue a dmae command over the init-channel and wait for completion */
517 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
518                                u32 *comp)
519 {
520         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
521         int rc = 0;
522 
523         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
524 
525         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
526          * as long as this code is called both from syscall context and
527          * from ndo_set_rx_mode() flow that may be called from BH.
528          */
529 
530         spin_lock_bh(&bp->dmae_lock);
531 
532         /* reset completion */
533         *comp = 0;
534 
535         /* post the command on the channel used for initializations */
536         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
537 
538         /* wait for completion */
539         udelay(5);
540         while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
541 
542                 if (!cnt ||
543                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
544                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
545                         BNX2X_ERR("DMAE timeout!\n");
546                         rc = DMAE_TIMEOUT;
547                         goto unlock;
548                 }
549                 cnt--;
550                 udelay(50);
551         }
552         if (*comp & DMAE_PCI_ERR_FLAG) {
553                 BNX2X_ERR("DMAE PCI error!\n");
554                 rc = DMAE_PCI_ERROR;
555         }
556 
557 unlock:
558 
559         spin_unlock_bh(&bp->dmae_lock);
560 
561         return rc;
562 }
563 
564 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
565                       u32 len32)
566 {
567         int rc;
568         struct dmae_command dmae;
569 
570         if (!bp->dmae_ready) {
571                 u32 *data = bnx2x_sp(bp, wb_data[0]);
572 
573                 if (CHIP_IS_E1(bp))
574                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
575                 else
576                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
577                 return;
578         }
579 
580         /* set opcode and fixed command fields */
581         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
582 
583         /* fill in addresses and len */
584         dmae.src_addr_lo = U64_LO(dma_addr);
585         dmae.src_addr_hi = U64_HI(dma_addr);
586         dmae.dst_addr_lo = dst_addr >> 2;
587         dmae.dst_addr_hi = 0;
588         dmae.len = len32;
589 
590         /* issue the command and wait for completion */
591         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
592         if (rc) {
593                 BNX2X_ERR("DMAE returned failure %d\n", rc);
594 #ifdef BNX2X_STOP_ON_ERROR
595                 bnx2x_panic();
596 #endif
597         }
598 }
599 
600 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
601 {
602         int rc;
603         struct dmae_command dmae;
604 
605         if (!bp->dmae_ready) {
606                 u32 *data = bnx2x_sp(bp, wb_data[0]);
607                 int i;
608 
609                 if (CHIP_IS_E1(bp))
610                         for (i = 0; i < len32; i++)
611                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
612                 else
613                         for (i = 0; i < len32; i++)
614                                 data[i] = REG_RD(bp, src_addr + i*4);
615 
616                 return;
617         }
618 
619         /* set opcode and fixed command fields */
620         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
621 
622         /* fill in addresses and len */
623         dmae.src_addr_lo = src_addr >> 2;
624         dmae.src_addr_hi = 0;
625         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
626         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
627         dmae.len = len32;
628 
629         /* issue the command and wait for completion */
630         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
631         if (rc) {
632                 BNX2X_ERR("DMAE returned failure %d\n", rc);
633 #ifdef BNX2X_STOP_ON_ERROR
634                 bnx2x_panic();
635 #endif
636         }
637 }
638 
639 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
640                                       u32 addr, u32 len)
641 {
642         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
643         int offset = 0;
644 
645         while (len > dmae_wr_max) {
646                 bnx2x_write_dmae(bp, phys_addr + offset,
647                                  addr + offset, dmae_wr_max);
648                 offset += dmae_wr_max * 4;
649                 len -= dmae_wr_max;
650         }
651 
652         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
653 }
654 
655 enum storms {
656            XSTORM,
657            TSTORM,
658            CSTORM,
659            USTORM,
660            MAX_STORMS
661 };
662 
663 #define STORMS_NUM 4
664 #define REGS_IN_ENTRY 4
665 
666 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
667                                               enum storms storm,
668                                               int entry)
669 {
670         switch (storm) {
671         case XSTORM:
672                 return XSTORM_ASSERT_LIST_OFFSET(entry);
673         case TSTORM:
674                 return TSTORM_ASSERT_LIST_OFFSET(entry);
675         case CSTORM:
676                 return CSTORM_ASSERT_LIST_OFFSET(entry);
677         case USTORM:
678                 return USTORM_ASSERT_LIST_OFFSET(entry);
679         case MAX_STORMS:
680         default:
681                 BNX2X_ERR("unknown storm\n");
682         }
683         return -EINVAL;
684 }
685 
686 static int bnx2x_mc_assert(struct bnx2x *bp)
687 {
688         char last_idx;
689         int i, j, rc = 0;
690         enum storms storm;
691         u32 regs[REGS_IN_ENTRY];
692         u32 bar_storm_intmem[STORMS_NUM] = {
693                 BAR_XSTRORM_INTMEM,
694                 BAR_TSTRORM_INTMEM,
695                 BAR_CSTRORM_INTMEM,
696                 BAR_USTRORM_INTMEM
697         };
698         u32 storm_assert_list_index[STORMS_NUM] = {
699                 XSTORM_ASSERT_LIST_INDEX_OFFSET,
700                 TSTORM_ASSERT_LIST_INDEX_OFFSET,
701                 CSTORM_ASSERT_LIST_INDEX_OFFSET,
702                 USTORM_ASSERT_LIST_INDEX_OFFSET
703         };
704         char *storms_string[STORMS_NUM] = {
705                 "XSTORM",
706                 "TSTORM",
707                 "CSTORM",
708                 "USTORM"
709         };
710 
711         for (storm = XSTORM; storm < MAX_STORMS; storm++) {
712                 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
713                                    storm_assert_list_index[storm]);
714                 if (last_idx)
715                         BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
716                                   storms_string[storm], last_idx);
717 
718                 /* print the asserts */
719                 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
720                         /* read a single assert entry */
721                         for (j = 0; j < REGS_IN_ENTRY; j++)
722                                 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
723                                           bnx2x_get_assert_list_entry(bp,
724                                                                       storm,
725                                                                       i) +
726                                           sizeof(u32) * j);
727 
728                         /* log entry if it contains a valid assert */
729                         if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
730                                 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
731                                           storms_string[storm], i, regs[3],
732                                           regs[2], regs[1], regs[0]);
733                                 rc++;
734                         } else {
735                                 break;
736                         }
737                 }
738         }
739 
740         BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
741                   CHIP_IS_E1(bp) ? "everest1" :
742                   CHIP_IS_E1H(bp) ? "everest1h" :
743                   CHIP_IS_E2(bp) ? "everest2" : "everest3",
744                   BCM_5710_FW_MAJOR_VERSION,
745                   BCM_5710_FW_MINOR_VERSION,
746                   BCM_5710_FW_REVISION_VERSION);
747 
748         return rc;
749 }
750 
751 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
752 #define SCRATCH_BUFFER_SIZE(bp) \
753         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
754 
755 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
756 {
757         u32 addr, val;
758         u32 mark, offset;
759         __be32 data[9];
760         int word;
761         u32 trace_shmem_base;
762         if (BP_NOMCP(bp)) {
763                 BNX2X_ERR("NO MCP - can not dump\n");
764                 return;
765         }
766         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
767                 (bp->common.bc_ver & 0xff0000) >> 16,
768                 (bp->common.bc_ver & 0xff00) >> 8,
769                 (bp->common.bc_ver & 0xff));
770 
771         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
772         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
773                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
774 
775         if (BP_PATH(bp) == 0)
776                 trace_shmem_base = bp->common.shmem_base;
777         else
778                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
779 
780         /* sanity */
781         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
782             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
783                                 SCRATCH_BUFFER_SIZE(bp)) {
784                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
785                           trace_shmem_base);
786                 return;
787         }
788 
789         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
790 
791         /* validate TRCB signature */
792         mark = REG_RD(bp, addr);
793         if (mark != MFW_TRACE_SIGNATURE) {
794                 BNX2X_ERR("Trace buffer signature is missing.");
795                 return ;
796         }
797 
798         /* read cyclic buffer pointer */
799         addr += 4;
800         mark = REG_RD(bp, addr);
801         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
802         if (mark >= trace_shmem_base || mark < addr + 4) {
803                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
804                 return;
805         }
806         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
807 
808         printk("%s", lvl);
809 
810         /* dump buffer after the mark */
811         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
812                 for (word = 0; word < 8; word++)
813                         data[word] = htonl(REG_RD(bp, offset + 4*word));
814                 data[8] = 0x0;
815                 pr_cont("%s", (char *)data);
816         }
817 
818         /* dump buffer before the mark */
819         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
820                 for (word = 0; word < 8; word++)
821                         data[word] = htonl(REG_RD(bp, offset + 4*word));
822                 data[8] = 0x0;
823                 pr_cont("%s", (char *)data);
824         }
825         printk("%s" "end of fw dump\n", lvl);
826 }
827 
828 static void bnx2x_fw_dump(struct bnx2x *bp)
829 {
830         bnx2x_fw_dump_lvl(bp, KERN_ERR);
831 }
832 
833 static void bnx2x_hc_int_disable(struct bnx2x *bp)
834 {
835         int port = BP_PORT(bp);
836         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
837         u32 val = REG_RD(bp, addr);
838 
839         /* in E1 we must use only PCI configuration space to disable
840          * MSI/MSIX capability
841          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
842          */
843         if (CHIP_IS_E1(bp)) {
844                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
845                  * Use mask register to prevent from HC sending interrupts
846                  * after we exit the function
847                  */
848                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
849 
850                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
851                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
852                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
853         } else
854                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
855                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
856                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
857                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
858 
859         DP(NETIF_MSG_IFDOWN,
860            "write %x to HC %d (addr 0x%x)\n",
861            val, port, addr);
862 
863         /* flush all outstanding writes */
864         mmiowb();
865 
866         REG_WR(bp, addr, val);
867         if (REG_RD(bp, addr) != val)
868                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
869 }
870 
871 static void bnx2x_igu_int_disable(struct bnx2x *bp)
872 {
873         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
874 
875         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
876                  IGU_PF_CONF_INT_LINE_EN |
877                  IGU_PF_CONF_ATTN_BIT_EN);
878 
879         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
880 
881         /* flush all outstanding writes */
882         mmiowb();
883 
884         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
885         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
886                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
887 }
888 
889 static void bnx2x_int_disable(struct bnx2x *bp)
890 {
891         if (bp->common.int_block == INT_BLOCK_HC)
892                 bnx2x_hc_int_disable(bp);
893         else
894                 bnx2x_igu_int_disable(bp);
895 }
896 
897 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
898 {
899         int i;
900         u16 j;
901         struct hc_sp_status_block_data sp_sb_data;
902         int func = BP_FUNC(bp);
903 #ifdef BNX2X_STOP_ON_ERROR
904         u16 start = 0, end = 0;
905         u8 cos;
906 #endif
907         if (IS_PF(bp) && disable_int)
908                 bnx2x_int_disable(bp);
909 
910         bp->stats_state = STATS_STATE_DISABLED;
911         bp->eth_stats.unrecoverable_error++;
912         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
913 
914         BNX2X_ERR("begin crash dump -----------------\n");
915 
916         /* Indices */
917         /* Common */
918         if (IS_PF(bp)) {
919                 struct host_sp_status_block *def_sb = bp->def_status_blk;
920                 int data_size, cstorm_offset;
921 
922                 BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
923                           bp->def_idx, bp->def_att_idx, bp->attn_state,
924                           bp->spq_prod_idx, bp->stats_counter);
925                 BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
926                           def_sb->atten_status_block.attn_bits,
927                           def_sb->atten_status_block.attn_bits_ack,
928                           def_sb->atten_status_block.status_block_id,
929                           def_sb->atten_status_block.attn_bits_index);
930                 BNX2X_ERR("     def (");
931                 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
932                         pr_cont("0x%x%s",
933                                 def_sb->sp_sb.index_values[i],
934                                 (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
935 
936                 data_size = sizeof(struct hc_sp_status_block_data) /
937                             sizeof(u32);
938                 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
939                 for (i = 0; i < data_size; i++)
940                         *((u32 *)&sp_sb_data + i) =
941                                 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
942                                            i * sizeof(u32));
943 
944                 pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
945                         sp_sb_data.igu_sb_id,
946                         sp_sb_data.igu_seg_id,
947                         sp_sb_data.p_func.pf_id,
948                         sp_sb_data.p_func.vnic_id,
949                         sp_sb_data.p_func.vf_id,
950                         sp_sb_data.p_func.vf_valid,
951                         sp_sb_data.state);
952         }
953 
954         for_each_eth_queue(bp, i) {
955                 struct bnx2x_fastpath *fp = &bp->fp[i];
956                 int loop;
957                 struct hc_status_block_data_e2 sb_data_e2;
958                 struct hc_status_block_data_e1x sb_data_e1x;
959                 struct hc_status_block_sm  *hc_sm_p =
960                         CHIP_IS_E1x(bp) ?
961                         sb_data_e1x.common.state_machine :
962                         sb_data_e2.common.state_machine;
963                 struct hc_index_data *hc_index_p =
964                         CHIP_IS_E1x(bp) ?
965                         sb_data_e1x.index_data :
966                         sb_data_e2.index_data;
967                 u8 data_size, cos;
968                 u32 *sb_data_p;
969                 struct bnx2x_fp_txdata txdata;
970 
971                 if (!bp->fp)
972                         break;
973 
974                 if (!fp->rx_cons_sb)
975                         continue;
976 
977                 /* Rx */
978                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
979                           i, fp->rx_bd_prod, fp->rx_bd_cons,
980                           fp->rx_comp_prod,
981                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
982                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
983                           fp->rx_sge_prod, fp->last_max_sge,
984                           le16_to_cpu(fp->fp_hc_idx));
985 
986                 /* Tx */
987                 for_each_cos_in_tx_queue(fp, cos)
988                 {
989                         if (!fp->txdata_ptr[cos])
990                                 break;
991 
992                         txdata = *fp->txdata_ptr[cos];
993 
994                         if (!txdata.tx_cons_sb)
995                                 continue;
996 
997                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
998                                   i, txdata.tx_pkt_prod,
999                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
1000                                   txdata.tx_bd_cons,
1001                                   le16_to_cpu(*txdata.tx_cons_sb));
1002                 }
1003 
1004                 loop = CHIP_IS_E1x(bp) ?
1005                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1006 
1007                 /* host sb data */
1008 
1009                 if (IS_FCOE_FP(fp))
1010                         continue;
1011 
1012                 BNX2X_ERR("     run indexes (");
1013                 for (j = 0; j < HC_SB_MAX_SM; j++)
1014                         pr_cont("0x%x%s",
1015                                fp->sb_running_index[j],
1016                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1017 
1018                 BNX2X_ERR("     indexes (");
1019                 for (j = 0; j < loop; j++)
1020                         pr_cont("0x%x%s",
1021                                fp->sb_index_values[j],
1022                                (j == loop - 1) ? ")" : " ");
1023 
1024                 /* VF cannot access FW refelection for status block */
1025                 if (IS_VF(bp))
1026                         continue;
1027 
1028                 /* fw sb data */
1029                 data_size = CHIP_IS_E1x(bp) ?
1030                         sizeof(struct hc_status_block_data_e1x) :
1031                         sizeof(struct hc_status_block_data_e2);
1032                 data_size /= sizeof(u32);
1033                 sb_data_p = CHIP_IS_E1x(bp) ?
1034                         (u32 *)&sb_data_e1x :
1035                         (u32 *)&sb_data_e2;
1036                 /* copy sb data in here */
1037                 for (j = 0; j < data_size; j++)
1038                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1039                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1040                                 j * sizeof(u32));
1041 
1042                 if (!CHIP_IS_E1x(bp)) {
1043                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1044                                 sb_data_e2.common.p_func.pf_id,
1045                                 sb_data_e2.common.p_func.vf_id,
1046                                 sb_data_e2.common.p_func.vf_valid,
1047                                 sb_data_e2.common.p_func.vnic_id,
1048                                 sb_data_e2.common.same_igu_sb_1b,
1049                                 sb_data_e2.common.state);
1050                 } else {
1051                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1052                                 sb_data_e1x.common.p_func.pf_id,
1053                                 sb_data_e1x.common.p_func.vf_id,
1054                                 sb_data_e1x.common.p_func.vf_valid,
1055                                 sb_data_e1x.common.p_func.vnic_id,
1056                                 sb_data_e1x.common.same_igu_sb_1b,
1057                                 sb_data_e1x.common.state);
1058                 }
1059 
1060                 /* SB_SMs data */
1061                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1062                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1063                                 j, hc_sm_p[j].__flags,
1064                                 hc_sm_p[j].igu_sb_id,
1065                                 hc_sm_p[j].igu_seg_id,
1066                                 hc_sm_p[j].time_to_expire,
1067                                 hc_sm_p[j].timer_value);
1068                 }
1069 
1070                 /* Indices data */
1071                 for (j = 0; j < loop; j++) {
1072                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1073                                hc_index_p[j].flags,
1074                                hc_index_p[j].timeout);
1075                 }
1076         }
1077 
1078 #ifdef BNX2X_STOP_ON_ERROR
1079         if (IS_PF(bp)) {
1080                 /* event queue */
1081                 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1082                 for (i = 0; i < NUM_EQ_DESC; i++) {
1083                         u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1084 
1085                         BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1086                                   i, bp->eq_ring[i].message.opcode,
1087                                   bp->eq_ring[i].message.error);
1088                         BNX2X_ERR("data: %x %x %x\n",
1089                                   data[0], data[1], data[2]);
1090                 }
1091         }
1092 
1093         /* Rings */
1094         /* Rx */
1095         for_each_valid_rx_queue(bp, i) {
1096                 struct bnx2x_fastpath *fp = &bp->fp[i];
1097 
1098                 if (!bp->fp)
1099                         break;
1100 
1101                 if (!fp->rx_cons_sb)
1102                         continue;
1103 
1104                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1105                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1106                 for (j = start; j != end; j = RX_BD(j + 1)) {
1107                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1108                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1109 
1110                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1111                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1112                 }
1113 
1114                 start = RX_SGE(fp->rx_sge_prod);
1115                 end = RX_SGE(fp->last_max_sge);
1116                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1117                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1118                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1119 
1120                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1121                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1122                 }
1123 
1124                 start = RCQ_BD(fp->rx_comp_cons - 10);
1125                 end = RCQ_BD(fp->rx_comp_cons + 503);
1126                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1127                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1128 
1129                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1130                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1131                 }
1132         }
1133 
1134         /* Tx */
1135         for_each_valid_tx_queue(bp, i) {
1136                 struct bnx2x_fastpath *fp = &bp->fp[i];
1137 
1138                 if (!bp->fp)
1139                         break;
1140 
1141                 for_each_cos_in_tx_queue(fp, cos) {
1142                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1143 
1144                         if (!fp->txdata_ptr[cos])
1145                                 break;
1146 
1147                         if (!txdata->tx_cons_sb)
1148                                 continue;
1149 
1150                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1151                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1152                         for (j = start; j != end; j = TX_BD(j + 1)) {
1153                                 struct sw_tx_bd *sw_bd =
1154                                         &txdata->tx_buf_ring[j];
1155 
1156                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1157                                           i, cos, j, sw_bd->skb,
1158                                           sw_bd->first_bd);
1159                         }
1160 
1161                         start = TX_BD(txdata->tx_bd_cons - 10);
1162                         end = TX_BD(txdata->tx_bd_cons + 254);
1163                         for (j = start; j != end; j = TX_BD(j + 1)) {
1164                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1165 
1166                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1167                                           i, cos, j, tx_bd[0], tx_bd[1],
1168                                           tx_bd[2], tx_bd[3]);
1169                         }
1170                 }
1171         }
1172 #endif
1173         if (IS_PF(bp)) {
1174                 bnx2x_fw_dump(bp);
1175                 bnx2x_mc_assert(bp);
1176         }
1177         BNX2X_ERR("end crash dump -----------------\n");
1178 }
1179 
1180 /*
1181  * FLR Support for E2
1182  *
1183  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1184  * initialization.
1185  */
1186 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1187 #define FLR_WAIT_INTERVAL       50      /* usec */
1188 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1189 
1190 struct pbf_pN_buf_regs {
1191         int pN;
1192         u32 init_crd;
1193         u32 crd;
1194         u32 crd_freed;
1195 };
1196 
1197 struct pbf_pN_cmd_regs {
1198         int pN;
1199         u32 lines_occup;
1200         u32 lines_freed;
1201 };
1202 
1203 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1204                                      struct pbf_pN_buf_regs *regs,
1205                                      u32 poll_count)
1206 {
1207         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1208         u32 cur_cnt = poll_count;
1209 
1210         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1211         crd = crd_start = REG_RD(bp, regs->crd);
1212         init_crd = REG_RD(bp, regs->init_crd);
1213 
1214         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1215         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1216         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1217 
1218         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1219                (init_crd - crd_start))) {
1220                 if (cur_cnt--) {
1221                         udelay(FLR_WAIT_INTERVAL);
1222                         crd = REG_RD(bp, regs->crd);
1223                         crd_freed = REG_RD(bp, regs->crd_freed);
1224                 } else {
1225                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1226                            regs->pN);
1227                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1228                            regs->pN, crd);
1229                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1230                            regs->pN, crd_freed);
1231                         break;
1232                 }
1233         }
1234         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1235            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1236 }
1237 
1238 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1239                                      struct pbf_pN_cmd_regs *regs,
1240                                      u32 poll_count)
1241 {
1242         u32 occup, to_free, freed, freed_start;
1243         u32 cur_cnt = poll_count;
1244 
1245         occup = to_free = REG_RD(bp, regs->lines_occup);
1246         freed = freed_start = REG_RD(bp, regs->lines_freed);
1247 
1248         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1249         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1250 
1251         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1252                 if (cur_cnt--) {
1253                         udelay(FLR_WAIT_INTERVAL);
1254                         occup = REG_RD(bp, regs->lines_occup);
1255                         freed = REG_RD(bp, regs->lines_freed);
1256                 } else {
1257                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1258                            regs->pN);
1259                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1260                            regs->pN, occup);
1261                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1262                            regs->pN, freed);
1263                         break;
1264                 }
1265         }
1266         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1267            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1268 }
1269 
1270 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1271                                     u32 expected, u32 poll_count)
1272 {
1273         u32 cur_cnt = poll_count;
1274         u32 val;
1275 
1276         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1277                 udelay(FLR_WAIT_INTERVAL);
1278 
1279         return val;
1280 }
1281 
1282 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1283                                     char *msg, u32 poll_cnt)
1284 {
1285         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1286         if (val != 0) {
1287                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1288                 return 1;
1289         }
1290         return 0;
1291 }
1292 
1293 /* Common routines with VF FLR cleanup */
1294 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1295 {
1296         /* adjust polling timeout */
1297         if (CHIP_REV_IS_EMUL(bp))
1298                 return FLR_POLL_CNT * 2000;
1299 
1300         if (CHIP_REV_IS_FPGA(bp))
1301                 return FLR_POLL_CNT * 120;
1302 
1303         return FLR_POLL_CNT;
1304 }
1305 
1306 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1307 {
1308         struct pbf_pN_cmd_regs cmd_regs[] = {
1309                 {0, (CHIP_IS_E3B0(bp)) ?
1310                         PBF_REG_TQ_OCCUPANCY_Q0 :
1311                         PBF_REG_P0_TQ_OCCUPANCY,
1312                     (CHIP_IS_E3B0(bp)) ?
1313                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1314                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1315                 {1, (CHIP_IS_E3B0(bp)) ?
1316                         PBF_REG_TQ_OCCUPANCY_Q1 :
1317                         PBF_REG_P1_TQ_OCCUPANCY,
1318                     (CHIP_IS_E3B0(bp)) ?
1319                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1320                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1321                 {4, (CHIP_IS_E3B0(bp)) ?
1322                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1323                         PBF_REG_P4_TQ_OCCUPANCY,
1324                     (CHIP_IS_E3B0(bp)) ?
1325                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1326                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1327         };
1328 
1329         struct pbf_pN_buf_regs buf_regs[] = {
1330                 {0, (CHIP_IS_E3B0(bp)) ?
1331                         PBF_REG_INIT_CRD_Q0 :
1332                         PBF_REG_P0_INIT_CRD ,
1333                     (CHIP_IS_E3B0(bp)) ?
1334                         PBF_REG_CREDIT_Q0 :
1335                         PBF_REG_P0_CREDIT,
1336                     (CHIP_IS_E3B0(bp)) ?
1337                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1338                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1339                 {1, (CHIP_IS_E3B0(bp)) ?
1340                         PBF_REG_INIT_CRD_Q1 :
1341                         PBF_REG_P1_INIT_CRD,
1342                     (CHIP_IS_E3B0(bp)) ?
1343                         PBF_REG_CREDIT_Q1 :
1344                         PBF_REG_P1_CREDIT,
1345                     (CHIP_IS_E3B0(bp)) ?
1346                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1347                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1348                 {4, (CHIP_IS_E3B0(bp)) ?
1349                         PBF_REG_INIT_CRD_LB_Q :
1350                         PBF_REG_P4_INIT_CRD,
1351                     (CHIP_IS_E3B0(bp)) ?
1352                         PBF_REG_CREDIT_LB_Q :
1353                         PBF_REG_P4_CREDIT,
1354                     (CHIP_IS_E3B0(bp)) ?
1355                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1356                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1357         };
1358 
1359         int i;
1360 
1361         /* Verify the command queues are flushed P0, P1, P4 */
1362         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1363                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1364 
1365         /* Verify the transmission buffers are flushed P0, P1, P4 */
1366         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1367                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1368 }
1369 
1370 #define OP_GEN_PARAM(param) \
1371         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1372 
1373 #define OP_GEN_TYPE(type) \
1374         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1375 
1376 #define OP_GEN_AGG_VECT(index) \
1377         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1378 
1379 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1380 {
1381         u32 op_gen_command = 0;
1382         u32 comp_addr = BAR_CSTRORM_INTMEM +
1383                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1384         int ret = 0;
1385 
1386         if (REG_RD(bp, comp_addr)) {
1387                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1388                 return 1;
1389         }
1390 
1391         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1392         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1393         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1394         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1395 
1396         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1397         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1398 
1399         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1400                 BNX2X_ERR("FW final cleanup did not succeed\n");
1401                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1402                    (REG_RD(bp, comp_addr)));
1403                 bnx2x_panic();
1404                 return 1;
1405         }
1406         /* Zero completion for next FLR */
1407         REG_WR(bp, comp_addr, 0);
1408 
1409         return ret;
1410 }
1411 
1412 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1413 {
1414         u16 status;
1415 
1416         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1417         return status & PCI_EXP_DEVSTA_TRPND;
1418 }
1419 
1420 /* PF FLR specific routines
1421 */
1422 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1423 {
1424         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1425         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1426                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1427                         "CFC PF usage counter timed out",
1428                         poll_cnt))
1429                 return 1;
1430 
1431         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1432         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1433                         DORQ_REG_PF_USAGE_CNT,
1434                         "DQ PF usage counter timed out",
1435                         poll_cnt))
1436                 return 1;
1437 
1438         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1439         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1440                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1441                         "QM PF usage counter timed out",
1442                         poll_cnt))
1443                 return 1;
1444 
1445         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1446         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1447                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1448                         "Timers VNIC usage counter timed out",
1449                         poll_cnt))
1450                 return 1;
1451         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1452                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1453                         "Timers NUM_SCANS usage counter timed out",
1454                         poll_cnt))
1455                 return 1;
1456 
1457         /* Wait DMAE PF usage counter to zero */
1458         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1459                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1460                         "DMAE command register timed out",
1461                         poll_cnt))
1462                 return 1;
1463 
1464         return 0;
1465 }
1466 
1467 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1468 {
1469         u32 val;
1470 
1471         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1472         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1473 
1474         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1475         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1476 
1477         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1478         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1479 
1480         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1481         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1482 
1483         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1484         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1485 
1486         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1487         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1488 
1489         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1490         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1491 
1492         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1493         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1494            val);
1495 }
1496 
1497 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1498 {
1499         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1500 
1501         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1502 
1503         /* Re-enable PF target read access */
1504         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1505 
1506         /* Poll HW usage counters */
1507         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1508         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1509                 return -EBUSY;
1510 
1511         /* Zero the igu 'trailing edge' and 'leading edge' */
1512 
1513         /* Send the FW cleanup command */
1514         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1515                 return -EBUSY;
1516 
1517         /* ATC cleanup */
1518 
1519         /* Verify TX hw is flushed */
1520         bnx2x_tx_hw_flushed(bp, poll_cnt);
1521 
1522         /* Wait 100ms (not adjusted according to platform) */
1523         msleep(100);
1524 
1525         /* Verify no pending pci transactions */
1526         if (bnx2x_is_pcie_pending(bp->pdev))
1527                 BNX2X_ERR("PCIE Transactions still pending\n");
1528 
1529         /* Debug */
1530         bnx2x_hw_enable_status(bp);
1531 
1532         /*
1533          * Master enable - Due to WB DMAE writes performed before this
1534          * register is re-initialized as part of the regular function init
1535          */
1536         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1537 
1538         return 0;
1539 }
1540 
1541 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1542 {
1543         int port = BP_PORT(bp);
1544         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1545         u32 val = REG_RD(bp, addr);
1546         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1547         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1548         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1549 
1550         if (msix) {
1551                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1552                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1553                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1554                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1555                 if (single_msix)
1556                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1557         } else if (msi) {
1558                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1559                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1560                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1561                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1562         } else {
1563                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1564                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1565                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1566                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1567 
1568                 if (!CHIP_IS_E1(bp)) {
1569                         DP(NETIF_MSG_IFUP,
1570                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1571 
1572                         REG_WR(bp, addr, val);
1573 
1574                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1575                 }
1576         }
1577 
1578         if (CHIP_IS_E1(bp))
1579                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1580 
1581         DP(NETIF_MSG_IFUP,
1582            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1583            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1584 
1585         REG_WR(bp, addr, val);
1586         /*
1587          * Ensure that HC_CONFIG is written before leading/trailing edge config
1588          */
1589         mmiowb();
1590         barrier();
1591 
1592         if (!CHIP_IS_E1(bp)) {
1593                 /* init leading/trailing edge */
1594                 if (IS_MF(bp)) {
1595                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1596                         if (bp->port.pmf)
1597                                 /* enable nig and gpio3 attention */
1598                                 val |= 0x1100;
1599                 } else
1600                         val = 0xffff;
1601 
1602                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1603                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1604         }
1605 
1606         /* Make sure that interrupts are indeed enabled from here on */
1607         mmiowb();
1608 }
1609 
1610 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1611 {
1612         u32 val;
1613         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1614         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1615         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1616 
1617         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1618 
1619         if (msix) {
1620                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1621                          IGU_PF_CONF_SINGLE_ISR_EN);
1622                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1623                         IGU_PF_CONF_ATTN_BIT_EN);
1624 
1625                 if (single_msix)
1626                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1627         } else if (msi) {
1628                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1629                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1630                         IGU_PF_CONF_ATTN_BIT_EN |
1631                         IGU_PF_CONF_SINGLE_ISR_EN);
1632         } else {
1633                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1634                 val |= (IGU_PF_CONF_INT_LINE_EN |
1635                         IGU_PF_CONF_ATTN_BIT_EN |
1636                         IGU_PF_CONF_SINGLE_ISR_EN);
1637         }
1638 
1639         /* Clean previous status - need to configure igu prior to ack*/
1640         if ((!msix) || single_msix) {
1641                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1642                 bnx2x_ack_int(bp);
1643         }
1644 
1645         val |= IGU_PF_CONF_FUNC_EN;
1646 
1647         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1648            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1649 
1650         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1651 
1652         if (val & IGU_PF_CONF_INT_LINE_EN)
1653                 pci_intx(bp->pdev, true);
1654 
1655         barrier();
1656 
1657         /* init leading/trailing edge */
1658         if (IS_MF(bp)) {
1659                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1660                 if (bp->port.pmf)
1661                         /* enable nig and gpio3 attention */
1662                         val |= 0x1100;
1663         } else
1664                 val = 0xffff;
1665 
1666         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1667         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1668 
1669         /* Make sure that interrupts are indeed enabled from here on */
1670         mmiowb();
1671 }
1672 
1673 void bnx2x_int_enable(struct bnx2x *bp)
1674 {
1675         if (bp->common.int_block == INT_BLOCK_HC)
1676                 bnx2x_hc_int_enable(bp);
1677         else
1678                 bnx2x_igu_int_enable(bp);
1679 }
1680 
1681 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1682 {
1683         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1684         int i, offset;
1685 
1686         if (disable_hw)
1687                 /* prevent the HW from sending interrupts */
1688                 bnx2x_int_disable(bp);
1689 
1690         /* make sure all ISRs are done */
1691         if (msix) {
1692                 synchronize_irq(bp->msix_table[0].vector);
1693                 offset = 1;
1694                 if (CNIC_SUPPORT(bp))
1695                         offset++;
1696                 for_each_eth_queue(bp, i)
1697                         synchronize_irq(bp->msix_table[offset++].vector);
1698         } else
1699                 synchronize_irq(bp->pdev->irq);
1700 
1701         /* make sure sp_task is not running */
1702         cancel_delayed_work(&bp->sp_task);
1703         cancel_delayed_work(&bp->period_task);
1704         flush_workqueue(bnx2x_wq);
1705 }
1706 
1707 /* fast path */
1708 
1709 /*
1710  * General service functions
1711  */
1712 
1713 /* Return true if succeeded to acquire the lock */
1714 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1715 {
1716         u32 lock_status;
1717         u32 resource_bit = (1 << resource);
1718         int func = BP_FUNC(bp);
1719         u32 hw_lock_control_reg;
1720 
1721         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1722            "Trying to take a lock on resource %d\n", resource);
1723 
1724         /* Validating that the resource is within range */
1725         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1726                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1727                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1728                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1729                 return false;
1730         }
1731 
1732         if (func <= 5)
1733                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1734         else
1735                 hw_lock_control_reg =
1736                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1737 
1738         /* Try to acquire the lock */
1739         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1740         lock_status = REG_RD(bp, hw_lock_control_reg);
1741         if (lock_status & resource_bit)
1742                 return true;
1743 
1744         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1745            "Failed to get a lock on resource %d\n", resource);
1746         return false;
1747 }
1748 
1749 /**
1750  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1751  *
1752  * @bp: driver handle
1753  *
1754  * Returns the recovery leader resource id according to the engine this function
1755  * belongs to. Currently only only 2 engines is supported.
1756  */
1757 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1758 {
1759         if (BP_PATH(bp))
1760                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1761         else
1762                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1763 }
1764 
1765 /**
1766  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1767  *
1768  * @bp: driver handle
1769  *
1770  * Tries to acquire a leader lock for current engine.
1771  */
1772 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1773 {
1774         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1775 }
1776 
1777 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1778 
1779 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1780 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1781 {
1782         /* Set the interrupt occurred bit for the sp-task to recognize it
1783          * must ack the interrupt and transition according to the IGU
1784          * state machine.
1785          */
1786         atomic_set(&bp->interrupt_occurred, 1);
1787 
1788         /* The sp_task must execute only after this bit
1789          * is set, otherwise we will get out of sync and miss all
1790          * further interrupts. Hence, the barrier.
1791          */
1792         smp_wmb();
1793 
1794         /* schedule sp_task to workqueue */
1795         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1796 }
1797 
1798 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1799 {
1800         struct bnx2x *bp = fp->bp;
1801         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1802         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1803         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1804         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1805 
1806         DP(BNX2X_MSG_SP,
1807            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1808            fp->index, cid, command, bp->state,
1809            rr_cqe->ramrod_cqe.ramrod_type);
1810 
1811         /* If cid is within VF range, replace the slowpath object with the
1812          * one corresponding to this VF
1813          */
1814         if (cid >= BNX2X_FIRST_VF_CID  &&
1815             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1816                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1817 
1818         switch (command) {
1819         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1820                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1821                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1822                 break;
1823 
1824         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1825                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1826                 drv_cmd = BNX2X_Q_CMD_SETUP;
1827                 break;
1828 
1829         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1830                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1831                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1832                 break;
1833 
1834         case (RAMROD_CMD_ID_ETH_HALT):
1835                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1836                 drv_cmd = BNX2X_Q_CMD_HALT;
1837                 break;
1838 
1839         case (RAMROD_CMD_ID_ETH_TERMINATE):
1840                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1841                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1842                 break;
1843 
1844         case (RAMROD_CMD_ID_ETH_EMPTY):
1845                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1846                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1847                 break;
1848 
1849         case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1850                 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1851                 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1852                 break;
1853 
1854         default:
1855                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1856                           command, fp->index);
1857                 return;
1858         }
1859 
1860         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1861             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1862                 /* q_obj->complete_cmd() failure means that this was
1863                  * an unexpected completion.
1864                  *
1865                  * In this case we don't want to increase the bp->spq_left
1866                  * because apparently we haven't sent this command the first
1867                  * place.
1868                  */
1869 #ifdef BNX2X_STOP_ON_ERROR
1870                 bnx2x_panic();
1871 #else
1872                 return;
1873 #endif
1874 
1875         smp_mb__before_atomic();
1876         atomic_inc(&bp->cq_spq_left);
1877         /* push the change in bp->spq_left and towards the memory */
1878         smp_mb__after_atomic();
1879 
1880         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1881 
1882         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1883             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1884                 /* if Q update ramrod is completed for last Q in AFEX vif set
1885                  * flow, then ACK MCP at the end
1886                  *
1887                  * mark pending ACK to MCP bit.
1888                  * prevent case that both bits are cleared.
1889                  * At the end of load/unload driver checks that
1890                  * sp_state is cleared, and this order prevents
1891                  * races
1892                  */
1893                 smp_mb__before_atomic();
1894                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1895                 wmb();
1896                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1897                 smp_mb__after_atomic();
1898 
1899                 /* schedule the sp task as mcp ack is required */
1900                 bnx2x_schedule_sp_task(bp);
1901         }
1902 
1903         return;
1904 }
1905 
1906 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1907 {
1908         struct bnx2x *bp = netdev_priv(dev_instance);
1909         u16 status = bnx2x_ack_int(bp);
1910         u16 mask;
1911         int i;
1912         u8 cos;
1913 
1914         /* Return here if interrupt is shared and it's not for us */
1915         if (unlikely(status == 0)) {
1916                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1917                 return IRQ_NONE;
1918         }
1919         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1920 
1921 #ifdef BNX2X_STOP_ON_ERROR
1922         if (unlikely(bp->panic))
1923                 return IRQ_HANDLED;
1924 #endif
1925 
1926         for_each_eth_queue(bp, i) {
1927                 struct bnx2x_fastpath *fp = &bp->fp[i];
1928 
1929                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1930                 if (status & mask) {
1931                         /* Handle Rx or Tx according to SB id */
1932                         for_each_cos_in_tx_queue(fp, cos)
1933                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1934                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1935                         napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1936                         status &= ~mask;
1937                 }
1938         }
1939 
1940         if (CNIC_SUPPORT(bp)) {
1941                 mask = 0x2;
1942                 if (status & (mask | 0x1)) {
1943                         struct cnic_ops *c_ops = NULL;
1944 
1945                         rcu_read_lock();
1946                         c_ops = rcu_dereference(bp->cnic_ops);
1947                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1948                                       CNIC_DRV_STATE_HANDLES_IRQ))
1949                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1950                         rcu_read_unlock();
1951 
1952                         status &= ~mask;
1953                 }
1954         }
1955 
1956         if (unlikely(status & 0x1)) {
1957 
1958                 /* schedule sp task to perform default status block work, ack
1959                  * attentions and enable interrupts.
1960                  */
1961                 bnx2x_schedule_sp_task(bp);
1962 
1963                 status &= ~0x1;
1964                 if (!status)
1965                         return IRQ_HANDLED;
1966         }
1967 
1968         if (unlikely(status))
1969                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1970                    status);
1971 
1972         return IRQ_HANDLED;
1973 }
1974 
1975 /* Link */
1976 
1977 /*
1978  * General service functions
1979  */
1980 
1981 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1982 {
1983         u32 lock_status;
1984         u32 resource_bit = (1 << resource);
1985         int func = BP_FUNC(bp);
1986         u32 hw_lock_control_reg;
1987         int cnt;
1988 
1989         /* Validating that the resource is within range */
1990         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1991                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1992                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1993                 return -EINVAL;
1994         }
1995 
1996         if (func <= 5) {
1997                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1998         } else {
1999                 hw_lock_control_reg =
2000                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2001         }
2002 
2003         /* Validating that the resource is not already taken */
2004         lock_status = REG_RD(bp, hw_lock_control_reg);
2005         if (lock_status & resource_bit) {
2006                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
2007                    lock_status, resource_bit);
2008                 return -EEXIST;
2009         }
2010 
2011         /* Try for 5 second every 5ms */
2012         for (cnt = 0; cnt < 1000; cnt++) {
2013                 /* Try to acquire the lock */
2014                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2015                 lock_status = REG_RD(bp, hw_lock_control_reg);
2016                 if (lock_status & resource_bit)
2017                         return 0;
2018 
2019                 usleep_range(5000, 10000);
2020         }
2021         BNX2X_ERR("Timeout\n");
2022         return -EAGAIN;
2023 }
2024 
2025 int bnx2x_release_leader_lock(struct bnx2x *bp)
2026 {
2027         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2028 }
2029 
2030 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2031 {
2032         u32 lock_status;
2033         u32 resource_bit = (1 << resource);
2034         int func = BP_FUNC(bp);
2035         u32 hw_lock_control_reg;
2036 
2037         /* Validating that the resource is within range */
2038         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2039                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2040                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
2041                 return -EINVAL;
2042         }
2043 
2044         if (func <= 5) {
2045                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2046         } else {
2047                 hw_lock_control_reg =
2048                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2049         }
2050 
2051         /* Validating that the resource is currently taken */
2052         lock_status = REG_RD(bp, hw_lock_control_reg);
2053         if (!(lock_status & resource_bit)) {
2054                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2055                           lock_status, resource_bit);
2056                 return -EFAULT;
2057         }
2058 
2059         REG_WR(bp, hw_lock_control_reg, resource_bit);
2060         return 0;
2061 }
2062 
2063 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2064 {
2065         /* The GPIO should be swapped if swap register is set and active */
2066         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2067                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2068         int gpio_shift = gpio_num +
2069                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2070         u32 gpio_mask = (1 << gpio_shift);
2071         u32 gpio_reg;
2072         int value;
2073 
2074         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2075                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2076                 return -EINVAL;
2077         }
2078 
2079         /* read GPIO value */
2080         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2081 
2082         /* get the requested pin value */
2083         if ((gpio_reg & gpio_mask) == gpio_mask)
2084                 value = 1;
2085         else
2086                 value = 0;
2087 
2088         return value;
2089 }
2090 
2091 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2092 {
2093         /* The GPIO should be swapped if swap register is set and active */
2094         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2095                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2096         int gpio_shift = gpio_num +
2097                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2098         u32 gpio_mask = (1 << gpio_shift);
2099         u32 gpio_reg;
2100 
2101         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2102                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2103                 return -EINVAL;
2104         }
2105 
2106         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2107         /* read GPIO and mask except the float bits */
2108         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2109 
2110         switch (mode) {
2111         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2112                 DP(NETIF_MSG_LINK,
2113                    "Set GPIO %d (shift %d) -> output low\n",
2114                    gpio_num, gpio_shift);
2115                 /* clear FLOAT and set CLR */
2116                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2117                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2118                 break;
2119 
2120         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2121                 DP(NETIF_MSG_LINK,
2122                    "Set GPIO %d (shift %d) -> output high\n",
2123                    gpio_num, gpio_shift);
2124                 /* clear FLOAT and set SET */
2125                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2126                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2127                 break;
2128 
2129         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2130                 DP(NETIF_MSG_LINK,
2131                    "Set GPIO %d (shift %d) -> input\n",
2132                    gpio_num, gpio_shift);
2133                 /* set FLOAT */
2134                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2135                 break;
2136 
2137         default:
2138                 break;
2139         }
2140 
2141         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2142         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2143 
2144         return 0;
2145 }
2146 
2147 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2148 {
2149         u32 gpio_reg = 0;
2150         int rc = 0;
2151 
2152         /* Any port swapping should be handled by caller. */
2153 
2154         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2155         /* read GPIO and mask except the float bits */
2156         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2157         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2158         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2159         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2160 
2161         switch (mode) {
2162         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2163                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2164                 /* set CLR */
2165                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2166                 break;
2167 
2168         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2169                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2170                 /* set SET */
2171                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2172                 break;
2173 
2174         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2175                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2176                 /* set FLOAT */
2177                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2178                 break;
2179 
2180         default:
2181                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2182                 rc = -EINVAL;
2183                 break;
2184         }
2185 
2186         if (rc == 0)
2187                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2188 
2189         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2190 
2191         return rc;
2192 }
2193 
2194 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2195 {
2196         /* The GPIO should be swapped if swap register is set and active */
2197         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2198                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2199         int gpio_shift = gpio_num +
2200                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2201         u32 gpio_mask = (1 << gpio_shift);
2202         u32 gpio_reg;
2203 
2204         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2205                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2206                 return -EINVAL;
2207         }
2208 
2209         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2210         /* read GPIO int */
2211         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2212 
2213         switch (mode) {
2214         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2215                 DP(NETIF_MSG_LINK,
2216                    "Clear GPIO INT %d (shift %d) -> output low\n",
2217                    gpio_num, gpio_shift);
2218                 /* clear SET and set CLR */
2219                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2220                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2221                 break;
2222 
2223         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2224                 DP(NETIF_MSG_LINK,
2225                    "Set GPIO INT %d (shift %d) -> output high\n",
2226                    gpio_num, gpio_shift);
2227                 /* clear CLR and set SET */
2228                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2229                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2230                 break;
2231 
2232         default:
2233                 break;
2234         }
2235 
2236         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2237         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2238 
2239         return 0;
2240 }
2241 
2242 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2243 {
2244         u32 spio_reg;
2245 
2246         /* Only 2 SPIOs are configurable */
2247         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2248                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2249                 return -EINVAL;
2250         }
2251 
2252         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2253         /* read SPIO and mask except the float bits */
2254         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2255 
2256         switch (mode) {
2257         case MISC_SPIO_OUTPUT_LOW:
2258                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2259                 /* clear FLOAT and set CLR */
2260                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2261                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2262                 break;
2263 
2264         case MISC_SPIO_OUTPUT_HIGH:
2265                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2266                 /* clear FLOAT and set SET */
2267                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2268                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2269                 break;
2270 
2271         case MISC_SPIO_INPUT_HI_Z:
2272                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2273                 /* set FLOAT */
2274                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2275                 break;
2276 
2277         default:
2278                 break;
2279         }
2280 
2281         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2282         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2283 
2284         return 0;
2285 }
2286 
2287 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2288 {
2289         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2290         switch (bp->link_vars.ieee_fc &
2291                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2292         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2293                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2294                                                    ADVERTISED_Pause);
2295                 break;
2296 
2297         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2298                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2299                                                   ADVERTISED_Pause);
2300                 break;
2301 
2302         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2303                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2304                 break;
2305 
2306         default:
2307                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2308                                                    ADVERTISED_Pause);
2309                 break;
2310         }
2311 }
2312 
2313 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2314 {
2315         /* Initialize link parameters structure variables
2316          * It is recommended to turn off RX FC for jumbo frames
2317          *  for better performance
2318          */
2319         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2320                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2321         else
2322                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2323 }
2324 
2325 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2326 {
2327         u32 pause_enabled = 0;
2328 
2329         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2330                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2331                         pause_enabled = 1;
2332 
2333                 REG_WR(bp, BAR_USTRORM_INTMEM +
2334                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2335                        pause_enabled);
2336         }
2337 
2338         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2339            pause_enabled ? "enabled" : "disabled");
2340 }
2341 
2342 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2343 {
2344         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2345         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2346 
2347         if (!BP_NOMCP(bp)) {
2348                 bnx2x_set_requested_fc(bp);
2349                 bnx2x_acquire_phy_lock(bp);
2350 
2351                 if (load_mode == LOAD_DIAG) {
2352                         struct link_params *lp = &bp->link_params;
2353                         lp->loopback_mode = LOOPBACK_XGXS;
2354                         /* do PHY loopback at 10G speed, if possible */
2355                         if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2356                                 if (lp->speed_cap_mask[cfx_idx] &
2357                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2358                                         lp->req_line_speed[cfx_idx] =
2359                                         SPEED_10000;
2360                                 else
2361                                         lp->req_line_speed[cfx_idx] =
2362                                         SPEED_1000;
2363                         }
2364                 }
2365 
2366                 if (load_mode == LOAD_LOOPBACK_EXT) {
2367                         struct link_params *lp = &bp->link_params;
2368                         lp->loopback_mode = LOOPBACK_EXT;
2369                 }
2370 
2371                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2372 
2373                 bnx2x_release_phy_lock(bp);
2374 
2375                 bnx2x_init_dropless_fc(bp);
2376 
2377                 bnx2x_calc_fc_adv(bp);
2378 
2379                 if (bp->link_vars.link_up) {
2380                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2381                         bnx2x_link_report(bp);
2382                 }
2383                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2384                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2385                 return rc;
2386         }
2387         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2388         return -EINVAL;
2389 }
2390 
2391 void bnx2x_link_set(struct bnx2x *bp)
2392 {
2393         if (!BP_NOMCP(bp)) {
2394                 bnx2x_acquire_phy_lock(bp);
2395                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2396                 bnx2x_release_phy_lock(bp);
2397 
2398                 bnx2x_init_dropless_fc(bp);
2399 
2400                 bnx2x_calc_fc_adv(bp);
2401         } else
2402                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2403 }
2404 
2405 static void bnx2x__link_reset(struct bnx2x *bp)
2406 {
2407         if (!BP_NOMCP(bp)) {
2408                 bnx2x_acquire_phy_lock(bp);
2409                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2410                 bnx2x_release_phy_lock(bp);
2411         } else
2412                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2413 }
2414 
2415 void bnx2x_force_link_reset(struct bnx2x *bp)
2416 {
2417         bnx2x_acquire_phy_lock(bp);
2418         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2419         bnx2x_release_phy_lock(bp);
2420 }
2421 
2422 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2423 {
2424         u8 rc = 0;
2425 
2426         if (!BP_NOMCP(bp)) {
2427                 bnx2x_acquire_phy_lock(bp);
2428                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2429                                      is_serdes);
2430                 bnx2x_release_phy_lock(bp);
2431         } else
2432                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2433 
2434         return rc;
2435 }
2436 
2437 /* Calculates the sum of vn_min_rates.
2438    It's needed for further normalizing of the min_rates.
2439    Returns:
2440      sum of vn_min_rates.
2441        or
2442      0 - if all the min_rates are 0.
2443      In the later case fairness algorithm should be deactivated.
2444      If not all min_rates are zero then those that are zeroes will be set to 1.
2445  */
2446 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2447                                       struct cmng_init_input *input)
2448 {
2449         int all_zero = 1;
2450         int vn;
2451 
2452         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2453                 u32 vn_cfg = bp->mf_config[vn];
2454                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2455                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2456 
2457                 /* Skip hidden vns */
2458                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2459                         vn_min_rate = 0;
2460                 /* If min rate is zero - set it to 1 */
2461                 else if (!vn_min_rate)
2462                         vn_min_rate = DEF_MIN_RATE;
2463                 else
2464                         all_zero = 0;
2465 
2466                 input->vnic_min_rate[vn] = vn_min_rate;
2467         }
2468 
2469         /* if ETS or all min rates are zeros - disable fairness */
2470         if (BNX2X_IS_ETS_ENABLED(bp)) {
2471                 input->flags.cmng_enables &=
2472                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2473                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2474         } else if (all_zero) {
2475                 input->flags.cmng_enables &=
2476                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2477                 DP(NETIF_MSG_IFUP,
2478                    "All MIN values are zeroes fairness will be disabled\n");
2479         } else
2480                 input->flags.cmng_enables |=
2481                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2482 }
2483 
2484 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2485                                     struct cmng_init_input *input)
2486 {
2487         u16 vn_max_rate;
2488         u32 vn_cfg = bp->mf_config[vn];
2489 
2490         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2491                 vn_max_rate = 0;
2492         else {
2493                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2494 
2495                 if (IS_MF_SI(bp)) {
2496                         /* maxCfg in percents of linkspeed */
2497                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2498                 } else /* SD modes */
2499                         /* maxCfg is absolute in 100Mb units */
2500                         vn_max_rate = maxCfg * 100;
2501         }
2502 
2503         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2504 
2505         input->vnic_max_rate[vn] = vn_max_rate;
2506 }
2507 
2508 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2509 {
2510         if (CHIP_REV_IS_SLOW(bp))
2511                 return CMNG_FNS_NONE;
2512         if (IS_MF(bp))
2513                 return CMNG_FNS_MINMAX;
2514 
2515         return CMNG_FNS_NONE;
2516 }
2517 
2518 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2519 {
2520         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2521 
2522         if (BP_NOMCP(bp))
2523                 return; /* what should be the default value in this case */
2524 
2525         /* For 2 port configuration the absolute function number formula
2526          * is:
2527          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2528          *
2529          *      and there are 4 functions per port
2530          *
2531          * For 4 port configuration it is
2532          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2533          *
2534          *      and there are 2 functions per port
2535          */
2536         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2537                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2538 
2539                 if (func >= E1H_FUNC_MAX)
2540                         break;
2541 
2542                 bp->mf_config[vn] =
2543                         MF_CFG_RD(bp, func_mf_config[func].config);
2544         }
2545         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2546                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2547                 bp->flags |= MF_FUNC_DIS;
2548         } else {
2549                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2550                 bp->flags &= ~MF_FUNC_DIS;
2551         }
2552 }
2553 
2554 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2555 {
2556         struct cmng_init_input input;
2557         memset(&input, 0, sizeof(struct cmng_init_input));
2558 
2559         input.port_rate = bp->link_vars.line_speed;
2560 
2561         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2562                 int vn;
2563 
2564                 /* read mf conf from shmem */
2565                 if (read_cfg)
2566                         bnx2x_read_mf_cfg(bp);
2567 
2568                 /* vn_weight_sum and enable fairness if not 0 */
2569                 bnx2x_calc_vn_min(bp, &input);
2570 
2571                 /* calculate and set min-max rate for each vn */
2572                 if (bp->port.pmf)
2573                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2574                                 bnx2x_calc_vn_max(bp, vn, &input);
2575 
2576                 /* always enable rate shaping and fairness */
2577                 input.flags.cmng_enables |=
2578                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2579 
2580                 bnx2x_init_cmng(&input, &bp->cmng);
2581                 return;
2582         }
2583 
2584         /* rate shaping and fairness are disabled */
2585         DP(NETIF_MSG_IFUP,
2586            "rate shaping and fairness are disabled\n");
2587 }
2588 
2589 static void storm_memset_cmng(struct bnx2x *bp,
2590                               struct cmng_init *cmng,
2591                               u8 port)
2592 {
2593         int vn;
2594         size_t size = sizeof(struct cmng_struct_per_port);
2595 
2596         u32 addr = BAR_XSTRORM_INTMEM +
2597                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2598 
2599         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2600 
2601         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2602                 int func = func_by_vn(bp, vn);
2603 
2604                 addr = BAR_XSTRORM_INTMEM +
2605                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2606                 size = sizeof(struct rate_shaping_vars_per_vn);
2607                 __storm_memset_struct(bp, addr, size,
2608                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2609 
2610                 addr = BAR_XSTRORM_INTMEM +
2611                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2612                 size = sizeof(struct fairness_vars_per_vn);
2613                 __storm_memset_struct(bp, addr, size,
2614                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2615         }
2616 }
2617 
2618 /* init cmng mode in HW according to local configuration */
2619 void bnx2x_set_local_cmng(struct bnx2x *bp)
2620 {
2621         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2622 
2623         if (cmng_fns != CMNG_FNS_NONE) {
2624                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2625                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2626         } else {
2627                 /* rate shaping and fairness are disabled */
2628                 DP(NETIF_MSG_IFUP,
2629                    "single function mode without fairness\n");
2630         }
2631 }
2632 
2633 /* This function is called upon link interrupt */
2634 static void bnx2x_link_attn(struct bnx2x *bp)
2635 {
2636         /* Make sure that we are synced with the current statistics */
2637         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2638 
2639         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2640 
2641         bnx2x_init_dropless_fc(bp);
2642 
2643         if (bp->link_vars.link_up) {
2644 
2645                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2646                         struct host_port_stats *pstats;
2647 
2648                         pstats = bnx2x_sp(bp, port_stats);
2649                         /* reset old mac stats */
2650                         memset(&(pstats->mac_stx[0]), 0,
2651                                sizeof(struct mac_stx));
2652                 }
2653                 if (bp->state == BNX2X_STATE_OPEN)
2654                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2655         }
2656 
2657         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2658                 bnx2x_set_local_cmng(bp);
2659 
2660         __bnx2x_link_report(bp);
2661 
2662         if (IS_MF(bp))
2663                 bnx2x_link_sync_notify(bp);
2664 }
2665 
2666 void bnx2x__link_status_update(struct bnx2x *bp)
2667 {
2668         if (bp->state != BNX2X_STATE_OPEN)
2669                 return;
2670 
2671         /* read updated dcb configuration */
2672         if (IS_PF(bp)) {
2673                 bnx2x_dcbx_pmf_update(bp);
2674                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2675                 if (bp->link_vars.link_up)
2676                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2677                 else
2678                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2679                         /* indicate link status */
2680                 bnx2x_link_report(bp);
2681 
2682         } else { /* VF */
2683                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2684                                           SUPPORTED_10baseT_Full |
2685                                           SUPPORTED_100baseT_Half |
2686                                           SUPPORTED_100baseT_Full |
2687                                           SUPPORTED_1000baseT_Full |
2688                                           SUPPORTED_2500baseX_Full |
2689                                           SUPPORTED_10000baseT_Full |
2690                                           SUPPORTED_TP |
2691                                           SUPPORTED_FIBRE |
2692                                           SUPPORTED_Autoneg |
2693                                           SUPPORTED_Pause |
2694                                           SUPPORTED_Asym_Pause);
2695                 bp->port.advertising[0] = bp->port.supported[0];
2696 
2697                 bp->link_params.bp = bp;
2698                 bp->link_params.port = BP_PORT(bp);
2699                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2700                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2701                 bp->link_params.req_line_speed[0] = SPEED_10000;
2702                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2703                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2704                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2705                 bp->link_vars.line_speed = SPEED_10000;
2706                 bp->link_vars.link_status =
2707                         (LINK_STATUS_LINK_UP |
2708                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2709                 bp->link_vars.link_up = 1;
2710                 bp->link_vars.duplex = DUPLEX_FULL;
2711                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2712                 __bnx2x_link_report(bp);
2713 
2714                 bnx2x_sample_bulletin(bp);
2715 
2716                 /* if bulletin board did not have an update for link status
2717                  * __bnx2x_link_report will report current status
2718                  * but it will NOT duplicate report in case of already reported
2719                  * during sampling bulletin board.
2720                  */
2721                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2722         }
2723 }
2724 
2725 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2726                                   u16 vlan_val, u8 allowed_prio)
2727 {
2728         struct bnx2x_func_state_params func_params = {NULL};
2729         struct bnx2x_func_afex_update_params *f_update_params =
2730                 &func_params.params.afex_update;
2731 
2732         func_params.f_obj = &bp->func_obj;
2733         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2734 
2735         /* no need to wait for RAMROD completion, so don't
2736          * set RAMROD_COMP_WAIT flag
2737          */
2738 
2739         f_update_params->vif_id = vifid;
2740         f_update_params->afex_default_vlan = vlan_val;
2741         f_update_params->allowed_priorities = allowed_prio;
2742 
2743         /* if ramrod can not be sent, response to MCP immediately */
2744         if (bnx2x_func_state_change(bp, &func_params) < 0)
2745                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2746 
2747         return 0;
2748 }
2749 
2750 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2751                                           u16 vif_index, u8 func_bit_map)
2752 {
2753         struct bnx2x_func_state_params func_params = {NULL};
2754         struct bnx2x_func_afex_viflists_params *update_params =
2755                 &func_params.params.afex_viflists;
2756         int rc;
2757         u32 drv_msg_code;
2758 
2759         /* validate only LIST_SET and LIST_GET are received from switch */
2760         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2761                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2762                           cmd_type);
2763 
2764         func_params.f_obj = &bp->func_obj;
2765         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2766 
2767         /* set parameters according to cmd_type */
2768         update_params->afex_vif_list_command = cmd_type;
2769         update_params->vif_list_index = vif_index;
2770         update_params->func_bit_map =
2771                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2772         update_params->func_to_clear = 0;
2773         drv_msg_code =
2774                 (cmd_type == VIF_LIST_RULE_GET) ?
2775                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2776                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2777 
2778         /* if ramrod can not be sent, respond to MCP immediately for
2779          * SET and GET requests (other are not triggered from MCP)
2780          */
2781         rc = bnx2x_func_state_change(bp, &func_params);
2782         if (rc < 0)
2783                 bnx2x_fw_command(bp, drv_msg_code, 0);
2784 
2785         return 0;
2786 }
2787 
2788 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2789 {
2790         struct afex_stats afex_stats;
2791         u32 func = BP_ABS_FUNC(bp);
2792         u32 mf_config;
2793         u16 vlan_val;
2794         u32 vlan_prio;
2795         u16 vif_id;
2796         u8 allowed_prio;
2797         u8 vlan_mode;
2798         u32 addr_to_write, vifid, addrs, stats_type, i;
2799 
2800         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2801                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2802                 DP(BNX2X_MSG_MCP,
2803                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2804                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2805         }
2806 
2807         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2808                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2809                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2810                 DP(BNX2X_MSG_MCP,
2811                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2812                    vifid, addrs);
2813                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2814                                                addrs);
2815         }
2816 
2817         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2818                 addr_to_write = SHMEM2_RD(bp,
2819                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2820                 stats_type = SHMEM2_RD(bp,
2821                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2822 
2823                 DP(BNX2X_MSG_MCP,
2824                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2825                    addr_to_write);
2826 
2827                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2828 
2829                 /* write response to scratchpad, for MCP */
2830                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2831                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2832                                *(((u32 *)(&afex_stats))+i));
2833 
2834                 /* send ack message to MCP */
2835                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2836         }
2837 
2838         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2839                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2840                 bp->mf_config[BP_VN(bp)] = mf_config;
2841                 DP(BNX2X_MSG_MCP,
2842                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2843                    mf_config);
2844 
2845                 /* if VIF_SET is "enabled" */
2846                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2847                         /* set rate limit directly to internal RAM */
2848                         struct cmng_init_input cmng_input;
2849                         struct rate_shaping_vars_per_vn m_rs_vn;
2850                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2851                         u32 addr = BAR_XSTRORM_INTMEM +
2852                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2853 
2854                         bp->mf_config[BP_VN(bp)] = mf_config;
2855 
2856                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2857                         m_rs_vn.vn_counter.rate =
2858                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2859                         m_rs_vn.vn_counter.quota =
2860                                 (m_rs_vn.vn_counter.rate *
2861                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2862 
2863                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2864 
2865                         /* read relevant values from mf_cfg struct in shmem */
2866                         vif_id =
2867                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2868                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2869                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2870                         vlan_val =
2871                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2872                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2873                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2874                         vlan_prio = (mf_config &
2875                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2876                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2877                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2878                         vlan_mode =
2879                                 (MF_CFG_RD(bp,
2880                                            func_mf_config[func].afex_config) &
2881                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2882                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2883                         allowed_prio =
2884                                 (MF_CFG_RD(bp,
2885                                            func_mf_config[func].afex_config) &
2886                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2887                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2888 
2889                         /* send ramrod to FW, return in case of failure */
2890                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2891                                                    allowed_prio))
2892                                 return;
2893 
2894                         bp->afex_def_vlan_tag = vlan_val;
2895                         bp->afex_vlan_mode = vlan_mode;
2896                 } else {
2897                         /* notify link down because BP->flags is disabled */
2898                         bnx2x_link_report(bp);
2899 
2900                         /* send INVALID VIF ramrod to FW */
2901                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2902 
2903                         /* Reset the default afex VLAN */
2904                         bp->afex_def_vlan_tag = -1;
2905                 }
2906         }
2907 }
2908 
2909 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2910 {
2911         struct bnx2x_func_switch_update_params *switch_update_params;
2912         struct bnx2x_func_state_params func_params;
2913 
2914         memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2915         switch_update_params = &func_params.params.switch_update;
2916         func_params.f_obj = &bp->func_obj;
2917         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2918 
2919         if (IS_MF_UFP(bp)) {
2920                 int func = BP_ABS_FUNC(bp);
2921                 u32 val;
2922 
2923                 /* Re-learn the S-tag from shmem */
2924                 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2925                                 FUNC_MF_CFG_E1HOV_TAG_MASK;
2926                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2927                         bp->mf_ov = val;
2928                 } else {
2929                         BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2930                         goto fail;
2931                 }
2932 
2933                 /* Configure new S-tag in LLH */
2934                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2935                        bp->mf_ov);
2936 
2937                 /* Send Ramrod to update FW of change */
2938                 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2939                           &switch_update_params->changes);
2940                 switch_update_params->vlan = bp->mf_ov;
2941 
2942                 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2943                         BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2944                                   bp->mf_ov);
2945                         goto fail;
2946                 }
2947 
2948                 DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n", bp->mf_ov);
2949 
2950                 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2951 
2952                 return;
2953         }
2954 
2955         /* not supported by SW yet */
2956 fail:
2957         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2958 }
2959 
2960 static void bnx2x_pmf_update(struct bnx2x *bp)
2961 {
2962         int port = BP_PORT(bp);
2963         u32 val;
2964 
2965         bp->port.pmf = 1;
2966         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2967 
2968         /*
2969          * We need the mb() to ensure the ordering between the writing to
2970          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2971          */
2972         smp_mb();
2973 
2974         /* queue a periodic task */
2975         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2976 
2977         bnx2x_dcbx_pmf_update(bp);
2978 
2979         /* enable nig attention */
2980         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2981         if (bp->common.int_block == INT_BLOCK_HC) {
2982                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2983                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2984         } else if (!CHIP_IS_E1x(bp)) {
2985                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2986                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2987         }
2988 
2989         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2990 }
2991 
2992 /* end of Link */
2993 
2994 /* slow path */
2995 
2996 /*
2997  * General service functions
2998  */
2999 
3000 /* send the MCP a request, block until there is a reply */
3001 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
3002 {
3003         int mb_idx = BP_FW_MB_IDX(bp);
3004         u32 seq;
3005         u32 rc = 0;
3006         u32 cnt = 1;
3007         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3008 
3009         mutex_lock(&bp->fw_mb_mutex);
3010         seq = ++bp->fw_seq;
3011         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3012         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3013 
3014         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3015                         (command | seq), param);
3016 
3017         do {
3018                 /* let the FW do it's magic ... */
3019                 msleep(delay);
3020 
3021                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
3022 
3023                 /* Give the FW up to 5 second (500*10ms) */
3024         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
3025 
3026         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3027            cnt*delay, rc, seq);
3028 
3029         /* is this a reply to our command? */
3030         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3031                 rc &= FW_MSG_CODE_MASK;
3032         else {
3033                 /* FW BUG! */
3034                 BNX2X_ERR("FW failed to respond!\n");
3035                 bnx2x_fw_dump(bp);
3036                 rc = 0;
3037         }
3038         mutex_unlock(&bp->fw_mb_mutex);
3039 
3040         return rc;
3041 }
3042 
3043 static void storm_memset_func_cfg(struct bnx2x *bp,
3044                                  struct tstorm_eth_function_common_config *tcfg,
3045                                  u16 abs_fid)
3046 {
3047         size_t size = sizeof(struct tstorm_eth_function_common_config);
3048 
3049         u32 addr = BAR_TSTRORM_INTMEM +
3050                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3051 
3052         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3053 }
3054 
3055 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3056 {
3057         if (CHIP_IS_E1x(bp)) {
3058                 struct tstorm_eth_function_common_config tcfg = {0};
3059 
3060                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3061         }
3062 
3063         /* Enable the function in the FW */
3064         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3065         storm_memset_func_en(bp, p->func_id, 1);
3066 
3067         /* spq */
3068         if (p->func_flgs & FUNC_FLG_SPQ) {
3069                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3070                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3071                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3072         }
3073 }
3074 
3075 /**
3076  * bnx2x_get_common_flags - Return common flags
3077  *
3078  * @bp          device handle
3079  * @fp          queue handle
3080  * @zero_stats  TRUE if statistics zeroing is needed
3081  *
3082  * Return the flags that are common for the Tx-only and not normal connections.
3083  */
3084 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3085                                             struct bnx2x_fastpath *fp,
3086                                             bool zero_stats)
3087 {
3088         unsigned long flags = 0;
3089 
3090         /* PF driver will always initialize the Queue to an ACTIVE state */
3091         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3092 
3093         /* tx only connections collect statistics (on the same index as the
3094          * parent connection). The statistics are zeroed when the parent
3095          * connection is initialized.
3096          */
3097 
3098         __set_bit(BNX2X_Q_FLG_STATS, &flags);
3099         if (zero_stats)
3100                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3101 
3102         if (bp->flags & TX_SWITCHING)
3103                 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3104 
3105         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3106         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3107 
3108 #ifdef BNX2X_STOP_ON_ERROR
3109         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3110 #endif
3111 
3112         return flags;
3113 }
3114 
3115 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3116                                        struct bnx2x_fastpath *fp,
3117                                        bool leading)
3118 {
3119         unsigned long flags = 0;
3120 
3121         /* calculate other queue flags */
3122         if (IS_MF_SD(bp))
3123                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3124 
3125         if (IS_FCOE_FP(fp)) {
3126                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3127                 /* For FCoE - force usage of default priority (for afex) */
3128                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3129         }
3130 
3131         if (fp->mode != TPA_MODE_DISABLED) {
3132                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3133                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3134                 if (fp->mode == TPA_MODE_GRO)
3135                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3136         }
3137 
3138         if (leading) {
3139                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3140                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3141         }
3142 
3143         /* Always set HW VLAN stripping */
3144         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3145 
3146         /* configure silent vlan removal */
3147         if (IS_MF_AFEX(bp))
3148                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3149 
3150         return flags | bnx2x_get_common_flags(bp, fp, true);
3151 }
3152 
3153 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3154         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3155         u8 cos)
3156 {
3157         gen_init->stat_id = bnx2x_stats_id(fp);
3158         gen_init->spcl_id = fp->cl_id;
3159 
3160         /* Always use mini-jumbo MTU for FCoE L2 ring */
3161         if (IS_FCOE_FP(fp))
3162                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3163         else
3164                 gen_init->mtu = bp->dev->mtu;
3165 
3166         gen_init->cos = cos;
3167 
3168         gen_init->fp_hsi = ETH_FP_HSI_VERSION;
3169 }
3170 
3171 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3172         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3173         struct bnx2x_rxq_setup_params *rxq_init)
3174 {
3175         u8 max_sge = 0;
3176         u16 sge_sz = 0;
3177         u16 tpa_agg_size = 0;
3178 
3179         if (fp->mode != TPA_MODE_DISABLED) {
3180                 pause->sge_th_lo = SGE_TH_LO(bp);
3181                 pause->sge_th_hi = SGE_TH_HI(bp);
3182 
3183                 /* validate SGE ring has enough to cross high threshold */
3184                 WARN_ON(bp->dropless_fc &&
3185                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3186                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3187 
3188                 tpa_agg_size = TPA_AGG_SIZE;
3189                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3190                         SGE_PAGE_SHIFT;
3191                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3192                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3193                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3194         }
3195 
3196         /* pause - not for e1 */
3197         if (!CHIP_IS_E1(bp)) {
3198                 pause->bd_th_lo = BD_TH_LO(bp);
3199                 pause->bd_th_hi = BD_TH_HI(bp);
3200 
3201                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3202                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3203                 /*
3204                  * validate that rings have enough entries to cross
3205                  * high thresholds
3206                  */
3207                 WARN_ON(bp->dropless_fc &&
3208                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3209                                 bp->rx_ring_size);
3210                 WARN_ON(bp->dropless_fc &&
3211                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3212                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3213 
3214                 pause->pri_map = 1;
3215         }
3216 
3217         /* rxq setup */
3218         rxq_init->dscr_map = fp->rx_desc_mapping;
3219         rxq_init->sge_map = fp->rx_sge_mapping;
3220         rxq_init->rcq_map = fp->rx_comp_mapping;
3221         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3222 
3223         /* This should be a maximum number of data bytes that may be
3224          * placed on the BD (not including paddings).
3225          */
3226         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3227                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3228 
3229         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3230         rxq_init->tpa_agg_sz = tpa_agg_size;
3231         rxq_init->sge_buf_sz = sge_sz;
3232         rxq_init->max_sges_pkt = max_sge;
3233         rxq_init->rss_engine_id = BP_FUNC(bp);
3234         rxq_init->mcast_engine_id = BP_FUNC(bp);
3235 
3236         /* Maximum number or simultaneous TPA aggregation for this Queue.
3237          *
3238          * For PF Clients it should be the maximum available number.
3239          * VF driver(s) may want to define it to a smaller value.
3240          */
3241         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3242 
3243         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3244         rxq_init->fw_sb_id = fp->fw_sb_id;
3245 
3246         if (IS_FCOE_FP(fp))
3247                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3248         else
3249                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3250         /* configure silent vlan removal
3251          * if multi function mode is afex, then mask default vlan
3252          */
3253         if (IS_MF_AFEX(bp)) {
3254                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3255                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3256         }
3257 }
3258 
3259 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3260         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3261         u8 cos)
3262 {
3263         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3264         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3265         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3266         txq_init->fw_sb_id = fp->fw_sb_id;
3267 
3268         /*
3269          * set the tss leading client id for TX classification ==
3270          * leading RSS client id
3271          */
3272         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3273 
3274         if (IS_FCOE_FP(fp)) {
3275                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3276                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3277         }
3278 }
3279 
3280 static void bnx2x_pf_init(struct bnx2x *bp)
3281 {
3282         struct bnx2x_func_init_params func_init = {0};
3283         struct event_ring_data eq_data = { {0} };
3284         u16 flags;
3285 
3286         if (!CHIP_IS_E1x(bp)) {
3287                 /* reset IGU PF statistics: MSIX + ATTN */
3288                 /* PF */
3289                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3290                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3291                            (CHIP_MODE_IS_4_PORT(bp) ?
3292                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3293                 /* ATTN */
3294                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3295                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3296                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3297                            (CHIP_MODE_IS_4_PORT(bp) ?
3298                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3299         }
3300 
3301         /* function setup flags */
3302         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3303 
3304         /* This flag is relevant for E1x only.
3305          * E2 doesn't have a TPA configuration in a function level.
3306          */
3307         flags |= (bp->dev->features & NETIF_F_LRO) ? FUNC_FLG_TPA : 0;
3308 
3309         func_init.func_flgs = flags;
3310         func_init.pf_id = BP_FUNC(bp);
3311         func_init.func_id = BP_FUNC(bp);
3312         func_init.spq_map = bp->spq_mapping;
3313         func_init.spq_prod = bp->spq_prod_idx;
3314 
3315         bnx2x_func_init(bp, &func_init);
3316 
3317         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3318 
3319         /*
3320          * Congestion management values depend on the link rate
3321          * There is no active link so initial link rate is set to 10 Gbps.
3322          * When the link comes up The congestion management values are
3323          * re-calculated according to the actual link rate.
3324          */
3325         bp->link_vars.line_speed = SPEED_10000;
3326         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3327 
3328         /* Only the PMF sets the HW */
3329         if (bp->port.pmf)
3330                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3331 
3332         /* init Event Queue - PCI bus guarantees correct endianity*/
3333         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3334         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3335         eq_data.producer = bp->eq_prod;
3336         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3337         eq_data.sb_id = DEF_SB_ID;
3338         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3339 }
3340 
3341 static void bnx2x_e1h_disable(struct bnx2x *bp)
3342 {
3343         int port = BP_PORT(bp);
3344 
3345         bnx2x_tx_disable(bp);
3346 
3347         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3348 }
3349 
3350 static void bnx2x_e1h_enable(struct bnx2x *bp)
3351 {
3352         int port = BP_PORT(bp);
3353 
3354         if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3355                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3356 
3357         /* Tx queue should be only re-enabled */
3358         netif_tx_wake_all_queues(bp->dev);
3359 
3360         /*
3361          * Should not call netif_carrier_on since it will be called if the link
3362          * is up when checking for link state
3363          */
3364 }
3365 
3366 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3367 
3368 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3369 {
3370         struct eth_stats_info *ether_stat =
3371                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3372         struct bnx2x_vlan_mac_obj *mac_obj =
3373                 &bp->sp_objs->mac_obj;
3374         int i;
3375 
3376         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3377                 ETH_STAT_INFO_VERSION_LEN);
3378 
3379         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3380          * mac_local field in ether_stat struct. The base address is offset by 2
3381          * bytes to account for the field being 8 bytes but a mac address is
3382          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3383          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3384          * allocated by the ether_stat struct, so the macs will land in their
3385          * proper positions.
3386          */
3387         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3388                 memset(ether_stat->mac_local + i, 0,
3389                        sizeof(ether_stat->mac_local[0]));
3390         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3391                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3392                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3393                                 ETH_ALEN);
3394         ether_stat->mtu_size = bp->dev->mtu;
3395         if (bp->dev->features & NETIF_F_RXCSUM)
3396                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3397         if (bp->dev->features & NETIF_F_TSO)
3398                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3399         ether_stat->feature_flags |= bp->common.boot_mode;
3400 
3401         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3402 
3403         ether_stat->txq_size = bp->tx_ring_size;
3404         ether_stat->rxq_size = bp->rx_ring_size;
3405 
3406 #ifdef CONFIG_BNX2X_SRIOV
3407         ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3408 #endif
3409 }
3410 
3411 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3412 {
3413         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3414         struct fcoe_stats_info *fcoe_stat =
3415                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3416 
3417         if (!CNIC_LOADED(bp))
3418                 return;
3419 
3420         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3421 
3422         fcoe_stat->qos_priority =
3423                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3424 
3425         /* insert FCoE stats from ramrod response */
3426         if (!NO_FCOE(bp)) {
3427                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3428                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3429                         tstorm_queue_statistics;
3430 
3431                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3432                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3433                         xstorm_queue_statistics;
3434 
3435                 struct fcoe_statistics_params *fw_fcoe_stat =
3436                         &bp->fw_stats_data->fcoe;
3437 
3438                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3439                           fcoe_stat->rx_bytes_lo,
3440                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3441 
3442                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3443                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3444                           fcoe_stat->rx_bytes_lo,
3445                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3446 
3447                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3448                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3449                           fcoe_stat->rx_bytes_lo,
3450                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3451 
3452                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3453                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3454                           fcoe_stat->rx_bytes_lo,
3455                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3456 
3457                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3458                           fcoe_stat->rx_frames_lo,
3459                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3460 
3461                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3462                           fcoe_stat->rx_frames_lo,
3463                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3464 
3465                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3466                           fcoe_stat->rx_frames_lo,
3467                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3468 
3469                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3470                           fcoe_stat->rx_frames_lo,
3471                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3472 
3473                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3474                           fcoe_stat->tx_bytes_lo,
3475                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3476 
3477                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3478                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3479                           fcoe_stat->tx_bytes_lo,
3480                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3481 
3482                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3483                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3484                           fcoe_stat->tx_bytes_lo,
3485                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3486 
3487                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3488                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3489                           fcoe_stat->tx_bytes_lo,
3490                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3491 
3492                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3493                           fcoe_stat->tx_frames_lo,
3494                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3495 
3496                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3497                           fcoe_stat->tx_frames_lo,
3498                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3499 
3500                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3501                           fcoe_stat->tx_frames_lo,
3502                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3503 
3504                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3505                           fcoe_stat->tx_frames_lo,
3506                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3507         }
3508 
3509         /* ask L5 driver to add data to the struct */
3510         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3511 }
3512 
3513 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3514 {
3515         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3516         struct iscsi_stats_info *iscsi_stat =
3517                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3518 
3519         if (!CNIC_LOADED(bp))
3520                 return;
3521 
3522         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3523                ETH_ALEN);
3524 
3525         iscsi_stat->qos_priority =
3526                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3527 
3528         /* ask L5 driver to add data to the struct */
3529         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3530 }
3531 
3532 /* called due to MCP event (on pmf):
3533  *      reread new bandwidth configuration
3534  *      configure FW
3535  *      notify others function about the change
3536  */
3537 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3538 {
3539         if (bp->link_vars.link_up) {
3540                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3541                 bnx2x_link_sync_notify(bp);
3542         }
3543         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3544 }
3545 
3546 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3547 {
3548         bnx2x_config_mf_bw(bp);
3549         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3550 }
3551 
3552 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3553 {
3554         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3555         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3556 }
3557 
3558 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH        (20)
3559 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT         (25)
3560 
3561 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3562 {
3563         enum drv_info_opcode op_code;
3564         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3565         bool release = false;
3566         int wait;
3567 
3568         /* if drv_info version supported by MFW doesn't match - send NACK */
3569         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3570                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3571                 return;
3572         }
3573 
3574         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3575                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3576 
3577         /* Must prevent other flows from accessing drv_info_to_mcp */
3578         mutex_lock(&bp->drv_info_mutex);
3579 
3580         memset(&bp->slowpath->drv_info_to_mcp, 0,
3581                sizeof(union drv_info_to_mcp));
3582 
3583         switch (op_code) {
3584         case ETH_STATS_OPCODE:
3585                 bnx2x_drv_info_ether_stat(bp);
3586                 break;
3587         case FCOE_STATS_OPCODE:
3588                 bnx2x_drv_info_fcoe_stat(bp);
3589                 break;
3590         case ISCSI_STATS_OPCODE:
3591                 bnx2x_drv_info_iscsi_stat(bp);
3592                 break;
3593         default:
3594                 /* if op code isn't supported - send NACK */
3595                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3596                 goto out;
3597         }
3598 
3599         /* if we got drv_info attn from MFW then these fields are defined in
3600          * shmem2 for sure
3601          */
3602         SHMEM2_WR(bp, drv_info_host_addr_lo,
3603                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3604         SHMEM2_WR(bp, drv_info_host_addr_hi,
3605                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3606 
3607         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3608 
3609         /* Since possible management wants both this and get_driver_version
3610          * need to wait until management notifies us it finished utilizing
3611          * the buffer.
3612          */
3613         if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3614                 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3615         } else if (!bp->drv_info_mng_owner) {
3616                 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3617 
3618                 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3619                         u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3620 
3621                         /* Management is done; need to clear indication */
3622                         if (indication & bit) {
3623                                 SHMEM2_WR(bp, mfw_drv_indication,
3624                                           indication & ~bit);
3625                                 release = true;
3626                                 break;
3627                         }
3628 
3629                         msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3630                 }
3631         }
3632         if (!release) {
3633                 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3634                 bp->drv_info_mng_owner = true;
3635         }
3636 
3637 out:
3638         mutex_unlock(&bp->drv_info_mutex);
3639 }
3640 
3641 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3642 {
3643         u8 vals[4];
3644         int i = 0;
3645 
3646         if (bnx2x_format) {
3647                 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3648                            &vals[0], &vals[1], &vals[2], &vals[3]);
3649                 if (i > 0)
3650                         vals[0] -= '';
3651         } else {
3652                 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3653                            &vals[0], &vals[1], &vals[2], &vals[3]);
3654         }
3655 
3656         while (i < 4)
3657                 vals[i++] = 0;
3658 
3659         return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3660 }
3661 
3662 void bnx2x_update_mng_version(struct bnx2x *bp)
3663 {
3664         u32 iscsiver = DRV_VER_NOT_LOADED;
3665         u32 fcoever = DRV_VER_NOT_LOADED;
3666         u32 ethver = DRV_VER_NOT_LOADED;
3667         int idx = BP_FW_MB_IDX(bp);
3668         u8 *version;
3669 
3670         if (!SHMEM2_HAS(bp, func_os_drv_ver))
3671                 return;
3672 
3673         mutex_lock(&bp->drv_info_mutex);
3674         /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3675         if (bp->drv_info_mng_owner)
3676                 goto out;
3677 
3678         if (bp->state != BNX2X_STATE_OPEN)
3679                 goto out;
3680 
3681         /* Parse ethernet driver version */
3682         ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3683         if (!CNIC_LOADED(bp))
3684                 goto out;
3685 
3686         /* Try getting storage driver version via cnic */
3687         memset(&bp->slowpath->drv_info_to_mcp, 0,
3688                sizeof(union drv_info_to_mcp));
3689         bnx2x_drv_info_iscsi_stat(bp);
3690         version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3691         iscsiver = bnx2x_update_mng_version_utility(version, false);
3692 
3693         memset(&bp->slowpath->drv_info_to_mcp, 0,
3694                sizeof(union drv_info_to_mcp));
3695         bnx2x_drv_info_fcoe_stat(bp);
3696         version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3697         fcoever = bnx2x_update_mng_version_utility(version, false);
3698 
3699 out:
3700         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3701         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3702         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3703 
3704         mutex_unlock(&bp->drv_info_mutex);
3705 
3706         DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3707            ethver, iscsiver, fcoever);
3708 }
3709 
3710 static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
3711 {
3712         u32 cmd_ok, cmd_fail;
3713 
3714         /* sanity */
3715         if (event & DRV_STATUS_DCC_EVENT_MASK &&
3716             event & DRV_STATUS_OEM_EVENT_MASK) {
3717                 BNX2X_ERR("Received simultaneous events %08x\n", event);
3718                 return;
3719         }
3720 
3721         if (event & DRV_STATUS_DCC_EVENT_MASK) {
3722                 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3723                 cmd_ok = DRV_MSG_CODE_DCC_OK;
3724         } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3725                 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3726                 cmd_ok = DRV_MSG_CODE_OEM_OK;
3727         }
3728 
3729         DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3730 
3731         if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3732                      DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3733                 /* This is the only place besides the function initialization
3734                  * where the bp->flags can change so it is done without any
3735                  * locks
3736                  */
3737                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3738                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3739                         bp->flags |= MF_FUNC_DIS;
3740 
3741                         bnx2x_e1h_disable(bp);
3742                 } else {
3743                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3744                         bp->flags &= ~MF_FUNC_DIS;
3745 
3746                         bnx2x_e1h_enable(bp);
3747                 }
3748                 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3749                            DRV_STATUS_OEM_DISABLE_ENABLE_PF);
3750         }
3751 
3752         if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3753                      DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
3754                 bnx2x_config_mf_bw(bp);
3755                 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3756                            DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
3757         }
3758 
3759         /* Report results to MCP */
3760         if (event)
3761                 bnx2x_fw_command(bp, cmd_fail, 0);
3762         else
3763                 bnx2x_fw_command(bp, cmd_ok, 0);
3764 }
3765 
3766 /* must be called under the spq lock */
3767 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3768 {
3769         struct eth_spe *next_spe = bp->spq_prod_bd;
3770 
3771         if (bp->spq_prod_bd == bp->spq_last_bd) {
3772                 bp->spq_prod_bd = bp->spq;
3773                 bp->spq_prod_idx = 0;
3774                 DP(BNX2X_MSG_SP, "end of spq\n");
3775         } else {
3776                 bp->spq_prod_bd++;
3777                 bp->spq_prod_idx++;
3778         }
3779         return next_spe;
3780 }
3781 
3782 /* must be called under the spq lock */
3783 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3784 {
3785         int func = BP_FUNC(bp);
3786 
3787         /*
3788          * Make sure that BD data is updated before writing the producer:
3789          * BD data is written to the memory, the producer is read from the
3790          * memory, thus we need a full memory barrier to ensure the ordering.
3791          */
3792         mb();
3793 
3794         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3795                  bp->spq_prod_idx);
3796         mmiowb();
3797 }
3798 
3799 /**
3800  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3801  *
3802  * @cmd:        command to check
3803  * @cmd_type:   command type
3804  */
3805 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3806 {
3807         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3808             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3809             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3810             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3811             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3812             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3813             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3814                 return true;
3815         else
3816                 return false;
3817 }
3818 
3819 /**
3820  * bnx2x_sp_post - place a single command on an SP ring
3821  *
3822  * @bp:         driver handle
3823  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3824  * @cid:        SW CID the command is related to
3825  * @data_hi:    command private data address (high 32 bits)
3826  * @data_lo:    command private data address (low 32 bits)
3827  * @cmd_type:   command type (e.g. NONE, ETH)
3828  *
3829  * SP data is handled as if it's always an address pair, thus data fields are
3830  * not swapped to little endian in upper functions. Instead this function swaps
3831  * data as if it's two u32 fields.
3832  */
3833 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3834                   u32 data_hi, u32 data_lo, int cmd_type)
3835 {
3836         struct eth_spe *spe;
3837         u16 type;
3838         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3839 
3840 #ifdef BNX2X_STOP_ON_ERROR
3841         if (unlikely(bp->panic)) {
3842                 BNX2X_ERR("Can't post SP when there is panic\n");
3843                 return -EIO;
3844         }
3845 #endif
3846 
3847         spin_lock_bh(&bp->spq_lock);
3848 
3849         if (common) {
3850                 if (!atomic_read(&bp->eq_spq_left)) {
3851                         BNX2X_ERR("BUG! EQ ring full!\n");
3852                         spin_unlock_bh(&bp->spq_lock);
3853                         bnx2x_panic();
3854                         return -EBUSY;
3855                 }
3856         } else if (!atomic_read(&bp->cq_spq_left)) {
3857                         BNX2X_ERR("BUG! SPQ ring full!\n");
3858                         spin_unlock_bh(&bp->spq_lock);
3859                         bnx2x_panic();
3860                         return -EBUSY;
3861         }
3862 
3863         spe = bnx2x_sp_get_next(bp);
3864 
3865         /* CID needs port number to be encoded int it */
3866         spe->hdr.conn_and_cmd_data =
3867                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3868                                     HW_CID(bp, cid));
3869 
3870         /* In some cases, type may already contain the func-id
3871          * mainly in SRIOV related use cases, so we add it here only
3872          * if it's not already set.
3873          */
3874         if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3875                 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3876                         SPE_HDR_CONN_TYPE;
3877                 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3878                          SPE_HDR_FUNCTION_ID);
3879         } else {
3880                 type = cmd_type;
3881         }
3882 
3883         spe->hdr.type = cpu_to_le16(type);
3884 
3885         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3886         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3887 
3888         /*
3889          * It's ok if the actual decrement is issued towards the memory
3890          * somewhere between the spin_lock and spin_unlock. Thus no
3891          * more explicit memory barrier is needed.
3892          */
3893         if (common)
3894                 atomic_dec(&bp->eq_spq_left);
3895         else
3896                 atomic_dec(&bp->cq_spq_left);
3897 
3898         DP(BNX2X_MSG_SP,
3899            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3900            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3901            (u32)(U64_LO(bp->spq_mapping) +
3902            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3903            HW_CID(bp, cid), data_hi, data_lo, type,
3904            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3905 
3906         bnx2x_sp_prod_update(bp);
3907         spin_unlock_bh(&bp->spq_lock);
3908         return 0;
3909 }
3910 
3911 /* acquire split MCP access lock register */
3912 static int bnx2x_acquire_alr(struct bnx2x *bp)
3913 {
3914         u32 j, val;
3915         int rc = 0;
3916 
3917         might_sleep();
3918         for (j = 0; j < 1000; j++) {
3919                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3920                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3921                 if (val & MCPR_ACCESS_LOCK_LOCK)
3922                         break;
3923 
3924                 usleep_range(5000, 10000);
3925         }
3926         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3927                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3928                 rc = -EBUSY;
3929         }
3930 
3931         return rc;
3932 }
3933 
3934 /* release split MCP access lock register */
3935 static void bnx2x_release_alr(struct bnx2x *bp)
3936 {
3937         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3938 }
3939 
3940 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3941 #define BNX2X_DEF_SB_IDX        0x0002
3942 
3943 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3944 {
3945         struct host_sp_status_block *def_sb = bp->def_status_blk;
3946         u16 rc = 0;
3947 
3948         barrier(); /* status block is written to by the chip */
3949         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3950                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3951                 rc |= BNX2X_DEF_SB_ATT_IDX;
3952         }
3953 
3954         if (bp->def_idx != def_sb->sp_sb.running_index) {
3955                 bp->def_idx = def_sb->sp_sb.running_index;
3956                 rc |= BNX2X_DEF_SB_IDX;
3957         }
3958 
3959         /* Do not reorder: indices reading should complete before handling */
3960         barrier();
3961         return rc;
3962 }
3963 
3964 /*
3965  * slow path service functions
3966  */
3967 
3968 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3969 {
3970         int port = BP_PORT(bp);
3971         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3972                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3973         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3974                                        NIG_REG_MASK_INTERRUPT_PORT0;
3975         u32 aeu_mask;
3976         u32 nig_mask = 0;
3977         u32 reg_addr;
3978 
3979         if (bp->attn_state & asserted)
3980                 BNX2X_ERR("IGU ERROR\n");
3981 
3982         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3983         aeu_mask = REG_RD(bp, aeu_addr);
3984 
3985         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
3986            aeu_mask, asserted);
3987         aeu_mask &= ~(asserted & 0x3ff);
3988         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3989 
3990         REG_WR(bp, aeu_addr, aeu_mask);
3991         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3992 
3993         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3994         bp->attn_state |= asserted;
3995         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3996 
3997         if (asserted & ATTN_HARD_WIRED_MASK) {
3998                 if (asserted & ATTN_NIG_FOR_FUNC) {
3999 
4000                         bnx2x_acquire_phy_lock(bp);
4001 
4002                         /* save nig interrupt mask */
4003                         nig_mask = REG_RD(bp, nig_int_mask_addr);
4004 
4005                         /* If nig_mask is not set, no need to call the update
4006                          * function.
4007                          */
4008                         if (nig_mask) {
4009                                 REG_WR(bp, nig_int_mask_addr, 0);
4010 
4011                                 bnx2x_link_attn(bp);
4012                         }
4013 
4014                         /* handle unicore attn? */
4015                 }
4016                 if (asserted & ATTN_SW_TIMER_4_FUNC)
4017                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4018 
4019                 if (asserted & GPIO_2_FUNC)
4020                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4021 
4022                 if (asserted & GPIO_3_FUNC)
4023                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4024 
4025                 if (asserted & GPIO_4_FUNC)
4026                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4027 
4028                 if (port == 0) {
4029                         if (asserted & ATTN_GENERAL_ATTN_1) {
4030                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4031                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4032                         }
4033                         if (asserted & ATTN_GENERAL_ATTN_2) {
4034                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4035                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4036                         }
4037                         if (asserted & ATTN_GENERAL_ATTN_3) {
4038                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4039                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4040                         }
4041                 } else {
4042                         if (asserted & ATTN_GENERAL_ATTN_4) {
4043                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4044                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4045                         }
4046                         if (asserted & ATTN_GENERAL_ATTN_5) {
4047                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4048                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4049                         }
4050                         if (asserted & ATTN_GENERAL_ATTN_6) {
4051                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4052                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4053                         }
4054                 }
4055 
4056         } /* if hardwired */
4057 
4058         if (bp->common.int_block == INT_BLOCK_HC)
4059                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4060                             COMMAND_REG_ATTN_BITS_SET);
4061         else
4062                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4063 
4064         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4065            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4066         REG_WR(bp, reg_addr, asserted);
4067 
4068         /* now set back the mask */
4069         if (asserted & ATTN_NIG_FOR_FUNC) {
4070                 /* Verify that IGU ack through BAR was written before restoring
4071                  * NIG mask. This loop should exit after 2-3 iterations max.
4072                  */
4073                 if (bp->common.int_block != INT_BLOCK_HC) {
4074                         u32 cnt = 0, igu_acked;
4075                         do {
4076                                 igu_acked = REG_RD(bp,
4077                                                    IGU_REG_ATTENTION_ACK_BITS);
4078                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4079                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
4080                         if (!igu_acked)
4081                                 DP(NETIF_MSG_HW,
4082                                    "Failed to verify IGU ack on time\n");
4083                         barrier();
4084                 }
4085                 REG_WR(bp, nig_int_mask_addr, nig_mask);
4086                 bnx2x_release_phy_lock(bp);
4087         }
4088 }
4089 
4090 static void bnx2x_fan_failure(struct bnx2x *bp)
4091 {
4092         int port = BP_PORT(bp);
4093         u32 ext_phy_config;
4094         /* mark the failure */
4095         ext_phy_config =
4096                 SHMEM_RD(bp,
4097                          dev_info.port_hw_config[port].external_phy_config);
4098 
4099         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4100         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4101         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4102                  ext_phy_config);
4103 
4104         /* log the failure */
4105         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4106                             "Please contact OEM Support for assistance\n");
4107 
4108         /* Schedule device reset (unload)
4109          * This is due to some boards consuming sufficient power when driver is
4110          * up to overheat if fan fails.
4111          */
4112         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4113 }
4114 
4115 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4116 {
4117         int port = BP_PORT(bp);
4118         int reg_offset;
4119         u32 val;
4120 
4121         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4122                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4123 
4124         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4125 
4126                 val = REG_RD(bp, reg_offset);
4127                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4128                 REG_WR(bp, reg_offset, val);
4129 
4130                 BNX2X_ERR("SPIO5 hw attention\n");
4131 
4132                 /* Fan failure attention */
4133                 bnx2x_hw_reset_phy(&bp->link_params);
4134                 bnx2x_fan_failure(bp);
4135         }
4136 
4137         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4138                 bnx2x_acquire_phy_lock(bp);
4139                 bnx2x_handle_module_detect_int(&bp->link_params);
4140                 bnx2x_release_phy_lock(bp);
4141         }
4142 
4143         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4144 
4145                 val = REG_RD(bp, reg_offset);
4146                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4147                 REG_WR(bp, reg_offset, val);
4148 
4149                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4150                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
4151                 bnx2x_panic();
4152         }
4153 }
4154 
4155 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4156 {
4157         u32 val;
4158 
4159         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4160 
4161                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4162                 BNX2X_ERR("DB hw attention 0x%x\n", val);
4163                 /* DORQ discard attention */
4164                 if (val & 0x2)
4165                         BNX2X_ERR("FATAL error from DORQ\n");
4166         }
4167 
4168         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4169 
4170                 int port = BP_PORT(bp);
4171                 int reg_offset;
4172 
4173                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4174                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4175 
4176                 val = REG_RD(bp, reg_offset);
4177                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4178                 REG_WR(bp, reg_offset, val);
4179 
4180                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4181                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
4182                 bnx2x_panic();
4183         }
4184 }
4185 
4186 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4187 {
4188         u32 val;
4189 
4190         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4191 
4192                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4193                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4194                 /* CFC error attention */
4195                 if (val & 0x2)
4196                         BNX2X_ERR("FATAL error from CFC\n");
4197         }
4198 
4199         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4200                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4201                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4202                 /* RQ_USDMDP_FIFO_OVERFLOW */
4203                 if (val & 0x18000)
4204                         BNX2X_ERR("FATAL error from PXP\n");
4205 
4206                 if (!CHIP_IS_E1x(bp)) {
4207                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4208                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4209                 }
4210         }
4211 
4212         if (attn & HW_INTERRUT_ASSERT_SET_2) {
4213 
4214                 int port = BP_PORT(bp);
4215                 int reg_offset;
4216 
4217                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4218                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4219 
4220                 val = REG_RD(bp, reg_offset);
4221                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4222                 REG_WR(bp, reg_offset, val);
4223 
4224                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4225                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
4226                 bnx2x_panic();
4227         }
4228 }
4229 
4230 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4231 {
4232         u32 val;
4233 
4234         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4235 
4236                 if (attn & BNX2X_PMF_LINK_ASSERT) {
4237                         int func = BP_FUNC(bp);
4238 
4239                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4240                         bnx2x_read_mf_cfg(bp);
4241                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4242                                         func_mf_config[BP_ABS_FUNC(bp)].config);
4243                         val = SHMEM_RD(bp,
4244                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
4245 
4246                         if (val & (DRV_STATUS_DCC_EVENT_MASK |
4247                                    DRV_STATUS_OEM_EVENT_MASK))
4248                                 bnx2x_oem_event(bp,
4249                                         (val & (DRV_STATUS_DCC_EVENT_MASK |
4250                                                 DRV_STATUS_OEM_EVENT_MASK)));
4251 
4252                         if (val & DRV_STATUS_SET_MF_BW)
4253                                 bnx2x_set_mf_bw(bp);
4254 
4255                         if (val & DRV_STATUS_DRV_INFO_REQ)
4256                                 bnx2x_handle_drv_info_req(bp);
4257 
4258                         if (val & DRV_STATUS_VF_DISABLED)
4259                                 bnx2x_schedule_iov_task(bp,
4260                                                         BNX2X_IOV_HANDLE_FLR);
4261 
4262                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4263                                 bnx2x_pmf_update(bp);
4264 
4265                         if (bp->port.pmf &&
4266                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4267                                 bp->dcbx_enabled > 0)
4268                                 /* start dcbx state machine */
4269                                 bnx2x_dcbx_set_params(bp,
4270                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4271                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4272                                 bnx2x_handle_afex_cmd(bp,
4273                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4274                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4275                                 bnx2x_handle_eee_event(bp);
4276 
4277                         if (val & DRV_STATUS_OEM_UPDATE_SVID)
4278                                 bnx2x_handle_update_svid_cmd(bp);
4279 
4280                         if (bp->link_vars.periodic_flags &
4281                             PERIODIC_FLAGS_LINK_EVENT) {
4282                                 /*  sync with link */
4283                                 bnx2x_acquire_phy_lock(bp);
4284                                 bp->link_vars.periodic_flags &=
4285                                         ~PERIODIC_FLAGS_LINK_EVENT;
4286                                 bnx2x_release_phy_lock(bp);
4287                                 if (IS_MF(bp))
4288                                         bnx2x_link_sync_notify(bp);
4289                                 bnx2x_link_report(bp);
4290                         }
4291                         /* Always call it here: bnx2x_link_report() will
4292                          * prevent the link indication duplication.
4293                          */
4294                         bnx2x__link_status_update(bp);
4295                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4296 
4297                         BNX2X_ERR("MC assert!\n");
4298                         bnx2x_mc_assert(bp);
4299                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4300                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4301                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4302                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4303                         bnx2x_panic();
4304 
4305                 } else if (attn & BNX2X_MCP_ASSERT) {
4306 
4307                         BNX2X_ERR("MCP assert!\n");
4308                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4309                         bnx2x_fw_dump(bp);
4310 
4311                 } else
4312                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4313         }
4314 
4315         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4316                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4317                 if (attn & BNX2X_GRC_TIMEOUT) {
4318                         val = CHIP_IS_E1(bp) ? 0 :
4319                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4320                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4321                 }
4322                 if (attn & BNX2X_GRC_RSV) {
4323                         val = CHIP_IS_E1(bp) ? 0 :
4324                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4325                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4326                 }
4327                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4328         }
4329 }
4330 
4331 /*
4332  * Bits map:
4333  * 0-7   - Engine0 load counter.
4334  * 8-15  - Engine1 load counter.
4335  * 16    - Engine0 RESET_IN_PROGRESS bit.
4336  * 17    - Engine1 RESET_IN_PROGRESS bit.
4337  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4338  *         on the engine
4339  * 19    - Engine1 ONE_IS_LOADED.
4340  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4341  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4342  *         just the one belonging to its engine).
4343  *
4344  */
4345 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4346 
4347 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4348 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4349 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4350 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4351 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4352 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4353 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4354 
4355 /*
4356  * Set the GLOBAL_RESET bit.
4357  *
4358  * Should be run under rtnl lock
4359  */
4360 void bnx2x_set_reset_global(struct bnx2x *bp)
4361 {
4362         u32 val;
4363         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4364         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4365         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4366         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4367 }
4368 
4369 /*
4370  * Clear the GLOBAL_RESET bit.
4371  *
4372  * Should be run under rtnl lock
4373  */
4374 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4375 {
4376         u32 val;
4377         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4378         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4379         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4380         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4381 }
4382 
4383 /*
4384  * Checks the GLOBAL_RESET bit.
4385  *
4386  * should be run under rtnl lock
4387  */
4388 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4389 {
4390         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4391 
4392         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4393         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4394 }
4395 
4396 /*
4397  * Clear RESET_IN_PROGRESS bit for the current engine.
4398  *
4399  * Should be run under rtnl lock
4400  */
4401 static void bnx2x_set_reset_done(struct bnx2x *bp)
4402 {
4403         u32 val;
4404         u32 bit = BP_PATH(bp) ?
4405                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4406         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4407         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4408 
4409         /* Clear the bit */
4410         val &= ~bit;
4411         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4412 
4413         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4414 }
4415 
4416 /*
4417  * Set RESET_IN_PROGRESS for the current engine.
4418  *
4419  * should be run under rtnl lock
4420  */
4421 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4422 {
4423         u32 val;
4424         u32 bit = BP_PATH(bp) ?
4425                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4426         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4427         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4428 
4429         /* Set the bit */
4430         val |= bit;
4431         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4432         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4433 }
4434 
4435 /*
4436  * Checks the RESET_IN_PROGRESS bit for the given engine.
4437  * should be run under rtnl lock
4438  */
4439 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4440 {
4441         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4442         u32 bit = engine ?
4443                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4444 
4445         /* return false if bit is set */
4446         return (val & bit) ? false : true;
4447 }
4448 
4449 /*
4450  * set pf load for the current pf.
4451  *
4452  * should be run under rtnl lock
4453  */
4454 void bnx2x_set_pf_load(struct bnx2x *bp)
4455 {
4456         u32 val1, val;
4457         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4458                              BNX2X_PATH0_LOAD_CNT_MASK;
4459         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4460                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4461 
4462         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4463         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4464 
4465         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4466 
4467         /* get the current counter value */
4468         val1 = (val & mask) >> shift;
4469 
4470         /* set bit of that PF */
4471         val1 |= (1 << bp->pf_num);
4472 
4473         /* clear the old value */
4474         val &= ~mask;
4475 
4476         /* set the new one */
4477         val |= ((val1 << shift) & mask);
4478 
4479         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4480         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4481 }
4482 
4483 /**
4484  * bnx2x_clear_pf_load - clear pf load mark
4485  *
4486  * @bp:         driver handle
4487  *
4488  * Should be run under rtnl lock.
4489  * Decrements the load counter for the current engine. Returns
4490  * whether other functions are still loaded
4491  */
4492 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4493 {
4494         u32 val1, val;
4495         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4496                              BNX2X_PATH0_LOAD_CNT_MASK;
4497         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4498                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4499 
4500         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4501         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4502         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4503 
4504         /* get the current counter value */
4505         val1 = (val & mask) >> shift;
4506 
4507         /* clear bit of that PF */
4508         val1 &= ~(1 << bp->pf_num);
4509 
4510         /* clear the old value */
4511         val &= ~mask;
4512 
4513         /* set the new one */
4514         val |= ((val1 << shift) & mask);
4515 
4516         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4517         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4518         return val1 != 0;
4519 }
4520 
4521 /*
4522  * Read the load status for the current engine.
4523  *
4524  * should be run under rtnl lock
4525  */
4526 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4527 {
4528         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4529                              BNX2X_PATH0_LOAD_CNT_MASK);
4530         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4531                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4532         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4533 
4534         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4535 
4536         val = (val & mask) >> shift;
4537 
4538         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4539            engine, val);
4540 
4541         return val != 0;
4542 }
4543 
4544 static void _print_parity(struct bnx2x *bp, u32 reg)
4545 {
4546         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4547 }
4548 
4549 static void _print_next_block(int idx, const char *blk)
4550 {
4551         pr_cont("%s%s", idx ? ", " : "", blk);
4552 }
4553 
4554 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4555                                             int *par_num, bool print)
4556 {
4557         u32 cur_bit;
4558         bool res;
4559         int i;
4560 
4561         res = false;
4562 
4563         for (i = 0; sig; i++) {
4564                 cur_bit = (0x1UL << i);
4565                 if (sig & cur_bit) {
4566                         res |= true; /* Each bit is real error! */
4567 
4568                         if (print) {
4569                                 switch (cur_bit) {
4570                                 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4571                                         _print_next_block((*par_num)++, "BRB");
4572                                         _print_parity(bp,
4573                                                       BRB1_REG_BRB1_PRTY_STS);
4574                                         break;
4575                                 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4576                                         _print_next_block((*par_num)++,
4577                                                           "PARSER");
4578                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4579                                         break;
4580                                 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4581                                         _print_next_block((*par_num)++, "TSDM");
4582                                         _print_parity(bp,
4583                                                       TSDM_REG_TSDM_PRTY_STS);
4584                                         break;
4585                                 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4586                                         _print_next_block((*par_num)++,
4587                                                           "SEARCHER");
4588                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4589                                         break;
4590                                 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4591                                         _print_next_block((*par_num)++, "TCM");
4592                                         _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4593                                         break;
4594                                 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4595                                         _print_next_block((*par_num)++,
4596                                                           "TSEMI");
4597                                         _print_parity(bp,
4598                                                       TSEM_REG_TSEM_PRTY_STS_0);
4599                                         _print_parity(bp,
4600                                                       TSEM_REG_TSEM_PRTY_STS_1);
4601                                         break;
4602                                 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4603                                         _print_next_block((*par_num)++, "XPB");
4604                                         _print_parity(bp, GRCBASE_XPB +
4605                                                           PB_REG_PB_PRTY_STS);
4606                                         break;
4607                                 }
4608                         }
4609 
4610                         /* Clear the bit */
4611                         sig &= ~cur_bit;
4612                 }
4613         }
4614 
4615         return res;
4616 }
4617 
4618 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4619                                             int *par_num, bool *global,
4620                                             bool print)
4621 {
4622         u32 cur_bit;
4623         bool res;
4624         int i;
4625 
4626         res = false;
4627 
4628         for (i = 0; sig; i++) {
4629                 cur_bit = (0x1UL << i);
4630                 if (sig & cur_bit) {
4631                         res |= true; /* Each bit is real error! */
4632                         switch (cur_bit) {
4633                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4634                                 if (print) {
4635                                         _print_next_block((*par_num)++, "PBF");
4636                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4637                                 }
4638                                 break;
4639                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4640                                 if (print) {
4641                                         _print_next_block((*par_num)++, "QM");
4642                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4643                                 }
4644                                 break;
4645                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4646                                 if (print) {
4647                                         _print_next_block((*par_num)++, "TM");
4648                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4649                                 }
4650                                 break;
4651                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4652                                 if (print) {
4653                                         _print_next_block((*par_num)++, "XSDM");
4654                                         _print_parity(bp,
4655                                                       XSDM_REG_XSDM_PRTY_STS);
4656                                 }
4657                                 break;
4658                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4659                                 if (print) {
4660                                         _print_next_block((*par_num)++, "XCM");
4661                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4662                                 }
4663                                 break;
4664                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4665                                 if (print) {
4666                                         _print_next_block((*par_num)++,
4667                                                           "XSEMI");
4668                                         _print_parity(bp,
4669                                                       XSEM_REG_XSEM_PRTY_STS_0);
4670                                         _print_parity(bp,
4671                                                       XSEM_REG_XSEM_PRTY_STS_1);
4672                                 }
4673                                 break;
4674                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4675                                 if (print) {
4676                                         _print_next_block((*par_num)++,
4677                                                           "DOORBELLQ");
4678                                         _print_parity(bp,
4679                                                       DORQ_REG_DORQ_PRTY_STS);
4680                                 }
4681                                 break;
4682                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4683                                 if (print) {
4684                                         _print_next_block((*par_num)++, "NIG");
4685                                         if (CHIP_IS_E1x(bp)) {
4686                                                 _print_parity(bp,
4687                                                         NIG_REG_NIG_PRTY_STS);
4688                                         } else {
4689                                                 _print_parity(bp,
4690                                                         NIG_REG_NIG_PRTY_STS_0);
4691                                                 _print_parity(bp,
4692                                                         NIG_REG_NIG_PRTY_STS_1);
4693                                         }
4694                                 }
4695                                 break;
4696                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4697                                 if (print)
4698                                         _print_next_block((*par_num)++,
4699                                                           "VAUX PCI CORE");
4700                                 *global = true;
4701                                 break;
4702                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4703                                 if (print) {
4704                                         _print_next_block((*par_num)++,
4705                                                           "DEBUG");
4706                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4707                                 }
4708                                 break;
4709                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4710                                 if (print) {
4711                                         _print_next_block((*par_num)++, "USDM");
4712                                         _print_parity(bp,
4713                                                       USDM_REG_USDM_PRTY_STS);
4714                                 }
4715                                 break;
4716                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4717                                 if (print) {
4718                                         _print_next_block((*par_num)++, "UCM");
4719                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4720                                 }
4721                                 break;
4722                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4723                                 if (print) {
4724                                         _print_next_block((*par_num)++,
4725                                                           "USEMI");
4726                                         _print_parity(bp,
4727                                                       USEM_REG_USEM_PRTY_STS_0);
4728                                         _print_parity(bp,
4729                                                       USEM_REG_USEM_PRTY_STS_1);
4730                                 }
4731                                 break;
4732                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4733                                 if (print) {
4734                                         _print_next_block((*par_num)++, "UPB");
4735                                         _print_parity(bp, GRCBASE_UPB +
4736                                                           PB_REG_PB_PRTY_STS);
4737                                 }
4738                                 break;
4739                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4740                                 if (print) {
4741                                         _print_next_block((*par_num)++, "CSDM");
4742                                         _print_parity(bp,
4743                                                       CSDM_REG_CSDM_PRTY_STS);
4744                                 }
4745                                 break;
4746                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4747                                 if (print) {
4748                                         _print_next_block((*par_num)++, "CCM");
4749                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4750                                 }
4751                                 break;
4752                         }
4753 
4754                         /* Clear the bit */
4755                         sig &= ~cur_bit;
4756                 }
4757         }
4758 
4759         return res;
4760 }
4761 
4762 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4763                                             int *par_num, bool print)
4764 {
4765         u32 cur_bit;
4766         bool res;
4767         int i;
4768 
4769         res = false;
4770 
4771         for (i = 0; sig; i++) {
4772                 cur_bit = (0x1UL << i);
4773                 if (sig & cur_bit) {
4774                         res = true; /* Each bit is real error! */
4775                         if (print) {
4776                                 switch (cur_bit) {
4777                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4778                                         _print_next_block((*par_num)++,
4779                                                           "CSEMI");
4780                                         _print_parity(bp,
4781                                                       CSEM_REG_CSEM_PRTY_STS_0);
4782                                         _print_parity(bp,
4783                                                       CSEM_REG_CSEM_PRTY_STS_1);
4784                                         break;
4785                                 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4786                                         _print_next_block((*par_num)++, "PXP");
4787                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4788                                         _print_parity(bp,
4789                                                       PXP2_REG_PXP2_PRTY_STS_0);
4790                                         _print_parity(bp,
4791                                                       PXP2_REG_PXP2_PRTY_STS_1);
4792                                         break;
4793                                 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4794                                         _print_next_block((*par_num)++,
4795                                                           "PXPPCICLOCKCLIENT");
4796                                         break;
4797                                 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4798                                         _print_next_block((*par_num)++, "CFC");
4799                                         _print_parity(bp,
4800                                                       CFC_REG_CFC_PRTY_STS);
4801                                         break;
4802                                 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4803                                         _print_next_block((*par_num)++, "CDU");
4804                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4805                                         break;
4806                                 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4807                                         _print_next_block((*par_num)++, "DMAE");
4808                                         _print_parity(bp,
4809                                                       DMAE_REG_DMAE_PRTY_STS);
4810                                         break;
4811                                 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4812                                         _print_next_block((*par_num)++, "IGU");
4813                                         if (CHIP_IS_E1x(bp))
4814                                                 _print_parity(bp,
4815                                                         HC_REG_HC_PRTY_STS);
4816                                         else
4817                                                 _print_parity(bp,
4818                                                         IGU_REG_IGU_PRTY_STS);
4819                                         break;
4820                                 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4821                                         _print_next_block((*par_num)++, "MISC");
4822                                         _print_parity(bp,
4823                                                       MISC_REG_MISC_PRTY_STS);
4824                                         break;
4825                                 }
4826                         }
4827 
4828                         /* Clear the bit */
4829                         sig &= ~cur_bit;
4830                 }
4831         }
4832 
4833         return res;
4834 }
4835 
4836 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4837                                             int *par_num, bool *global,
4838                                             bool print)
4839 {
4840         bool res = false;
4841         u32 cur_bit;
4842         int i;
4843 
4844         for (i = 0; sig; i++) {
4845                 cur_bit = (0x1UL << i);
4846                 if (sig & cur_bit) {
4847                         switch (cur_bit) {
4848                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4849                                 if (print)
4850                                         _print_next_block((*par_num)++,
4851                                                           "MCP ROM");
4852                                 *global = true;
4853                                 res = true;
4854                                 break;
4855                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4856                                 if (print)
4857                                         _print_next_block((*par_num)++,
4858                                                           "MCP UMP RX");
4859                                 *global = true;
4860                                 res = true;
4861                                 break;
4862                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4863                                 if (print)
4864                                         _print_next_block((*par_num)++,
4865                                                           "MCP UMP TX");
4866                                 *global = true;
4867                                 res = true;
4868                                 break;
4869                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4870                                 if (print)
4871                                         _print_next_block((*par_num)++,
4872                                                           "MCP SCPAD");
4873                                 /* clear latched SCPAD PATIRY from MCP */
4874                                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4875                                        1UL << 10);
4876                                 break;
4877                         }
4878 
4879                         /* Clear the bit */
4880                         sig &= ~cur_bit;
4881                 }
4882         }
4883 
4884         return res;
4885 }
4886 
4887 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4888                                             int *par_num, bool print)
4889 {
4890         u32 cur_bit;
4891         bool res;
4892         int i;
4893 
4894         res = false;
4895 
4896         for (i = 0; sig; i++) {
4897                 cur_bit = (0x1UL << i);
4898                 if (sig & cur_bit) {
4899                         res = true; /* Each bit is real error! */
4900                         if (print) {
4901                                 switch (cur_bit) {
4902                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4903                                         _print_next_block((*par_num)++,
4904                                                           "PGLUE_B");
4905                                         _print_parity(bp,
4906                                                       PGLUE_B_REG_PGLUE_B_PRTY_STS);
4907                                         break;
4908                                 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4909                                         _print_next_block((*par_num)++, "ATC");
4910                                         _print_parity(bp,
4911                                                       ATC_REG_ATC_PRTY_STS);
4912                                         break;
4913                                 }
4914                         }
4915                         /* Clear the bit */
4916                         sig &= ~cur_bit;
4917                 }
4918         }
4919 
4920         return res;
4921 }
4922 
4923 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4924                               u32 *sig)
4925 {
4926         bool res = false;
4927 
4928         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4929             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4930             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4931             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4932             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4933                 int par_num = 0;
4934                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4935                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4936                           sig[0] & HW_PRTY_ASSERT_SET_0,
4937                           sig[1] & HW_PRTY_ASSERT_SET_1,
4938                           sig[2] & HW_PRTY_ASSERT_SET_2,
4939                           sig[3] & HW_PRTY_ASSERT_SET_3,
4940                           sig[4] & HW_PRTY_ASSERT_SET_4);
4941                 if (print)
4942                         netdev_err(bp->dev,
4943                                    "Parity errors detected in blocks: ");
4944                 res |= bnx2x_check_blocks_with_parity0(bp,
4945                         sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4946                 res |= bnx2x_check_blocks_with_parity1(bp,
4947                         sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4948                 res |= bnx2x_check_blocks_with_parity2(bp,
4949                         sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4950                 res |= bnx2x_check_blocks_with_parity3(bp,
4951                         sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4952                 res |= bnx2x_check_blocks_with_parity4(bp,
4953                         sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4954 
4955                 if (print)
4956                         pr_cont("\n");
4957         }
4958 
4959         return res;
4960 }
4961 
4962 /**
4963  * bnx2x_chk_parity_attn - checks for parity attentions.
4964  *
4965  * @bp:         driver handle
4966  * @global:     true if there was a global attention
4967  * @print:      show parity attention in syslog
4968  */
4969 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4970 {
4971         struct attn_route attn = { {0} };
4972         int port = BP_PORT(bp);
4973 
4974         attn.sig[0] = REG_RD(bp,
4975                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4976                              port*4);
4977         attn.sig[1] = REG_RD(bp,
4978                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4979                              port*4);
4980         attn.sig[2] = REG_RD(bp,
4981                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4982                              port*4);
4983         attn.sig[3] = REG_RD(bp,
4984                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4985                              port*4);
4986         /* Since MCP attentions can't be disabled inside the block, we need to
4987          * read AEU registers to see whether they're currently disabled
4988          */
4989         attn.sig[3] &= ((REG_RD(bp,
4990                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4991                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
4992                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
4993                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
4994 
4995         if (!CHIP_IS_E1x(bp))
4996                 attn.sig[4] = REG_RD(bp,
4997                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4998                                      port*4);
4999 
5000         return bnx2x_parity_attn(bp, global, print, attn.sig);
5001 }
5002 
5003 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
5004 {
5005         u32 val;
5006         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5007 
5008                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5009                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5010                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
5011                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5012                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
5013                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5014                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
5015                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5016                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
5017                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5018                 if (val &
5019                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
5020                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5021                 if (val &
5022                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
5023                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5024                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
5025                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5026                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
5027                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5028                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
5029                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5030         }
5031         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5032                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5033                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5034                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5035                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5036                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
5037                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5038                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
5039                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5040                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
5041                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5042                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5043                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5044                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
5045                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5046         }
5047 
5048         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5049                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5050                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5051                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5052                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5053         }
5054 }
5055 
5056 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5057 {
5058         struct attn_route attn, *group_mask;
5059         int port = BP_PORT(bp);
5060         int index;
5061         u32 reg_addr;
5062         u32 val;
5063         u32 aeu_mask;
5064         bool global = false;
5065 
5066         /* need to take HW lock because MCP or other port might also
5067            try to handle this event */
5068         bnx2x_acquire_alr(bp);
5069 
5070         if (bnx2x_chk_parity_attn(bp, &global, true)) {
5071 #ifndef BNX2X_STOP_ON_ERROR
5072                 bp->recovery_state = BNX2X_RECOVERY_INIT;
5073                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5074                 /* Disable HW interrupts */
5075                 bnx2x_int_disable(bp);
5076                 /* In case of parity errors don't handle attentions so that
5077                  * other function would "see" parity errors.
5078                  */
5079 #else
5080                 bnx2x_panic();
5081 #endif
5082                 bnx2x_release_alr(bp);
5083                 return;
5084         }
5085 
5086         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5087         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5088         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5089         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5090         if (!CHIP_IS_E1x(bp))
5091                 attn.sig[4] =
5092                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5093         else
5094                 attn.sig[4] = 0;
5095 
5096         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5097            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5098 
5099         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5100                 if (deasserted & (1 << index)) {
5101                         group_mask = &bp->attn_group[index];
5102 
5103                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5104                            index,
5105                            group_mask->sig[0], group_mask->sig[1],
5106                            group_mask->sig[2], group_mask->sig[3],
5107                            group_mask->sig[4]);
5108 
5109                         bnx2x_attn_int_deasserted4(bp,
5110                                         attn.sig[4] & group_mask->sig[4]);
5111                         bnx2x_attn_int_deasserted3(bp,
5112                                         attn.sig[3] & group_mask->sig[3]);
5113                         bnx2x_attn_int_deasserted1(bp,
5114                                         attn.sig[1] & group_mask->sig[1]);
5115                         bnx2x_attn_int_deasserted2(bp,
5116                                         attn.sig[2] & group_mask->sig[2]);
5117                         bnx2x_attn_int_deasserted0(bp,
5118                                         attn.sig[0] & group_mask->sig[0]);
5119                 }
5120         }
5121 
5122         bnx2x_release_alr(bp);
5123 
5124         if (bp->common.int_block == INT_BLOCK_HC)
5125                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5126                             COMMAND_REG_ATTN_BITS_CLR);
5127         else
5128                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5129 
5130         val = ~deasserted;
5131         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5132            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5133         REG_WR(bp, reg_addr, val);
5134 
5135         if (~bp->attn_state & deasserted)
5136                 BNX2X_ERR("IGU ERROR\n");
5137 
5138         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5139                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
5140 
5141         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5142         aeu_mask = REG_RD(bp, reg_addr);
5143 
5144         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
5145            aeu_mask, deasserted);
5146         aeu_mask |= (deasserted & 0x3ff);
5147         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5148 
5149         REG_WR(bp, reg_addr, aeu_mask);
5150         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5151 
5152         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5153         bp->attn_state &= ~deasserted;
5154         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5155 }
5156 
5157 static void bnx2x_attn_int(struct bnx2x *bp)
5158 {
5159         /* read local copy of bits */
5160         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5161                                                                 attn_bits);
5162         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5163                                                                 attn_bits_ack);
5164         u32 attn_state = bp->attn_state;
5165 
5166         /* look for changed bits */
5167         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
5168         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
5169 
5170         DP(NETIF_MSG_HW,
5171            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
5172            attn_bits, attn_ack, asserted, deasserted);
5173 
5174         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5175                 BNX2X_ERR("BAD attention state\n");
5176 
5177         /* handle bits that were raised */
5178         if (asserted)
5179                 bnx2x_attn_int_asserted(bp, asserted);
5180 
5181         if (deasserted)
5182                 bnx2x_attn_int_deasserted(bp, deasserted);
5183 }
5184 
5185 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5186                       u16 index, u8 op, u8 update)
5187 {
5188         u32 igu_addr = bp->igu_base_addr;
5189         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5190         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5191                              igu_addr);
5192 }
5193 
5194 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5195 {
5196         /* No memory barriers */
5197         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5198         mmiowb(); /* keep prod updates ordered */
5199 }
5200 
5201 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5202                                       union event_ring_elem *elem)
5203 {
5204         u8 err = elem->message.error;
5205 
5206         if (!bp->cnic_eth_dev.starting_cid  ||
5207             (cid < bp->cnic_eth_dev.starting_cid &&
5208             cid != bp->cnic_eth_dev.iscsi_l2_cid))
5209                 return 1;
5210 
5211         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5212 
5213         if (unlikely(err)) {
5214 
5215                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5216                           cid);
5217                 bnx2x_panic_dump(bp, false);
5218         }
5219         bnx2x_cnic_cfc_comp(bp, cid, err);
5220         return 0;
5221 }
5222 
5223 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5224 {
5225         struct bnx2x_mcast_ramrod_params rparam;
5226         int rc;
5227 
5228         memset(&rparam, 0, sizeof(rparam));
5229 
5230         rparam.mcast_obj = &bp->mcast_obj;
5231 
5232         netif_addr_lock_bh(bp->dev);
5233 
5234         /* Clear pending state for the last command */
5235         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5236 
5237         /* If there are pending mcast commands - send them */
5238         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5239                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5240                 if (rc < 0)
5241                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5242                                   rc);
5243         }
5244 
5245         netif_addr_unlock_bh(bp->dev);
5246 }
5247 
5248 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5249                                             union event_ring_elem *elem)
5250 {
5251         unsigned long ramrod_flags = 0;
5252         int rc = 0;
5253         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5254         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5255 
5256         /* Always push next commands out, don't wait here */
5257         __set_bit(RAMROD_CONT, &ramrod_flags);
5258 
5259         switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5260                             >> BNX2X_SWCID_SHIFT) {
5261         case BNX2X_FILTER_MAC_PENDING:
5262                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5263                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5264                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5265                 else
5266                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5267 
5268                 break;
5269         case BNX2X_FILTER_MCAST_PENDING:
5270                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5271                 /* This is only relevant for 57710 where multicast MACs are
5272                  * configured as unicast MACs using the same ramrod.
5273                  */
5274                 bnx2x_handle_mcast_eqe(bp);
5275                 return;
5276         default:
5277                 BNX2X_ERR("Unsupported classification command: %d\n",
5278                           elem->message.data.eth_event.echo);
5279                 return;
5280         }
5281 
5282         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5283 
5284         if (rc < 0)
5285                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5286         else if (rc > 0)
5287                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5288 }
5289 
5290 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5291 
5292 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5293 {
5294         netif_addr_lock_bh(bp->dev);
5295 
5296         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5297 
5298         /* Send rx_mode command again if was requested */
5299         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5300                 bnx2x_set_storm_rx_mode(bp);
5301         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5302                                     &bp->sp_state))
5303                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5304         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5305                                     &bp->sp_state))
5306                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5307 
5308         netif_addr_unlock_bh(bp->dev);
5309 }
5310 
5311 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5312                                               union event_ring_elem *elem)
5313 {
5314         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5315                 DP(BNX2X_MSG_SP,
5316                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5317                    elem->message.data.vif_list_event.func_bit_map);
5318                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5319                         elem->message.data.vif_list_event.func_bit_map);
5320         } else if (elem->message.data.vif_list_event.echo ==
5321                    VIF_LIST_RULE_SET) {
5322                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5323                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5324         }
5325 }
5326 
5327 /* called with rtnl_lock */
5328 static void bnx2x_after_function_update(struct bnx2x *bp)
5329 {
5330         int q, rc;
5331         struct bnx2x_fastpath *fp;
5332         struct bnx2x_queue_state_params queue_params = {NULL};
5333         struct bnx2x_queue_update_params *q_update_params =
5334                 &queue_params.params.update;
5335 
5336         /* Send Q update command with afex vlan removal values for all Qs */
5337         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5338 
5339         /* set silent vlan removal values according to vlan mode */
5340         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5341                   &q_update_params->update_flags);
5342         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5343                   &q_update_params->update_flags);
5344         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5345 
5346         /* in access mode mark mask and value are 0 to strip all vlans */
5347         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5348                 q_update_params->silent_removal_value = 0;
5349                 q_update_params->silent_removal_mask = 0;
5350         } else {
5351                 q_update_params->silent_removal_value =
5352                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5353                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5354         }
5355 
5356         for_each_eth_queue(bp, q) {
5357                 /* Set the appropriate Queue object */
5358                 fp = &bp->fp[q];
5359                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5360 
5361                 /* send the ramrod */
5362                 rc = bnx2x_queue_state_change(bp, &queue_params);
5363                 if (rc < 0)
5364                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5365                                   q);
5366         }
5367 
5368         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5369                 fp = &bp->fp[FCOE_IDX(bp)];
5370                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5371 
5372                 /* clear pending completion bit */
5373                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5374 
5375                 /* mark latest Q bit */
5376                 smp_mb__before_atomic();
5377                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5378                 smp_mb__after_atomic();
5379 
5380                 /* send Q update ramrod for FCoE Q */
5381                 rc = bnx2x_queue_state_change(bp, &queue_params);
5382                 if (rc < 0)
5383                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5384                                   q);
5385         } else {
5386                 /* If no FCoE ring - ACK MCP now */
5387                 bnx2x_link_report(bp);
5388                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5389         }
5390 }
5391 
5392 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5393         struct bnx2x *bp, u32 cid)
5394 {
5395         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5396 
5397         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5398                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5399         else
5400                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5401 }
5402 
5403 static void bnx2x_eq_int(struct bnx2x *bp)
5404 {
5405         u16 hw_cons, sw_cons, sw_prod;
5406         union event_ring_elem *elem;
5407         u8 echo;
5408         u32 cid;
5409         u8 opcode;
5410         int rc, spqe_cnt = 0;
5411         struct bnx2x_queue_sp_obj *q_obj;
5412         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5413         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5414 
5415         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5416 
5417         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5418          * when we get the next-page we need to adjust so the loop
5419          * condition below will be met. The next element is the size of a
5420          * regular element and hence incrementing by 1
5421          */
5422         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5423                 hw_cons++;
5424 
5425         /* This function may never run in parallel with itself for a
5426          * specific bp, thus there is no need in "paired" read memory
5427          * barrier here.
5428          */
5429         sw_cons = bp->eq_cons;
5430         sw_prod = bp->eq_prod;
5431 
5432         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5433                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5434 
5435         for (; sw_cons != hw_cons;
5436               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5437 
5438                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5439 
5440                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5441                 if (!rc) {
5442                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5443                            rc);
5444                         goto next_spqe;
5445                 }
5446 
5447                 /* elem CID originates from FW; actually LE */
5448                 cid = SW_CID((__force __le32)
5449                              elem->message.data.cfc_del_event.cid);
5450                 opcode = elem->message.opcode;
5451 
5452                 /* handle eq element */
5453                 switch (opcode) {
5454                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5455                         bnx2x_vf_mbx_schedule(bp,
5456                                               &elem->message.data.vf_pf_event);
5457                         continue;
5458 
5459                 case EVENT_RING_OPCODE_STAT_QUERY:
5460                         DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5461                                "got statistics comp event %d\n",
5462                                bp->stats_comp++);
5463                         /* nothing to do with stats comp */
5464                         goto next_spqe;
5465 
5466                 case EVENT_RING_OPCODE_CFC_DEL:
5467                         /* handle according to cid range */
5468                         /*
5469                          * we may want to verify here that the bp state is
5470                          * HALTING
5471                          */
5472                         DP(BNX2X_MSG_SP,
5473                            "got delete ramrod for MULTI[%d]\n", cid);
5474 
5475                         if (CNIC_LOADED(bp) &&
5476                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5477                                 goto next_spqe;
5478 
5479                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5480 
5481                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5482                                 break;
5483 
5484                         goto next_spqe;
5485 
5486                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5487                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5488                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5489                         if (f_obj->complete_cmd(bp, f_obj,
5490                                                 BNX2X_F_CMD_TX_STOP))
5491                                 break;
5492                         goto next_spqe;
5493 
5494                 case EVENT_RING_OPCODE_START_TRAFFIC:
5495                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5496                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5497                         if (f_obj->complete_cmd(bp, f_obj,
5498                                                 BNX2X_F_CMD_TX_START))
5499                                 break;
5500                         goto next_spqe;
5501 
5502                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5503                         echo = elem->message.data.function_update_event.echo;
5504                         if (echo == SWITCH_UPDATE) {
5505                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5506                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5507                                 if (f_obj->complete_cmd(
5508                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5509                                         break;
5510 
5511                         } else {
5512                                 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5513 
5514                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5515                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5516                                 f_obj->complete_cmd(bp, f_obj,
5517                                                     BNX2X_F_CMD_AFEX_UPDATE);
5518 
5519                                 /* We will perform the Queues update from
5520                                  * sp_rtnl task as all Queue SP operations
5521                                  * should run under rtnl_lock.
5522                                  */
5523                                 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5524                         }
5525 
5526                         goto next_spqe;
5527 
5528                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5529                         f_obj->complete_cmd(bp, f_obj,
5530                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5531                         bnx2x_after_afex_vif_lists(bp, elem);
5532                         goto next_spqe;
5533                 case EVENT_RING_OPCODE_FUNCTION_START:
5534                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5535                            "got FUNC_START ramrod\n");
5536                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5537                                 break;
5538 
5539                         goto next_spqe;
5540 
5541                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5542                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5543                            "got FUNC_STOP ramrod\n");
5544                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5545                                 break;
5546 
5547                         goto next_spqe;
5548 
5549                 case EVENT_RING_OPCODE_SET_TIMESYNC:
5550                         DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5551                            "got set_timesync ramrod completion\n");
5552                         if (f_obj->complete_cmd(bp, f_obj,
5553                                                 BNX2X_F_CMD_SET_TIMESYNC))
5554                                 break;
5555                         goto next_spqe;
5556                 }
5557 
5558                 switch (opcode | bp->state) {
5559                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5560                       BNX2X_STATE_OPEN):
5561                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5562                       BNX2X_STATE_OPENING_WAIT4_PORT):
5563                         cid = elem->message.data.eth_event.echo &
5564                                 BNX2X_SWCID_MASK;
5565                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5566                            cid);
5567                         rss_raw->clear_pending(rss_raw);
5568                         break;
5569 
5570                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5571                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5572                 case (EVENT_RING_OPCODE_SET_MAC |
5573                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5574                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5575                       BNX2X_STATE_OPEN):
5576                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5577                       BNX2X_STATE_DIAG):
5578                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5579                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5580                         DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5581                         bnx2x_handle_classification_eqe(bp, elem);
5582                         break;
5583 
5584                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5585                       BNX2X_STATE_OPEN):
5586                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5587                       BNX2X_STATE_DIAG):
5588                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5589                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5590                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5591                         bnx2x_handle_mcast_eqe(bp);
5592                         break;
5593 
5594                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5595                       BNX2X_STATE_OPEN):
5596                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5597                       BNX2X_STATE_DIAG):
5598                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5599                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5600                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5601                         bnx2x_handle_rx_mode_eqe(bp);
5602                         break;
5603                 default:
5604                         /* unknown event log error and continue */
5605                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5606                                   elem->message.opcode, bp->state);
5607                 }
5608 next_spqe:
5609                 spqe_cnt++;
5610         } /* for */
5611 
5612         smp_mb__before_atomic();
5613         atomic_add(spqe_cnt, &bp->eq_spq_left);
5614 
5615         bp->eq_cons = sw_cons;
5616         bp->eq_prod = sw_prod;
5617         /* Make sure that above mem writes were issued towards the memory */
5618         smp_wmb();
5619 
5620         /* update producer */
5621         bnx2x_update_eq_prod(bp, bp->eq_prod);
5622 }
5623 
5624 static void bnx2x_sp_task(struct work_struct *work)
5625 {
5626         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5627 
5628         DP(BNX2X_MSG_SP, "sp task invoked\n");
5629 
5630         /* make sure the atomic interrupt_occurred has been written */
5631         smp_rmb();
5632         if (atomic_read(&bp->interrupt_occurred)) {
5633 
5634                 /* what work needs to be performed? */
5635                 u16 status = bnx2x_update_dsb_idx(bp);
5636 
5637                 DP(BNX2X_MSG_SP, "status %x\n", status);
5638                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5639                 atomic_set(&bp->interrupt_occurred, 0);
5640 
5641                 /* HW attentions */
5642                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5643                         bnx2x_attn_int(bp);
5644                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5645                 }
5646 
5647                 /* SP events: STAT_QUERY and others */
5648                 if (status & BNX2X_DEF_SB_IDX) {
5649                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5650 
5651                 if (FCOE_INIT(bp) &&
5652                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5653                                 /* Prevent local bottom-halves from running as
5654                                  * we are going to change the local NAPI list.
5655                                  */
5656                                 local_bh_disable();
5657                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5658                                 local_bh_enable();
5659                         }
5660 
5661                         /* Handle EQ completions */
5662                         bnx2x_eq_int(bp);
5663                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5664                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5665 
5666                         status &= ~BNX2X_DEF_SB_IDX;
5667                 }
5668 
5669                 /* if status is non zero then perhaps something went wrong */
5670                 if (unlikely(status))
5671                         DP(BNX2X_MSG_SP,
5672                            "got an unknown interrupt! (status 0x%x)\n", status);
5673 
5674                 /* ack status block only if something was actually handled */
5675                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5676                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5677         }
5678 
5679         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5680         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5681                                &bp->sp_state)) {
5682                 bnx2x_link_report(bp);
5683                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5684         }
5685 }
5686 
5687 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5688 {
5689         struct net_device *dev = dev_instance;
5690         struct bnx2x *bp = netdev_priv(dev);
5691 
5692         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5693                      IGU_INT_DISABLE, 0);
5694 
5695 #ifdef BNX2X_STOP_ON_ERROR
5696         if (unlikely(bp->panic))
5697                 return IRQ_HANDLED;
5698 #endif
5699 
5700         if (CNIC_LOADED(bp)) {
5701                 struct cnic_ops *c_ops;
5702 
5703                 rcu_read_lock();
5704                 c_ops = rcu_dereference(bp->cnic_ops);
5705                 if (c_ops)
5706                         c_ops->cnic_handler(bp->cnic_data, NULL);
5707                 rcu_read_unlock();
5708         }
5709 
5710         /* schedule sp task to perform default status block work, ack
5711          * attentions and enable interrupts.
5712          */
5713         bnx2x_schedule_sp_task(bp);
5714 
5715         return IRQ_HANDLED;
5716 }
5717 
5718 /* end of slow path */
5719 
5720 void bnx2x_drv_pulse(struct bnx2x *bp)
5721 {
5722         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5723                  bp->fw_drv_pulse_wr_seq);
5724 }
5725 
5726 static void bnx2x_timer(unsigned long data)
5727 {
5728         struct bnx2x *bp = (struct bnx2x *) data;
5729 
5730         if (!netif_running(bp->dev))
5731                 return;
5732 
5733         if (IS_PF(bp) &&
5734             !BP_NOMCP(bp)) {
5735                 int mb_idx = BP_FW_MB_IDX(bp);
5736                 u16 drv_pulse;
5737                 u16 mcp_pulse;
5738 
5739                 ++bp->fw_drv_pulse_wr_seq;
5740                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5741                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5742                 bnx2x_drv_pulse(bp);
5743 
5744                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5745                              MCP_PULSE_SEQ_MASK);
5746                 /* The delta between driver pulse and mcp response
5747                  * should not get too big. If the MFW is more than 5 pulses
5748                  * behind, we should worry about it enough to generate an error
5749                  * log.
5750                  */
5751                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5752                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5753                                   drv_pulse, mcp_pulse);
5754         }
5755 
5756         if (bp->state == BNX2X_STATE_OPEN)
5757                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5758 
5759         /* sample pf vf bulletin board for new posts from pf */
5760         if (IS_VF(bp))
5761                 bnx2x_timer_sriov(bp);
5762 
5763         mod_timer(&bp->timer, jiffies + bp->current_interval);
5764 }
5765 
5766 /* end of Statistics */
5767 
5768 /* nic init */
5769 
5770 /*
5771  * nic init service functions
5772  */
5773 
5774 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5775 {
5776         u32 i;
5777         if (!(len%4) && !(addr%4))
5778                 for (i = 0; i < len; i += 4)
5779                         REG_WR(bp, addr + i, fill);
5780         else
5781                 for (i = 0; i < len; i++)
5782                         REG_WR8(bp, addr + i, fill);
5783 }
5784 
5785 /* helper: writes FP SP data to FW - data_size in dwords */
5786 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5787                                 int fw_sb_id,
5788                                 u32 *sb_data_p,
5789                                 u32 data_size)
5790 {
5791         int index;
5792         for (index = 0; index < data_size; index++)
5793                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5794                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5795                         sizeof(u32)*index,
5796                         *(sb_data_p + index));
5797 }
5798 
5799 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5800 {
5801         u32 *sb_data_p;
5802         u32 data_size = 0;
5803         struct hc_status_block_data_e2 sb_data_e2;
5804         struct hc_status_block_data_e1x sb_data_e1x;
5805 
5806         /* disable the function first */
5807         if (!CHIP_IS_E1x(bp)) {
5808                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5809                 sb_data_e2.common.state = SB_DISABLED;
5810                 sb_data_e2.common.p_func.vf_valid = false;
5811                 sb_data_p = (u32 *)&sb_data_e2;
5812                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5813         } else {
5814                 memset(&sb_data_e1x, 0,
5815                        sizeof(struct hc_status_block_data_e1x));
5816                 sb_data_e1x.common.state = SB_DISABLED;
5817                 sb_data_e1x.common.p_func.vf_valid = false;
5818                 sb_data_p = (u32 *)&sb_data_e1x;
5819                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5820         }
5821         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5822 
5823         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5824                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5825                         CSTORM_STATUS_BLOCK_SIZE);
5826         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5827                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5828                         CSTORM_SYNC_BLOCK_SIZE);
5829 }
5830 
5831 /* helper:  writes SP SB data to FW */
5832 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5833                 struct hc_sp_status_block_data *sp_sb_data)
5834 {
5835         int func = BP_FUNC(bp);
5836         int i;
5837         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5838                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5839                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5840                         i*sizeof(u32),
5841                         *((u32 *)sp_sb_data + i));
5842 }
5843 
5844 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5845 {
5846         int func = BP_FUNC(bp);
5847         struct hc_sp_status_block_data sp_sb_data;
5848         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5849 
5850         sp_sb_data.state = SB_DISABLED;
5851         sp_sb_data.p_func.vf_valid = false;
5852 
5853         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5854 
5855         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5856                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5857                         CSTORM_SP_STATUS_BLOCK_SIZE);
5858         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5859                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5860                         CSTORM_SP_SYNC_BLOCK_SIZE);
5861 }
5862 
5863 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5864                                            int igu_sb_id, int igu_seg_id)
5865 {
5866         hc_sm->igu_sb_id = igu_sb_id;
5867         hc_sm->igu_seg_id = igu_seg_id;
5868         hc_sm->timer_value = 0xFF;
5869         hc_sm->time_to_expire = 0xFFFFFFFF;
5870 }
5871 
5872 /* allocates state machine ids. */
5873 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5874 {
5875         /* zero out state machine indices */
5876         /* rx indices */
5877         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5878 
5879         /* tx indices */
5880         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5881         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5882         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5883         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5884 
5885         /* map indices */
5886         /* rx indices */
5887         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5888                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5889 
5890         /* tx indices */
5891         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5892                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5893         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5894                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5895         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5896                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5897         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5898                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5899 }
5900 
5901 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5902                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5903 {
5904         int igu_seg_id;
5905 
5906         struct hc_status_block_data_e2 sb_data_e2;
5907         struct hc_status_block_data_e1x sb_data_e1x;
5908         struct hc_status_block_sm  *hc_sm_p;
5909         int data_size;
5910         u32 *sb_data_p;
5911 
5912         if (CHIP_INT_MODE_IS_BC(bp))
5913                 igu_seg_id = HC_SEG_ACCESS_NORM;
5914         else
5915                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5916 
5917         bnx2x_zero_fp_sb(bp, fw_sb_id);
5918 
5919         if (!CHIP_IS_E1x(bp)) {
5920                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5921                 sb_data_e2.common.state = SB_ENABLED;
5922                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5923                 sb_data_e2.common.p_func.vf_id = vfid;
5924                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5925                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5926                 sb_data_e2.common.same_igu_sb_1b = true;
5927                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5928                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5929                 hc_sm_p = sb_data_e2.common.state_machine;
5930                 sb_data_p = (u32 *)&sb_data_e2;
5931                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5932                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5933         } else {
5934                 memset(&sb_data_e1x, 0,
5935                        sizeof(struct hc_status_block_data_e1x));
5936                 sb_data_e1x.common.state = SB_ENABLED;
5937                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5938                 sb_data_e1x.common.p_func.vf_id = 0xff;
5939                 sb_data_e1x.common.p_func.vf_valid = false;
5940                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5941                 sb_data_e1x.common.same_igu_sb_1b = true;
5942                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5943                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5944                 hc_sm_p = sb_data_e1x.common.state_machine;
5945                 sb_data_p = (u32 *)&sb_data_e1x;
5946                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5947                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5948         }
5949 
5950         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5951                                        igu_sb_id, igu_seg_id);
5952         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5953                                        igu_sb_id, igu_seg_id);
5954 
5955         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5956 
5957         /* write indices to HW - PCI guarantees endianity of regpairs */
5958         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5959 }
5960 
5961 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5962                                      u16 tx_usec, u16 rx_usec)
5963 {
5964         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5965                                     false, rx_usec);
5966         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5967                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5968                                        tx_usec);
5969         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5970                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5971                                        tx_usec);
5972         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5973                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5974                                        tx_usec);
5975 }
5976 
5977 static void bnx2x_init_def_sb(struct bnx2x *bp)
5978 {
5979         struct host_sp_status_block *def_sb = bp->def_status_blk;
5980         dma_addr_t mapping = bp->def_status_blk_mapping;
5981         int igu_sp_sb_index;
5982         int igu_seg_id;
5983         int port = BP_PORT(bp);
5984         int func = BP_FUNC(bp);
5985         int reg_offset, reg_offset_en5;
5986         u64 section;
5987         int index;
5988         struct hc_sp_status_block_data sp_sb_data;
5989         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5990 
5991         if (CHIP_INT_MODE_IS_BC(bp)) {
5992                 igu_sp_sb_index = DEF_SB_IGU_ID;
5993                 igu_seg_id = HC_SEG_ACCESS_DEF;
5994         } else {
5995                 igu_sp_sb_index = bp->igu_dsb_id;
5996                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5997         }
5998 
5999         /* ATTN */
6000         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6001                                             atten_status_block);
6002         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
6003 
6004         bp->attn_state = 0;
6005 
6006         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6007                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6008         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6009                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
6010         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
6011                 int sindex;
6012                 /* take care of sig[0]..sig[4] */
6013                 for (sindex = 0; sindex < 4; sindex++)
6014                         bp->attn_group[index].sig[sindex] =
6015                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
6016 
6017                 if (!CHIP_IS_E1x(bp))
6018                         /*
6019                          * enable5 is separate from the rest of the registers,
6020                          * and therefore the address skip is 4
6021                          * and not 16 between the different groups
6022                          */
6023                         bp->attn_group[index].sig[4] = REG_RD(bp,
6024                                         reg_offset_en5 + 0x4*index);
6025                 else
6026                         bp->attn_group[index].sig[4] = 0;
6027         }
6028 
6029         if (bp->common.int_block == INT_BLOCK_HC) {
6030                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6031                                      HC_REG_ATTN_MSG0_ADDR_L);
6032 
6033                 REG_WR(bp, reg_offset, U64_LO(section));
6034                 REG_WR(bp, reg_offset + 4, U64_HI(section));
6035         } else if (!CHIP_IS_E1x(bp)) {
6036                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6037                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6038         }
6039 
6040         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6041                                             sp_sb);
6042 
6043         bnx2x_zero_sp_sb(bp);
6044 
6045         /* PCI guarantees endianity of regpairs */
6046         sp_sb_data.state                = SB_ENABLED;
6047         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
6048         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
6049         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
6050         sp_sb_data.igu_seg_id           = igu_seg_id;
6051         sp_sb_data.p_func.pf_id         = func;
6052         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
6053         sp_sb_data.p_func.vf_id         = 0xff;
6054 
6055         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
6056 
6057         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6058 }
6059 
6060 void bnx2x_update_coalesce(struct bnx2x *bp)
6061 {
6062         int i;
6063 
6064         for_each_eth_queue(bp, i)
6065                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
6066                                          bp->tx_ticks, bp->rx_ticks);
6067 }
6068 
6069 static void bnx2x_init_sp_ring(struct bnx2x *bp)
6070 {
6071         spin_lock_init(&bp->spq_lock);
6072         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
6073 
6074         bp->spq_prod_idx = 0;
6075         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6076         bp->spq_prod_bd = bp->spq;
6077         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
6078 }
6079 
6080 static void bnx2x_init_eq_ring(struct bnx2x *bp)
6081 {
6082         int i;
6083         for (i = 1; i <= NUM_EQ_PAGES; i++) {
6084                 union event_ring_elem *elem =
6085                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6086 
6087                 elem->next_page.addr.hi =
6088                         cpu_to_le32(U64_HI(bp->eq_mapping +
6089                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6090                 elem->next_page.addr.lo =
6091                         cpu_to_le32(U64_LO(bp->eq_mapping +
6092                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
6093         }
6094         bp->eq_cons = 0;
6095         bp->eq_prod = NUM_EQ_DESC;
6096         bp->eq_cons_sb = BNX2X_EQ_INDEX;
6097         /* we want a warning message before it gets wrought... */
6098         atomic_set(&bp->eq_spq_left,
6099                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
6100 }
6101 
6102 /* called with netif_addr_lock_bh() */
6103 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6104                                unsigned long rx_mode_flags,
6105                                unsigned long rx_accept_flags,
6106                                unsigned long tx_accept_flags,
6107                                unsigned long ramrod_flags)
6108 {
6109         struct bnx2x_rx_mode_ramrod_params ramrod_param;
6110         int rc;
6111 
6112         memset(&ramrod_param, 0, sizeof(ramrod_param));
6113 
6114         /* Prepare ramrod parameters */
6115         ramrod_param.cid = 0;
6116         ramrod_param.cl_id = cl_id;
6117         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6118         ramrod_param.func_id = BP_FUNC(bp);
6119 
6120         ramrod_param.pstate = &bp->sp_state;
6121         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6122 
6123         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6124         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6125 
6126         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6127 
6128         ramrod_param.ramrod_flags = ramrod_flags;
6129         ramrod_param.rx_mode_flags = rx_mode_flags;
6130 
6131         ramrod_param.rx_accept_flags = rx_accept_flags;
6132         ramrod_param.tx_accept_flags = tx_accept_flags;
6133 
6134         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6135         if (rc < 0) {
6136                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6137                 return rc;
6138         }
6139 
6140         return 0;
6141 }
6142 
6143 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6144                                    unsigned long *rx_accept_flags,
6145                                    unsigned long *tx_accept_flags)
6146 {
6147         /* Clear the flags first */
6148         *rx_accept_flags = 0;
6149         *tx_accept_flags = 0;
6150 
6151         switch (rx_mode) {
6152         case BNX2X_RX_MODE_NONE:
6153                 /*
6154                  * 'drop all' supersedes any accept flags that may have been
6155                  * passed to the function.
6156                  */
6157                 break;
6158         case BNX2X_RX_MODE_NORMAL:
6159                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6160                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6161                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6162 
6163                 /* internal switching mode */
6164                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6165                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6166                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6167 
6168                 break;
6169         case BNX2X_RX_MODE_ALLMULTI:
6170                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6171                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6172                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6173 
6174                 /* internal switching mode */
6175                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6176                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6177                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6178 
6179                 break;
6180         case BNX2X_RX_MODE_PROMISC:
6181                 /* According to definition of SI mode, iface in promisc mode
6182                  * should receive matched and unmatched (in resolution of port)
6183                  * unicast packets.
6184                  */
6185                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6186                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6187                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6188                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6189 
6190                 /* internal switching mode */
6191                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6192                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6193 
6194                 if (IS_MF_SI(bp))
6195                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6196                 else
6197                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6198 
6199                 break;
6200         default:
6201                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6202                 return -EINVAL;
6203         }
6204 
6205         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
6206         if (rx_mode != BNX2X_RX_MODE_NONE) {
6207                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6208                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6209         }
6210 
6211         return 0;
6212 }
6213 
6214 /* called with netif_addr_lock_bh() */
6215 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6216 {
6217         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6218         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6219         int rc;
6220 
6221         if (!NO_FCOE(bp))
6222                 /* Configure rx_mode of FCoE Queue */
6223                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6224 
6225         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6226                                      &tx_accept_flags);
6227         if (rc)
6228                 return rc;
6229 
6230         __set_bit(RAMROD_RX, &ramrod_flags);
6231         __set_bit(RAMROD_TX, &ramrod_flags);
6232 
6233         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6234                                    rx_accept_flags, tx_accept_flags,
6235                                    ramrod_flags);
6236 }
6237 
6238 static void bnx2x_init_internal_common(struct bnx2x *bp)
6239 {
6240         int i;
6241 
6242         /* Zero this manually as its initialization is
6243            currently missing in the initTool */
6244         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6245                 REG_WR(bp, BAR_USTRORM_INTMEM +
6246                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
6247         if (!CHIP_IS_E1x(bp)) {
6248                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6249                         CHIP_INT_MODE_IS_BC(bp) ?
6250                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6251         }
6252 }
6253 
6254 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6255 {
6256         switch (load_code) {
6257         case FW_MSG_CODE_DRV_LOAD_COMMON:
6258         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6259                 bnx2x_init_internal_common(bp);
6260                 /* no break */
6261 
6262         case FW_MSG_CODE_DRV_LOAD_PORT:
6263                 /* nothing to do */
6264                 /* no break */
6265 
6266         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6267                 /* internal memory per function is
6268                    initialized inside bnx2x_pf_init */
6269                 break;
6270 
6271         default:
6272                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6273                 break;
6274         }
6275 }
6276 
6277 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6278 {
6279         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6280 }
6281 
6282 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6283 {
6284         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6285 }
6286 
6287 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6288 {
6289         if (CHIP_IS_E1x(fp->bp))
6290                 return BP_L_ID(fp->bp) + fp->index;
6291         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6292                 return bnx2x_fp_igu_sb_id(fp);
6293 }
6294 
6295 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6296 {
6297         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6298         u8 cos;
6299         unsigned long q_type = 0;
6300         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6301         fp->rx_queue = fp_idx;
6302         fp->cid = fp_idx;
6303         fp->cl_id = bnx2x_fp_cl_id(fp);
6304         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6305         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6306         /* qZone id equals to FW (per path) client id */
6307         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
6308 
6309         /* init shortcut */
6310         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6311 
6312         /* Setup SB indices */
6313         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6314 
6315         /* Configure Queue State object */
6316         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6317         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6318 
6319         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6320 
6321         /* init tx data */
6322         for_each_cos_in_tx_queue(fp, cos) {
6323                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6324                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6325                                   FP_COS_TO_TXQ(fp, cos, bp),
6326                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
6327                 cids[cos] = fp->txdata_ptr[cos]->cid;
6328         }
6329 
6330         /* nothing more for vf to do here */
6331         if (IS_VF(bp))
6332                 return;
6333 
6334         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6335                       fp->fw_sb_id, fp->igu_sb_id);
6336         bnx2x_update_fpsb_idx(fp);
6337         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6338                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6339                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6340 
6341         /**
6342          * Configure classification DBs: Always enable Tx switching
6343          */
6344         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6345 
6346         DP(NETIF_MSG_IFUP,
6347            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",