Version:  2.0.40 2.2.26 2.4.37 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8

Linux/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

  1 /* bnx2x_main.c: QLogic Everest network driver.
  2  *
  3  * Copyright (c) 2007-2013 Broadcom Corporation
  4  * Copyright (c) 2014 QLogic Corporation
  5  * All rights reserved
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License as published by
  9  * the Free Software Foundation.
 10  *
 11  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
 12  * Written by: Eliezer Tamir
 13  * Based on code from Michael Chan's bnx2 driver
 14  * UDP CSUM errata workaround by Arik Gendelman
 15  * Slowpath and fastpath rework by Vladislav Zolotarov
 16  * Statistics and Link management by Yitchak Gertner
 17  *
 18  */
 19 
 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 21 
 22 #include <linux/module.h>
 23 #include <linux/moduleparam.h>
 24 #include <linux/kernel.h>
 25 #include <linux/device.h>  /* for dev_info() */
 26 #include <linux/timer.h>
 27 #include <linux/errno.h>
 28 #include <linux/ioport.h>
 29 #include <linux/slab.h>
 30 #include <linux/interrupt.h>
 31 #include <linux/pci.h>
 32 #include <linux/aer.h>
 33 #include <linux/init.h>
 34 #include <linux/netdevice.h>
 35 #include <linux/etherdevice.h>
 36 #include <linux/skbuff.h>
 37 #include <linux/dma-mapping.h>
 38 #include <linux/bitops.h>
 39 #include <linux/irq.h>
 40 #include <linux/delay.h>
 41 #include <asm/byteorder.h>
 42 #include <linux/time.h>
 43 #include <linux/ethtool.h>
 44 #include <linux/mii.h>
 45 #include <linux/if_vlan.h>
 46 #include <linux/crash_dump.h>
 47 #include <net/ip.h>
 48 #include <net/ipv6.h>
 49 #include <net/tcp.h>
 50 #include <net/vxlan.h>
 51 #include <net/checksum.h>
 52 #include <net/ip6_checksum.h>
 53 #include <linux/workqueue.h>
 54 #include <linux/crc32.h>
 55 #include <linux/crc32c.h>
 56 #include <linux/prefetch.h>
 57 #include <linux/zlib.h>
 58 #include <linux/io.h>
 59 #include <linux/semaphore.h>
 60 #include <linux/stringify.h>
 61 #include <linux/vmalloc.h>
 62 #include "bnx2x.h"
 63 #include "bnx2x_init.h"
 64 #include "bnx2x_init_ops.h"
 65 #include "bnx2x_cmn.h"
 66 #include "bnx2x_vfpf.h"
 67 #include "bnx2x_dcb.h"
 68 #include "bnx2x_sp.h"
 69 #include <linux/firmware.h>
 70 #include "bnx2x_fw_file_hdr.h"
 71 /* FW files */
 72 #define FW_FILE_VERSION                                 \
 73         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
 74         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
 75         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
 76         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
 77 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
 78 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
 79 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
 80 
 81 /* Time in jiffies before concluding the transmitter is hung */
 82 #define TX_TIMEOUT              (5*HZ)
 83 
 84 static char version[] =
 85         "QLogic 5771x/578xx 10/20-Gigabit Ethernet Driver "
 86         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 87 
 88 MODULE_AUTHOR("Eliezer Tamir");
 89 MODULE_DESCRIPTION("QLogic "
 90                    "BCM57710/57711/57711E/"
 91                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
 92                    "57840/57840_MF Driver");
 93 MODULE_LICENSE("GPL");
 94 MODULE_VERSION(DRV_MODULE_VERSION);
 95 MODULE_FIRMWARE(FW_FILE_NAME_E1);
 96 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
 97 MODULE_FIRMWARE(FW_FILE_NAME_E2);
 98 
 99 int bnx2x_num_queues;
100 module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
101 MODULE_PARM_DESC(num_queues,
102                  " Set number of queues (default is as a number of CPUs)");
103 
104 static int disable_tpa;
105 module_param(disable_tpa, int, S_IRUGO);
106 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
107 
108 static int int_mode;
109 module_param(int_mode, int, S_IRUGO);
110 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
111                                 "(1 INT#x; 2 MSI)");
112 
113 static int dropless_fc;
114 module_param(dropless_fc, int, S_IRUGO);
115 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
116 
117 static int mrrs = -1;
118 module_param(mrrs, int, S_IRUGO);
119 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
120 
121 static int debug;
122 module_param(debug, int, S_IRUGO);
123 MODULE_PARM_DESC(debug, " Default debug msglevel");
124 
125 static struct workqueue_struct *bnx2x_wq;
126 struct workqueue_struct *bnx2x_iov_wq;
127 
128 struct bnx2x_mac_vals {
129         u32 xmac_addr;
130         u32 xmac_val;
131         u32 emac_addr;
132         u32 emac_val;
133         u32 umac_addr[2];
134         u32 umac_val[2];
135         u32 bmac_addr;
136         u32 bmac_val[2];
137 };
138 
139 enum bnx2x_board_type {
140         BCM57710 = 0,
141         BCM57711,
142         BCM57711E,
143         BCM57712,
144         BCM57712_MF,
145         BCM57712_VF,
146         BCM57800,
147         BCM57800_MF,
148         BCM57800_VF,
149         BCM57810,
150         BCM57810_MF,
151         BCM57810_VF,
152         BCM57840_4_10,
153         BCM57840_2_20,
154         BCM57840_MF,
155         BCM57840_VF,
156         BCM57811,
157         BCM57811_MF,
158         BCM57840_O,
159         BCM57840_MFO,
160         BCM57811_VF
161 };
162 
163 /* indexed by board_type, above */
164 static struct {
165         char *name;
166 } board_info[] = {
167         [BCM57710]      = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" },
168         [BCM57711]      = { "QLogic BCM57711 10 Gigabit PCIe" },
169         [BCM57711E]     = { "QLogic BCM57711E 10 Gigabit PCIe" },
170         [BCM57712]      = { "QLogic BCM57712 10 Gigabit Ethernet" },
171         [BCM57712_MF]   = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" },
172         [BCM57712_VF]   = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" },
173         [BCM57800]      = { "QLogic BCM57800 10 Gigabit Ethernet" },
174         [BCM57800_MF]   = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" },
175         [BCM57800_VF]   = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" },
176         [BCM57810]      = { "QLogic BCM57810 10 Gigabit Ethernet" },
177         [BCM57810_MF]   = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" },
178         [BCM57810_VF]   = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" },
179         [BCM57840_4_10] = { "QLogic BCM57840 10 Gigabit Ethernet" },
180         [BCM57840_2_20] = { "QLogic BCM57840 20 Gigabit Ethernet" },
181         [BCM57840_MF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
182         [BCM57840_VF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" },
183         [BCM57811]      = { "QLogic BCM57811 10 Gigabit Ethernet" },
184         [BCM57811_MF]   = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" },
185         [BCM57840_O]    = { "QLogic BCM57840 10/20 Gigabit Ethernet" },
186         [BCM57840_MFO]  = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
187         [BCM57811_VF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }
188 };
189 
190 #ifndef PCI_DEVICE_ID_NX2_57710
191 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
192 #endif
193 #ifndef PCI_DEVICE_ID_NX2_57711
194 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
195 #endif
196 #ifndef PCI_DEVICE_ID_NX2_57711E
197 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
198 #endif
199 #ifndef PCI_DEVICE_ID_NX2_57712
200 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
201 #endif
202 #ifndef PCI_DEVICE_ID_NX2_57712_MF
203 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
204 #endif
205 #ifndef PCI_DEVICE_ID_NX2_57712_VF
206 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
207 #endif
208 #ifndef PCI_DEVICE_ID_NX2_57800
209 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
210 #endif
211 #ifndef PCI_DEVICE_ID_NX2_57800_MF
212 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
213 #endif
214 #ifndef PCI_DEVICE_ID_NX2_57800_VF
215 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
216 #endif
217 #ifndef PCI_DEVICE_ID_NX2_57810
218 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
219 #endif
220 #ifndef PCI_DEVICE_ID_NX2_57810_MF
221 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
222 #endif
223 #ifndef PCI_DEVICE_ID_NX2_57840_O
224 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
225 #endif
226 #ifndef PCI_DEVICE_ID_NX2_57810_VF
227 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
228 #endif
229 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
230 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
231 #endif
232 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
233 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
234 #endif
235 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
236 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
237 #endif
238 #ifndef PCI_DEVICE_ID_NX2_57840_MF
239 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
240 #endif
241 #ifndef PCI_DEVICE_ID_NX2_57840_VF
242 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
243 #endif
244 #ifndef PCI_DEVICE_ID_NX2_57811
245 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
246 #endif
247 #ifndef PCI_DEVICE_ID_NX2_57811_MF
248 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
249 #endif
250 #ifndef PCI_DEVICE_ID_NX2_57811_VF
251 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
252 #endif
253 
254 static const struct pci_device_id bnx2x_pci_tbl[] = {
255         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
268         { PCI_VDEVICE(QLOGIC,   PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
272         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
273         { PCI_VDEVICE(QLOGIC,   PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
274         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
275         { PCI_VDEVICE(QLOGIC,   PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
276         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
277         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
278         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
279         { 0 }
280 };
281 
282 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
283 
284 /* Global resources for unloading a previously loaded device */
285 #define BNX2X_PREV_WAIT_NEEDED 1
286 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
287 static LIST_HEAD(bnx2x_prev_list);
288 
289 /* Forward declaration */
290 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
291 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
292 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
293 
294 /****************************************************************************
295 * General service functions
296 ****************************************************************************/
297 
298 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
299 
300 static void __storm_memset_dma_mapping(struct bnx2x *bp,
301                                        u32 addr, dma_addr_t mapping)
302 {
303         REG_WR(bp,  addr, U64_LO(mapping));
304         REG_WR(bp,  addr + 4, U64_HI(mapping));
305 }
306 
307 static void storm_memset_spq_addr(struct bnx2x *bp,
308                                   dma_addr_t mapping, u16 abs_fid)
309 {
310         u32 addr = XSEM_REG_FAST_MEMORY +
311                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
312 
313         __storm_memset_dma_mapping(bp, addr, mapping);
314 }
315 
316 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
317                                   u16 pf_id)
318 {
319         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
320                 pf_id);
321         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
322                 pf_id);
323         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
324                 pf_id);
325         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
326                 pf_id);
327 }
328 
329 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
330                                  u8 enable)
331 {
332         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
333                 enable);
334         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
335                 enable);
336         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
337                 enable);
338         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
339                 enable);
340 }
341 
342 static void storm_memset_eq_data(struct bnx2x *bp,
343                                  struct event_ring_data *eq_data,
344                                 u16 pfid)
345 {
346         size_t size = sizeof(struct event_ring_data);
347 
348         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
349 
350         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
351 }
352 
353 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
354                                  u16 pfid)
355 {
356         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
357         REG_WR16(bp, addr, eq_prod);
358 }
359 
360 /* used only at init
361  * locking is done by mcp
362  */
363 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
364 {
365         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
366         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
367         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
368                                PCICFG_VENDOR_ID_OFFSET);
369 }
370 
371 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
372 {
373         u32 val;
374 
375         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
376         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
377         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
378                                PCICFG_VENDOR_ID_OFFSET);
379 
380         return val;
381 }
382 
383 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
384 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
385 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
386 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
387 #define DMAE_DP_DST_NONE        "dst_addr [none]"
388 
389 static void bnx2x_dp_dmae(struct bnx2x *bp,
390                           struct dmae_command *dmae, int msglvl)
391 {
392         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
393         int i;
394 
395         switch (dmae->opcode & DMAE_COMMAND_DST) {
396         case DMAE_CMD_DST_PCI:
397                 if (src_type == DMAE_CMD_SRC_PCI)
398                         DP(msglvl, "DMAE: opcode 0x%08x\n"
399                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
400                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
401                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
402                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
403                            dmae->comp_addr_hi, dmae->comp_addr_lo,
404                            dmae->comp_val);
405                 else
406                         DP(msglvl, "DMAE: opcode 0x%08x\n"
407                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
408                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
409                            dmae->opcode, dmae->src_addr_lo >> 2,
410                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
411                            dmae->comp_addr_hi, dmae->comp_addr_lo,
412                            dmae->comp_val);
413                 break;
414         case DMAE_CMD_DST_GRC:
415                 if (src_type == DMAE_CMD_SRC_PCI)
416                         DP(msglvl, "DMAE: opcode 0x%08x\n"
417                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
418                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
419                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
420                            dmae->len, dmae->dst_addr_lo >> 2,
421                            dmae->comp_addr_hi, dmae->comp_addr_lo,
422                            dmae->comp_val);
423                 else
424                         DP(msglvl, "DMAE: opcode 0x%08x\n"
425                            "src [%08x], len [%d*4], dst [%08x]\n"
426                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
427                            dmae->opcode, dmae->src_addr_lo >> 2,
428                            dmae->len, dmae->dst_addr_lo >> 2,
429                            dmae->comp_addr_hi, dmae->comp_addr_lo,
430                            dmae->comp_val);
431                 break;
432         default:
433                 if (src_type == DMAE_CMD_SRC_PCI)
434                         DP(msglvl, "DMAE: opcode 0x%08x\n"
435                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
436                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
437                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
438                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
439                            dmae->comp_val);
440                 else
441                         DP(msglvl, "DMAE: opcode 0x%08x\n"
442                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
443                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
444                            dmae->opcode, dmae->src_addr_lo >> 2,
445                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
446                            dmae->comp_val);
447                 break;
448         }
449 
450         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
451                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
452                    i, *(((u32 *)dmae) + i));
453 }
454 
455 /* copy command into DMAE command memory and set DMAE command go */
456 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
457 {
458         u32 cmd_offset;
459         int i;
460 
461         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
462         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
463                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
464         }
465         REG_WR(bp, dmae_reg_go_c[idx], 1);
466 }
467 
468 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
469 {
470         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
471                            DMAE_CMD_C_ENABLE);
472 }
473 
474 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
475 {
476         return opcode & ~DMAE_CMD_SRC_RESET;
477 }
478 
479 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
480                              bool with_comp, u8 comp_type)
481 {
482         u32 opcode = 0;
483 
484         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
485                    (dst_type << DMAE_COMMAND_DST_SHIFT));
486 
487         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
488 
489         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
490         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
491                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
492         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
493 
494 #ifdef __BIG_ENDIAN
495         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
496 #else
497         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
498 #endif
499         if (with_comp)
500                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
501         return opcode;
502 }
503 
504 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
505                                       struct dmae_command *dmae,
506                                       u8 src_type, u8 dst_type)
507 {
508         memset(dmae, 0, sizeof(struct dmae_command));
509 
510         /* set the opcode */
511         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
512                                          true, DMAE_COMP_PCI);
513 
514         /* fill in the completion parameters */
515         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
516         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
517         dmae->comp_val = DMAE_COMP_VAL;
518 }
519 
520 /* issue a dmae command over the init-channel and wait for completion */
521 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
522                                u32 *comp)
523 {
524         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
525         int rc = 0;
526 
527         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
528 
529         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
530          * as long as this code is called both from syscall context and
531          * from ndo_set_rx_mode() flow that may be called from BH.
532          */
533 
534         spin_lock_bh(&bp->dmae_lock);
535 
536         /* reset completion */
537         *comp = 0;
538 
539         /* post the command on the channel used for initializations */
540         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
541 
542         /* wait for completion */
543         udelay(5);
544         while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
545 
546                 if (!cnt ||
547                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
548                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
549                         BNX2X_ERR("DMAE timeout!\n");
550                         rc = DMAE_TIMEOUT;
551                         goto unlock;
552                 }
553                 cnt--;
554                 udelay(50);
555         }
556         if (*comp & DMAE_PCI_ERR_FLAG) {
557                 BNX2X_ERR("DMAE PCI error!\n");
558                 rc = DMAE_PCI_ERROR;
559         }
560 
561 unlock:
562 
563         spin_unlock_bh(&bp->dmae_lock);
564 
565         return rc;
566 }
567 
568 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
569                       u32 len32)
570 {
571         int rc;
572         struct dmae_command dmae;
573 
574         if (!bp->dmae_ready) {
575                 u32 *data = bnx2x_sp(bp, wb_data[0]);
576 
577                 if (CHIP_IS_E1(bp))
578                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
579                 else
580                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
581                 return;
582         }
583 
584         /* set opcode and fixed command fields */
585         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
586 
587         /* fill in addresses and len */
588         dmae.src_addr_lo = U64_LO(dma_addr);
589         dmae.src_addr_hi = U64_HI(dma_addr);
590         dmae.dst_addr_lo = dst_addr >> 2;
591         dmae.dst_addr_hi = 0;
592         dmae.len = len32;
593 
594         /* issue the command and wait for completion */
595         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
596         if (rc) {
597                 BNX2X_ERR("DMAE returned failure %d\n", rc);
598 #ifdef BNX2X_STOP_ON_ERROR
599                 bnx2x_panic();
600 #endif
601         }
602 }
603 
604 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
605 {
606         int rc;
607         struct dmae_command dmae;
608 
609         if (!bp->dmae_ready) {
610                 u32 *data = bnx2x_sp(bp, wb_data[0]);
611                 int i;
612 
613                 if (CHIP_IS_E1(bp))
614                         for (i = 0; i < len32; i++)
615                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
616                 else
617                         for (i = 0; i < len32; i++)
618                                 data[i] = REG_RD(bp, src_addr + i*4);
619 
620                 return;
621         }
622 
623         /* set opcode and fixed command fields */
624         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
625 
626         /* fill in addresses and len */
627         dmae.src_addr_lo = src_addr >> 2;
628         dmae.src_addr_hi = 0;
629         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
630         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
631         dmae.len = len32;
632 
633         /* issue the command and wait for completion */
634         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
635         if (rc) {
636                 BNX2X_ERR("DMAE returned failure %d\n", rc);
637 #ifdef BNX2X_STOP_ON_ERROR
638                 bnx2x_panic();
639 #endif
640         }
641 }
642 
643 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
644                                       u32 addr, u32 len)
645 {
646         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
647         int offset = 0;
648 
649         while (len > dmae_wr_max) {
650                 bnx2x_write_dmae(bp, phys_addr + offset,
651                                  addr + offset, dmae_wr_max);
652                 offset += dmae_wr_max * 4;
653                 len -= dmae_wr_max;
654         }
655 
656         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
657 }
658 
659 enum storms {
660            XSTORM,
661            TSTORM,
662            CSTORM,
663            USTORM,
664            MAX_STORMS
665 };
666 
667 #define STORMS_NUM 4
668 #define REGS_IN_ENTRY 4
669 
670 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
671                                               enum storms storm,
672                                               int entry)
673 {
674         switch (storm) {
675         case XSTORM:
676                 return XSTORM_ASSERT_LIST_OFFSET(entry);
677         case TSTORM:
678                 return TSTORM_ASSERT_LIST_OFFSET(entry);
679         case CSTORM:
680                 return CSTORM_ASSERT_LIST_OFFSET(entry);
681         case USTORM:
682                 return USTORM_ASSERT_LIST_OFFSET(entry);
683         case MAX_STORMS:
684         default:
685                 BNX2X_ERR("unknown storm\n");
686         }
687         return -EINVAL;
688 }
689 
690 static int bnx2x_mc_assert(struct bnx2x *bp)
691 {
692         char last_idx;
693         int i, j, rc = 0;
694         enum storms storm;
695         u32 regs[REGS_IN_ENTRY];
696         u32 bar_storm_intmem[STORMS_NUM] = {
697                 BAR_XSTRORM_INTMEM,
698                 BAR_TSTRORM_INTMEM,
699                 BAR_CSTRORM_INTMEM,
700                 BAR_USTRORM_INTMEM
701         };
702         u32 storm_assert_list_index[STORMS_NUM] = {
703                 XSTORM_ASSERT_LIST_INDEX_OFFSET,
704                 TSTORM_ASSERT_LIST_INDEX_OFFSET,
705                 CSTORM_ASSERT_LIST_INDEX_OFFSET,
706                 USTORM_ASSERT_LIST_INDEX_OFFSET
707         };
708         char *storms_string[STORMS_NUM] = {
709                 "XSTORM",
710                 "TSTORM",
711                 "CSTORM",
712                 "USTORM"
713         };
714 
715         for (storm = XSTORM; storm < MAX_STORMS; storm++) {
716                 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
717                                    storm_assert_list_index[storm]);
718                 if (last_idx)
719                         BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
720                                   storms_string[storm], last_idx);
721 
722                 /* print the asserts */
723                 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
724                         /* read a single assert entry */
725                         for (j = 0; j < REGS_IN_ENTRY; j++)
726                                 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
727                                           bnx2x_get_assert_list_entry(bp,
728                                                                       storm,
729                                                                       i) +
730                                           sizeof(u32) * j);
731 
732                         /* log entry if it contains a valid assert */
733                         if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
734                                 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
735                                           storms_string[storm], i, regs[3],
736                                           regs[2], regs[1], regs[0]);
737                                 rc++;
738                         } else {
739                                 break;
740                         }
741                 }
742         }
743 
744         BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
745                   CHIP_IS_E1(bp) ? "everest1" :
746                   CHIP_IS_E1H(bp) ? "everest1h" :
747                   CHIP_IS_E2(bp) ? "everest2" : "everest3",
748                   BCM_5710_FW_MAJOR_VERSION,
749                   BCM_5710_FW_MINOR_VERSION,
750                   BCM_5710_FW_REVISION_VERSION);
751 
752         return rc;
753 }
754 
755 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
756 #define SCRATCH_BUFFER_SIZE(bp) \
757         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
758 
759 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
760 {
761         u32 addr, val;
762         u32 mark, offset;
763         __be32 data[9];
764         int word;
765         u32 trace_shmem_base;
766         if (BP_NOMCP(bp)) {
767                 BNX2X_ERR("NO MCP - can not dump\n");
768                 return;
769         }
770         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
771                 (bp->common.bc_ver & 0xff0000) >> 16,
772                 (bp->common.bc_ver & 0xff00) >> 8,
773                 (bp->common.bc_ver & 0xff));
774 
775         if (pci_channel_offline(bp->pdev)) {
776                 BNX2X_ERR("Cannot dump MCP info while in PCI error\n");
777                 return;
778         }
779 
780         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
781         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
782                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
783 
784         if (BP_PATH(bp) == 0)
785                 trace_shmem_base = bp->common.shmem_base;
786         else
787                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
788 
789         /* sanity */
790         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
791             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
792                                 SCRATCH_BUFFER_SIZE(bp)) {
793                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
794                           trace_shmem_base);
795                 return;
796         }
797 
798         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
799 
800         /* validate TRCB signature */
801         mark = REG_RD(bp, addr);
802         if (mark != MFW_TRACE_SIGNATURE) {
803                 BNX2X_ERR("Trace buffer signature is missing.");
804                 return ;
805         }
806 
807         /* read cyclic buffer pointer */
808         addr += 4;
809         mark = REG_RD(bp, addr);
810         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
811         if (mark >= trace_shmem_base || mark < addr + 4) {
812                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
813                 return;
814         }
815         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
816 
817         printk("%s", lvl);
818 
819         /* dump buffer after the mark */
820         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
821                 for (word = 0; word < 8; word++)
822                         data[word] = htonl(REG_RD(bp, offset + 4*word));
823                 data[8] = 0x0;
824                 pr_cont("%s", (char *)data);
825         }
826 
827         /* dump buffer before the mark */
828         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
829                 for (word = 0; word < 8; word++)
830                         data[word] = htonl(REG_RD(bp, offset + 4*word));
831                 data[8] = 0x0;
832                 pr_cont("%s", (char *)data);
833         }
834         printk("%s" "end of fw dump\n", lvl);
835 }
836 
837 static void bnx2x_fw_dump(struct bnx2x *bp)
838 {
839         bnx2x_fw_dump_lvl(bp, KERN_ERR);
840 }
841 
842 static void bnx2x_hc_int_disable(struct bnx2x *bp)
843 {
844         int port = BP_PORT(bp);
845         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
846         u32 val = REG_RD(bp, addr);
847 
848         /* in E1 we must use only PCI configuration space to disable
849          * MSI/MSIX capability
850          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
851          */
852         if (CHIP_IS_E1(bp)) {
853                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
854                  * Use mask register to prevent from HC sending interrupts
855                  * after we exit the function
856                  */
857                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
858 
859                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
860                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
861                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
862         } else
863                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
864                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
865                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
866                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
867 
868         DP(NETIF_MSG_IFDOWN,
869            "write %x to HC %d (addr 0x%x)\n",
870            val, port, addr);
871 
872         /* flush all outstanding writes */
873         mmiowb();
874 
875         REG_WR(bp, addr, val);
876         if (REG_RD(bp, addr) != val)
877                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
878 }
879 
880 static void bnx2x_igu_int_disable(struct bnx2x *bp)
881 {
882         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
883 
884         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
885                  IGU_PF_CONF_INT_LINE_EN |
886                  IGU_PF_CONF_ATTN_BIT_EN);
887 
888         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
889 
890         /* flush all outstanding writes */
891         mmiowb();
892 
893         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
894         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
895                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
896 }
897 
898 static void bnx2x_int_disable(struct bnx2x *bp)
899 {
900         if (bp->common.int_block == INT_BLOCK_HC)
901                 bnx2x_hc_int_disable(bp);
902         else
903                 bnx2x_igu_int_disable(bp);
904 }
905 
906 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
907 {
908         int i;
909         u16 j;
910         struct hc_sp_status_block_data sp_sb_data;
911         int func = BP_FUNC(bp);
912 #ifdef BNX2X_STOP_ON_ERROR
913         u16 start = 0, end = 0;
914         u8 cos;
915 #endif
916         if (IS_PF(bp) && disable_int)
917                 bnx2x_int_disable(bp);
918 
919         bp->stats_state = STATS_STATE_DISABLED;
920         bp->eth_stats.unrecoverable_error++;
921         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
922 
923         BNX2X_ERR("begin crash dump -----------------\n");
924 
925         /* Indices */
926         /* Common */
927         if (IS_PF(bp)) {
928                 struct host_sp_status_block *def_sb = bp->def_status_blk;
929                 int data_size, cstorm_offset;
930 
931                 BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
932                           bp->def_idx, bp->def_att_idx, bp->attn_state,
933                           bp->spq_prod_idx, bp->stats_counter);
934                 BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
935                           def_sb->atten_status_block.attn_bits,
936                           def_sb->atten_status_block.attn_bits_ack,
937                           def_sb->atten_status_block.status_block_id,
938                           def_sb->atten_status_block.attn_bits_index);
939                 BNX2X_ERR("     def (");
940                 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
941                         pr_cont("0x%x%s",
942                                 def_sb->sp_sb.index_values[i],
943                                 (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
944 
945                 data_size = sizeof(struct hc_sp_status_block_data) /
946                             sizeof(u32);
947                 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
948                 for (i = 0; i < data_size; i++)
949                         *((u32 *)&sp_sb_data + i) =
950                                 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
951                                            i * sizeof(u32));
952 
953                 pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
954                         sp_sb_data.igu_sb_id,
955                         sp_sb_data.igu_seg_id,
956                         sp_sb_data.p_func.pf_id,
957                         sp_sb_data.p_func.vnic_id,
958                         sp_sb_data.p_func.vf_id,
959                         sp_sb_data.p_func.vf_valid,
960                         sp_sb_data.state);
961         }
962 
963         for_each_eth_queue(bp, i) {
964                 struct bnx2x_fastpath *fp = &bp->fp[i];
965                 int loop;
966                 struct hc_status_block_data_e2 sb_data_e2;
967                 struct hc_status_block_data_e1x sb_data_e1x;
968                 struct hc_status_block_sm  *hc_sm_p =
969                         CHIP_IS_E1x(bp) ?
970                         sb_data_e1x.common.state_machine :
971                         sb_data_e2.common.state_machine;
972                 struct hc_index_data *hc_index_p =
973                         CHIP_IS_E1x(bp) ?
974                         sb_data_e1x.index_data :
975                         sb_data_e2.index_data;
976                 u8 data_size, cos;
977                 u32 *sb_data_p;
978                 struct bnx2x_fp_txdata txdata;
979 
980                 if (!bp->fp)
981                         break;
982 
983                 if (!fp->rx_cons_sb)
984                         continue;
985 
986                 /* Rx */
987                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
988                           i, fp->rx_bd_prod, fp->rx_bd_cons,
989                           fp->rx_comp_prod,
990                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
991                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
992                           fp->rx_sge_prod, fp->last_max_sge,
993                           le16_to_cpu(fp->fp_hc_idx));
994 
995                 /* Tx */
996                 for_each_cos_in_tx_queue(fp, cos)
997                 {
998                         if (!fp->txdata_ptr[cos])
999                                 break;
1000 
1001                         txdata = *fp->txdata_ptr[cos];
1002 
1003                         if (!txdata.tx_cons_sb)
1004                                 continue;
1005 
1006                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
1007                                   i, txdata.tx_pkt_prod,
1008                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
1009                                   txdata.tx_bd_cons,
1010                                   le16_to_cpu(*txdata.tx_cons_sb));
1011                 }
1012 
1013                 loop = CHIP_IS_E1x(bp) ?
1014                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1015 
1016                 /* host sb data */
1017 
1018                 if (IS_FCOE_FP(fp))
1019                         continue;
1020 
1021                 BNX2X_ERR("     run indexes (");
1022                 for (j = 0; j < HC_SB_MAX_SM; j++)
1023                         pr_cont("0x%x%s",
1024                                fp->sb_running_index[j],
1025                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1026 
1027                 BNX2X_ERR("     indexes (");
1028                 for (j = 0; j < loop; j++)
1029                         pr_cont("0x%x%s",
1030                                fp->sb_index_values[j],
1031                                (j == loop - 1) ? ")" : " ");
1032 
1033                 /* VF cannot access FW refelection for status block */
1034                 if (IS_VF(bp))
1035                         continue;
1036 
1037                 /* fw sb data */
1038                 data_size = CHIP_IS_E1x(bp) ?
1039                         sizeof(struct hc_status_block_data_e1x) :
1040                         sizeof(struct hc_status_block_data_e2);
1041                 data_size /= sizeof(u32);
1042                 sb_data_p = CHIP_IS_E1x(bp) ?
1043                         (u32 *)&sb_data_e1x :
1044                         (u32 *)&sb_data_e2;
1045                 /* copy sb data in here */
1046                 for (j = 0; j < data_size; j++)
1047                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1048                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1049                                 j * sizeof(u32));
1050 
1051                 if (!CHIP_IS_E1x(bp)) {
1052                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1053                                 sb_data_e2.common.p_func.pf_id,
1054                                 sb_data_e2.common.p_func.vf_id,
1055                                 sb_data_e2.common.p_func.vf_valid,
1056                                 sb_data_e2.common.p_func.vnic_id,
1057                                 sb_data_e2.common.same_igu_sb_1b,
1058                                 sb_data_e2.common.state);
1059                 } else {
1060                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1061                                 sb_data_e1x.common.p_func.pf_id,
1062                                 sb_data_e1x.common.p_func.vf_id,
1063                                 sb_data_e1x.common.p_func.vf_valid,
1064                                 sb_data_e1x.common.p_func.vnic_id,
1065                                 sb_data_e1x.common.same_igu_sb_1b,
1066                                 sb_data_e1x.common.state);
1067                 }
1068 
1069                 /* SB_SMs data */
1070                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1071                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1072                                 j, hc_sm_p[j].__flags,
1073                                 hc_sm_p[j].igu_sb_id,
1074                                 hc_sm_p[j].igu_seg_id,
1075                                 hc_sm_p[j].time_to_expire,
1076                                 hc_sm_p[j].timer_value);
1077                 }
1078 
1079                 /* Indices data */
1080                 for (j = 0; j < loop; j++) {
1081                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1082                                hc_index_p[j].flags,
1083                                hc_index_p[j].timeout);
1084                 }
1085         }
1086 
1087 #ifdef BNX2X_STOP_ON_ERROR
1088         if (IS_PF(bp)) {
1089                 /* event queue */
1090                 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1091                 for (i = 0; i < NUM_EQ_DESC; i++) {
1092                         u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1093 
1094                         BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1095                                   i, bp->eq_ring[i].message.opcode,
1096                                   bp->eq_ring[i].message.error);
1097                         BNX2X_ERR("data: %x %x %x\n",
1098                                   data[0], data[1], data[2]);
1099                 }
1100         }
1101 
1102         /* Rings */
1103         /* Rx */
1104         for_each_valid_rx_queue(bp, i) {
1105                 struct bnx2x_fastpath *fp = &bp->fp[i];
1106 
1107                 if (!bp->fp)
1108                         break;
1109 
1110                 if (!fp->rx_cons_sb)
1111                         continue;
1112 
1113                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1114                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1115                 for (j = start; j != end; j = RX_BD(j + 1)) {
1116                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1117                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1118 
1119                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1120                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1121                 }
1122 
1123                 start = RX_SGE(fp->rx_sge_prod);
1124                 end = RX_SGE(fp->last_max_sge);
1125                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1126                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1127                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1128 
1129                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1130                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1131                 }
1132 
1133                 start = RCQ_BD(fp->rx_comp_cons - 10);
1134                 end = RCQ_BD(fp->rx_comp_cons + 503);
1135                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1136                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1137 
1138                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1139                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1140                 }
1141         }
1142 
1143         /* Tx */
1144         for_each_valid_tx_queue(bp, i) {
1145                 struct bnx2x_fastpath *fp = &bp->fp[i];
1146 
1147                 if (!bp->fp)
1148                         break;
1149 
1150                 for_each_cos_in_tx_queue(fp, cos) {
1151                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1152 
1153                         if (!fp->txdata_ptr[cos])
1154                                 break;
1155 
1156                         if (!txdata->tx_cons_sb)
1157                                 continue;
1158 
1159                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1160                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1161                         for (j = start; j != end; j = TX_BD(j + 1)) {
1162                                 struct sw_tx_bd *sw_bd =
1163                                         &txdata->tx_buf_ring[j];
1164 
1165                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1166                                           i, cos, j, sw_bd->skb,
1167                                           sw_bd->first_bd);
1168                         }
1169 
1170                         start = TX_BD(txdata->tx_bd_cons - 10);
1171                         end = TX_BD(txdata->tx_bd_cons + 254);
1172                         for (j = start; j != end; j = TX_BD(j + 1)) {
1173                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1174 
1175                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1176                                           i, cos, j, tx_bd[0], tx_bd[1],
1177                                           tx_bd[2], tx_bd[3]);
1178                         }
1179                 }
1180         }
1181 #endif
1182         if (IS_PF(bp)) {
1183                 bnx2x_fw_dump(bp);
1184                 bnx2x_mc_assert(bp);
1185         }
1186         BNX2X_ERR("end crash dump -----------------\n");
1187 }
1188 
1189 /*
1190  * FLR Support for E2
1191  *
1192  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1193  * initialization.
1194  */
1195 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1196 #define FLR_WAIT_INTERVAL       50      /* usec */
1197 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1198 
1199 struct pbf_pN_buf_regs {
1200         int pN;
1201         u32 init_crd;
1202         u32 crd;
1203         u32 crd_freed;
1204 };
1205 
1206 struct pbf_pN_cmd_regs {
1207         int pN;
1208         u32 lines_occup;
1209         u32 lines_freed;
1210 };
1211 
1212 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1213                                      struct pbf_pN_buf_regs *regs,
1214                                      u32 poll_count)
1215 {
1216         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1217         u32 cur_cnt = poll_count;
1218 
1219         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1220         crd = crd_start = REG_RD(bp, regs->crd);
1221         init_crd = REG_RD(bp, regs->init_crd);
1222 
1223         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1224         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1225         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1226 
1227         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1228                (init_crd - crd_start))) {
1229                 if (cur_cnt--) {
1230                         udelay(FLR_WAIT_INTERVAL);
1231                         crd = REG_RD(bp, regs->crd);
1232                         crd_freed = REG_RD(bp, regs->crd_freed);
1233                 } else {
1234                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1235                            regs->pN);
1236                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1237                            regs->pN, crd);
1238                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1239                            regs->pN, crd_freed);
1240                         break;
1241                 }
1242         }
1243         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1244            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1245 }
1246 
1247 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1248                                      struct pbf_pN_cmd_regs *regs,
1249                                      u32 poll_count)
1250 {
1251         u32 occup, to_free, freed, freed_start;
1252         u32 cur_cnt = poll_count;
1253 
1254         occup = to_free = REG_RD(bp, regs->lines_occup);
1255         freed = freed_start = REG_RD(bp, regs->lines_freed);
1256 
1257         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1258         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1259 
1260         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1261                 if (cur_cnt--) {
1262                         udelay(FLR_WAIT_INTERVAL);
1263                         occup = REG_RD(bp, regs->lines_occup);
1264                         freed = REG_RD(bp, regs->lines_freed);
1265                 } else {
1266                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1267                            regs->pN);
1268                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1269                            regs->pN, occup);
1270                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1271                            regs->pN, freed);
1272                         break;
1273                 }
1274         }
1275         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1276            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1277 }
1278 
1279 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1280                                     u32 expected, u32 poll_count)
1281 {
1282         u32 cur_cnt = poll_count;
1283         u32 val;
1284 
1285         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1286                 udelay(FLR_WAIT_INTERVAL);
1287 
1288         return val;
1289 }
1290 
1291 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1292                                     char *msg, u32 poll_cnt)
1293 {
1294         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1295         if (val != 0) {
1296                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1297                 return 1;
1298         }
1299         return 0;
1300 }
1301 
1302 /* Common routines with VF FLR cleanup */
1303 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1304 {
1305         /* adjust polling timeout */
1306         if (CHIP_REV_IS_EMUL(bp))
1307                 return FLR_POLL_CNT * 2000;
1308 
1309         if (CHIP_REV_IS_FPGA(bp))
1310                 return FLR_POLL_CNT * 120;
1311 
1312         return FLR_POLL_CNT;
1313 }
1314 
1315 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1316 {
1317         struct pbf_pN_cmd_regs cmd_regs[] = {
1318                 {0, (CHIP_IS_E3B0(bp)) ?
1319                         PBF_REG_TQ_OCCUPANCY_Q0 :
1320                         PBF_REG_P0_TQ_OCCUPANCY,
1321                     (CHIP_IS_E3B0(bp)) ?
1322                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1323                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1324                 {1, (CHIP_IS_E3B0(bp)) ?
1325                         PBF_REG_TQ_OCCUPANCY_Q1 :
1326                         PBF_REG_P1_TQ_OCCUPANCY,
1327                     (CHIP_IS_E3B0(bp)) ?
1328                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1329                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1330                 {4, (CHIP_IS_E3B0(bp)) ?
1331                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1332                         PBF_REG_P4_TQ_OCCUPANCY,
1333                     (CHIP_IS_E3B0(bp)) ?
1334                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1335                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1336         };
1337 
1338         struct pbf_pN_buf_regs buf_regs[] = {
1339                 {0, (CHIP_IS_E3B0(bp)) ?
1340                         PBF_REG_INIT_CRD_Q0 :
1341                         PBF_REG_P0_INIT_CRD ,
1342                     (CHIP_IS_E3B0(bp)) ?
1343                         PBF_REG_CREDIT_Q0 :
1344                         PBF_REG_P0_CREDIT,
1345                     (CHIP_IS_E3B0(bp)) ?
1346                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1347                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1348                 {1, (CHIP_IS_E3B0(bp)) ?
1349                         PBF_REG_INIT_CRD_Q1 :
1350                         PBF_REG_P1_INIT_CRD,
1351                     (CHIP_IS_E3B0(bp)) ?
1352                         PBF_REG_CREDIT_Q1 :
1353                         PBF_REG_P1_CREDIT,
1354                     (CHIP_IS_E3B0(bp)) ?
1355                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1356                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1357                 {4, (CHIP_IS_E3B0(bp)) ?
1358                         PBF_REG_INIT_CRD_LB_Q :
1359                         PBF_REG_P4_INIT_CRD,
1360                     (CHIP_IS_E3B0(bp)) ?
1361                         PBF_REG_CREDIT_LB_Q :
1362                         PBF_REG_P4_CREDIT,
1363                     (CHIP_IS_E3B0(bp)) ?
1364                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1365                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1366         };
1367 
1368         int i;
1369 
1370         /* Verify the command queues are flushed P0, P1, P4 */
1371         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1372                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1373 
1374         /* Verify the transmission buffers are flushed P0, P1, P4 */
1375         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1376                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1377 }
1378 
1379 #define OP_GEN_PARAM(param) \
1380         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1381 
1382 #define OP_GEN_TYPE(type) \
1383         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1384 
1385 #define OP_GEN_AGG_VECT(index) \
1386         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1387 
1388 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1389 {
1390         u32 op_gen_command = 0;
1391         u32 comp_addr = BAR_CSTRORM_INTMEM +
1392                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1393         int ret = 0;
1394 
1395         if (REG_RD(bp, comp_addr)) {
1396                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1397                 return 1;
1398         }
1399 
1400         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1401         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1402         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1403         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1404 
1405         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1406         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1407 
1408         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1409                 BNX2X_ERR("FW final cleanup did not succeed\n");
1410                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1411                    (REG_RD(bp, comp_addr)));
1412                 bnx2x_panic();
1413                 return 1;
1414         }
1415         /* Zero completion for next FLR */
1416         REG_WR(bp, comp_addr, 0);
1417 
1418         return ret;
1419 }
1420 
1421 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1422 {
1423         u16 status;
1424 
1425         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1426         return status & PCI_EXP_DEVSTA_TRPND;
1427 }
1428 
1429 /* PF FLR specific routines
1430 */
1431 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1432 {
1433         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1434         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1435                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1436                         "CFC PF usage counter timed out",
1437                         poll_cnt))
1438                 return 1;
1439 
1440         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1441         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1442                         DORQ_REG_PF_USAGE_CNT,
1443                         "DQ PF usage counter timed out",
1444                         poll_cnt))
1445                 return 1;
1446 
1447         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1448         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1449                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1450                         "QM PF usage counter timed out",
1451                         poll_cnt))
1452                 return 1;
1453 
1454         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1455         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1456                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1457                         "Timers VNIC usage counter timed out",
1458                         poll_cnt))
1459                 return 1;
1460         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1461                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1462                         "Timers NUM_SCANS usage counter timed out",
1463                         poll_cnt))
1464                 return 1;
1465 
1466         /* Wait DMAE PF usage counter to zero */
1467         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1468                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1469                         "DMAE command register timed out",
1470                         poll_cnt))
1471                 return 1;
1472 
1473         return 0;
1474 }
1475 
1476 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1477 {
1478         u32 val;
1479 
1480         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1481         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1482 
1483         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1484         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1485 
1486         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1487         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1488 
1489         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1490         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1491 
1492         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1493         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1494 
1495         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1496         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1497 
1498         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1499         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1500 
1501         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1502         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1503            val);
1504 }
1505 
1506 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1507 {
1508         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1509 
1510         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1511 
1512         /* Re-enable PF target read access */
1513         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1514 
1515         /* Poll HW usage counters */
1516         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1517         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1518                 return -EBUSY;
1519 
1520         /* Zero the igu 'trailing edge' and 'leading edge' */
1521 
1522         /* Send the FW cleanup command */
1523         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1524                 return -EBUSY;
1525 
1526         /* ATC cleanup */
1527 
1528         /* Verify TX hw is flushed */
1529         bnx2x_tx_hw_flushed(bp, poll_cnt);
1530 
1531         /* Wait 100ms (not adjusted according to platform) */
1532         msleep(100);
1533 
1534         /* Verify no pending pci transactions */
1535         if (bnx2x_is_pcie_pending(bp->pdev))
1536                 BNX2X_ERR("PCIE Transactions still pending\n");
1537 
1538         /* Debug */
1539         bnx2x_hw_enable_status(bp);
1540 
1541         /*
1542          * Master enable - Due to WB DMAE writes performed before this
1543          * register is re-initialized as part of the regular function init
1544          */
1545         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1546 
1547         return 0;
1548 }
1549 
1550 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1551 {
1552         int port = BP_PORT(bp);
1553         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1554         u32 val = REG_RD(bp, addr);
1555         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1556         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1557         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1558 
1559         if (msix) {
1560                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1561                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1562                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1563                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1564                 if (single_msix)
1565                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1566         } else if (msi) {
1567                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1568                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1569                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1570                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1571         } else {
1572                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1573                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1574                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1575                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1576 
1577                 if (!CHIP_IS_E1(bp)) {
1578                         DP(NETIF_MSG_IFUP,
1579                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1580 
1581                         REG_WR(bp, addr, val);
1582 
1583                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1584                 }
1585         }
1586 
1587         if (CHIP_IS_E1(bp))
1588                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1589 
1590         DP(NETIF_MSG_IFUP,
1591            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1592            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1593 
1594         REG_WR(bp, addr, val);
1595         /*
1596          * Ensure that HC_CONFIG is written before leading/trailing edge config
1597          */
1598         mmiowb();
1599         barrier();
1600 
1601         if (!CHIP_IS_E1(bp)) {
1602                 /* init leading/trailing edge */
1603                 if (IS_MF(bp)) {
1604                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1605                         if (bp->port.pmf)
1606                                 /* enable nig and gpio3 attention */
1607                                 val |= 0x1100;
1608                 } else
1609                         val = 0xffff;
1610 
1611                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1612                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1613         }
1614 
1615         /* Make sure that interrupts are indeed enabled from here on */
1616         mmiowb();
1617 }
1618 
1619 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1620 {
1621         u32 val;
1622         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1623         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1624         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1625 
1626         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1627 
1628         if (msix) {
1629                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1630                          IGU_PF_CONF_SINGLE_ISR_EN);
1631                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1632                         IGU_PF_CONF_ATTN_BIT_EN);
1633 
1634                 if (single_msix)
1635                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1636         } else if (msi) {
1637                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1638                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1639                         IGU_PF_CONF_ATTN_BIT_EN |
1640                         IGU_PF_CONF_SINGLE_ISR_EN);
1641         } else {
1642                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1643                 val |= (IGU_PF_CONF_INT_LINE_EN |
1644                         IGU_PF_CONF_ATTN_BIT_EN |
1645                         IGU_PF_CONF_SINGLE_ISR_EN);
1646         }
1647 
1648         /* Clean previous status - need to configure igu prior to ack*/
1649         if ((!msix) || single_msix) {
1650                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1651                 bnx2x_ack_int(bp);
1652         }
1653 
1654         val |= IGU_PF_CONF_FUNC_EN;
1655 
1656         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1657            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1658 
1659         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1660 
1661         if (val & IGU_PF_CONF_INT_LINE_EN)
1662                 pci_intx(bp->pdev, true);
1663 
1664         barrier();
1665 
1666         /* init leading/trailing edge */
1667         if (IS_MF(bp)) {
1668                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1669                 if (bp->port.pmf)
1670                         /* enable nig and gpio3 attention */
1671                         val |= 0x1100;
1672         } else
1673                 val = 0xffff;
1674 
1675         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1676         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1677 
1678         /* Make sure that interrupts are indeed enabled from here on */
1679         mmiowb();
1680 }
1681 
1682 void bnx2x_int_enable(struct bnx2x *bp)
1683 {
1684         if (bp->common.int_block == INT_BLOCK_HC)
1685                 bnx2x_hc_int_enable(bp);
1686         else
1687                 bnx2x_igu_int_enable(bp);
1688 }
1689 
1690 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1691 {
1692         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1693         int i, offset;
1694 
1695         if (disable_hw)
1696                 /* prevent the HW from sending interrupts */
1697                 bnx2x_int_disable(bp);
1698 
1699         /* make sure all ISRs are done */
1700         if (msix) {
1701                 synchronize_irq(bp->msix_table[0].vector);
1702                 offset = 1;
1703                 if (CNIC_SUPPORT(bp))
1704                         offset++;
1705                 for_each_eth_queue(bp, i)
1706                         synchronize_irq(bp->msix_table[offset++].vector);
1707         } else
1708                 synchronize_irq(bp->pdev->irq);
1709 
1710         /* make sure sp_task is not running */
1711         cancel_delayed_work(&bp->sp_task);
1712         cancel_delayed_work(&bp->period_task);
1713         flush_workqueue(bnx2x_wq);
1714 }
1715 
1716 /* fast path */
1717 
1718 /*
1719  * General service functions
1720  */
1721 
1722 /* Return true if succeeded to acquire the lock */
1723 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1724 {
1725         u32 lock_status;
1726         u32 resource_bit = (1 << resource);
1727         int func = BP_FUNC(bp);
1728         u32 hw_lock_control_reg;
1729 
1730         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1731            "Trying to take a lock on resource %d\n", resource);
1732 
1733         /* Validating that the resource is within range */
1734         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1735                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1736                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1737                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1738                 return false;
1739         }
1740 
1741         if (func <= 5)
1742                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1743         else
1744                 hw_lock_control_reg =
1745                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1746 
1747         /* Try to acquire the lock */
1748         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1749         lock_status = REG_RD(bp, hw_lock_control_reg);
1750         if (lock_status & resource_bit)
1751                 return true;
1752 
1753         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1754            "Failed to get a lock on resource %d\n", resource);
1755         return false;
1756 }
1757 
1758 /**
1759  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1760  *
1761  * @bp: driver handle
1762  *
1763  * Returns the recovery leader resource id according to the engine this function
1764  * belongs to. Currently only only 2 engines is supported.
1765  */
1766 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1767 {
1768         if (BP_PATH(bp))
1769                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1770         else
1771                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1772 }
1773 
1774 /**
1775  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1776  *
1777  * @bp: driver handle
1778  *
1779  * Tries to acquire a leader lock for current engine.
1780  */
1781 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1782 {
1783         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1784 }
1785 
1786 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1787 
1788 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1789 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1790 {
1791         /* Set the interrupt occurred bit for the sp-task to recognize it
1792          * must ack the interrupt and transition according to the IGU
1793          * state machine.
1794          */
1795         atomic_set(&bp->interrupt_occurred, 1);
1796 
1797         /* The sp_task must execute only after this bit
1798          * is set, otherwise we will get out of sync and miss all
1799          * further interrupts. Hence, the barrier.
1800          */
1801         smp_wmb();
1802 
1803         /* schedule sp_task to workqueue */
1804         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1805 }
1806 
1807 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1808 {
1809         struct bnx2x *bp = fp->bp;
1810         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1811         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1812         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1813         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1814 
1815         DP(BNX2X_MSG_SP,
1816            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1817            fp->index, cid, command, bp->state,
1818            rr_cqe->ramrod_cqe.ramrod_type);
1819 
1820         /* If cid is within VF range, replace the slowpath object with the
1821          * one corresponding to this VF
1822          */
1823         if (cid >= BNX2X_FIRST_VF_CID  &&
1824             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1825                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1826 
1827         switch (command) {
1828         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1829                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1830                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1831                 break;
1832 
1833         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1834                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1835                 drv_cmd = BNX2X_Q_CMD_SETUP;
1836                 break;
1837 
1838         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1839                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1840                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1841                 break;
1842 
1843         case (RAMROD_CMD_ID_ETH_HALT):
1844                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1845                 drv_cmd = BNX2X_Q_CMD_HALT;
1846                 break;
1847 
1848         case (RAMROD_CMD_ID_ETH_TERMINATE):
1849                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1850                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1851                 break;
1852 
1853         case (RAMROD_CMD_ID_ETH_EMPTY):
1854                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1855                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1856                 break;
1857 
1858         case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1859                 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1860                 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1861                 break;
1862 
1863         default:
1864                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1865                           command, fp->index);
1866                 return;
1867         }
1868 
1869         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1870             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1871                 /* q_obj->complete_cmd() failure means that this was
1872                  * an unexpected completion.
1873                  *
1874                  * In this case we don't want to increase the bp->spq_left
1875                  * because apparently we haven't sent this command the first
1876                  * place.
1877                  */
1878 #ifdef BNX2X_STOP_ON_ERROR
1879                 bnx2x_panic();
1880 #else
1881                 return;
1882 #endif
1883 
1884         smp_mb__before_atomic();
1885         atomic_inc(&bp->cq_spq_left);
1886         /* push the change in bp->spq_left and towards the memory */
1887         smp_mb__after_atomic();
1888 
1889         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1890 
1891         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1892             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1893                 /* if Q update ramrod is completed for last Q in AFEX vif set
1894                  * flow, then ACK MCP at the end
1895                  *
1896                  * mark pending ACK to MCP bit.
1897                  * prevent case that both bits are cleared.
1898                  * At the end of load/unload driver checks that
1899                  * sp_state is cleared, and this order prevents
1900                  * races
1901                  */
1902                 smp_mb__before_atomic();
1903                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1904                 wmb();
1905                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1906                 smp_mb__after_atomic();
1907 
1908                 /* schedule the sp task as mcp ack is required */
1909                 bnx2x_schedule_sp_task(bp);
1910         }
1911 
1912         return;
1913 }
1914 
1915 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1916 {
1917         struct bnx2x *bp = netdev_priv(dev_instance);
1918         u16 status = bnx2x_ack_int(bp);
1919         u16 mask;
1920         int i;
1921         u8 cos;
1922 
1923         /* Return here if interrupt is shared and it's not for us */
1924         if (unlikely(status == 0)) {
1925                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1926                 return IRQ_NONE;
1927         }
1928         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1929 
1930 #ifdef BNX2X_STOP_ON_ERROR
1931         if (unlikely(bp->panic))
1932                 return IRQ_HANDLED;
1933 #endif
1934 
1935         for_each_eth_queue(bp, i) {
1936                 struct bnx2x_fastpath *fp = &bp->fp[i];
1937 
1938                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1939                 if (status & mask) {
1940                         /* Handle Rx or Tx according to SB id */
1941                         for_each_cos_in_tx_queue(fp, cos)
1942                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1943                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1944                         napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1945                         status &= ~mask;
1946                 }
1947         }
1948 
1949         if (CNIC_SUPPORT(bp)) {
1950                 mask = 0x2;
1951                 if (status & (mask | 0x1)) {
1952                         struct cnic_ops *c_ops = NULL;
1953 
1954                         rcu_read_lock();
1955                         c_ops = rcu_dereference(bp->cnic_ops);
1956                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1957                                       CNIC_DRV_STATE_HANDLES_IRQ))
1958                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1959                         rcu_read_unlock();
1960 
1961                         status &= ~mask;
1962                 }
1963         }
1964 
1965         if (unlikely(status & 0x1)) {
1966 
1967                 /* schedule sp task to perform default status block work, ack
1968                  * attentions and enable interrupts.
1969                  */
1970                 bnx2x_schedule_sp_task(bp);
1971 
1972                 status &= ~0x1;
1973                 if (!status)
1974                         return IRQ_HANDLED;
1975         }
1976 
1977         if (unlikely(status))
1978                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1979                    status);
1980 
1981         return IRQ_HANDLED;
1982 }
1983 
1984 /* Link */
1985 
1986 /*
1987  * General service functions
1988  */
1989 
1990 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1991 {
1992         u32 lock_status;
1993         u32 resource_bit = (1 << resource);
1994         int func = BP_FUNC(bp);
1995         u32 hw_lock_control_reg;
1996         int cnt;
1997 
1998         /* Validating that the resource is within range */
1999         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2000                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2001                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
2002                 return -EINVAL;
2003         }
2004 
2005         if (func <= 5) {
2006                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2007         } else {
2008                 hw_lock_control_reg =
2009                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2010         }
2011 
2012         /* Validating that the resource is not already taken */
2013         lock_status = REG_RD(bp, hw_lock_control_reg);
2014         if (lock_status & resource_bit) {
2015                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
2016                    lock_status, resource_bit);
2017                 return -EEXIST;
2018         }
2019 
2020         /* Try for 5 second every 5ms */
2021         for (cnt = 0; cnt < 1000; cnt++) {
2022                 /* Try to acquire the lock */
2023                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2024                 lock_status = REG_RD(bp, hw_lock_control_reg);
2025                 if (lock_status & resource_bit)
2026                         return 0;
2027 
2028                 usleep_range(5000, 10000);
2029         }
2030         BNX2X_ERR("Timeout\n");
2031         return -EAGAIN;
2032 }
2033 
2034 int bnx2x_release_leader_lock(struct bnx2x *bp)
2035 {
2036         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2037 }
2038 
2039 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2040 {
2041         u32 lock_status;
2042         u32 resource_bit = (1 << resource);
2043         int func = BP_FUNC(bp);
2044         u32 hw_lock_control_reg;
2045 
2046         /* Validating that the resource is within range */
2047         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2048                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2049                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
2050                 return -EINVAL;
2051         }
2052 
2053         if (func <= 5) {
2054                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2055         } else {
2056                 hw_lock_control_reg =
2057                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2058         }
2059 
2060         /* Validating that the resource is currently taken */
2061         lock_status = REG_RD(bp, hw_lock_control_reg);
2062         if (!(lock_status & resource_bit)) {
2063                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2064                           lock_status, resource_bit);
2065                 return -EFAULT;
2066         }
2067 
2068         REG_WR(bp, hw_lock_control_reg, resource_bit);
2069         return 0;
2070 }
2071 
2072 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2073 {
2074         /* The GPIO should be swapped if swap register is set and active */
2075         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2076                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2077         int gpio_shift = gpio_num +
2078                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2079         u32 gpio_mask = (1 << gpio_shift);
2080         u32 gpio_reg;
2081         int value;
2082 
2083         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2084                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2085                 return -EINVAL;
2086         }
2087 
2088         /* read GPIO value */
2089         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2090 
2091         /* get the requested pin value */
2092         if ((gpio_reg & gpio_mask) == gpio_mask)
2093                 value = 1;
2094         else
2095                 value = 0;
2096 
2097         return value;
2098 }
2099 
2100 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2101 {
2102         /* The GPIO should be swapped if swap register is set and active */
2103         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2104                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2105         int gpio_shift = gpio_num +
2106                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2107         u32 gpio_mask = (1 << gpio_shift);
2108         u32 gpio_reg;
2109 
2110         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2111                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2112                 return -EINVAL;
2113         }
2114 
2115         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2116         /* read GPIO and mask except the float bits */
2117         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2118 
2119         switch (mode) {
2120         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2121                 DP(NETIF_MSG_LINK,
2122                    "Set GPIO %d (shift %d) -> output low\n",
2123                    gpio_num, gpio_shift);
2124                 /* clear FLOAT and set CLR */
2125                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2126                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2127                 break;
2128 
2129         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2130                 DP(NETIF_MSG_LINK,
2131                    "Set GPIO %d (shift %d) -> output high\n",
2132                    gpio_num, gpio_shift);
2133                 /* clear FLOAT and set SET */
2134                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2135                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2136                 break;
2137 
2138         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2139                 DP(NETIF_MSG_LINK,
2140                    "Set GPIO %d (shift %d) -> input\n",
2141                    gpio_num, gpio_shift);
2142                 /* set FLOAT */
2143                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2144                 break;
2145 
2146         default:
2147                 break;
2148         }
2149 
2150         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2151         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2152 
2153         return 0;
2154 }
2155 
2156 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2157 {
2158         u32 gpio_reg = 0;
2159         int rc = 0;
2160 
2161         /* Any port swapping should be handled by caller. */
2162 
2163         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2164         /* read GPIO and mask except the float bits */
2165         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2166         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2167         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2168         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2169 
2170         switch (mode) {
2171         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2172                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2173                 /* set CLR */
2174                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2175                 break;
2176 
2177         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2178                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2179                 /* set SET */
2180                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2181                 break;
2182 
2183         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2184                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2185                 /* set FLOAT */
2186                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2187                 break;
2188 
2189         default:
2190                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2191                 rc = -EINVAL;
2192                 break;
2193         }
2194 
2195         if (rc == 0)
2196                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2197 
2198         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2199 
2200         return rc;
2201 }
2202 
2203 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2204 {
2205         /* The GPIO should be swapped if swap register is set and active */
2206         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2207                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2208         int gpio_shift = gpio_num +
2209                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2210         u32 gpio_mask = (1 << gpio_shift);
2211         u32 gpio_reg;
2212 
2213         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2214                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2215                 return -EINVAL;
2216         }
2217 
2218         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2219         /* read GPIO int */
2220         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2221 
2222         switch (mode) {
2223         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2224                 DP(NETIF_MSG_LINK,
2225                    "Clear GPIO INT %d (shift %d) -> output low\n",
2226                    gpio_num, gpio_shift);
2227                 /* clear SET and set CLR */
2228                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2229                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2230                 break;
2231 
2232         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2233                 DP(NETIF_MSG_LINK,
2234                    "Set GPIO INT %d (shift %d) -> output high\n",
2235                    gpio_num, gpio_shift);
2236                 /* clear CLR and set SET */
2237                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2238                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2239                 break;
2240 
2241         default:
2242                 break;
2243         }
2244 
2245         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2246         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2247 
2248         return 0;
2249 }
2250 
2251 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2252 {
2253         u32 spio_reg;
2254 
2255         /* Only 2 SPIOs are configurable */
2256         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2257                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2258                 return -EINVAL;
2259         }
2260 
2261         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2262         /* read SPIO and mask except the float bits */
2263         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2264 
2265         switch (mode) {
2266         case MISC_SPIO_OUTPUT_LOW:
2267                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2268                 /* clear FLOAT and set CLR */
2269                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2270                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2271                 break;
2272 
2273         case MISC_SPIO_OUTPUT_HIGH:
2274                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2275                 /* clear FLOAT and set SET */
2276                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2277                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2278                 break;
2279 
2280         case MISC_SPIO_INPUT_HI_Z:
2281                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2282                 /* set FLOAT */
2283                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2284                 break;
2285 
2286         default:
2287                 break;
2288         }
2289 
2290         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2291         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2292 
2293         return 0;
2294 }
2295 
2296 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2297 {
2298         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2299 
2300         bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2301                                            ADVERTISED_Pause);
2302         switch (bp->link_vars.ieee_fc &
2303                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2304         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2305                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2306                                                   ADVERTISED_Pause);
2307                 break;
2308 
2309         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2310                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2311                 break;
2312 
2313         default:
2314                 break;
2315         }
2316 }
2317 
2318 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2319 {
2320         /* Initialize link parameters structure variables
2321          * It is recommended to turn off RX FC for jumbo frames
2322          *  for better performance
2323          */
2324         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2325                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2326         else
2327                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2328 }
2329 
2330 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2331 {
2332         u32 pause_enabled = 0;
2333 
2334         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2335                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2336                         pause_enabled = 1;
2337 
2338                 REG_WR(bp, BAR_USTRORM_INTMEM +
2339                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2340                        pause_enabled);
2341         }
2342 
2343         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2344            pause_enabled ? "enabled" : "disabled");
2345 }
2346 
2347 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2348 {
2349         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2350         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2351 
2352         if (!BP_NOMCP(bp)) {
2353                 bnx2x_set_requested_fc(bp);
2354                 bnx2x_acquire_phy_lock(bp);
2355 
2356                 if (load_mode == LOAD_DIAG) {
2357                         struct link_params *lp = &bp->link_params;
2358                         lp->loopback_mode = LOOPBACK_XGXS;
2359                         /* Prefer doing PHY loopback at highest speed */
2360                         if (lp->req_line_speed[cfx_idx] < SPEED_20000) {
2361                                 if (lp->speed_cap_mask[cfx_idx] &
2362                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
2363                                         lp->req_line_speed[cfx_idx] =
2364                                         SPEED_20000;
2365                                 else if (lp->speed_cap_mask[cfx_idx] &
2366                                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2367                                                 lp->req_line_speed[cfx_idx] =
2368                                                 SPEED_10000;
2369                                 else
2370                                         lp->req_line_speed[cfx_idx] =
2371                                         SPEED_1000;
2372                         }
2373                 }
2374 
2375                 if (load_mode == LOAD_LOOPBACK_EXT) {
2376                         struct link_params *lp = &bp->link_params;
2377                         lp->loopback_mode = LOOPBACK_EXT;
2378                 }
2379 
2380                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2381 
2382                 bnx2x_release_phy_lock(bp);
2383 
2384                 bnx2x_init_dropless_fc(bp);
2385 
2386                 bnx2x_calc_fc_adv(bp);
2387 
2388                 if (bp->link_vars.link_up) {
2389                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2390                         bnx2x_link_report(bp);
2391                 }
2392                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2393                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2394                 return rc;
2395         }
2396         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2397         return -EINVAL;
2398 }
2399 
2400 void bnx2x_link_set(struct bnx2x *bp)
2401 {
2402         if (!BP_NOMCP(bp)) {
2403                 bnx2x_acquire_phy_lock(bp);
2404                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2405                 bnx2x_release_phy_lock(bp);
2406 
2407                 bnx2x_init_dropless_fc(bp);
2408 
2409                 bnx2x_calc_fc_adv(bp);
2410         } else
2411                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2412 }
2413 
2414 static void bnx2x__link_reset(struct bnx2x *bp)
2415 {
2416         if (!BP_NOMCP(bp)) {
2417                 bnx2x_acquire_phy_lock(bp);
2418                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2419                 bnx2x_release_phy_lock(bp);
2420         } else
2421                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2422 }
2423 
2424 void bnx2x_force_link_reset(struct bnx2x *bp)
2425 {
2426         bnx2x_acquire_phy_lock(bp);
2427         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2428         bnx2x_release_phy_lock(bp);
2429 }
2430 
2431 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2432 {
2433         u8 rc = 0;
2434 
2435         if (!BP_NOMCP(bp)) {
2436                 bnx2x_acquire_phy_lock(bp);
2437                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2438                                      is_serdes);
2439                 bnx2x_release_phy_lock(bp);
2440         } else
2441                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2442 
2443         return rc;
2444 }
2445 
2446 /* Calculates the sum of vn_min_rates.
2447    It's needed for further normalizing of the min_rates.
2448    Returns:
2449      sum of vn_min_rates.
2450        or
2451      0 - if all the min_rates are 0.
2452      In the later case fairness algorithm should be deactivated.
2453      If not all min_rates are zero then those that are zeroes will be set to 1.
2454  */
2455 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2456                                       struct cmng_init_input *input)
2457 {
2458         int all_zero = 1;
2459         int vn;
2460 
2461         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2462                 u32 vn_cfg = bp->mf_config[vn];
2463                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2464                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2465 
2466                 /* Skip hidden vns */
2467                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2468                         vn_min_rate = 0;
2469                 /* If min rate is zero - set it to 1 */
2470                 else if (!vn_min_rate)
2471                         vn_min_rate = DEF_MIN_RATE;
2472                 else
2473                         all_zero = 0;
2474 
2475                 input->vnic_min_rate[vn] = vn_min_rate;
2476         }
2477 
2478         /* if ETS or all min rates are zeros - disable fairness */
2479         if (BNX2X_IS_ETS_ENABLED(bp)) {
2480                 input->flags.cmng_enables &=
2481                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2482                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2483         } else if (all_zero) {
2484                 input->flags.cmng_enables &=
2485                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2486                 DP(NETIF_MSG_IFUP,
2487                    "All MIN values are zeroes fairness will be disabled\n");
2488         } else
2489                 input->flags.cmng_enables |=
2490                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2491 }
2492 
2493 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2494                                     struct cmng_init_input *input)
2495 {
2496         u16 vn_max_rate;
2497         u32 vn_cfg = bp->mf_config[vn];
2498 
2499         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2500                 vn_max_rate = 0;
2501         else {
2502                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2503 
2504                 if (IS_MF_PERCENT_BW(bp)) {
2505                         /* maxCfg in percents of linkspeed */
2506                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2507                 } else /* SD modes */
2508                         /* maxCfg is absolute in 100Mb units */
2509                         vn_max_rate = maxCfg * 100;
2510         }
2511 
2512         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2513 
2514         input->vnic_max_rate[vn] = vn_max_rate;
2515 }
2516 
2517 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2518 {
2519         if (CHIP_REV_IS_SLOW(bp))
2520                 return CMNG_FNS_NONE;
2521         if (IS_MF(bp))
2522                 return CMNG_FNS_MINMAX;
2523 
2524         return CMNG_FNS_NONE;
2525 }
2526 
2527 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2528 {
2529         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2530 
2531         if (BP_NOMCP(bp))
2532                 return; /* what should be the default value in this case */
2533 
2534         /* For 2 port configuration the absolute function number formula
2535          * is:
2536          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2537          *
2538          *      and there are 4 functions per port
2539          *
2540          * For 4 port configuration it is
2541          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2542          *
2543          *      and there are 2 functions per port
2544          */
2545         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2546                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2547 
2548                 if (func >= E1H_FUNC_MAX)
2549                         break;
2550 
2551                 bp->mf_config[vn] =
2552                         MF_CFG_RD(bp, func_mf_config[func].config);
2553         }
2554         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2555                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2556                 bp->flags |= MF_FUNC_DIS;
2557         } else {
2558                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2559                 bp->flags &= ~MF_FUNC_DIS;
2560         }
2561 }
2562 
2563 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2564 {
2565         struct cmng_init_input input;
2566         memset(&input, 0, sizeof(struct cmng_init_input));
2567 
2568         input.port_rate = bp->link_vars.line_speed;
2569 
2570         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2571                 int vn;
2572 
2573                 /* read mf conf from shmem */
2574                 if (read_cfg)
2575                         bnx2x_read_mf_cfg(bp);
2576 
2577                 /* vn_weight_sum and enable fairness if not 0 */
2578                 bnx2x_calc_vn_min(bp, &input);
2579 
2580                 /* calculate and set min-max rate for each vn */
2581                 if (bp->port.pmf)
2582                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2583                                 bnx2x_calc_vn_max(bp, vn, &input);
2584 
2585                 /* always enable rate shaping and fairness */
2586                 input.flags.cmng_enables |=
2587                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2588 
2589                 bnx2x_init_cmng(&input, &bp->cmng);
2590                 return;
2591         }
2592 
2593         /* rate shaping and fairness are disabled */
2594         DP(NETIF_MSG_IFUP,
2595            "rate shaping and fairness are disabled\n");
2596 }
2597 
2598 static void storm_memset_cmng(struct bnx2x *bp,
2599                               struct cmng_init *cmng,
2600                               u8 port)
2601 {
2602         int vn;
2603         size_t size = sizeof(struct cmng_struct_per_port);
2604 
2605         u32 addr = BAR_XSTRORM_INTMEM +
2606                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2607 
2608         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2609 
2610         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2611                 int func = func_by_vn(bp, vn);
2612 
2613                 addr = BAR_XSTRORM_INTMEM +
2614                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2615                 size = sizeof(struct rate_shaping_vars_per_vn);
2616                 __storm_memset_struct(bp, addr, size,
2617                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2618 
2619                 addr = BAR_XSTRORM_INTMEM +
2620                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2621                 size = sizeof(struct fairness_vars_per_vn);
2622                 __storm_memset_struct(bp, addr, size,
2623                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2624         }
2625 }
2626 
2627 /* init cmng mode in HW according to local configuration */
2628 void bnx2x_set_local_cmng(struct bnx2x *bp)
2629 {
2630         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2631 
2632         if (cmng_fns != CMNG_FNS_NONE) {
2633                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2634                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2635         } else {
2636                 /* rate shaping and fairness are disabled */
2637                 DP(NETIF_MSG_IFUP,
2638                    "single function mode without fairness\n");
2639         }
2640 }
2641 
2642 /* This function is called upon link interrupt */
2643 static void bnx2x_link_attn(struct bnx2x *bp)
2644 {
2645         /* Make sure that we are synced with the current statistics */
2646         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2647 
2648         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2649 
2650         bnx2x_init_dropless_fc(bp);
2651 
2652         if (bp->link_vars.link_up) {
2653 
2654                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2655                         struct host_port_stats *pstats;
2656 
2657                         pstats = bnx2x_sp(bp, port_stats);
2658                         /* reset old mac stats */
2659                         memset(&(pstats->mac_stx[0]), 0,
2660                                sizeof(struct mac_stx));
2661                 }
2662                 if (bp->state == BNX2X_STATE_OPEN)
2663                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2664         }
2665 
2666         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2667                 bnx2x_set_local_cmng(bp);
2668 
2669         __bnx2x_link_report(bp);
2670 
2671         if (IS_MF(bp))
2672                 bnx2x_link_sync_notify(bp);
2673 }
2674 
2675 void bnx2x__link_status_update(struct bnx2x *bp)
2676 {
2677         if (bp->state != BNX2X_STATE_OPEN)
2678                 return;
2679 
2680         /* read updated dcb configuration */
2681         if (IS_PF(bp)) {
2682                 bnx2x_dcbx_pmf_update(bp);
2683                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2684                 if (bp->link_vars.link_up)
2685                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2686                 else
2687                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2688                         /* indicate link status */
2689                 bnx2x_link_report(bp);
2690 
2691         } else { /* VF */
2692                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2693                                           SUPPORTED_10baseT_Full |
2694                                           SUPPORTED_100baseT_Half |
2695                                           SUPPORTED_100baseT_Full |
2696                                           SUPPORTED_1000baseT_Full |
2697                                           SUPPORTED_2500baseX_Full |
2698                                           SUPPORTED_10000baseT_Full |
2699                                           SUPPORTED_TP |
2700                                           SUPPORTED_FIBRE |
2701                                           SUPPORTED_Autoneg |
2702                                           SUPPORTED_Pause |
2703                                           SUPPORTED_Asym_Pause);
2704                 bp->port.advertising[0] = bp->port.supported[0];
2705 
2706                 bp->link_params.bp = bp;
2707                 bp->link_params.port = BP_PORT(bp);
2708                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2709                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2710                 bp->link_params.req_line_speed[0] = SPEED_10000;
2711                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2712                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2713                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2714                 bp->link_vars.line_speed = SPEED_10000;
2715                 bp->link_vars.link_status =
2716                         (LINK_STATUS_LINK_UP |
2717                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2718                 bp->link_vars.link_up = 1;
2719                 bp->link_vars.duplex = DUPLEX_FULL;
2720                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2721                 __bnx2x_link_report(bp);
2722 
2723                 bnx2x_sample_bulletin(bp);
2724 
2725                 /* if bulletin board did not have an update for link status
2726                  * __bnx2x_link_report will report current status
2727                  * but it will NOT duplicate report in case of already reported
2728                  * during sampling bulletin board.
2729                  */
2730                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2731         }
2732 }
2733 
2734 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2735                                   u16 vlan_val, u8 allowed_prio)
2736 {
2737         struct bnx2x_func_state_params func_params = {NULL};
2738         struct bnx2x_func_afex_update_params *f_update_params =
2739                 &func_params.params.afex_update;
2740 
2741         func_params.f_obj = &bp->func_obj;
2742         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2743 
2744         /* no need to wait for RAMROD completion, so don't
2745          * set RAMROD_COMP_WAIT flag
2746          */
2747 
2748         f_update_params->vif_id = vifid;
2749         f_update_params->afex_default_vlan = vlan_val;
2750         f_update_params->allowed_priorities = allowed_prio;
2751 
2752         /* if ramrod can not be sent, response to MCP immediately */
2753         if (bnx2x_func_state_change(bp, &func_params) < 0)
2754                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2755 
2756         return 0;
2757 }
2758 
2759 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2760                                           u16 vif_index, u8 func_bit_map)
2761 {
2762         struct bnx2x_func_state_params func_params = {NULL};
2763         struct bnx2x_func_afex_viflists_params *update_params =
2764                 &func_params.params.afex_viflists;
2765         int rc;
2766         u32 drv_msg_code;
2767 
2768         /* validate only LIST_SET and LIST_GET are received from switch */
2769         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2770                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2771                           cmd_type);
2772 
2773         func_params.f_obj = &bp->func_obj;
2774         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2775 
2776         /* set parameters according to cmd_type */
2777         update_params->afex_vif_list_command = cmd_type;
2778         update_params->vif_list_index = vif_index;
2779         update_params->func_bit_map =
2780                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2781         update_params->func_to_clear = 0;
2782         drv_msg_code =
2783                 (cmd_type == VIF_LIST_RULE_GET) ?
2784                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2785                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2786 
2787         /* if ramrod can not be sent, respond to MCP immediately for
2788          * SET and GET requests (other are not triggered from MCP)
2789          */
2790         rc = bnx2x_func_state_change(bp, &func_params);
2791         if (rc < 0)
2792                 bnx2x_fw_command(bp, drv_msg_code, 0);
2793 
2794         return 0;
2795 }
2796 
2797 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2798 {
2799         struct afex_stats afex_stats;
2800         u32 func = BP_ABS_FUNC(bp);
2801         u32 mf_config;
2802         u16 vlan_val;
2803         u32 vlan_prio;
2804         u16 vif_id;
2805         u8 allowed_prio;
2806         u8 vlan_mode;
2807         u32 addr_to_write, vifid, addrs, stats_type, i;
2808 
2809         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2810                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2811                 DP(BNX2X_MSG_MCP,
2812                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2813                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2814         }
2815 
2816         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2817                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2818                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2819                 DP(BNX2X_MSG_MCP,
2820                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2821                    vifid, addrs);
2822                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2823                                                addrs);
2824         }
2825 
2826         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2827                 addr_to_write = SHMEM2_RD(bp,
2828                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2829                 stats_type = SHMEM2_RD(bp,
2830                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2831 
2832                 DP(BNX2X_MSG_MCP,
2833                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2834                    addr_to_write);
2835 
2836                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2837 
2838                 /* write response to scratchpad, for MCP */
2839                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2840                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2841                                *(((u32 *)(&afex_stats))+i));
2842 
2843                 /* send ack message to MCP */
2844                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2845         }
2846 
2847         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2848                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2849                 bp->mf_config[BP_VN(bp)] = mf_config;
2850                 DP(BNX2X_MSG_MCP,
2851                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2852                    mf_config);
2853 
2854                 /* if VIF_SET is "enabled" */
2855                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2856                         /* set rate limit directly to internal RAM */
2857                         struct cmng_init_input cmng_input;
2858                         struct rate_shaping_vars_per_vn m_rs_vn;
2859                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2860                         u32 addr = BAR_XSTRORM_INTMEM +
2861                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2862 
2863                         bp->mf_config[BP_VN(bp)] = mf_config;
2864 
2865                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2866                         m_rs_vn.vn_counter.rate =
2867                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2868                         m_rs_vn.vn_counter.quota =
2869                                 (m_rs_vn.vn_counter.rate *
2870                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2871 
2872                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2873 
2874                         /* read relevant values from mf_cfg struct in shmem */
2875                         vif_id =
2876                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2877                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2878                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2879                         vlan_val =
2880                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2881                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2882                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2883                         vlan_prio = (mf_config &
2884                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2885                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2886                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2887                         vlan_mode =
2888                                 (MF_CFG_RD(bp,
2889                                            func_mf_config[func].afex_config) &
2890                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2891                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2892                         allowed_prio =
2893                                 (MF_CFG_RD(bp,
2894                                            func_mf_config[func].afex_config) &
2895                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2896                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2897 
2898                         /* send ramrod to FW, return in case of failure */
2899                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2900                                                    allowed_prio))
2901                                 return;
2902 
2903                         bp->afex_def_vlan_tag = vlan_val;
2904                         bp->afex_vlan_mode = vlan_mode;
2905                 } else {
2906                         /* notify link down because BP->flags is disabled */
2907                         bnx2x_link_report(bp);
2908 
2909                         /* send INVALID VIF ramrod to FW */
2910                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2911 
2912                         /* Reset the default afex VLAN */
2913                         bp->afex_def_vlan_tag = -1;
2914                 }
2915         }
2916 }
2917 
2918 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2919 {
2920         struct bnx2x_func_switch_update_params *switch_update_params;
2921         struct bnx2x_func_state_params func_params;
2922 
2923         memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2924         switch_update_params = &func_params.params.switch_update;
2925         func_params.f_obj = &bp->func_obj;
2926         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2927 
2928         if (IS_MF_UFP(bp) || IS_MF_BD(bp)) {
2929                 int func = BP_ABS_FUNC(bp);
2930                 u32 val;
2931 
2932                 /* Re-learn the S-tag from shmem */
2933                 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2934                                 FUNC_MF_CFG_E1HOV_TAG_MASK;
2935                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2936                         bp->mf_ov = val;
2937                 } else {
2938                         BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2939                         goto fail;
2940                 }
2941 
2942                 /* Configure new S-tag in LLH */
2943                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2944                        bp->mf_ov);
2945 
2946                 /* Send Ramrod to update FW of change */
2947                 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2948                           &switch_update_params->changes);
2949                 switch_update_params->vlan = bp->mf_ov;
2950 
2951                 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2952                         BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2953                                   bp->mf_ov);
2954                         goto fail;
2955                 } else {
2956                         DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n",
2957                            bp->mf_ov);
2958                 }
2959         } else {
2960                 goto fail;
2961         }
2962 
2963         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2964         return;
2965 fail:
2966         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2967 }
2968 
2969 static void bnx2x_pmf_update(struct bnx2x *bp)
2970 {
2971         int port = BP_PORT(bp);
2972         u32 val;
2973 
2974         bp->port.pmf = 1;
2975         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2976 
2977         /*
2978          * We need the mb() to ensure the ordering between the writing to
2979          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2980          */
2981         smp_mb();
2982 
2983         /* queue a periodic task */
2984         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2985 
2986         bnx2x_dcbx_pmf_update(bp);
2987 
2988         /* enable nig attention */
2989         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2990         if (bp->common.int_block == INT_BLOCK_HC) {
2991                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2992                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2993         } else if (!CHIP_IS_E1x(bp)) {
2994                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2995                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2996         }
2997 
2998         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2999 }
3000 
3001 /* end of Link */
3002 
3003 /* slow path */
3004 
3005 /*
3006  * General service functions
3007  */
3008 
3009 /* send the MCP a request, block until there is a reply */
3010 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
3011 {
3012         int mb_idx = BP_FW_MB_IDX(bp);
3013         u32 seq;
3014         u32 rc = 0;
3015         u32 cnt = 1;
3016         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3017 
3018         mutex_lock(&bp->fw_mb_mutex);
3019         seq = ++bp->fw_seq;
3020         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3021         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3022 
3023         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3024                         (command | seq), param);
3025 
3026         do {
3027                 /* let the FW do it's magic ... */
3028                 msleep(delay);
3029 
3030                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
3031 
3032                 /* Give the FW up to 5 second (500*10ms) */
3033         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
3034 
3035         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3036            cnt*delay, rc, seq);
3037 
3038         /* is this a reply to our command? */
3039         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3040                 rc &= FW_MSG_CODE_MASK;
3041         else {
3042                 /* FW BUG! */
3043                 BNX2X_ERR("FW failed to respond!\n");
3044                 bnx2x_fw_dump(bp);
3045                 rc = 0;
3046         }
3047         mutex_unlock(&bp->fw_mb_mutex);
3048 
3049         return rc;
3050 }
3051 
3052 static void storm_memset_func_cfg(struct bnx2x *bp,
3053                                  struct tstorm_eth_function_common_config *tcfg,
3054                                  u16 abs_fid)
3055 {
3056         size_t size = sizeof(struct tstorm_eth_function_common_config);
3057 
3058         u32 addr = BAR_TSTRORM_INTMEM +
3059                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3060 
3061         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3062 }
3063 
3064 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3065 {
3066         if (CHIP_IS_E1x(bp)) {
3067                 struct tstorm_eth_function_common_config tcfg = {0};
3068 
3069                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3070         }
3071 
3072         /* Enable the function in the FW */
3073         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3074         storm_memset_func_en(bp, p->func_id, 1);
3075 
3076         /* spq */
3077         if (p->spq_active) {
3078                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3079                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3080                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3081         }
3082 }
3083 
3084 /**
3085  * bnx2x_get_common_flags - Return common flags
3086  *
3087  * @bp          device handle
3088  * @fp          queue handle
3089  * @zero_stats  TRUE if statistics zeroing is needed
3090  *
3091  * Return the flags that are common for the Tx-only and not normal connections.
3092  */
3093 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3094                                             struct bnx2x_fastpath *fp,
3095                                             bool zero_stats)
3096 {
3097         unsigned long flags = 0;
3098 
3099         /* PF driver will always initialize the Queue to an ACTIVE state */
3100         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3101 
3102         /* tx only connections collect statistics (on the same index as the
3103          * parent connection). The statistics are zeroed when the parent
3104          * connection is initialized.
3105          */
3106 
3107         __set_bit(BNX2X_Q_FLG_STATS, &flags);
3108         if (zero_stats)
3109                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3110 
3111         if (bp->flags & TX_SWITCHING)
3112                 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3113 
3114         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3115         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3116 
3117 #ifdef BNX2X_STOP_ON_ERROR
3118         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3119 #endif
3120 
3121         return flags;
3122 }
3123 
3124 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3125                                        struct bnx2x_fastpath *fp,
3126                                        bool leading)
3127 {
3128         unsigned long flags = 0;
3129 
3130         /* calculate other queue flags */
3131         if (IS_MF_SD(bp))
3132                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3133 
3134         if (IS_FCOE_FP(fp)) {
3135                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3136                 /* For FCoE - force usage of default priority (for afex) */
3137                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3138         }
3139 
3140         if (fp->mode != TPA_MODE_DISABLED) {
3141                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3142                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3143                 if (fp->mode == TPA_MODE_GRO)
3144                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3145         }
3146 
3147         if (leading) {
3148                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3149                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3150         }
3151 
3152         /* Always set HW VLAN stripping */
3153         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3154 
3155         /* configure silent vlan removal */
3156         if (IS_MF_AFEX(bp))
3157                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3158 
3159         return flags | bnx2x_get_common_flags(bp, fp, true);
3160 }
3161 
3162 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3163         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3164         u8 cos)
3165 {
3166         gen_init->stat_id = bnx2x_stats_id(fp);
3167         gen_init->spcl_id = fp->cl_id;
3168 
3169         /* Always use mini-jumbo MTU for FCoE L2 ring */
3170         if (IS_FCOE_FP(fp))
3171                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3172         else
3173                 gen_init->mtu = bp->dev->mtu;
3174 
3175         gen_init->cos = cos;
3176 
3177         gen_init->fp_hsi = ETH_FP_HSI_VERSION;
3178 }
3179 
3180 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3181         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3182         struct bnx2x_rxq_setup_params *rxq_init)
3183 {
3184         u8 max_sge = 0;
3185         u16 sge_sz = 0;
3186         u16 tpa_agg_size = 0;
3187 
3188         if (fp->mode != TPA_MODE_DISABLED) {
3189                 pause->sge_th_lo = SGE_TH_LO(bp);
3190                 pause->sge_th_hi = SGE_TH_HI(bp);
3191 
3192                 /* validate SGE ring has enough to cross high threshold */
3193                 WARN_ON(bp->dropless_fc &&
3194                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3195                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3196 
3197                 tpa_agg_size = TPA_AGG_SIZE;
3198                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3199                         SGE_PAGE_SHIFT;
3200                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3201                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3202                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3203         }
3204 
3205         /* pause - not for e1 */
3206         if (!CHIP_IS_E1(bp)) {
3207                 pause->bd_th_lo = BD_TH_LO(bp);
3208                 pause->bd_th_hi = BD_TH_HI(bp);
3209 
3210                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3211                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3212                 /*
3213                  * validate that rings have enough entries to cross
3214                  * high thresholds
3215                  */
3216                 WARN_ON(bp->dropless_fc &&
3217                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3218                                 bp->rx_ring_size);
3219                 WARN_ON(bp->dropless_fc &&
3220                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3221                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3222 
3223                 pause->pri_map = 1;
3224         }
3225 
3226         /* rxq setup */
3227         rxq_init->dscr_map = fp->rx_desc_mapping;
3228         rxq_init->sge_map = fp->rx_sge_mapping;
3229         rxq_init->rcq_map = fp->rx_comp_mapping;
3230         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3231 
3232         /* This should be a maximum number of data bytes that may be
3233          * placed on the BD (not including paddings).
3234          */
3235         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3236                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3237 
3238         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3239         rxq_init->tpa_agg_sz = tpa_agg_size;
3240         rxq_init->sge_buf_sz = sge_sz;
3241         rxq_init->max_sges_pkt = max_sge;
3242         rxq_init->rss_engine_id = BP_FUNC(bp);
3243         rxq_init->mcast_engine_id = BP_FUNC(bp);
3244 
3245         /* Maximum number or simultaneous TPA aggregation for this Queue.
3246          *
3247          * For PF Clients it should be the maximum available number.
3248          * VF driver(s) may want to define it to a smaller value.
3249          */
3250         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3251 
3252         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3253         rxq_init->fw_sb_id = fp->fw_sb_id;
3254 
3255         if (IS_FCOE_FP(fp))
3256                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3257         else
3258                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3259         /* configure silent vlan removal
3260          * if multi function mode is afex, then mask default vlan
3261          */
3262         if (IS_MF_AFEX(bp)) {
3263                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3264                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3265         }
3266 }
3267 
3268 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3269         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3270         u8 cos)
3271 {
3272         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3273         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3274         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3275         txq_init->fw_sb_id = fp->fw_sb_id;
3276 
3277         /*
3278          * set the tss leading client id for TX classification ==
3279          * leading RSS client id
3280          */
3281         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3282 
3283         if (IS_FCOE_FP(fp)) {
3284                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3285                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3286         }
3287 }
3288 
3289 static void bnx2x_pf_init(struct bnx2x *bp)
3290 {
3291         struct bnx2x_func_init_params func_init = {0};
3292         struct event_ring_data eq_data = { {0} };
3293 
3294         if (!CHIP_IS_E1x(bp)) {
3295                 /* reset IGU PF statistics: MSIX + ATTN */
3296                 /* PF */
3297                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3298                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3299                            (CHIP_MODE_IS_4_PORT(bp) ?
3300                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3301                 /* ATTN */
3302                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3303                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3304                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3305                            (CHIP_MODE_IS_4_PORT(bp) ?
3306                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3307         }
3308 
3309         func_init.spq_active = true;
3310         func_init.pf_id = BP_FUNC(bp);
3311         func_init.func_id = BP_FUNC(bp);
3312         func_init.spq_map = bp->spq_mapping;
3313         func_init.spq_prod = bp->spq_prod_idx;
3314 
3315         bnx2x_func_init(bp, &func_init);
3316 
3317         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3318 
3319         /*
3320          * Congestion management values depend on the link rate
3321          * There is no active link so initial link rate is set to 10 Gbps.
3322          * When the link comes up The congestion management values are
3323          * re-calculated according to the actual link rate.
3324          */
3325         bp->link_vars.line_speed = SPEED_10000;
3326         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3327 
3328         /* Only the PMF sets the HW */
3329         if (bp->port.pmf)
3330                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3331 
3332         /* init Event Queue - PCI bus guarantees correct endianity*/
3333         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3334         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3335         eq_data.producer = bp->eq_prod;
3336         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3337         eq_data.sb_id = DEF_SB_ID;
3338         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3339 }
3340 
3341 static void bnx2x_e1h_disable(struct bnx2x *bp)
3342 {
3343         int port = BP_PORT(bp);
3344 
3345         bnx2x_tx_disable(bp);
3346 
3347         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3348 }
3349 
3350 static void bnx2x_e1h_enable(struct bnx2x *bp)
3351 {
3352         int port = BP_PORT(bp);
3353 
3354         if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3355                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3356 
3357         /* Tx queue should be only re-enabled */
3358         netif_tx_wake_all_queues(bp->dev);
3359 
3360         /*
3361          * Should not call netif_carrier_on since it will be called if the link
3362          * is up when checking for link state
3363          */
3364 }
3365 
3366 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3367 
3368 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3369 {
3370         struct eth_stats_info *ether_stat =
3371                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3372         struct bnx2x_vlan_mac_obj *mac_obj =
3373                 &bp->sp_objs->mac_obj;
3374         int i;
3375 
3376         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3377                 ETH_STAT_INFO_VERSION_LEN);
3378 
3379         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3380          * mac_local field in ether_stat struct. The base address is offset by 2
3381          * bytes to account for the field being 8 bytes but a mac address is
3382          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3383          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3384          * allocated by the ether_stat struct, so the macs will land in their
3385          * proper positions.
3386          */
3387         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3388                 memset(ether_stat->mac_local + i, 0,
3389                        sizeof(ether_stat->mac_local[0]));
3390         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3391                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3392                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3393                                 ETH_ALEN);
3394         ether_stat->mtu_size = bp->dev->mtu;
3395         if (bp->dev->features & NETIF_F_RXCSUM)
3396                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3397         if (bp->dev->features & NETIF_F_TSO)
3398                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3399         ether_stat->feature_flags |= bp->common.boot_mode;
3400 
3401         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3402 
3403         ether_stat->txq_size = bp->tx_ring_size;
3404         ether_stat->rxq_size = bp->rx_ring_size;
3405 
3406 #ifdef CONFIG_BNX2X_SRIOV
3407         ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3408 #endif
3409 }
3410 
3411 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3412 {
3413         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3414         struct fcoe_stats_info *fcoe_stat =
3415                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3416 
3417         if (!CNIC_LOADED(bp))
3418                 return;
3419 
3420         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3421 
3422         fcoe_stat->qos_priority =
3423                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3424 
3425         /* insert FCoE stats from ramrod response */
3426         if (!NO_FCOE(bp)) {
3427                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3428                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3429                         tstorm_queue_statistics;
3430 
3431                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3432                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3433                         xstorm_queue_statistics;
3434 
3435                 struct fcoe_statistics_params *fw_fcoe_stat =
3436                         &bp->fw_stats_data->fcoe;
3437 
3438                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3439                           fcoe_stat->rx_bytes_lo,
3440                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3441 
3442                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3443                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3444                           fcoe_stat->rx_bytes_lo,
3445                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3446 
3447                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3448                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3449                           fcoe_stat->rx_bytes_lo,
3450                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3451 
3452                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3453                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3454                           fcoe_stat->rx_bytes_lo,
3455                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3456 
3457                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3458                           fcoe_stat->rx_frames_lo,
3459                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3460 
3461                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3462                           fcoe_stat->rx_frames_lo,
3463                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3464 
3465                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3466                           fcoe_stat->rx_frames_lo,
3467                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3468 
3469                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3470                           fcoe_stat->rx_frames_lo,
3471                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3472 
3473                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3474                           fcoe_stat->tx_bytes_lo,
3475                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3476 
3477                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3478                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3479                           fcoe_stat->tx_bytes_lo,
3480                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3481 
3482                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3483                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3484                           fcoe_stat->tx_bytes_lo,
3485                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3486 
3487                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3488                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3489                           fcoe_stat->tx_bytes_lo,
3490                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3491 
3492                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3493                           fcoe_stat->tx_frames_lo,
3494                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3495 
3496                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3497                           fcoe_stat->tx_frames_lo,
3498                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3499 
3500                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3501                           fcoe_stat->tx_frames_lo,
3502                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3503 
3504                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3505                           fcoe_stat->tx_frames_lo,
3506                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3507         }
3508 
3509         /* ask L5 driver to add data to the struct */
3510         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3511 }
3512 
3513 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3514 {
3515         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3516         struct iscsi_stats_info *iscsi_stat =
3517                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3518 
3519         if (!CNIC_LOADED(bp))
3520                 return;
3521 
3522         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3523                ETH_ALEN);
3524 
3525         iscsi_stat->qos_priority =
3526                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3527 
3528         /* ask L5 driver to add data to the struct */
3529         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3530 }
3531 
3532 /* called due to MCP event (on pmf):
3533  *      reread new bandwidth configuration
3534  *      configure FW
3535  *      notify others function about the change
3536  */
3537 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3538 {
3539         if (bp->link_vars.link_up) {
3540                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3541                 bnx2x_link_sync_notify(bp);
3542         }
3543         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3544 }
3545 
3546 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3547 {
3548         bnx2x_config_mf_bw(bp);
3549         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3550 }
3551 
3552 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3553 {
3554         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3555         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3556 }
3557 
3558 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH        (20)
3559 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT         (25)
3560 
3561 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3562 {
3563         enum drv_info_opcode op_code;
3564         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3565         bool release = false;
3566         int wait;
3567 
3568         /* if drv_info version supported by MFW doesn't match - send NACK */
3569         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3570                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3571                 return;
3572         }
3573 
3574         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3575                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3576 
3577         /* Must prevent other flows from accessing drv_info_to_mcp */
3578         mutex_lock(&bp->drv_info_mutex);
3579 
3580         memset(&bp->slowpath->drv_info_to_mcp, 0,
3581                sizeof(union drv_info_to_mcp));
3582 
3583         switch (op_code) {
3584         case ETH_STATS_OPCODE:
3585                 bnx2x_drv_info_ether_stat(bp);
3586                 break;
3587         case FCOE_STATS_OPCODE:
3588                 bnx2x_drv_info_fcoe_stat(bp);
3589                 break;
3590         case ISCSI_STATS_OPCODE:
3591                 bnx2x_drv_info_iscsi_stat(bp);
3592                 break;
3593         default:
3594                 /* if op code isn't supported - send NACK */
3595                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3596                 goto out;
3597         }
3598 
3599         /* if we got drv_info attn from MFW then these fields are defined in
3600          * shmem2 for sure
3601          */
3602         SHMEM2_WR(bp, drv_info_host_addr_lo,
3603                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3604         SHMEM2_WR(bp, drv_info_host_addr_hi,
3605                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3606 
3607         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3608 
3609         /* Since possible management wants both this and get_driver_version
3610          * need to wait until management notifies us it finished utilizing
3611          * the buffer.
3612          */
3613         if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3614                 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3615         } else if (!bp->drv_info_mng_owner) {
3616                 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3617 
3618                 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3619                         u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3620 
3621                         /* Management is done; need to clear indication */
3622                         if (indication & bit) {
3623                                 SHMEM2_WR(bp, mfw_drv_indication,
3624                                           indication & ~bit);
3625                                 release = true;
3626                                 break;
3627                         }
3628 
3629                         msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3630                 }
3631         }
3632         if (!release) {
3633                 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3634                 bp->drv_info_mng_owner = true;
3635         }
3636 
3637 out:
3638         mutex_unlock(&bp->drv_info_mutex);
3639 }
3640 
3641 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3642 {
3643         u8 vals[4];
3644         int i = 0;
3645 
3646         if (bnx2x_format) {
3647                 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3648                            &vals[0], &vals[1], &vals[2], &vals[3]);
3649                 if (i > 0)
3650                         vals[0] -= '';
3651         } else {
3652                 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3653                            &vals[0], &vals[1], &vals[2], &vals[3]);
3654         }
3655 
3656         while (i < 4)
3657                 vals[i++] = 0;
3658 
3659         return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3660 }
3661 
3662 void bnx2x_update_mng_version(struct bnx2x *bp)
3663 {
3664         u32 iscsiver = DRV_VER_NOT_LOADED;
3665         u32 fcoever = DRV_VER_NOT_LOADED;
3666         u32 ethver = DRV_VER_NOT_LOADED;
3667         int idx = BP_FW_MB_IDX(bp);
3668         u8 *version;
3669 
3670         if (!SHMEM2_HAS(bp, func_os_drv_ver))
3671                 return;
3672 
3673         mutex_lock(&bp->drv_info_mutex);
3674         /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3675         if (bp->drv_info_mng_owner)
3676                 goto out;
3677 
3678         if (bp->state != BNX2X_STATE_OPEN)
3679                 goto out;
3680 
3681         /* Parse ethernet driver version */
3682         ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3683         if (!CNIC_LOADED(bp))
3684                 goto out;
3685 
3686         /* Try getting storage driver version via cnic */
3687         memset(&bp->slowpath->drv_info_to_mcp, 0,
3688                sizeof(union drv_info_to_mcp));
3689         bnx2x_drv_info_iscsi_stat(bp);
3690         version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3691         iscsiver = bnx2x_update_mng_version_utility(version, false);
3692 
3693         memset(&bp->slowpath->drv_info_to_mcp, 0,
3694                sizeof(union drv_info_to_mcp));
3695         bnx2x_drv_info_fcoe_stat(bp);
3696         version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3697         fcoever = bnx2x_update_mng_version_utility(version, false);
3698 
3699 out:
3700         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3701         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3702         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3703 
3704         mutex_unlock(&bp->drv_info_mutex);
3705 
3706         DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3707            ethver, iscsiver, fcoever);
3708 }
3709 
3710 void bnx2x_update_mfw_dump(struct bnx2x *bp)
3711 {
3712         u32 drv_ver;
3713         u32 valid_dump;
3714 
3715         if (!SHMEM2_HAS(bp, drv_info))
3716                 return;
3717 
3718         /* Update Driver load time, possibly broken in y2038 */
3719         SHMEM2_WR(bp, drv_info.epoc, (u32)ktime_get_real_seconds());
3720 
3721         drv_ver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3722         SHMEM2_WR(bp, drv_info.drv_ver, drv_ver);
3723 
3724         SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM));
3725 
3726         /* Check & notify On-Chip dump. */
3727         valid_dump = SHMEM2_RD(bp, drv_info.valid_dump);
3728 
3729         if (valid_dump & FIRST_DUMP_VALID)
3730                 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 1st partition\n");
3731 
3732         if (valid_dump & SECOND_DUMP_VALID)
3733                 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 2nd partition\n");
3734 }
3735 
3736 static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
3737 {
3738         u32 cmd_ok, cmd_fail;
3739 
3740         /* sanity */
3741         if (event & DRV_STATUS_DCC_EVENT_MASK &&
3742             event & DRV_STATUS_OEM_EVENT_MASK) {
3743                 BNX2X_ERR("Received simultaneous events %08x\n", event);
3744                 return;
3745         }
3746 
3747         if (event & DRV_STATUS_DCC_EVENT_MASK) {
3748                 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3749                 cmd_ok = DRV_MSG_CODE_DCC_OK;
3750         } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3751                 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3752                 cmd_ok = DRV_MSG_CODE_OEM_OK;
3753         }
3754 
3755         DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3756 
3757         if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3758                      DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3759                 /* This is the only place besides the function initialization
3760                  * where the bp->flags can change so it is done without any
3761                  * locks
3762                  */
3763                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3764                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3765                         bp->flags |= MF_FUNC_DIS;
3766 
3767                         bnx2x_e1h_disable(bp);
3768                 } else {
3769                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3770                         bp->flags &= ~MF_FUNC_DIS;
3771 
3772                         bnx2x_e1h_enable(bp);
3773                 }
3774                 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3775                            DRV_STATUS_OEM_DISABLE_ENABLE_PF);
3776         }
3777 
3778         if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3779                      DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
3780                 bnx2x_config_mf_bw(bp);
3781                 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3782                            DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
3783         }
3784 
3785         /* Report results to MCP */
3786         if (event)
3787                 bnx2x_fw_command(bp, cmd_fail, 0);
3788         else
3789                 bnx2x_fw_command(bp, cmd_ok, 0);
3790 }
3791 
3792 /* must be called under the spq lock */
3793 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3794 {
3795         struct eth_spe *next_spe = bp->spq_prod_bd;
3796 
3797         if (bp->spq_prod_bd == bp->spq_last_bd) {
3798                 bp->spq_prod_bd = bp->spq;
3799                 bp->spq_prod_idx = 0;
3800                 DP(BNX2X_MSG_SP, "end of spq\n");
3801         } else {
3802                 bp->spq_prod_bd++;
3803                 bp->spq_prod_idx++;
3804         }
3805         return next_spe;
3806 }
3807 
3808 /* must be called under the spq lock */
3809 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3810 {
3811         int func = BP_FUNC(bp);
3812 
3813         /*
3814          * Make sure that BD data is updated before writing the producer:
3815          * BD data is written to the memory, the producer is read from the
3816          * memory, thus we need a full memory barrier to ensure the ordering.
3817          */
3818         mb();
3819 
3820         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3821                  bp->spq_prod_idx);
3822         mmiowb();
3823 }
3824 
3825 /**
3826  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3827  *
3828  * @cmd:        command to check
3829  * @cmd_type:   command type
3830  */
3831 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3832 {
3833         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3834             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3835             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3836             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3837             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3838             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3839             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3840                 return true;
3841         else
3842                 return false;
3843 }
3844 
3845 /**
3846  * bnx2x_sp_post - place a single command on an SP ring
3847  *
3848  * @bp:         driver handle
3849  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3850  * @cid:        SW CID the command is related to
3851  * @data_hi:    command private data address (high 32 bits)
3852  * @data_lo:    command private data address (low 32 bits)
3853  * @cmd_type:   command type (e.g. NONE, ETH)
3854  *
3855  * SP data is handled as if it's always an address pair, thus data fields are
3856  * not swapped to little endian in upper functions. Instead this function swaps
3857  * data as if it's two u32 fields.
3858  */
3859 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3860                   u32 data_hi, u32 data_lo, int cmd_type)
3861 {
3862         struct eth_spe *spe;
3863         u16 type;
3864         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3865 
3866 #ifdef BNX2X_STOP_ON_ERROR
3867         if (unlikely(bp->panic)) {
3868                 BNX2X_ERR("Can't post SP when there is panic\n");
3869                 return -EIO;
3870         }
3871 #endif
3872 
3873         spin_lock_bh(&bp->spq_lock);
3874 
3875         if (common) {
3876                 if (!atomic_read(&bp->eq_spq_left)) {
3877                         BNX2X_ERR("BUG! EQ ring full!\n");
3878                         spin_unlock_bh(&bp->spq_lock);
3879                         bnx2x_panic();
3880                         return -EBUSY;
3881                 }
3882         } else if (!atomic_read(&bp->cq_spq_left)) {
3883                         BNX2X_ERR("BUG! SPQ ring full!\n");
3884                         spin_unlock_bh(&bp->spq_lock);
3885                         bnx2x_panic();
3886                         return -EBUSY;
3887         }
3888 
3889         spe = bnx2x_sp_get_next(bp);
3890 
3891         /* CID needs port number to be encoded int it */
3892         spe->hdr.conn_and_cmd_data =
3893                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3894                                     HW_CID(bp, cid));
3895 
3896         /* In some cases, type may already contain the func-id
3897          * mainly in SRIOV related use cases, so we add it here only
3898          * if it's not already set.
3899          */
3900         if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3901                 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3902                         SPE_HDR_CONN_TYPE;
3903                 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3904                          SPE_HDR_FUNCTION_ID);
3905         } else {
3906                 type = cmd_type;
3907         }
3908 
3909         spe->hdr.type = cpu_to_le16(type);
3910 
3911         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3912         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3913 
3914         /*
3915          * It's ok if the actual decrement is issued towards the memory
3916          * somewhere between the spin_lock and spin_unlock. Thus no
3917          * more explicit memory barrier is needed.
3918          */
3919         if (common)
3920                 atomic_dec(&bp->eq_spq_left);
3921         else
3922                 atomic_dec(&bp->cq_spq_left);
3923 
3924         DP(BNX2X_MSG_SP,
3925            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3926            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3927            (u32)(U64_LO(bp->spq_mapping) +
3928            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3929            HW_CID(bp, cid), data_hi, data_lo, type,
3930            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3931 
3932         bnx2x_sp_prod_update(bp);
3933         spin_unlock_bh(&bp->spq_lock);
3934         return 0;
3935 }
3936 
3937 /* acquire split MCP access lock register */
3938 static int bnx2x_acquire_alr(struct bnx2x *bp)
3939 {
3940         u32 j, val;
3941         int rc = 0;
3942 
3943         might_sleep();
3944         for (j = 0; j < 1000; j++) {
3945                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3946                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3947                 if (val & MCPR_ACCESS_LOCK_LOCK)
3948                         break;
3949 
3950                 usleep_range(5000, 10000);
3951         }
3952         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3953                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3954                 rc = -EBUSY;
3955         }
3956 
3957         return rc;
3958 }
3959 
3960 /* release split MCP access lock register */
3961 static void bnx2x_release_alr(struct bnx2x *bp)
3962 {
3963         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3964 }
3965 
3966 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3967 #define BNX2X_DEF_SB_IDX        0x0002
3968 
3969 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3970 {
3971         struct host_sp_status_block *def_sb = bp->def_status_blk;
3972         u16 rc = 0;
3973 
3974         barrier(); /* status block is written to by the chip */
3975         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3976                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3977                 rc |= BNX2X_DEF_SB_ATT_IDX;
3978         }
3979 
3980         if (bp->def_idx != def_sb->sp_sb.running_index) {
3981                 bp->def_idx = def_sb->sp_sb.running_index;
3982                 rc |= BNX2X_DEF_SB_IDX;
3983         }
3984 
3985         /* Do not reorder: indices reading should complete before handling */
3986         barrier();
3987         return rc;
3988 }
3989 
3990 /*
3991  * slow path service functions
3992  */
3993 
3994 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3995 {
3996         int port = BP_PORT(bp);
3997         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3998                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3999         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
4000                                        NIG_REG_MASK_INTERRUPT_PORT0;
4001         u32 aeu_mask;
4002         u32 nig_mask = 0;
4003         u32 reg_addr;
4004 
4005         if (bp->attn_state & asserted)
4006                 BNX2X_ERR("IGU ERROR\n");
4007 
4008         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4009         aeu_mask = REG_RD(bp, aeu_addr);
4010 
4011         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
4012            aeu_mask, asserted);
4013         aeu_mask &= ~(asserted & 0x3ff);
4014         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4015 
4016         REG_WR(bp, aeu_addr, aeu_mask);
4017         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4018 
4019         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4020         bp->attn_state |= asserted;
4021         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4022 
4023         if (asserted & ATTN_HARD_WIRED_MASK) {
4024                 if (asserted & ATTN_NIG_FOR_FUNC) {
4025 
4026                         bnx2x_acquire_phy_lock(bp);
4027 
4028                         /* save nig interrupt mask */
4029                         nig_mask = REG_RD(bp, nig_int_mask_addr);
4030 
4031                         /* If nig_mask is not set, no need to call the update
4032                          * function.
4033                          */
4034                         if (nig_mask) {
4035                                 REG_WR(bp, nig_int_mask_addr, 0);
4036 
4037                                 bnx2x_link_attn(bp);
4038                         }
4039 
4040                         /* handle unicore attn? */
4041                 }
4042                 if (asserted & ATTN_SW_TIMER_4_FUNC)
4043                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4044 
4045                 if (asserted & GPIO_2_FUNC)
4046                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4047 
4048                 if (asserted & GPIO_3_FUNC)
4049                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4050 
4051                 if (asserted & GPIO_4_FUNC)
4052                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4053 
4054                 if (port == 0) {
4055                         if (asserted & ATTN_GENERAL_ATTN_1) {
4056                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4057                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4058                         }
4059                         if (asserted & ATTN_GENERAL_ATTN_2) {
4060                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4061                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4062                         }
4063                         if (asserted & ATTN_GENERAL_ATTN_3) {
4064                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4065                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4066                         }
4067                 } else {
4068                         if (asserted & ATTN_GENERAL_ATTN_4) {
4069                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4070                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4071                         }
4072                         if (asserted & ATTN_GENERAL_ATTN_5) {
4073                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4074                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4075                         }
4076                         if (asserted & ATTN_GENERAL_ATTN_6) {
4077                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4078                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4079                         }
4080                 }
4081 
4082         } /* if hardwired */
4083 
4084         if (bp->common.int_block == INT_BLOCK_HC)
4085                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4086                             COMMAND_REG_ATTN_BITS_SET);
4087         else
4088                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4089 
4090         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4091            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4092         REG_WR(bp, reg_addr, asserted);
4093 
4094         /* now set back the mask */
4095         if (asserted & ATTN_NIG_FOR_FUNC) {
4096                 /* Verify that IGU ack through BAR was written before restoring
4097                  * NIG mask. This loop should exit after 2-3 iterations max.
4098                  */
4099                 if (bp->common.int_block != INT_BLOCK_HC) {
4100                         u32 cnt = 0, igu_acked;
4101                         do {
4102                                 igu_acked = REG_RD(bp,
4103                                                    IGU_REG_ATTENTION_ACK_BITS);
4104                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4105                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
4106                         if (!igu_acked)
4107                                 DP(NETIF_MSG_HW,
4108                                    "Failed to verify IGU ack on time\n");
4109                         barrier();
4110                 }
4111                 REG_WR(bp, nig_int_mask_addr, nig_mask);
4112                 bnx2x_release_phy_lock(bp);
4113         }
4114 }
4115 
4116 static void bnx2x_fan_failure(struct bnx2x *bp)
4117 {
4118         int port = BP_PORT(bp);
4119         u32 ext_phy_config;
4120         /* mark the failure */
4121         ext_phy_config =
4122                 SHMEM_RD(bp,
4123                          dev_info.port_hw_config[port].external_phy_config);
4124 
4125         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4126         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4127         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4128                  ext_phy_config);
4129 
4130         /* log the failure */
4131         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4132                             "Please contact OEM Support for assistance\n");
4133 
4134         /* Schedule device reset (unload)
4135          * This is due to some boards consuming sufficient power when driver is
4136          * up to overheat if fan fails.
4137          */
4138         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4139 }
4140 
4141 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4142 {
4143         int port = BP_PORT(bp);
4144         int reg_offset;
4145         u32 val;
4146 
4147         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4148                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4149 
4150         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4151 
4152                 val = REG_RD(bp, reg_offset);
4153                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4154                 REG_WR(bp, reg_offset, val);
4155 
4156                 BNX2X_ERR("SPIO5 hw attention\n");
4157 
4158                 /* Fan failure attention */
4159                 bnx2x_hw_reset_phy(&bp->link_params);
4160                 bnx2x_fan_failure(bp);
4161         }
4162 
4163         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4164                 bnx2x_acquire_phy_lock(bp);
4165                 bnx2x_handle_module_detect_int(&bp->link_params);
4166                 bnx2x_release_phy_lock(bp);
4167         }
4168 
4169         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4170 
4171                 val = REG_RD(bp, reg_offset);
4172                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4173                 REG_WR(bp, reg_offset, val);
4174 
4175                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4176                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
4177                 bnx2x_panic();
4178         }
4179 }
4180 
4181 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4182 {
4183         u32 val;
4184 
4185         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4186 
4187                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4188                 BNX2X_ERR("DB hw attention 0x%x\n", val);
4189                 /* DORQ discard attention */
4190                 if (val & 0x2)
4191                         BNX2X_ERR("FATAL error from DORQ\n");
4192         }
4193 
4194         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4195 
4196                 int port = BP_PORT(bp);
4197                 int reg_offset;
4198 
4199                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4200                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4201 
4202                 val = REG_RD(bp, reg_offset);
4203                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4204                 REG_WR(bp, reg_offset, val);
4205 
4206                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4207                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
4208                 bnx2x_panic();
4209         }
4210 }
4211 
4212 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4213 {
4214         u32 val;
4215 
4216         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4217 
4218                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4219                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4220                 /* CFC error attention */
4221                 if (val & 0x2)
4222                         BNX2X_ERR("FATAL error from CFC\n");
4223         }
4224 
4225         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4226                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4227                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4228                 /* RQ_USDMDP_FIFO_OVERFLOW */
4229                 if (val & 0x18000)
4230                         BNX2X_ERR("FATAL error from PXP\n");
4231 
4232                 if (!CHIP_IS_E1x(bp)) {
4233                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4234                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4235                 }
4236         }
4237 
4238         if (attn & HW_INTERRUT_ASSERT_SET_2) {
4239 
4240                 int port = BP_PORT(bp);
4241                 int reg_offset;
4242 
4243                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4244                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4245 
4246                 val = REG_RD(bp, reg_offset);
4247                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4248                 REG_WR(bp, reg_offset, val);
4249 
4250                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4251                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
4252                 bnx2x_panic();
4253         }
4254 }
4255 
4256 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4257 {
4258         u32 val;
4259 
4260         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4261 
4262                 if (attn & BNX2X_PMF_LINK_ASSERT) {
4263                         int func = BP_FUNC(bp);
4264 
4265                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4266                         bnx2x_read_mf_cfg(bp);
4267                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4268                                         func_mf_config[BP_ABS_FUNC(bp)].config);
4269                         val = SHMEM_RD(bp,
4270                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
4271 
4272                         if (val & (DRV_STATUS_DCC_EVENT_MASK |
4273                                    DRV_STATUS_OEM_EVENT_MASK))
4274                                 bnx2x_oem_event(bp,
4275                                         (val & (DRV_STATUS_DCC_EVENT_MASK |
4276                                                 DRV_STATUS_OEM_EVENT_MASK)));
4277 
4278                         if (val & DRV_STATUS_SET_MF_BW)
4279                                 bnx2x_set_mf_bw(bp);
4280 
4281                         if (val & DRV_STATUS_DRV_INFO_REQ)
4282                                 bnx2x_handle_drv_info_req(bp);
4283 
4284                         if (val & DRV_STATUS_VF_DISABLED)
4285                                 bnx2x_schedule_iov_task(bp,
4286                                                         BNX2X_IOV_HANDLE_FLR);
4287 
4288                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4289                                 bnx2x_pmf_update(bp);
4290 
4291                         if (bp->port.pmf &&
4292                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4293                                 bp->dcbx_enabled > 0)
4294                                 /* start dcbx state machine */
4295                                 bnx2x_dcbx_set_params(bp,
4296                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4297                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4298                                 bnx2x_handle_afex_cmd(bp,
4299                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4300                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4301                                 bnx2x_handle_eee_event(bp);
4302 
4303                         if (val & DRV_STATUS_OEM_UPDATE_SVID)
4304                                 bnx2x_handle_update_svid_cmd(bp);
4305 
4306                         if (bp->link_vars.periodic_flags &
4307                             PERIODIC_FLAGS_LINK_EVENT) {
4308                                 /*  sync with link */
4309                                 bnx2x_acquire_phy_lock(bp);
4310                                 bp->link_vars.periodic_flags &=
4311                                         ~PERIODIC_FLAGS_LINK_EVENT;
4312                                 bnx2x_release_phy_lock(bp);
4313                                 if (IS_MF(bp))
4314                                         bnx2x_link_sync_notify(bp);
4315                                 bnx2x_link_report(bp);
4316                         }
4317                         /* Always call it here: bnx2x_link_report() will
4318                          * prevent the link indication duplication.
4319                          */
4320                         bnx2x__link_status_update(bp);
4321                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4322 
4323                         BNX2X_ERR("MC assert!\n");
4324                         bnx2x_mc_assert(bp);
4325                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4326                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4327                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4328                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4329                         bnx2x_panic();
4330 
4331                 } else if (attn & BNX2X_MCP_ASSERT) {
4332 
4333                         BNX2X_ERR("MCP assert!\n");
4334                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4335                         bnx2x_fw_dump(bp);
4336 
4337                 } else
4338                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4339         }
4340 
4341         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4342                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4343                 if (attn & BNX2X_GRC_TIMEOUT) {
4344                         val = CHIP_IS_E1(bp) ? 0 :
4345                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4346                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4347                 }
4348                 if (attn & BNX2X_GRC_RSV) {
4349                         val = CHIP_IS_E1(bp) ? 0 :
4350                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4351                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4352                 }
4353                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4354         }
4355 }
4356 
4357 /*
4358  * Bits map:
4359  * 0-7   - Engine0 load counter.
4360  * 8-15  - Engine1 load counter.
4361  * 16    - Engine0 RESET_IN_PROGRESS bit.
4362  * 17    - Engine1 RESET_IN_PROGRESS bit.
4363  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4364  *         on the engine
4365  * 19    - Engine1 ONE_IS_LOADED.
4366  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4367  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4368  *         just the one belonging to its engine).
4369  *
4370  */
4371 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4372 
4373 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4374 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4375 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4376 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4377 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4378 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4379 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4380 
4381 /*
4382  * Set the GLOBAL_RESET bit.
4383  *
4384  * Should be run under rtnl lock
4385  */
4386 void bnx2x_set_reset_global(struct bnx2x *bp)
4387 {
4388         u32 val;
4389         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4390         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4391         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4392         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4393 }
4394 
4395 /*
4396  * Clear the GLOBAL_RESET bit.
4397  *
4398  * Should be run under rtnl lock
4399  */
4400 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4401 {
4402         u32 val;
4403         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4404         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4405         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4406         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4407 }
4408 
4409 /*
4410  * Checks the GLOBAL_RESET bit.
4411  *
4412  * should be run under rtnl lock
4413  */
4414 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4415 {
4416         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4417 
4418         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4419         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4420 }
4421 
4422 /*
4423  * Clear RESET_IN_PROGRESS bit for the current engine.
4424  *
4425  * Should be run under rtnl lock
4426  */
4427 static void bnx2x_set_reset_done(struct bnx2x *bp)
4428 {
4429         u32 val;
4430         u32 bit = BP_PATH(bp) ?
4431                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4432         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4433         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4434 
4435         /* Clear the bit */
4436         val &= ~bit;
4437         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4438 
4439         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4440 }
4441 
4442 /*
4443  * Set RESET_IN_PROGRESS for the current engine.
4444  *
4445  * should be run under rtnl lock
4446  */
4447 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4448 {
4449         u32 val;
4450         u32 bit = BP_PATH(bp) ?
4451                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4452         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4453         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4454 
4455         /* Set the bit */
4456         val |= bit;
4457         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4458         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4459 }
4460 
4461 /*
4462  * Checks the RESET_IN_PROGRESS bit for the given engine.
4463  * should be run under rtnl lock
4464  */
4465 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4466 {
4467         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4468         u32 bit = engine ?
4469                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4470 
4471         /* return false if bit is set */
4472         return (val & bit) ? false : true;
4473 }
4474 
4475 /*
4476  * set pf load for the current pf.
4477  *
4478  * should be run under rtnl lock
4479  */
4480 void bnx2x_set_pf_load(struct bnx2x *bp)
4481 {
4482         u32 val1, val;
4483         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4484                              BNX2X_PATH0_LOAD_CNT_MASK;
4485         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4486                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4487 
4488         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4489         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4490 
4491         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4492 
4493         /* get the current counter value */
4494         val1 = (val & mask) >> shift;
4495 
4496         /* set bit of that PF */
4497         val1 |= (1 << bp->pf_num);
4498 
4499         /* clear the old value */
4500         val &= ~mask;
4501 
4502         /* set the new one */
4503         val |= ((val1 << shift) & mask);
4504 
4505         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4506         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4507 }
4508 
4509 /**
4510  * bnx2x_clear_pf_load - clear pf load mark
4511  *
4512  * @bp:         driver handle
4513  *
4514  * Should be run under rtnl lock.
4515  * Decrements the load counter for the current engine. Returns
4516  * whether other functions are still loaded
4517  */
4518 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4519 {
4520         u32 val1, val;
4521         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4522                              BNX2X_PATH0_LOAD_CNT_MASK;
4523         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4524                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4525 
4526         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4527         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4528         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4529 
4530         /* get the current counter value */
4531         val1 = (val & mask) >> shift;
4532 
4533         /* clear bit of that PF */
4534         val1 &= ~(1 << bp->pf_num);
4535 
4536         /* clear the old value */
4537         val &= ~mask;
4538 
4539         /* set the new one */
4540         val |= ((val1 << shift) & mask);
4541 
4542         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4543         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4544         return val1 != 0;
4545 }
4546 
4547 /*
4548  * Read the load status for the current engine.
4549  *
4550  * should be run under rtnl lock
4551  */
4552 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4553 {
4554         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4555                              BNX2X_PATH0_LOAD_CNT_MASK);
4556         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4557                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4558         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4559 
4560         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4561 
4562         val = (val & mask) >> shift;
4563 
4564         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4565            engine, val);
4566 
4567         return val != 0;
4568 }
4569 
4570 static void _print_parity(struct bnx2x *bp, u32 reg)
4571 {
4572         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4573 }
4574 
4575 static void _print_next_block(int idx, const char *blk)
4576 {
4577         pr_cont("%s%s", idx ? ", " : "", blk);
4578 }
4579 
4580 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4581                                             int *par_num, bool print)
4582 {
4583         u32 cur_bit;
4584         bool res;
4585         int i;
4586 
4587         res = false;
4588 
4589         for (i = 0; sig; i++) {
4590                 cur_bit = (0x1UL << i);
4591                 if (sig & cur_bit) {
4592                         res |= true; /* Each bit is real error! */
4593 
4594                         if (print) {
4595                                 switch (cur_bit) {
4596                                 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4597                                         _print_next_block((*par_num)++, "BRB");
4598                                         _print_parity(bp,
4599                                                       BRB1_REG_BRB1_PRTY_STS);
4600                                         break;
4601                                 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4602                                         _print_next_block((*par_num)++,
4603                                                           "PARSER");
4604                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4605                                         break;
4606                                 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4607                                         _print_next_block((*par_num)++, "TSDM");
4608                                         _print_parity(bp,
4609                                                       TSDM_REG_TSDM_PRTY_STS);
4610                                         break;
4611                                 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4612                                         _print_next_block((*par_num)++,
4613                                                           "SEARCHER");
4614                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4615                                         break;
4616                                 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4617                                         _print_next_block((*par_num)++, "TCM");
4618                                         _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4619                                         break;
4620                                 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4621                                         _print_next_block((*par_num)++,
4622                                                           "TSEMI");
4623                                         _print_parity(bp,
4624                                                       TSEM_REG_TSEM_PRTY_STS_0);
4625                                         _print_parity(bp,
4626                                                       TSEM_REG_TSEM_PRTY_STS_1);
4627                                         break;
4628                                 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4629                                         _print_next_block((*par_num)++, "XPB");
4630                                         _print_parity(bp, GRCBASE_XPB +
4631                                                           PB_REG_PB_PRTY_STS);
4632                                         break;
4633                                 }
4634                         }
4635 
4636                         /* Clear the bit */
4637                         sig &= ~cur_bit;
4638                 }
4639         }
4640 
4641         return res;
4642 }
4643 
4644 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4645                                             int *par_num, bool *global,
4646                                             bool print)
4647 {
4648         u32 cur_bit;
4649         bool res;
4650         int i;
4651 
4652         res = false;
4653 
4654         for (i = 0; sig; i++) {
4655                 cur_bit = (0x1UL << i);
4656                 if (sig & cur_bit) {
4657                         res |= true; /* Each bit is real error! */
4658                         switch (cur_bit) {
4659                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4660                                 if (print) {
4661                                         _print_next_block((*par_num)++, "PBF");
4662                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4663                                 }
4664                                 break;
4665                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4666                                 if (print) {
4667                                         _print_next_block((*par_num)++, "QM");
4668                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4669                                 }
4670                                 break;
4671                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4672                                 if (print) {
4673                                         _print_next_block((*par_num)++, "TM");
4674                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4675                                 }
4676                                 break;
4677                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4678                                 if (print) {
4679                                         _print_next_block((*par_num)++, "XSDM");
4680                                         _print_parity(bp,
4681                                                       XSDM_REG_XSDM_PRTY_STS);
4682                                 }
4683                                 break;
4684                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4685                                 if (print) {
4686                                         _print_next_block((*par_num)++, "XCM");
4687                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4688                                 }
4689                                 break;
4690                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4691                                 if (print) {
4692                                         _print_next_block((*par_num)++,
4693                                                           "XSEMI");
4694                                         _print_parity(bp,
4695                                                       XSEM_REG_XSEM_PRTY_STS_0);
4696                                         _print_parity(bp,
4697                                                       XSEM_REG_XSEM_PRTY_STS_1);
4698                                 }
4699                                 break;
4700                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4701                                 if (print) {
4702                                         _print_next_block((*par_num)++,
4703                                                           "DOORBELLQ");
4704                                         _print_parity(bp,
4705                                                       DORQ_REG_DORQ_PRTY_STS);
4706                                 }
4707                                 break;
4708                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4709                                 if (print) {
4710                                         _print_next_block((*par_num)++, "NIG");
4711                                         if (CHIP_IS_E1x(bp)) {
4712                                                 _print_parity(bp,
4713                                                         NIG_REG_NIG_PRTY_STS);
4714                                         } else {
4715                                                 _print_parity(bp,
4716                                                         NIG_REG_NIG_PRTY_STS_0);
4717                                                 _print_parity(bp,
4718                                                         NIG_REG_NIG_PRTY_STS_1);
4719                                         }
4720                                 }
4721                                 break;
4722                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4723                                 if (print)
4724                                         _print_next_block((*par_num)++,
4725                                                           "VAUX PCI CORE");
4726                                 *global = true;
4727                                 break;
4728                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4729                                 if (print) {
4730                                         _print_next_block((*par_num)++,
4731                                                           "DEBUG");
4732                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4733                                 }
4734                                 break;
4735                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4736                                 if (print) {
4737                                         _print_next_block((*par_num)++, "USDM");
4738                                         _print_parity(bp,
4739                                                       USDM_REG_USDM_PRTY_STS);
4740                                 }
4741                                 break;
4742                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4743                                 if (print) {
4744                                         _print_next_block((*par_num)++, "UCM");
4745                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4746                                 }
4747                                 break;
4748                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4749                                 if (print) {
4750                                         _print_next_block((*par_num)++,
4751                                                           "USEMI");
4752                                         _print_parity(bp,
4753                                                       USEM_REG_USEM_PRTY_STS_0);
4754                                         _print_parity(bp,
4755                                                       USEM_REG_USEM_PRTY_STS_1);
4756                                 }
4757                                 break;
4758                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4759                                 if (print) {
4760                                         _print_next_block((*par_num)++, "UPB");
4761                                         _print_parity(bp, GRCBASE_UPB +
4762                                                           PB_REG_PB_PRTY_STS);
4763                                 }
4764                                 break;
4765                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4766                                 if (print) {
4767                                         _print_next_block((*par_num)++, "CSDM");
4768                                         _print_parity(bp,
4769                                                       CSDM_REG_CSDM_PRTY_STS);
4770                                 }
4771                                 break;
4772                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4773                                 if (print) {
4774                                         _print_next_block((*par_num)++, "CCM");
4775                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4776                                 }
4777                                 break;
4778                         }
4779 
4780                         /* Clear the bit */
4781                         sig &= ~cur_bit;
4782                 }
4783         }
4784 
4785         return res;
4786 }
4787 
4788 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4789                                             int *par_num, bool print)
4790 {
4791         u32 cur_bit;
4792         bool res;
4793         int i;
4794 
4795         res = false;
4796 
4797         for (i = 0; sig; i++) {
4798                 cur_bit = (0x1UL << i);
4799                 if (sig & cur_bit) {
4800                         res = true; /* Each bit is real error! */
4801                         if (print) {
4802                                 switch (cur_bit) {
4803                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4804                                         _print_next_block((*par_num)++,
4805                                                           "CSEMI");
4806                                         _print_parity(bp,
4807                                                       CSEM_REG_CSEM_PRTY_STS_0);
4808                                         _print_parity(bp,
4809                                                       CSEM_REG_CSEM_PRTY_STS_1);
4810                                         break;
4811                                 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4812                                         _print_next_block((*par_num)++, "PXP");
4813                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4814                                         _print_parity(bp,
4815                                                       PXP2_REG_PXP2_PRTY_STS_0);
4816                                         _print_parity(bp,
4817                                                       PXP2_REG_PXP2_PRTY_STS_1);
4818                                         break;
4819                                 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4820                                         _print_next_block((*par_num)++,
4821                                                           "PXPPCICLOCKCLIENT");
4822                                         break;
4823                                 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4824                                         _print_next_block((*par_num)++, "CFC");
4825                                         _print_parity(bp,
4826                                                       CFC_REG_CFC_PRTY_STS);
4827                                         break;
4828                                 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4829                                         _print_next_block((*par_num)++, "CDU");
4830                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4831                                         break;
4832                                 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4833                                         _print_next_block((*par_num)++, "DMAE");
4834                                         _print_parity(bp,
4835                                                       DMAE_REG_DMAE_PRTY_STS);
4836                                         break;
4837                                 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4838                                         _print_next_block((*par_num)++, "IGU");
4839                                         if (CHIP_IS_E1x(bp))
4840                                                 _print_parity(bp,
4841                                                         HC_REG_HC_PRTY_STS);
4842                                         else
4843                                                 _print_parity(bp,
4844                                                         IGU_REG_IGU_PRTY_STS);
4845                                         break;
4846                                 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4847                                         _print_next_block((*par_num)++, "MISC");
4848                                         _print_parity(bp,
4849                                                       MISC_REG_MISC_PRTY_STS);
4850                                         break;
4851                                 }
4852                         }
4853 
4854                         /* Clear the bit */
4855                         sig &= ~cur_bit;
4856                 }
4857         }
4858 
4859         return res;
4860 }
4861 
4862 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4863                                             int *par_num, bool *global,
4864                                             bool print)
4865 {
4866         bool res = false;
4867         u32 cur_bit;
4868         int i;
4869 
4870         for (i = 0; sig; i++) {
4871                 cur_bit = (0x1UL << i);
4872                 if (sig & cur_bit) {
4873                         switch (cur_bit) {
4874                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4875                                 if (print)
4876                                         _print_next_block((*par_num)++,
4877                                                           "MCP ROM");
4878                                 *global = true;
4879                                 res = true;
4880                                 break;
4881                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4882                                 if (print)
4883                                         _print_next_block((*par_num)++,
4884                                                           "MCP UMP RX");
4885                                 *global = true;
4886                                 res = true;
4887                                 break;
4888                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4889                                 if (print)
4890                                         _print_next_block((*par_num)++,
4891                                                           "MCP UMP TX");
4892                                 *global = true;
4893                                 res = true;
4894                                 break;
4895                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4896                                 (*par_num)++;
4897                                 /* clear latched SCPAD PATIRY from MCP */
4898                                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4899                                        1UL << 10);
4900                                 break;
4901                         }
4902 
4903                         /* Clear the bit */
4904                         sig &= ~cur_bit;
4905                 }
4906         }
4907 
4908         return res;
4909 }
4910 
4911 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4912                                             int *par_num, bool print)
4913 {
4914         u32 cur_bit;
4915         bool res;
4916         int i;
4917 
4918         res = false;
4919 
4920         for (i = 0; sig; i++) {
4921                 cur_bit = (0x1UL << i);
4922                 if (sig & cur_bit) {
4923                         res = true; /* Each bit is real error! */
4924                         if (print) {
4925                                 switch (cur_bit) {
4926                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4927                                         _print_next_block((*par_num)++,
4928                                                           "PGLUE_B");
4929                                         _print_parity(bp,
4930                                                       PGLUE_B_REG_PGLUE_B_PRTY_STS);
4931                                         break;
4932                                 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4933                                         _print_next_block((*par_num)++, "ATC");
4934                                         _print_parity(bp,
4935                                                       ATC_REG_ATC_PRTY_STS);
4936                                         break;
4937                                 }
4938                         }
4939                         /* Clear the bit */
4940                         sig &= ~cur_bit;
4941                 }
4942         }
4943 
4944         return res;
4945 }
4946 
4947 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4948                               u32 *sig)
4949 {
4950         bool res = false;
4951 
4952         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4953             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4954             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4955             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4956             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4957                 int par_num = 0;
4958 
4959                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4960                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4961                           sig[0] & HW_PRTY_ASSERT_SET_0,
4962                           sig[1] & HW_PRTY_ASSERT_SET_1,
4963                           sig[2] & HW_PRTY_ASSERT_SET_2,
4964                           sig[3] & HW_PRTY_ASSERT_SET_3,
4965                           sig[4] & HW_PRTY_ASSERT_SET_4);
4966                 if (print) {
4967                         if (((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4968                              (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4969                              (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4970                              (sig[4] & HW_PRTY_ASSERT_SET_4)) ||
4971                              (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) {
4972                                 netdev_err(bp->dev,
4973                                            "Parity errors detected in blocks: ");
4974                         } else {
4975                                 print = false;
4976                         }
4977                 }
4978                 res |= bnx2x_check_blocks_with_parity0(bp,
4979                         sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4980                 res |= bnx2x_check_blocks_with_parity1(bp,
4981                         sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4982                 res |= bnx2x_check_blocks_with_parity2(bp,
4983                         sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4984                 res |= bnx2x_check_blocks_with_parity3(bp,
4985                         sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4986                 res |= bnx2x_check_blocks_with_parity4(bp,
4987                         sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4988 
4989                 if (print)
4990                         pr_cont("\n");
4991         }
4992 
4993         return res;
4994 }
4995 
4996 /**
4997  * bnx2x_chk_parity_attn - checks for parity attentions.
4998  *
4999  * @bp:         driver handle
5000  * @global:     true if there was a global attention
5001  * @print:      show parity attention in syslog
5002  */
5003 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
5004 {
5005         struct attn_route attn = { {0} };
5006         int port = BP_PORT(bp);
5007 
5008         attn.sig[0] = REG_RD(bp,
5009                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5010                              port*4);
5011         attn.sig[1] = REG_RD(bp,
5012                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
5013                              port*4);
5014         attn.sig[2] = REG_RD(bp,
5015                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
5016                              port*4);
5017         attn.sig[3] = REG_RD(bp,
5018                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
5019                              port*4);
5020         /* Since MCP attentions can't be disabled inside the block, we need to
5021          * read AEU registers to see whether they're currently disabled
5022          */
5023         attn.sig[3] &= ((REG_RD(bp,
5024                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
5025                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
5026                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
5027                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
5028 
5029         if (!CHIP_IS_E1x(bp))
5030                 attn.sig[4] = REG_RD(bp,
5031                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
5032                                      port*4);
5033 
5034         return bnx2x_parity_attn(bp, global, print, attn.sig);
5035 }
5036 
5037 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
5038 {
5039         u32 val;
5040         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5041 
5042                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5043                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5044                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
5045                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5046                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
5047                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5048                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
5049                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5050                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
5051                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5052                 if (val &
5053                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
5054                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5055                 if (val &
5056                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
5057                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5058                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
5059                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5060                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
5061                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5062                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
5063                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5064         }
5065         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5066                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5067                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5068                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5069                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5070                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
5071                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5072                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
5073                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5074                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
5075                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5076                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5077                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5078                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
5079                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5080         }
5081 
5082         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5083                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5084                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5085                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5086                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5087         }
5088 }
5089 
5090 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5091 {
5092         struct attn_route attn, *group_mask;
5093         int port = BP_PORT(bp);
5094         int index;
5095         u32 reg_addr;
5096         u32 val;
5097         u32 aeu_mask;
5098         bool global = false;
5099 
5100         /* need to take HW lock because MCP or other port might also
5101            try to handle this event */
5102         bnx2x_acquire_alr(bp);
5103 
5104         if (bnx2x_chk_parity_attn(bp, &global, true)) {
5105 #ifndef BNX2X_STOP_ON_ERROR
5106                 bp->recovery_state = BNX2X_RECOVERY_INIT;
5107                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5108                 /* Disable HW interrupts */
5109                 bnx2x_int_disable(bp);
5110                 /* In case of parity errors don't handle attentions so that
5111                  * other function would "see" parity errors.
5112                  */
5113 #else
5114                 bnx2x_panic();
5115 #endif
5116                 bnx2x_release_alr(bp);
5117                 return;
5118         }
5119 
5120         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5121         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5122         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5123         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5124         if (!CHIP_IS_E1x(bp))
5125                 attn.sig[4] =
5126                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5127         else
5128                 attn.sig[4] = 0;
5129 
5130         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5131            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5132 
5133         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5134                 if (deasserted & (1 << index)) {
5135                         group_mask = &bp->attn_group[index];
5136 
5137                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5138                            index,
5139                            group_mask->sig[0], group_mask->sig[1],
5140                            group_mask->sig[2], group_mask->sig[3],
5141                            group_mask->sig[4]);
5142 
5143                         bnx2x_attn_int_deasserted4(bp,
5144                                         attn.sig[4] & group_mask->sig[4]);
5145                         bnx2x_attn_int_deasserted3(bp,
5146                                         attn.sig[3] & group_mask->sig[3]);
5147                         bnx2x_attn_int_deasserted1(bp,
5148                                         attn.sig[1] & group_mask->sig[1]);
5149                         bnx2x_attn_int_deasserted2(bp,
5150                                         attn.sig[2] & group_mask->sig[2]);
5151                         bnx2x_attn_int_deasserted0(bp,
5152                                         attn.sig[0] & group_mask->sig[0]);
5153                 }
5154         }
5155 
5156         bnx2x_release_alr(bp);
5157 
5158         if (bp->common.int_block == INT_BLOCK_HC)
5159                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5160                             COMMAND_REG_ATTN_BITS_CLR);
5161         else
5162                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5163 
5164         val = ~deasserted;
5165         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5166            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5167         REG_WR(bp, reg_addr, val);
5168 
5169         if (~bp->attn_state & deasserted)
5170                 BNX2X_ERR("IGU ERROR\n");
5171 
5172         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5173                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
5174 
5175         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5176         aeu_mask = REG_RD(bp, reg_addr);
5177 
5178         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
5179            aeu_mask, deasserted);
5180         aeu_mask |= (deasserted & 0x3ff);
5181         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5182 
5183         REG_WR(bp, reg_addr, aeu_mask);
5184         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5185 
5186         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5187         bp->attn_state &= ~deasserted;
5188         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5189 }
5190 
5191 static void bnx2x_attn_int(struct bnx2x *bp)
5192 {
5193         /* read local copy of bits */
5194         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5195                                                                 attn_bits);
5196         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5197                                                                 attn_bits_ack);
5198         u32 attn_state = bp->attn_state;
5199 
5200         /* look for changed bits */
5201         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
5202         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
5203 
5204         DP(NETIF_MSG_HW,
5205            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
5206            attn_bits, attn_ack, asserted, deasserted);
5207 
5208         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5209                 BNX2X_ERR("BAD attention state\n");
5210 
5211         /* handle bits that were raised */
5212         if (asserted)
5213                 bnx2x_attn_int_asserted(bp, asserted);
5214 
5215         if (deasserted)
5216                 bnx2x_attn_int_deasserted(bp, deasserted);
5217 }
5218 
5219 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5220                       u16 index, u8 op, u8 update)
5221 {
5222         u32 igu_addr = bp->igu_base_addr;
5223         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5224         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5225                              igu_addr);
5226 }
5227 
5228 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5229 {
5230         /* No memory barriers */
5231         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5232         mmiowb(); /* keep prod updates ordered */
5233 }
5234 
5235 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5236                                       union event_ring_elem *elem)
5237 {
5238         u8 err = elem->message.error;
5239 
5240         if (!bp->cnic_eth_dev.starting_cid  ||
5241             (cid < bp->cnic_eth_dev.starting_cid &&
5242             cid != bp->cnic_eth_dev.iscsi_l2_cid))
5243                 return 1;
5244 
5245         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5246 
5247         if (unlikely(err)) {
5248 
5249                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5250                           cid);
5251                 bnx2x_panic_dump(bp, false);
5252         }
5253         bnx2x_cnic_cfc_comp(bp, cid, err);
5254         return 0;
5255 }
5256 
5257 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5258 {
5259         struct bnx2x_mcast_ramrod_params rparam;
5260         int rc;
5261 
5262         memset(&rparam, 0, sizeof(rparam));
5263 
5264         rparam.mcast_obj = &bp->mcast_obj;
5265 
5266         netif_addr_lock_bh(bp->dev);
5267 
5268         /* Clear pending state for the last command */
5269         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5270 
5271         /* If there are pending mcast commands - send them */
5272         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5273                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5274                 if (rc < 0)
5275                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5276                                   rc);
5277         }
5278 
5279         netif_addr_unlock_bh(bp->dev);
5280 }
5281 
5282 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5283                                             union event_ring_elem *elem)
5284 {
5285         unsigned long ramrod_flags = 0;
5286         int rc = 0;
5287         u32 echo = le32_to_cpu(elem->message.data.eth_event.echo);
5288         u32 cid = echo & BNX2X_SWCID_MASK;
5289         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5290 
5291         /* Always push next commands out, don't wait here */
5292         __set_bit(RAMROD_CONT, &ramrod_flags);
5293 
5294         switch (echo >> BNX2X_SWCID_SHIFT) {
5295         case BNX2X_FILTER_MAC_PENDING:
5296                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5297                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5298                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5299                 else
5300                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5301 
5302                 break;
5303         case BNX2X_FILTER_VLAN_PENDING:
5304                 DP(BNX2X_MSG_SP, "Got SETUP_VLAN completions\n");
5305                 vlan_mac_obj = &bp->sp_objs[cid].vlan_obj;
5306                 break;
5307         case BNX2X_FILTER_MCAST_PENDING:
5308                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5309                 /* This is only relevant for 57710 where multicast MACs are
5310                  * configured as unicast MACs using the same ramrod.
5311                  */
5312                 bnx2x_handle_mcast_eqe(bp);
5313                 return;
5314         default:
5315                 BNX2X_ERR("Unsupported classification command: 0x%x\n", echo);
5316                 return;
5317         }
5318 
5319         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5320 
5321         if (rc < 0)
5322                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5323         else if (rc > 0)
5324                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5325 }
5326 
5327 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5328 
5329 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5330 {
5331         netif_addr_lock_bh(bp->dev);
5332 
5333         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5334 
5335         /* Send rx_mode command again if was requested */
5336         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5337                 bnx2x_set_storm_rx_mode(bp);
5338         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5339                                     &bp->sp_state))
5340                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5341         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5342                                     &bp->sp_state))
5343                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5344 
5345         netif_addr_unlock_bh(bp->dev);
5346 }
5347 
5348 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5349                                               union event_ring_elem *elem)
5350 {
5351         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5352                 DP(BNX2X_MSG_SP,
5353                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5354                    elem->message.data.vif_list_event.func_bit_map);
5355                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5356                         elem->message.data.vif_list_event.func_bit_map);
5357         } else if (elem->message.data.vif_list_event.echo ==
5358                    VIF_LIST_RULE_SET) {
5359                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5360                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5361         }
5362 }
5363 
5364 /* called with rtnl_lock */
5365 static void bnx2x_after_function_update(struct bnx2x *bp)
5366 {
5367         int q, rc;
5368         struct bnx2x_fastpath *fp;
5369         struct bnx2x_queue_state_params queue_params = {NULL};
5370         struct bnx2x_queue_update_params *q_update_params =
5371                 &queue_params.params.update;
5372 
5373         /* Send Q update command with afex vlan removal values for all Qs */
5374         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5375 
5376         /* set silent vlan removal values according to vlan mode */
5377         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5378                   &q_update_params->update_flags);
5379         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5380                   &q_update_params->update_flags);
5381         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5382 
5383         /* in access mode mark mask and value are 0 to strip all vlans */
5384         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5385                 q_update_params->silent_removal_value = 0;
5386                 q_update_params->silent_removal_mask = 0;
5387         } else {
5388                 q_update_params->silent_removal_value =
5389                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5390                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5391         }
5392 
5393         for_each_eth_queue(bp, q) {
5394                 /* Set the appropriate Queue object */
5395                 fp = &bp->fp[q];
5396                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5397 
5398                 /* send the ramrod */
5399                 rc = bnx2x_queue_state_change(bp, &queue_params);
5400                 if (rc < 0)
5401                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5402                                   q);
5403         }
5404 
5405         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5406                 fp = &bp->fp[FCOE_IDX(bp)];
5407                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5408 
5409                 /* clear pending completion bit */
5410                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5411 
5412                 /* mark latest Q bit */
5413                 smp_mb__before_atomic();
5414                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5415                 smp_mb__after_atomic();
5416 
5417                 /* send Q update ramrod for FCoE Q */
5418                 rc = bnx2x_queue_state_change(bp, &queue_params);
5419                 if (rc < 0)
5420                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5421                                   q);
5422         } else {
5423                 /* If no FCoE ring - ACK MCP now */
5424                 bnx2x_link_report(bp);
5425                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5426         }
5427 }
5428 
5429 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5430         struct bnx2x *bp, u32 cid)
5431 {
5432         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5433 
5434         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5435                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5436         else
5437                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5438 }
5439 
5440 static void bnx2x_eq_int(struct bnx2x *bp)
5441 {
5442         u16 hw_cons, sw_cons, sw_prod;
5443         union event_ring_elem *elem;
5444         u8 echo;
5445         u32 cid;
5446         u8 opcode;
5447         int rc, spqe_cnt = 0;
5448         struct bnx2x_queue_sp_obj *q_obj;
5449         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5450         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5451 
5452         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5453 
5454         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5455          * when we get the next-page we need to adjust so the loop
5456          * condition below will be met. The next element is the size of a
5457          * regular element and hence incrementing by 1
5458          */
5459         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5460                 hw_cons++;
5461 
5462         /* This function may never run in parallel with itself for a
5463          * specific bp, thus there is no need in "paired" read memory
5464          * barrier here.
5465          */
5466         sw_cons = bp->eq_cons;
5467         sw_prod = bp->eq_prod;
5468 
5469         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5470                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5471 
5472         for (; sw_cons != hw_cons;
5473               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5474 
5475                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5476 
5477                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5478                 if (!rc) {
5479                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5480                            rc);
5481                         goto next_spqe;
5482                 }
5483 
5484                 opcode = elem->message.opcode;
5485 
5486                 /* handle eq element */
5487                 switch (opcode) {
5488                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5489                         bnx2x_vf_mbx_schedule(bp,
5490                                               &elem->message.data.vf_pf_event);
5491                         continue;
5492 
5493                 case EVENT_RING_OPCODE_STAT_QUERY:
5494                         DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5495                                "got statistics comp event %d\n",
5496                                bp->stats_comp++);
5497                         /* nothing to do with stats comp */
5498                         goto next_spqe;
5499 
5500                 case EVENT_RING_OPCODE_CFC_DEL:
5501                         /* handle according to cid range */
5502                         /*
5503                          * we may want to verify here that the bp state is
5504                          * HALTING
5505                          */
5506 
5507                         /* elem CID originates from FW; actually LE */
5508                         cid = SW_CID(elem->message.data.cfc_del_event.cid);
5509 
5510                         DP(BNX2X_MSG_SP,
5511                            "got delete ramrod for MULTI[%d]\n", cid);
5512 
5513                         if (CNIC_LOADED(bp) &&
5514                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5515                                 goto next_spqe;
5516 
5517                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5518 
5519                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5520                                 break;
5521 
5522                         goto next_spqe;
5523 
5524                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5525                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5526                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5527                         if (f_obj->complete_cmd(bp, f_obj,
5528                                                 BNX2X_F_CMD_TX_STOP))
5529                                 break;
5530                         goto next_spqe;
5531 
5532                 case EVENT_RING_OPCODE_START_TRAFFIC:
5533                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5534                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5535                         if (f_obj->complete_cmd(bp, f_obj,
5536                                                 BNX2X_F_CMD_TX_START))
5537                                 break;
5538                         goto next_spqe;
5539 
5540                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5541                         echo = elem->message.data.function_update_event.echo;
5542                         if (echo == SWITCH_UPDATE) {
5543                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5544                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5545                                 if (f_obj->complete_cmd(
5546                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5547                                         break;
5548 
5549                         } else {
5550                                 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5551 
5552                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5553                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5554                                 f_obj->complete_cmd(bp, f_obj,
5555                                                     BNX2X_F_CMD_AFEX_UPDATE);
5556 
5557                                 /* We will perform the Queues update from
5558                                  * sp_rtnl task as all Queue SP operations
5559                                  * should run under rtnl_lock.
5560                                  */
5561                                 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5562                         }
5563 
5564                         goto next_spqe;
5565 
5566                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5567                         f_obj->complete_cmd(bp, f_obj,
5568                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5569                         bnx2x_after_afex_vif_lists(bp, elem);
5570                         goto next_spqe;
5571                 case EVENT_RING_OPCODE_FUNCTION_START:
5572                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5573                            "got FUNC_START ramrod\n");
5574                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5575                                 break;
5576 
5577                         goto next_spqe;
5578 
5579                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5580                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5581                            "got FUNC_STOP ramrod\n");
5582                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5583                                 break;
5584 
5585                         goto next_spqe;
5586 
5587                 case EVENT_RING_OPCODE_SET_TIMESYNC:
5588                         DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5589                            "got set_timesync ramrod completion\n");
5590                         if (f_obj->complete_cmd(bp, f_obj,
5591                                                 BNX2X_F_CMD_SET_TIMESYNC))
5592                                 break;
5593                         goto next_spqe;
5594                 }
5595 
5596                 switch (opcode | bp->state) {
5597                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5598                       BNX2X_STATE_OPEN):
5599                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5600                       BNX2X_STATE_OPENING_WAIT4_PORT):
5601                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5602                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5603                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5604                            SW_CID(elem->message.data.eth_event.echo));
5605                         rss_raw->clear_pending(rss_raw);
5606                         break;
5607 
5608                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5609                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5610                 case (EVENT_RING_OPCODE_SET_MAC |
5611                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5612                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5613                       BNX2X_STATE_OPEN):
5614                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5615                       BNX2X_STATE_DIAG):
5616                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5617                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5618                         DP(BNX2X_MSG_SP, "got (un)set vlan/mac ramrod\n");
5619                         bnx2x_handle_classification_eqe(bp, elem);
5620                         break;
5621 
5622                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5623                       BNX2X_STATE_OPEN):
5624                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5625                       BNX2X_STATE_DIAG):
5626                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5627                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5628                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5629                         bnx2x_handle_mcast_eqe(bp);
5630                         break;
5631 
5632                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5633                       BNX2X_STATE_OPEN):
5634                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5635                       BNX2X_STATE_DIAG):
5636                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5637                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5638                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5639                         bnx2x_handle_rx_mode_eqe(bp);
5640                         break;
5641                 default:
5642                         /* unknown event log error and continue */
5643                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5644                                   elem->message.opcode, bp->state);
5645                 }
5646 next_spqe:
5647                 spqe_cnt++;
5648         } /* for */
5649 
5650         smp_mb__before_atomic();
5651         atomic_add(spqe_cnt, &bp->eq_spq_left);
5652 
5653         bp->eq_cons = sw_cons;
5654         bp->eq_prod = sw_prod;
5655         /* Make sure that above mem writes were issued towards the memory */
5656         smp_wmb();
5657 
5658         /* update producer */
5659         bnx2x_update_eq_prod(bp, bp->eq_prod);
5660 }
5661 
5662 static void bnx2x_sp_task(struct work_struct *work)
5663 {
5664         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5665 
5666         DP(BNX2X_MSG_SP, "sp task invoked\n");
5667 
5668         /* make sure the atomic interrupt_occurred has been written */
5669         smp_rmb();
5670         if (atomic_read(&bp->interrupt_occurred)) {
5671 
5672                 /* what work needs to be performed? */
5673                 u16 status = bnx2x_update_dsb_idx(bp);
5674 
5675                 DP(BNX2X_MSG_SP, "status %x\n", status);
5676                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5677                 atomic_set(&bp->interrupt_occurred, 0);
5678 
5679                 /* HW attentions */
5680                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5681                         bnx2x_attn_int(bp);
5682                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5683                 }
5684 
5685                 /* SP events: STAT_QUERY and others */
5686                 if (status & BNX2X_DEF_SB_IDX) {
5687                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5688 
5689                         if (FCOE_INIT(bp) &&
5690                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5691                                 /* Prevent local bottom-halves from running as
5692                                  * we are going to change the local NAPI list.
5693                                  */
5694                                 local_bh_disable();
5695                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5696                                 local_bh_enable();
5697                         }
5698 
5699                         /* Handle EQ completions */
5700                         bnx2x_eq_int(bp);
5701                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5702                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5703 
5704                         status &= ~BNX2X_DEF_SB_IDX;
5705                 }
5706 
5707                 /* if status is non zero then perhaps something went wrong */
5708                 if (unlikely(status))
5709                         DP(BNX2X_MSG_SP,
5710                            "got an unknown interrupt! (status 0x%x)\n", status);
5711 
5712                 /* ack status block only if something was actually handled */
5713                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5714                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5715         }
5716 
5717         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5718         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5719                                &bp->sp_state)) {
5720                 bnx2x_link_report(bp);
5721                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5722         }
5723 }
5724 
5725 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5726 {
5727         struct net_device *dev = dev_instance;
5728         struct bnx2x *bp = netdev_priv(dev);
5729 
5730         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5731                      IGU_INT_DISABLE, 0);
5732 
5733 #ifdef BNX2X_STOP_ON_ERROR
5734         if (unlikely(bp->panic))
5735                 return IRQ_HANDLED;
5736 #endif
5737 
5738         if (CNIC_LOADED(bp)) {
5739                 struct cnic_ops *c_ops;
5740 
5741                 rcu_read_lock();
5742                 c_ops = rcu_dereference(bp->cnic_ops);
5743                 if (c_ops)
5744                         c_ops->cnic_handler(bp->cnic_data, NULL);
5745                 rcu_read_unlock();
5746         }
5747 
5748         /* schedule sp task to perform default status block work, ack
5749          * attentions and enable interrupts.
5750          */
5751         bnx2x_schedule_sp_task(bp);
5752 
5753         return IRQ_HANDLED;
5754 }
5755 
5756 /* end of slow path */
5757 
5758 void bnx2x_drv_pulse(struct bnx2x *bp)
5759 {
5760         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5761                  bp->fw_drv_pulse_wr_seq);
5762 }
5763 
5764 static void bnx2x_timer(unsigned long data)
5765 {
5766         struct bnx2x *bp = (struct bnx2x *) data;
5767 
5768         if (!netif_running(bp->dev))
5769                 return;
5770 
5771         if (IS_PF(bp) &&
5772             !BP_NOMCP(bp)) {
5773                 int mb_idx = BP_FW_MB_IDX(bp);
5774                 u16 drv_pulse;
5775                 u16 mcp_pulse;
5776 
5777                 ++bp->fw_drv_pulse_wr_seq;
5778                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5779                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5780                 bnx2x_drv_pulse(bp);
5781 
5782                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5783                              MCP_PULSE_SEQ_MASK);
5784                 /* The delta between driver pulse and mcp response
5785                  * should not get too big. If the MFW is more than 5 pulses
5786                  * behind, we should worry about it enough to generate an error
5787                  * log.
5788                  */
5789                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5790                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5791                                   drv_pulse, mcp_pulse);
5792         }
5793 
5794         if (bp->state == BNX2X_STATE_OPEN)
5795                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5796 
5797         /* sample pf vf bulletin board for new posts from pf */
5798         if (IS_VF(bp))
5799                 bnx2x_timer_sriov(bp);
5800 
5801         mod_timer(&bp->timer, jiffies + bp->current_interval);
5802 }
5803 
5804 /* end of Statistics */
5805 
5806 /* nic init */
5807 
5808 /*
5809  * nic init service functions
5810  */
5811 
5812 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5813 {
5814         u32 i;
5815         if (!(len%4) && !(addr%4))
5816                 for (i = 0; i < len; i += 4)
5817                         REG_WR(bp, addr + i, fill);
5818         else
5819                 for (i = 0; i < len; i++)
5820                         REG_WR8(bp, addr + i, fill);
5821 }
5822 
5823 /* helper: writes FP SP data to FW - data_size in dwords */
5824 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5825                                 int fw_sb_id,
5826                                 u32 *sb_data_p,
5827                                 u32 data_size)
5828 {
5829         int index;
5830         for (index = 0; index < data_size; index++)
5831                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5832                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5833                         sizeof(u32)*index,
5834                         *(sb_data_p + index));
5835 }
5836 
5837 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5838 {
5839         u32 *sb_data_p;
5840         u32 data_size = 0;
5841         struct hc_status_block_data_e2 sb_data_e2;
5842         struct hc_status_block_data_e1x sb_data_e1x;
5843 
5844         /* disable the function first */
5845         if (!CHIP_IS_E1x(bp)) {
5846                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5847                 sb_data_e2.common.state = SB_DISABLED;
5848                 sb_data_e2.common.p_func.vf_valid = false;
5849                 sb_data_p = (u32 *)&sb_data_e2;
5850                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5851         } else {
5852                 memset(&sb_data_e1x, 0,
5853                        sizeof(struct hc_status_block_data_e1x));
5854                 sb_data_e1x.common.state = SB_DISABLED;
5855                 sb_data_e1x.common.p_func.vf_valid = false;
5856                 sb_data_p = (u32 *)&sb_data_e1x;
5857                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5858         }
5859         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5860 
5861         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5862                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5863                         CSTORM_STATUS_BLOCK_SIZE);
5864         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5865                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5866                         CSTORM_SYNC_BLOCK_SIZE);
5867 }
5868 
5869 /* helper:  writes SP SB data to FW */
5870 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5871                 struct hc_sp_status_block_data *sp_sb_data)
5872 {
5873         int func = BP_FUNC(bp);
5874         int i;
5875         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5876                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5877                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5878                         i*sizeof(u32),
5879                         *((u32 *)sp_sb_data + i));
5880 }
5881 
5882 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5883 {
5884         int func = BP_FUNC(bp);
5885         struct hc_sp_status_block_data sp_sb_data;
5886         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5887 
5888         sp_sb_data.state = SB_DISABLED;
5889         sp_sb_data.p_func.vf_valid = false;
5890 
5891         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5892 
5893         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5894                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5895                         CSTORM_SP_STATUS_BLOCK_SIZE);
5896         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5897                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5898                         CSTORM_SP_SYNC_BLOCK_SIZE);
5899 }
5900 
5901 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5902                                            int igu_sb_id, int igu_seg_id)
5903 {
5904         hc_sm->igu_sb_id = igu_sb_id;
5905         hc_sm->igu_seg_id = igu_seg_id;
5906         hc_sm->timer_value = 0xFF;
5907         hc_sm->time_to_expire = 0xFFFFFFFF;
5908 }
5909 
5910 /* allocates state machine ids. */
5911 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5912 {
5913         /* zero out state machine indices */
5914         /* rx indices */
5915         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5916 
5917         /* tx indices */
5918         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5919         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5920         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5921         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5922 
5923         /* map indices */
5924         /* rx indices */
5925         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5926                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5927 
5928         /* tx indices */
5929         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5930                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5931         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5932                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5933         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5934                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5935         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5936                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5937 }
5938 
5939 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5940                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5941 {
5942         int igu_seg_id;
5943 
5944         struct hc_status_block_data_e2 sb_data_e2;
5945         struct hc_status_block_data_e1x sb_data_e1x;
5946         struct hc_status_block_sm  *hc_sm_p;
5947         int data_size;
5948         u32 *sb_data_p;
5949 
5950         if (CHIP_INT_MODE_IS_BC(bp))
5951                 igu_seg_id = HC_SEG_ACCESS_NORM;
5952         else
5953                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5954 
5955         bnx2x_zero_fp_sb(bp, fw_sb_id);
5956 
5957         if (!CHIP_IS_E1x(bp)) {
5958                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5959                 sb_data_e2.common.state = SB_ENABLED;
5960                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5961                 sb_data_e2.common.p_func.vf_id = vfid;
5962                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5963                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5964                 sb_data_e2.common.same_igu_sb_1b = true;
5965                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5966                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5967                 hc_sm_p = sb_data_e2.common.state_machine;
5968                 sb_data_p = (u32 *)&sb_data_e2;
5969                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5970                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5971         } else {
5972                 memset(&sb_data_e1x, 0,
5973                        sizeof(struct hc_status_block_data_e1x));
5974                 sb_data_e1x.common.state = SB_ENABLED;
5975                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5976                 sb_data_e1x.common.p_func.vf_id = 0xff;
5977                 sb_data_e1x.common.p_func.vf_valid = false;
5978                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5979                 sb_data_e1x.common.same_igu_sb_1b = true;
5980                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5981                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5982                 hc_sm_p = sb_data_e1x.common.state_machine;
5983                 sb_data_p = (u32 *)&sb_data_e1x;
5984                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5985                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5986         }
5987 
5988         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5989                                        igu_sb_id, igu_seg_id);
5990         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5991                                        igu_sb_id, igu_seg_id);
5992 
5993         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5994 
5995         /* write indices to HW - PCI guarantees endianity of regpairs */
5996         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5997 }
5998 
5999 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
6000                                      u16 tx_usec, u16 rx_usec)
6001 {
6002         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
6003                                     false, rx_usec);
6004         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6005                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
6006                                        tx_usec);
6007         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6008                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
6009                                        tx_usec);
6010         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6011                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
6012                                        tx_usec);
6013 }
6014 
6015 static void bnx2x_init_def_sb(struct bnx2x *bp)
6016 {
6017         struct host_sp_status_block *def_sb = bp->def_status_blk;
6018         dma_addr_t mapping = bp->def_status_blk_mapping;
6019         int igu_sp_sb_index;
6020         int igu_seg_id;
6021         int port = BP_PORT(bp);
6022         int func = BP_FUNC(bp);
6023         int reg_offset, reg_offset_en5;
6024         u64 section;
6025         int index;
6026         struct hc_sp_status_block_data sp_sb_data;
6027         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
6028 
6029         if (CHIP_INT_MODE_IS_BC(bp)) {
6030                 igu_sp_sb_index = DEF_SB_IGU_ID;
6031                 igu_seg_id = HC_SEG_ACCESS_DEF;
6032         } else {
6033                 igu_sp_sb_index = bp->igu_dsb_id;
6034                 igu_seg_id = IGU_SEG_ACCESS_DEF;
6035         }
6036 
6037         /* ATTN */
6038         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6039                                             atten_status_block);
6040         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
6041 
6042         bp->attn_state = 0;
6043 
6044         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6045                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6046         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6047                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
6048         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
6049                 int sindex;
6050                 /* take care of sig[0]..sig[4] */
6051                 for (sindex = 0; sindex < 4; sindex++)
6052                         bp->attn_group[index].sig[sindex] =
6053                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
6054 
6055                 if (!CHIP_IS_E1x(bp))
6056                         /*
6057                          * enable5 is separate from the rest of the registers,
6058                          * and therefore the address skip is 4
6059                          * and not 16 between the different groups
6060                          */
6061                         bp->attn_group[index].sig[4] = REG_RD(bp,
6062                                         reg_offset_en5 + 0x4*index);
6063                 else
6064                         bp->attn_group[index].sig[4] = 0;
6065         }
6066 
6067         if (bp->common.int_block == INT_BLOCK_HC) {
6068                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6069                                      HC_REG_ATTN_MSG0_ADDR_L);
6070 
6071                 REG_WR(bp, reg_offset, U64_LO(section));
6072                 REG_WR(bp, reg_offset + 4, U64_HI(section));
6073         } else if (!CHIP_IS_E1x(bp)) {
6074                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6075                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6076         }
6077 
6078         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6079                                             sp_sb);
6080 
6081         bnx2x_zero_sp_sb(bp);
6082 
6083         /* PCI guarantees endianity of regpairs */
6084         sp_sb_data.state                = SB_ENABLED;
6085         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
6086         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
6087         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
6088         sp_sb_data.igu_seg_id           = igu_seg_id;
6089         sp_sb_data.p_func.pf_id         = func;
6090         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
6091         sp_sb_data.p_func.vf_id         = 0xff;
6092 
6093         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
6094 
6095         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6096 }
6097 
6098 void bnx2x_update_coalesce(struct bnx2x *bp)
6099 {
6100         int i;
6101 
6102         for_each_eth_queue(bp, i)
6103                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
6104                                          bp->tx_ticks, bp->rx_ticks);
6105 }
6106 
6107 static void bnx2x_init_sp_ring(struct bnx2x *bp)
6108 {
6109         spin_lock_init(&bp->spq_lock);
6110         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
6111 
6112         bp->spq_prod_idx = 0;
6113         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6114         bp->spq_prod_bd = bp->spq;
6115         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
6116 }
6117 
6118 static void bnx2x_init_eq_ring(struct bnx2x *bp)
6119 {
6120         int i;
6121         for (i = 1; i <= NUM_EQ_PAGES; i++) {
6122                 union event_ring_elem *elem =
6123                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6124 
6125                 elem->next_page.addr.hi =
6126                         cpu_to_le32(U64_HI(bp->eq_mapping +