Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4

Linux/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

  1 /* bnx2x_main.c: QLogic Everest network driver.
  2  *
  3  * Copyright (c) 2007-2013 Broadcom Corporation
  4  * Copyright (c) 2014 QLogic Corporation
  5  * All rights reserved
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License as published by
  9  * the Free Software Foundation.
 10  *
 11  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
 12  * Written by: Eliezer Tamir
 13  * Based on code from Michael Chan's bnx2 driver
 14  * UDP CSUM errata workaround by Arik Gendelman
 15  * Slowpath and fastpath rework by Vladislav Zolotarov
 16  * Statistics and Link management by Yitchak Gertner
 17  *
 18  */
 19 
 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 21 
 22 #include <linux/module.h>
 23 #include <linux/moduleparam.h>
 24 #include <linux/kernel.h>
 25 #include <linux/device.h>  /* for dev_info() */
 26 #include <linux/timer.h>
 27 #include <linux/errno.h>
 28 #include <linux/ioport.h>
 29 #include <linux/slab.h>
 30 #include <linux/interrupt.h>
 31 #include <linux/pci.h>
 32 #include <linux/aer.h>
 33 #include <linux/init.h>
 34 #include <linux/netdevice.h>
 35 #include <linux/etherdevice.h>
 36 #include <linux/skbuff.h>
 37 #include <linux/dma-mapping.h>
 38 #include <linux/bitops.h>
 39 #include <linux/irq.h>
 40 #include <linux/delay.h>
 41 #include <asm/byteorder.h>
 42 #include <linux/time.h>
 43 #include <linux/ethtool.h>
 44 #include <linux/mii.h>
 45 #include <linux/if_vlan.h>
 46 #include <linux/crash_dump.h>
 47 #include <net/ip.h>
 48 #include <net/ipv6.h>
 49 #include <net/tcp.h>
 50 #include <net/vxlan.h>
 51 #include <net/checksum.h>
 52 #include <net/ip6_checksum.h>
 53 #include <linux/workqueue.h>
 54 #include <linux/crc32.h>
 55 #include <linux/crc32c.h>
 56 #include <linux/prefetch.h>
 57 #include <linux/zlib.h>
 58 #include <linux/io.h>
 59 #include <linux/semaphore.h>
 60 #include <linux/stringify.h>
 61 #include <linux/vmalloc.h>
 62 
 63 #include "bnx2x.h"
 64 #include "bnx2x_init.h"
 65 #include "bnx2x_init_ops.h"
 66 #include "bnx2x_cmn.h"
 67 #include "bnx2x_vfpf.h"
 68 #include "bnx2x_dcb.h"
 69 #include "bnx2x_sp.h"
 70 #include <linux/firmware.h>
 71 #include "bnx2x_fw_file_hdr.h"
 72 /* FW files */
 73 #define FW_FILE_VERSION                                 \
 74         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
 75         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
 76         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
 77         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
 78 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
 79 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
 80 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
 81 
 82 /* Time in jiffies before concluding the transmitter is hung */
 83 #define TX_TIMEOUT              (5*HZ)
 84 
 85 static char version[] =
 86         "QLogic 5771x/578xx 10/20-Gigabit Ethernet Driver "
 87         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 88 
 89 MODULE_AUTHOR("Eliezer Tamir");
 90 MODULE_DESCRIPTION("QLogic "
 91                    "BCM57710/57711/57711E/"
 92                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
 93                    "57840/57840_MF Driver");
 94 MODULE_LICENSE("GPL");
 95 MODULE_VERSION(DRV_MODULE_VERSION);
 96 MODULE_FIRMWARE(FW_FILE_NAME_E1);
 97 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
 98 MODULE_FIRMWARE(FW_FILE_NAME_E2);
 99 
100 int bnx2x_num_queues;
101 module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
102 MODULE_PARM_DESC(num_queues,
103                  " Set number of queues (default is as a number of CPUs)");
104 
105 static int disable_tpa;
106 module_param(disable_tpa, int, S_IRUGO);
107 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
108 
109 static int int_mode;
110 module_param(int_mode, int, S_IRUGO);
111 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
112                                 "(1 INT#x; 2 MSI)");
113 
114 static int dropless_fc;
115 module_param(dropless_fc, int, S_IRUGO);
116 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
117 
118 static int mrrs = -1;
119 module_param(mrrs, int, S_IRUGO);
120 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
121 
122 static int debug;
123 module_param(debug, int, S_IRUGO);
124 MODULE_PARM_DESC(debug, " Default debug msglevel");
125 
126 static struct workqueue_struct *bnx2x_wq;
127 struct workqueue_struct *bnx2x_iov_wq;
128 
129 struct bnx2x_mac_vals {
130         u32 xmac_addr;
131         u32 xmac_val;
132         u32 emac_addr;
133         u32 emac_val;
134         u32 umac_addr[2];
135         u32 umac_val[2];
136         u32 bmac_addr;
137         u32 bmac_val[2];
138 };
139 
140 enum bnx2x_board_type {
141         BCM57710 = 0,
142         BCM57711,
143         BCM57711E,
144         BCM57712,
145         BCM57712_MF,
146         BCM57712_VF,
147         BCM57800,
148         BCM57800_MF,
149         BCM57800_VF,
150         BCM57810,
151         BCM57810_MF,
152         BCM57810_VF,
153         BCM57840_4_10,
154         BCM57840_2_20,
155         BCM57840_MF,
156         BCM57840_VF,
157         BCM57811,
158         BCM57811_MF,
159         BCM57840_O,
160         BCM57840_MFO,
161         BCM57811_VF
162 };
163 
164 /* indexed by board_type, above */
165 static struct {
166         char *name;
167 } board_info[] = {
168         [BCM57710]      = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" },
169         [BCM57711]      = { "QLogic BCM57711 10 Gigabit PCIe" },
170         [BCM57711E]     = { "QLogic BCM57711E 10 Gigabit PCIe" },
171         [BCM57712]      = { "QLogic BCM57712 10 Gigabit Ethernet" },
172         [BCM57712_MF]   = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" },
173         [BCM57712_VF]   = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" },
174         [BCM57800]      = { "QLogic BCM57800 10 Gigabit Ethernet" },
175         [BCM57800_MF]   = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" },
176         [BCM57800_VF]   = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" },
177         [BCM57810]      = { "QLogic BCM57810 10 Gigabit Ethernet" },
178         [BCM57810_MF]   = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" },
179         [BCM57810_VF]   = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" },
180         [BCM57840_4_10] = { "QLogic BCM57840 10 Gigabit Ethernet" },
181         [BCM57840_2_20] = { "QLogic BCM57840 20 Gigabit Ethernet" },
182         [BCM57840_MF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
183         [BCM57840_VF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" },
184         [BCM57811]      = { "QLogic BCM57811 10 Gigabit Ethernet" },
185         [BCM57811_MF]   = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" },
186         [BCM57840_O]    = { "QLogic BCM57840 10/20 Gigabit Ethernet" },
187         [BCM57840_MFO]  = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
188         [BCM57811_VF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }
189 };
190 
191 #ifndef PCI_DEVICE_ID_NX2_57710
192 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
193 #endif
194 #ifndef PCI_DEVICE_ID_NX2_57711
195 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
196 #endif
197 #ifndef PCI_DEVICE_ID_NX2_57711E
198 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
199 #endif
200 #ifndef PCI_DEVICE_ID_NX2_57712
201 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
202 #endif
203 #ifndef PCI_DEVICE_ID_NX2_57712_MF
204 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
205 #endif
206 #ifndef PCI_DEVICE_ID_NX2_57712_VF
207 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
208 #endif
209 #ifndef PCI_DEVICE_ID_NX2_57800
210 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
211 #endif
212 #ifndef PCI_DEVICE_ID_NX2_57800_MF
213 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
214 #endif
215 #ifndef PCI_DEVICE_ID_NX2_57800_VF
216 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
217 #endif
218 #ifndef PCI_DEVICE_ID_NX2_57810
219 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
220 #endif
221 #ifndef PCI_DEVICE_ID_NX2_57810_MF
222 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
223 #endif
224 #ifndef PCI_DEVICE_ID_NX2_57840_O
225 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
226 #endif
227 #ifndef PCI_DEVICE_ID_NX2_57810_VF
228 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
229 #endif
230 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
231 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
232 #endif
233 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
234 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
235 #endif
236 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
237 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
238 #endif
239 #ifndef PCI_DEVICE_ID_NX2_57840_MF
240 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
241 #endif
242 #ifndef PCI_DEVICE_ID_NX2_57840_VF
243 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
244 #endif
245 #ifndef PCI_DEVICE_ID_NX2_57811
246 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
247 #endif
248 #ifndef PCI_DEVICE_ID_NX2_57811_MF
249 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
250 #endif
251 #ifndef PCI_DEVICE_ID_NX2_57811_VF
252 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
253 #endif
254 
255 static const struct pci_device_id bnx2x_pci_tbl[] = {
256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
269         { PCI_VDEVICE(QLOGIC,   PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
272         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
273         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
274         { PCI_VDEVICE(QLOGIC,   PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
275         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
276         { PCI_VDEVICE(QLOGIC,   PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
277         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
278         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
279         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
280         { 0 }
281 };
282 
283 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
284 
285 /* Global resources for unloading a previously loaded device */
286 #define BNX2X_PREV_WAIT_NEEDED 1
287 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
288 static LIST_HEAD(bnx2x_prev_list);
289 
290 /* Forward declaration */
291 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
292 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
293 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
294 
295 /****************************************************************************
296 * General service functions
297 ****************************************************************************/
298 
299 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
300 
301 static void __storm_memset_dma_mapping(struct bnx2x *bp,
302                                        u32 addr, dma_addr_t mapping)
303 {
304         REG_WR(bp,  addr, U64_LO(mapping));
305         REG_WR(bp,  addr + 4, U64_HI(mapping));
306 }
307 
308 static void storm_memset_spq_addr(struct bnx2x *bp,
309                                   dma_addr_t mapping, u16 abs_fid)
310 {
311         u32 addr = XSEM_REG_FAST_MEMORY +
312                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
313 
314         __storm_memset_dma_mapping(bp, addr, mapping);
315 }
316 
317 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
318                                   u16 pf_id)
319 {
320         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
321                 pf_id);
322         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
323                 pf_id);
324         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
325                 pf_id);
326         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
327                 pf_id);
328 }
329 
330 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
331                                  u8 enable)
332 {
333         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
334                 enable);
335         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
336                 enable);
337         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
338                 enable);
339         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
340                 enable);
341 }
342 
343 static void storm_memset_eq_data(struct bnx2x *bp,
344                                  struct event_ring_data *eq_data,
345                                 u16 pfid)
346 {
347         size_t size = sizeof(struct event_ring_data);
348 
349         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
350 
351         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
352 }
353 
354 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
355                                  u16 pfid)
356 {
357         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
358         REG_WR16(bp, addr, eq_prod);
359 }
360 
361 /* used only at init
362  * locking is done by mcp
363  */
364 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
365 {
366         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
367         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
368         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
369                                PCICFG_VENDOR_ID_OFFSET);
370 }
371 
372 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
373 {
374         u32 val;
375 
376         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
377         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
378         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
379                                PCICFG_VENDOR_ID_OFFSET);
380 
381         return val;
382 }
383 
384 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
385 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
386 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
387 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
388 #define DMAE_DP_DST_NONE        "dst_addr [none]"
389 
390 static void bnx2x_dp_dmae(struct bnx2x *bp,
391                           struct dmae_command *dmae, int msglvl)
392 {
393         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
394         int i;
395 
396         switch (dmae->opcode & DMAE_COMMAND_DST) {
397         case DMAE_CMD_DST_PCI:
398                 if (src_type == DMAE_CMD_SRC_PCI)
399                         DP(msglvl, "DMAE: opcode 0x%08x\n"
400                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
401                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
402                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
403                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
404                            dmae->comp_addr_hi, dmae->comp_addr_lo,
405                            dmae->comp_val);
406                 else
407                         DP(msglvl, "DMAE: opcode 0x%08x\n"
408                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
409                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
410                            dmae->opcode, dmae->src_addr_lo >> 2,
411                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
412                            dmae->comp_addr_hi, dmae->comp_addr_lo,
413                            dmae->comp_val);
414                 break;
415         case DMAE_CMD_DST_GRC:
416                 if (src_type == DMAE_CMD_SRC_PCI)
417                         DP(msglvl, "DMAE: opcode 0x%08x\n"
418                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
419                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
420                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
421                            dmae->len, dmae->dst_addr_lo >> 2,
422                            dmae->comp_addr_hi, dmae->comp_addr_lo,
423                            dmae->comp_val);
424                 else
425                         DP(msglvl, "DMAE: opcode 0x%08x\n"
426                            "src [%08x], len [%d*4], dst [%08x]\n"
427                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
428                            dmae->opcode, dmae->src_addr_lo >> 2,
429                            dmae->len, dmae->dst_addr_lo >> 2,
430                            dmae->comp_addr_hi, dmae->comp_addr_lo,
431                            dmae->comp_val);
432                 break;
433         default:
434                 if (src_type == DMAE_CMD_SRC_PCI)
435                         DP(msglvl, "DMAE: opcode 0x%08x\n"
436                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
437                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
438                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
439                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
440                            dmae->comp_val);
441                 else
442                         DP(msglvl, "DMAE: opcode 0x%08x\n"
443                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
444                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
445                            dmae->opcode, dmae->src_addr_lo >> 2,
446                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
447                            dmae->comp_val);
448                 break;
449         }
450 
451         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
452                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
453                    i, *(((u32 *)dmae) + i));
454 }
455 
456 /* copy command into DMAE command memory and set DMAE command go */
457 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
458 {
459         u32 cmd_offset;
460         int i;
461 
462         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
463         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
464                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
465         }
466         REG_WR(bp, dmae_reg_go_c[idx], 1);
467 }
468 
469 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
470 {
471         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
472                            DMAE_CMD_C_ENABLE);
473 }
474 
475 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
476 {
477         return opcode & ~DMAE_CMD_SRC_RESET;
478 }
479 
480 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
481                              bool with_comp, u8 comp_type)
482 {
483         u32 opcode = 0;
484 
485         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
486                    (dst_type << DMAE_COMMAND_DST_SHIFT));
487 
488         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
489 
490         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
491         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
492                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
493         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
494 
495 #ifdef __BIG_ENDIAN
496         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
497 #else
498         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
499 #endif
500         if (with_comp)
501                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
502         return opcode;
503 }
504 
505 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
506                                       struct dmae_command *dmae,
507                                       u8 src_type, u8 dst_type)
508 {
509         memset(dmae, 0, sizeof(struct dmae_command));
510 
511         /* set the opcode */
512         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
513                                          true, DMAE_COMP_PCI);
514 
515         /* fill in the completion parameters */
516         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
517         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
518         dmae->comp_val = DMAE_COMP_VAL;
519 }
520 
521 /* issue a dmae command over the init-channel and wait for completion */
522 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
523                                u32 *comp)
524 {
525         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
526         int rc = 0;
527 
528         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
529 
530         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
531          * as long as this code is called both from syscall context and
532          * from ndo_set_rx_mode() flow that may be called from BH.
533          */
534 
535         spin_lock_bh(&bp->dmae_lock);
536 
537         /* reset completion */
538         *comp = 0;
539 
540         /* post the command on the channel used for initializations */
541         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
542 
543         /* wait for completion */
544         udelay(5);
545         while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
546 
547                 if (!cnt ||
548                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
549                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
550                         BNX2X_ERR("DMAE timeout!\n");
551                         rc = DMAE_TIMEOUT;
552                         goto unlock;
553                 }
554                 cnt--;
555                 udelay(50);
556         }
557         if (*comp & DMAE_PCI_ERR_FLAG) {
558                 BNX2X_ERR("DMAE PCI error!\n");
559                 rc = DMAE_PCI_ERROR;
560         }
561 
562 unlock:
563 
564         spin_unlock_bh(&bp->dmae_lock);
565 
566         return rc;
567 }
568 
569 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
570                       u32 len32)
571 {
572         int rc;
573         struct dmae_command dmae;
574 
575         if (!bp->dmae_ready) {
576                 u32 *data = bnx2x_sp(bp, wb_data[0]);
577 
578                 if (CHIP_IS_E1(bp))
579                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
580                 else
581                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
582                 return;
583         }
584 
585         /* set opcode and fixed command fields */
586         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
587 
588         /* fill in addresses and len */
589         dmae.src_addr_lo = U64_LO(dma_addr);
590         dmae.src_addr_hi = U64_HI(dma_addr);
591         dmae.dst_addr_lo = dst_addr >> 2;
592         dmae.dst_addr_hi = 0;
593         dmae.len = len32;
594 
595         /* issue the command and wait for completion */
596         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
597         if (rc) {
598                 BNX2X_ERR("DMAE returned failure %d\n", rc);
599 #ifdef BNX2X_STOP_ON_ERROR
600                 bnx2x_panic();
601 #endif
602         }
603 }
604 
605 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
606 {
607         int rc;
608         struct dmae_command dmae;
609 
610         if (!bp->dmae_ready) {
611                 u32 *data = bnx2x_sp(bp, wb_data[0]);
612                 int i;
613 
614                 if (CHIP_IS_E1(bp))
615                         for (i = 0; i < len32; i++)
616                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
617                 else
618                         for (i = 0; i < len32; i++)
619                                 data[i] = REG_RD(bp, src_addr + i*4);
620 
621                 return;
622         }
623 
624         /* set opcode and fixed command fields */
625         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
626 
627         /* fill in addresses and len */
628         dmae.src_addr_lo = src_addr >> 2;
629         dmae.src_addr_hi = 0;
630         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
631         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
632         dmae.len = len32;
633 
634         /* issue the command and wait for completion */
635         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
636         if (rc) {
637                 BNX2X_ERR("DMAE returned failure %d\n", rc);
638 #ifdef BNX2X_STOP_ON_ERROR
639                 bnx2x_panic();
640 #endif
641         }
642 }
643 
644 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
645                                       u32 addr, u32 len)
646 {
647         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
648         int offset = 0;
649 
650         while (len > dmae_wr_max) {
651                 bnx2x_write_dmae(bp, phys_addr + offset,
652                                  addr + offset, dmae_wr_max);
653                 offset += dmae_wr_max * 4;
654                 len -= dmae_wr_max;
655         }
656 
657         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
658 }
659 
660 enum storms {
661            XSTORM,
662            TSTORM,
663            CSTORM,
664            USTORM,
665            MAX_STORMS
666 };
667 
668 #define STORMS_NUM 4
669 #define REGS_IN_ENTRY 4
670 
671 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
672                                               enum storms storm,
673                                               int entry)
674 {
675         switch (storm) {
676         case XSTORM:
677                 return XSTORM_ASSERT_LIST_OFFSET(entry);
678         case TSTORM:
679                 return TSTORM_ASSERT_LIST_OFFSET(entry);
680         case CSTORM:
681                 return CSTORM_ASSERT_LIST_OFFSET(entry);
682         case USTORM:
683                 return USTORM_ASSERT_LIST_OFFSET(entry);
684         case MAX_STORMS:
685         default:
686                 BNX2X_ERR("unknown storm\n");
687         }
688         return -EINVAL;
689 }
690 
691 static int bnx2x_mc_assert(struct bnx2x *bp)
692 {
693         char last_idx;
694         int i, j, rc = 0;
695         enum storms storm;
696         u32 regs[REGS_IN_ENTRY];
697         u32 bar_storm_intmem[STORMS_NUM] = {
698                 BAR_XSTRORM_INTMEM,
699                 BAR_TSTRORM_INTMEM,
700                 BAR_CSTRORM_INTMEM,
701                 BAR_USTRORM_INTMEM
702         };
703         u32 storm_assert_list_index[STORMS_NUM] = {
704                 XSTORM_ASSERT_LIST_INDEX_OFFSET,
705                 TSTORM_ASSERT_LIST_INDEX_OFFSET,
706                 CSTORM_ASSERT_LIST_INDEX_OFFSET,
707                 USTORM_ASSERT_LIST_INDEX_OFFSET
708         };
709         char *storms_string[STORMS_NUM] = {
710                 "XSTORM",
711                 "TSTORM",
712                 "CSTORM",
713                 "USTORM"
714         };
715 
716         for (storm = XSTORM; storm < MAX_STORMS; storm++) {
717                 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
718                                    storm_assert_list_index[storm]);
719                 if (last_idx)
720                         BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
721                                   storms_string[storm], last_idx);
722 
723                 /* print the asserts */
724                 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
725                         /* read a single assert entry */
726                         for (j = 0; j < REGS_IN_ENTRY; j++)
727                                 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
728                                           bnx2x_get_assert_list_entry(bp,
729                                                                       storm,
730                                                                       i) +
731                                           sizeof(u32) * j);
732 
733                         /* log entry if it contains a valid assert */
734                         if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
735                                 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
736                                           storms_string[storm], i, regs[3],
737                                           regs[2], regs[1], regs[0]);
738                                 rc++;
739                         } else {
740                                 break;
741                         }
742                 }
743         }
744 
745         BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
746                   CHIP_IS_E1(bp) ? "everest1" :
747                   CHIP_IS_E1H(bp) ? "everest1h" :
748                   CHIP_IS_E2(bp) ? "everest2" : "everest3",
749                   BCM_5710_FW_MAJOR_VERSION,
750                   BCM_5710_FW_MINOR_VERSION,
751                   BCM_5710_FW_REVISION_VERSION);
752 
753         return rc;
754 }
755 
756 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
757 #define SCRATCH_BUFFER_SIZE(bp) \
758         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
759 
760 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
761 {
762         u32 addr, val;
763         u32 mark, offset;
764         __be32 data[9];
765         int word;
766         u32 trace_shmem_base;
767         if (BP_NOMCP(bp)) {
768                 BNX2X_ERR("NO MCP - can not dump\n");
769                 return;
770         }
771         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
772                 (bp->common.bc_ver & 0xff0000) >> 16,
773                 (bp->common.bc_ver & 0xff00) >> 8,
774                 (bp->common.bc_ver & 0xff));
775 
776         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
777         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
778                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
779 
780         if (BP_PATH(bp) == 0)
781                 trace_shmem_base = bp->common.shmem_base;
782         else
783                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
784 
785         /* sanity */
786         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
787             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
788                                 SCRATCH_BUFFER_SIZE(bp)) {
789                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
790                           trace_shmem_base);
791                 return;
792         }
793 
794         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
795 
796         /* validate TRCB signature */
797         mark = REG_RD(bp, addr);
798         if (mark != MFW_TRACE_SIGNATURE) {
799                 BNX2X_ERR("Trace buffer signature is missing.");
800                 return ;
801         }
802 
803         /* read cyclic buffer pointer */
804         addr += 4;
805         mark = REG_RD(bp, addr);
806         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
807         if (mark >= trace_shmem_base || mark < addr + 4) {
808                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
809                 return;
810         }
811         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
812 
813         printk("%s", lvl);
814 
815         /* dump buffer after the mark */
816         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
817                 for (word = 0; word < 8; word++)
818                         data[word] = htonl(REG_RD(bp, offset + 4*word));
819                 data[8] = 0x0;
820                 pr_cont("%s", (char *)data);
821         }
822 
823         /* dump buffer before the mark */
824         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
825                 for (word = 0; word < 8; word++)
826                         data[word] = htonl(REG_RD(bp, offset + 4*word));
827                 data[8] = 0x0;
828                 pr_cont("%s", (char *)data);
829         }
830         printk("%s" "end of fw dump\n", lvl);
831 }
832 
833 static void bnx2x_fw_dump(struct bnx2x *bp)
834 {
835         bnx2x_fw_dump_lvl(bp, KERN_ERR);
836 }
837 
838 static void bnx2x_hc_int_disable(struct bnx2x *bp)
839 {
840         int port = BP_PORT(bp);
841         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
842         u32 val = REG_RD(bp, addr);
843 
844         /* in E1 we must use only PCI configuration space to disable
845          * MSI/MSIX capability
846          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
847          */
848         if (CHIP_IS_E1(bp)) {
849                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
850                  * Use mask register to prevent from HC sending interrupts
851                  * after we exit the function
852                  */
853                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
854 
855                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
856                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
857                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
858         } else
859                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
860                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
861                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
862                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
863 
864         DP(NETIF_MSG_IFDOWN,
865            "write %x to HC %d (addr 0x%x)\n",
866            val, port, addr);
867 
868         /* flush all outstanding writes */
869         mmiowb();
870 
871         REG_WR(bp, addr, val);
872         if (REG_RD(bp, addr) != val)
873                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
874 }
875 
876 static void bnx2x_igu_int_disable(struct bnx2x *bp)
877 {
878         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
879 
880         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
881                  IGU_PF_CONF_INT_LINE_EN |
882                  IGU_PF_CONF_ATTN_BIT_EN);
883 
884         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
885 
886         /* flush all outstanding writes */
887         mmiowb();
888 
889         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
890         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
891                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
892 }
893 
894 static void bnx2x_int_disable(struct bnx2x *bp)
895 {
896         if (bp->common.int_block == INT_BLOCK_HC)
897                 bnx2x_hc_int_disable(bp);
898         else
899                 bnx2x_igu_int_disable(bp);
900 }
901 
902 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
903 {
904         int i;
905         u16 j;
906         struct hc_sp_status_block_data sp_sb_data;
907         int func = BP_FUNC(bp);
908 #ifdef BNX2X_STOP_ON_ERROR
909         u16 start = 0, end = 0;
910         u8 cos;
911 #endif
912         if (IS_PF(bp) && disable_int)
913                 bnx2x_int_disable(bp);
914 
915         bp->stats_state = STATS_STATE_DISABLED;
916         bp->eth_stats.unrecoverable_error++;
917         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
918 
919         BNX2X_ERR("begin crash dump -----------------\n");
920 
921         /* Indices */
922         /* Common */
923         if (IS_PF(bp)) {
924                 struct host_sp_status_block *def_sb = bp->def_status_blk;
925                 int data_size, cstorm_offset;
926 
927                 BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
928                           bp->def_idx, bp->def_att_idx, bp->attn_state,
929                           bp->spq_prod_idx, bp->stats_counter);
930                 BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
931                           def_sb->atten_status_block.attn_bits,
932                           def_sb->atten_status_block.attn_bits_ack,
933                           def_sb->atten_status_block.status_block_id,
934                           def_sb->atten_status_block.attn_bits_index);
935                 BNX2X_ERR("     def (");
936                 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
937                         pr_cont("0x%x%s",
938                                 def_sb->sp_sb.index_values[i],
939                                 (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
940 
941                 data_size = sizeof(struct hc_sp_status_block_data) /
942                             sizeof(u32);
943                 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
944                 for (i = 0; i < data_size; i++)
945                         *((u32 *)&sp_sb_data + i) =
946                                 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
947                                            i * sizeof(u32));
948 
949                 pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
950                         sp_sb_data.igu_sb_id,
951                         sp_sb_data.igu_seg_id,
952                         sp_sb_data.p_func.pf_id,
953                         sp_sb_data.p_func.vnic_id,
954                         sp_sb_data.p_func.vf_id,
955                         sp_sb_data.p_func.vf_valid,
956                         sp_sb_data.state);
957         }
958 
959         for_each_eth_queue(bp, i) {
960                 struct bnx2x_fastpath *fp = &bp->fp[i];
961                 int loop;
962                 struct hc_status_block_data_e2 sb_data_e2;
963                 struct hc_status_block_data_e1x sb_data_e1x;
964                 struct hc_status_block_sm  *hc_sm_p =
965                         CHIP_IS_E1x(bp) ?
966                         sb_data_e1x.common.state_machine :
967                         sb_data_e2.common.state_machine;
968                 struct hc_index_data *hc_index_p =
969                         CHIP_IS_E1x(bp) ?
970                         sb_data_e1x.index_data :
971                         sb_data_e2.index_data;
972                 u8 data_size, cos;
973                 u32 *sb_data_p;
974                 struct bnx2x_fp_txdata txdata;
975 
976                 if (!bp->fp)
977                         break;
978 
979                 if (!fp->rx_cons_sb)
980                         continue;
981 
982                 /* Rx */
983                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
984                           i, fp->rx_bd_prod, fp->rx_bd_cons,
985                           fp->rx_comp_prod,
986                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
987                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
988                           fp->rx_sge_prod, fp->last_max_sge,
989                           le16_to_cpu(fp->fp_hc_idx));
990 
991                 /* Tx */
992                 for_each_cos_in_tx_queue(fp, cos)
993                 {
994                         if (!fp->txdata_ptr[cos])
995                                 break;
996 
997                         txdata = *fp->txdata_ptr[cos];
998 
999                         if (!txdata.tx_cons_sb)
1000                                 continue;
1001 
1002                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
1003                                   i, txdata.tx_pkt_prod,
1004                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
1005                                   txdata.tx_bd_cons,
1006                                   le16_to_cpu(*txdata.tx_cons_sb));
1007                 }
1008 
1009                 loop = CHIP_IS_E1x(bp) ?
1010                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1011 
1012                 /* host sb data */
1013 
1014                 if (IS_FCOE_FP(fp))
1015                         continue;
1016 
1017                 BNX2X_ERR("     run indexes (");
1018                 for (j = 0; j < HC_SB_MAX_SM; j++)
1019                         pr_cont("0x%x%s",
1020                                fp->sb_running_index[j],
1021                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1022 
1023                 BNX2X_ERR("     indexes (");
1024                 for (j = 0; j < loop; j++)
1025                         pr_cont("0x%x%s",
1026                                fp->sb_index_values[j],
1027                                (j == loop - 1) ? ")" : " ");
1028 
1029                 /* VF cannot access FW refelection for status block */
1030                 if (IS_VF(bp))
1031                         continue;
1032 
1033                 /* fw sb data */
1034                 data_size = CHIP_IS_E1x(bp) ?
1035                         sizeof(struct hc_status_block_data_e1x) :
1036                         sizeof(struct hc_status_block_data_e2);
1037                 data_size /= sizeof(u32);
1038                 sb_data_p = CHIP_IS_E1x(bp) ?
1039                         (u32 *)&sb_data_e1x :
1040                         (u32 *)&sb_data_e2;
1041                 /* copy sb data in here */
1042                 for (j = 0; j < data_size; j++)
1043                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1044                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1045                                 j * sizeof(u32));
1046 
1047                 if (!CHIP_IS_E1x(bp)) {
1048                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1049                                 sb_data_e2.common.p_func.pf_id,
1050                                 sb_data_e2.common.p_func.vf_id,
1051                                 sb_data_e2.common.p_func.vf_valid,
1052                                 sb_data_e2.common.p_func.vnic_id,
1053                                 sb_data_e2.common.same_igu_sb_1b,
1054                                 sb_data_e2.common.state);
1055                 } else {
1056                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1057                                 sb_data_e1x.common.p_func.pf_id,
1058                                 sb_data_e1x.common.p_func.vf_id,
1059                                 sb_data_e1x.common.p_func.vf_valid,
1060                                 sb_data_e1x.common.p_func.vnic_id,
1061                                 sb_data_e1x.common.same_igu_sb_1b,
1062                                 sb_data_e1x.common.state);
1063                 }
1064 
1065                 /* SB_SMs data */
1066                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1067                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1068                                 j, hc_sm_p[j].__flags,
1069                                 hc_sm_p[j].igu_sb_id,
1070                                 hc_sm_p[j].igu_seg_id,
1071                                 hc_sm_p[j].time_to_expire,
1072                                 hc_sm_p[j].timer_value);
1073                 }
1074 
1075                 /* Indices data */
1076                 for (j = 0; j < loop; j++) {
1077                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1078                                hc_index_p[j].flags,
1079                                hc_index_p[j].timeout);
1080                 }
1081         }
1082 
1083 #ifdef BNX2X_STOP_ON_ERROR
1084         if (IS_PF(bp)) {
1085                 /* event queue */
1086                 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1087                 for (i = 0; i < NUM_EQ_DESC; i++) {
1088                         u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1089 
1090                         BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1091                                   i, bp->eq_ring[i].message.opcode,
1092                                   bp->eq_ring[i].message.error);
1093                         BNX2X_ERR("data: %x %x %x\n",
1094                                   data[0], data[1], data[2]);
1095                 }
1096         }
1097 
1098         /* Rings */
1099         /* Rx */
1100         for_each_valid_rx_queue(bp, i) {
1101                 struct bnx2x_fastpath *fp = &bp->fp[i];
1102 
1103                 if (!bp->fp)
1104                         break;
1105 
1106                 if (!fp->rx_cons_sb)
1107                         continue;
1108 
1109                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1110                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1111                 for (j = start; j != end; j = RX_BD(j + 1)) {
1112                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1113                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1114 
1115                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1116                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1117                 }
1118 
1119                 start = RX_SGE(fp->rx_sge_prod);
1120                 end = RX_SGE(fp->last_max_sge);
1121                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1122                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1123                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1124 
1125                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1126                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1127                 }
1128 
1129                 start = RCQ_BD(fp->rx_comp_cons - 10);
1130                 end = RCQ_BD(fp->rx_comp_cons + 503);
1131                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1132                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1133 
1134                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1135                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1136                 }
1137         }
1138 
1139         /* Tx */
1140         for_each_valid_tx_queue(bp, i) {
1141                 struct bnx2x_fastpath *fp = &bp->fp[i];
1142 
1143                 if (!bp->fp)
1144                         break;
1145 
1146                 for_each_cos_in_tx_queue(fp, cos) {
1147                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1148 
1149                         if (!fp->txdata_ptr[cos])
1150                                 break;
1151 
1152                         if (!txdata->tx_cons_sb)
1153                                 continue;
1154 
1155                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1156                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1157                         for (j = start; j != end; j = TX_BD(j + 1)) {
1158                                 struct sw_tx_bd *sw_bd =
1159                                         &txdata->tx_buf_ring[j];
1160 
1161                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1162                                           i, cos, j, sw_bd->skb,
1163                                           sw_bd->first_bd);
1164                         }
1165 
1166                         start = TX_BD(txdata->tx_bd_cons - 10);
1167                         end = TX_BD(txdata->tx_bd_cons + 254);
1168                         for (j = start; j != end; j = TX_BD(j + 1)) {
1169                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1170 
1171                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1172                                           i, cos, j, tx_bd[0], tx_bd[1],
1173                                           tx_bd[2], tx_bd[3]);
1174                         }
1175                 }
1176         }
1177 #endif
1178         if (IS_PF(bp)) {
1179                 bnx2x_fw_dump(bp);
1180                 bnx2x_mc_assert(bp);
1181         }
1182         BNX2X_ERR("end crash dump -----------------\n");
1183 }
1184 
1185 /*
1186  * FLR Support for E2
1187  *
1188  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1189  * initialization.
1190  */
1191 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1192 #define FLR_WAIT_INTERVAL       50      /* usec */
1193 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1194 
1195 struct pbf_pN_buf_regs {
1196         int pN;
1197         u32 init_crd;
1198         u32 crd;
1199         u32 crd_freed;
1200 };
1201 
1202 struct pbf_pN_cmd_regs {
1203         int pN;
1204         u32 lines_occup;
1205         u32 lines_freed;
1206 };
1207 
1208 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1209                                      struct pbf_pN_buf_regs *regs,
1210                                      u32 poll_count)
1211 {
1212         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1213         u32 cur_cnt = poll_count;
1214 
1215         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1216         crd = crd_start = REG_RD(bp, regs->crd);
1217         init_crd = REG_RD(bp, regs->init_crd);
1218 
1219         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1220         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1221         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1222 
1223         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1224                (init_crd - crd_start))) {
1225                 if (cur_cnt--) {
1226                         udelay(FLR_WAIT_INTERVAL);
1227                         crd = REG_RD(bp, regs->crd);
1228                         crd_freed = REG_RD(bp, regs->crd_freed);
1229                 } else {
1230                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1231                            regs->pN);
1232                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1233                            regs->pN, crd);
1234                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1235                            regs->pN, crd_freed);
1236                         break;
1237                 }
1238         }
1239         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1240            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1241 }
1242 
1243 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1244                                      struct pbf_pN_cmd_regs *regs,
1245                                      u32 poll_count)
1246 {
1247         u32 occup, to_free, freed, freed_start;
1248         u32 cur_cnt = poll_count;
1249 
1250         occup = to_free = REG_RD(bp, regs->lines_occup);
1251         freed = freed_start = REG_RD(bp, regs->lines_freed);
1252 
1253         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1254         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1255 
1256         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1257                 if (cur_cnt--) {
1258                         udelay(FLR_WAIT_INTERVAL);
1259                         occup = REG_RD(bp, regs->lines_occup);
1260                         freed = REG_RD(bp, regs->lines_freed);
1261                 } else {
1262                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1263                            regs->pN);
1264                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1265                            regs->pN, occup);
1266                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1267                            regs->pN, freed);
1268                         break;
1269                 }
1270         }
1271         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1272            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1273 }
1274 
1275 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1276                                     u32 expected, u32 poll_count)
1277 {
1278         u32 cur_cnt = poll_count;
1279         u32 val;
1280 
1281         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1282                 udelay(FLR_WAIT_INTERVAL);
1283 
1284         return val;
1285 }
1286 
1287 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1288                                     char *msg, u32 poll_cnt)
1289 {
1290         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1291         if (val != 0) {
1292                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1293                 return 1;
1294         }
1295         return 0;
1296 }
1297 
1298 /* Common routines with VF FLR cleanup */
1299 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1300 {
1301         /* adjust polling timeout */
1302         if (CHIP_REV_IS_EMUL(bp))
1303                 return FLR_POLL_CNT * 2000;
1304 
1305         if (CHIP_REV_IS_FPGA(bp))
1306                 return FLR_POLL_CNT * 120;
1307 
1308         return FLR_POLL_CNT;
1309 }
1310 
1311 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1312 {
1313         struct pbf_pN_cmd_regs cmd_regs[] = {
1314                 {0, (CHIP_IS_E3B0(bp)) ?
1315                         PBF_REG_TQ_OCCUPANCY_Q0 :
1316                         PBF_REG_P0_TQ_OCCUPANCY,
1317                     (CHIP_IS_E3B0(bp)) ?
1318                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1319                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1320                 {1, (CHIP_IS_E3B0(bp)) ?
1321                         PBF_REG_TQ_OCCUPANCY_Q1 :
1322                         PBF_REG_P1_TQ_OCCUPANCY,
1323                     (CHIP_IS_E3B0(bp)) ?
1324                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1325                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1326                 {4, (CHIP_IS_E3B0(bp)) ?
1327                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1328                         PBF_REG_P4_TQ_OCCUPANCY,
1329                     (CHIP_IS_E3B0(bp)) ?
1330                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1331                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1332         };
1333 
1334         struct pbf_pN_buf_regs buf_regs[] = {
1335                 {0, (CHIP_IS_E3B0(bp)) ?
1336                         PBF_REG_INIT_CRD_Q0 :
1337                         PBF_REG_P0_INIT_CRD ,
1338                     (CHIP_IS_E3B0(bp)) ?
1339                         PBF_REG_CREDIT_Q0 :
1340                         PBF_REG_P0_CREDIT,
1341                     (CHIP_IS_E3B0(bp)) ?
1342                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1343                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1344                 {1, (CHIP_IS_E3B0(bp)) ?
1345                         PBF_REG_INIT_CRD_Q1 :
1346                         PBF_REG_P1_INIT_CRD,
1347                     (CHIP_IS_E3B0(bp)) ?
1348                         PBF_REG_CREDIT_Q1 :
1349                         PBF_REG_P1_CREDIT,
1350                     (CHIP_IS_E3B0(bp)) ?
1351                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1352                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1353                 {4, (CHIP_IS_E3B0(bp)) ?
1354                         PBF_REG_INIT_CRD_LB_Q :
1355                         PBF_REG_P4_INIT_CRD,
1356                     (CHIP_IS_E3B0(bp)) ?
1357                         PBF_REG_CREDIT_LB_Q :
1358                         PBF_REG_P4_CREDIT,
1359                     (CHIP_IS_E3B0(bp)) ?
1360                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1361                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1362         };
1363 
1364         int i;
1365 
1366         /* Verify the command queues are flushed P0, P1, P4 */
1367         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1368                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1369 
1370         /* Verify the transmission buffers are flushed P0, P1, P4 */
1371         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1372                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1373 }
1374 
1375 #define OP_GEN_PARAM(param) \
1376         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1377 
1378 #define OP_GEN_TYPE(type) \
1379         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1380 
1381 #define OP_GEN_AGG_VECT(index) \
1382         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1383 
1384 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1385 {
1386         u32 op_gen_command = 0;
1387         u32 comp_addr = BAR_CSTRORM_INTMEM +
1388                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1389         int ret = 0;
1390 
1391         if (REG_RD(bp, comp_addr)) {
1392                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1393                 return 1;
1394         }
1395 
1396         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1397         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1398         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1399         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1400 
1401         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1402         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1403 
1404         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1405                 BNX2X_ERR("FW final cleanup did not succeed\n");
1406                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1407                    (REG_RD(bp, comp_addr)));
1408                 bnx2x_panic();
1409                 return 1;
1410         }
1411         /* Zero completion for next FLR */
1412         REG_WR(bp, comp_addr, 0);
1413 
1414         return ret;
1415 }
1416 
1417 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1418 {
1419         u16 status;
1420 
1421         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1422         return status & PCI_EXP_DEVSTA_TRPND;
1423 }
1424 
1425 /* PF FLR specific routines
1426 */
1427 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1428 {
1429         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1430         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1431                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1432                         "CFC PF usage counter timed out",
1433                         poll_cnt))
1434                 return 1;
1435 
1436         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1437         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1438                         DORQ_REG_PF_USAGE_CNT,
1439                         "DQ PF usage counter timed out",
1440                         poll_cnt))
1441                 return 1;
1442 
1443         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1444         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1445                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1446                         "QM PF usage counter timed out",
1447                         poll_cnt))
1448                 return 1;
1449 
1450         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1451         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1452                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1453                         "Timers VNIC usage counter timed out",
1454                         poll_cnt))
1455                 return 1;
1456         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1457                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1458                         "Timers NUM_SCANS usage counter timed out",
1459                         poll_cnt))
1460                 return 1;
1461 
1462         /* Wait DMAE PF usage counter to zero */
1463         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1464                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1465                         "DMAE command register timed out",
1466                         poll_cnt))
1467                 return 1;
1468 
1469         return 0;
1470 }
1471 
1472 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1473 {
1474         u32 val;
1475 
1476         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1477         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1478 
1479         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1480         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1481 
1482         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1483         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1484 
1485         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1486         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1487 
1488         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1489         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1490 
1491         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1492         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1493 
1494         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1495         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1496 
1497         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1498         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1499            val);
1500 }
1501 
1502 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1503 {
1504         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1505 
1506         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1507 
1508         /* Re-enable PF target read access */
1509         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1510 
1511         /* Poll HW usage counters */
1512         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1513         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1514                 return -EBUSY;
1515 
1516         /* Zero the igu 'trailing edge' and 'leading edge' */
1517 
1518         /* Send the FW cleanup command */
1519         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1520                 return -EBUSY;
1521 
1522         /* ATC cleanup */
1523 
1524         /* Verify TX hw is flushed */
1525         bnx2x_tx_hw_flushed(bp, poll_cnt);
1526 
1527         /* Wait 100ms (not adjusted according to platform) */
1528         msleep(100);
1529 
1530         /* Verify no pending pci transactions */
1531         if (bnx2x_is_pcie_pending(bp->pdev))
1532                 BNX2X_ERR("PCIE Transactions still pending\n");
1533 
1534         /* Debug */
1535         bnx2x_hw_enable_status(bp);
1536 
1537         /*
1538          * Master enable - Due to WB DMAE writes performed before this
1539          * register is re-initialized as part of the regular function init
1540          */
1541         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1542 
1543         return 0;
1544 }
1545 
1546 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1547 {
1548         int port = BP_PORT(bp);
1549         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1550         u32 val = REG_RD(bp, addr);
1551         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1552         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1553         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1554 
1555         if (msix) {
1556                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1557                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1558                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1559                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1560                 if (single_msix)
1561                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1562         } else if (msi) {
1563                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1564                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1565                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1566                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1567         } else {
1568                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1569                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1570                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1571                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1572 
1573                 if (!CHIP_IS_E1(bp)) {
1574                         DP(NETIF_MSG_IFUP,
1575                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1576 
1577                         REG_WR(bp, addr, val);
1578 
1579                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1580                 }
1581         }
1582 
1583         if (CHIP_IS_E1(bp))
1584                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1585 
1586         DP(NETIF_MSG_IFUP,
1587            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1588            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1589 
1590         REG_WR(bp, addr, val);
1591         /*
1592          * Ensure that HC_CONFIG is written before leading/trailing edge config
1593          */
1594         mmiowb();
1595         barrier();
1596 
1597         if (!CHIP_IS_E1(bp)) {
1598                 /* init leading/trailing edge */
1599                 if (IS_MF(bp)) {
1600                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1601                         if (bp->port.pmf)
1602                                 /* enable nig and gpio3 attention */
1603                                 val |= 0x1100;
1604                 } else
1605                         val = 0xffff;
1606 
1607                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1608                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1609         }
1610 
1611         /* Make sure that interrupts are indeed enabled from here on */
1612         mmiowb();
1613 }
1614 
1615 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1616 {
1617         u32 val;
1618         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1619         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1620         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1621 
1622         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1623 
1624         if (msix) {
1625                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1626                          IGU_PF_CONF_SINGLE_ISR_EN);
1627                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1628                         IGU_PF_CONF_ATTN_BIT_EN);
1629 
1630                 if (single_msix)
1631                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1632         } else if (msi) {
1633                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1634                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1635                         IGU_PF_CONF_ATTN_BIT_EN |
1636                         IGU_PF_CONF_SINGLE_ISR_EN);
1637         } else {
1638                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1639                 val |= (IGU_PF_CONF_INT_LINE_EN |
1640                         IGU_PF_CONF_ATTN_BIT_EN |
1641                         IGU_PF_CONF_SINGLE_ISR_EN);
1642         }
1643 
1644         /* Clean previous status - need to configure igu prior to ack*/
1645         if ((!msix) || single_msix) {
1646                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1647                 bnx2x_ack_int(bp);
1648         }
1649 
1650         val |= IGU_PF_CONF_FUNC_EN;
1651 
1652         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1653            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1654 
1655         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1656 
1657         if (val & IGU_PF_CONF_INT_LINE_EN)
1658                 pci_intx(bp->pdev, true);
1659 
1660         barrier();
1661 
1662         /* init leading/trailing edge */
1663         if (IS_MF(bp)) {
1664                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1665                 if (bp->port.pmf)
1666                         /* enable nig and gpio3 attention */
1667                         val |= 0x1100;
1668         } else
1669                 val = 0xffff;
1670 
1671         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1672         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1673 
1674         /* Make sure that interrupts are indeed enabled from here on */
1675         mmiowb();
1676 }
1677 
1678 void bnx2x_int_enable(struct bnx2x *bp)
1679 {
1680         if (bp->common.int_block == INT_BLOCK_HC)
1681                 bnx2x_hc_int_enable(bp);
1682         else
1683                 bnx2x_igu_int_enable(bp);
1684 }
1685 
1686 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1687 {
1688         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1689         int i, offset;
1690 
1691         if (disable_hw)
1692                 /* prevent the HW from sending interrupts */
1693                 bnx2x_int_disable(bp);
1694 
1695         /* make sure all ISRs are done */
1696         if (msix) {
1697                 synchronize_irq(bp->msix_table[0].vector);
1698                 offset = 1;
1699                 if (CNIC_SUPPORT(bp))
1700                         offset++;
1701                 for_each_eth_queue(bp, i)
1702                         synchronize_irq(bp->msix_table[offset++].vector);
1703         } else
1704                 synchronize_irq(bp->pdev->irq);
1705 
1706         /* make sure sp_task is not running */
1707         cancel_delayed_work(&bp->sp_task);
1708         cancel_delayed_work(&bp->period_task);
1709         flush_workqueue(bnx2x_wq);
1710 }
1711 
1712 /* fast path */
1713 
1714 /*
1715  * General service functions
1716  */
1717 
1718 /* Return true if succeeded to acquire the lock */
1719 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1720 {
1721         u32 lock_status;
1722         u32 resource_bit = (1 << resource);
1723         int func = BP_FUNC(bp);
1724         u32 hw_lock_control_reg;
1725 
1726         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1727            "Trying to take a lock on resource %d\n", resource);
1728 
1729         /* Validating that the resource is within range */
1730         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1731                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1732                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1733                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1734                 return false;
1735         }
1736 
1737         if (func <= 5)
1738                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1739         else
1740                 hw_lock_control_reg =
1741                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1742 
1743         /* Try to acquire the lock */
1744         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1745         lock_status = REG_RD(bp, hw_lock_control_reg);
1746         if (lock_status & resource_bit)
1747                 return true;
1748 
1749         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1750            "Failed to get a lock on resource %d\n", resource);
1751         return false;
1752 }
1753 
1754 /**
1755  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1756  *
1757  * @bp: driver handle
1758  *
1759  * Returns the recovery leader resource id according to the engine this function
1760  * belongs to. Currently only only 2 engines is supported.
1761  */
1762 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1763 {
1764         if (BP_PATH(bp))
1765                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1766         else
1767                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1768 }
1769 
1770 /**
1771  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1772  *
1773  * @bp: driver handle
1774  *
1775  * Tries to acquire a leader lock for current engine.
1776  */
1777 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1778 {
1779         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1780 }
1781 
1782 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1783 
1784 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1785 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1786 {
1787         /* Set the interrupt occurred bit for the sp-task to recognize it
1788          * must ack the interrupt and transition according to the IGU
1789          * state machine.
1790          */
1791         atomic_set(&bp->interrupt_occurred, 1);
1792 
1793         /* The sp_task must execute only after this bit
1794          * is set, otherwise we will get out of sync and miss all
1795          * further interrupts. Hence, the barrier.
1796          */
1797         smp_wmb();
1798 
1799         /* schedule sp_task to workqueue */
1800         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1801 }
1802 
1803 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1804 {
1805         struct bnx2x *bp = fp->bp;
1806         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1807         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1808         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1809         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1810 
1811         DP(BNX2X_MSG_SP,
1812            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1813            fp->index, cid, command, bp->state,
1814            rr_cqe->ramrod_cqe.ramrod_type);
1815 
1816         /* If cid is within VF range, replace the slowpath object with the
1817          * one corresponding to this VF
1818          */
1819         if (cid >= BNX2X_FIRST_VF_CID  &&
1820             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1821                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1822 
1823         switch (command) {
1824         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1825                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1826                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1827                 break;
1828 
1829         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1830                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1831                 drv_cmd = BNX2X_Q_CMD_SETUP;
1832                 break;
1833 
1834         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1835                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1836                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1837                 break;
1838 
1839         case (RAMROD_CMD_ID_ETH_HALT):
1840                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1841                 drv_cmd = BNX2X_Q_CMD_HALT;
1842                 break;
1843 
1844         case (RAMROD_CMD_ID_ETH_TERMINATE):
1845                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1846                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1847                 break;
1848 
1849         case (RAMROD_CMD_ID_ETH_EMPTY):
1850                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1851                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1852                 break;
1853 
1854         case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1855                 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1856                 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1857                 break;
1858 
1859         default:
1860                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1861                           command, fp->index);
1862                 return;
1863         }
1864 
1865         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1866             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1867                 /* q_obj->complete_cmd() failure means that this was
1868                  * an unexpected completion.
1869                  *
1870                  * In this case we don't want to increase the bp->spq_left
1871                  * because apparently we haven't sent this command the first
1872                  * place.
1873                  */
1874 #ifdef BNX2X_STOP_ON_ERROR
1875                 bnx2x_panic();
1876 #else
1877                 return;
1878 #endif
1879 
1880         smp_mb__before_atomic();
1881         atomic_inc(&bp->cq_spq_left);
1882         /* push the change in bp->spq_left and towards the memory */
1883         smp_mb__after_atomic();
1884 
1885         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1886 
1887         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1888             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1889                 /* if Q update ramrod is completed for last Q in AFEX vif set
1890                  * flow, then ACK MCP at the end
1891                  *
1892                  * mark pending ACK to MCP bit.
1893                  * prevent case that both bits are cleared.
1894                  * At the end of load/unload driver checks that
1895                  * sp_state is cleared, and this order prevents
1896                  * races
1897                  */
1898                 smp_mb__before_atomic();
1899                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1900                 wmb();
1901                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1902                 smp_mb__after_atomic();
1903 
1904                 /* schedule the sp task as mcp ack is required */
1905                 bnx2x_schedule_sp_task(bp);
1906         }
1907 
1908         return;
1909 }
1910 
1911 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1912 {
1913         struct bnx2x *bp = netdev_priv(dev_instance);
1914         u16 status = bnx2x_ack_int(bp);
1915         u16 mask;
1916         int i;
1917         u8 cos;
1918 
1919         /* Return here if interrupt is shared and it's not for us */
1920         if (unlikely(status == 0)) {
1921                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1922                 return IRQ_NONE;
1923         }
1924         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1925 
1926 #ifdef BNX2X_STOP_ON_ERROR
1927         if (unlikely(bp->panic))
1928                 return IRQ_HANDLED;
1929 #endif
1930 
1931         for_each_eth_queue(bp, i) {
1932                 struct bnx2x_fastpath *fp = &bp->fp[i];
1933 
1934                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1935                 if (status & mask) {
1936                         /* Handle Rx or Tx according to SB id */
1937                         for_each_cos_in_tx_queue(fp, cos)
1938                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1939                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1940                         napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1941                         status &= ~mask;
1942                 }
1943         }
1944 
1945         if (CNIC_SUPPORT(bp)) {
1946                 mask = 0x2;
1947                 if (status & (mask | 0x1)) {
1948                         struct cnic_ops *c_ops = NULL;
1949 
1950                         rcu_read_lock();
1951                         c_ops = rcu_dereference(bp->cnic_ops);
1952                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1953                                       CNIC_DRV_STATE_HANDLES_IRQ))
1954                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1955                         rcu_read_unlock();
1956 
1957                         status &= ~mask;
1958                 }
1959         }
1960 
1961         if (unlikely(status & 0x1)) {
1962 
1963                 /* schedule sp task to perform default status block work, ack
1964                  * attentions and enable interrupts.
1965                  */
1966                 bnx2x_schedule_sp_task(bp);
1967 
1968                 status &= ~0x1;
1969                 if (!status)
1970                         return IRQ_HANDLED;
1971         }
1972 
1973         if (unlikely(status))
1974                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1975                    status);
1976 
1977         return IRQ_HANDLED;
1978 }
1979 
1980 /* Link */
1981 
1982 /*
1983  * General service functions
1984  */
1985 
1986 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1987 {
1988         u32 lock_status;
1989         u32 resource_bit = (1 << resource);
1990         int func = BP_FUNC(bp);
1991         u32 hw_lock_control_reg;
1992         int cnt;
1993 
1994         /* Validating that the resource is within range */
1995         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1996                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1997                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1998                 return -EINVAL;
1999         }
2000 
2001         if (func <= 5) {
2002                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2003         } else {
2004                 hw_lock_control_reg =
2005                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2006         }
2007 
2008         /* Validating that the resource is not already taken */
2009         lock_status = REG_RD(bp, hw_lock_control_reg);
2010         if (lock_status & resource_bit) {
2011                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
2012                    lock_status, resource_bit);
2013                 return -EEXIST;
2014         }
2015 
2016         /* Try for 5 second every 5ms */
2017         for (cnt = 0; cnt < 1000; cnt++) {
2018                 /* Try to acquire the lock */
2019                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2020                 lock_status = REG_RD(bp, hw_lock_control_reg);
2021                 if (lock_status & resource_bit)
2022                         return 0;
2023 
2024                 usleep_range(5000, 10000);
2025         }
2026         BNX2X_ERR("Timeout\n");
2027         return -EAGAIN;
2028 }
2029 
2030 int bnx2x_release_leader_lock(struct bnx2x *bp)
2031 {
2032         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2033 }
2034 
2035 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2036 {
2037         u32 lock_status;
2038         u32 resource_bit = (1 << resource);
2039         int func = BP_FUNC(bp);
2040         u32 hw_lock_control_reg;
2041 
2042         /* Validating that the resource is within range */
2043         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2044                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2045                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
2046                 return -EINVAL;
2047         }
2048 
2049         if (func <= 5) {
2050                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2051         } else {
2052                 hw_lock_control_reg =
2053                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2054         }
2055 
2056         /* Validating that the resource is currently taken */
2057         lock_status = REG_RD(bp, hw_lock_control_reg);
2058         if (!(lock_status & resource_bit)) {
2059                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2060                           lock_status, resource_bit);
2061                 return -EFAULT;
2062         }
2063 
2064         REG_WR(bp, hw_lock_control_reg, resource_bit);
2065         return 0;
2066 }
2067 
2068 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2069 {
2070         /* The GPIO should be swapped if swap register is set and active */
2071         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2072                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2073         int gpio_shift = gpio_num +
2074                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2075         u32 gpio_mask = (1 << gpio_shift);
2076         u32 gpio_reg;
2077         int value;
2078 
2079         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2080                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2081                 return -EINVAL;
2082         }
2083 
2084         /* read GPIO value */
2085         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2086 
2087         /* get the requested pin value */
2088         if ((gpio_reg & gpio_mask) == gpio_mask)
2089                 value = 1;
2090         else
2091                 value = 0;
2092 
2093         return value;
2094 }
2095 
2096 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2097 {
2098         /* The GPIO should be swapped if swap register is set and active */
2099         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2100                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2101         int gpio_shift = gpio_num +
2102                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2103         u32 gpio_mask = (1 << gpio_shift);
2104         u32 gpio_reg;
2105 
2106         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2107                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2108                 return -EINVAL;
2109         }
2110 
2111         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2112         /* read GPIO and mask except the float bits */
2113         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2114 
2115         switch (mode) {
2116         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2117                 DP(NETIF_MSG_LINK,
2118                    "Set GPIO %d (shift %d) -> output low\n",
2119                    gpio_num, gpio_shift);
2120                 /* clear FLOAT and set CLR */
2121                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2122                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2123                 break;
2124 
2125         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2126                 DP(NETIF_MSG_LINK,
2127                    "Set GPIO %d (shift %d) -> output high\n",
2128                    gpio_num, gpio_shift);
2129                 /* clear FLOAT and set SET */
2130                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2131                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2132                 break;
2133 
2134         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2135                 DP(NETIF_MSG_LINK,
2136                    "Set GPIO %d (shift %d) -> input\n",
2137                    gpio_num, gpio_shift);
2138                 /* set FLOAT */
2139                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2140                 break;
2141 
2142         default:
2143                 break;
2144         }
2145 
2146         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2147         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2148 
2149         return 0;
2150 }
2151 
2152 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2153 {
2154         u32 gpio_reg = 0;
2155         int rc = 0;
2156 
2157         /* Any port swapping should be handled by caller. */
2158 
2159         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2160         /* read GPIO and mask except the float bits */
2161         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2162         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2163         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2164         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2165 
2166         switch (mode) {
2167         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2168                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2169                 /* set CLR */
2170                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2171                 break;
2172 
2173         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2174                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2175                 /* set SET */
2176                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2177                 break;
2178 
2179         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2180                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2181                 /* set FLOAT */
2182                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2183                 break;
2184 
2185         default:
2186                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2187                 rc = -EINVAL;
2188                 break;
2189         }
2190 
2191         if (rc == 0)
2192                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2193 
2194         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2195 
2196         return rc;
2197 }
2198 
2199 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2200 {
2201         /* The GPIO should be swapped if swap register is set and active */
2202         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2203                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2204         int gpio_shift = gpio_num +
2205                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2206         u32 gpio_mask = (1 << gpio_shift);
2207         u32 gpio_reg;
2208 
2209         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2210                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2211                 return -EINVAL;
2212         }
2213 
2214         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2215         /* read GPIO int */
2216         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2217 
2218         switch (mode) {
2219         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2220                 DP(NETIF_MSG_LINK,
2221                    "Clear GPIO INT %d (shift %d) -> output low\n",
2222                    gpio_num, gpio_shift);
2223                 /* clear SET and set CLR */
2224                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2225                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2226                 break;
2227 
2228         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2229                 DP(NETIF_MSG_LINK,
2230                    "Set GPIO INT %d (shift %d) -> output high\n",
2231                    gpio_num, gpio_shift);
2232                 /* clear CLR and set SET */
2233                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2234                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2235                 break;
2236 
2237         default:
2238                 break;
2239         }
2240 
2241         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2242         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2243 
2244         return 0;
2245 }
2246 
2247 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2248 {
2249         u32 spio_reg;
2250 
2251         /* Only 2 SPIOs are configurable */
2252         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2253                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2254                 return -EINVAL;
2255         }
2256 
2257         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2258         /* read SPIO and mask except the float bits */
2259         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2260 
2261         switch (mode) {
2262         case MISC_SPIO_OUTPUT_LOW:
2263                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2264                 /* clear FLOAT and set CLR */
2265                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2266                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2267                 break;
2268 
2269         case MISC_SPIO_OUTPUT_HIGH:
2270                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2271                 /* clear FLOAT and set SET */
2272                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2273                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2274                 break;
2275 
2276         case MISC_SPIO_INPUT_HI_Z:
2277                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2278                 /* set FLOAT */
2279                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2280                 break;
2281 
2282         default:
2283                 break;
2284         }
2285 
2286         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2287         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2288 
2289         return 0;
2290 }
2291 
2292 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2293 {
2294         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2295 
2296         bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2297                                            ADVERTISED_Pause);
2298         switch (bp->link_vars.ieee_fc &
2299                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2300         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2301                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2302                                                   ADVERTISED_Pause);
2303                 break;
2304 
2305         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2306                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2307                 break;
2308 
2309         default:
2310                 break;
2311         }
2312 }
2313 
2314 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2315 {
2316         /* Initialize link parameters structure variables
2317          * It is recommended to turn off RX FC for jumbo frames
2318          *  for better performance
2319          */
2320         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2321                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2322         else
2323                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2324 }
2325 
2326 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2327 {
2328         u32 pause_enabled = 0;
2329 
2330         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2331                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2332                         pause_enabled = 1;
2333 
2334                 REG_WR(bp, BAR_USTRORM_INTMEM +
2335                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2336                        pause_enabled);
2337         }
2338 
2339         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2340            pause_enabled ? "enabled" : "disabled");
2341 }
2342 
2343 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2344 {
2345         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2346         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2347 
2348         if (!BP_NOMCP(bp)) {
2349                 bnx2x_set_requested_fc(bp);
2350                 bnx2x_acquire_phy_lock(bp);
2351 
2352                 if (load_mode == LOAD_DIAG) {
2353                         struct link_params *lp = &bp->link_params;
2354                         lp->loopback_mode = LOOPBACK_XGXS;
2355                         /* Prefer doing PHY loopback at highest speed */
2356                         if (lp->req_line_speed[cfx_idx] < SPEED_20000) {
2357                                 if (lp->speed_cap_mask[cfx_idx] &
2358                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
2359                                         lp->req_line_speed[cfx_idx] =
2360                                         SPEED_20000;
2361                                 else if (lp->speed_cap_mask[cfx_idx] &
2362                                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2363                                                 lp->req_line_speed[cfx_idx] =
2364                                                 SPEED_10000;
2365                                 else
2366                                         lp->req_line_speed[cfx_idx] =
2367                                         SPEED_1000;
2368                         }
2369                 }
2370 
2371                 if (load_mode == LOAD_LOOPBACK_EXT) {
2372                         struct link_params *lp = &bp->link_params;
2373                         lp->loopback_mode = LOOPBACK_EXT;
2374                 }
2375 
2376                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2377 
2378                 bnx2x_release_phy_lock(bp);
2379 
2380                 bnx2x_init_dropless_fc(bp);
2381 
2382                 bnx2x_calc_fc_adv(bp);
2383 
2384                 if (bp->link_vars.link_up) {
2385                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2386                         bnx2x_link_report(bp);
2387                 }
2388                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2389                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2390                 return rc;
2391         }
2392         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2393         return -EINVAL;
2394 }
2395 
2396 void bnx2x_link_set(struct bnx2x *bp)
2397 {
2398         if (!BP_NOMCP(bp)) {
2399                 bnx2x_acquire_phy_lock(bp);
2400                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2401                 bnx2x_release_phy_lock(bp);
2402 
2403                 bnx2x_init_dropless_fc(bp);
2404 
2405                 bnx2x_calc_fc_adv(bp);
2406         } else
2407                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2408 }
2409 
2410 static void bnx2x__link_reset(struct bnx2x *bp)
2411 {
2412         if (!BP_NOMCP(bp)) {
2413                 bnx2x_acquire_phy_lock(bp);
2414                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2415                 bnx2x_release_phy_lock(bp);
2416         } else
2417                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2418 }
2419 
2420 void bnx2x_force_link_reset(struct bnx2x *bp)
2421 {
2422         bnx2x_acquire_phy_lock(bp);
2423         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2424         bnx2x_release_phy_lock(bp);
2425 }
2426 
2427 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2428 {
2429         u8 rc = 0;
2430 
2431         if (!BP_NOMCP(bp)) {
2432                 bnx2x_acquire_phy_lock(bp);
2433                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2434                                      is_serdes);
2435                 bnx2x_release_phy_lock(bp);
2436         } else
2437                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2438 
2439         return rc;
2440 }
2441 
2442 /* Calculates the sum of vn_min_rates.
2443    It's needed for further normalizing of the min_rates.
2444    Returns:
2445      sum of vn_min_rates.
2446        or
2447      0 - if all the min_rates are 0.
2448      In the later case fairness algorithm should be deactivated.
2449      If not all min_rates are zero then those that are zeroes will be set to 1.
2450  */
2451 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2452                                       struct cmng_init_input *input)
2453 {
2454         int all_zero = 1;
2455         int vn;
2456 
2457         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2458                 u32 vn_cfg = bp->mf_config[vn];
2459                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2460                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2461 
2462                 /* Skip hidden vns */
2463                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2464                         vn_min_rate = 0;
2465                 /* If min rate is zero - set it to 1 */
2466                 else if (!vn_min_rate)
2467                         vn_min_rate = DEF_MIN_RATE;
2468                 else
2469                         all_zero = 0;
2470 
2471                 input->vnic_min_rate[vn] = vn_min_rate;
2472         }
2473 
2474         /* if ETS or all min rates are zeros - disable fairness */
2475         if (BNX2X_IS_ETS_ENABLED(bp)) {
2476                 input->flags.cmng_enables &=
2477                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2478                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2479         } else if (all_zero) {
2480                 input->flags.cmng_enables &=
2481                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2482                 DP(NETIF_MSG_IFUP,
2483                    "All MIN values are zeroes fairness will be disabled\n");
2484         } else
2485                 input->flags.cmng_enables |=
2486                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2487 }
2488 
2489 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2490                                     struct cmng_init_input *input)
2491 {
2492         u16 vn_max_rate;
2493         u32 vn_cfg = bp->mf_config[vn];
2494 
2495         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2496                 vn_max_rate = 0;
2497         else {
2498                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2499 
2500                 if (IS_MF_PERCENT_BW(bp)) {
2501                         /* maxCfg in percents of linkspeed */
2502                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2503                 } else /* SD modes */
2504                         /* maxCfg is absolute in 100Mb units */
2505                         vn_max_rate = maxCfg * 100;
2506         }
2507 
2508         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2509 
2510         input->vnic_max_rate[vn] = vn_max_rate;
2511 }
2512 
2513 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2514 {
2515         if (CHIP_REV_IS_SLOW(bp))
2516                 return CMNG_FNS_NONE;
2517         if (IS_MF(bp))
2518                 return CMNG_FNS_MINMAX;
2519 
2520         return CMNG_FNS_NONE;
2521 }
2522 
2523 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2524 {
2525         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2526 
2527         if (BP_NOMCP(bp))
2528                 return; /* what should be the default value in this case */
2529 
2530         /* For 2 port configuration the absolute function number formula
2531          * is:
2532          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2533          *
2534          *      and there are 4 functions per port
2535          *
2536          * For 4 port configuration it is
2537          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2538          *
2539          *      and there are 2 functions per port
2540          */
2541         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2542                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2543 
2544                 if (func >= E1H_FUNC_MAX)
2545                         break;
2546 
2547                 bp->mf_config[vn] =
2548                         MF_CFG_RD(bp, func_mf_config[func].config);
2549         }
2550         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2551                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2552                 bp->flags |= MF_FUNC_DIS;
2553         } else {
2554                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2555                 bp->flags &= ~MF_FUNC_DIS;
2556         }
2557 }
2558 
2559 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2560 {
2561         struct cmng_init_input input;
2562         memset(&input, 0, sizeof(struct cmng_init_input));
2563 
2564         input.port_rate = bp->link_vars.line_speed;
2565 
2566         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2567                 int vn;
2568 
2569                 /* read mf conf from shmem */
2570                 if (read_cfg)
2571                         bnx2x_read_mf_cfg(bp);
2572 
2573                 /* vn_weight_sum and enable fairness if not 0 */
2574                 bnx2x_calc_vn_min(bp, &input);
2575 
2576                 /* calculate and set min-max rate for each vn */
2577                 if (bp->port.pmf)
2578                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2579                                 bnx2x_calc_vn_max(bp, vn, &input);
2580 
2581                 /* always enable rate shaping and fairness */
2582                 input.flags.cmng_enables |=
2583                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2584 
2585                 bnx2x_init_cmng(&input, &bp->cmng);
2586                 return;
2587         }
2588 
2589         /* rate shaping and fairness are disabled */
2590         DP(NETIF_MSG_IFUP,
2591            "rate shaping and fairness are disabled\n");
2592 }
2593 
2594 static void storm_memset_cmng(struct bnx2x *bp,
2595                               struct cmng_init *cmng,
2596                               u8 port)
2597 {
2598         int vn;
2599         size_t size = sizeof(struct cmng_struct_per_port);
2600 
2601         u32 addr = BAR_XSTRORM_INTMEM +
2602                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2603 
2604         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2605 
2606         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2607                 int func = func_by_vn(bp, vn);
2608 
2609                 addr = BAR_XSTRORM_INTMEM +
2610                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2611                 size = sizeof(struct rate_shaping_vars_per_vn);
2612                 __storm_memset_struct(bp, addr, size,
2613                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2614 
2615                 addr = BAR_XSTRORM_INTMEM +
2616                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2617                 size = sizeof(struct fairness_vars_per_vn);
2618                 __storm_memset_struct(bp, addr, size,
2619                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2620         }
2621 }
2622 
2623 /* init cmng mode in HW according to local configuration */
2624 void bnx2x_set_local_cmng(struct bnx2x *bp)
2625 {
2626         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2627 
2628         if (cmng_fns != CMNG_FNS_NONE) {
2629                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2630                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2631         } else {
2632                 /* rate shaping and fairness are disabled */
2633                 DP(NETIF_MSG_IFUP,
2634                    "single function mode without fairness\n");
2635         }
2636 }
2637 
2638 /* This function is called upon link interrupt */
2639 static void bnx2x_link_attn(struct bnx2x *bp)
2640 {
2641         /* Make sure that we are synced with the current statistics */
2642         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2643 
2644         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2645 
2646         bnx2x_init_dropless_fc(bp);
2647 
2648         if (bp->link_vars.link_up) {
2649 
2650                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2651                         struct host_port_stats *pstats;
2652 
2653                         pstats = bnx2x_sp(bp, port_stats);
2654                         /* reset old mac stats */
2655                         memset(&(pstats->mac_stx[0]), 0,
2656                                sizeof(struct mac_stx));
2657                 }
2658                 if (bp->state == BNX2X_STATE_OPEN)
2659                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2660         }
2661 
2662         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2663                 bnx2x_set_local_cmng(bp);
2664 
2665         __bnx2x_link_report(bp);
2666 
2667         if (IS_MF(bp))
2668                 bnx2x_link_sync_notify(bp);
2669 }
2670 
2671 void bnx2x__link_status_update(struct bnx2x *bp)
2672 {
2673         if (bp->state != BNX2X_STATE_OPEN)
2674                 return;
2675 
2676         /* read updated dcb configuration */
2677         if (IS_PF(bp)) {
2678                 bnx2x_dcbx_pmf_update(bp);
2679                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2680                 if (bp->link_vars.link_up)
2681                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2682                 else
2683                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2684                         /* indicate link status */
2685                 bnx2x_link_report(bp);
2686 
2687         } else { /* VF */
2688                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2689                                           SUPPORTED_10baseT_Full |
2690                                           SUPPORTED_100baseT_Half |
2691                                           SUPPORTED_100baseT_Full |
2692                                           SUPPORTED_1000baseT_Full |
2693                                           SUPPORTED_2500baseX_Full |
2694                                           SUPPORTED_10000baseT_Full |
2695                                           SUPPORTED_TP |
2696                                           SUPPORTED_FIBRE |
2697                                           SUPPORTED_Autoneg |
2698                                           SUPPORTED_Pause |
2699                                           SUPPORTED_Asym_Pause);
2700                 bp->port.advertising[0] = bp->port.supported[0];
2701 
2702                 bp->link_params.bp = bp;
2703                 bp->link_params.port = BP_PORT(bp);
2704                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2705                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2706                 bp->link_params.req_line_speed[0] = SPEED_10000;
2707                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2708                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2709                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2710                 bp->link_vars.line_speed = SPEED_10000;
2711                 bp->link_vars.link_status =
2712                         (LINK_STATUS_LINK_UP |
2713                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2714                 bp->link_vars.link_up = 1;
2715                 bp->link_vars.duplex = DUPLEX_FULL;
2716                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2717                 __bnx2x_link_report(bp);
2718 
2719                 bnx2x_sample_bulletin(bp);
2720 
2721                 /* if bulletin board did not have an update for link status
2722                  * __bnx2x_link_report will report current status
2723                  * but it will NOT duplicate report in case of already reported
2724                  * during sampling bulletin board.
2725                  */
2726                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2727         }
2728 }
2729 
2730 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2731                                   u16 vlan_val, u8 allowed_prio)
2732 {
2733         struct bnx2x_func_state_params func_params = {NULL};
2734         struct bnx2x_func_afex_update_params *f_update_params =
2735                 &func_params.params.afex_update;
2736 
2737         func_params.f_obj = &bp->func_obj;
2738         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2739 
2740         /* no need to wait for RAMROD completion, so don't
2741          * set RAMROD_COMP_WAIT flag
2742          */
2743 
2744         f_update_params->vif_id = vifid;
2745         f_update_params->afex_default_vlan = vlan_val;
2746         f_update_params->allowed_priorities = allowed_prio;
2747 
2748         /* if ramrod can not be sent, response to MCP immediately */
2749         if (bnx2x_func_state_change(bp, &func_params) < 0)
2750                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2751 
2752         return 0;
2753 }
2754 
2755 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2756                                           u16 vif_index, u8 func_bit_map)
2757 {
2758         struct bnx2x_func_state_params func_params = {NULL};
2759         struct bnx2x_func_afex_viflists_params *update_params =
2760                 &func_params.params.afex_viflists;
2761         int rc;
2762         u32 drv_msg_code;
2763 
2764         /* validate only LIST_SET and LIST_GET are received from switch */
2765         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2766                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2767                           cmd_type);
2768 
2769         func_params.f_obj = &bp->func_obj;
2770         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2771 
2772         /* set parameters according to cmd_type */
2773         update_params->afex_vif_list_command = cmd_type;
2774         update_params->vif_list_index = vif_index;
2775         update_params->func_bit_map =
2776                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2777         update_params->func_to_clear = 0;
2778         drv_msg_code =
2779                 (cmd_type == VIF_LIST_RULE_GET) ?
2780                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2781                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2782 
2783         /* if ramrod can not be sent, respond to MCP immediately for
2784          * SET and GET requests (other are not triggered from MCP)
2785          */
2786         rc = bnx2x_func_state_change(bp, &func_params);
2787         if (rc < 0)
2788                 bnx2x_fw_command(bp, drv_msg_code, 0);
2789 
2790         return 0;
2791 }
2792 
2793 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2794 {
2795         struct afex_stats afex_stats;
2796         u32 func = BP_ABS_FUNC(bp);
2797         u32 mf_config;
2798         u16 vlan_val;
2799         u32 vlan_prio;
2800         u16 vif_id;
2801         u8 allowed_prio;
2802         u8 vlan_mode;
2803         u32 addr_to_write, vifid, addrs, stats_type, i;
2804 
2805         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2806                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2807                 DP(BNX2X_MSG_MCP,
2808                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2809                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2810         }
2811 
2812         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2813                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2814                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2815                 DP(BNX2X_MSG_MCP,
2816                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2817                    vifid, addrs);
2818                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2819                                                addrs);
2820         }
2821 
2822         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2823                 addr_to_write = SHMEM2_RD(bp,
2824                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2825                 stats_type = SHMEM2_RD(bp,
2826                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2827 
2828                 DP(BNX2X_MSG_MCP,
2829                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2830                    addr_to_write);
2831 
2832                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2833 
2834                 /* write response to scratchpad, for MCP */
2835                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2836                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2837                                *(((u32 *)(&afex_stats))+i));
2838 
2839                 /* send ack message to MCP */
2840                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2841         }
2842 
2843         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2844                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2845                 bp->mf_config[BP_VN(bp)] = mf_config;
2846                 DP(BNX2X_MSG_MCP,
2847                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2848                    mf_config);
2849 
2850                 /* if VIF_SET is "enabled" */
2851                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2852                         /* set rate limit directly to internal RAM */
2853                         struct cmng_init_input cmng_input;
2854                         struct rate_shaping_vars_per_vn m_rs_vn;
2855                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2856                         u32 addr = BAR_XSTRORM_INTMEM +
2857                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2858 
2859                         bp->mf_config[BP_VN(bp)] = mf_config;
2860 
2861                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2862                         m_rs_vn.vn_counter.rate =
2863                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2864                         m_rs_vn.vn_counter.quota =
2865                                 (m_rs_vn.vn_counter.rate *
2866                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2867 
2868                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2869 
2870                         /* read relevant values from mf_cfg struct in shmem */
2871                         vif_id =
2872                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2873                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2874                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2875                         vlan_val =
2876                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2877                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2878                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2879                         vlan_prio = (mf_config &
2880                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2881                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2882                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2883                         vlan_mode =
2884                                 (MF_CFG_RD(bp,
2885                                            func_mf_config[func].afex_config) &
2886                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2887                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2888                         allowed_prio =
2889                                 (MF_CFG_RD(bp,
2890                                            func_mf_config[func].afex_config) &
2891                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2892                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2893 
2894                         /* send ramrod to FW, return in case of failure */
2895                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2896                                                    allowed_prio))
2897                                 return;
2898 
2899                         bp->afex_def_vlan_tag = vlan_val;
2900                         bp->afex_vlan_mode = vlan_mode;
2901                 } else {
2902                         /* notify link down because BP->flags is disabled */
2903                         bnx2x_link_report(bp);
2904 
2905                         /* send INVALID VIF ramrod to FW */
2906                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2907 
2908                         /* Reset the default afex VLAN */
2909                         bp->afex_def_vlan_tag = -1;
2910                 }
2911         }
2912 }
2913 
2914 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2915 {
2916         struct bnx2x_func_switch_update_params *switch_update_params;
2917         struct bnx2x_func_state_params func_params;
2918 
2919         memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2920         switch_update_params = &func_params.params.switch_update;
2921         func_params.f_obj = &bp->func_obj;
2922         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2923 
2924         if (IS_MF_UFP(bp) || IS_MF_BD(bp)) {
2925                 int func = BP_ABS_FUNC(bp);
2926                 u32 val;
2927 
2928                 /* Re-learn the S-tag from shmem */
2929                 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2930                                 FUNC_MF_CFG_E1HOV_TAG_MASK;
2931                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2932                         bp->mf_ov = val;
2933                 } else {
2934                         BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2935                         goto fail;
2936                 }
2937 
2938                 /* Configure new S-tag in LLH */
2939                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2940                        bp->mf_ov);
2941 
2942                 /* Send Ramrod to update FW of change */
2943                 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2944                           &switch_update_params->changes);
2945                 switch_update_params->vlan = bp->mf_ov;
2946 
2947                 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2948                         BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2949                                   bp->mf_ov);
2950                         goto fail;
2951                 } else {
2952                         DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n",
2953                            bp->mf_ov);
2954                 }
2955         } else {
2956                 goto fail;
2957         }
2958 
2959         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2960         return;
2961 fail:
2962         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2963 }
2964 
2965 static void bnx2x_pmf_update(struct bnx2x *bp)
2966 {
2967         int port = BP_PORT(bp);
2968         u32 val;
2969 
2970         bp->port.pmf = 1;
2971         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2972 
2973         /*
2974          * We need the mb() to ensure the ordering between the writing to
2975          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2976          */
2977         smp_mb();
2978 
2979         /* queue a periodic task */
2980         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2981 
2982         bnx2x_dcbx_pmf_update(bp);
2983 
2984         /* enable nig attention */
2985         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2986         if (bp->common.int_block == INT_BLOCK_HC) {
2987                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2988                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2989         } else if (!CHIP_IS_E1x(bp)) {
2990                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2991                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2992         }
2993 
2994         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2995 }
2996 
2997 /* end of Link */
2998 
2999 /* slow path */
3000 
3001 /*
3002  * General service functions
3003  */
3004 
3005 /* send the MCP a request, block until there is a reply */
3006 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
3007 {
3008         int mb_idx = BP_FW_MB_IDX(bp);
3009         u32 seq;
3010         u32 rc = 0;
3011         u32 cnt = 1;
3012         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3013 
3014         mutex_lock(&bp->fw_mb_mutex);
3015         seq = ++bp->fw_seq;
3016         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3017         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3018 
3019         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3020                         (command | seq), param);
3021 
3022         do {
3023                 /* let the FW do it's magic ... */
3024                 msleep(delay);
3025 
3026                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
3027 
3028                 /* Give the FW up to 5 second (500*10ms) */
3029         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
3030 
3031         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3032            cnt*delay, rc, seq);
3033 
3034         /* is this a reply to our command? */
3035         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3036                 rc &= FW_MSG_CODE_MASK;
3037         else {
3038                 /* FW BUG! */
3039                 BNX2X_ERR("FW failed to respond!\n");
3040                 bnx2x_fw_dump(bp);
3041                 rc = 0;
3042         }
3043         mutex_unlock(&bp->fw_mb_mutex);
3044 
3045         return rc;
3046 }
3047 
3048 static void storm_memset_func_cfg(struct bnx2x *bp,
3049                                  struct tstorm_eth_function_common_config *tcfg,
3050                                  u16 abs_fid)
3051 {
3052         size_t size = sizeof(struct tstorm_eth_function_common_config);
3053 
3054         u32 addr = BAR_TSTRORM_INTMEM +
3055                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3056 
3057         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3058 }
3059 
3060 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3061 {
3062         if (CHIP_IS_E1x(bp)) {
3063                 struct tstorm_eth_function_common_config tcfg = {0};
3064 
3065                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3066         }
3067 
3068         /* Enable the function in the FW */
3069         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3070         storm_memset_func_en(bp, p->func_id, 1);
3071 
3072         /* spq */
3073         if (p->spq_active) {
3074                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3075                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3076                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3077         }
3078 }
3079 
3080 /**
3081  * bnx2x_get_common_flags - Return common flags
3082  *
3083  * @bp          device handle
3084  * @fp          queue handle
3085  * @zero_stats  TRUE if statistics zeroing is needed
3086  *
3087  * Return the flags that are common for the Tx-only and not normal connections.
3088  */
3089 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3090                                             struct bnx2x_fastpath *fp,
3091                                             bool zero_stats)
3092 {
3093         unsigned long flags = 0;
3094 
3095         /* PF driver will always initialize the Queue to an ACTIVE state */
3096         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3097 
3098         /* tx only connections collect statistics (on the same index as the
3099          * parent connection). The statistics are zeroed when the parent
3100          * connection is initialized.
3101          */
3102 
3103         __set_bit(BNX2X_Q_FLG_STATS, &flags);
3104         if (zero_stats)
3105                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3106 
3107         if (bp->flags & TX_SWITCHING)
3108                 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3109 
3110         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3111         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3112 
3113 #ifdef BNX2X_STOP_ON_ERROR
3114         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3115 #endif
3116 
3117         return flags;
3118 }
3119 
3120 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3121                                        struct bnx2x_fastpath *fp,
3122                                        bool leading)
3123 {
3124         unsigned long flags = 0;
3125 
3126         /* calculate other queue flags */
3127         if (IS_MF_SD(bp))
3128                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3129 
3130         if (IS_FCOE_FP(fp)) {
3131                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3132                 /* For FCoE - force usage of default priority (for afex) */
3133                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3134         }
3135 
3136         if (fp->mode != TPA_MODE_DISABLED) {
3137                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3138                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3139                 if (fp->mode == TPA_MODE_GRO)
3140                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3141         }
3142 
3143         if (leading) {
3144                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3145                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3146         }
3147 
3148         /* Always set HW VLAN stripping */
3149         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3150 
3151         /* configure silent vlan removal */
3152         if (IS_MF_AFEX(bp))
3153                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3154 
3155         return flags | bnx2x_get_common_flags(bp, fp, true);
3156 }
3157 
3158 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3159         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3160         u8 cos)
3161 {
3162         gen_init->stat_id = bnx2x_stats_id(fp);
3163         gen_init->spcl_id = fp->cl_id;
3164 
3165         /* Always use mini-jumbo MTU for FCoE L2 ring */
3166         if (IS_FCOE_FP(fp))
3167                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3168         else
3169                 gen_init->mtu = bp->dev->mtu;
3170 
3171         gen_init->cos = cos;
3172 
3173         gen_init->fp_hsi = ETH_FP_HSI_VERSION;
3174 }
3175 
3176 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3177         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3178         struct bnx2x_rxq_setup_params *rxq_init)
3179 {
3180         u8 max_sge = 0;
3181         u16 sge_sz = 0;
3182         u16 tpa_agg_size = 0;
3183 
3184         if (fp->mode != TPA_MODE_DISABLED) {
3185                 pause->sge_th_lo = SGE_TH_LO(bp);
3186                 pause->sge_th_hi = SGE_TH_HI(bp);
3187 
3188                 /* validate SGE ring has enough to cross high threshold */
3189                 WARN_ON(bp->dropless_fc &&
3190                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3191                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3192 
3193                 tpa_agg_size = TPA_AGG_SIZE;
3194                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3195                         SGE_PAGE_SHIFT;
3196                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3197                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3198                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3199         }
3200 
3201         /* pause - not for e1 */
3202         if (!CHIP_IS_E1(bp)) {
3203                 pause->bd_th_lo = BD_TH_LO(bp);
3204                 pause->bd_th_hi = BD_TH_HI(bp);
3205 
3206                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3207                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3208                 /*
3209                  * validate that rings have enough entries to cross
3210                  * high thresholds
3211                  */
3212                 WARN_ON(bp->dropless_fc &&
3213                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3214                                 bp->rx_ring_size);
3215                 WARN_ON(bp->dropless_fc &&
3216                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3217                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3218 
3219                 pause->pri_map = 1;
3220         }
3221 
3222         /* rxq setup */
3223         rxq_init->dscr_map = fp->rx_desc_mapping;
3224         rxq_init->sge_map = fp->rx_sge_mapping;
3225         rxq_init->rcq_map = fp->rx_comp_mapping;
3226         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3227 
3228         /* This should be a maximum number of data bytes that may be
3229          * placed on the BD (not including paddings).
3230          */
3231         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3232                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3233 
3234         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3235         rxq_init->tpa_agg_sz = tpa_agg_size;
3236         rxq_init->sge_buf_sz = sge_sz;
3237         rxq_init->max_sges_pkt = max_sge;
3238         rxq_init->rss_engine_id = BP_FUNC(bp);
3239         rxq_init->mcast_engine_id = BP_FUNC(bp);
3240 
3241         /* Maximum number or simultaneous TPA aggregation for this Queue.
3242          *
3243          * For PF Clients it should be the maximum available number.
3244          * VF driver(s) may want to define it to a smaller value.
3245          */
3246         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3247 
3248         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3249         rxq_init->fw_sb_id = fp->fw_sb_id;
3250 
3251         if (IS_FCOE_FP(fp))
3252                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3253         else
3254                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3255         /* configure silent vlan removal
3256          * if multi function mode is afex, then mask default vlan
3257          */
3258         if (IS_MF_AFEX(bp)) {
3259                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3260                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3261         }
3262 }
3263 
3264 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3265         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3266         u8 cos)
3267 {
3268         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3269         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3270         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3271         txq_init->fw_sb_id = fp->fw_sb_id;
3272 
3273         /*
3274          * set the tss leading client id for TX classification ==
3275          * leading RSS client id
3276          */
3277         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3278 
3279         if (IS_FCOE_FP(fp)) {
3280                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3281                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3282         }
3283 }
3284 
3285 static void bnx2x_pf_init(struct bnx2x *bp)
3286 {
3287         struct bnx2x_func_init_params func_init = {0};
3288         struct event_ring_data eq_data = { {0} };
3289 
3290         if (!CHIP_IS_E1x(bp)) {
3291                 /* reset IGU PF statistics: MSIX + ATTN */
3292                 /* PF */
3293                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3294                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3295                            (CHIP_MODE_IS_4_PORT(bp) ?
3296                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3297                 /* ATTN */
3298                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3299                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3300                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3301                            (CHIP_MODE_IS_4_PORT(bp) ?
3302                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3303         }
3304 
3305         func_init.spq_active = true;
3306         func_init.pf_id = BP_FUNC(bp);
3307         func_init.func_id = BP_FUNC(bp);
3308         func_init.spq_map = bp->spq_mapping;
3309         func_init.spq_prod = bp->spq_prod_idx;
3310 
3311         bnx2x_func_init(bp, &func_init);
3312 
3313         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3314 
3315         /*
3316          * Congestion management values depend on the link rate
3317          * There is no active link so initial link rate is set to 10 Gbps.
3318          * When the link comes up The congestion management values are
3319          * re-calculated according to the actual link rate.
3320          */
3321         bp->link_vars.line_speed = SPEED_10000;
3322         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3323 
3324         /* Only the PMF sets the HW */
3325         if (bp->port.pmf)
3326                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3327 
3328         /* init Event Queue - PCI bus guarantees correct endianity*/
3329         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3330         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3331         eq_data.producer = bp->eq_prod;
3332         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3333         eq_data.sb_id = DEF_SB_ID;
3334         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3335 }
3336 
3337 static void bnx2x_e1h_disable(struct bnx2x *bp)
3338 {
3339         int port = BP_PORT(bp);
3340 
3341         bnx2x_tx_disable(bp);
3342 
3343         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3344 }
3345 
3346 static void bnx2x_e1h_enable(struct bnx2x *bp)
3347 {
3348         int port = BP_PORT(bp);
3349 
3350         if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3351                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3352 
3353         /* Tx queue should be only re-enabled */
3354         netif_tx_wake_all_queues(bp->dev);
3355 
3356         /*
3357          * Should not call netif_carrier_on since it will be called if the link
3358          * is up when checking for link state
3359          */
3360 }
3361 
3362 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3363 
3364 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3365 {
3366         struct eth_stats_info *ether_stat =
3367                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3368         struct bnx2x_vlan_mac_obj *mac_obj =
3369                 &bp->sp_objs->mac_obj;
3370         int i;
3371 
3372         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3373                 ETH_STAT_INFO_VERSION_LEN);
3374 
3375         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3376          * mac_local field in ether_stat struct. The base address is offset by 2
3377          * bytes to account for the field being 8 bytes but a mac address is
3378          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3379          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3380          * allocated by the ether_stat struct, so the macs will land in their
3381          * proper positions.
3382          */
3383         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3384                 memset(ether_stat->mac_local + i, 0,
3385                        sizeof(ether_stat->mac_local[0]));
3386         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3387                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3388                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3389                                 ETH_ALEN);
3390         ether_stat->mtu_size = bp->dev->mtu;
3391         if (bp->dev->features & NETIF_F_RXCSUM)
3392                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3393         if (bp->dev->features & NETIF_F_TSO)
3394                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3395         ether_stat->feature_flags |= bp->common.boot_mode;
3396 
3397         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3398 
3399         ether_stat->txq_size = bp->tx_ring_size;
3400         ether_stat->rxq_size = bp->rx_ring_size;
3401 
3402 #ifdef CONFIG_BNX2X_SRIOV
3403         ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3404 #endif
3405 }
3406 
3407 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3408 {
3409         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3410         struct fcoe_stats_info *fcoe_stat =
3411                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3412 
3413         if (!CNIC_LOADED(bp))
3414                 return;
3415 
3416         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3417 
3418         fcoe_stat->qos_priority =
3419                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3420 
3421         /* insert FCoE stats from ramrod response */
3422         if (!NO_FCOE(bp)) {
3423                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3424                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3425                         tstorm_queue_statistics;
3426 
3427                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3428                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3429                         xstorm_queue_statistics;
3430 
3431                 struct fcoe_statistics_params *fw_fcoe_stat =
3432                         &bp->fw_stats_data->fcoe;
3433 
3434                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3435                           fcoe_stat->rx_bytes_lo,
3436                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3437 
3438                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3439                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3440                           fcoe_stat->rx_bytes_lo,
3441                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3442 
3443                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3444                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3445                           fcoe_stat->rx_bytes_lo,
3446                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3447 
3448                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3449                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3450                           fcoe_stat->rx_bytes_lo,
3451                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3452 
3453                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3454                           fcoe_stat->rx_frames_lo,
3455                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3456 
3457                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3458                           fcoe_stat->rx_frames_lo,
3459                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3460 
3461                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3462                           fcoe_stat->rx_frames_lo,
3463                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3464 
3465                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3466                           fcoe_stat->rx_frames_lo,
3467                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3468 
3469                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3470                           fcoe_stat->tx_bytes_lo,
3471                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3472 
3473                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3474                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3475                           fcoe_stat->tx_bytes_lo,
3476                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3477 
3478                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3479                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3480                           fcoe_stat->tx_bytes_lo,
3481                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3482 
3483                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3484                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3485                           fcoe_stat->tx_bytes_lo,
3486                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3487 
3488                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3489                           fcoe_stat->tx_frames_lo,
3490                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3491 
3492                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3493                           fcoe_stat->tx_frames_lo,
3494                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3495 
3496                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3497                           fcoe_stat->tx_frames_lo,
3498                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3499 
3500                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3501                           fcoe_stat->tx_frames_lo,
3502                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3503         }
3504 
3505         /* ask L5 driver to add data to the struct */
3506         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3507 }
3508 
3509 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3510 {
3511         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3512         struct iscsi_stats_info *iscsi_stat =
3513                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3514 
3515         if (!CNIC_LOADED(bp))
3516                 return;
3517 
3518         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3519                ETH_ALEN);
3520 
3521         iscsi_stat->qos_priority =
3522                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3523 
3524         /* ask L5 driver to add data to the struct */
3525         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3526 }
3527 
3528 /* called due to MCP event (on pmf):
3529  *      reread new bandwidth configuration
3530  *      configure FW
3531  *      notify others function about the change
3532  */
3533 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3534 {
3535         if (bp->link_vars.link_up) {
3536                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3537                 bnx2x_link_sync_notify(bp);
3538         }
3539         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3540 }
3541 
3542 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3543 {
3544         bnx2x_config_mf_bw(bp);
3545         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3546 }
3547 
3548 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3549 {
3550         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3551         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3552 }
3553 
3554 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH        (20)
3555 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT         (25)
3556 
3557 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3558 {
3559         enum drv_info_opcode op_code;
3560         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3561         bool release = false;
3562         int wait;
3563 
3564         /* if drv_info version supported by MFW doesn't match - send NACK */
3565         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3566                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3567                 return;
3568         }
3569 
3570         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3571                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3572 
3573         /* Must prevent other flows from accessing drv_info_to_mcp */
3574         mutex_lock(&bp->drv_info_mutex);
3575 
3576         memset(&bp->slowpath->drv_info_to_mcp, 0,
3577                sizeof(union drv_info_to_mcp));
3578 
3579         switch (op_code) {
3580         case ETH_STATS_OPCODE:
3581                 bnx2x_drv_info_ether_stat(bp);
3582                 break;
3583         case FCOE_STATS_OPCODE:
3584                 bnx2x_drv_info_fcoe_stat(bp);
3585                 break;
3586         case ISCSI_STATS_OPCODE:
3587                 bnx2x_drv_info_iscsi_stat(bp);
3588                 break;
3589         default:
3590                 /* if op code isn't supported - send NACK */
3591                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3592                 goto out;
3593         }
3594 
3595         /* if we got drv_info attn from MFW then these fields are defined in
3596          * shmem2 for sure
3597          */
3598         SHMEM2_WR(bp, drv_info_host_addr_lo,
3599                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3600         SHMEM2_WR(bp, drv_info_host_addr_hi,
3601                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3602 
3603         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3604 
3605         /* Since possible management wants both this and get_driver_version
3606          * need to wait until management notifies us it finished utilizing
3607          * the buffer.
3608          */
3609         if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3610                 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3611         } else if (!bp->drv_info_mng_owner) {
3612                 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3613 
3614                 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3615                         u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3616 
3617                         /* Management is done; need to clear indication */
3618                         if (indication & bit) {
3619                                 SHMEM2_WR(bp, mfw_drv_indication,
3620                                           indication & ~bit);
3621                                 release = true;
3622                                 break;
3623                         }
3624 
3625                         msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3626                 }
3627         }
3628         if (!release) {
3629                 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3630                 bp->drv_info_mng_owner = true;
3631         }
3632 
3633 out:
3634         mutex_unlock(&bp->drv_info_mutex);
3635 }
3636 
3637 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3638 {
3639         u8 vals[4];
3640         int i = 0;
3641 
3642         if (bnx2x_format) {
3643                 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3644                            &vals[0], &vals[1], &vals[2], &vals[3]);
3645                 if (i > 0)
3646                         vals[0] -= '';
3647         } else {
3648                 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3649                            &vals[0], &vals[1], &vals[2], &vals[3]);
3650         }
3651 
3652         while (i < 4)
3653                 vals[i++] = 0;
3654 
3655         return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3656 }
3657 
3658 void bnx2x_update_mng_version(struct bnx2x *bp)
3659 {
3660         u32 iscsiver = DRV_VER_NOT_LOADED;
3661         u32 fcoever = DRV_VER_NOT_LOADED;
3662         u32 ethver = DRV_VER_NOT_LOADED;
3663         int idx = BP_FW_MB_IDX(bp);
3664         u8 *version;
3665 
3666         if (!SHMEM2_HAS(bp, func_os_drv_ver))
3667                 return;
3668 
3669         mutex_lock(&bp->drv_info_mutex);
3670         /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3671         if (bp->drv_info_mng_owner)
3672                 goto out;
3673 
3674         if (bp->state != BNX2X_STATE_OPEN)
3675                 goto out;
3676 
3677         /* Parse ethernet driver version */
3678         ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3679         if (!CNIC_LOADED(bp))
3680                 goto out;
3681 
3682         /* Try getting storage driver version via cnic */
3683         memset(&bp->slowpath->drv_info_to_mcp, 0,
3684                sizeof(union drv_info_to_mcp));
3685         bnx2x_drv_info_iscsi_stat(bp);
3686         version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3687         iscsiver = bnx2x_update_mng_version_utility(version, false);
3688 
3689         memset(&bp->slowpath->drv_info_to_mcp, 0,
3690                sizeof(union drv_info_to_mcp));
3691         bnx2x_drv_info_fcoe_stat(bp);
3692         version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3693         fcoever = bnx2x_update_mng_version_utility(version, false);
3694 
3695 out:
3696         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3697         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3698         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3699 
3700         mutex_unlock(&bp->drv_info_mutex);
3701 
3702         DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3703            ethver, iscsiver, fcoever);
3704 }
3705 
3706 void bnx2x_update_mfw_dump(struct bnx2x *bp)
3707 {
3708         u32 drv_ver;
3709         u32 valid_dump;
3710 
3711         if (!SHMEM2_HAS(bp, drv_info))
3712                 return;
3713 
3714         /* Update Driver load time, possibly broken in y2038 */
3715         SHMEM2_WR(bp, drv_info.epoc, (u32)ktime_get_real_seconds());
3716 
3717         drv_ver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3718         SHMEM2_WR(bp, drv_info.drv_ver, drv_ver);
3719 
3720         SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM));
3721 
3722         /* Check & notify On-Chip dump. */
3723         valid_dump = SHMEM2_RD(bp, drv_info.valid_dump);
3724 
3725         if (valid_dump & FIRST_DUMP_VALID)
3726                 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 1st partition\n");
3727 
3728         if (valid_dump & SECOND_DUMP_VALID)
3729                 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 2nd partition\n");
3730 }
3731 
3732 static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
3733 {
3734         u32 cmd_ok, cmd_fail;
3735 
3736         /* sanity */
3737         if (event & DRV_STATUS_DCC_EVENT_MASK &&
3738             event & DRV_STATUS_OEM_EVENT_MASK) {
3739                 BNX2X_ERR("Received simultaneous events %08x\n", event);
3740                 return;
3741         }
3742 
3743         if (event & DRV_STATUS_DCC_EVENT_MASK) {
3744                 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3745                 cmd_ok = DRV_MSG_CODE_DCC_OK;
3746         } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3747                 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3748                 cmd_ok = DRV_MSG_CODE_OEM_OK;
3749         }
3750 
3751         DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3752 
3753         if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3754                      DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3755                 /* This is the only place besides the function initialization
3756                  * where the bp->flags can change so it is done without any
3757                  * locks
3758                  */
3759                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3760                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3761                         bp->flags |= MF_FUNC_DIS;
3762 
3763                         bnx2x_e1h_disable(bp);
3764                 } else {
3765                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3766                         bp->flags &= ~MF_FUNC_DIS;
3767 
3768                         bnx2x_e1h_enable(bp);
3769                 }
3770                 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3771                            DRV_STATUS_OEM_DISABLE_ENABLE_PF);
3772         }
3773 
3774         if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3775                      DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
3776                 bnx2x_config_mf_bw(bp);
3777                 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3778                            DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
3779         }
3780 
3781         /* Report results to MCP */
3782         if (event)
3783                 bnx2x_fw_command(bp, cmd_fail, 0);
3784         else
3785                 bnx2x_fw_command(bp, cmd_ok, 0);
3786 }
3787 
3788 /* must be called under the spq lock */
3789 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3790 {
3791         struct eth_spe *next_spe = bp->spq_prod_bd;
3792 
3793         if (bp->spq_prod_bd == bp->spq_last_bd) {
3794                 bp->spq_prod_bd = bp->spq;
3795                 bp->spq_prod_idx = 0;
3796                 DP(BNX2X_MSG_SP, "end of spq\n");
3797         } else {
3798                 bp->spq_prod_bd++;
3799                 bp->spq_prod_idx++;
3800         }
3801         return next_spe;
3802 }
3803 
3804 /* must be called under the spq lock */
3805 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3806 {
3807         int func = BP_FUNC(bp);
3808 
3809         /*
3810          * Make sure that BD data is updated before writing the producer:
3811          * BD data is written to the memory, the producer is read from the
3812          * memory, thus we need a full memory barrier to ensure the ordering.
3813          */
3814         mb();
3815 
3816         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3817                  bp->spq_prod_idx);
3818         mmiowb();
3819 }
3820 
3821 /**
3822  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3823  *
3824  * @cmd:        command to check
3825  * @cmd_type:   command type
3826  */
3827 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3828 {
3829         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3830             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3831             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3832             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3833             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3834             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3835             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3836                 return true;
3837         else
3838                 return false;
3839 }
3840 
3841 /**
3842  * bnx2x_sp_post - place a single command on an SP ring
3843  *
3844  * @bp:         driver handle
3845  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3846  * @cid:        SW CID the command is related to
3847  * @data_hi:    command private data address (high 32 bits)
3848  * @data_lo:    command private data address (low 32 bits)
3849  * @cmd_type:   command type (e.g. NONE, ETH)
3850  *
3851  * SP data is handled as if it's always an address pair, thus data fields are
3852  * not swapped to little endian in upper functions. Instead this function swaps
3853  * data as if it's two u32 fields.
3854  */
3855 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3856                   u32 data_hi, u32 data_lo, int cmd_type)
3857 {
3858         struct eth_spe *spe;
3859         u16 type;
3860         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3861 
3862 #ifdef BNX2X_STOP_ON_ERROR
3863         if (unlikely(bp->panic)) {
3864                 BNX2X_ERR("Can't post SP when there is panic\n");
3865                 return -EIO;
3866         }
3867 #endif
3868 
3869         spin_lock_bh(&bp->spq_lock);
3870 
3871         if (common) {
3872                 if (!atomic_read(&bp->eq_spq_left)) {
3873                         BNX2X_ERR("BUG! EQ ring full!\n");
3874                         spin_unlock_bh(&bp->spq_lock);
3875                         bnx2x_panic();
3876                         return -EBUSY;
3877                 }
3878         } else if (!atomic_read(&bp->cq_spq_left)) {
3879                         BNX2X_ERR("BUG! SPQ ring full!\n");
3880                         spin_unlock_bh(&bp->spq_lock);
3881                         bnx2x_panic();
3882                         return -EBUSY;
3883         }
3884 
3885         spe = bnx2x_sp_get_next(bp);
3886 
3887         /* CID needs port number to be encoded int it */
3888         spe->hdr.conn_and_cmd_data =
3889                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3890                                     HW_CID(bp, cid));
3891 
3892         /* In some cases, type may already contain the func-id
3893          * mainly in SRIOV related use cases, so we add it here only
3894          * if it's not already set.
3895          */
3896         if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3897                 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3898                         SPE_HDR_CONN_TYPE;
3899                 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3900                          SPE_HDR_FUNCTION_ID);
3901         } else {
3902                 type = cmd_type;
3903         }
3904 
3905         spe->hdr.type = cpu_to_le16(type);
3906 
3907         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3908         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3909 
3910         /*
3911          * It's ok if the actual decrement is issued towards the memory
3912          * somewhere between the spin_lock and spin_unlock. Thus no
3913          * more explicit memory barrier is needed.
3914          */
3915         if (common)
3916                 atomic_dec(&bp->eq_spq_left);
3917         else
3918                 atomic_dec(&bp->cq_spq_left);
3919 
3920         DP(BNX2X_MSG_SP,
3921            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3922            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3923            (u32)(U64_LO(bp->spq_mapping) +
3924            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3925            HW_CID(bp, cid), data_hi, data_lo, type,
3926            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3927 
3928         bnx2x_sp_prod_update(bp);
3929         spin_unlock_bh(&bp->spq_lock);
3930         return 0;
3931 }
3932 
3933 /* acquire split MCP access lock register */
3934 static int bnx2x_acquire_alr(struct bnx2x *bp)
3935 {
3936         u32 j, val;
3937         int rc = 0;
3938 
3939         might_sleep();
3940         for (j = 0; j < 1000; j++) {
3941                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3942                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3943                 if (val & MCPR_ACCESS_LOCK_LOCK)
3944                         break;
3945 
3946                 usleep_range(5000, 10000);
3947         }
3948         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3949                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3950                 rc = -EBUSY;
3951         }
3952 
3953         return rc;
3954 }
3955 
3956 /* release split MCP access lock register */
3957 static void bnx2x_release_alr(struct bnx2x *bp)
3958 {
3959         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3960 }
3961 
3962 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3963 #define BNX2X_DEF_SB_IDX        0x0002
3964 
3965 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3966 {
3967         struct host_sp_status_block *def_sb = bp->def_status_blk;
3968         u16 rc = 0;
3969 
3970         barrier(); /* status block is written to by the chip */
3971         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3972                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3973                 rc |= BNX2X_DEF_SB_ATT_IDX;
3974         }
3975 
3976         if (bp->def_idx != def_sb->sp_sb.running_index) {
3977                 bp->def_idx = def_sb->sp_sb.running_index;
3978                 rc |= BNX2X_DEF_SB_IDX;
3979         }
3980 
3981         /* Do not reorder: indices reading should complete before handling */
3982         barrier();
3983         return rc;
3984 }
3985 
3986 /*
3987  * slow path service functions
3988  */
3989 
3990 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3991 {
3992         int port = BP_PORT(bp);
3993         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3994                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3995         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3996                                        NIG_REG_MASK_INTERRUPT_PORT0;
3997         u32 aeu_mask;
3998         u32 nig_mask = 0;
3999         u32 reg_addr;
4000 
4001         if (bp->attn_state & asserted)
4002                 BNX2X_ERR("IGU ERROR\n");
4003 
4004         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4005         aeu_mask = REG_RD(bp, aeu_addr);
4006 
4007         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
4008            aeu_mask, asserted);
4009         aeu_mask &= ~(asserted & 0x3ff);
4010         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4011 
4012         REG_WR(bp, aeu_addr, aeu_mask);
4013         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4014 
4015         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4016         bp->attn_state |= asserted;
4017         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4018 
4019         if (asserted & ATTN_HARD_WIRED_MASK) {
4020                 if (asserted & ATTN_NIG_FOR_FUNC) {
4021 
4022                         bnx2x_acquire_phy_lock(bp);
4023 
4024                         /* save nig interrupt mask */
4025                         nig_mask = REG_RD(bp, nig_int_mask_addr);
4026 
4027                         /* If nig_mask is not set, no need to call the update
4028                          * function.
4029                          */
4030                         if (nig_mask) {
4031                                 REG_WR(bp, nig_int_mask_addr, 0);
4032 
4033                                 bnx2x_link_attn(bp);
4034                         }
4035 
4036                         /* handle unicore attn? */
4037                 }
4038                 if (asserted & ATTN_SW_TIMER_4_FUNC)
4039                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4040 
4041                 if (asserted & GPIO_2_FUNC)
4042                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4043 
4044                 if (asserted & GPIO_3_FUNC)
4045                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4046 
4047                 if (asserted & GPIO_4_FUNC)
4048                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4049 
4050                 if (port == 0) {
4051                         if (asserted & ATTN_GENERAL_ATTN_1) {
4052                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4053                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4054                         }
4055                         if (asserted & ATTN_GENERAL_ATTN_2) {
4056                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4057                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4058                         }
4059                         if (asserted & ATTN_GENERAL_ATTN_3) {
4060                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4061                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4062                         }
4063                 } else {
4064                         if (asserted & ATTN_GENERAL_ATTN_4) {
4065                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4066                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4067                         }
4068                         if (asserted & ATTN_GENERAL_ATTN_5) {
4069                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4070                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4071                         }
4072                         if (asserted & ATTN_GENERAL_ATTN_6) {
4073                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4074                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4075                         }
4076                 }
4077 
4078         } /* if hardwired */
4079 
4080         if (bp->common.int_block == INT_BLOCK_HC)
4081                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4082                             COMMAND_REG_ATTN_BITS_SET);
4083         else
4084                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4085 
4086         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4087            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4088         REG_WR(bp, reg_addr, asserted);
4089 
4090         /* now set back the mask */
4091         if (asserted & ATTN_NIG_FOR_FUNC) {
4092                 /* Verify that IGU ack through BAR was written before restoring
4093                  * NIG mask. This loop should exit after 2-3 iterations max.
4094                  */
4095                 if (bp->common.int_block != INT_BLOCK_HC) {
4096                         u32 cnt = 0, igu_acked;
4097                         do {
4098                                 igu_acked = REG_RD(bp,
4099                                                    IGU_REG_ATTENTION_ACK_BITS);
4100                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4101                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
4102                         if (!igu_acked)
4103                                 DP(NETIF_MSG_HW,
4104                                    "Failed to verify IGU ack on time\n");
4105                         barrier();
4106                 }
4107                 REG_WR(bp, nig_int_mask_addr, nig_mask);
4108                 bnx2x_release_phy_lock(bp);
4109         }
4110 }
4111 
4112 static void bnx2x_fan_failure(struct bnx2x *bp)
4113 {
4114         int port = BP_PORT(bp);
4115         u32 ext_phy_config;
4116         /* mark the failure */
4117         ext_phy_config =
4118                 SHMEM_RD(bp,
4119                          dev_info.port_hw_config[port].external_phy_config);
4120 
4121         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4122         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4123         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4124                  ext_phy_config);
4125 
4126         /* log the failure */
4127         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4128                             "Please contact OEM Support for assistance\n");
4129 
4130         /* Schedule device reset (unload)
4131          * This is due to some boards consuming sufficient power when driver is
4132          * up to overheat if fan fails.
4133          */
4134         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4135 }
4136 
4137 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4138 {
4139         int port = BP_PORT(bp);
4140         int reg_offset;
4141         u32 val;
4142 
4143         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4144                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4145 
4146         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4147 
4148                 val = REG_RD(bp, reg_offset);
4149                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4150                 REG_WR(bp, reg_offset, val);
4151 
4152                 BNX2X_ERR("SPIO5 hw attention\n");
4153 
4154                 /* Fan failure attention */
4155                 bnx2x_hw_reset_phy(&bp->link_params);
4156                 bnx2x_fan_failure(bp);
4157         }
4158 
4159         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4160                 bnx2x_acquire_phy_lock(bp);
4161                 bnx2x_handle_module_detect_int(&bp->link_params);
4162                 bnx2x_release_phy_lock(bp);
4163         }
4164 
4165         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4166 
4167                 val = REG_RD(bp, reg_offset);
4168                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4169                 REG_WR(bp, reg_offset, val);
4170 
4171                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4172                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
4173                 bnx2x_panic();
4174         }
4175 }
4176 
4177 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4178 {
4179         u32 val;
4180 
4181         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4182 
4183                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4184                 BNX2X_ERR("DB hw attention 0x%x\n", val);
4185                 /* DORQ discard attention */
4186                 if (val & 0x2)
4187                         BNX2X_ERR("FATAL error from DORQ\n");
4188         }
4189 
4190         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4191 
4192                 int port = BP_PORT(bp);
4193                 int reg_offset;
4194 
4195                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4196                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4197 
4198                 val = REG_RD(bp, reg_offset);
4199                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4200                 REG_WR(bp, reg_offset, val);
4201 
4202                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4203                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
4204                 bnx2x_panic();
4205         }
4206 }
4207 
4208 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4209 {
4210         u32 val;
4211 
4212         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4213 
4214                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4215                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4216                 /* CFC error attention */
4217                 if (val & 0x2)
4218                         BNX2X_ERR("FATAL error from CFC\n");
4219         }
4220 
4221         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4222                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4223                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4224                 /* RQ_USDMDP_FIFO_OVERFLOW */
4225                 if (val & 0x18000)
4226                         BNX2X_ERR("FATAL error from PXP\n");
4227 
4228                 if (!CHIP_IS_E1x(bp)) {
4229                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4230                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4231                 }
4232         }
4233 
4234         if (attn & HW_INTERRUT_ASSERT_SET_2) {
4235 
4236                 int port = BP_PORT(bp);
4237                 int reg_offset;
4238 
4239                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4240                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4241 
4242                 val = REG_RD(bp, reg_offset);
4243                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4244                 REG_WR(bp, reg_offset, val);
4245 
4246                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4247                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
4248                 bnx2x_panic();
4249         }
4250 }
4251 
4252 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4253 {
4254         u32 val;
4255 
4256         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4257 
4258                 if (attn & BNX2X_PMF_LINK_ASSERT) {
4259                         int func = BP_FUNC(bp);
4260 
4261                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4262                         bnx2x_read_mf_cfg(bp);
4263                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4264                                         func_mf_config[BP_ABS_FUNC(bp)].config);
4265                         val = SHMEM_RD(bp,
4266                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
4267 
4268                         if (val & (DRV_STATUS_DCC_EVENT_MASK |
4269                                    DRV_STATUS_OEM_EVENT_MASK))
4270                                 bnx2x_oem_event(bp,
4271                                         (val & (DRV_STATUS_DCC_EVENT_MASK |
4272                                                 DRV_STATUS_OEM_EVENT_MASK)));
4273 
4274                         if (val & DRV_STATUS_SET_MF_BW)
4275                                 bnx2x_set_mf_bw(bp);
4276 
4277                         if (val & DRV_STATUS_DRV_INFO_REQ)
4278                                 bnx2x_handle_drv_info_req(bp);
4279 
4280                         if (val & DRV_STATUS_VF_DISABLED)
4281                                 bnx2x_schedule_iov_task(bp,
4282                                                         BNX2X_IOV_HANDLE_FLR);
4283 
4284                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4285                                 bnx2x_pmf_update(bp);
4286 
4287                         if (bp->port.pmf &&
4288                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4289                                 bp->dcbx_enabled > 0)
4290                                 /* start dcbx state machine */
4291                                 bnx2x_dcbx_set_params(bp,
4292                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4293                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4294                                 bnx2x_handle_afex_cmd(bp,
4295                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4296                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4297                                 bnx2x_handle_eee_event(bp);
4298 
4299                         if (val & DRV_STATUS_OEM_UPDATE_SVID)
4300                                 bnx2x_handle_update_svid_cmd(bp);
4301 
4302                         if (bp->link_vars.periodic_flags &
4303                             PERIODIC_FLAGS_LINK_EVENT) {
4304                                 /*  sync with link */
4305                                 bnx2x_acquire_phy_lock(bp);
4306                                 bp->link_vars.periodic_flags &=
4307                                         ~PERIODIC_FLAGS_LINK_EVENT;
4308                                 bnx2x_release_phy_lock(bp);
4309                                 if (IS_MF(bp))
4310                                         bnx2x_link_sync_notify(bp);
4311                                 bnx2x_link_report(bp);
4312                         }
4313                         /* Always call it here: bnx2x_link_report() will
4314                          * prevent the link indication duplication.
4315                          */
4316                         bnx2x__link_status_update(bp);
4317                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4318 
4319                         BNX2X_ERR("MC assert!\n");
4320                         bnx2x_mc_assert(bp);
4321                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4322                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4323                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4324                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4325                         bnx2x_panic();
4326 
4327                 } else if (attn & BNX2X_MCP_ASSERT) {
4328 
4329                         BNX2X_ERR("MCP assert!\n");
4330                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4331                         bnx2x_fw_dump(bp);
4332 
4333                 } else
4334                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4335         }
4336 
4337         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4338                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4339                 if (attn & BNX2X_GRC_TIMEOUT) {
4340                         val = CHIP_IS_E1(bp) ? 0 :
4341                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4342                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4343                 }
4344                 if (attn & BNX2X_GRC_RSV) {
4345                         val = CHIP_IS_E1(bp) ? 0 :
4346                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4347                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4348                 }
4349                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4350         }
4351 }
4352 
4353 /*
4354  * Bits map:
4355  * 0-7   - Engine0 load counter.
4356  * 8-15  - Engine1 load counter.
4357  * 16    - Engine0 RESET_IN_PROGRESS bit.
4358  * 17    - Engine1 RESET_IN_PROGRESS bit.
4359  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4360  *         on the engine
4361  * 19    - Engine1 ONE_IS_LOADED.
4362  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4363  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4364  *         just the one belonging to its engine).
4365  *
4366  */
4367 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4368 
4369 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4370 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4371 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4372 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4373 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4374 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4375 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4376 
4377 /*
4378  * Set the GLOBAL_RESET bit.
4379  *
4380  * Should be run under rtnl lock
4381  */
4382 void bnx2x_set_reset_global(struct bnx2x *bp)
4383 {
4384         u32 val;
4385         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4386         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4387         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4388         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4389 }
4390 
4391 /*
4392  * Clear the GLOBAL_RESET bit.
4393  *
4394  * Should be run under rtnl lock
4395  */
4396 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4397 {
4398         u32 val;
4399         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4400         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4401         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4402         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4403 }
4404 
4405 /*
4406  * Checks the GLOBAL_RESET bit.
4407  *
4408  * should be run under rtnl lock
4409  */
4410 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4411 {
4412         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4413 
4414         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4415         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4416 }
4417 
4418 /*
4419  * Clear RESET_IN_PROGRESS bit for the current engine.
4420  *
4421  * Should be run under rtnl lock
4422  */
4423 static void bnx2x_set_reset_done(struct bnx2x *bp)
4424 {
4425         u32 val;
4426         u32 bit = BP_PATH(bp) ?
4427                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4428         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4429         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4430 
4431         /* Clear the bit */
4432         val &= ~bit;
4433         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4434 
4435         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4436 }
4437 
4438 /*
4439  * Set RESET_IN_PROGRESS for the current engine.
4440  *
4441  * should be run under rtnl lock
4442  */
4443 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4444 {
4445         u32 val;
4446         u32 bit = BP_PATH(bp) ?
4447                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4448         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4449         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4450 
4451         /* Set the bit */
4452         val |= bit;
4453         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4454         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4455 }
4456 
4457 /*
4458  * Checks the RESET_IN_PROGRESS bit for the given engine.
4459  * should be run under rtnl lock
4460  */
4461 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4462 {
4463         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4464         u32 bit = engine ?
4465                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4466 
4467         /* return false if bit is set */
4468         return (val & bit) ? false : true;
4469 }
4470 
4471 /*
4472  * set pf load for the current pf.
4473  *
4474  * should be run under rtnl lock
4475  */
4476 void bnx2x_set_pf_load(struct bnx2x *bp)
4477 {
4478         u32 val1, val;
4479         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4480                              BNX2X_PATH0_LOAD_CNT_MASK;
4481         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4482                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4483 
4484         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4485         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4486 
4487         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4488 
4489         /* get the current counter value */
4490         val1 = (val & mask) >> shift;
4491 
4492         /* set bit of that PF */
4493         val1 |= (1 << bp->pf_num);
4494 
4495         /* clear the old value */
4496         val &= ~mask;
4497 
4498         /* set the new one */
4499         val |= ((val1 << shift) & mask);
4500 
4501         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4502         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4503 }
4504 
4505 /**
4506  * bnx2x_clear_pf_load - clear pf load mark
4507  *
4508  * @bp:         driver handle
4509  *
4510  * Should be run under rtnl lock.
4511  * Decrements the load counter for the current engine. Returns
4512  * whether other functions are still loaded
4513  */
4514 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4515 {
4516         u32 val1, val;
4517         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4518                              BNX2X_PATH0_LOAD_CNT_MASK;
4519         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4520                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4521 
4522         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4523         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4524         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4525 
4526         /* get the current counter value */
4527         val1 = (val & mask) >> shift;
4528 
4529         /* clear bit of that PF */
4530         val1 &= ~(1 << bp->pf_num);
4531 
4532         /* clear the old value */
4533         val &= ~mask;
4534 
4535         /* set the new one */
4536         val |= ((val1 << shift) & mask);
4537 
4538         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4539         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4540         return val1 != 0;
4541 }
4542 
4543 /*
4544  * Read the load status for the current engine.
4545  *
4546  * should be run under rtnl lock
4547  */
4548 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4549 {
4550         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4551                              BNX2X_PATH0_LOAD_CNT_MASK);
4552         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4553                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4554         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4555 
4556         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4557 
4558         val = (val & mask) >> shift;
4559 
4560         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4561            engine, val);
4562 
4563         return val != 0;
4564 }
4565 
4566 static void _print_parity(struct bnx2x *bp, u32 reg)
4567 {
4568         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4569 }
4570 
4571 static void _print_next_block(int idx, const char *blk)
4572 {
4573         pr_cont("%s%s", idx ? ", " : "", blk);
4574 }
4575 
4576 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4577                                             int *par_num, bool print)
4578 {
4579         u32 cur_bit;
4580         bool res;
4581         int i;
4582 
4583         res = false;
4584 
4585         for (i = 0; sig; i++) {
4586                 cur_bit = (0x1UL << i);
4587                 if (sig & cur_bit) {
4588                         res |= true; /* Each bit is real error! */
4589 
4590                         if (print) {
4591                                 switch (cur_bit) {
4592                                 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4593                                         _print_next_block((*par_num)++, "BRB");
4594                                         _print_parity(bp,
4595                                                       BRB1_REG_BRB1_PRTY_STS);
4596                                         break;
4597                                 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4598                                         _print_next_block((*par_num)++,
4599                                                           "PARSER");
4600                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4601                                         break;
4602                                 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4603                                         _print_next_block((*par_num)++, "TSDM");
4604                                         _print_parity(bp,
4605                                                       TSDM_REG_TSDM_PRTY_STS);
4606                                         break;
4607                                 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4608                                         _print_next_block((*par_num)++,
4609                                                           "SEARCHER");
4610                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4611                                         break;
4612                                 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4613                                         _print_next_block((*par_num)++, "TCM");
4614                                         _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4615                                         break;
4616                                 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4617                                         _print_next_block((*par_num)++,
4618                                                           "TSEMI");
4619                                         _print_parity(bp,
4620                                                       TSEM_REG_TSEM_PRTY_STS_0);
4621                                         _print_parity(bp,
4622                                                       TSEM_REG_TSEM_PRTY_STS_1);
4623                                         break;
4624                                 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4625                                         _print_next_block((*par_num)++, "XPB");
4626                                         _print_parity(bp, GRCBASE_XPB +
4627                                                           PB_REG_PB_PRTY_STS);
4628                                         break;
4629                                 }
4630                         }
4631 
4632                         /* Clear the bit */
4633                         sig &= ~cur_bit;
4634                 }
4635         }
4636 
4637         return res;
4638 }
4639 
4640 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4641                                             int *par_num, bool *global,
4642                                             bool print)
4643 {
4644         u32 cur_bit;
4645         bool res;
4646         int i;
4647 
4648         res = false;
4649 
4650         for (i = 0; sig; i++) {
4651                 cur_bit = (0x1UL << i);
4652                 if (sig & cur_bit) {
4653                         res |= true; /* Each bit is real error! */
4654                         switch (cur_bit) {
4655                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4656                                 if (print) {
4657                                         _print_next_block((*par_num)++, "PBF");
4658                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4659                                 }
4660                                 break;
4661                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4662                                 if (print) {
4663                                         _print_next_block((*par_num)++, "QM");
4664                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4665                                 }
4666                                 break;
4667                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4668                                 if (print) {
4669                                         _print_next_block((*par_num)++, "TM");
4670                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4671                                 }
4672                                 break;
4673                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4674                                 if (print) {
4675                                         _print_next_block((*par_num)++, "XSDM");
4676                                         _print_parity(bp,
4677                                                       XSDM_REG_XSDM_PRTY_STS);
4678                                 }
4679                                 break;
4680                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4681                                 if (print) {
4682                                         _print_next_block((*par_num)++, "XCM");
4683                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4684                                 }
4685                                 break;
4686                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4687                                 if (print) {
4688                                         _print_next_block((*par_num)++,
4689                                                           "XSEMI");
4690                                         _print_parity(bp,
4691                                                       XSEM_REG_XSEM_PRTY_STS_0);
4692                                         _print_parity(bp,
4693                                                       XSEM_REG_XSEM_PRTY_STS_1);
4694                                 }
4695                                 break;
4696                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4697                                 if (print) {
4698                                         _print_next_block((*par_num)++,
4699                                                           "DOORBELLQ");
4700                                         _print_parity(bp,
4701                                                       DORQ_REG_DORQ_PRTY_STS);
4702                                 }
4703                                 break;
4704                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4705                                 if (print) {
4706                                         _print_next_block((*par_num)++, "NIG");
4707                                         if (CHIP_IS_E1x(bp)) {
4708                                                 _print_parity(bp,
4709                                                         NIG_REG_NIG_PRTY_STS);
4710                                         } else {
4711                                                 _print_parity(bp,
4712                                                         NIG_REG_NIG_PRTY_STS_0);
4713                                                 _print_parity(bp,
4714                                                         NIG_REG_NIG_PRTY_STS_1);
4715                                         }
4716                                 }
4717                                 break;
4718                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4719                                 if (print)
4720                                         _print_next_block((*par_num)++,
4721                                                           "VAUX PCI CORE");
4722                                 *global = true;
4723                                 break;
4724                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4725                                 if (print) {
4726                                         _print_next_block((*par_num)++,
4727                                                           "DEBUG");
4728                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4729                                 }
4730                                 break;
4731                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4732                                 if (print) {
4733                                         _print_next_block((*par_num)++, "USDM");
4734                                         _print_parity(bp,
4735                                                       USDM_REG_USDM_PRTY_STS);
4736                                 }
4737                                 break;
4738                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4739                                 if (print) {
4740                                         _print_next_block((*par_num)++, "UCM");
4741                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4742                                 }
4743                                 break;
4744                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4745                                 if (print) {
4746                                         _print_next_block((*par_num)++,
4747                                                           "USEMI");
4748                                         _print_parity(bp,
4749                                                       USEM_REG_USEM_PRTY_STS_0);
4750                                         _print_parity(bp,
4751                                                       USEM_REG_USEM_PRTY_STS_1);
4752                                 }
4753                                 break;
4754                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4755                                 if (print) {
4756                                         _print_next_block((*par_num)++, "UPB");
4757                                         _print_parity(bp, GRCBASE_UPB +
4758                                                           PB_REG_PB_PRTY_STS);
4759                                 }
4760                                 break;
4761                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4762                                 if (print) {
4763                                         _print_next_block((*par_num)++, "CSDM");
4764                                         _print_parity(bp,
4765                                                       CSDM_REG_CSDM_PRTY_STS);
4766                                 }
4767                                 break;
4768                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4769                                 if (print) {
4770                                         _print_next_block((*par_num)++, "CCM");
4771                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4772                                 }
4773                                 break;
4774                         }
4775 
4776                         /* Clear the bit */
4777                         sig &= ~cur_bit;
4778                 }
4779         }
4780 
4781         return res;
4782 }
4783 
4784 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4785                                             int *par_num, bool print)
4786 {
4787         u32 cur_bit;
4788         bool res;
4789         int i;
4790 
4791         res = false;
4792 
4793         for (i = 0; sig; i++) {
4794                 cur_bit = (0x1UL << i);
4795                 if (sig & cur_bit) {
4796                         res = true; /* Each bit is real error! */
4797                         if (print) {
4798                                 switch (cur_bit) {
4799                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4800                                         _print_next_block((*par_num)++,
4801                                                           "CSEMI");
4802                                         _print_parity(bp,
4803                                                       CSEM_REG_CSEM_PRTY_STS_0);
4804                                         _print_parity(bp,
4805                                                       CSEM_REG_CSEM_PRTY_STS_1);
4806                                         break;
4807                                 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4808                                         _print_next_block((*par_num)++, "PXP");
4809                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4810                                         _print_parity(bp,
4811                                                       PXP2_REG_PXP2_PRTY_STS_0);
4812                                         _print_parity(bp,
4813                                                       PXP2_REG_PXP2_PRTY_STS_1);
4814                                         break;
4815                                 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4816                                         _print_next_block((*par_num)++,
4817                                                           "PXPPCICLOCKCLIENT");
4818                                         break;
4819                                 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4820                                         _print_next_block((*par_num)++, "CFC");
4821                                         _print_parity(bp,
4822                                                       CFC_REG_CFC_PRTY_STS);
4823                                         break;
4824                                 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4825                                         _print_next_block((*par_num)++, "CDU");
4826                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4827                                         break;
4828                                 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4829                                         _print_next_block((*par_num)++, "DMAE");
4830                                         _print_parity(bp,
4831                                                       DMAE_REG_DMAE_PRTY_STS);
4832                                         break;
4833                                 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4834                                         _print_next_block((*par_num)++, "IGU");
4835                                         if (CHIP_IS_E1x(bp))
4836                                                 _print_parity(bp,
4837                                                         HC_REG_HC_PRTY_STS);
4838                                         else
4839                                                 _print_parity(bp,
4840                                                         IGU_REG_IGU_PRTY_STS);
4841                                         break;
4842                                 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4843                                         _print_next_block((*par_num)++, "MISC");
4844                                         _print_parity(bp,
4845                                                       MISC_REG_MISC_PRTY_STS);
4846                                         break;
4847                                 }
4848                         }
4849 
4850                         /* Clear the bit */
4851                         sig &= ~cur_bit;
4852                 }
4853         }
4854 
4855         return res;
4856 }
4857 
4858 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4859                                             int *par_num, bool *global,
4860                                             bool print)
4861 {
4862         bool res = false;
4863         u32 cur_bit;
4864         int i;
4865 
4866         for (i = 0; sig; i++) {
4867                 cur_bit = (0x1UL << i);
4868                 if (sig & cur_bit) {
4869                         switch (cur_bit) {
4870                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4871                                 if (print)
4872                                         _print_next_block((*par_num)++,
4873                                                           "MCP ROM");
4874                                 *global = true;
4875                                 res = true;
4876                                 break;
4877                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4878                                 if (print)
4879                                         _print_next_block((*par_num)++,
4880                                                           "MCP UMP RX");
4881                                 *global = true;
4882                                 res = true;
4883                                 break;
4884                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4885                                 if (print)
4886                                         _print_next_block((*par_num)++,
4887                                                           "MCP UMP TX");
4888                                 *global = true;
4889                                 res = true;
4890                                 break;
4891                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4892                                 (*par_num)++;
4893                                 /* clear latched SCPAD PATIRY from MCP */
4894                                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4895                                        1UL << 10);
4896                                 break;
4897                         }
4898 
4899                         /* Clear the bit */
4900                         sig &= ~cur_bit;
4901                 }
4902         }
4903 
4904         return res;
4905 }
4906 
4907 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4908                                             int *par_num, bool print)
4909 {
4910         u32 cur_bit;
4911         bool res;
4912         int i;
4913 
4914         res = false;
4915 
4916         for (i = 0; sig; i++) {
4917                 cur_bit = (0x1UL << i);
4918                 if (sig & cur_bit) {
4919                         res = true; /* Each bit is real error! */
4920                         if (print) {
4921                                 switch (cur_bit) {
4922                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4923                                         _print_next_block((*par_num)++,
4924                                                           "PGLUE_B");
4925                                         _print_parity(bp,
4926                                                       PGLUE_B_REG_PGLUE_B_PRTY_STS);
4927                                         break;
4928                                 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4929                                         _print_next_block((*par_num)++, "ATC");
4930                                         _print_parity(bp,
4931                                                       ATC_REG_ATC_PRTY_STS);
4932                                         break;
4933                                 }
4934                         }
4935                         /* Clear the bit */
4936                         sig &= ~cur_bit;
4937                 }
4938         }
4939 
4940         return res;
4941 }
4942 
4943 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4944                               u32 *sig)
4945 {
4946         bool res = false;
4947 
4948         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4949             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4950             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4951             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4952             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4953                 int par_num = 0;
4954 
4955                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4956                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4957                           sig[0] & HW_PRTY_ASSERT_SET_0,
4958                           sig[1] & HW_PRTY_ASSERT_SET_1,
4959                           sig[2] & HW_PRTY_ASSERT_SET_2,
4960                           sig[3] & HW_PRTY_ASSERT_SET_3,
4961                           sig[4] & HW_PRTY_ASSERT_SET_4);
4962                 if (print) {
4963                         if (((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4964                              (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4965                              (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4966                              (sig[4] & HW_PRTY_ASSERT_SET_4)) ||
4967                              (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) {
4968                                 netdev_err(bp->dev,
4969                                            "Parity errors detected in blocks: ");
4970                         } else {
4971                                 print = false;
4972                         }
4973                 }
4974                 res |= bnx2x_check_blocks_with_parity0(bp,
4975                         sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4976                 res |= bnx2x_check_blocks_with_parity1(bp,
4977                         sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4978                 res |= bnx2x_check_blocks_with_parity2(bp,
4979                         sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4980                 res |= bnx2x_check_blocks_with_parity3(bp,
4981                         sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4982                 res |= bnx2x_check_blocks_with_parity4(bp,
4983                         sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4984 
4985                 if (print)
4986                         pr_cont("\n");
4987         }
4988 
4989         return res;
4990 }
4991 
4992 /**
4993  * bnx2x_chk_parity_attn - checks for parity attentions.
4994  *
4995  * @bp:         driver handle
4996  * @global:     true if there was a global attention
4997  * @print:      show parity attention in syslog
4998  */
4999 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
5000 {
5001         struct attn_route attn = { {0} };
5002         int port = BP_PORT(bp);
5003 
5004         attn.sig[0] = REG_RD(bp,
5005                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5006                              port*4);
5007         attn.sig[1] = REG_RD(bp,
5008                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
5009                              port*4);
5010         attn.sig[2] = REG_RD(bp,
5011                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
5012                              port*4);
5013         attn.sig[3] = REG_RD(bp,
5014                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
5015                              port*4);
5016         /* Since MCP attentions can't be disabled inside the block, we need to
5017          * read AEU registers to see whether they're currently disabled
5018          */
5019         attn.sig[3] &= ((REG_RD(bp,
5020                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
5021                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
5022                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
5023                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
5024 
5025         if (!CHIP_IS_E1x(bp))
5026                 attn.sig[4] = REG_RD(bp,
5027                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
5028                                      port*4);
5029 
5030         return bnx2x_parity_attn(bp, global, print, attn.sig);
5031 }
5032 
5033 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
5034 {
5035         u32 val;
5036         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5037 
5038                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5039                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5040                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
5041                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5042                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
5043                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5044                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
5045                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5046                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
5047                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5048                 if (val &
5049                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
5050                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5051                 if (val &
5052                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
5053                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5054                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
5055                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5056                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
5057                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5058                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
5059                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5060         }
5061         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5062                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5063                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5064                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5065                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5066                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
5067                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5068                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
5069                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5070                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
5071                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5072                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5073                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5074                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
5075                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5076         }
5077 
5078         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5079                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5080                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5081                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5082                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5083         }
5084 }
5085 
5086 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5087 {
5088         struct attn_route attn, *group_mask;
5089         int port = BP_PORT(bp);
5090         int index;
5091         u32 reg_addr;
5092         u32 val;
5093         u32 aeu_mask;
5094         bool global = false;
5095 
5096         /* need to take HW lock because MCP or other port might also
5097            try to handle this event */
5098         bnx2x_acquire_alr(bp);
5099 
5100         if (bnx2x_chk_parity_attn(bp, &global, true)) {
5101 #ifndef BNX2X_STOP_ON_ERROR
5102                 bp->recovery_state = BNX2X_RECOVERY_INIT;
5103                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5104                 /* Disable HW interrupts */
5105                 bnx2x_int_disable(bp);
5106                 /* In case of parity errors don't handle attentions so that
5107                  * other function would "see" parity errors.
5108                  */
5109 #else
5110                 bnx2x_panic();
5111 #endif
5112                 bnx2x_release_alr(bp);
5113                 return;
5114         }
5115 
5116         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5117         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5118         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5119         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5120         if (!CHIP_IS_E1x(bp))
5121                 attn.sig[4] =
5122                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5123         else
5124                 attn.sig[4] = 0;
5125 
5126         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5127            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5128 
5129         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5130                 if (deasserted & (1 << index)) {
5131                         group_mask = &bp->attn_group[index];
5132 
5133                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5134                            index,
5135                            group_mask->sig[0], group_mask->sig[1],
5136                            group_mask->sig[2], group_mask->sig[3],
5137                            group_mask->sig[4]);
5138 
5139                         bnx2x_attn_int_deasserted4(bp,
5140                                         attn.sig[4] & group_mask->sig[4]);
5141                         bnx2x_attn_int_deasserted3(bp,
5142                                         attn.sig[3] & group_mask->sig[3]);
5143                         bnx2x_attn_int_deasserted1(bp,
5144                                         attn.sig[1] & group_mask->sig[1]);
5145                         bnx2x_attn_int_deasserted2(bp,
5146                                         attn.sig[2] & group_mask->sig[2]);
5147                         bnx2x_attn_int_deasserted0(bp,
5148                                         attn.sig[0] & group_mask->sig[0]);
5149                 }
5150         }
5151 
5152         bnx2x_release_alr(bp);
5153 
5154         if (bp->common.int_block == INT_BLOCK_HC)
5155                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5156                             COMMAND_REG_ATTN_BITS_CLR);
5157         else
5158                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5159 
5160         val = ~deasserted;
5161         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5162            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5163         REG_WR(bp, reg_addr, val);
5164 
5165         if (~bp->attn_state & deasserted)
5166                 BNX2X_ERR("IGU ERROR\n");
5167 
5168         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5169                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
5170 
5171         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5172         aeu_mask = REG_RD(bp, reg_addr);
5173 
5174         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
5175            aeu_mask, deasserted);
5176         aeu_mask |= (deasserted & 0x3ff);
5177         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5178 
5179         REG_WR(bp, reg_addr, aeu_mask);
5180         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5181 
5182         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5183         bp->attn_state &= ~deasserted;
5184         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5185 }
5186 
5187 static void bnx2x_attn_int(struct bnx2x *bp)
5188 {
5189         /* read local copy of bits */
5190         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5191                                                                 attn_bits);
5192         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5193                                                                 attn_bits_ack);
5194         u32 attn_state = bp->attn_state;
5195 
5196         /* look for changed bits */
5197         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
5198         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
5199 
5200         DP(NETIF_MSG_HW,
5201            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
5202            attn_bits, attn_ack, asserted, deasserted);
5203 
5204         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5205                 BNX2X_ERR("BAD attention state\n");
5206 
5207         /* handle bits that were raised */
5208         if (asserted)
5209                 bnx2x_attn_int_asserted(bp, asserted);
5210 
5211         if (deasserted)
5212                 bnx2x_attn_int_deasserted(bp, deasserted);
5213 }
5214 
5215 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5216                       u16 index, u8 op, u8 update)
5217 {
5218         u32 igu_addr = bp->igu_base_addr;
5219         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5220         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5221                              igu_addr);
5222 }
5223 
5224 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5225 {
5226         /* No memory barriers */
5227         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5228         mmiowb(); /* keep prod updates ordered */
5229 }
5230 
5231 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5232                                       union event_ring_elem *elem)
5233 {
5234         u8 err = elem->message.error;
5235 
5236         if (!bp->cnic_eth_dev.starting_cid  ||
5237             (cid < bp->cnic_eth_dev.starting_cid &&
5238             cid != bp->cnic_eth_dev.iscsi_l2_cid))
5239                 return 1;
5240 
5241         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5242 
5243         if (unlikely(err)) {
5244 
5245                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5246                           cid);
5247                 bnx2x_panic_dump(bp, false);
5248         }
5249         bnx2x_cnic_cfc_comp(bp, cid, err);
5250         return 0;
5251 }
5252 
5253 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5254 {
5255         struct bnx2x_mcast_ramrod_params rparam;
5256         int rc;
5257 
5258         memset(&rparam, 0, sizeof(rparam));
5259 
5260         rparam.mcast_obj = &bp->mcast_obj;
5261 
5262         netif_addr_lock_bh(bp->dev);
5263 
5264         /* Clear pending state for the last command */
5265         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5266 
5267         /* If there are pending mcast commands - send them */
5268         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5269                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5270                 if (rc < 0)
5271                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5272                                   rc);
5273         }
5274 
5275         netif_addr_unlock_bh(bp->dev);
5276 }
5277 
5278 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5279                                             union event_ring_elem *elem)
5280 {
5281         unsigned long ramrod_flags = 0;
5282         int rc = 0;
5283         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5284         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5285 
5286         /* Always push next commands out, don't wait here */
5287         __set_bit(RAMROD_CONT, &ramrod_flags);
5288 
5289         switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5290                             >> BNX2X_SWCID_SHIFT) {
5291         case BNX2X_FILTER_MAC_PENDING:
5292                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5293                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5294                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5295                 else
5296                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5297 
5298                 break;
5299         case BNX2X_FILTER_VLAN_PENDING:
5300                 DP(BNX2X_MSG_SP, "Got SETUP_VLAN completions\n");
5301                 vlan_mac_obj = &bp->sp_objs[cid].vlan_obj;
5302                 break;
5303         case BNX2X_FILTER_MCAST_PENDING:
5304                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5305                 /* This is only relevant for 57710 where multicast MACs are
5306                  * configured as unicast MACs using the same ramrod.
5307                  */
5308                 bnx2x_handle_mcast_eqe(bp);
5309                 return;
5310         default:
5311                 BNX2X_ERR("Unsupported classification command: %d\n",
5312                           elem->message.data.eth_event.echo);
5313                 return;
5314         }
5315 
5316         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5317 
5318         if (rc < 0)
5319                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5320         else if (rc > 0)
5321                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5322 }
5323 
5324 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5325 
5326 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5327 {
5328         netif_addr_lock_bh(bp->dev);
5329 
5330         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5331 
5332         /* Send rx_mode command again if was requested */
5333         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5334                 bnx2x_set_storm_rx_mode(bp);
5335         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5336                                     &bp->sp_state))
5337                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5338         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5339                                     &bp->sp_state))
5340                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5341 
5342         netif_addr_unlock_bh(bp->dev);
5343 }
5344 
5345 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5346                                               union event_ring_elem *elem)
5347 {
5348         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5349                 DP(BNX2X_MSG_SP,
5350                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5351                    elem->message.data.vif_list_event.func_bit_map);
5352                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5353                         elem->message.data.vif_list_event.func_bit_map);
5354         } else if (elem->message.data.vif_list_event.echo ==
5355                    VIF_LIST_RULE_SET) {
5356                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5357                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5358         }
5359 }
5360 
5361 /* called with rtnl_lock */
5362 static void bnx2x_after_function_update(struct bnx2x *bp)
5363 {
5364         int q, rc;
5365         struct bnx2x_fastpath *fp;
5366         struct bnx2x_queue_state_params queue_params = {NULL};
5367         struct bnx2x_queue_update_params *q_update_params =
5368                 &queue_params.params.update;
5369 
5370         /* Send Q update command with afex vlan removal values for all Qs */
5371         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5372 
5373         /* set silent vlan removal values according to vlan mode */
5374         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5375                   &q_update_params->update_flags);
5376         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5377                   &q_update_params->update_flags);
5378         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5379 
5380         /* in access mode mark mask and value are 0 to strip all vlans */
5381         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5382                 q_update_params->silent_removal_value = 0;
5383                 q_update_params->silent_removal_mask = 0;
5384         } else {
5385                 q_update_params->silent_removal_value =
5386                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5387                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5388         }
5389 
5390         for_each_eth_queue(bp, q) {
5391                 /* Set the appropriate Queue object */
5392                 fp = &bp->fp[q];
5393                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5394 
5395                 /* send the ramrod */
5396                 rc = bnx2x_queue_state_change(bp, &queue_params);
5397                 if (rc < 0)
5398                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5399                                   q);
5400         }
5401 
5402         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5403                 fp = &bp->fp[FCOE_IDX(bp)];
5404                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5405 
5406                 /* clear pending completion bit */
5407                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5408 
5409                 /* mark latest Q bit */
5410                 smp_mb__before_atomic();
5411                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5412                 smp_mb__after_atomic();
5413 
5414                 /* send Q update ramrod for FCoE Q */
5415                 rc = bnx2x_queue_state_change(bp, &queue_params);
5416                 if (rc < 0)
5417                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5418                                   q);
5419         } else {
5420                 /* If no FCoE ring - ACK MCP now */
5421                 bnx2x_link_report(bp);
5422                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5423         }
5424 }
5425 
5426 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5427         struct bnx2x *bp, u32 cid)
5428 {
5429         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5430 
5431         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5432                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5433         else
5434                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5435 }
5436 
5437 static void bnx2x_eq_int(struct bnx2x *bp)
5438 {
5439         u16 hw_cons, sw_cons, sw_prod;
5440         union event_ring_elem *elem;
5441         u8 echo;
5442         u32 cid;
5443         u8 opcode;
5444         int rc, spqe_cnt = 0;
5445         struct bnx2x_queue_sp_obj *q_obj;
5446         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5447         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5448 
5449         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5450 
5451         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5452          * when we get the next-page we need to adjust so the loop
5453          * condition below will be met. The next element is the size of a
5454          * regular element and hence incrementing by 1
5455          */
5456         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5457                 hw_cons++;
5458 
5459         /* This function may never run in parallel with itself for a
5460          * specific bp, thus there is no need in "paired" read memory
5461          * barrier here.
5462          */
5463         sw_cons = bp->eq_cons;
5464         sw_prod = bp->eq_prod;
5465 
5466         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5467                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5468 
5469         for (; sw_cons != hw_cons;
5470               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5471 
5472                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5473 
5474                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5475                 if (!rc) {
5476                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5477                            rc);
5478                         goto next_spqe;
5479                 }
5480 
5481                 /* elem CID originates from FW; actually LE */
5482                 cid = SW_CID((__force __le32)
5483                              elem->message.data.cfc_del_event.cid);
5484                 opcode = elem->message.opcode;
5485 
5486                 /* handle eq element */
5487                 switch (opcode) {
5488                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5489                         bnx2x_vf_mbx_schedule(bp,
5490                                               &elem->message.data.vf_pf_event);
5491                         continue;
5492 
5493                 case EVENT_RING_OPCODE_STAT_QUERY:
5494                         DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5495                                "got statistics comp event %d\n",
5496                                bp->stats_comp++);
5497                         /* nothing to do with stats comp */
5498                         goto next_spqe;
5499 
5500                 case EVENT_RING_OPCODE_CFC_DEL:
5501                         /* handle according to cid range */
5502                         /*
5503                          * we may want to verify here that the bp state is
5504                          * HALTING
5505                          */
5506                         DP(BNX2X_MSG_SP,
5507                            "got delete ramrod for MULTI[%d]\n", cid);
5508 
5509                         if (CNIC_LOADED(bp) &&
5510                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5511                                 goto next_spqe;
5512 
5513                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5514 
5515                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5516                                 break;
5517 
5518                         goto next_spqe;
5519 
5520                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5521                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5522                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5523                         if (f_obj->complete_cmd(bp, f_obj,
5524                                                 BNX2X_F_CMD_TX_STOP))
5525                                 break;
5526                         goto next_spqe;
5527 
5528                 case EVENT_RING_OPCODE_START_TRAFFIC:
5529                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5530                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5531                         if (f_obj->complete_cmd(bp, f_obj,
5532                                                 BNX2X_F_CMD_TX_START))
5533                                 break;
5534                         goto next_spqe;
5535 
5536                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5537                         echo = elem->message.data.function_update_event.echo;
5538                         if (echo == SWITCH_UPDATE) {
5539                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5540                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5541                                 if (f_obj->complete_cmd(
5542                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5543                                         break;
5544 
5545                         } else {
5546                                 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5547 
5548                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5549                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5550                                 f_obj->complete_cmd(bp, f_obj,
5551                                                     BNX2X_F_CMD_AFEX_UPDATE);
5552 
5553                                 /* We will perform the Queues update from
5554                                  * sp_rtnl task as all Queue SP operations
5555                                  * should run under rtnl_lock.
5556                                  */
5557                                 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5558                         }
5559 
5560                         goto next_spqe;
5561 
5562                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5563                         f_obj->complete_cmd(bp, f_obj,
5564                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5565                         bnx2x_after_afex_vif_lists(bp, elem);
5566                         goto next_spqe;
5567                 case EVENT_RING_OPCODE_FUNCTION_START:
5568                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5569                            "got FUNC_START ramrod\n");
5570                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5571                                 break;
5572 
5573                         goto next_spqe;
5574 
5575                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5576                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5577                            "got FUNC_STOP ramrod\n");
5578                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5579                                 break;
5580 
5581                         goto next_spqe;
5582 
5583                 case EVENT_RING_OPCODE_SET_TIMESYNC:
5584                         DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5585                            "got set_timesync ramrod completion\n");
5586                         if (f_obj->complete_cmd(bp, f_obj,
5587                                                 BNX2X_F_CMD_SET_TIMESYNC))
5588                                 break;
5589                         goto next_spqe;
5590                 }
5591 
5592                 switch (opcode | bp->state) {
5593                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5594                       BNX2X_STATE_OPEN):
5595                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5596                       BNX2X_STATE_OPENING_WAIT4_PORT):
5597                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5598                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5599                         cid = elem->message.data.eth_event.echo &
5600                                 BNX2X_SWCID_MASK;
5601                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5602                            cid);
5603                         rss_raw->clear_pending(rss_raw);
5604                         break;
5605 
5606                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5607                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5608                 case (EVENT_RING_OPCODE_SET_MAC |
5609                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5610                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5611                       BNX2X_STATE_OPEN):
5612                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5613                       BNX2X_STATE_DIAG):
5614                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5615                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5616                         DP(BNX2X_MSG_SP, "got (un)set vlan/mac ramrod\n");
5617                         bnx2x_handle_classification_eqe(bp, elem);
5618                         break;
5619 
5620                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5621                       BNX2X_STATE_OPEN):
5622                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5623                       BNX2X_STATE_DIAG):
5624                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5625                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5626                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5627                         bnx2x_handle_mcast_eqe(bp);
5628                         break;
5629 
5630                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5631                       BNX2X_STATE_OPEN):
5632                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5633                       BNX2X_STATE_DIAG):
5634                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5635                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5636                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5637                         bnx2x_handle_rx_mode_eqe(bp);
5638                         break;
5639                 default:
5640                         /* unknown event log error and continue */
5641                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5642                                   elem->message.opcode, bp->state);
5643                 }
5644 next_spqe:
5645                 spqe_cnt++;
5646         } /* for */
5647 
5648         smp_mb__before_atomic();
5649         atomic_add(spqe_cnt, &bp->eq_spq_left);
5650 
5651         bp->eq_cons = sw_cons;
5652         bp->eq_prod = sw_prod;
5653         /* Make sure that above mem writes were issued towards the memory */
5654         smp_wmb();
5655 
5656         /* update producer */
5657         bnx2x_update_eq_prod(bp, bp->eq_prod);
5658 }
5659 
5660 static void bnx2x_sp_task(struct work_struct *work)
5661 {
5662         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5663 
5664         DP(BNX2X_MSG_SP, "sp task invoked\n");
5665 
5666         /* make sure the atomic interrupt_occurred has been written */
5667         smp_rmb();
5668         if (atomic_read(&bp->interrupt_occurred)) {
5669 
5670                 /* what work needs to be performed? */
5671                 u16 status = bnx2x_update_dsb_idx(bp);
5672 
5673                 DP(BNX2X_MSG_SP, "status %x\n", status);
5674                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5675                 atomic_set(&bp->interrupt_occurred, 0);
5676 
5677                 /* HW attentions */
5678                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5679                         bnx2x_attn_int(bp);
5680                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5681                 }
5682 
5683                 /* SP events: STAT_QUERY and others */
5684                 if (status & BNX2X_DEF_SB_IDX) {
5685                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5686 
5687                 if (FCOE_INIT(bp) &&
5688                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5689                                 /* Prevent local bottom-halves from running as
5690                                  * we are going to change the local NAPI list.
5691                                  */
5692                                 local_bh_disable();
5693                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5694                                 local_bh_enable();
5695                         }
5696 
5697                         /* Handle EQ completions */
5698                         bnx2x_eq_int(bp);
5699                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5700                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5701 
5702                         status &= ~BNX2X_DEF_SB_IDX;
5703                 }
5704 
5705                 /* if status is non zero then perhaps something went wrong */
5706                 if (unlikely(status))
5707                         DP(BNX2X_MSG_SP,
5708                            "got an unknown interrupt! (status 0x%x)\n", status);
5709 
5710                 /* ack status block only if something was actually handled */
5711                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5712                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5713         }
5714 
5715         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5716         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5717                                &bp->sp_state)) {
5718                 bnx2x_link_report(bp);
5719                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5720         }
5721 }
5722 
5723 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5724 {
5725         struct net_device *dev = dev_instance;
5726         struct bnx2x *bp = netdev_priv(dev);
5727 
5728         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5729                      IGU_INT_DISABLE, 0);
5730 
5731 #ifdef BNX2X_STOP_ON_ERROR
5732         if (unlikely(bp->panic))
5733                 return IRQ_HANDLED;
5734 #endif
5735 
5736         if (CNIC_LOADED(bp)) {
5737                 struct cnic_ops *c_ops;
5738 
5739                 rcu_read_lock();
5740                 c_ops = rcu_dereference(bp->cnic_ops);
5741                 if (c_ops)
5742                         c_ops->cnic_handler(bp->cnic_data, NULL);
5743                 rcu_read_unlock();
5744         }
5745 
5746         /* schedule sp task to perform default status block work, ack
5747          * attentions and enable interrupts.
5748          */
5749         bnx2x_schedule_sp_task(bp);
5750 
5751         return IRQ_HANDLED;
5752 }
5753 
5754 /* end of slow path */
5755 
5756 void bnx2x_drv_pulse(struct bnx2x *bp)
5757 {
5758         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5759                  bp->fw_drv_pulse_wr_seq);
5760 }
5761 
5762 static void bnx2x_timer(unsigned long data)
5763 {
5764         struct bnx2x *bp = (struct bnx2x *) data;
5765 
5766         if (!netif_running(bp->dev))
5767                 return;
5768 
5769         if (IS_PF(bp) &&
5770             !BP_NOMCP(bp)) {
5771                 int mb_idx = BP_FW_MB_IDX(bp);
5772                 u16 drv_pulse;
5773                 u16 mcp_pulse;
5774 
5775                 ++bp->fw_drv_pulse_wr_seq;
5776                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5777                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5778                 bnx2x_drv_pulse(bp);
5779 
5780                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5781                              MCP_PULSE_SEQ_MASK);
5782                 /* The delta between driver pulse and mcp response
5783                  * should not get too big. If the MFW is more than 5 pulses
5784                  * behind, we should worry about it enough to generate an error
5785                  * log.
5786                  */
5787                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5788                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5789                                   drv_pulse, mcp_pulse);
5790         }
5791 
5792         if (bp->state == BNX2X_STATE_OPEN)
5793                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5794 
5795         /* sample pf vf bulletin board for new posts from pf */
5796         if (IS_VF(bp))
5797                 bnx2x_timer_sriov(bp);
5798 
5799         mod_timer(&bp->timer, jiffies + bp->current_interval);
5800 }
5801 
5802 /* end of Statistics */
5803 
5804 /* nic init */
5805 
5806 /*
5807  * nic init service functions
5808  */
5809 
5810 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5811 {
5812         u32 i;
5813         if (!(len%4) && !(addr%4))
5814                 for (i = 0; i < len; i += 4)
5815                         REG_WR(bp, addr + i, fill);
5816         else
5817                 for (i = 0; i < len; i++)
5818                         REG_WR8(bp, addr + i, fill);
5819 }
5820 
5821 /* helper: writes FP SP data to FW - data_size in dwords */
5822 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5823                                 int fw_sb_id,
5824                                 u32 *sb_data_p,
5825                                 u32 data_size)
5826 {
5827         int index;
5828         for (index = 0; index < data_size; index++)
5829                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5830                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5831                         sizeof(u32)*index,
5832                         *(sb_data_p + index));
5833 }
5834 
5835 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5836 {
5837         u32 *sb_data_p;
5838         u32 data_size = 0;
5839         struct hc_status_block_data_e2 sb_data_e2;
5840         struct hc_status_block_data_e1x sb_data_e1x;
5841 
5842         /* disable the function first */
5843         if (!CHIP_IS_E1x(bp)) {
5844                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5845                 sb_data_e2.common.state = SB_DISABLED;
5846                 sb_data_e2.common.p_func.vf_valid = false;
5847                 sb_data_p = (u32 *)&sb_data_e2;
5848                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5849         } else {
5850                 memset(&sb_data_e1x, 0,
5851                        sizeof(struct hc_status_block_data_e1x));
5852                 sb_data_e1x.common.state = SB_DISABLED;
5853                 sb_data_e1x.common.p_func.vf_valid = false;
5854                 sb_data_p = (u32 *)&sb_data_e1x;
5855                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5856         }
5857         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5858 
5859         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5860                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5861                         CSTORM_STATUS_BLOCK_SIZE);
5862         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5863                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5864                         CSTORM_SYNC_BLOCK_SIZE);
5865 }
5866 
5867 /* helper:  writes SP SB data to FW */
5868 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5869                 struct hc_sp_status_block_data *sp_sb_data)
5870 {
5871         int func = BP_FUNC(bp);
5872         int i;
5873         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5874                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5875                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5876                         i*sizeof(u32),
5877                         *((u32 *)sp_sb_data + i));
5878 }
5879 
5880 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5881 {
5882         int func = BP_FUNC(bp);
5883         struct hc_sp_status_block_data sp_sb_data;
5884         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5885 
5886         sp_sb_data.state = SB_DISABLED;
5887         sp_sb_data.p_func.vf_valid = false;
5888 
5889         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5890 
5891         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5892                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5893                         CSTORM_SP_STATUS_BLOCK_SIZE);
5894         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5895                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5896                         CSTORM_SP_SYNC_BLOCK_SIZE);
5897 }
5898 
5899 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5900                                            int igu_sb_id, int igu_seg_id)
5901 {
5902         hc_sm->igu_sb_id = igu_sb_id;
5903         hc_sm->igu_seg_id = igu_seg_id;
5904         hc_sm->timer_value = 0xFF;
5905         hc_sm->time_to_expire = 0xFFFFFFFF;
5906 }
5907 
5908 /* allocates state machine ids. */
5909 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5910 {
5911         /* zero out state machine indices */
5912         /* rx indices */
5913         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5914 
5915         /* tx indices */
5916         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5917         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5918         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5919         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5920 
5921         /* map indices */
5922         /* rx indices */
5923         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5924                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5925 
5926         /* tx indices */
5927         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5928                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5929         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5930                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5931         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5932                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5933         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5934                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5935 }
5936 
5937 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5938                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5939 {
5940         int igu_seg_id;
5941 
5942         struct hc_status_block_data_e2 sb_data_e2;
5943         struct hc_status_block_data_e1x sb_data_e1x;
5944         struct hc_status_block_sm  *hc_sm_p;
5945         int data_size;
5946         u32 *sb_data_p;
5947 
5948         if (CHIP_INT_MODE_IS_BC(bp))
5949                 igu_seg_id = HC_SEG_ACCESS_NORM;
5950         else
5951                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5952 
5953         bnx2x_zero_fp_sb(bp, fw_sb_id);
5954 
5955         if (!CHIP_IS_E1x(bp)) {
5956                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5957                 sb_data_e2.common.state = SB_ENABLED;
5958                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5959                 sb_data_e2.common.p_func.vf_id = vfid;
5960                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5961                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5962                 sb_data_e2.common.same_igu_sb_1b = true;
5963                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5964                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5965                 hc_sm_p = sb_data_e2.common.state_machine;
5966                 sb_data_p = (u32 *)&sb_data_e2;
5967                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5968                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5969         } else {
5970                 memset(&sb_data_e1x, 0,
5971                        sizeof(struct hc_status_block_data_e1x));
5972                 sb_data_e1x.common.state = SB_ENABLED;
5973                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5974                 sb_data_e1x.common.p_func.vf_id = 0xff;
5975                 sb_data_e1x.common.p_func.vf_valid = false;
5976                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5977                 sb_data_e1x.common.same_igu_sb_1b = true;
5978                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5979                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5980                 hc_sm_p = sb_data_e1x.common.state_machine;
5981                 sb_data_p = (u32 *)&sb_data_e1x;
5982                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5983                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5984         }
5985 
5986         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5987                                        igu_sb_id, igu_seg_id);
5988         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5989                                        igu_sb_id, igu_seg_id);
5990 
5991         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5992 
5993         /* write indices to HW - PCI guarantees endianity of regpairs */
5994         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5995 }
5996 
5997 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5998                                      u16 tx_usec, u16 rx_usec)
5999 {
6000         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
6001                                     false, rx_usec);
6002         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6003                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
6004                                        tx_usec);
6005         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6006                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
6007                                        tx_usec);
6008         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6009                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
6010                                        tx_usec);
6011 }
6012 
6013 static void bnx2x_init_def_sb(struct bnx2x *bp)
6014 {
6015         struct host_sp_status_block *def_sb = bp->def_status_blk;
6016         dma_addr_t mapping = bp->def_status_blk_mapping;
6017         int igu_sp_sb_index;
6018         int igu_seg_id;
6019         int port = BP_PORT(bp);
6020         int func = BP_FUNC(bp);
6021         int reg_offset, reg_offset_en5;
6022         u64 section;
6023         int index;
6024         struct hc_sp_status_block_data sp_sb_data;
6025         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
6026 
6027         if (CHIP_INT_MODE_IS_BC(bp)) {
6028                 igu_sp_sb_index = DEF_SB_IGU_ID;
6029                 igu_seg_id = HC_SEG_ACCESS_DEF;
6030         } else {
6031                 igu_sp_sb_index = bp->igu_dsb_id;
6032                 igu_seg_id = IGU_SEG_ACCESS_DEF;
6033         }
6034 
6035         /* ATTN */
6036         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6037                                             atten_status_block);
6038         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
6039 
6040         bp->attn_state = 0;
6041 
6042         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6043                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6044         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6045                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
6046         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
6047                 int sindex;
6048                 /* take care of sig[0]..sig[4] */
6049                 for (sindex = 0; sindex < 4; sindex++)
6050                         bp->attn_group[index].sig[sindex] =
6051                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
6052 
6053                 if (!CHIP_IS_E1x(bp))
6054                         /*
6055                          * enable5 is separate from the rest of the registers,
6056                          * and therefore the address skip is 4
6057                          * and not 16 between the different groups
6058                          */
6059                         bp->attn_group[index].sig[4] = REG_RD(bp,
6060                                         reg_offset_en5 + 0x4*index);
6061                 else
6062                         bp->attn_group[index].sig[4] = 0;
6063         }
6064 
6065         if (bp->common.int_block == INT_BLOCK_HC) {
6066                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6067                                      HC_REG_ATTN_MSG0_ADDR_L);
6068 
6069                 REG_WR(bp, reg_offset, U64_LO(section));
6070                 REG_WR(bp, reg_offset + 4, U64_HI(section));
6071         } else if (!CHIP_IS_E1x(bp)) {
6072                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6073                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6074         }
6075 
6076         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6077                                             sp_sb);
6078 
6079         bnx2x_zero_sp_sb(bp);
6080 
6081         /* PCI guarantees endianity of regpairs */
6082         sp_sb_data.state                = SB_ENABLED;
6083         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
6084         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
6085         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
6086         sp_sb_data.igu_seg_id           = igu_seg_id;
6087         sp_sb_data.p_func.pf_id         = func;
6088         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
6089         sp_sb_data.p_func.vf_id         = 0xff;
6090 
6091         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
6092 
6093         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6094 }
6095 
6096 void bnx2x_update_coalesce(struct bnx2x *bp)
6097 {
6098         int i;
6099 
6100         for_each_eth_queue(bp, i)
6101                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
6102                                          bp->tx_ticks, bp->rx_ticks);
6103 }
6104 
6105 static void bnx2x_init_sp_ring(struct bnx2x *bp)
6106 {
6107         spin_lock_init(&bp->spq_lock);
6108         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
6109 
6110         bp->spq_prod_idx = 0;
6111         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6112         bp->spq_prod_bd = bp->spq;
6113         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
6114 }
6115 
6116 static void bnx2x_init_eq_ring(struct bnx2x *bp)
6117 {
6118         int i;
6119         for (i = 1; i <= NUM_EQ_PAGES; i++) {
6120                 union event_ring_elem *elem =
6121                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6122 
6123                 elem->next_page.addr.hi =
6124                         cpu_to_le32(U64_HI(bp->eq_mapping +
6125                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6126                 elem->next_page.addr.lo =
6127                         cpu_to_le32(U64_LO(bp->eq_mapping +
6128                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
6129         }
6130         bp->eq_cons = 0;
6131         bp->eq_prod = NUM_EQ_DESC;
6132         bp->eq_cons_sb = BNX2X_EQ_INDEX;
6133         /* we want a warning message before it gets wrought... */
6134         atomic_set(&bp->eq_spq_left,
6135                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
6136 }
6137 
6138 /* called with netif_addr_lock_bh() */
6139 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6140                                unsigned long rx_mode_flags,
6141                                unsigned long rx_accept_flags,
6142                                unsigned long tx_accept_flags,
6143                                unsigned long ramrod_flags)
6144 {
6145         struct bnx2x_rx_mode_ramrod_params ramrod_param;
6146         int rc;
6147 
6148         memset(&ramrod_param, 0, sizeof(ramrod_param));
6149 
6150         /* Prepare ramrod parameters */
6151         ramrod_param.cid = 0;
6152         ramrod_param.cl_id = cl_id;
6153         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6154         ramrod_param.func_id = BP_FUNC(bp);
6155 
6156         ramrod_param.pstate = &bp->sp_state;
6157         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6158 
6159         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6160         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6161 
6162         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6163 
6164         ramrod_param.ramrod_flags = ramrod_flags;
6165         ramrod_param.rx_mode_flags = rx_mode_flags;
6166 
6167         ramrod_param.rx_accept_flags = rx_accept_flags;
6168         ramrod_param.tx_accept_flags = tx_accept_flags;
6169 
6170         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6171         if (rc < 0) {
6172                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6173                 return rc;
6174         }
6175 
6176         return 0;
6177 }
6178 
6179 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6180                                    unsigned long *rx_accept_flags,
6181                                    unsigned long *tx_accept_flags)
6182 {
6183         /* Clear the flags first */
6184         *rx_accept_flags = 0;
6185         *tx_accept_flags = 0;
6186 
6187         switch (rx_mode) {
6188         case BNX2X_RX_MODE_NONE:
6189                 /*
6190                  * 'drop all' supersedes any accept flags that may have been
6191                  * passed to the function.
6192                  */
6193                 break;
6194         case BNX2X_RX_MODE_NORMAL:
6195                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6196                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6197                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6198 
6199                 /* internal switching mode */
6200                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6201                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6202                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6203 
6204                 if (bp->accept_any_vlan) {
6205                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6206                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6207                 }
6208 
6209                 break;
6210         case BNX2X_RX_MODE_ALLMULTI:
6211                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6212                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6213                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6214 
6215                 /* internal switching mode */
6216                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6217                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6218                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6219 
6220                 if (bp->accept_any_vlan) {
6221                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6222                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6223                 }
6224 
6225                 break;
6226         case BNX2X_RX_MODE_PROMISC:
6227                 /* According to definition of SI mode, iface in promisc mode
6228                  * should receive matched and unmatched (in resolution of port)
6229                  * unicast packets.
6230                  */
6231                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6232                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6233                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6234                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6235 
6236                 /* internal switching mode */
6237                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6238                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6239 
6240                 if (IS_MF_SI(bp))
6241                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6242                 else
6243                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6244 
6245                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6246                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6247 
6248                 break;
6249         default:
6250                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6251                 return -EINVAL;
6252         }
6253 
6254         return 0;
6255 }
6256 
6257 /* called with netif_addr_lock_bh() */
6258 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6259 {
6260         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6261         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6262         int rc;
6263 
6264         if (!NO_FCOE(bp))
6265                 /* Configure rx_mode of FCoE Queue */
6266                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6267 
6268         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6269                                      &tx_accept_flags);
6270         if (rc)
6271                 return rc;
6272 
6273         __set_bit(RAMROD_RX, &ramrod_flags);
6274         __set_bit(RAMROD_TX, &ramrod_flags);
6275 
6276         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6277                                    rx_accept_flags, tx_accept_flags,
6278                                    ramrod_flags);
6279 }
6280 
6281 static void bnx2x_init_internal_common(struct bnx2x *bp)
6282 {
6283         int i;
6284 
6285         /* Zero this manually as its initialization is
6286            currently missing in the initTool */
6287         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6288                 REG_WR(bp, BAR_USTRORM_INTMEM +
6289                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
6290         if (!CHIP_IS_E1x(bp)) {
6291                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6292                         CHIP_INT_MODE_IS_BC(bp) ?
6293                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6294         }
6295 }
6296 
6297 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6298 {
6299         switch (load_code) {
6300         case FW_MSG_CODE_DRV_LOAD_COMMON:
6301         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6302                 bnx2x_init_internal_common(bp);
6303                 /* no break */
6304 
6305         case FW_MSG_CODE_DRV_LOAD_PORT:
6306                 /* nothing to do */
6307                 /* no break */
6308 
6309         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6310                 /* internal memory per function is
6311                    initialized inside bnx2x_pf_init */
6312                 break;
6313 
6314         default:
6315                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6316                 break;
6317         }
6318 }
6319 
6320 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6321 {
6322         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6323 }
6324 
6325 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6326 {
6327         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6328 }
6329 
6330 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6331 {
6332         if (CHIP_IS_E1x(fp->bp))
6333                 return BP_L_ID(fp->bp) + fp->index;
6334         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6335                 return bnx2x_fp_igu_sb_id(fp);
6336 }
6337 
6338 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6339 {