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Version: 2.6.32 2.6.33 2.6.34 2.6.35 2.6.36 2.6.37 2.6.38 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9
Architecture: x86 arm avr32 blackfin m68k m68knommu microblaze mips powerpc sh
1 /* bnx2x_main.c: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17 18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19 20 #include <linux/module.h> 21 #include <linux/moduleparam.h> 22 #include <linux/kernel.h> 23 #include <linux/device.h> /* for dev_info() */ 24 #include <linux/timer.h> 25 #include <linux/errno.h> 26 #include <linux/ioport.h> 27 #include <linux/slab.h> 28 #include <linux/interrupt.h> 29 #include <linux/pci.h> 30 #include <linux/init.h> 31 #include <linux/netdevice.h> 32 #include <linux/etherdevice.h> 33 #include <linux/skbuff.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/bitops.h> 36 #include <linux/irq.h> 37 #include <linux/delay.h> 38 #include <asm/byteorder.h> 39 #include <linux/time.h> 40 #include <linux/ethtool.h> 41 #include <linux/mii.h> 42 #include <linux/if_vlan.h> 43 #include <net/ip.h> 44 #include <net/ipv6.h> 45 #include <net/tcp.h> 46 #include <net/checksum.h> 47 #include <net/ip6_checksum.h> 48 #include <linux/workqueue.h> 49 #include <linux/crc32.h> 50 #include <linux/crc32c.h> 51 #include <linux/prefetch.h> 52 #include <linux/zlib.h> 53 #include <linux/io.h> 54 #include <linux/semaphore.h> 55 #include <linux/stringify.h> 56 #include <linux/vmalloc.h> 57 58 #include "bnx2x.h" 59 #include "bnx2x_init.h" 60 #include "bnx2x_init_ops.h" 61 #include "bnx2x_cmn.h" 62 #include "bnx2x_vfpf.h" 63 #include "bnx2x_dcb.h" 64 #include "bnx2x_sp.h" 65 66 #include <linux/firmware.h> 67 #include "bnx2x_fw_file_hdr.h" 68 /* FW files */ 69 #define FW_FILE_VERSION \ 70 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ 71 __stringify(BCM_5710_FW_MINOR_VERSION) "." \ 72 __stringify(BCM_5710_FW_REVISION_VERSION) "." \ 73 __stringify(BCM_5710_FW_ENGINEERING_VERSION) 74 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" 75 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" 76 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" 77 78 #define MAC_LEADING_ZERO_CNT (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN) 79 80 /* Time in jiffies before concluding the transmitter is hung */ 81 #define TX_TIMEOUT (5*HZ) 82 83 static char version[] = 84 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " 85 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 86 87 MODULE_AUTHOR("Eliezer Tamir"); 88 MODULE_DESCRIPTION("Broadcom NetXtreme II " 89 "BCM57710/57711/57711E/" 90 "57712/57712_MF/57800/57800_MF/57810/57810_MF/" 91 "57840/57840_MF Driver"); 92 MODULE_LICENSE("GPL"); 93 MODULE_VERSION(DRV_MODULE_VERSION); 94 MODULE_FIRMWARE(FW_FILE_NAME_E1); 95 MODULE_FIRMWARE(FW_FILE_NAME_E1H); 96 MODULE_FIRMWARE(FW_FILE_NAME_E2); 97 98 99 int num_queues; 100 module_param(num_queues, int, 0); 101 MODULE_PARM_DESC(num_queues, 102 " Set number of queues (default is as a number of CPUs)"); 103 104 static int disable_tpa; 105 module_param(disable_tpa, int, 0); 106 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); 107 108 #define INT_MODE_INTx 1 109 #define INT_MODE_MSI 2 110 int int_mode; 111 module_param(int_mode, int, 0); 112 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " 113 "(1 INT#x; 2 MSI)"); 114 115 static int dropless_fc; 116 module_param(dropless_fc, int, 0); 117 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); 118 119 static int mrrs = -1; 120 module_param(mrrs, int, 0); 121 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); 122 123 static int debug; 124 module_param(debug, int, 0); 125 MODULE_PARM_DESC(debug, " Default debug msglevel"); 126 127 128 129 struct workqueue_struct *bnx2x_wq; 130 131 struct bnx2x_mac_vals { 132 u32 xmac_addr; 133 u32 xmac_val; 134 u32 emac_addr; 135 u32 emac_val; 136 u32 umac_addr; 137 u32 umac_val; 138 u32 bmac_addr; 139 u32 bmac_val[2]; 140 }; 141 142 enum bnx2x_board_type { 143 BCM57710 = 0, 144 BCM57711, 145 BCM57711E, 146 BCM57712, 147 BCM57712_MF, 148 BCM57712_VF, 149 BCM57800, 150 BCM57800_MF, 151 BCM57800_VF, 152 BCM57810, 153 BCM57810_MF, 154 BCM57810_VF, 155 BCM57840_4_10, 156 BCM57840_2_20, 157 BCM57840_MF, 158 BCM57840_VF, 159 BCM57811, 160 BCM57811_MF, 161 BCM57840_O, 162 BCM57840_MFO, 163 BCM57811_VF 164 }; 165 166 /* indexed by board_type, above */ 167 static struct { 168 char *name; 169 } board_info[] = { 170 [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, 171 [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, 172 [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, 173 [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, 174 [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, 175 [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" }, 176 [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, 177 [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, 178 [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" }, 179 [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, 180 [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, 181 [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" }, 182 [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" }, 183 [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" }, 184 [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" }, 185 [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }, 186 [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" }, 187 [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" }, 188 [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, 189 [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" }, 190 [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" } 191 }; 192 193 #ifndef PCI_DEVICE_ID_NX2_57710 194 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 195 #endif 196 #ifndef PCI_DEVICE_ID_NX2_57711 197 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 198 #endif 199 #ifndef PCI_DEVICE_ID_NX2_57711E 200 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E 201 #endif 202 #ifndef PCI_DEVICE_ID_NX2_57712 203 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 204 #endif 205 #ifndef PCI_DEVICE_ID_NX2_57712_MF 206 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF 207 #endif 208 #ifndef PCI_DEVICE_ID_NX2_57712_VF 209 #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF 210 #endif 211 #ifndef PCI_DEVICE_ID_NX2_57800 212 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 213 #endif 214 #ifndef PCI_DEVICE_ID_NX2_57800_MF 215 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF 216 #endif 217 #ifndef PCI_DEVICE_ID_NX2_57800_VF 218 #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF 219 #endif 220 #ifndef PCI_DEVICE_ID_NX2_57810 221 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 222 #endif 223 #ifndef PCI_DEVICE_ID_NX2_57810_MF 224 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF 225 #endif 226 #ifndef PCI_DEVICE_ID_NX2_57840_O 227 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE 228 #endif 229 #ifndef PCI_DEVICE_ID_NX2_57810_VF 230 #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF 231 #endif 232 #ifndef PCI_DEVICE_ID_NX2_57840_4_10 233 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10 234 #endif 235 #ifndef PCI_DEVICE_ID_NX2_57840_2_20 236 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20 237 #endif 238 #ifndef PCI_DEVICE_ID_NX2_57840_MFO 239 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE 240 #endif 241 #ifndef PCI_DEVICE_ID_NX2_57840_MF 242 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF 243 #endif 244 #ifndef PCI_DEVICE_ID_NX2_57840_VF 245 #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF 246 #endif 247 #ifndef PCI_DEVICE_ID_NX2_57811 248 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811 249 #endif 250 #ifndef PCI_DEVICE_ID_NX2_57811_MF 251 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF 252 #endif 253 #ifndef PCI_DEVICE_ID_NX2_57811_VF 254 #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF 255 #endif 256 257 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { 258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, 259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, 260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, 261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, 262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, 263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF }, 264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, 265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, 266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF }, 267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, 268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, 269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O }, 270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 }, 271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 }, 272 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF }, 273 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO }, 274 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, 275 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF }, 276 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 }, 277 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF }, 278 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF }, 279 { 0 } 280 }; 281 282 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); 283 284 /* Global resources for unloading a previously loaded device */ 285 #define BNX2X_PREV_WAIT_NEEDED 1 286 static DEFINE_SEMAPHORE(bnx2x_prev_sem); 287 static LIST_HEAD(bnx2x_prev_list); 288 /**************************************************************************** 289 * General service functions 290 ****************************************************************************/ 291 292 static void __storm_memset_dma_mapping(struct bnx2x *bp, 293 u32 addr, dma_addr_t mapping) 294 { 295 REG_WR(bp, addr, U64_LO(mapping)); 296 REG_WR(bp, addr + 4, U64_HI(mapping)); 297 } 298 299 static void storm_memset_spq_addr(struct bnx2x *bp, 300 dma_addr_t mapping, u16 abs_fid) 301 { 302 u32 addr = XSEM_REG_FAST_MEMORY + 303 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); 304 305 __storm_memset_dma_mapping(bp, addr, mapping); 306 } 307 308 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, 309 u16 pf_id) 310 { 311 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), 312 pf_id); 313 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), 314 pf_id); 315 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), 316 pf_id); 317 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), 318 pf_id); 319 } 320 321 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, 322 u8 enable) 323 { 324 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), 325 enable); 326 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), 327 enable); 328 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), 329 enable); 330 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), 331 enable); 332 } 333 334 static void storm_memset_eq_data(struct bnx2x *bp, 335 struct event_ring_data *eq_data, 336 u16 pfid) 337 { 338 size_t size = sizeof(struct event_ring_data); 339 340 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); 341 342 __storm_memset_struct(bp, addr, size, (u32 *)eq_data); 343 } 344 345 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, 346 u16 pfid) 347 { 348 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); 349 REG_WR16(bp, addr, eq_prod); 350 } 351 352 /* used only at init 353 * locking is done by mcp 354 */ 355 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) 356 { 357 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 358 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); 359 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 360 PCICFG_VENDOR_ID_OFFSET); 361 } 362 363 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) 364 { 365 u32 val; 366 367 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 368 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); 369 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 370 PCICFG_VENDOR_ID_OFFSET); 371 372 return val; 373 } 374 375 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]" 376 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" 377 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]" 378 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" 379 #define DMAE_DP_DST_NONE "dst_addr [none]" 380 381 void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, int msglvl) 382 { 383 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; 384 385 switch (dmae->opcode & DMAE_COMMAND_DST) { 386 case DMAE_CMD_DST_PCI: 387 if (src_type == DMAE_CMD_SRC_PCI) 388 DP(msglvl, "DMAE: opcode 0x%08x\n" 389 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" 390 "comp_addr [%x:%08x], comp_val 0x%08x\n", 391 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 392 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 393 dmae->comp_addr_hi, dmae->comp_addr_lo, 394 dmae->comp_val); 395 else 396 DP(msglvl, "DMAE: opcode 0x%08x\n" 397 "src [%08x], len [%d*4], dst [%x:%08x]\n" 398 "comp_addr [%x:%08x], comp_val 0x%08x\n", 399 dmae->opcode, dmae->src_addr_lo >> 2, 400 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 401 dmae->comp_addr_hi, dmae->comp_addr_lo, 402 dmae->comp_val); 403 break; 404 case DMAE_CMD_DST_GRC: 405 if (src_type == DMAE_CMD_SRC_PCI) 406 DP(msglvl, "DMAE: opcode 0x%08x\n" 407 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" 408 "comp_addr [%x:%08x], comp_val 0x%08x\n", 409 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 410 dmae->len, dmae->dst_addr_lo >> 2, 411 dmae->comp_addr_hi, dmae->comp_addr_lo, 412 dmae->comp_val); 413 else 414 DP(msglvl, "DMAE: opcode 0x%08x\n" 415 "src [%08x], len [%d*4], dst [%08x]\n" 416 "comp_addr [%x:%08x], comp_val 0x%08x\n", 417 dmae->opcode, dmae->src_addr_lo >> 2, 418 dmae->len, dmae->dst_addr_lo >> 2, 419 dmae->comp_addr_hi, dmae->comp_addr_lo, 420 dmae->comp_val); 421 break; 422 default: 423 if (src_type == DMAE_CMD_SRC_PCI) 424 DP(msglvl, "DMAE: opcode 0x%08x\n" 425 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" 426 "comp_addr [%x:%08x] comp_val 0x%08x\n", 427 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 428 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 429 dmae->comp_val); 430 else 431 DP(msglvl, "DMAE: opcode 0x%08x\n" 432 "src_addr [%08x] len [%d * 4] dst_addr [none]\n" 433 "comp_addr [%x:%08x] comp_val 0x%08x\n", 434 dmae->opcode, dmae->src_addr_lo >> 2, 435 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 436 dmae->comp_val); 437 break; 438 } 439 } 440 441 /* copy command into DMAE command memory and set DMAE command go */ 442 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) 443 { 444 u32 cmd_offset; 445 int i; 446 447 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); 448 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { 449 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); 450 } 451 REG_WR(bp, dmae_reg_go_c[idx], 1); 452 } 453 454 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) 455 { 456 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | 457 DMAE_CMD_C_ENABLE); 458 } 459 460 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) 461 { 462 return opcode & ~DMAE_CMD_SRC_RESET; 463 } 464 465 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 466 bool with_comp, u8 comp_type) 467 { 468 u32 opcode = 0; 469 470 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | 471 (dst_type << DMAE_COMMAND_DST_SHIFT)); 472 473 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); 474 475 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); 476 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | 477 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); 478 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); 479 480 #ifdef __BIG_ENDIAN 481 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; 482 #else 483 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; 484 #endif 485 if (with_comp) 486 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); 487 return opcode; 488 } 489 490 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, 491 struct dmae_command *dmae, 492 u8 src_type, u8 dst_type) 493 { 494 memset(dmae, 0, sizeof(struct dmae_command)); 495 496 /* set the opcode */ 497 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, 498 true, DMAE_COMP_PCI); 499 500 /* fill in the completion parameters */ 501 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); 502 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); 503 dmae->comp_val = DMAE_COMP_VAL; 504 } 505 506 /* issue a dmae command over the init-channel and wait for completion */ 507 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae) 508 { 509 u32 *wb_comp = bnx2x_sp(bp, wb_comp); 510 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; 511 int rc = 0; 512 513 /* 514 * Lock the dmae channel. Disable BHs to prevent a dead-lock 515 * as long as this code is called both from syscall context and 516 * from ndo_set_rx_mode() flow that may be called from BH. 517 */ 518 spin_lock_bh(&bp->dmae_lock); 519 520 /* reset completion */ 521 *wb_comp = 0; 522 523 /* post the command on the channel used for initializations */ 524 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); 525 526 /* wait for completion */ 527 udelay(5); 528 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { 529 530 if (!cnt || 531 (bp->recovery_state != BNX2X_RECOVERY_DONE && 532 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { 533 BNX2X_ERR("DMAE timeout!\n"); 534 rc = DMAE_TIMEOUT; 535 goto unlock; 536 } 537 cnt--; 538 udelay(50); 539 } 540 if (*wb_comp & DMAE_PCI_ERR_FLAG) { 541 BNX2X_ERR("DMAE PCI error!\n"); 542 rc = DMAE_PCI_ERROR; 543 } 544 545 unlock: 546 spin_unlock_bh(&bp->dmae_lock); 547 return rc; 548 } 549 550 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 551 u32 len32) 552 { 553 struct dmae_command dmae; 554 555 if (!bp->dmae_ready) { 556 u32 *data = bnx2x_sp(bp, wb_data[0]); 557 558 if (CHIP_IS_E1(bp)) 559 bnx2x_init_ind_wr(bp, dst_addr, data, len32); 560 else 561 bnx2x_init_str_wr(bp, dst_addr, data, len32); 562 return; 563 } 564 565 /* set opcode and fixed command fields */ 566 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); 567 568 /* fill in addresses and len */ 569 dmae.src_addr_lo = U64_LO(dma_addr); 570 dmae.src_addr_hi = U64_HI(dma_addr); 571 dmae.dst_addr_lo = dst_addr >> 2; 572 dmae.dst_addr_hi = 0; 573 dmae.len = len32; 574 575 /* issue the command and wait for completion */ 576 bnx2x_issue_dmae_with_comp(bp, &dmae); 577 } 578 579 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) 580 { 581 struct dmae_command dmae; 582 583 if (!bp->dmae_ready) { 584 u32 *data = bnx2x_sp(bp, wb_data[0]); 585 int i; 586 587 if (CHIP_IS_E1(bp)) 588 for (i = 0; i < len32; i++) 589 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); 590 else 591 for (i = 0; i < len32; i++) 592 data[i] = REG_RD(bp, src_addr + i*4); 593 594 return; 595 } 596 597 /* set opcode and fixed command fields */ 598 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); 599 600 /* fill in addresses and len */ 601 dmae.src_addr_lo = src_addr >> 2; 602 dmae.src_addr_hi = 0; 603 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); 604 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); 605 dmae.len = len32; 606 607 /* issue the command and wait for completion */ 608 bnx2x_issue_dmae_with_comp(bp, &dmae); 609 } 610 611 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, 612 u32 addr, u32 len) 613 { 614 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); 615 int offset = 0; 616 617 while (len > dmae_wr_max) { 618 bnx2x_write_dmae(bp, phys_addr + offset, 619 addr + offset, dmae_wr_max); 620 offset += dmae_wr_max * 4; 621 len -= dmae_wr_max; 622 } 623 624 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); 625 } 626 627 static int bnx2x_mc_assert(struct bnx2x *bp) 628 { 629 char last_idx; 630 int i, rc = 0; 631 u32 row0, row1, row2, row3; 632 633 /* XSTORM */ 634 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + 635 XSTORM_ASSERT_LIST_INDEX_OFFSET); 636 if (last_idx) 637 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 638 639 /* print the asserts */ 640 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 641 642 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + 643 XSTORM_ASSERT_LIST_OFFSET(i)); 644 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + 645 XSTORM_ASSERT_LIST_OFFSET(i) + 4); 646 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + 647 XSTORM_ASSERT_LIST_OFFSET(i) + 8); 648 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + 649 XSTORM_ASSERT_LIST_OFFSET(i) + 12); 650 651 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 652 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 653 i, row3, row2, row1, row0); 654 rc++; 655 } else { 656 break; 657 } 658 } 659 660 /* TSTORM */ 661 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + 662 TSTORM_ASSERT_LIST_INDEX_OFFSET); 663 if (last_idx) 664 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 665 666 /* print the asserts */ 667 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 668 669 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + 670 TSTORM_ASSERT_LIST_OFFSET(i)); 671 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + 672 TSTORM_ASSERT_LIST_OFFSET(i) + 4); 673 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + 674 TSTORM_ASSERT_LIST_OFFSET(i) + 8); 675 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + 676 TSTORM_ASSERT_LIST_OFFSET(i) + 12); 677 678 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 679 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 680 i, row3, row2, row1, row0); 681 rc++; 682 } else { 683 break; 684 } 685 } 686 687 /* CSTORM */ 688 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + 689 CSTORM_ASSERT_LIST_INDEX_OFFSET); 690 if (last_idx) 691 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 692 693 /* print the asserts */ 694 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 695 696 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + 697 CSTORM_ASSERT_LIST_OFFSET(i)); 698 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + 699 CSTORM_ASSERT_LIST_OFFSET(i) + 4); 700 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + 701 CSTORM_ASSERT_LIST_OFFSET(i) + 8); 702 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + 703 CSTORM_ASSERT_LIST_OFFSET(i) + 12); 704 705 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 706 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 707 i, row3, row2, row1, row0); 708 rc++; 709 } else { 710 break; 711 } 712 } 713 714 /* USTORM */ 715 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + 716 USTORM_ASSERT_LIST_INDEX_OFFSET); 717 if (last_idx) 718 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 719 720 /* print the asserts */ 721 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 722 723 row0 = REG_RD(bp, BAR_USTRORM_INTMEM + 724 USTORM_ASSERT_LIST_OFFSET(i)); 725 row1 = REG_RD(bp, BAR_USTRORM_INTMEM + 726 USTORM_ASSERT_LIST_OFFSET(i) + 4); 727 row2 = REG_RD(bp, BAR_USTRORM_INTMEM + 728 USTORM_ASSERT_LIST_OFFSET(i) + 8); 729 row3 = REG_RD(bp, BAR_USTRORM_INTMEM + 730 USTORM_ASSERT_LIST_OFFSET(i) + 12); 731 732 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 733 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 734 i, row3, row2, row1, row0); 735 rc++; 736 } else { 737 break; 738 } 739 } 740 741 return rc; 742 } 743 744 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) 745 { 746 u32 addr, val; 747 u32 mark, offset; 748 __be32 data[9]; 749 int word; 750 u32 trace_shmem_base; 751 if (BP_NOMCP(bp)) { 752 BNX2X_ERR("NO MCP - can not dump\n"); 753 return; 754 } 755 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", 756 (bp->common.bc_ver & 0xff0000) >> 16, 757 (bp->common.bc_ver & 0xff00) >> 8, 758 (bp->common.bc_ver & 0xff)); 759 760 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); 761 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) 762 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val); 763 764 if (BP_PATH(bp) == 0) 765 trace_shmem_base = bp->common.shmem_base; 766 else 767 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); 768 addr = trace_shmem_base - 0x800; 769 770 /* validate TRCB signature */ 771 mark = REG_RD(bp, addr); 772 if (mark != MFW_TRACE_SIGNATURE) { 773 BNX2X_ERR("Trace buffer signature is missing."); 774 return ; 775 } 776 777 /* read cyclic buffer pointer */ 778 addr += 4; 779 mark = REG_RD(bp, addr); 780 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) 781 + ((mark + 0x3) & ~0x3) - 0x08000000; 782 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); 783 784 printk("%s", lvl); 785 786 /* dump buffer after the mark */ 787 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { 788 for (word = 0; word < 8; word++) 789 data[word] = htonl(REG_RD(bp, offset + 4*word)); 790 data[8] = 0x0; 791 pr_cont("%s", (char *)data); 792 } 793 794 /* dump buffer before the mark */ 795 for (offset = addr + 4; offset <= mark; offset += 0x8*4) { 796 for (word = 0; word < 8; word++) 797 data[word] = htonl(REG_RD(bp, offset + 4*word)); 798 data[8] = 0x0; 799 pr_cont("%s", (char *)data); 800 } 801 printk("%s" "end of fw dump\n", lvl); 802 } 803 804 static void bnx2x_fw_dump(struct bnx2x *bp) 805 { 806 bnx2x_fw_dump_lvl(bp, KERN_ERR); 807 } 808 809 static void bnx2x_hc_int_disable(struct bnx2x *bp) 810 { 811 int port = BP_PORT(bp); 812 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 813 u32 val = REG_RD(bp, addr); 814 815 /* in E1 we must use only PCI configuration space to disable 816 * MSI/MSIX capablility 817 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block 818 */ 819 if (CHIP_IS_E1(bp)) { 820 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on 821 * Use mask register to prevent from HC sending interrupts 822 * after we exit the function 823 */ 824 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); 825 826 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 827 HC_CONFIG_0_REG_INT_LINE_EN_0 | 828 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 829 } else 830 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 831 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 832 HC_CONFIG_0_REG_INT_LINE_EN_0 | 833 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 834 835 DP(NETIF_MSG_IFDOWN, 836 "write %x to HC %d (addr 0x%x)\n", 837 val, port, addr); 838 839 /* flush all outstanding writes */ 840 mmiowb(); 841 842 REG_WR(bp, addr, val); 843 if (REG_RD(bp, addr) != val) 844 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 845 } 846 847 static void bnx2x_igu_int_disable(struct bnx2x *bp) 848 { 849 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 850 851 val &= ~(IGU_PF_CONF_MSI_MSIX_EN | 852 IGU_PF_CONF_INT_LINE_EN | 853 IGU_PF_CONF_ATTN_BIT_EN); 854 855 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val); 856 857 /* flush all outstanding writes */ 858 mmiowb(); 859 860 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 861 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) 862 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 863 } 864 865 static void bnx2x_int_disable(struct bnx2x *bp) 866 { 867 if (bp->common.int_block == INT_BLOCK_HC) 868 bnx2x_hc_int_disable(bp); 869 else 870 bnx2x_igu_int_disable(bp); 871 } 872 873 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int) 874 { 875 int i; 876 u16 j; 877 struct hc_sp_status_block_data sp_sb_data; 878 int func = BP_FUNC(bp); 879 #ifdef BNX2X_STOP_ON_ERROR 880 u16 start = 0, end = 0; 881 u8 cos; 882 #endif 883 if (disable_int) 884 bnx2x_int_disable(bp); 885 886 bp->stats_state = STATS_STATE_DISABLED; 887 bp->eth_stats.unrecoverable_error++; 888 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); 889 890 BNX2X_ERR("begin crash dump -----------------\n"); 891 892 /* Indices */ 893 /* Common */ 894 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", 895 bp->def_idx, bp->def_att_idx, bp->attn_state, 896 bp->spq_prod_idx, bp->stats_counter); 897 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", 898 bp->def_status_blk->atten_status_block.attn_bits, 899 bp->def_status_blk->atten_status_block.attn_bits_ack, 900 bp->def_status_blk->atten_status_block.status_block_id, 901 bp->def_status_blk->atten_status_block.attn_bits_index); 902 BNX2X_ERR(" def ("); 903 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) 904 pr_cont("0x%x%s", 905 bp->def_status_blk->sp_sb.index_values[i], 906 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); 907 908 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 909 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + 910 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 911 i*sizeof(u32)); 912 913 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", 914 sp_sb_data.igu_sb_id, 915 sp_sb_data.igu_seg_id, 916 sp_sb_data.p_func.pf_id, 917 sp_sb_data.p_func.vnic_id, 918 sp_sb_data.p_func.vf_id, 919 sp_sb_data.p_func.vf_valid, 920 sp_sb_data.state); 921 922 923 for_each_eth_queue(bp, i) { 924 struct bnx2x_fastpath *fp = &bp->fp[i]; 925 int loop; 926 struct hc_status_block_data_e2 sb_data_e2; 927 struct hc_status_block_data_e1x sb_data_e1x; 928 struct hc_status_block_sm *hc_sm_p = 929 CHIP_IS_E1x(bp) ? 930 sb_data_e1x.common.state_machine : 931 sb_data_e2.common.state_machine; 932 struct hc_index_data *hc_index_p = 933 CHIP_IS_E1x(bp) ? 934 sb_data_e1x.index_data : 935 sb_data_e2.index_data; 936 u8 data_size, cos; 937 u32 *sb_data_p; 938 struct bnx2x_fp_txdata txdata; 939 940 /* Rx */ 941 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", 942 i, fp->rx_bd_prod, fp->rx_bd_cons, 943 fp->rx_comp_prod, 944 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); 945 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n", 946 fp->rx_sge_prod, fp->last_max_sge, 947 le16_to_cpu(fp->fp_hc_idx)); 948 949 /* Tx */ 950 for_each_cos_in_tx_queue(fp, cos) 951 { 952 txdata = *fp->txdata_ptr[cos]; 953 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n", 954 i, txdata.tx_pkt_prod, 955 txdata.tx_pkt_cons, txdata.tx_bd_prod, 956 txdata.tx_bd_cons, 957 le16_to_cpu(*txdata.tx_cons_sb)); 958 } 959 960 loop = CHIP_IS_E1x(bp) ? 961 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; 962 963 /* host sb data */ 964 965 if (IS_FCOE_FP(fp)) 966 continue; 967 968 BNX2X_ERR(" run indexes ("); 969 for (j = 0; j < HC_SB_MAX_SM; j++) 970 pr_cont("0x%x%s", 971 fp->sb_running_index[j], 972 (j == HC_SB_MAX_SM - 1) ? ")" : " "); 973 974 BNX2X_ERR(" indexes ("); 975 for (j = 0; j < loop; j++) 976 pr_cont("0x%x%s", 977 fp->sb_index_values[j], 978 (j == loop - 1) ? ")" : " "); 979 /* fw sb data */ 980 data_size = CHIP_IS_E1x(bp) ? 981 sizeof(struct hc_status_block_data_e1x) : 982 sizeof(struct hc_status_block_data_e2); 983 data_size /= sizeof(u32); 984 sb_data_p = CHIP_IS_E1x(bp) ? 985 (u32 *)&sb_data_e1x : 986 (u32 *)&sb_data_e2; 987 /* copy sb data in here */ 988 for (j = 0; j < data_size; j++) 989 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + 990 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + 991 j * sizeof(u32)); 992 993 if (!CHIP_IS_E1x(bp)) { 994 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", 995 sb_data_e2.common.p_func.pf_id, 996 sb_data_e2.common.p_func.vf_id, 997 sb_data_e2.common.p_func.vf_valid, 998 sb_data_e2.common.p_func.vnic_id, 999 sb_data_e2.common.same_igu_sb_1b, 1000 sb_data_e2.common.state); 1001 } else { 1002 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", 1003 sb_data_e1x.common.p_func.pf_id, 1004 sb_data_e1x.common.p_func.vf_id, 1005 sb_data_e1x.common.p_func.vf_valid, 1006 sb_data_e1x.common.p_func.vnic_id, 1007 sb_data_e1x.common.same_igu_sb_1b, 1008 sb_data_e1x.common.state); 1009 } 1010 1011 /* SB_SMs data */ 1012 for (j = 0; j < HC_SB_MAX_SM; j++) { 1013 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n", 1014 j, hc_sm_p[j].__flags, 1015 hc_sm_p[j].igu_sb_id, 1016 hc_sm_p[j].igu_seg_id, 1017 hc_sm_p[j].time_to_expire, 1018 hc_sm_p[j].timer_value); 1019 } 1020 1021 /* Indecies data */ 1022 for (j = 0; j < loop; j++) { 1023 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j, 1024 hc_index_p[j].flags, 1025 hc_index_p[j].timeout); 1026 } 1027 } 1028 1029 #ifdef BNX2X_STOP_ON_ERROR 1030 1031 /* event queue */ 1032 for (i = 0; i < NUM_EQ_DESC; i++) { 1033 u32 *data = (u32 *)&bp->eq_ring[i].message.data; 1034 1035 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n", 1036 i, bp->eq_ring[i].message.opcode, 1037 bp->eq_ring[i].message.error); 1038 BNX2X_ERR("data: %x %x %x\n", data[0], data[1], data[2]); 1039 } 1040 1041 /* Rings */ 1042 /* Rx */ 1043 for_each_valid_rx_queue(bp, i) { 1044 struct bnx2x_fastpath *fp = &bp->fp[i]; 1045 1046 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); 1047 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); 1048 for (j = start; j != end; j = RX_BD(j + 1)) { 1049 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; 1050 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; 1051 1052 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", 1053 i, j, rx_bd[1], rx_bd[0], sw_bd->data); 1054 } 1055 1056 start = RX_SGE(fp->rx_sge_prod); 1057 end = RX_SGE(fp->last_max_sge); 1058 for (j = start; j != end; j = RX_SGE(j + 1)) { 1059 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; 1060 struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; 1061 1062 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", 1063 i, j, rx_sge[1], rx_sge[0], sw_page->page); 1064 } 1065 1066 start = RCQ_BD(fp->rx_comp_cons - 10); 1067 end = RCQ_BD(fp->rx_comp_cons + 503); 1068 for (j = start; j != end; j = RCQ_BD(j + 1)) { 1069 u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; 1070 1071 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", 1072 i, j, cqe[0], cqe[1], cqe[2], cqe[3]); 1073 } 1074 } 1075 1076 /* Tx */ 1077 for_each_valid_tx_queue(bp, i) { 1078 struct bnx2x_fastpath *fp = &bp->fp[i]; 1079 for_each_cos_in_tx_queue(fp, cos) { 1080 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos]; 1081 1082 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); 1083 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); 1084 for (j = start; j != end; j = TX_BD(j + 1)) { 1085 struct sw_tx_bd *sw_bd = 1086 &txdata->tx_buf_ring[j]; 1087 1088 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n", 1089 i, cos, j, sw_bd->skb, 1090 sw_bd->first_bd); 1091 } 1092 1093 start = TX_BD(txdata->tx_bd_cons - 10); 1094 end = TX_BD(txdata->tx_bd_cons + 254); 1095 for (j = start; j != end; j = TX_BD(j + 1)) { 1096 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; 1097 1098 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n", 1099 i, cos, j, tx_bd[0], tx_bd[1], 1100 tx_bd[2], tx_bd[3]); 1101 } 1102 } 1103 } 1104 #endif 1105 bnx2x_fw_dump(bp); 1106 bnx2x_mc_assert(bp); 1107 BNX2X_ERR("end crash dump -----------------\n"); 1108 } 1109 1110 /* 1111 * FLR Support for E2 1112 * 1113 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW 1114 * initialization. 1115 */ 1116 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */ 1117 #define FLR_WAIT_INTERVAL 50 /* usec */ 1118 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */ 1119 1120 struct pbf_pN_buf_regs { 1121 int pN; 1122 u32 init_crd; 1123 u32 crd; 1124 u32 crd_freed; 1125 }; 1126 1127 struct pbf_pN_cmd_regs { 1128 int pN; 1129 u32 lines_occup; 1130 u32 lines_freed; 1131 }; 1132 1133 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, 1134 struct pbf_pN_buf_regs *regs, 1135 u32 poll_count) 1136 { 1137 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; 1138 u32 cur_cnt = poll_count; 1139 1140 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); 1141 crd = crd_start = REG_RD(bp, regs->crd); 1142 init_crd = REG_RD(bp, regs->init_crd); 1143 1144 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); 1145 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); 1146 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); 1147 1148 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < 1149 (init_crd - crd_start))) { 1150 if (cur_cnt--) { 1151 udelay(FLR_WAIT_INTERVAL); 1152 crd = REG_RD(bp, regs->crd); 1153 crd_freed = REG_RD(bp, regs->crd_freed); 1154 } else { 1155 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", 1156 regs->pN); 1157 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", 1158 regs->pN, crd); 1159 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", 1160 regs->pN, crd_freed); 1161 break; 1162 } 1163 } 1164 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", 1165 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 1166 } 1167 1168 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, 1169 struct pbf_pN_cmd_regs *regs, 1170 u32 poll_count) 1171 { 1172 u32 occup, to_free, freed, freed_start; 1173 u32 cur_cnt = poll_count; 1174 1175 occup = to_free = REG_RD(bp, regs->lines_occup); 1176 freed = freed_start = REG_RD(bp, regs->lines_freed); 1177 1178 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); 1179 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); 1180 1181 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { 1182 if (cur_cnt--) { 1183 udelay(FLR_WAIT_INTERVAL); 1184 occup = REG_RD(bp, regs->lines_occup); 1185 freed = REG_RD(bp, regs->lines_freed); 1186 } else { 1187 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", 1188 regs->pN); 1189 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", 1190 regs->pN, occup); 1191 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", 1192 regs->pN, freed); 1193 break; 1194 } 1195 } 1196 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", 1197 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 1198 } 1199 1200 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, 1201 u32 expected, u32 poll_count) 1202 { 1203 u32 cur_cnt = poll_count; 1204 u32 val; 1205 1206 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) 1207 udelay(FLR_WAIT_INTERVAL); 1208 1209 return val; 1210 } 1211 1212 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 1213 char *msg, u32 poll_cnt) 1214 { 1215 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); 1216 if (val != 0) { 1217 BNX2X_ERR("%s usage count=%d\n", msg, val); 1218 return 1; 1219 } 1220 return 0; 1221 } 1222 1223 /* Common routines with VF FLR cleanup */ 1224 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) 1225 { 1226 /* adjust polling timeout */ 1227 if (CHIP_REV_IS_EMUL(bp)) 1228 return FLR_POLL_CNT * 2000; 1229 1230 if (CHIP_REV_IS_FPGA(bp)) 1231 return FLR_POLL_CNT * 120; 1232 1233 return FLR_POLL_CNT; 1234 } 1235 1236 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) 1237 { 1238 struct pbf_pN_cmd_regs cmd_regs[] = { 1239 {0, (CHIP_IS_E3B0(bp)) ? 1240 PBF_REG_TQ_OCCUPANCY_Q0 : 1241 PBF_REG_P0_TQ_OCCUPANCY, 1242 (CHIP_IS_E3B0(bp)) ? 1243 PBF_REG_TQ_LINES_FREED_CNT_Q0 : 1244 PBF_REG_P0_TQ_LINES_FREED_CNT}, 1245 {1, (CHIP_IS_E3B0(bp)) ? 1246 PBF_REG_TQ_OCCUPANCY_Q1 : 1247 PBF_REG_P1_TQ_OCCUPANCY, 1248 (CHIP_IS_E3B0(bp)) ? 1249 PBF_REG_TQ_LINES_FREED_CNT_Q1 : 1250 PBF_REG_P1_TQ_LINES_FREED_CNT}, 1251 {4, (CHIP_IS_E3B0(bp)) ? 1252 PBF_REG_TQ_OCCUPANCY_LB_Q : 1253 PBF_REG_P4_TQ_OCCUPANCY, 1254 (CHIP_IS_E3B0(bp)) ? 1255 PBF_REG_TQ_LINES_FREED_CNT_LB_Q : 1256 PBF_REG_P4_TQ_LINES_FREED_CNT} 1257 }; 1258 1259 struct pbf_pN_buf_regs buf_regs[] = { 1260 {0, (CHIP_IS_E3B0(bp)) ? 1261 PBF_REG_INIT_CRD_Q0 : 1262 PBF_REG_P0_INIT_CRD , 1263 (CHIP_IS_E3B0(bp)) ? 1264 PBF_REG_CREDIT_Q0 : 1265 PBF_REG_P0_CREDIT, 1266 (CHIP_IS_E3B0(bp)) ? 1267 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : 1268 PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, 1269 {1, (CHIP_IS_E3B0(bp)) ? 1270 PBF_REG_INIT_CRD_Q1 : 1271 PBF_REG_P1_INIT_CRD, 1272 (CHIP_IS_E3B0(bp)) ? 1273 PBF_REG_CREDIT_Q1 : 1274 PBF_REG_P1_CREDIT, 1275 (CHIP_IS_E3B0(bp)) ? 1276 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : 1277 PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, 1278 {4, (CHIP_IS_E3B0(bp)) ? 1279 PBF_REG_INIT_CRD_LB_Q : 1280 PBF_REG_P4_INIT_CRD, 1281 (CHIP_IS_E3B0(bp)) ? 1282 PBF_REG_CREDIT_LB_Q : 1283 PBF_REG_P4_CREDIT, 1284 (CHIP_IS_E3B0(bp)) ? 1285 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : 1286 PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, 1287 }; 1288 1289 int i; 1290 1291 /* Verify the command queues are flushed P0, P1, P4 */ 1292 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) 1293 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); 1294 1295 1296 /* Verify the transmission buffers are flushed P0, P1, P4 */ 1297 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) 1298 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); 1299 } 1300 1301 #define OP_GEN_PARAM(param) \ 1302 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) 1303 1304 #define OP_GEN_TYPE(type) \ 1305 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) 1306 1307 #define OP_GEN_AGG_VECT(index) \ 1308 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) 1309 1310 1311 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt) 1312 { 1313 u32 op_gen_command = 0; 1314 1315 u32 comp_addr = BAR_CSTRORM_INTMEM + 1316 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); 1317 int ret = 0; 1318 1319 if (REG_RD(bp, comp_addr)) { 1320 BNX2X_ERR("Cleanup complete was not 0 before sending\n"); 1321 return 1; 1322 } 1323 1324 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); 1325 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); 1326 op_gen_command |= OP_GEN_AGG_VECT(clnup_func); 1327 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; 1328 1329 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); 1330 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command); 1331 1332 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { 1333 BNX2X_ERR("FW final cleanup did not succeed\n"); 1334 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n", 1335 (REG_RD(bp, comp_addr))); 1336 bnx2x_panic(); 1337 return 1; 1338 } 1339 /* Zero completion for nxt FLR */ 1340 REG_WR(bp, comp_addr, 0); 1341 1342 return ret; 1343 } 1344 1345 u8 bnx2x_is_pcie_pending(struct pci_dev *dev) 1346 { 1347 u16 status; 1348 1349 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status); 1350 return status & PCI_EXP_DEVSTA_TRPND; 1351 } 1352 1353 /* PF FLR specific routines 1354 */ 1355 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) 1356 { 1357 1358 /* wait for CFC PF usage-counter to zero (includes all the VFs) */ 1359 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1360 CFC_REG_NUM_LCIDS_INSIDE_PF, 1361 "CFC PF usage counter timed out", 1362 poll_cnt)) 1363 return 1; 1364 1365 1366 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ 1367 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1368 DORQ_REG_PF_USAGE_CNT, 1369 "DQ PF usage counter timed out", 1370 poll_cnt)) 1371 return 1; 1372 1373 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ 1374 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1375 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), 1376 "QM PF usage counter timed out", 1377 poll_cnt)) 1378 return 1; 1379 1380 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ 1381 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1382 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), 1383 "Timers VNIC usage counter timed out", 1384 poll_cnt)) 1385 return 1; 1386 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1387 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), 1388 "Timers NUM_SCANS usage counter timed out", 1389 poll_cnt)) 1390 return 1; 1391 1392 /* Wait DMAE PF usage counter to zero */ 1393 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1394 dmae_reg_go_c[INIT_DMAE_C(bp)], 1395 "DMAE dommand register timed out", 1396 poll_cnt)) 1397 return 1; 1398 1399 return 0; 1400 } 1401 1402 static void bnx2x_hw_enable_status(struct bnx2x *bp) 1403 { 1404 u32 val; 1405 1406 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); 1407 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); 1408 1409 val = REG_RD(bp, PBF_REG_DISABLE_PF); 1410 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); 1411 1412 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); 1413 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); 1414 1415 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); 1416 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); 1417 1418 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); 1419 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); 1420 1421 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); 1422 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); 1423 1424 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); 1425 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); 1426 1427 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1428 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", 1429 val); 1430 } 1431 1432 static int bnx2x_pf_flr_clnup(struct bnx2x *bp) 1433 { 1434 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); 1435 1436 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); 1437 1438 /* Re-enable PF target read access */ 1439 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 1440 1441 /* Poll HW usage counters */ 1442 DP(BNX2X_MSG_SP, "Polling usage counters\n"); 1443 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) 1444 return -EBUSY; 1445 1446 /* Zero the igu 'trailing edge' and 'leading edge' */ 1447 1448 /* Send the FW cleanup command */ 1449 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) 1450 return -EBUSY; 1451 1452 /* ATC cleanup */ 1453 1454 /* Verify TX hw is flushed */ 1455 bnx2x_tx_hw_flushed(bp, poll_cnt); 1456 1457 /* Wait 100ms (not adjusted according to platform) */ 1458 msleep(100); 1459 1460 /* Verify no pending pci transactions */ 1461 if (bnx2x_is_pcie_pending(bp->pdev)) 1462 BNX2X_ERR("PCIE Transactions still pending\n"); 1463 1464 /* Debug */ 1465 bnx2x_hw_enable_status(bp); 1466 1467 /* 1468 * Master enable - Due to WB DMAE writes performed before this 1469 * register is re-initialized as part of the regular function init 1470 */ 1471 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 1472 1473 return 0; 1474 } 1475 1476 static void bnx2x_hc_int_enable(struct bnx2x *bp) 1477 { 1478 int port = BP_PORT(bp); 1479 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1480 u32 val = REG_RD(bp, addr); 1481 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; 1482 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; 1483 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; 1484 1485 if (msix) { 1486 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1487 HC_CONFIG_0_REG_INT_LINE_EN_0); 1488 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1489 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1490 if (single_msix) 1491 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0; 1492 } else if (msi) { 1493 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; 1494 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1495 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1496 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1497 } else { 1498 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1499 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1500 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1501 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1502 1503 if (!CHIP_IS_E1(bp)) { 1504 DP(NETIF_MSG_IFUP, 1505 "write %x to HC %d (addr 0x%x)\n", val, port, addr); 1506 1507 REG_WR(bp, addr, val); 1508 1509 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; 1510 } 1511 } 1512 1513 if (CHIP_IS_E1(bp)) 1514 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); 1515 1516 DP(NETIF_MSG_IFUP, 1517 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr, 1518 (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1519 1520 REG_WR(bp, addr, val); 1521 /* 1522 * Ensure that HC_CONFIG is written before leading/trailing edge config 1523 */ 1524 mmiowb(); 1525 barrier(); 1526 1527 if (!CHIP_IS_E1(bp)) { 1528 /* init leading/trailing edge */ 1529 if (IS_MF(bp)) { 1530 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1531 if (bp->port.pmf) 1532 /* enable nig and gpio3 attention */ 1533 val |= 0x1100; 1534 } else 1535 val = 0xffff; 1536 1537 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 1538 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 1539 } 1540 1541 /* Make sure that interrupts are indeed enabled from here on */ 1542 mmiowb(); 1543 } 1544 1545 static void bnx2x_igu_int_enable(struct bnx2x *bp) 1546 { 1547 u32 val; 1548 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; 1549 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; 1550 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; 1551 1552 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1553 1554 if (msix) { 1555 val &= ~(IGU_PF_CONF_INT_LINE_EN | 1556 IGU_PF_CONF_SINGLE_ISR_EN); 1557 val |= (IGU_PF_CONF_MSI_MSIX_EN | 1558 IGU_PF_CONF_ATTN_BIT_EN); 1559 1560 if (single_msix) 1561 val |= IGU_PF_CONF_SINGLE_ISR_EN; 1562 } else if (msi) { 1563 val &= ~IGU_PF_CONF_INT_LINE_EN; 1564 val |= (IGU_PF_CONF_MSI_MSIX_EN | 1565 IGU_PF_CONF_ATTN_BIT_EN | 1566 IGU_PF_CONF_SINGLE_ISR_EN); 1567 } else { 1568 val &= ~IGU_PF_CONF_MSI_MSIX_EN; 1569 val |= (IGU_PF_CONF_INT_LINE_EN | 1570 IGU_PF_CONF_ATTN_BIT_EN | 1571 IGU_PF_CONF_SINGLE_ISR_EN); 1572 } 1573 1574 /* Clean previous status - need to configure igu prior to ack*/ 1575 if ((!msix) || single_msix) { 1576 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1577 bnx2x_ack_int(bp); 1578 } 1579 1580 val |= IGU_PF_CONF_FUNC_EN; 1581 1582 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n", 1583 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1584 1585 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1586 1587 if (val & IGU_PF_CONF_INT_LINE_EN) 1588 pci_intx(bp->pdev, true); 1589 1590 barrier(); 1591 1592 /* init leading/trailing edge */ 1593 if (IS_MF(bp)) { 1594 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1595 if (bp->port.pmf) 1596 /* enable nig and gpio3 attention */ 1597 val |= 0x1100; 1598 } else 1599 val = 0xffff; 1600 1601 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 1602 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 1603 1604 /* Make sure that interrupts are indeed enabled from here on */ 1605 mmiowb(); 1606 } 1607 1608 void bnx2x_int_enable(struct bnx2x *bp) 1609 { 1610 if (bp->common.int_block == INT_BLOCK_HC) 1611 bnx2x_hc_int_enable(bp); 1612 else 1613 bnx2x_igu_int_enable(bp); 1614 } 1615 1616 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) 1617 { 1618 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1619 int i, offset; 1620 1621 if (disable_hw) 1622 /* prevent the HW from sending interrupts */ 1623 bnx2x_int_disable(bp); 1624 1625 /* make sure all ISRs are done */ 1626 if (msix) { 1627 synchronize_irq(bp->msix_table[0].vector); 1628 offset = 1; 1629 if (CNIC_SUPPORT(bp)) 1630 offset++; 1631 for_each_eth_queue(bp, i) 1632 synchronize_irq(bp->msix_table[offset++].vector); 1633 } else 1634 synchronize_irq(bp->pdev->irq); 1635 1636 /* make sure sp_task is not running */ 1637 cancel_delayed_work(&bp->sp_task); 1638 cancel_delayed_work(&bp->period_task); 1639 flush_workqueue(bnx2x_wq); 1640 } 1641 1642 /* fast path */ 1643 1644 /* 1645 * General service functions 1646 */ 1647 1648 /* Return true if succeeded to acquire the lock */ 1649 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) 1650 { 1651 u32 lock_status; 1652 u32 resource_bit = (1 << resource); 1653 int func = BP_FUNC(bp); 1654 u32 hw_lock_control_reg; 1655 1656 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, 1657 "Trying to take a lock on resource %d\n", resource); 1658 1659 /* Validating that the resource is within range */ 1660 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1661 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, 1662 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1663 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1664 return false; 1665 } 1666 1667 if (func <= 5) 1668 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1669 else 1670 hw_lock_control_reg = 1671 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1672 1673 /* Try to acquire the lock */ 1674 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1675 lock_status = REG_RD(bp, hw_lock_control_reg); 1676 if (lock_status & resource_bit) 1677 return true; 1678 1679 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, 1680 "Failed to get a lock on resource %d\n", resource); 1681 return false; 1682 } 1683 1684 /** 1685 * bnx2x_get_leader_lock_resource - get the recovery leader resource id 1686 * 1687 * @bp: driver handle 1688 * 1689 * Returns the recovery leader resource id according to the engine this function 1690 * belongs to. Currently only only 2 engines is supported. 1691 */ 1692 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp) 1693 { 1694 if (BP_PATH(bp)) 1695 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; 1696 else 1697 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; 1698 } 1699 1700 /** 1701 * bnx2x_trylock_leader_lock- try to acquire a leader lock. 1702 * 1703 * @bp: driver handle 1704 * 1705 * Tries to acquire a leader lock for current engine. 1706 */ 1707 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp) 1708 { 1709 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1710 } 1711 1712 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); 1713 1714 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */ 1715 static int bnx2x_schedule_sp_task(struct bnx2x *bp) 1716 { 1717 /* Set the interrupt occurred bit for the sp-task to recognize it 1718 * must ack the interrupt and transition according to the IGU 1719 * state machine. 1720 */ 1721 atomic_set(&bp->interrupt_occurred, 1); 1722 1723 /* The sp_task must execute only after this bit 1724 * is set, otherwise we will get out of sync and miss all 1725 * further interrupts. Hence, the barrier. 1726 */ 1727 smp_wmb(); 1728 1729 /* schedule sp_task to workqueue */ 1730 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 1731 } 1732 1733 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) 1734 { 1735 struct bnx2x *bp = fp->bp; 1736 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1737 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1738 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; 1739 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 1740 1741 DP(BNX2X_MSG_SP, 1742 "fp %d cid %d got ramrod #%d state is %x type is %d\n", 1743 fp->index, cid, command, bp->state, 1744 rr_cqe->ramrod_cqe.ramrod_type); 1745 1746 /* If cid is within VF range, replace the slowpath object with the 1747 * one corresponding to this VF 1748 */ 1749 if (cid >= BNX2X_FIRST_VF_CID && 1750 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS) 1751 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj); 1752 1753 switch (command) { 1754 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): 1755 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); 1756 drv_cmd = BNX2X_Q_CMD_UPDATE; 1757 break; 1758 1759 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): 1760 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); 1761 drv_cmd = BNX2X_Q_CMD_SETUP; 1762 break; 1763 1764 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): 1765 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); 1766 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 1767 break; 1768 1769 case (RAMROD_CMD_ID_ETH_HALT): 1770 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); 1771 drv_cmd = BNX2X_Q_CMD_HALT; 1772 break; 1773 1774 case (RAMROD_CMD_ID_ETH_TERMINATE): 1775 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid); 1776 drv_cmd = BNX2X_Q_CMD_TERMINATE; 1777 break; 1778 1779 case (RAMROD_CMD_ID_ETH_EMPTY): 1780 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); 1781 drv_cmd = BNX2X_Q_CMD_EMPTY; 1782 break; 1783 1784 default: 1785 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", 1786 command, fp->index); 1787 return; 1788 } 1789 1790 if ((drv_cmd != BNX2X_Q_CMD_MAX) && 1791 q_obj->complete_cmd(bp, q_obj, drv_cmd)) 1792 /* q_obj->complete_cmd() failure means that this was 1793 * an unexpected completion. 1794 * 1795 * In this case we don't want to increase the bp->spq_left 1796 * because apparently we haven't sent this command the first 1797 * place. 1798 */ 1799 #ifdef BNX2X_STOP_ON_ERROR 1800 bnx2x_panic(); 1801 #else 1802 return; 1803 #endif 1804 /* SRIOV: reschedule any 'in_progress' operations */ 1805 bnx2x_iov_sp_event(bp, cid, true); 1806 1807 smp_mb__before_atomic_inc(); 1808 atomic_inc(&bp->cq_spq_left); 1809 /* push the change in bp->spq_left and towards the memory */ 1810 smp_mb__after_atomic_inc(); 1811 1812 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); 1813 1814 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) && 1815 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) { 1816 /* if Q update ramrod is completed for last Q in AFEX vif set 1817 * flow, then ACK MCP at the end 1818 * 1819 * mark pending ACK to MCP bit. 1820 * prevent case that both bits are cleared. 1821 * At the end of load/unload driver checks that 1822 * sp_state is cleared, and this order prevents 1823 * races 1824 */ 1825 smp_mb__before_clear_bit(); 1826 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state); 1827 wmb(); 1828 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); 1829 smp_mb__after_clear_bit(); 1830 1831 /* schedule the sp task as mcp ack is required */ 1832 bnx2x_schedule_sp_task(bp); 1833 } 1834 1835 return; 1836 } 1837 1838 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) 1839 { 1840 struct bnx2x *bp = netdev_priv(dev_instance); 1841 u16 status = bnx2x_ack_int(bp); 1842 u16 mask; 1843 int i; 1844 u8 cos; 1845 1846 /* Return here if interrupt is shared and it's not for us */ 1847 if (unlikely(status == 0)) { 1848 DP(NETIF_MSG_INTR, "not our interrupt!\n"); 1849 return IRQ_NONE; 1850 } 1851 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); 1852 1853 #ifdef BNX2X_STOP_ON_ERROR 1854 if (unlikely(bp->panic)) 1855 return IRQ_HANDLED; 1856 #endif 1857 1858 for_each_eth_queue(bp, i) { 1859 struct bnx2x_fastpath *fp = &bp->fp[i]; 1860 1861 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp)); 1862 if (status & mask) { 1863 /* Handle Rx or Tx according to SB id */ 1864 prefetch(fp->rx_cons_sb); 1865 for_each_cos_in_tx_queue(fp, cos) 1866 prefetch(fp->txdata_ptr[cos]->tx_cons_sb); 1867 prefetch(&fp->sb_running_index[SM_RX_ID]); 1868 napi_schedule(&bnx2x_fp(bp, fp->index, napi)); 1869 status &= ~mask; 1870 } 1871 } 1872 1873 if (CNIC_SUPPORT(bp)) { 1874 mask = 0x2; 1875 if (status & (mask | 0x1)) { 1876 struct cnic_ops *c_ops = NULL; 1877 1878 rcu_read_lock(); 1879 c_ops = rcu_dereference(bp->cnic_ops); 1880 if (c_ops && (bp->cnic_eth_dev.drv_state & 1881 CNIC_DRV_STATE_HANDLES_IRQ)) 1882 c_ops->cnic_handler(bp->cnic_data, NULL); 1883 rcu_read_unlock(); 1884 1885 status &= ~mask; 1886 } 1887 } 1888 1889 if (unlikely(status & 0x1)) { 1890 1891 /* schedule sp task to perform default status block work, ack 1892 * attentions and enable interrupts. 1893 */ 1894 bnx2x_schedule_sp_task(bp); 1895 1896 status &= ~0x1; 1897 if (!status) 1898 return IRQ_HANDLED; 1899 } 1900 1901 if (unlikely(status)) 1902 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 1903 status); 1904 1905 return IRQ_HANDLED; 1906 } 1907 1908 /* Link */ 1909 1910 /* 1911 * General service functions 1912 */ 1913 1914 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) 1915 { 1916 u32 lock_status; 1917 u32 resource_bit = (1 << resource); 1918 int func = BP_FUNC(bp); 1919 u32 hw_lock_control_reg; 1920 int cnt; 1921 1922 /* Validating that the resource is within range */ 1923 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1924 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1925 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1926 return -EINVAL; 1927 } 1928 1929 if (func <= 5) { 1930 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1931 } else { 1932 hw_lock_control_reg = 1933 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1934 } 1935 1936 /* Validating that the resource is not already taken */ 1937 lock_status = REG_RD(bp, hw_lock_control_reg); 1938 if (lock_status & resource_bit) { 1939 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n", 1940 lock_status, resource_bit); 1941 return -EEXIST; 1942 } 1943 1944 /* Try for 5 second every 5ms */ 1945 for (cnt = 0; cnt < 1000; cnt++) { 1946 /* Try to acquire the lock */ 1947 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1948 lock_status = REG_RD(bp, hw_lock_control_reg); 1949 if (lock_status & resource_bit) 1950 return 0; 1951 1952 msleep(5); 1953 } 1954 BNX2X_ERR("Timeout\n"); 1955 return -EAGAIN; 1956 } 1957 1958 int bnx2x_release_leader_lock(struct bnx2x *bp) 1959 { 1960 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1961 } 1962 1963 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) 1964 { 1965 u32 lock_status; 1966 u32 resource_bit = (1 << resource); 1967 int func = BP_FUNC(bp); 1968 u32 hw_lock_control_reg; 1969 1970 /* Validating that the resource is within range */ 1971 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1972 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1973 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1974 return -EINVAL; 1975 } 1976 1977 if (func <= 5) { 1978 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1979 } else { 1980 hw_lock_control_reg = 1981 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1982 } 1983 1984 /* Validating that the resource is currently taken */ 1985 lock_status = REG_RD(bp, hw_lock_control_reg); 1986 if (!(lock_status & resource_bit)) { 1987 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n", 1988 lock_status, resource_bit); 1989 return -EFAULT; 1990 } 1991 1992 REG_WR(bp, hw_lock_control_reg, resource_bit); 1993 return 0; 1994 } 1995 1996 1997 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) 1998 { 1999 /* The GPIO should be swapped if swap register is set and active */ 2000 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2001 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2002 int gpio_shift = gpio_num + 2003 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2004 u32 gpio_mask = (1 << gpio_shift); 2005 u32 gpio_reg; 2006 int value; 2007 2008 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2009 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2010 return -EINVAL; 2011 } 2012 2013 /* read GPIO value */ 2014 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 2015 2016 /* get the requested pin value */ 2017 if ((gpio_reg & gpio_mask) == gpio_mask) 2018 value = 1; 2019 else 2020 value = 0; 2021 2022 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); 2023 2024 return value; 2025 } 2026 2027 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 2028 { 2029 /* The GPIO should be swapped if swap register is set and active */ 2030 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2031 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2032 int gpio_shift = gpio_num + 2033 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2034 u32 gpio_mask = (1 << gpio_shift); 2035 u32 gpio_reg; 2036 2037 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2038 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2039 return -EINVAL; 2040 } 2041 2042 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2043 /* read GPIO and mask except the float bits */ 2044 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); 2045 2046 switch (mode) { 2047 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 2048 DP(NETIF_MSG_LINK, 2049 "Set GPIO %d (shift %d) -> output low\n", 2050 gpio_num, gpio_shift); 2051 /* clear FLOAT and set CLR */ 2052 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 2053 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); 2054 break; 2055 2056 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2057 DP(NETIF_MSG_LINK, 2058 "Set GPIO %d (shift %d) -> output high\n", 2059 gpio_num, gpio_shift); 2060 /* clear FLOAT and set SET */ 2061 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 2062 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); 2063 break; 2064 2065 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2066 DP(NETIF_MSG_LINK, 2067 "Set GPIO %d (shift %d) -> input\n", 2068 gpio_num, gpio_shift); 2069 /* set FLOAT */ 2070 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 2071 break; 2072 2073 default: 2074 break; 2075 } 2076 2077 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 2078 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2079 2080 return 0; 2081 } 2082 2083 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) 2084 { 2085 u32 gpio_reg = 0; 2086 int rc = 0; 2087 2088 /* Any port swapping should be handled by caller. */ 2089 2090 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2091 /* read GPIO and mask except the float bits */ 2092 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 2093 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2094 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); 2095 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); 2096 2097 switch (mode) { 2098 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 2099 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); 2100 /* set CLR */ 2101 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); 2102 break; 2103 2104 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2105 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); 2106 /* set SET */ 2107 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); 2108 break; 2109 2110 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2111 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); 2112 /* set FLOAT */ 2113 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2114 break; 2115 2116 default: 2117 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); 2118 rc = -EINVAL; 2119 break; 2120 } 2121 2122 if (rc == 0) 2123 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 2124 2125 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2126 2127 return rc; 2128 } 2129 2130 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 2131 { 2132 /* The GPIO should be swapped if swap register is set and active */ 2133 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2134 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2135 int gpio_shift = gpio_num + 2136 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2137 u32 gpio_mask = (1 << gpio_shift); 2138 u32 gpio_reg; 2139 2140 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2141 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2142 return -EINVAL; 2143 } 2144 2145 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2146 /* read GPIO int */ 2147 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); 2148 2149 switch (mode) { 2150 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: 2151 DP(NETIF_MSG_LINK, 2152 "Clear GPIO INT %d (shift %d) -> output low\n", 2153 gpio_num, gpio_shift); 2154 /* clear SET and set CLR */ 2155 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2156 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2157 break; 2158 2159 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: 2160 DP(NETIF_MSG_LINK, 2161 "Set GPIO INT %d (shift %d) -> output high\n", 2162 gpio_num, gpio_shift); 2163 /* clear CLR and set SET */ 2164 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2165 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2166 break; 2167 2168 default: 2169 break; 2170 } 2171 2172 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); 2173 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2174 2175 return 0; 2176 } 2177 2178 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode) 2179 { 2180 u32 spio_reg; 2181 2182 /* Only 2 SPIOs are configurable */ 2183 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) { 2184 BNX2X_ERR("Invalid SPIO 0x%x\n", spio); 2185 return -EINVAL; 2186 } 2187 2188 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2189 /* read SPIO and mask except the float bits */ 2190 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT); 2191 2192 switch (mode) { 2193 case MISC_SPIO_OUTPUT_LOW: 2194 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio); 2195 /* clear FLOAT and set CLR */ 2196 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); 2197 spio_reg |= (spio << MISC_SPIO_CLR_POS); 2198 break; 2199 2200 case MISC_SPIO_OUTPUT_HIGH: 2201 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio); 2202 /* clear FLOAT and set SET */ 2203 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); 2204 spio_reg |= (spio << MISC_SPIO_SET_POS); 2205 break; 2206 2207 case MISC_SPIO_INPUT_HI_Z: 2208 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio); 2209 /* set FLOAT */ 2210 spio_reg |= (spio << MISC_SPIO_FLOAT_POS); 2211 break; 2212 2213 default: 2214 break; 2215 } 2216 2217 REG_WR(bp, MISC_REG_SPIO, spio_reg); 2218 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2219 2220 return 0; 2221 } 2222 2223 void bnx2x_calc_fc_adv(struct bnx2x *bp) 2224 { 2225 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); 2226 switch (bp->link_vars.ieee_fc & 2227 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { 2228 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: 2229 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2230 ADVERTISED_Pause); 2231 break; 2232 2233 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: 2234 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | 2235 ADVERTISED_Pause); 2236 break; 2237 2238 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: 2239 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; 2240 break; 2241 2242 default: 2243 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2244 ADVERTISED_Pause); 2245 break; 2246 } 2247 } 2248 2249 static void bnx2x_set_requested_fc(struct bnx2x *bp) 2250 { 2251 /* Initialize link parameters structure variables 2252 * It is recommended to turn off RX FC for jumbo frames 2253 * for better performance 2254 */ 2255 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) 2256 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; 2257 else 2258 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; 2259 } 2260 2261 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) 2262 { 2263 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp); 2264 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; 2265 2266 if (!BP_NOMCP(bp)) { 2267 bnx2x_set_requested_fc(bp); 2268 bnx2x_acquire_phy_lock(bp); 2269 2270 if (load_mode == LOAD_DIAG) { 2271 struct link_params *lp = &bp->link_params; 2272 lp->loopback_mode = LOOPBACK_XGXS; 2273 /* do PHY loopback at 10G speed, if possible */ 2274 if (lp->req_line_speed[cfx_idx] < SPEED_10000) { 2275 if (lp->speed_cap_mask[cfx_idx] & 2276 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 2277 lp->req_line_speed[cfx_idx] = 2278 SPEED_10000; 2279 else 2280 lp->req_line_speed[cfx_idx] = 2281 SPEED_1000; 2282 } 2283 } 2284 2285 if (load_mode == LOAD_LOOPBACK_EXT) { 2286 struct link_params *lp = &bp->link_params; 2287 lp->loopback_mode = LOOPBACK_EXT; 2288 } 2289 2290 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2291 2292 bnx2x_release_phy_lock(bp); 2293 2294 bnx2x_calc_fc_adv(bp); 2295 2296 if (bp->link_vars.link_up) { 2297 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2298 bnx2x_link_report(bp); 2299 } 2300 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2301 bp->link_params.req_line_speed[cfx_idx] = req_line_speed; 2302 return rc; 2303 } 2304 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 2305 return -EINVAL; 2306 } 2307 2308 void bnx2x_link_set(struct bnx2x *bp) 2309 { 2310 if (!BP_NOMCP(bp)) { 2311 bnx2x_acquire_phy_lock(bp); 2312 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2313 bnx2x_release_phy_lock(bp); 2314 2315 bnx2x_calc_fc_adv(bp); 2316 } else 2317 BNX2X_ERR("Bootcode is missing - can not set link\n"); 2318 } 2319 2320 static void bnx2x__link_reset(struct bnx2x *bp) 2321 { 2322 if (!BP_NOMCP(bp)) { 2323 bnx2x_acquire_phy_lock(bp); 2324 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars); 2325 bnx2x_release_phy_lock(bp); 2326 } else 2327 BNX2X_ERR("Bootcode is missing - can not reset link\n"); 2328 } 2329 2330 void bnx2x_force_link_reset(struct bnx2x *bp) 2331 { 2332 bnx2x_acquire_phy_lock(bp); 2333 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2334 bnx2x_release_phy_lock(bp); 2335 } 2336 2337 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) 2338 { 2339 u8 rc = 0; 2340 2341 if (!BP_NOMCP(bp)) { 2342 bnx2x_acquire_phy_lock(bp); 2343 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, 2344 is_serdes); 2345 bnx2x_release_phy_lock(bp); 2346 } else 2347 BNX2X_ERR("Bootcode is missing - can not test link\n"); 2348 2349 return rc; 2350 } 2351 2352 2353 /* Calculates the sum of vn_min_rates. 2354 It's needed for further normalizing of the min_rates. 2355 Returns: 2356 sum of vn_min_rates. 2357 or 2358 0 - if all the min_rates are 0. 2359 In the later case fainess algorithm should be deactivated. 2360 If not all min_rates are zero then those that are zeroes will be set to 1. 2361 */ 2362 static void bnx2x_calc_vn_min(struct bnx2x *bp, 2363 struct cmng_init_input *input) 2364 { 2365 int all_zero = 1; 2366 int vn; 2367 2368 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2369 u32 vn_cfg = bp->mf_config[vn]; 2370 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2371 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2372 2373 /* Skip hidden vns */ 2374 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) 2375 vn_min_rate = 0; 2376 /* If min rate is zero - set it to 1 */ 2377 else if (!vn_min_rate) 2378 vn_min_rate = DEF_MIN_RATE; 2379 else 2380 all_zero = 0; 2381 2382 input->vnic_min_rate[vn] = vn_min_rate; 2383 } 2384 2385 /* if ETS or all min rates are zeros - disable fairness */ 2386 if (BNX2X_IS_ETS_ENABLED(bp)) { 2387 input->flags.cmng_enables &= 2388 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2389 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); 2390 } else if (all_zero) { 2391 input->flags.cmng_enables &= 2392 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2393 DP(NETIF_MSG_IFUP, 2394 "All MIN values are zeroes fairness will be disabled\n"); 2395 } else 2396 input->flags.cmng_enables |= 2397 CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2398 } 2399 2400 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn, 2401 struct cmng_init_input *input) 2402 { 2403 u16 vn_max_rate; 2404 u32 vn_cfg = bp->mf_config[vn]; 2405 2406 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) 2407 vn_max_rate = 0; 2408 else { 2409 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); 2410 2411 if (IS_MF_SI(bp)) { 2412 /* maxCfg in percents of linkspeed */ 2413 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; 2414 } else /* SD modes */ 2415 /* maxCfg is absolute in 100Mb units */ 2416 vn_max_rate = maxCfg * 100; 2417 } 2418 2419 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate); 2420 2421 input->vnic_max_rate[vn] = vn_max_rate; 2422 } 2423 2424 2425 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) 2426 { 2427 if (CHIP_REV_IS_SLOW(bp)) 2428 return CMNG_FNS_NONE; 2429 if (IS_MF(bp)) 2430 return CMNG_FNS_MINMAX; 2431 2432 return CMNG_FNS_NONE; 2433 } 2434 2435 void bnx2x_read_mf_cfg(struct bnx2x *bp) 2436 { 2437 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); 2438 2439 if (BP_NOMCP(bp)) 2440 return; /* what should be the default bvalue in this case */ 2441 2442 /* For 2 port configuration the absolute function number formula 2443 * is: 2444 * abs_func = 2 * vn + BP_PORT + BP_PATH 2445 * 2446 * and there are 4 functions per port 2447 * 2448 * For 4 port configuration it is 2449 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH 2450 * 2451 * and there are 2 functions per port 2452 */ 2453 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2454 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); 2455 2456 if (func >= E1H_FUNC_MAX) 2457 break; 2458 2459 bp->mf_config[vn] = 2460 MF_CFG_RD(bp, func_mf_config[func].config); 2461 } 2462 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { 2463 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n"); 2464 bp->flags |= MF_FUNC_DIS; 2465 } else { 2466 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); 2467 bp->flags &= ~MF_FUNC_DIS; 2468 } 2469 } 2470 2471 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) 2472 { 2473 struct cmng_init_input input; 2474 memset(&input, 0, sizeof(struct cmng_init_input)); 2475 2476 input.port_rate = bp->link_vars.line_speed; 2477 2478 if (cmng_type == CMNG_FNS_MINMAX) { 2479 int vn; 2480 2481 /* read mf conf from shmem */ 2482 if (read_cfg) 2483 bnx2x_read_mf_cfg(bp); 2484 2485 /* vn_weight_sum and enable fairness if not 0 */ 2486 bnx2x_calc_vn_min(bp, &input); 2487 2488 /* calculate and set min-max rate for each vn */ 2489 if (bp->port.pmf) 2490 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) 2491 bnx2x_calc_vn_max(bp, vn, &input); 2492 2493 /* always enable rate shaping and fairness */ 2494 input.flags.cmng_enables |= 2495 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; 2496 2497 bnx2x_init_cmng(&input, &bp->cmng); 2498 return; 2499 } 2500 2501 /* rate shaping and fairness are disabled */ 2502 DP(NETIF_MSG_IFUP, 2503 "rate shaping and fairness are disabled\n"); 2504 } 2505 2506 static void storm_memset_cmng(struct bnx2x *bp, 2507 struct cmng_init *cmng, 2508 u8 port) 2509 { 2510 int vn; 2511 size_t size = sizeof(struct cmng_struct_per_port); 2512 2513 u32 addr = BAR_XSTRORM_INTMEM + 2514 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port); 2515 2516 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port); 2517 2518 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2519 int func = func_by_vn(bp, vn); 2520 2521 addr = BAR_XSTRORM_INTMEM + 2522 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func); 2523 size = sizeof(struct rate_shaping_vars_per_vn); 2524 __storm_memset_struct(bp, addr, size, 2525 (u32 *)&cmng->vnic.vnic_max_rate[vn]); 2526 2527 addr = BAR_XSTRORM_INTMEM + 2528 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func); 2529 size = sizeof(struct fairness_vars_per_vn); 2530 __storm_memset_struct(bp, addr, size, 2531 (u32 *)&cmng->vnic.vnic_min_rate[vn]); 2532 } 2533 } 2534 2535 /* This function is called upon link interrupt */ 2536 static void bnx2x_link_attn(struct bnx2x *bp) 2537 { 2538 /* Make sure that we are synced with the current statistics */ 2539 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2540 2541 bnx2x_link_update(&bp->link_params, &bp->link_vars); 2542 2543 if (bp->link_vars.link_up) { 2544 2545 /* dropless flow control */ 2546 if (!CHIP_IS_E1(bp) && bp->dropless_fc) { 2547 int port = BP_PORT(bp); 2548 u32 pause_enabled = 0; 2549 2550 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) 2551 pause_enabled = 1; 2552 2553 REG_WR(bp, BAR_USTRORM_INTMEM + 2554 USTORM_ETH_PAUSE_ENABLED_OFFSET(port), 2555 pause_enabled); 2556 } 2557 2558 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { 2559 struct host_port_stats *pstats; 2560 2561 pstats = bnx2x_sp(bp, port_stats); 2562 /* reset old mac stats */ 2563 memset(&(pstats->mac_stx[0]), 0, 2564 sizeof(struct mac_stx)); 2565 } 2566 if (bp->state == BNX2X_STATE_OPEN) 2567 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2568 } 2569 2570 if (bp->link_vars.link_up && bp->link_vars.line_speed) { 2571 int cmng_fns = bnx2x_get_cmng_fns_mode(bp); 2572 2573 if (cmng_fns != CMNG_FNS_NONE) { 2574 bnx2x_cmng_fns_init(bp, false, cmng_fns); 2575 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2576 } else 2577 /* rate shaping and fairness are disabled */ 2578 DP(NETIF_MSG_IFUP, 2579 "single function mode without fairness\n"); 2580 } 2581 2582 __bnx2x_link_report(bp); 2583 2584 if (IS_MF(bp)) 2585 bnx2x_link_sync_notify(bp); 2586 } 2587 2588 void bnx2x__link_status_update(struct bnx2x *bp) 2589 { 2590 if (bp->state != BNX2X_STATE_OPEN) 2591 return; 2592 2593 /* read updated dcb configuration */ 2594 if (IS_PF(bp)) { 2595 bnx2x_dcbx_pmf_update(bp); 2596 bnx2x_link_status_update(&bp->link_params, &bp->link_vars); 2597 if (bp->link_vars.link_up) 2598 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2599 else 2600 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2601 /* indicate link status */ 2602 bnx2x_link_report(bp); 2603 2604 } else { /* VF */ 2605 bp->port.supported[0] |= (SUPPORTED_10baseT_Half | 2606 SUPPORTED_10baseT_Full | 2607 SUPPORTED_100baseT_Half | 2608 SUPPORTED_100baseT_Full | 2609 SUPPORTED_1000baseT_Full | 2610 SUPPORTED_2500baseX_Full | 2611 SUPPORTED_10000baseT_Full | 2612 SUPPORTED_TP | 2613 SUPPORTED_FIBRE | 2614 SUPPORTED_Autoneg | 2615 SUPPORTED_Pause | 2616 SUPPORTED_Asym_Pause); 2617 bp->port.advertising[0] = bp->port.supported[0]; 2618 2619 bp->link_params.bp = bp; 2620 bp->link_params.port = BP_PORT(bp); 2621 bp->link_params.req_duplex[0] = DUPLEX_FULL; 2622 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE; 2623 bp->link_params.req_line_speed[0] = SPEED_10000; 2624 bp->link_params.speed_cap_mask[0] = 0x7f0000; 2625 bp->link_params.switch_cfg = SWITCH_CFG_10G; 2626 bp->link_vars.mac_type = MAC_TYPE_BMAC; 2627 bp->link_vars.line_speed = SPEED_10000; 2628 bp->link_vars.link_status = 2629 (LINK_STATUS_LINK_UP | 2630 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD); 2631 bp->link_vars.link_up = 1; 2632 bp->link_vars.duplex = DUPLEX_FULL; 2633 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE; 2634 __bnx2x_link_report(bp); 2635 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2636 } 2637 } 2638 2639 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid, 2640 u16 vlan_val, u8 allowed_prio) 2641 { 2642 struct bnx2x_func_state_params func_params = {NULL}; 2643 struct bnx2x_func_afex_update_params *f_update_params = 2644 &func_params.params.afex_update; 2645 2646 func_params.f_obj = &bp->func_obj; 2647 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE; 2648 2649 /* no need to wait for RAMROD completion, so don't 2650 * set RAMROD_COMP_WAIT flag 2651 */ 2652 2653 f_update_params->vif_id = vifid; 2654 f_update_params->afex_default_vlan = vlan_val; 2655 f_update_params->allowed_priorities = allowed_prio; 2656 2657 /* if ramrod can not be sent, response to MCP immediately */ 2658 if (bnx2x_func_state_change(bp, &func_params) < 0) 2659 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); 2660 2661 return 0; 2662 } 2663 2664 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type, 2665 u16 vif_index, u8 func_bit_map) 2666 { 2667 struct bnx2x_func_state_params func_params = {NULL}; 2668 struct bnx2x_func_afex_viflists_params *update_params = 2669 &func_params.params.afex_viflists; 2670 int rc; 2671 u32 drv_msg_code; 2672 2673 /* validate only LIST_SET and LIST_GET are received from switch */ 2674 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET)) 2675 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n", 2676 cmd_type); 2677 2678 func_params.f_obj = &bp->func_obj; 2679 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS; 2680 2681 /* set parameters according to cmd_type */ 2682 update_params->afex_vif_list_command = cmd_type; 2683 update_params->vif_list_index = vif_index; 2684 update_params->func_bit_map = 2685 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map; 2686 update_params->func_to_clear = 0; 2687 drv_msg_code = 2688 (cmd_type == VIF_LIST_RULE_GET) ? 2689 DRV_MSG_CODE_AFEX_LISTGET_ACK : 2690 DRV_MSG_CODE_AFEX_LISTSET_ACK; 2691 2692 /* if ramrod can not be sent, respond to MCP immediately for 2693 * SET and GET requests (other are not triggered from MCP) 2694 */ 2695 rc = bnx2x_func_state_change(bp, &func_params); 2696 if (rc < 0) 2697 bnx2x_fw_command(bp, drv_msg_code, 0); 2698 2699 return 0; 2700 } 2701 2702 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd) 2703 { 2704 struct afex_stats afex_stats; 2705 u32 func = BP_ABS_FUNC(bp); 2706 u32 mf_config; 2707 u16 vlan_val; 2708 u32 vlan_prio; 2709 u16 vif_id; 2710 u8 allowed_prio; 2711 u8 vlan_mode; 2712 u32 addr_to_write, vifid, addrs, stats_type, i; 2713 2714 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) { 2715 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); 2716 DP(BNX2X_MSG_MCP, 2717 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid); 2718 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0); 2719 } 2720 2721 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) { 2722 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); 2723 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]); 2724 DP(BNX2X_MSG_MCP, 2725 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n", 2726 vifid, addrs); 2727 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid, 2728 addrs); 2729 } 2730 2731 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) { 2732 addr_to_write = SHMEM2_RD(bp, 2733 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]); 2734 stats_type = SHMEM2_RD(bp, 2735 afex_param1_to_driver[BP_FW_MB_IDX(bp)]); 2736 2737 DP(BNX2X_MSG_MCP, 2738 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n", 2739 addr_to_write); 2740 2741 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type); 2742 2743 /* write response to scratchpad, for MCP */ 2744 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++) 2745 REG_WR(bp, addr_to_write + i*sizeof(u32), 2746 *(((u32 *)(&afex_stats))+i)); 2747 2748 /* send ack message to MCP */ 2749 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0); 2750 } 2751 2752 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) { 2753 mf_config = MF_CFG_RD(bp, func_mf_config[func].config); 2754 bp->mf_config[BP_VN(bp)] = mf_config; 2755 DP(BNX2X_MSG_MCP, 2756 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n", 2757 mf_config); 2758 2759 /* if VIF_SET is "enabled" */ 2760 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) { 2761 /* set rate limit directly to internal RAM */ 2762 struct cmng_init_input cmng_input; 2763 struct rate_shaping_vars_per_vn m_rs_vn; 2764 size_t size = sizeof(struct rate_shaping_vars_per_vn); 2765 u32 addr = BAR_XSTRORM_INTMEM + 2766 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp)); 2767 2768 bp->mf_config[BP_VN(bp)] = mf_config; 2769 2770 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input); 2771 m_rs_vn.vn_counter.rate = 2772 cmng_input.vnic_max_rate[BP_VN(bp)]; 2773 m_rs_vn.vn_counter.quota = 2774 (m_rs_vn.vn_counter.rate * 2775 RS_PERIODIC_TIMEOUT_USEC) / 8; 2776 2777 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn); 2778 2779 /* read relevant values from mf_cfg struct in shmem */ 2780 vif_id = 2781 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 2782 FUNC_MF_CFG_E1HOV_TAG_MASK) >> 2783 FUNC_MF_CFG_E1HOV_TAG_SHIFT; 2784 vlan_val = 2785 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 2786 FUNC_MF_CFG_AFEX_VLAN_MASK) >> 2787 FUNC_MF_CFG_AFEX_VLAN_SHIFT; 2788 vlan_prio = (mf_config & 2789 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >> 2790 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT; 2791 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT); 2792 vlan_mode = 2793 (MF_CFG_RD(bp, 2794 func_mf_config[func].afex_config) & 2795 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >> 2796 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT; 2797 allowed_prio = 2798 (MF_CFG_RD(bp, 2799 func_mf_config[func].afex_config) & 2800 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >> 2801 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT; 2802 2803 /* send ramrod to FW, return in case of failure */ 2804 if (bnx2x_afex_func_update(bp, vif_id, vlan_val, 2805 allowed_prio)) 2806 return; 2807 2808 bp->afex_def_vlan_tag = vlan_val; 2809 bp->afex_vlan_mode = vlan_mode; 2810 } else { 2811 /* notify link down because BP->flags is disabled */ 2812 bnx2x_link_report(bp); 2813 2814 /* send INVALID VIF ramrod to FW */ 2815 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0); 2816 2817 /* Reset the default afex VLAN */ 2818 bp->afex_def_vlan_tag = -1; 2819 } 2820 } 2821 } 2822 2823 static void bnx2x_pmf_update(struct bnx2x *bp) 2824 { 2825 int port = BP_PORT(bp); 2826 u32 val; 2827 2828 bp->port.pmf = 1; 2829 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf); 2830 2831 /* 2832 * We need the mb() to ensure the ordering between the writing to 2833 * bp->port.pmf here and reading it from the bnx2x_periodic_task(). 2834 */ 2835 smp_mb(); 2836 2837 /* queue a periodic task */ 2838 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2839 2840 bnx2x_dcbx_pmf_update(bp); 2841 2842 /* enable nig attention */ 2843 val = (0xff0f | (1 << (BP_VN(bp) + 4))); 2844 if (bp->common.int_block == INT_BLOCK_HC) { 2845 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 2846 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 2847 } else if (!CHIP_IS_E1x(bp)) { 2848 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 2849 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 2850 } 2851 2852 bnx2x_stats_handle(bp, STATS_EVENT_PMF); 2853 } 2854 2855 /* end of Link */ 2856 2857 /* slow path */ 2858 2859 /* 2860 * General service functions 2861 */ 2862 2863 /* send the MCP a request, block until there is a reply */ 2864 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) 2865 { 2866 int mb_idx = BP_FW_MB_IDX(bp); 2867 u32 seq; 2868 u32 rc = 0; 2869 u32 cnt = 1; 2870 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; 2871 2872 mutex_lock(&bp->fw_mb_mutex); 2873 seq = ++bp->fw_seq; 2874 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); 2875 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); 2876 2877 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", 2878 (command | seq), param); 2879 2880 do { 2881 /* let the FW do it's magic ... */ 2882 msleep(delay); 2883 2884 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); 2885 2886 /* Give the FW up to 5 second (500*10ms) */ 2887 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); 2888 2889 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", 2890 cnt*delay, rc, seq); 2891 2892 /* is this a reply to our command? */ 2893 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) 2894 rc &= FW_MSG_CODE_MASK; 2895 else { 2896 /* FW BUG! */ 2897 BNX2X_ERR("FW failed to respond!\n"); 2898 bnx2x_fw_dump(bp); 2899 rc = 0; 2900 } 2901 mutex_unlock(&bp->fw_mb_mutex); 2902 2903 return rc; 2904 } 2905 2906 2907 static void storm_memset_func_cfg(struct bnx2x *bp, 2908 struct tstorm_eth_function_common_config *tcfg, 2909 u16 abs_fid) 2910 { 2911 size_t size = sizeof(struct tstorm_eth_function_common_config); 2912 2913 u32 addr = BAR_TSTRORM_INTMEM + 2914 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid); 2915 2916 __storm_memset_struct(bp, addr, size, (u32 *)tcfg); 2917 } 2918 2919 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) 2920 { 2921 if (CHIP_IS_E1x(bp)) { 2922 struct tstorm_eth_function_common_config tcfg = {0}; 2923 2924 storm_memset_func_cfg(bp, &tcfg, p->func_id); 2925 } 2926 2927 /* Enable the function in the FW */ 2928 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); 2929 storm_memset_func_en(bp, p->func_id, 1); 2930 2931 /* spq */ 2932 if (p->func_flgs & FUNC_FLG_SPQ) { 2933 storm_memset_spq_addr(bp, p->spq_map, p->func_id); 2934 REG_WR(bp, XSEM_REG_FAST_MEMORY + 2935 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); 2936 } 2937 } 2938 2939 /** 2940 * bnx2x_get_tx_only_flags - Return common flags 2941 * 2942 * @bp device handle 2943 * @fp queue handle 2944 * @zero_stats TRUE if statistics zeroing is needed 2945 * 2946 * Return the flags that are common for the Tx-only and not normal connections. 2947 */ 2948 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp, 2949 struct bnx2x_fastpath *fp, 2950 bool zero_stats) 2951 { 2952 unsigned long flags = 0; 2953 2954 /* PF driver will always initialize the Queue to an ACTIVE state */ 2955 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); 2956 2957 /* tx only connections collect statistics (on the same index as the 2958 * parent connection). The statistics are zeroed when the parent 2959 * connection is initialized. 2960 */ 2961 2962 __set_bit(BNX2X_Q_FLG_STATS, &flags); 2963 if (zero_stats) 2964 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); 2965 2966 2967 #ifdef BNX2X_STOP_ON_ERROR 2968 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags); 2969 #endif 2970 2971 return flags; 2972 } 2973 2974 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp, 2975 struct bnx2x_fastpath *fp, 2976 bool leading) 2977 { 2978 unsigned long flags = 0; 2979 2980 /* calculate other queue flags */ 2981 if (IS_MF_SD(bp)) 2982 __set_bit(BNX2X_Q_FLG_OV, &flags); 2983 2984 if (IS_FCOE_FP(fp)) { 2985 __set_bit(BNX2X_Q_FLG_FCOE, &flags); 2986 /* For FCoE - force usage of default priority (for afex) */ 2987 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags); 2988 } 2989 2990 if (!fp->disable_tpa) { 2991 __set_bit(BNX2X_Q_FLG_TPA, &flags); 2992 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); 2993 if (fp->mode == TPA_MODE_GRO) 2994 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags); 2995 } 2996 2997 if (leading) { 2998 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); 2999 __set_bit(BNX2X_Q_FLG_MCAST, &flags); 3000 } 3001 3002 /* Always set HW VLAN stripping */ 3003 __set_bit(BNX2X_Q_FLG_VLAN, &flags); 3004 3005 /* configure silent vlan removal */ 3006 if (IS_MF_AFEX(bp)) 3007 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags); 3008 3009 3010 return flags | bnx2x_get_common_flags(bp, fp, true); 3011 } 3012 3013 static void bnx2x_pf_q_prep_general(struct bnx2x *bp, 3014 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, 3015 u8 cos) 3016 { 3017 gen_init->stat_id = bnx2x_stats_id(fp); 3018 gen_init->spcl_id = fp->cl_id; 3019 3020 /* Always use mini-jumbo MTU for FCoE L2 ring */ 3021 if (IS_FCOE_FP(fp)) 3022 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; 3023 else 3024 gen_init->mtu = bp->dev->mtu; 3025 3026 gen_init->cos = cos; 3027 } 3028 3029 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, 3030 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, 3031 struct bnx2x_rxq_setup_params *rxq_init) 3032 { 3033 u8 max_sge = 0; 3034 u16 sge_sz = 0; 3035 u16 tpa_agg_size = 0; 3036 3037 if (!fp->disable_tpa) { 3038 pause->sge_th_lo = SGE_TH_LO(bp); 3039 pause->sge_th_hi = SGE_TH_HI(bp); 3040 3041 /* validate SGE ring has enough to cross high threshold */ 3042 WARN_ON(bp->dropless_fc && 3043 pause->sge_th_hi + FW_PREFETCH_CNT > 3044 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); 3045 3046 tpa_agg_size = TPA_AGG_SIZE; 3047 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> 3048 SGE_PAGE_SHIFT; 3049 max_sge = ((max_sge + PAGES_PER_SGE - 1) & 3050 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; 3051 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff); 3052 } 3053 3054 /* pause - not for e1 */ 3055 if (!CHIP_IS_E1(bp)) { 3056 pause->bd_th_lo = BD_TH_LO(bp); 3057 pause->bd_th_hi = BD_TH_HI(bp); 3058 3059 pause->rcq_th_lo = RCQ_TH_LO(bp); 3060 pause->rcq_th_hi = RCQ_TH_HI(bp); 3061 /* 3062 * validate that rings have enough entries to cross 3063 * high thresholds 3064 */ 3065 WARN_ON(bp->dropless_fc && 3066 pause->bd_th_hi + FW_PREFETCH_CNT > 3067 bp->rx_ring_size); 3068 WARN_ON(bp->dropless_fc && 3069 pause->rcq_th_hi + FW_PREFETCH_CNT > 3070 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); 3071 3072 pause->pri_map = 1; 3073 } 3074 3075 /* rxq setup */ 3076 rxq_init->dscr_map = fp->rx_desc_mapping; 3077 rxq_init->sge_map = fp->rx_sge_mapping; 3078 rxq_init->rcq_map = fp->rx_comp_mapping; 3079 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; 3080 3081 /* This should be a maximum number of data bytes that may be 3082 * placed on the BD (not including paddings). 3083 */ 3084 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - 3085 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; 3086 3087 rxq_init->cl_qzone_id = fp->cl_qzone_id; 3088 rxq_init->tpa_agg_sz = tpa_agg_size; 3089 rxq_init->sge_buf_sz = sge_sz; 3090 rxq_init->max_sges_pkt = max_sge; 3091 rxq_init->rss_engine_id = BP_FUNC(bp); 3092 rxq_init->mcast_engine_id = BP_FUNC(bp); 3093 3094 /* Maximum number or simultaneous TPA aggregation for this Queue. 3095 * 3096 * For PF Clients it should be the maximum available number. 3097 * VF driver(s) may want to define it to a smaller value. 3098 */ 3099 rxq_init->max_tpa_queues = MAX_AGG_QS(bp); 3100 3101 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; 3102 rxq_init->fw_sb_id = fp->fw_sb_id; 3103 3104 if (IS_FCOE_FP(fp)) 3105 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; 3106 else 3107 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 3108 /* configure silent vlan removal 3109 * if multi function mode is afex, then mask default vlan 3110 */ 3111 if (IS_MF_AFEX(bp)) { 3112 rxq_init->silent_removal_value = bp->afex_def_vlan_tag; 3113 rxq_init->silent_removal_mask = VLAN_VID_MASK; 3114 } 3115 } 3116 3117 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, 3118 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, 3119 u8 cos) 3120 { 3121 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping; 3122 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; 3123 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; 3124 txq_init->fw_sb_id = fp->fw_sb_id; 3125 3126 /* 3127 * set the tss leading client id for TX classfication == 3128 * leading RSS client id 3129 */ 3130 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); 3131 3132 if (IS_FCOE_FP(fp)) { 3133 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; 3134 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; 3135 } 3136 } 3137 3138 static void bnx2x_pf_init(struct bnx2x *bp) 3139 { 3140 struct bnx2x_func_init_params func_init = {0}; 3141 struct event_ring_data eq_data = { {0} }; 3142 u16 flags; 3143 3144 if (!CHIP_IS_E1x(bp)) { 3145 /* reset IGU PF statistics: MSIX + ATTN */ 3146 /* PF */ 3147 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 3148 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 3149 (CHIP_MODE_IS_4_PORT(bp) ? 3150 BP_FUNC(bp) : BP_VN(bp))*4, 0); 3151 /* ATTN */ 3152 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 3153 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 3154 BNX2X_IGU_STAS_MSG_PF_CNT*4 + 3155 (CHIP_MODE_IS_4_PORT(bp) ? 3156 BP_FUNC(bp) : BP_VN(bp))*4, 0); 3157 } 3158 3159 /* function setup flags */ 3160 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); 3161 3162 /* This flag is relevant for E1x only. 3163 * E2 doesn't have a TPA configuration in a function level. 3164 */ 3165 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; 3166 3167 func_init.func_flgs = flags; 3168 func_init.pf_id = BP_FUNC(bp); 3169 func_init.func_id = BP_FUNC(bp); 3170 func_init.spq_map = bp->spq_mapping; 3171 func_init.spq_prod = bp->spq_prod_idx; 3172 3173 bnx2x_func_init(bp, &func_init); 3174 3175 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); 3176 3177 /* 3178 * Congestion management values depend on the link rate 3179 * There is no active link so initial link rate is set to 10 Gbps. 3180 * When the link comes up The congestion management values are 3181 * re-calculated according to the actual link rate. 3182 */ 3183 bp->link_vars.line_speed = SPEED_10000; 3184 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); 3185 3186 /* Only the PMF sets the HW */ 3187 if (bp->port.pmf) 3188 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 3189 3190 /* init Event Queue - PCI bus guarantees correct endianity*/ 3191 eq_data.base_addr.hi = U64_HI(bp->eq_mapping); 3192 eq_data.base_addr.lo = U64_LO(bp->eq_mapping); 3193 eq_data.producer = bp->eq_prod; 3194 eq_data.index_id = HC_SP_INDEX_EQ_CONS; 3195 eq_data.sb_id = DEF_SB_ID; 3196 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); 3197 } 3198 3199 3200 static void bnx2x_e1h_disable(struct bnx2x *bp) 3201 { 3202 int port = BP_PORT(bp); 3203 3204 bnx2x_tx_disable(bp); 3205 3206 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 3207 } 3208 3209 static void bnx2x_e1h_enable(struct bnx2x *bp) 3210 { 3211 int port = BP_PORT(bp); 3212 3213 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 3214 3215 /* Tx queue should be only reenabled */ 3216 netif_tx_wake_all_queues(bp->dev); 3217 3218 /* 3219 * Should not call netif_carrier_on since it will be called if the link 3220 * is up when checking for link state 3221 */ 3222 } 3223 3224 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 3225 3226 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) 3227 { 3228 struct eth_stats_info *ether_stat = 3229 &bp->slowpath->drv_info_to_mcp.ether_stat; 3230 3231 strlcpy(ether_stat->version, DRV_MODULE_VERSION, 3232 ETH_STAT_INFO_VERSION_LEN); 3233 3234 bp->sp_objs[0].mac_obj.get_n_elements(bp, &bp->sp_objs[0].mac_obj, 3235 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, 3236 ether_stat->mac_local); 3237 3238 ether_stat->mtu_size = bp->dev->mtu; 3239 3240 if (bp->dev->features & NETIF_F_RXCSUM) 3241 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; 3242 if (bp->dev->features & NETIF_F_TSO) 3243 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; 3244 ether_stat->feature_flags |= bp->common.boot_mode; 3245 3246 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; 3247 3248 ether_stat->txq_size = bp->tx_ring_size; 3249 ether_stat->rxq_size = bp->rx_ring_size; 3250 } 3251 3252 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) 3253 { 3254 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 3255 struct fcoe_stats_info *fcoe_stat = 3256 &bp->slowpath->drv_info_to_mcp.fcoe_stat; 3257 3258 if (!CNIC_LOADED(bp)) 3259 return; 3260 3261 memcpy(fcoe_stat->mac_local + MAC_LEADING_ZERO_CNT, 3262 bp->fip_mac, ETH_ALEN); 3263 3264 fcoe_stat->qos_priority = 3265 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; 3266 3267 /* insert FCoE stats from ramrod response */ 3268 if (!NO_FCOE(bp)) { 3269 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = 3270 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. 3271 tstorm_queue_statistics; 3272 3273 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = 3274 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. 3275 xstorm_queue_statistics; 3276 3277 struct fcoe_statistics_params *fw_fcoe_stat = 3278 &bp->fw_stats_data->fcoe; 3279 3280 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0, 3281 fcoe_stat->rx_bytes_lo, 3282 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); 3283 3284 ADD_64_LE(fcoe_stat->rx_bytes_hi, 3285 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, 3286 fcoe_stat->rx_bytes_lo, 3287 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); 3288 3289 ADD_64_LE(fcoe_stat->rx_bytes_hi, 3290 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, 3291 fcoe_stat->rx_bytes_lo, 3292 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); 3293 3294 ADD_64_LE(fcoe_stat->rx_bytes_hi, 3295 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, 3296 fcoe_stat->rx_bytes_lo, 3297 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); 3298 3299 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, 3300 fcoe_stat->rx_frames_lo, 3301 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); 3302 3303 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, 3304 fcoe_stat->rx_frames_lo, 3305 fcoe_q_tstorm_stats->rcv_ucast_pkts); 3306 3307 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, 3308 fcoe_stat->rx_frames_lo, 3309 fcoe_q_tstorm_stats->rcv_bcast_pkts); 3310 3311 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, 3312 fcoe_stat->rx_frames_lo, 3313 fcoe_q_tstorm_stats->rcv_mcast_pkts); 3314 3315 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0, 3316 fcoe_stat->tx_bytes_lo, 3317 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); 3318 3319 ADD_64_LE(fcoe_stat->tx_bytes_hi, 3320 fcoe_q_xstorm_stats->ucast_bytes_sent.hi, 3321 fcoe_stat->tx_bytes_lo, 3322 fcoe_q_xstorm_stats->ucast_bytes_sent.lo); 3323 3324 ADD_64_LE(fcoe_stat->tx_bytes_hi, 3325 fcoe_q_xstorm_stats->bcast_bytes_sent.hi, 3326 fcoe_stat->tx_bytes_lo, 3327 fcoe_q_xstorm_stats->bcast_bytes_sent.lo); 3328 3329 ADD_64_LE(fcoe_stat->tx_bytes_hi, 3330 fcoe_q_xstorm_stats->mcast_bytes_sent.hi, 3331 fcoe_stat->tx_bytes_lo, 3332 fcoe_q_xstorm_stats->mcast_bytes_sent.lo); 3333 3334 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, 3335 fcoe_stat->tx_frames_lo, 3336 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); 3337 3338 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, 3339 fcoe_stat->tx_frames_lo, 3340 fcoe_q_xstorm_stats->ucast_pkts_sent); 3341 3342 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, 3343 fcoe_stat->tx_frames_lo, 3344 fcoe_q_xstorm_stats->bcast_pkts_sent); 3345 3346 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, 3347 fcoe_stat->tx_frames_lo, 3348 fcoe_q_xstorm_stats->mcast_pkts_sent); 3349 } 3350 3351 /* ask L5 driver to add data to the struct */ 3352 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); 3353 } 3354 3355 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) 3356 { 3357 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 3358 struct iscsi_stats_info *iscsi_stat = 3359 &bp->slowpath->drv_info_to_mcp.iscsi_stat; 3360 3361 if (!CNIC_LOADED(bp)) 3362 return; 3363 3364 memcpy(iscsi_stat->mac_local + MAC_LEADING_ZERO_CNT, 3365 bp->cnic_eth_dev.iscsi_mac, ETH_ALEN); 3366 3367 iscsi_stat->qos_priority = 3368 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; 3369 3370 /* ask L5 driver to add data to the struct */ 3371 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); 3372 } 3373 3374 /* called due to MCP event (on pmf): 3375 * reread new bandwidth configuration 3376 * configure FW 3377 * notify others function about the change 3378 */ 3379 static void bnx2x_config_mf_bw(struct bnx2x *bp) 3380 { 3381 if (bp->link_vars.link_up) { 3382 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); 3383 bnx2x_link_sync_notify(bp); 3384 } 3385 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 3386 } 3387 3388 static void bnx2x_set_mf_bw(struct bnx2x *bp) 3389 { 3390 bnx2x_config_mf_bw(bp); 3391 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); 3392 } 3393 3394 static void bnx2x_handle_eee_event(struct bnx2x *bp) 3395 { 3396 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n"); 3397 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0); 3398 } 3399 3400 static void bnx2x_handle_drv_info_req(struct bnx2x *bp) 3401 { 3402 enum drv_info_opcode op_code; 3403 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); 3404 3405 /* if drv_info version supported by MFW doesn't match - send NACK */ 3406 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { 3407 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3408 return; 3409 } 3410 3411 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> 3412 DRV_INFO_CONTROL_OP_CODE_SHIFT; 3413 3414 memset(&bp->slowpath->drv_info_to_mcp, 0, 3415 sizeof(union drv_info_to_mcp)); 3416 3417 switch (op_code) { 3418 case ETH_STATS_OPCODE: 3419 bnx2x_drv_info_ether_stat(bp); 3420 break; 3421 case FCOE_STATS_OPCODE: 3422 bnx2x_drv_info_fcoe_stat(bp); 3423 break; 3424 case ISCSI_STATS_OPCODE: 3425 bnx2x_drv_info_iscsi_stat(bp); 3426 break; 3427 default: 3428 /* if op code isn't supported - send NACK */ 3429 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3430 return; 3431 } 3432 3433 /* if we got drv_info attn from MFW then these fields are defined in 3434 * shmem2 for sure 3435 */ 3436 SHMEM2_WR(bp, drv_info_host_addr_lo, 3437 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3438 SHMEM2_WR(bp, drv_info_host_addr_hi, 3439 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3440 3441 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); 3442 } 3443 3444 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) 3445 { 3446 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); 3447 3448 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { 3449 3450 /* 3451 * This is the only place besides the function initialization 3452 * where the bp->flags can change so it is done without any 3453 * locks 3454 */ 3455 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { 3456 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n"); 3457 bp->flags |= MF_FUNC_DIS; 3458 3459 bnx2x_e1h_disable(bp); 3460 } else { 3461 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n"); 3462 bp->flags &= ~MF_FUNC_DIS; 3463 3464 bnx2x_e1h_enable(bp); 3465 } 3466 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; 3467 } 3468 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { 3469 bnx2x_config_mf_bw(bp); 3470 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; 3471 } 3472 3473 /* Report results to MCP */ 3474 if (dcc_event) 3475 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); 3476 else 3477 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); 3478 } 3479 3480 /* must be called under the spq lock */ 3481 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) 3482 { 3483 struct eth_spe *next_spe = bp->spq_prod_bd; 3484 3485 if (bp->spq_prod_bd == bp->spq_last_bd) { 3486 bp->spq_prod_bd = bp->spq; 3487 bp->spq_prod_idx = 0; 3488 DP(BNX2X_MSG_SP, "end of spq\n"); 3489 } else { 3490 bp->spq_prod_bd++; 3491 bp->spq_prod_idx++; 3492 } 3493 return next_spe; 3494 } 3495 3496 /* must be called under the spq lock */ 3497 static void bnx2x_sp_prod_update(struct bnx2x *bp) 3498 { 3499 int func = BP_FUNC(bp); 3500 3501 /* 3502 * Make sure that BD data is updated before writing the producer: 3503 * BD data is written to the memory, the producer is read from the 3504 * memory, thus we need a full memory barrier to ensure the ordering. 3505 */ 3506 mb(); 3507 3508 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), 3509 bp->spq_prod_idx); 3510 mmiowb(); 3511 } 3512 3513 /** 3514 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ 3515 * 3516 * @cmd: command to check 3517 * @cmd_type: command type 3518 */ 3519 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) 3520 { 3521 if ((cmd_type == NONE_CONNECTION_TYPE) || 3522 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || 3523 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || 3524 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || 3525 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || 3526 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || 3527 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) 3528 return true; 3529 else 3530 return false; 3531 3532 } 3533 3534 3535 /** 3536 * bnx2x_sp_post - place a single command on an SP ring 3537 * 3538 * @bp: driver handle 3539 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) 3540 * @cid: SW CID the command is related to 3541 * @data_hi: command private data address (high 32 bits) 3542 * @data_lo: command private data address (low 32 bits) 3543 * @cmd_type: command type (e.g. NONE, ETH) 3544 * 3545 * SP data is handled as if it's always an address pair, thus data fields are 3546 * not swapped to little endian in upper functions. Instead this function swaps 3547 * data as if it's two u32 fields. 3548 */ 3549 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 3550 u32 data_hi, u32 data_lo, int cmd_type) 3551 { 3552 struct eth_spe *spe; 3553 u16 type; 3554 bool common = bnx2x_is_contextless_ramrod(command, cmd_type); 3555 3556 #ifdef BNX2X_STOP_ON_ERROR 3557 if (unlikely(bp->panic)) { 3558 BNX2X_ERR("Can't post SP when there is panic\n"); 3559 return -EIO; 3560 } 3561 #endif 3562 3563 spin_lock_bh(&bp->spq_lock); 3564 3565 if (common) { 3566 if (!atomic_read(&bp->eq_spq_left)) { 3567 BNX2X_ERR("BUG! EQ ring full!\n"); 3568 spin_unlock_bh(&bp->spq_lock); 3569 bnx2x_panic(); 3570 return -EBUSY; 3571 } 3572 } else if (!atomic_read(&bp->cq_spq_left)) { 3573 BNX2X_ERR("BUG! SPQ ring full!\n"); 3574 spin_unlock_bh(&bp->spq_lock); 3575 bnx2x_panic(); 3576 return -EBUSY; 3577 } 3578 3579 spe = bnx2x_sp_get_next(bp); 3580 3581 /* CID needs port number to be encoded int it */ 3582 spe->hdr.conn_and_cmd_data = 3583 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | 3584 HW_CID(bp, cid)); 3585 3586 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; 3587 3588 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & 3589 SPE_HDR_FUNCTION_ID); 3590 3591 spe->hdr.type = cpu_to_le16(type); 3592 3593 spe->data.update_data_addr.hi = cpu_to_le32(data_hi); 3594 spe->data.update_data_addr.lo = cpu_to_le32(data_lo); 3595 3596 /* 3597 * It's ok if the actual decrement is issued towards the memory 3598 * somewhere between the spin_lock and spin_unlock. Thus no 3599 * more explict memory barrier is needed. 3600 */ 3601 if (common) 3602 atomic_dec(&bp->eq_spq_left); 3603 else 3604 atomic_dec(&bp->cq_spq_left); 3605 3606 3607 DP(BNX2X_MSG_SP, 3608 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n", 3609 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), 3610 (u32)(U64_LO(bp->spq_mapping) + 3611 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, 3612 HW_CID(bp, cid), data_hi, data_lo, type, 3613 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); 3614 3615 bnx2x_sp_prod_update(bp); 3616 spin_unlock_bh(&bp->spq_lock); 3617 return 0; 3618 } 3619 3620 /* acquire split MCP access lock register */ 3621 static int bnx2x_acquire_alr(struct bnx2x *bp) 3622 { 3623 u32 j, val; 3624 int rc = 0; 3625 3626 might_sleep(); 3627 for (j = 0; j < 1000; j++) { 3628 val = (1UL << 31); 3629 REG_WR(bp, GRCBASE_MCP + 0x9c, val); 3630 val = REG_RD(bp, GRCBASE_MCP + 0x9c); 3631 if (val & (1L << 31)) 3632 break; 3633 3634 msleep(5); 3635 } 3636 if (!(val & (1L << 31))) { 3637 BNX2X_ERR("Cannot acquire MCP access lock register\n"); 3638 rc = -EBUSY; 3639 } 3640 3641 return rc; 3642 } 3643 3644 /* release split MCP access lock register */ 3645 static void bnx2x_release_alr(struct bnx2x *bp) 3646 { 3647 REG_WR(bp, GRCBASE_MCP + 0x9c, 0); 3648 } 3649 3650 #define BNX2X_DEF_SB_ATT_IDX 0x0001 3651 #define BNX2X_DEF_SB_IDX 0x0002 3652 3653 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp) 3654 { 3655 struct host_sp_status_block *def_sb = bp->def_status_blk; 3656 u16 rc = 0; 3657 3658 barrier(); /* status block is written to by the chip */ 3659 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { 3660 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; 3661 rc |= BNX2X_DEF_SB_ATT_IDX; 3662 } 3663 3664 if (bp->def_idx != def_sb->sp_sb.running_index) { 3665 bp->def_idx = def_sb->sp_sb.running_index; 3666 rc |= BNX2X_DEF_SB_IDX; 3667 } 3668 3669 /* Do not reorder: indecies reading should complete before handling */ 3670 barrier(); 3671 return rc; 3672 } 3673 3674 /* 3675 * slow path service functions 3676 */ 3677 3678 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) 3679 { 3680 int port = BP_PORT(bp); 3681 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 3682 MISC_REG_AEU_MASK_ATTN_FUNC_0; 3683 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : 3684 NIG_REG_MASK_INTERRUPT_PORT0; 3685 u32 aeu_mask; 3686 u32 nig_mask = 0; 3687 u32 reg_addr; 3688 3689 if (bp->attn_state & asserted) 3690 BNX2X_ERR("IGU ERROR\n"); 3691 3692 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3693 aeu_mask = REG_RD(bp, aeu_addr); 3694 3695 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", 3696 aeu_mask, asserted); 3697 aeu_mask &= ~(asserted & 0x3ff); 3698 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 3699 3700 REG_WR(bp, aeu_addr, aeu_mask); 3701 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3702 3703 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 3704 bp->attn_state |= asserted; 3705 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 3706 3707 if (asserted & ATTN_HARD_WIRED_MASK) { 3708 if (asserted & ATTN_NIG_FOR_FUNC) { 3709 3710 bnx2x_acquire_phy_lock(bp); 3711 3712 /* save nig interrupt mask */ 3713 nig_mask = REG_RD(bp, nig_int_mask_addr); 3714 3715 /* If nig_mask is not set, no need to call the update 3716 * function. 3717 */ 3718 if (nig_mask) { 3719 REG_WR(bp, nig_int_mask_addr, 0); 3720 3721 bnx2x_link_attn(bp); 3722 } 3723 3724 /* handle unicore attn? */ 3725 } 3726 if (asserted & ATTN_SW_TIMER_4_FUNC) 3727 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); 3728 3729 if (asserted & GPIO_2_FUNC) 3730 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); 3731 3732 if (asserted & GPIO_3_FUNC) 3733 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); 3734 3735 if (asserted & GPIO_4_FUNC) 3736 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); 3737 3738 if (port == 0) { 3739 if (asserted & ATTN_GENERAL_ATTN_1) { 3740 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); 3741 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); 3742 } 3743 if (asserted & ATTN_GENERAL_ATTN_2) { 3744 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); 3745 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); 3746 } 3747 if (asserted & ATTN_GENERAL_ATTN_3) { 3748 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); 3749 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); 3750 } 3751 } else { 3752 if (asserted & ATTN_GENERAL_ATTN_4) { 3753 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); 3754 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); 3755 } 3756 if (asserted & ATTN_GENERAL_ATTN_5) { 3757 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); 3758 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); 3759 } 3760 if (asserted & ATTN_GENERAL_ATTN_6) { 3761 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); 3762 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); 3763 } 3764 } 3765 3766 } /* if hardwired */ 3767 3768 if (bp->common.int_block == INT_BLOCK_HC) 3769 reg_addr = (HC_REG_COMMAND_REG + port*32 + 3770 COMMAND_REG_ATTN_BITS_SET); 3771 else 3772 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); 3773 3774 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, 3775 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 3776 REG_WR(bp, reg_addr, asserted); 3777 3778 /* now set back the mask */ 3779 if (asserted & ATTN_NIG_FOR_FUNC) { 3780 /* Verify that IGU ack through BAR was written before restoring 3781 * NIG mask. This loop should exit after 2-3 iterations max. 3782 */ 3783 if (bp->common.int_block != INT_BLOCK_HC) { 3784 u32 cnt = 0, igu_acked; 3785 do { 3786 igu_acked = REG_RD(bp, 3787 IGU_REG_ATTENTION_ACK_BITS); 3788 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) && 3789 (++cnt < MAX_IGU_ATTN_ACK_TO)); 3790 if (!igu_acked) 3791 DP(NETIF_MSG_HW, 3792 "Failed to verify IGU ack on time\n"); 3793 barrier(); 3794 } 3795 REG_WR(bp, nig_int_mask_addr, nig_mask); 3796 bnx2x_release_phy_lock(bp); 3797 } 3798 } 3799 3800 static void bnx2x_fan_failure(struct bnx2x *bp) 3801 { 3802 int port = BP_PORT(bp); 3803 u32 ext_phy_config; 3804 /* mark the failure */ 3805 ext_phy_config = 3806 SHMEM_RD(bp, 3807 dev_info.port_hw_config[port].external_phy_config); 3808 3809 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 3810 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; 3811 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, 3812 ext_phy_config); 3813 3814 /* log the failure */ 3815 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n" 3816 "Please contact OEM Support for assistance\n"); 3817 3818 /* 3819 * Schedule device reset (unload) 3820 * This is due to some boards consuming sufficient power when driver is 3821 * up to overheat if fan fails. 3822 */ 3823 smp_mb__before_clear_bit(); 3824 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state); 3825 smp_mb__after_clear_bit(); 3826 schedule_delayed_work(&bp->sp_rtnl_task, 0); 3827 3828 } 3829 3830 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) 3831 { 3832 int port = BP_PORT(bp); 3833 int reg_offset; 3834 u32 val; 3835 3836 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 3837 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 3838 3839 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { 3840 3841 val = REG_RD(bp, reg_offset); 3842 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; 3843 REG_WR(bp, reg_offset, val); 3844 3845 BNX2X_ERR("SPIO5 hw attention\n"); 3846 3847 /* Fan failure attention */ 3848 bnx2x_hw_reset_phy(&bp->link_params); 3849 bnx2x_fan_failure(bp); 3850 } 3851 3852 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { 3853 bnx2x_acquire_phy_lock(bp); 3854 bnx2x_handle_module_detect_int(&bp->link_params); 3855 bnx2x_release_phy_lock(bp); 3856 } 3857 3858 if (attn & HW_INTERRUT_ASSERT_SET_0) { 3859 3860 val = REG_RD(bp, reg_offset); 3861 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); 3862 REG_WR(bp, reg_offset, val); 3863 3864 BNX2X_ERR("FATAL HW block attention set0 0x%x\n", 3865 (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); 3866 bnx2x_panic(); 3867 } 3868 } 3869 3870 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) 3871 { 3872 u32 val; 3873 3874 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { 3875 3876 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); 3877 BNX2X_ERR("DB hw attention 0x%x\n", val); 3878 /* DORQ discard attention */ 3879 if (val & 0x2) 3880 BNX2X_ERR("FATAL error from DORQ\n"); 3881 } 3882 3883 if (attn & HW_INTERRUT_ASSERT_SET_1) { 3884 3885 int port = BP_PORT(bp); 3886 int reg_offset; 3887 3888 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : 3889 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); 3890 3891 val = REG_RD(bp, reg_offset); 3892 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); 3893 REG_WR(bp, reg_offset, val); 3894 3895 BNX2X_ERR("FATAL HW block attention set1 0x%x\n", 3896 (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); 3897 bnx2x_panic(); 3898 } 3899 } 3900 3901 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) 3902 { 3903 u32 val; 3904 3905 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { 3906 3907 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); 3908 BNX2X_ERR("CFC hw attention 0x%x\n", val); 3909 /* CFC error attention */ 3910 if (val & 0x2) 3911 BNX2X_ERR("FATAL error from CFC\n"); 3912 } 3913 3914 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { 3915 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); 3916 BNX2X_ERR("PXP hw attention-0 0x%x\n", val); 3917 /* RQ_USDMDP_FIFO_OVERFLOW */ 3918 if (val & 0x18000) 3919 BNX2X_ERR("FATAL error from PXP\n"); 3920 3921 if (!CHIP_IS_E1x(bp)) { 3922 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); 3923 BNX2X_ERR("PXP hw attention-1 0x%x\n", val); 3924 } 3925 } 3926 3927 if (attn & HW_INTERRUT_ASSERT_SET_2) { 3928 3929 int port = BP_PORT(bp); 3930 int reg_offset; 3931 3932 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : 3933 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); 3934 3935 val = REG_RD(bp, reg_offset); 3936 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); 3937 REG_WR(bp, reg_offset, val); 3938 3939 BNX2X_ERR("FATAL HW block attention set2 0x%x\n", 3940 (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); 3941 bnx2x_panic(); 3942 } 3943 } 3944 3945 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) 3946 { 3947 u32 val; 3948 3949 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { 3950 3951 if (attn & BNX2X_PMF_LINK_ASSERT) { 3952 int func = BP_FUNC(bp); 3953 3954 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 3955 bnx2x_read_mf_cfg(bp); 3956 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, 3957 func_mf_config[BP_ABS_FUNC(bp)].config); 3958 val = SHMEM_RD(bp, 3959 func_mb[BP_FW_MB_IDX(bp)].drv_status); 3960 if (val & DRV_STATUS_DCC_EVENT_MASK) 3961 bnx2x_dcc_event(bp, 3962 (val & DRV_STATUS_DCC_EVENT_MASK)); 3963 3964 if (val & DRV_STATUS_SET_MF_BW) 3965 bnx2x_set_mf_bw(bp); 3966 3967 if (val & DRV_STATUS_DRV_INFO_REQ) 3968 bnx2x_handle_drv_info_req(bp); 3969 3970 if (val & DRV_STATUS_VF_DISABLED) 3971 bnx2x_vf_handle_flr_event(bp); 3972 3973 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) 3974 bnx2x_pmf_update(bp); 3975 3976 if (bp->port.pmf && 3977 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && 3978 bp->dcbx_enabled > 0) 3979 /* start dcbx state machine */ 3980 bnx2x_dcbx_set_params(bp, 3981 BNX2X_DCBX_STATE_NEG_RECEIVED); 3982 if (val & DRV_STATUS_AFEX_EVENT_MASK) 3983 bnx2x_handle_afex_cmd(bp, 3984 val & DRV_STATUS_AFEX_EVENT_MASK); 3985 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS) 3986 bnx2x_handle_eee_event(bp); 3987 if (bp->link_vars.periodic_flags & 3988 PERIODIC_FLAGS_LINK_EVENT) { 3989 /* sync with link */ 3990 bnx2x_acquire_phy_lock(bp); 3991 bp->link_vars.periodic_flags &= 3992 ~PERIODIC_FLAGS_LINK_EVENT; 3993 bnx2x_release_phy_lock(bp); 3994 if (IS_MF(bp)) 3995 bnx2x_link_sync_notify(bp); 3996 bnx2x_link_report(bp); 3997 } 3998 /* Always call it here: bnx2x_link_report() will 3999 * prevent the link indication duplication. 4000 */ 4001 bnx2x__link_status_update(bp); 4002 } else if (attn & BNX2X_MC_ASSERT_BITS) { 4003 4004 BNX2X_ERR("MC assert!\n"); 4005 bnx2x_mc_assert(bp); 4006 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); 4007 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); 4008 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); 4009 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); 4010 bnx2x_panic(); 4011 4012 } else if (attn & BNX2X_MCP_ASSERT) { 4013 4014 BNX2X_ERR("MCP assert!\n"); 4015 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); 4016 bnx2x_fw_dump(bp); 4017 4018 } else 4019 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); 4020 } 4021 4022 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { 4023 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); 4024 if (attn & BNX2X_GRC_TIMEOUT) { 4025 val = CHIP_IS_E1(bp) ? 0 : 4026 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); 4027 BNX2X_ERR("GRC time-out 0x%08x\n", val); 4028 } 4029 if (attn & BNX2X_GRC_RSV) { 4030 val = CHIP_IS_E1(bp) ? 0 : 4031 REG_RD(bp, MISC_REG_GRC_RSV_ATTN); 4032 BNX2X_ERR("GRC reserved 0x%08x\n", val); 4033 } 4034 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); 4035 } 4036 } 4037 4038 /* 4039 * Bits map: 4040 * 0-7 - Engine0 load counter. 4041 * 8-15 - Engine1 load counter. 4042 * 16 - Engine0 RESET_IN_PROGRESS bit. 4043 * 17 - Engine1 RESET_IN_PROGRESS bit. 4044 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function 4045 * on the engine 4046 * 19 - Engine1 ONE_IS_LOADED. 4047 * 20 - Chip reset flow bit. When set none-leader must wait for both engines 4048 * leader to complete (check for both RESET_IN_PROGRESS bits and not for 4049 * just the one belonging to its engine). 4050 * 4051 */ 4052 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 4053 4054 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff 4055 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0 4056 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 4057 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8 4058 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 4059 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 4060 #define BNX2X_GLOBAL_RESET_BIT 0x00040000 4061 4062 /* 4063 * Set the GLOBAL_RESET bit. 4064 * 4065 * Should be run under rtnl lock 4066 */ 4067 void bnx2x_set_reset_global(struct bnx2x *bp) 4068 { 4069 u32 val; 4070 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4071 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4072 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); 4073 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4074 } 4075 4076 /* 4077 * Clear the GLOBAL_RESET bit. 4078 * 4079 * Should be run under rtnl lock 4080 */ 4081 static void bnx2x_clear_reset_global(struct bnx2x *bp) 4082 { 4083 u32 val; 4084 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4085 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4086 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); 4087 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4088 } 4089 4090 /* 4091 * Checks the GLOBAL_RESET bit. 4092 * 4093 * should be run under rtnl lock 4094 */ 4095 static bool bnx2x_reset_is_global(struct bnx2x *bp) 4096 { 4097 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4098 4099 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); 4100 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; 4101 } 4102 4103 /* 4104 * Clear RESET_IN_PROGRESS bit for the current engine. 4105 * 4106 * Should be run under rtnl lock 4107 */ 4108 static void bnx2x_set_reset_done(struct bnx2x *bp) 4109 { 4110 u32 val; 4111 u32 bit = BP_PATH(bp) ? 4112 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 4113 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4114 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4115 4116 /* Clear the bit */ 4117 val &= ~bit; 4118 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 4119 4120 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4121 } 4122 4123 /* 4124 * Set RESET_IN_PROGRESS for the current engine. 4125 * 4126 * should be run under rtnl lock 4127 */ 4128 void bnx2x_set_reset_in_progress(struct bnx2x *bp) 4129 { 4130 u32 val; 4131 u32 bit = BP_PATH(bp) ? 4132 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 4133 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4134 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4135 4136 /* Set the bit */ 4137 val |= bit; 4138 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 4139 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4140 } 4141 4142 /* 4143 * Checks the RESET_IN_PROGRESS bit for the given engine. 4144 * should be run under rtnl lock 4145 */ 4146 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) 4147 { 4148 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4149 u32 bit = engine ? 4150 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 4151 4152 /* return false if bit is set */ 4153 return (val & bit) ? false : true; 4154 } 4155 4156 /* 4157 * set pf load for the current pf. 4158 * 4159 * should be run under rtnl lock 4160 */ 4161 void bnx2x_set_pf_load(struct bnx2x *bp) 4162 { 4163 u32 val1, val; 4164 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 4165 BNX2X_PATH0_LOAD_CNT_MASK; 4166 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 4167 BNX2X_PATH0_LOAD_CNT_SHIFT; 4168 4169 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4170 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4171 4172 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val); 4173 4174 /* get the current counter value */ 4175 val1 = (val & mask) >> shift; 4176 4177 /* set bit of that PF */ 4178 val1 |= (1 << bp->pf_num); 4179 4180 /* clear the old value */ 4181 val &= ~mask; 4182 4183 /* set the new one */ 4184 val |= ((val1 << shift) & mask); 4185 4186 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 4187 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4188 } 4189 4190 /** 4191 * bnx2x_clear_pf_load - clear pf load mark 4192 * 4193 * @bp: driver handle 4194 * 4195 * Should be run under rtnl lock. 4196 * Decrements the load counter for the current engine. Returns 4197 * whether other functions are still loaded 4198 */ 4199 bool bnx2x_clear_pf_load(struct bnx2x *bp) 4200 { 4201 u32 val1, val; 4202 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 4203 BNX2X_PATH0_LOAD_CNT_MASK; 4204 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 4205 BNX2X_PATH0_LOAD_CNT_SHIFT; 4206 4207 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4208 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4209 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val); 4210 4211 /* get the current counter value */ 4212 val1 = (val & mask) >> shift; 4213 4214 /* clear bit of that PF */ 4215 val1 &= ~(1 << bp->pf_num); 4216 4217 /* clear the old value */ 4218 val &= ~mask; 4219 4220 /* set the new one */ 4221 val |= ((val1 << shift) & mask); 4222 4223 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 4224 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4225 return val1 != 0; 4226 } 4227 4228 /* 4229 * Read the load status for the current engine. 4230 * 4231 * should be run under rtnl lock 4232 */ 4233 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine) 4234 { 4235 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : 4236 BNX2X_PATH0_LOAD_CNT_MASK); 4237 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : 4238 BNX2X_PATH0_LOAD_CNT_SHIFT); 4239 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4240 4241 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val); 4242 4243 val = (val & mask) >> shift; 4244 4245 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n", 4246 engine, val); 4247 4248 return val != 0; 4249 } 4250 4251 static void _print_next_block(int idx, const char *blk) 4252 { 4253 pr_cont("%s%s", idx ? ", " : "", blk); 4254 } 4255 4256 static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num, 4257 bool print) 4258 { 4259 int i = 0; 4260 u32 cur_bit = 0; 4261 for (i = 0; sig; i++) { 4262 cur_bit = ((u32)0x1 << i); 4263 if (sig & cur_bit) { 4264 switch (cur_bit) { 4265 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: 4266 if (print) 4267 _print_next_block(par_num++, "BRB"); 4268 break; 4269 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: 4270 if (print) 4271 _print_next_block(par_num++, "PARSER"); 4272 break; 4273 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: 4274 if (print) 4275 _print_next_block(par_num++, "TSDM"); 4276 break; 4277 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: 4278 if (print) 4279 _print_next_block(par_num++, 4280 "SEARCHER"); 4281 break; 4282 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: 4283 if (print) 4284 _print_next_block(par_num++, "TCM"); 4285 break; 4286 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: 4287 if (print) 4288 _print_next_block(par_num++, "TSEMI"); 4289 break; 4290 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: 4291 if (print) 4292 _print_next_block(par_num++, "XPB"); 4293 break; 4294 } 4295 4296 /* Clear the bit */ 4297 sig &= ~cur_bit; 4298 } 4299 } 4300 4301 return par_num; 4302 } 4303 4304 static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num, 4305 bool *global, bool print) 4306 { 4307 int i = 0; 4308 u32 cur_bit = 0; 4309 for (i = 0; sig; i++) { 4310 cur_bit = ((u32)0x1 << i); 4311 if (sig & cur_bit) { 4312 switch (cur_bit) { 4313 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: 4314 if (print) 4315 _print_next_block(par_num++, "PBF"); 4316 break; 4317 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: 4318 if (print) 4319 _print_next_block(par_num++, "QM"); 4320 break; 4321 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: 4322 if (print) 4323 _print_next_block(par_num++, "TM"); 4324 break; 4325 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: 4326 if (print) 4327 _print_next_block(par_num++, "XSDM"); 4328 break; 4329 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: 4330 if (print) 4331 _print_next_block(par_num++, "XCM"); 4332 break; 4333 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: 4334 if (print) 4335 _print_next_block(par_num++, "XSEMI"); 4336 break; 4337 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: 4338 if (print) 4339 _print_next_block(par_num++, 4340 "DOORBELLQ"); 4341 break; 4342 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: 4343 if (print) 4344 _print_next_block(par_num++, "NIG"); 4345 break; 4346 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: 4347 if (print) 4348 _print_next_block(par_num++, 4349 "VAUX PCI CORE"); 4350 *global = true; 4351 break; 4352 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: 4353 if (print) 4354 _print_next_block(par_num++, "DEBUG"); 4355 break; 4356 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: 4357 if (print) 4358 _print_next_block(par_num++, "USDM"); 4359 break; 4360 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: 4361 if (print) 4362 _print_next_block(par_num++, "UCM"); 4363 break; 4364 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: 4365 if (print) 4366 _print_next_block(par_num++, "USEMI"); 4367 break; 4368 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: 4369 if (print) 4370 _print_next_block(par_num++, "UPB"); 4371 break; 4372 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: 4373 if (print) 4374 _print_next_block(par_num++, "CSDM"); 4375 break; 4376 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: 4377 if (print) 4378 _print_next_block(par_num++, "CCM"); 4379 break; 4380 } 4381 4382 /* Clear the bit */ 4383 sig &= ~cur_bit; 4384 } 4385 } 4386 4387 return par_num; 4388 } 4389 4390 static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num, 4391 bool print) 4392 { 4393 int i = 0; 4394 u32 cur_bit = 0; 4395 for (i = 0; sig; i++) { 4396 cur_bit = ((u32)0x1 << i); 4397 if (sig & cur_bit) { 4398 switch (cur_bit) { 4399 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: 4400 if (print) 4401 _print_next_block(par_num++, "CSEMI"); 4402 break; 4403 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: 4404 if (print) 4405 _print_next_block(par_num++, "PXP"); 4406 break; 4407 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: 4408 if (print) 4409 _print_next_block(par_num++, 4410 "PXPPCICLOCKCLIENT"); 4411 break; 4412 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: 4413 if (print) 4414 _print_next_block(par_num++, "CFC"); 4415 break; 4416 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: 4417 if (print) 4418 _print_next_block(par_num++, "CDU"); 4419 break; 4420 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: 4421 if (print) 4422 _print_next_block(par_num++, "DMAE"); 4423 break; 4424 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: 4425 if (print) 4426 _print_next_block(par_num++, "IGU"); 4427 break; 4428 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: 4429 if (print) 4430 _print_next_block(par_num++, "MISC"); 4431 break; 4432 } 4433 4434 /* Clear the bit */ 4435 sig &= ~cur_bit; 4436 } 4437 } 4438 4439 return par_num; 4440 } 4441 4442 static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, 4443 bool *global, bool print) 4444 { 4445 int i = 0; 4446 u32 cur_bit = 0; 4447 for (i = 0; sig; i++) { 4448 cur_bit = ((u32)0x1 << i); 4449 if (sig & cur_bit) { 4450 switch (cur_bit) { 4451 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: 4452 if (print) 4453 _print_next_block(par_num++, "MCP ROM"); 4454 *global = true; 4455 break; 4456 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: 4457 if (print) 4458 _print_next_block(par_num++, 4459 "MCP UMP RX"); 4460 *global = true; 4461 break; 4462 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: 4463 if (print) 4464 _print_next_block(par_num++, 4465 "MCP UMP TX"); 4466 *global = true; 4467 break; 4468 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: 4469 if (print) 4470 _print_next_block(par_num++, 4471 "MCP SCPAD"); 4472 *global = true; 4473 break; 4474 } 4475 4476 /* Clear the bit */ 4477 sig &= ~cur_bit; 4478 } 4479 } 4480 4481 return par_num; 4482 } 4483 4484 static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num, 4485 bool print) 4486 { 4487 int i = 0; 4488 u32 cur_bit = 0; 4489 for (i = 0; sig; i++) { 4490 cur_bit = ((u32)0x1 << i); 4491 if (sig & cur_bit) { 4492 switch (cur_bit) { 4493 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: 4494 if (print) 4495 _print_next_block(par_num++, "PGLUE_B"); 4496 break; 4497 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: 4498 if (print) 4499 _print_next_block(par_num++, "ATC"); 4500 break; 4501 } 4502 4503 /* Clear the bit */ 4504 sig &= ~cur_bit; 4505 } 4506 } 4507 4508 return par_num; 4509 } 4510 4511 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, 4512 u32 *sig) 4513 { 4514 if ((sig[0] & HW_PRTY_ASSERT_SET_0) || 4515 (sig[1] & HW_PRTY_ASSERT_SET_1) || 4516 (sig[2] & HW_PRTY_ASSERT_SET_2) || 4517 (sig[3] & HW_PRTY_ASSERT_SET_3) || 4518 (sig[4] & HW_PRTY_ASSERT_SET_4)) { 4519 int par_num = 0; 4520 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n" 4521 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n", 4522 sig[0] & HW_PRTY_ASSERT_SET_0, 4523 sig[1] & HW_PRTY_ASSERT_SET_1, 4524 sig[2] & HW_PRTY_ASSERT_SET_2, 4525 sig[3] & HW_PRTY_ASSERT_SET_3, 4526 sig[4] & HW_PRTY_ASSERT_SET_4); 4527 if (print) 4528 netdev_err(bp->dev, 4529 "Parity errors detected in blocks: "); 4530 par_num = bnx2x_check_blocks_with_parity0( 4531 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); 4532 par_num = bnx2x_check_blocks_with_parity1( 4533 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); 4534 par_num = bnx2x_check_blocks_with_parity2( 4535 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); 4536 par_num = bnx2x_check_blocks_with_parity3( 4537 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); 4538 par_num = bnx2x_check_blocks_with_parity4( 4539 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); 4540 4541 if (print) 4542 pr_cont("\n"); 4543 4544 return true; 4545 } else 4546 return false; 4547 } 4548 4549 /** 4550 * bnx2x_chk_parity_attn - checks for parity attentions. 4551 * 4552 * @bp: driver handle 4553 * @global: true if there was a global attention 4554 * @print: show parity attention in syslog 4555 */ 4556 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) 4557 { 4558 struct attn_route attn = { {0} }; 4559 int port = BP_PORT(bp); 4560 4561 attn.sig[0] = REG_RD(bp, 4562 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + 4563 port*4); 4564 attn.sig[1] = REG_RD(bp, 4565 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + 4566 port*4); 4567 attn.sig[2] = REG_RD(bp, 4568 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + 4569 port*4); 4570 attn.sig[3] = REG_RD(bp, 4571 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + 4572 port*4); 4573 4574 if (!CHIP_IS_E1x(bp)) 4575 attn.sig[4] = REG_RD(bp, 4576 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + 4577 port*4); 4578 4579 return bnx2x_parity_attn(bp, global, print, attn.sig); 4580 } 4581 4582 4583 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) 4584 { 4585 u32 val; 4586 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { 4587 4588 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); 4589 BNX2X_ERR("PGLUE hw attention 0x%x\n", val); 4590 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) 4591 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n"); 4592 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) 4593 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n"); 4594 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) 4595 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n"); 4596 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) 4597 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n"); 4598 if (val & 4599 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) 4600 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n"); 4601 if (val & 4602 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) 4603 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n"); 4604 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) 4605 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n"); 4606 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) 4607 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n"); 4608 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) 4609 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n"); 4610 } 4611 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { 4612 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); 4613 BNX2X_ERR("ATC hw attention 0x%x\n", val); 4614 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) 4615 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); 4616 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) 4617 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n"); 4618 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) 4619 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n"); 4620 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) 4621 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n"); 4622 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) 4623 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); 4624 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) 4625 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n"); 4626 } 4627 4628 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4629 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { 4630 BNX2X_ERR("FATAL parity attention set4 0x%x\n", 4631 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4632 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); 4633 } 4634 4635 } 4636 4637 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) 4638 { 4639 struct attn_route attn, *group_mask; 4640 int port = BP_PORT(bp); 4641 int index; 4642 u32 reg_addr; 4643 u32 val; 4644 u32 aeu_mask; 4645 bool global = false; 4646 4647 /* need to take HW lock because MCP or other port might also 4648 try to handle this event */ 4649 bnx2x_acquire_alr(bp); 4650 4651 if (bnx2x_chk_parity_attn(bp, &global, true)) { 4652 #ifndef BNX2X_STOP_ON_ERROR 4653 bp->recovery_state = BNX2X_RECOVERY_INIT; 4654 schedule_delayed_work(&bp->sp_rtnl_task, 0); 4655 /* Disable HW interrupts */ 4656 bnx2x_int_disable(bp); 4657 /* In case of parity errors don't handle attentions so that 4658 * other function would "see" parity errors. 4659 */ 4660 #else 4661 bnx2x_panic(); 4662 #endif 4663 bnx2x_release_alr(bp); 4664 return; 4665 } 4666 4667 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 4668 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 4669 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); 4670 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); 4671 if (!CHIP_IS_E1x(bp)) 4672 attn.sig[4] = 4673 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); 4674 else 4675 attn.sig[4] = 0; 4676 4677 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", 4678 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); 4679 4680 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 4681 if (deasserted & (1 << index)) { 4682 group_mask = &bp->attn_group[index]; 4683 4684 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n", 4685 index, 4686 group_mask->sig[0], group_mask->sig[1], 4687 group_mask->sig[2], group_mask->sig[3], 4688 group_mask->sig[4]); 4689 4690 bnx2x_attn_int_deasserted4(bp, 4691 attn.sig[4] & group_mask->sig[4]); 4692 bnx2x_attn_int_deasserted3(bp, 4693 attn.sig[3] & group_mask->sig[3]); 4694 bnx2x_attn_int_deasserted1(bp, 4695 attn.sig[1] & group_mask->sig[1]); 4696 bnx2x_attn_int_deasserted2(bp, 4697 attn.sig[2] & group_mask->sig[2]); 4698 bnx2x_attn_int_deasserted0(bp, 4699 attn.sig[0] & group_mask->sig[0]); 4700 } 4701 } 4702 4703 bnx2x_release_alr(bp); 4704 4705 if (bp->common.int_block == INT_BLOCK_HC) 4706 reg_addr = (HC_REG_COMMAND_REG + port*32 + 4707 COMMAND_REG_ATTN_BITS_CLR); 4708 else 4709 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); 4710 4711 val = ~deasserted; 4712 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, 4713 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 4714 REG_WR(bp, reg_addr, val); 4715 4716 if (~bp->attn_state & deasserted) 4717 BNX2X_ERR("IGU ERROR\n"); 4718 4719 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 4720 MISC_REG_AEU_MASK_ATTN_FUNC_0; 4721 4722 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4723 aeu_mask = REG_RD(bp, reg_addr); 4724 4725 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", 4726 aeu_mask, deasserted); 4727 aeu_mask |= (deasserted & 0x3ff); 4728 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 4729 4730 REG_WR(bp, reg_addr, aeu_mask); 4731 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4732 4733 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 4734 bp->attn_state &= ~deasserted; 4735 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 4736 } 4737 4738 static void bnx2x_attn_int(struct bnx2x *bp) 4739 { 4740 /* read local copy of bits */ 4741 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. 4742 attn_bits); 4743 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. 4744 attn_bits_ack); 4745 u32 attn_state = bp->attn_state; 4746 4747 /* look for changed bits */ 4748 u32 asserted = attn_bits & ~attn_ack & ~attn_state; 4749 u32 deasserted = ~attn_bits & attn_ack & attn_state; 4750 4751 DP(NETIF_MSG_HW, 4752 "attn_bits %x attn_ack %x asserted %x deasserted %x\n", 4753 attn_bits, attn_ack, asserted, deasserted); 4754 4755 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) 4756 BNX2X_ERR("BAD attention state\n"); 4757 4758 /* handle bits that were raised */ 4759 if (asserted) 4760 bnx2x_attn_int_asserted(bp, asserted); 4761 4762 if (deasserted) 4763 bnx2x_attn_int_deasserted(bp, deasserted); 4764 } 4765 4766 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 4767 u16 index, u8 op, u8 update) 4768 { 4769 u32 igu_addr = bp->igu_base_addr; 4770 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; 4771 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, 4772 igu_addr); 4773 } 4774 4775 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) 4776 { 4777 /* No memory barriers */ 4778 storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); 4779 mmiowb(); /* keep prod updates ordered */ 4780 } 4781 4782 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, 4783 union event_ring_elem *elem) 4784 { 4785 u8 err = elem->message.error; 4786 4787 if (!bp->cnic_eth_dev.starting_cid || 4788 (cid < bp->cnic_eth_dev.starting_cid && 4789 cid != bp->cnic_eth_dev.iscsi_l2_cid)) 4790 return 1; 4791 4792 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); 4793 4794 if (unlikely(err)) { 4795 4796 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", 4797 cid); 4798 bnx2x_panic_dump(bp, false); 4799 } 4800 bnx2x_cnic_cfc_comp(bp, cid, err); 4801 return 0; 4802 } 4803 4804 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp) 4805 { 4806 struct bnx2x_mcast_ramrod_params rparam; 4807 int rc; 4808 4809 memset(&rparam, 0, sizeof(rparam)); 4810 4811 rparam.mcast_obj = &bp->mcast_obj; 4812 4813 netif_addr_lock_bh(bp->dev); 4814 4815 /* Clear pending state for the last command */ 4816 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); 4817 4818 /* If there are pending mcast commands - send them */ 4819 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { 4820 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); 4821 if (rc < 0) 4822 BNX2X_ERR("Failed to send pending mcast commands: %d\n", 4823 rc); 4824 } 4825 4826 netif_addr_unlock_bh(bp->dev); 4827 } 4828 4829 static void bnx2x_handle_classification_eqe(struct bnx2x *bp, 4830 union event_ring_elem *elem) 4831 { 4832 unsigned long ramrod_flags = 0; 4833 int rc = 0; 4834 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; 4835 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 4836 4837 /* Always push next commands out, don't wait here */ 4838 __set_bit(RAMROD_CONT, &ramrod_flags); 4839 4840 switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo) 4841 >> BNX2X_SWCID_SHIFT) { 4842 case BNX2X_FILTER_MAC_PENDING: 4843 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n"); 4844 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp))) 4845 vlan_mac_obj = &bp->iscsi_l2_mac_obj; 4846 else 4847 vlan_mac_obj = &bp->sp_objs[cid].mac_obj; 4848 4849 break; 4850 case BNX2X_FILTER_MCAST_PENDING: 4851 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n"); 4852 /* This is only relevant for 57710 where multicast MACs are 4853 * configured as unicast MACs using the same ramrod. 4854 */ 4855 bnx2x_handle_mcast_eqe(bp); 4856 return; 4857 default: 4858 BNX2X_ERR("Unsupported classification command: %d\n", 4859 elem->message.data.eth_event.echo); 4860 return; 4861 } 4862 4863 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); 4864 4865 if (rc < 0) 4866 BNX2X_ERR("Failed to schedule new commands: %d\n", rc); 4867 else if (rc > 0) 4868 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); 4869 4870 } 4871 4872 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); 4873 4874 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) 4875 { 4876 netif_addr_lock_bh(bp->dev); 4877 4878 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 4879 4880 /* Send rx_mode command again if was requested */ 4881 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) 4882 bnx2x_set_storm_rx_mode(bp); 4883 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, 4884 &bp->sp_state)) 4885 bnx2x_set_iscsi_eth_rx_mode(bp, true); 4886 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 4887 &bp->sp_state)) 4888 bnx2x_set_iscsi_eth_rx_mode(bp, false); 4889 4890 netif_addr_unlock_bh(bp->dev); 4891 } 4892 4893 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp, 4894 union event_ring_elem *elem) 4895 { 4896 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) { 4897 DP(BNX2X_MSG_SP, 4898 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n", 4899 elem->message.data.vif_list_event.func_bit_map); 4900 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK, 4901 elem->message.data.vif_list_event.func_bit_map); 4902 } else if (elem->message.data.vif_list_event.echo == 4903 VIF_LIST_RULE_SET) { 4904 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n"); 4905 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0); 4906 } 4907 } 4908 4909 /* called with rtnl_lock */ 4910 static void bnx2x_after_function_update(struct bnx2x *bp) 4911 { 4912 int q, rc; 4913 struct bnx2x_fastpath *fp; 4914 struct bnx2x_queue_state_params queue_params = {NULL}; 4915 struct bnx2x_queue_update_params *q_update_params = 4916 &queue_params.params.update; 4917 4918 /* Send Q update command with afex vlan removal values for all Qs */ 4919 queue_params.cmd = BNX2X_Q_CMD_UPDATE; 4920 4921 /* set silent vlan removal values according to vlan mode */ 4922 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 4923 &q_update_params->update_flags); 4924 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, 4925 &q_update_params->update_flags); 4926 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); 4927 4928 /* in access mode mark mask and value are 0 to strip all vlans */ 4929 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) { 4930 q_update_params->silent_removal_value = 0; 4931 q_update_params->silent_removal_mask = 0; 4932 } else { 4933 q_update_params->silent_removal_value = 4934 (bp->afex_def_vlan_tag & VLAN_VID_MASK); 4935 q_update_params->silent_removal_mask = VLAN_VID_MASK; 4936 } 4937 4938 for_each_eth_queue(bp, q) { 4939 /* Set the appropriate Queue object */ 4940 fp = &bp->fp[q]; 4941 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 4942 4943 /* send the ramrod */ 4944 rc = bnx2x_queue_state_change(bp, &queue_params); 4945 if (rc < 0) 4946 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", 4947 q); 4948 } 4949 4950 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) { 4951 fp = &bp->fp[FCOE_IDX(bp)]; 4952 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 4953 4954 /* clear pending completion bit */ 4955 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); 4956 4957 /* mark latest Q bit */ 4958 smp_mb__before_clear_bit(); 4959 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); 4960 smp_mb__after_clear_bit(); 4961 4962 /* send Q update ramrod for FCoE Q */ 4963 rc = bnx2x_queue_state_change(bp, &queue_params); 4964 if (rc < 0) 4965 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", 4966 q); 4967 } else { 4968 /* If no FCoE ring - ACK MCP now */ 4969 bnx2x_link_report(bp); 4970 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); 4971 } 4972 } 4973 4974 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( 4975 struct bnx2x *bp, u32 cid) 4976 { 4977 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); 4978 4979 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp))) 4980 return &bnx2x_fcoe_sp_obj(bp, q_obj); 4981 else 4982 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj; 4983 } 4984 4985 static void bnx2x_eq_int(struct bnx2x *bp) 4986 { 4987 u16 hw_cons, sw_cons, sw_prod; 4988 union event_ring_elem *elem; 4989 u8 echo; 4990 u32 cid; 4991 u8 opcode; 4992 int rc, spqe_cnt = 0; 4993 struct bnx2x_queue_sp_obj *q_obj; 4994 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; 4995 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; 4996 4997 hw_cons = le16_to_cpu(*bp->eq_cons_sb); 4998 4999 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. 5000 * when we get the the next-page we nned to adjust so the loop 5001 * condition below will be met. The next element is the size of a 5002 * regular element and hence incrementing by 1 5003 */ 5004 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) 5005 hw_cons++; 5006 5007 /* This function may never run in parallel with itself for a 5008 * specific bp, thus there is no need in "paired" read memory 5009 * barrier here. 5010 */ 5011 sw_cons = bp->eq_cons; 5012 sw_prod = bp->eq_prod; 5013 5014 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", 5015 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); 5016 5017 for (; sw_cons != hw_cons; 5018 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { 5019 5020 elem = &bp->eq_ring[EQ_DESC(sw_cons)]; 5021 5022 rc = bnx2x_iov_eq_sp_event(bp, elem); 5023 if (!rc) { 5024 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n", 5025 rc); 5026 goto next_spqe; 5027 } 5028 5029 /* elem CID originates from FW; actually LE */ 5030 cid = SW_CID((__force __le32) 5031 elem->message.data.cfc_del_event.cid); 5032 opcode = elem->message.opcode; 5033 5034 /* handle eq element */ 5035 switch (opcode) { 5036 case EVENT_RING_OPCODE_VF_PF_CHANNEL: 5037 DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n"); 5038 bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event); 5039 continue; 5040 5041 case EVENT_RING_OPCODE_STAT_QUERY: 5042 DP(BNX2X_MSG_SP | BNX2X_MSG_STATS, 5043 "got statistics comp event %d\n", 5044 bp->stats_comp++); 5045 /* nothing to do with stats comp */ 5046 goto next_spqe; 5047 5048 case EVENT_RING_OPCODE_CFC_DEL: 5049 /* handle according to cid range */ 5050 /* 5051 * we may want to verify here that the bp state is 5052 * HALTING 5053 */ 5054 DP(BNX2X_MSG_SP, 5055 "got delete ramrod for MULTI[%d]\n", cid); 5056 5057 if (CNIC_LOADED(bp) && 5058 !bnx2x_cnic_handle_cfc_del(bp, cid, elem)) 5059 goto next_spqe; 5060 5061 q_obj = bnx2x_cid_to_q_obj(bp, cid); 5062 5063 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) 5064 break; 5065 5066 5067 5068 goto next_spqe; 5069 5070 case EVENT_RING_OPCODE_STOP_TRAFFIC: 5071 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n"); 5072 if (f_obj->complete_cmd(bp, f_obj, 5073 BNX2X_F_CMD_TX_STOP)) 5074 break; 5075 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); 5076 goto next_spqe; 5077 5078 case EVENT_RING_OPCODE_START_TRAFFIC: 5079 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n"); 5080 if (f_obj->complete_cmd(bp, f_obj, 5081 BNX2X_F_CMD_TX_START)) 5082 break; 5083 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); 5084 goto next_spqe; 5085 5086 case EVENT_RING_OPCODE_FUNCTION_UPDATE: 5087 echo = elem->message.data.function_update_event.echo; 5088 if (echo == SWITCH_UPDATE) { 5089 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, 5090 "got FUNC_SWITCH_UPDATE ramrod\n"); 5091 if (f_obj->complete_cmd( 5092 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE)) 5093 break; 5094 5095 } else { 5096 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP, 5097 "AFEX: ramrod completed FUNCTION_UPDATE\n"); 5098 f_obj->complete_cmd(bp, f_obj, 5099 BNX2X_F_CMD_AFEX_UPDATE); 5100 5101 /* We will perform the Queues update from 5102 * sp_rtnl task as all Queue SP operations 5103 * should run under rtnl_lock. 5104 */ 5105 smp_mb__before_clear_bit(); 5106 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, 5107 &bp->sp_rtnl_state); 5108 smp_mb__after_clear_bit(); 5109 5110 schedule_delayed_work(&bp->sp_rtnl_task, 0); 5111 } 5112 5113 goto next_spqe; 5114 5115 case EVENT_RING_OPCODE_AFEX_VIF_LISTS: 5116 f_obj->complete_cmd(bp, f_obj, 5117 BNX2X_F_CMD_AFEX_VIFLISTS); 5118 bnx2x_after_afex_vif_lists(bp, elem); 5119 goto next_spqe; 5120 case EVENT_RING_OPCODE_FUNCTION_START: 5121 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, 5122 "got FUNC_START ramrod\n"); 5123 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) 5124 break; 5125 5126 goto next_spqe; 5127 5128 case EVENT_RING_OPCODE_FUNCTION_STOP: 5129 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, 5130 "got FUNC_STOP ramrod\n"); 5131 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) 5132 break; 5133 5134 goto next_spqe; 5135 } 5136 5137 switch (opcode | bp->state) { 5138 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 5139 BNX2X_STATE_OPEN): 5140 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 5141 BNX2X_STATE_OPENING_WAIT4_PORT): 5142 cid = elem->message.data.eth_event.echo & 5143 BNX2X_SWCID_MASK; 5144 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", 5145 cid); 5146 rss_raw->clear_pending(rss_raw); 5147 break; 5148 5149 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): 5150 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): 5151 case (EVENT_RING_OPCODE_SET_MAC | 5152 BNX2X_STATE_CLOSING_WAIT4_HALT): 5153 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 5154 BNX2X_STATE_OPEN): 5155 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 5156 BNX2X_STATE_DIAG): 5157 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 5158 BNX2X_STATE_CLOSING_WAIT4_HALT): 5159 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); 5160 bnx2x_handle_classification_eqe(bp, elem); 5161 break; 5162 5163 case (EVENT_RING_OPCODE_MULTICAST_RULES | 5164 BNX2X_STATE_OPEN): 5165 case (EVENT_RING_OPCODE_MULTICAST_RULES | 5166 BNX2X_STATE_DIAG): 5167 case (EVENT_RING_OPCODE_MULTICAST_RULES | 5168 BNX2X_STATE_CLOSING_WAIT4_HALT): 5169 DP(BNX2X_MSG_SP, "got mcast ramrod\n"); 5170 bnx2x_handle_mcast_eqe(bp); 5171 break; 5172 5173 case (EVENT_RING_OPCODE_FILTERS_RULES | 5174 BNX2X_STATE_OPEN): 5175 case (EVENT_RING_OPCODE_FILTERS_RULES | 5176 BNX2X_STATE_DIAG): 5177 case (EVENT_RING_OPCODE_FILTERS_RULES | 5178 BNX2X_STATE_CLOSING_WAIT4_HALT): 5179 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); 5180 bnx2x_handle_rx_mode_eqe(bp); 5181 break; 5182 default: 5183 /* unknown event log error and continue */ 5184 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", 5185 elem->message.opcode, bp->state); 5186 } 5187 next_spqe: 5188 spqe_cnt++; 5189 } /* for */ 5190 5191 smp_mb__before_atomic_inc(); 5192 atomic_add(spqe_cnt, &bp->eq_spq_left); 5193 5194 bp->eq_cons = sw_cons; 5195 bp->eq_prod = sw_prod; 5196 /* Make sure that above mem writes were issued towards the memory */ 5197 smp_wmb(); 5198 5199 /* update producer */ 5200 bnx2x_update_eq_prod(bp, bp->eq_prod); 5201 } 5202 5203 static void bnx2x_sp_task(struct work_struct *work) 5204 { 5205 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); 5206 5207 DP(BNX2X_MSG_SP, "sp task invoked\n"); 5208 5209 /* make sure the atomic interupt_occurred has been written */ 5210 smp_rmb(); 5211 if (atomic_read(&bp->interrupt_occurred)) { 5212 5213 /* what work needs to be performed? */ 5214 u16 status = bnx2x_update_dsb_idx(bp); 5215 5216 DP(BNX2X_MSG_SP, "status %x\n", status); 5217 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n"); 5218 atomic_set(&bp->interrupt_occurred, 0); 5219 5220 /* HW attentions */ 5221 if (status & BNX2X_DEF_SB_ATT_IDX) { 5222 bnx2x_attn_int(bp); 5223 status &= ~BNX2X_DEF_SB_ATT_IDX; 5224 } 5225 5226 /* SP events: STAT_QUERY and others */ 5227 if (status & BNX2X_DEF_SB_IDX) { 5228 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 5229 5230 if (FCOE_INIT(bp) && 5231 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { 5232 /* Prevent local bottom-halves from running as 5233 * we are going to change the local NAPI list. 5234 */ 5235 local_bh_disable(); 5236 napi_schedule(&bnx2x_fcoe(bp, napi)); 5237 local_bh_enable(); 5238 } 5239 5240 /* Handle EQ completions */ 5241 bnx2x_eq_int(bp); 5242 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 5243 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); 5244 5245 status &= ~BNX2X_DEF_SB_IDX; 5246 } 5247 5248 /* if status is non zero then perhaps something went wrong */ 5249 if (unlikely(status)) 5250 DP(BNX2X_MSG_SP, 5251 "got an unknown interrupt! (status 0x%x)\n", status); 5252 5253 /* ack status block only if something was actually handled */ 5254 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, 5255 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); 5256 5257 } 5258 5259 /* must be called after the EQ processing (since eq leads to sriov 5260 * ramrod completion flows). 5261 * This flow may have been scheduled by the arrival of a ramrod 5262 * completion, or by the sriov code rescheduling itself. 5263 */ 5264 bnx2x_iov_sp_task(bp); 5265 5266 /* afex - poll to check if VIFSET_ACK should be sent to MFW */ 5267 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, 5268 &bp->sp_state)) { 5269 bnx2x_link_report(bp); 5270 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); 5271 } 5272 } 5273 5274 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) 5275 { 5276 struct net_device *dev = dev_instance; 5277 struct bnx2x *bp = netdev_priv(dev); 5278 5279 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, 5280 IGU_INT_DISABLE, 0); 5281 5282 #ifdef BNX2X_STOP_ON_ERROR 5283 if (unlikely(bp->panic)) 5284 return IRQ_HANDLED; 5285 #endif 5286 5287 if (CNIC_LOADED(bp)) { 5288 struct cnic_ops *c_ops; 5289 5290 rcu_read_lock(); 5291 c_ops = rcu_dereference(bp->cnic_ops); 5292 if (c_ops) 5293 c_ops->cnic_handler(bp->cnic_data, NULL); 5294 rcu_read_unlock(); 5295 } 5296 5297 /* schedule sp task to perform default status block work, ack 5298 * attentions and enable interrupts. 5299 */ 5300 bnx2x_schedule_sp_task(bp); 5301 5302 return IRQ_HANDLED; 5303 } 5304 5305 /* end of slow path */ 5306 5307 5308 void bnx2x_drv_pulse(struct bnx2x *bp) 5309 { 5310 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, 5311 bp->fw_drv_pulse_wr_seq); 5312 } 5313 5314 static void bnx2x_timer(unsigned long data) 5315 { 5316 struct bnx2x *bp = (struct bnx2x *) data; 5317 5318 if (!netif_running(bp->dev)) 5319 return; 5320 5321 if (IS_PF(bp) && 5322 !BP_NOMCP(bp)) { 5323 int mb_idx = BP_FW_MB_IDX(bp); 5324 u32 drv_pulse; 5325 u32 mcp_pulse; 5326 5327 ++bp->fw_drv_pulse_wr_seq; 5328 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; 5329 /* TBD - add SYSTEM_TIME */ 5330 drv_pulse = bp->fw_drv_pulse_wr_seq; 5331 bnx2x_drv_pulse(bp); 5332 5333 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & 5334 MCP_PULSE_SEQ_MASK); 5335 /* The delta between driver pulse and mcp response 5336 * should be 1 (before mcp response) or 0 (after mcp response) 5337 */ 5338 if ((drv_pulse != mcp_pulse) && 5339 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { 5340 /* someone lost a heartbeat... */ 5341 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n", 5342 drv_pulse, mcp_pulse); 5343 } 5344 } 5345 5346 if (bp->state == BNX2X_STATE_OPEN) 5347 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); 5348 5349 /* sample pf vf bulletin board for new posts from pf */ 5350 if (IS_VF(bp)) 5351 bnx2x_sample_bulletin(bp); 5352 5353 mod_timer(&bp->timer, jiffies + bp->current_interval); 5354 } 5355 5356 /* end of Statistics */ 5357 5358 /* nic init */ 5359 5360 /* 5361 * nic init service functions 5362 */ 5363 5364 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) 5365 { 5366 u32 i; 5367 if (!(len%4) && !(addr%4)) 5368 for (i = 0; i < len; i += 4) 5369 REG_WR(bp, addr + i, fill); 5370 else 5371 for (i = 0; i < len; i++) 5372 REG_WR8(bp, addr + i, fill); 5373 5374 } 5375 5376 /* helper: writes FP SP data to FW - data_size in dwords */ 5377 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp, 5378 int fw_sb_id, 5379 u32 *sb_data_p, 5380 u32 data_size) 5381 { 5382 int index; 5383 for (index = 0; index < data_size; index++) 5384 REG_WR(bp, BAR_CSTRORM_INTMEM + 5385 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + 5386 sizeof(u32)*index, 5387 *(sb_data_p + index)); 5388 } 5389 5390 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) 5391 { 5392 u32 *sb_data_p; 5393 u32 data_size = 0; 5394 struct hc_status_block_data_e2 sb_data_e2; 5395 struct hc_status_block_data_e1x sb_data_e1x; 5396 5397 /* disable the function first */ 5398 if (!CHIP_IS_E1x(bp)) { 5399 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 5400 sb_data_e2.common.state = SB_DISABLED; 5401 sb_data_e2.common.p_func.vf_valid = false; 5402 sb_data_p = (u32 *)&sb_data_e2; 5403 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 5404 } else { 5405 memset(&sb_data_e1x, 0, 5406 sizeof(struct hc_status_block_data_e1x)); 5407 sb_data_e1x.common.state = SB_DISABLED; 5408 sb_data_e1x.common.p_func.vf_valid = false; 5409 sb_data_p = (u32 *)&sb_data_e1x; 5410 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 5411 } 5412 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 5413 5414 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 5415 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, 5416 CSTORM_STATUS_BLOCK_SIZE); 5417 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 5418 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, 5419 CSTORM_SYNC_BLOCK_SIZE); 5420 } 5421 5422 /* helper: writes SP SB data to FW */ 5423 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp, 5424 struct hc_sp_status_block_data *sp_sb_data) 5425 { 5426 int func = BP_FUNC(bp); 5427 int i; 5428 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 5429 REG_WR(bp, BAR_CSTRORM_INTMEM + 5430 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 5431 i*sizeof(u32), 5432 *((u32 *)sp_sb_data + i)); 5433 } 5434 5435 static void bnx2x_zero_sp_sb(struct bnx2x *bp) 5436 { 5437 int func = BP_FUNC(bp); 5438 struct hc_sp_status_block_data sp_sb_data; 5439 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 5440 5441 sp_sb_data.state = SB_DISABLED; 5442 sp_sb_data.p_func.vf_valid = false; 5443 5444 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 5445 5446 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 5447 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, 5448 CSTORM_SP_STATUS_BLOCK_SIZE); 5449 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 5450 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, 5451 CSTORM_SP_SYNC_BLOCK_SIZE); 5452 5453 } 5454 5455 5456 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, 5457 int igu_sb_id, int igu_seg_id) 5458 { 5459 hc_sm->igu_sb_id = igu_sb_id; 5460 hc_sm->igu_seg_id = igu_seg_id; 5461 hc_sm->timer_value = 0xFF; 5462 hc_sm->time_to_expire = 0xFFFFFFFF; 5463 } 5464 5465 5466 /* allocates state machine ids. */ 5467 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) 5468 { 5469 /* zero out state machine indices */ 5470 /* rx indices */ 5471 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 5472 5473 /* tx indices */ 5474 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 5475 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; 5476 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; 5477 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; 5478 5479 /* map indices */ 5480 /* rx indices */ 5481 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= 5482 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5483 5484 /* tx indices */ 5485 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= 5486 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5487 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= 5488 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5489 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= 5490 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5491 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= 5492 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5493 } 5494 5495 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 5496 u8 vf_valid, int fw_sb_id, int igu_sb_id) 5497 { 5498 int igu_seg_id; 5499 5500 struct hc_status_block_data_e2 sb_data_e2; 5501 struct hc_status_block_data_e1x sb_data_e1x; 5502 struct hc_status_block_sm *hc_sm_p; 5503 int data_size; 5504 u32 *sb_data_p; 5505 5506 if (CHIP_INT_MODE_IS_BC(bp)) 5507 igu_seg_id = HC_SEG_ACCESS_NORM; 5508 else 5509 igu_seg_id = IGU_SEG_ACCESS_NORM; 5510 5511 bnx2x_zero_fp_sb(bp, fw_sb_id); 5512 5513 if (!CHIP_IS_E1x(bp)) { 5514 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 5515 sb_data_e2.common.state = SB_ENABLED; 5516 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); 5517 sb_data_e2.common.p_func.vf_id = vfid; 5518 sb_data_e2.common.p_func.vf_valid = vf_valid; 5519 sb_data_e2.common.p_func.vnic_id = BP_VN(bp); 5520 sb_data_e2.common.same_igu_sb_1b = true; 5521 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); 5522 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); 5523 hc_sm_p = sb_data_e2.common.state_machine; 5524 sb_data_p = (u32 *)&sb_data_e2; 5525 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 5526 bnx2x_map_sb_state_machines(sb_data_e2.index_data); 5527 } else { 5528 memset(&sb_data_e1x, 0, 5529 sizeof(struct hc_status_block_data_e1x)); 5530 sb_data_e1x.common.state = SB_ENABLED; 5531 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); 5532 sb_data_e1x.common.p_func.vf_id = 0xff; 5533 sb_data_e1x.common.p_func.vf_valid = false; 5534 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); 5535 sb_data_e1x.common.same_igu_sb_1b = true; 5536 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); 5537 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); 5538 hc_sm_p = sb_data_e1x.common.state_machine; 5539 sb_data_p = (u32 *)&sb_data_e1x; 5540 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 5541 bnx2x_map_sb_state_machines(sb_data_e1x.index_data); 5542 } 5543 5544 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], 5545 igu_sb_id, igu_seg_id); 5546 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], 5547 igu_sb_id, igu_seg_id); 5548 5549 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id); 5550 5551 /* write indices to HW - PCI guarantees endianity of regpairs */ 5552 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 5553 } 5554 5555 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, 5556 u16 tx_usec, u16 rx_usec) 5557 { 5558 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, 5559 false, rx_usec); 5560 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5561 HC_INDEX_ETH_TX_CQ_CONS_COS0, false, 5562 tx_usec); 5563 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5564 HC_INDEX_ETH_TX_CQ_CONS_COS1, false, 5565 tx_usec); 5566 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5567 HC_INDEX_ETH_TX_CQ_CONS_COS2, false, 5568 tx_usec); 5569 } 5570 5571 static void bnx2x_init_def_sb(struct bnx2x *bp) 5572 { 5573 struct host_sp_status_block *def_sb = bp->def_status_blk; 5574 dma_addr_t mapping = bp->def_status_blk_mapping; 5575 int igu_sp_sb_index; 5576 int igu_seg_id; 5577 int port = BP_PORT(bp); 5578 int func = BP_FUNC(bp); 5579 int reg_offset, reg_offset_en5; 5580 u64 section; 5581 int index; 5582 struct hc_sp_status_block_data sp_sb_data; 5583 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 5584 5585 if (CHIP_INT_MODE_IS_BC(bp)) { 5586 igu_sp_sb_index = DEF_SB_IGU_ID; 5587 igu_seg_id = HC_SEG_ACCESS_DEF; 5588 } else { 5589 igu_sp_sb_index = bp->igu_dsb_id; 5590 igu_seg_id = IGU_SEG_ACCESS_DEF; 5591 } 5592 5593 /* ATTN */ 5594 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 5595 atten_status_block); 5596 def_sb->atten_status_block.status_block_id = igu_sp_sb_index; 5597 5598 bp->attn_state = 0; 5599 5600 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 5601 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 5602 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : 5603 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); 5604 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 5605 int sindex; 5606 /* take care of sig[0]..sig[4] */ 5607 for (sindex = 0; sindex < 4; sindex++) 5608 bp->attn_group[index].sig[sindex] = 5609 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); 5610 5611 if (!CHIP_IS_E1x(bp)) 5612 /* 5613 * enable5 is separate from the rest of the registers, 5614 * and therefore the address skip is 4 5615 * and not 16 between the different groups 5616 */ 5617 bp->attn_group[index].sig[4] = REG_RD(bp, 5618 reg_offset_en5 + 0x4*index); 5619 else 5620 bp->attn_group[index].sig[4] = 0; 5621 } 5622 5623 if (bp->common.int_block == INT_BLOCK_HC) { 5624 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : 5625 HC_REG_ATTN_MSG0_ADDR_L); 5626 5627 REG_WR(bp, reg_offset, U64_LO(section)); 5628 REG_WR(bp, reg_offset + 4, U64_HI(section)); 5629 } else if (!CHIP_IS_E1x(bp)) { 5630 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); 5631 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); 5632 } 5633 5634 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 5635 sp_sb); 5636 5637 bnx2x_zero_sp_sb(bp); 5638 5639 /* PCI guarantees endianity of regpairs */ 5640 sp_sb_data.state = SB_ENABLED; 5641 sp_sb_data.host_sb_addr.lo = U64_LO(section); 5642 sp_sb_data.host_sb_addr.hi = U64_HI(section); 5643 sp_sb_data.igu_sb_id = igu_sp_sb_index; 5644 sp_sb_data.igu_seg_id = igu_seg_id; 5645 sp_sb_data.p_func.pf_id = func; 5646 sp_sb_data.p_func.vnic_id = BP_VN(bp); 5647 sp_sb_data.p_func.vf_id = 0xff; 5648 5649 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 5650 5651 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); 5652 } 5653 5654 void bnx2x_update_coalesce(struct bnx2x *bp) 5655 { 5656 int i; 5657 5658 for_each_eth_queue(bp, i) 5659 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, 5660 bp->tx_ticks, bp->rx_ticks); 5661 } 5662 5663 static void bnx2x_init_sp_ring(struct bnx2x *bp) 5664 { 5665 spin_lock_init(&bp->spq_lock); 5666 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); 5667 5668 bp->spq_prod_idx = 0; 5669 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; 5670 bp->spq_prod_bd = bp->spq; 5671 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; 5672 } 5673 5674 static void bnx2x_init_eq_ring(struct bnx2x *bp) 5675 { 5676 int i; 5677 for (i = 1; i <= NUM_EQ_PAGES; i++) { 5678 union event_ring_elem *elem = 5679 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; 5680 5681 elem->next_page.addr.hi = 5682 cpu_to_le32(U64_HI(bp->eq_mapping + 5683 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); 5684 elem->next_page.addr.lo = 5685 cpu_to_le32(U64_LO(bp->eq_mapping + 5686 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); 5687 } 5688 bp->eq_cons = 0; 5689 bp->eq_prod = NUM_EQ_DESC; 5690 bp->eq_cons_sb = BNX2X_EQ_INDEX; 5691 /* we want a warning message before it gets rought... */ 5692 atomic_set(&bp->eq_spq_left, 5693 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); 5694 } 5695 5696 /* called with netif_addr_lock_bh() */ 5697 int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 5698 unsigned long rx_mode_flags, 5699 unsigned long rx_accept_flags, 5700 unsigned long tx_accept_flags, 5701 unsigned long ramrod_flags) 5702 { 5703 struct bnx2x_rx_mode_ramrod_params ramrod_param; 5704 int rc; 5705 5706 memset(&ramrod_param, 0, sizeof(ramrod_param)); 5707 5708 /* Prepare ramrod parameters */ 5709 ramrod_param.cid = 0; 5710 ramrod_param.cl_id = cl_id; 5711 ramrod_param.rx_mode_obj = &bp->rx_mode_obj; 5712 ramrod_param.func_id = BP_FUNC(bp); 5713 5714 ramrod_param.pstate = &bp->sp_state; 5715 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; 5716 5717 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); 5718 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); 5719 5720 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 5721 5722 ramrod_param.ramrod_flags = ramrod_flags; 5723 ramrod_param.rx_mode_flags = rx_mode_flags; 5724 5725 ramrod_param.rx_accept_flags = rx_accept_flags; 5726 ramrod_param.tx_accept_flags = tx_accept_flags; 5727 5728 rc = bnx2x_config_rx_mode(bp, &ramrod_param); 5729 if (rc < 0) { 5730 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); 5731 return rc; 5732 } 5733 5734 return 0; 5735 } 5736 5737 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode, 5738 unsigned long *rx_accept_flags, 5739 unsigned long *tx_accept_flags) 5740 { 5741 /* Clear the flags first */ 5742 *rx_accept_flags = 0; 5743 *tx_accept_flags = 0; 5744 5745 switch (rx_mode) { 5746 case BNX2X_RX_MODE_NONE: 5747 /* 5748 * 'drop all' supersedes any accept flags that may have been 5749 * passed to the function. 5750 */ 5751 break; 5752 case BNX2X_RX_MODE_NORMAL: 5753 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); 5754 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags); 5755 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); 5756 5757 /* internal switching mode */ 5758 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); 5759 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags); 5760 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); 5761 5762 break; 5763 case BNX2X_RX_MODE_ALLMULTI: 5764 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); 5765 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags); 5766 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); 5767 5768 /* internal switching mode */ 5769 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); 5770 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags); 5771 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); 5772 5773 break; 5774 case BNX2X_RX_MODE_PROMISC: 5775 /* According to deffinition of SI mode, iface in promisc mode 5776 * should receive matched and unmatched (in resolution of port) 5777 * unicast packets. 5778 */ 5779 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags); 5780 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); 5781 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags); 5782 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); 5783 5784 /* internal switching mode */ 5785 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags); 5786 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); 5787 5788 if (IS_MF_SI(bp)) 5789 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags); 5790 else 5791 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); 5792 5793 break; 5794 default: 5795 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode); 5796 return -EINVAL; 5797 } 5798 5799 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */ 5800 if (bp->rx_mode != BNX2X_RX_MODE_NONE) { 5801 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags); 5802 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags); 5803 } 5804 5805 return 0; 5806 } 5807 5808 /* called with netif_addr_lock_bh() */ 5809 int bnx2x_set_storm_rx_mode(struct bnx2x *bp) 5810 { 5811 unsigned long rx_mode_flags = 0, ramrod_flags = 0; 5812 unsigned long rx_accept_flags = 0, tx_accept_flags = 0; 5813 int rc; 5814 5815 if (!NO_FCOE(bp)) 5816 /* Configure rx_mode of FCoE Queue */ 5817 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); 5818 5819 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags, 5820 &tx_accept_flags); 5821 if (rc) 5822 return rc; 5823 5824 __set_bit(RAMROD_RX, &ramrod_flags); 5825 __set_bit(RAMROD_TX, &ramrod_flags); 5826 5827 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, 5828 rx_accept_flags, tx_accept_flags, 5829 ramrod_flags); 5830 } 5831 5832 static void bnx2x_init_internal_common(struct bnx2x *bp) 5833 { 5834 int i; 5835 5836 if (IS_MF_SI(bp)) 5837 /* 5838 * In switch independent mode, the TSTORM needs to accept 5839 * packets that failed classification, since approximate match 5840 * mac addresses aren't written to NIG LLH 5841 */ 5842 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5843 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); 5844 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ 5845 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5846 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); 5847 5848 /* Zero this manually as its initialization is 5849 currently missing in the initTool */ 5850 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) 5851 REG_WR(bp, BAR_USTRORM_INTMEM + 5852 USTORM_AGG_DATA_OFFSET + i * 4, 0); 5853 if (!CHIP_IS_E1x(bp)) { 5854 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, 5855 CHIP_INT_MODE_IS_BC(bp) ? 5856 HC_IGU_BC_MODE : HC_IGU_NBC_MODE); 5857 } 5858 } 5859 5860 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) 5861 { 5862 switch (load_code) { 5863 case FW_MSG_CODE_DRV_LOAD_COMMON: 5864 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: 5865 bnx2x_init_internal_common(bp); 5866 /* no break */ 5867 5868 case FW_MSG_CODE_DRV_LOAD_PORT: 5869 /* nothing to do */ 5870 /* no break */ 5871 5872 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 5873 /* internal memory per function is 5874 initialized inside bnx2x_pf_init */ 5875 break; 5876 5877 default: 5878 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); 5879 break; 5880 } 5881 } 5882 5883 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) 5884 { 5885 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp); 5886 } 5887 5888 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) 5889 { 5890 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp); 5891 } 5892 5893 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) 5894 { 5895 if (CHIP_IS_E1x(fp->bp)) 5896 return BP_L_ID(fp->bp) + fp->index; 5897 else /* We want Client ID to be the same as IGU SB ID for 57712 */ 5898 return bnx2x_fp_igu_sb_id(fp); 5899 } 5900 5901 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) 5902 { 5903 struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; 5904 u8 cos; 5905 unsigned long q_type = 0; 5906 u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; 5907 fp->rx_queue = fp_idx; 5908 fp->cid = fp_idx; 5909 fp->cl_id = bnx2x_fp_cl_id(fp); 5910 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); 5911 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); 5912 /* qZone id equals to FW (per path) client id */ 5913 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); 5914 5915 /* init shortcut */ 5916 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); 5917 5918 /* Setup SB indicies */ 5919 fp->rx_cons_sb = BNX2X_RX_SB_INDEX; 5920 5921 /* Configure Queue State object */ 5922 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 5923 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 5924 5925 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); 5926 5927 /* init tx data */ 5928 for_each_cos_in_tx_queue(fp, cos) { 5929 bnx2x_init_txdata(bp, fp->txdata_ptr[cos], 5930 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp), 5931 FP_COS_TO_TXQ(fp, cos, bp), 5932 BNX2X_TX_SB_INDEX_BASE + cos, fp); 5933 cids[cos] = fp->txdata_ptr[cos]->cid; 5934 } 5935 5936 /* nothing more for vf to do here */ 5937 if (IS_VF(bp)) 5938 return; 5939 5940 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, 5941 fp->fw_sb_id, fp->igu_sb_id); 5942 bnx2x_update_fpsb_idx(fp); 5943 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids, 5944 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 5945 bnx2x_sp_mapping(bp, q_rdata), q_type); 5946 5947 /** 5948 * Configure classification DBs: Always enable Tx switching 5949 */ 5950 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); 5951 5952 DP(NETIF_MSG_IFUP, 5953 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", 5954 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 5955 fp->igu_sb_id); 5956 } 5957 5958 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata) 5959 { 5960 int i; 5961 5962 for (i = 1; i <= NUM_TX_RINGS; i++) { 5963 struct eth_tx_next_bd *tx_next_bd = 5964 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd; 5965 5966 tx_next_bd->addr_hi = 5967 cpu_to_le32(U64_HI(txdata->tx_desc_mapping + 5968 BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); 5969 tx_next_bd->addr_lo = 5970 cpu_to_le32(U64_LO(txdata->tx_desc_mapping + 5971 BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); 5972 } 5973 5974 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1); 5975 txdata->tx_db.data.zero_fill1 = 0; 5976 txdata->tx_db.data.prod = 0; 5977 5978 txdata->tx_pkt_prod = 0; 5979 txdata->tx_pkt_cons = 0; 5980 txdata->tx_bd_prod = 0; 5981 txdata->tx_bd_cons = 0; 5982 txdata->tx_pkt = 0; 5983 } 5984 5985 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp) 5986 { 5987 int i; 5988 5989 for_each_tx_queue_cnic(bp, i) 5990 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]); 5991 } 5992 static void bnx2x_init_tx_rings(struct bnx2x *bp) 5993 { 5994 int i; 5995 u8 cos; 5996 5997 for_each_eth_queue(bp, i) 5998 for_each_cos_in_tx_queue(&bp->fp[i], cos) 5999 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]); 6000 } 6001 6002 void bnx2x_nic_init_cnic(struct bnx2x *bp) 6003 { 6004 if (!NO_FCOE(bp)) 6005 bnx2x_init_fcoe_fp(bp); 6006 6007 bnx2x_init_sb(bp, bp->cnic_sb_mapping, 6008 BNX2X_VF_ID_INVALID, false, 6009 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); 6010 6011 /* ensure status block indices were read */ 6012 rmb(); 6013 bnx2x_init_rx_rings_cnic(bp); 6014 bnx2x_init_tx_rings_cnic(bp); 6015 6016 /* flush all */ 6017 mb(); 6018 mmiowb(); 6019 } 6020 6021 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) 6022 { 6023 int i; 6024 6025 for_each_eth_queue(bp, i) 6026 bnx2x_init_eth_fp(bp, i); 6027 6028 /* ensure status block indices were read */ 6029 rmb(); 6030 bnx2x_init_rx_rings(bp); 6031 bnx2x_init_tx_rings(bp); 6032 6033 if (IS_VF(bp)) 6034 return; 6035 6036 /* Initialize MOD_ABS interrupts */ 6037 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, 6038 bp->common.shmem_base, bp->common.shmem2_base, 6039 BP_PORT(bp)); 6040 6041 bnx2x_init_def_sb(bp); 6042 bnx2x_update_dsb_idx(bp); 6043 bnx2x_init_sp_ring(bp); 6044 bnx2x_init_eq_ring(bp); 6045 bnx2x_init_internal(bp, load_code); 6046 bnx2x_pf_init(bp); 6047 bnx2x_stats_init(bp); 6048 6049 /* flush all before enabling interrupts */ 6050 mb(); 6051 mmiowb(); 6052 6053 bnx2x_int_enable(bp); 6054 6055 /* Check for SPIO5 */ 6056 bnx2x_attn_int_deasserted0(bp, 6057 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & 6058 AEU_INPUTS_ATTN_BITS_SPIO5); 6059 } 6060 6061 /* end of nic init */ 6062 6063 /* 6064 * gzip service functions 6065 */ 6066 6067 static int bnx2x_gunzip_init(struct bnx2x *bp) 6068 { 6069 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, 6070 &bp->gunzip_mapping, GFP_KERNEL); 6071 if (bp->gunzip_buf == NULL) 6072 goto gunzip_nomem1; 6073 6074 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); 6075 if (bp->strm == NULL) 6076 goto gunzip_nomem2; 6077 6078 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); 6079 if (bp->strm->workspace == NULL) 6080 goto gunzip_nomem3; 6081 6082 return 0; 6083 6084 gunzip_nomem3: 6085 kfree(bp->strm); 6086 bp->strm = NULL; 6087 6088 gunzip_nomem2: 6089 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 6090 bp->gunzip_mapping); 6091 bp->gunzip_buf = NULL; 6092 6093 gunzip_nomem1: 6094 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n"); 6095 return -ENOMEM; 6096 } 6097 6098 static void bnx2x_gunzip_end(struct bnx2x *bp) 6099 { 6100 if (bp->strm) { 6101 vfree(bp->strm->workspace); 6102 kfree(bp->strm); 6103 bp->strm = NULL; 6104 } 6105 6106 if (bp->gunzip_buf) { 6107 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 6108 bp->gunzip_mapping); 6109 bp->gunzip_buf = NULL; 6110 } 6111 } 6112 6113 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) 6114 { 6115 int n, rc; 6116 6117 /* check gzip header */ 6118 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { 6119 BNX2X_ERR("Bad gzip header\n"); 6120 return -EINVAL; 6121 } 6122 6123 n = 10; 6124 6125 #define FNAME 0x8 6126 6127 if (zbuf[3] & FNAME) 6128 while ((zbuf[n++] != 0) && (n < len)); 6129 6130 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; 6131 bp->strm->avail_in = len - n; 6132 bp->strm->next_out = bp->gunzip_buf; 6133 bp->strm->avail_out = FW_BUF_SIZE; 6134 6135 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); 6136 if (rc != Z_OK) 6137 return rc; 6138 6139 rc = zlib_inflate(bp->strm, Z_FINISH); 6140 if ((rc != Z_OK) && (rc != Z_STREAM_END)) 6141 netdev_err(bp->dev, "Firmware decompression error: %s\n", 6142 bp->strm->msg); 6143 6144 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); 6145 if (bp->gunzip_outlen & 0x3) 6146 netdev_err(bp->dev, 6147 "Firmware decompression error: gunzip_outlen (%d) not aligned\n", 6148 bp->gunzip_outlen); 6149 bp->gunzip_outlen >>= 2; 6150 6151 zlib_inflateEnd(bp->strm); 6152 6153 if (rc == Z_STREAM_END) 6154 return 0; 6155 6156 return rc; 6157 } 6158 6159 /* nic load/unload */ 6160 6161 /* 6162 * General service functions 6163 */ 6164 6165 /* send a NIG loopback debug packet */ 6166 static void bnx2x_lb_pckt(struct bnx2x *bp) 6167 { 6168 u32 wb_write[3]; 6169 6170 /* Ethernet source and destination addresses */ 6171 wb_write[0] = 0x55555555; 6172 wb_write[1] = 0x55555555; 6173 wb_write[2] = 0x20; /* SOP */ 6174 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 6175 6176 /* NON-IP protocol */ 6177 wb_write[0] = 0x09000000; 6178 wb_write[1] = 0x55555555; 6179 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ 6180 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 6181 } 6182 6183 /* some of the internal memories 6184 * are not directly readable from the driver 6185 * to test them we send debug packets 6186 */ 6187 static int bnx2x_int_mem_test(struct bnx2x *bp) 6188 { 6189 int factor; 6190 int count, i; 6191 u32 val = 0; 6192 6193 if (CHIP_REV_IS_FPGA(bp)) 6194 factor = 120; 6195 else if (CHIP_REV_IS_EMUL(bp)) 6196 factor = 200; 6197 else 6198 factor = 1; 6199 6200 /* Disable inputs of parser neighbor blocks */ 6201 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 6202 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 6203 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 6204 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 6205 6206 /* Write 0 to parser credits for CFC search request */ 6207 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 6208 6209 /* send Ethernet packet */ 6210 bnx2x_lb_pckt(bp); 6211 6212 /* TODO do i reset NIG statistic? */ 6213 /* Wait until NIG register shows 1 packet of size 0x10 */ 6214 count = 1000 * factor; 6215 while (count) { 6216 6217 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 6218 val = *bnx2x_sp(bp, wb_data[0]); 6219 if (val == 0x10) 6220 break; 6221 6222 msleep(10); 6223 count--; 6224 } 6225 if (val != 0x10) { 6226 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 6227 return -1; 6228 } 6229 6230 /* Wait until PRS register shows 1 packet */ 6231 count = 1000 * factor; 6232 while (count) { 6233 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 6234 if (val == 1) 6235 break; 6236 6237 msleep(10); 6238 count--; 6239 } 6240 if (val != 0x1) { 6241 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 6242 return -2; 6243 } 6244 6245 /* Reset and init BRB, PRS */ 6246 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 6247 msleep(50); 6248 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 6249 msleep(50); 6250 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 6251 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 6252 6253 DP(NETIF_MSG_HW, "part2\n"); 6254 6255 /* Disable inputs of parser neighbor blocks */ 6256 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 6257 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 6258 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 6259 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 6260 6261 /* Write 0 to parser credits for CFC search request */ 6262 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 6263 6264 /* send 10 Ethernet packets */ 6265 for (i = 0; i < 10; i++) 6266 bnx2x_lb_pckt(bp); 6267 6268 /* Wait until NIG register shows 10 + 1 6269 packets of size 11*0x10 = 0xb0 */ 6270 count = 1000 * factor; 6271 while (count) { 6272 6273 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 6274 val = *bnx2x_sp(bp, wb_data[0]); 6275 if (val == 0xb0) 6276 break; 6277 6278 msleep(10); 6279 count--; 6280 } 6281 if (val != 0xb0) { 6282 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 6283 return -3; 6284 } 6285 6286 /* Wait until PRS register shows 2 packets */ 6287 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 6288 if (val != 2) 6289 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 6290 6291 /* Write 1 to parser credits for CFC search request */ 6292 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); 6293 6294 /* Wait until PRS register shows 3 packets */ 6295 msleep(10 * factor); 6296 /* Wait until NIG register shows 1 packet of size 0x10 */ 6297 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 6298 if (val != 3) 6299 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 6300 6301 /* clear NIG EOP FIFO */ 6302 for (i = 0; i < 11; i++) 6303 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); 6304 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); 6305 if (val != 1) { 6306 BNX2X_ERR("clear of NIG failed\n"); 6307 return -4; 6308 } 6309 6310 /* Reset and init BRB, PRS, NIG */ 6311 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 6312 msleep(50); 6313 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 6314 msleep(50); 6315 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 6316 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 6317 if (!CNIC_SUPPORT(bp)) 6318 /* set NIC mode */ 6319 REG_WR(bp, PRS_REG_NIC_MODE, 1); 6320 6321 /* Enable inputs of parser neighbor blocks */ 6322 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); 6323 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); 6324 REG_WR(bp, CFC_REG_DEBUG0, 0x0); 6325 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); 6326 6327 DP(NETIF_MSG_HW, "done\n"); 6328 6329 return 0; /* OK */ 6330 } 6331 6332 static void bnx2x_enable_blocks_attention(struct bnx2x *bp) 6333 { 6334 u32 val; 6335 6336 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 6337 if (!CHIP_IS_E1x(bp)) 6338 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); 6339 else 6340 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); 6341 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 6342 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 6343 /* 6344 * mask read length error interrupts in brb for parser 6345 * (parsing unit and 'checksum and crc' unit) 6346 * these errors are legal (PU reads fixed length and CAC can cause 6347 * read length error on truncated packets) 6348 */ 6349 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); 6350 REG_WR(bp, QM_REG_QM_INT_MASK, 0); 6351 REG_WR(bp, TM_REG_TM_INT_MASK, 0); 6352 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); 6353 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); 6354 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); 6355 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ 6356 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ 6357 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); 6358 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); 6359 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); 6360 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ 6361 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ 6362 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); 6363 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); 6364 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); 6365 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); 6366 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ 6367 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ 6368 6369 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT | 6370 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF | 6371 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN; 6372 if (!CHIP_IS_E1x(bp)) 6373 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED | 6374 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED; 6375 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val); 6376 6377 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); 6378 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); 6379 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); 6380 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ 6381 6382 if (!CHIP_IS_E1x(bp))