Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

  1 /* bnx2x_main.c: Broadcom Everest network driver.
  2  *
  3  * Copyright (c) 2007-2013 Broadcom Corporation
  4  *
  5  * This program is free software; you can redistribute it and/or modify
  6  * it under the terms of the GNU General Public License as published by
  7  * the Free Software Foundation.
  8  *
  9  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
 10  * Written by: Eliezer Tamir
 11  * Based on code from Michael Chan's bnx2 driver
 12  * UDP CSUM errata workaround by Arik Gendelman
 13  * Slowpath and fastpath rework by Vladislav Zolotarov
 14  * Statistics and Link management by Yitchak Gertner
 15  *
 16  */
 17 
 18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 19 
 20 #include <linux/module.h>
 21 #include <linux/moduleparam.h>
 22 #include <linux/kernel.h>
 23 #include <linux/device.h>  /* for dev_info() */
 24 #include <linux/timer.h>
 25 #include <linux/errno.h>
 26 #include <linux/ioport.h>
 27 #include <linux/slab.h>
 28 #include <linux/interrupt.h>
 29 #include <linux/pci.h>
 30 #include <linux/aer.h>
 31 #include <linux/init.h>
 32 #include <linux/netdevice.h>
 33 #include <linux/etherdevice.h>
 34 #include <linux/skbuff.h>
 35 #include <linux/dma-mapping.h>
 36 #include <linux/bitops.h>
 37 #include <linux/irq.h>
 38 #include <linux/delay.h>
 39 #include <asm/byteorder.h>
 40 #include <linux/time.h>
 41 #include <linux/ethtool.h>
 42 #include <linux/mii.h>
 43 #include <linux/if_vlan.h>
 44 #include <linux/crash_dump.h>
 45 #include <net/ip.h>
 46 #include <net/ipv6.h>
 47 #include <net/tcp.h>
 48 #include <net/checksum.h>
 49 #include <net/ip6_checksum.h>
 50 #include <linux/workqueue.h>
 51 #include <linux/crc32.h>
 52 #include <linux/crc32c.h>
 53 #include <linux/prefetch.h>
 54 #include <linux/zlib.h>
 55 #include <linux/io.h>
 56 #include <linux/semaphore.h>
 57 #include <linux/stringify.h>
 58 #include <linux/vmalloc.h>
 59 
 60 #include "bnx2x.h"
 61 #include "bnx2x_init.h"
 62 #include "bnx2x_init_ops.h"
 63 #include "bnx2x_cmn.h"
 64 #include "bnx2x_vfpf.h"
 65 #include "bnx2x_dcb.h"
 66 #include "bnx2x_sp.h"
 67 #include <linux/firmware.h>
 68 #include "bnx2x_fw_file_hdr.h"
 69 /* FW files */
 70 #define FW_FILE_VERSION                                 \
 71         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
 72         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
 73         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
 74         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
 75 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
 76 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
 77 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
 78 
 79 /* Time in jiffies before concluding the transmitter is hung */
 80 #define TX_TIMEOUT              (5*HZ)
 81 
 82 static char version[] =
 83         "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
 84         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 85 
 86 MODULE_AUTHOR("Eliezer Tamir");
 87 MODULE_DESCRIPTION("Broadcom NetXtreme II "
 88                    "BCM57710/57711/57711E/"
 89                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
 90                    "57840/57840_MF Driver");
 91 MODULE_LICENSE("GPL");
 92 MODULE_VERSION(DRV_MODULE_VERSION);
 93 MODULE_FIRMWARE(FW_FILE_NAME_E1);
 94 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
 95 MODULE_FIRMWARE(FW_FILE_NAME_E2);
 96 
 97 int bnx2x_num_queues;
 98 module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
 99 MODULE_PARM_DESC(num_queues,
100                  " Set number of queues (default is as a number of CPUs)");
101 
102 static int disable_tpa;
103 module_param(disable_tpa, int, S_IRUGO);
104 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
105 
106 static int int_mode;
107 module_param(int_mode, int, S_IRUGO);
108 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
109                                 "(1 INT#x; 2 MSI)");
110 
111 static int dropless_fc;
112 module_param(dropless_fc, int, S_IRUGO);
113 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
114 
115 static int mrrs = -1;
116 module_param(mrrs, int, S_IRUGO);
117 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
118 
119 static int debug;
120 module_param(debug, int, S_IRUGO);
121 MODULE_PARM_DESC(debug, " Default debug msglevel");
122 
123 static struct workqueue_struct *bnx2x_wq;
124 struct workqueue_struct *bnx2x_iov_wq;
125 
126 struct bnx2x_mac_vals {
127         u32 xmac_addr;
128         u32 xmac_val;
129         u32 emac_addr;
130         u32 emac_val;
131         u32 umac_addr;
132         u32 umac_val;
133         u32 bmac_addr;
134         u32 bmac_val[2];
135 };
136 
137 enum bnx2x_board_type {
138         BCM57710 = 0,
139         BCM57711,
140         BCM57711E,
141         BCM57712,
142         BCM57712_MF,
143         BCM57712_VF,
144         BCM57800,
145         BCM57800_MF,
146         BCM57800_VF,
147         BCM57810,
148         BCM57810_MF,
149         BCM57810_VF,
150         BCM57840_4_10,
151         BCM57840_2_20,
152         BCM57840_MF,
153         BCM57840_VF,
154         BCM57811,
155         BCM57811_MF,
156         BCM57840_O,
157         BCM57840_MFO,
158         BCM57811_VF
159 };
160 
161 /* indexed by board_type, above */
162 static struct {
163         char *name;
164 } board_info[] = {
165         [BCM57710]      = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
166         [BCM57711]      = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
167         [BCM57711E]     = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
168         [BCM57712]      = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
169         [BCM57712_MF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
170         [BCM57712_VF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
171         [BCM57800]      = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
172         [BCM57800_MF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
173         [BCM57800_VF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
174         [BCM57810]      = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
175         [BCM57810_MF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
176         [BCM57810_VF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
177         [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
178         [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
179         [BCM57840_MF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
180         [BCM57840_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
181         [BCM57811]      = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
182         [BCM57811_MF]   = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
183         [BCM57840_O]    = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
184         [BCM57840_MFO]  = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
185         [BCM57811_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
186 };
187 
188 #ifndef PCI_DEVICE_ID_NX2_57710
189 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
190 #endif
191 #ifndef PCI_DEVICE_ID_NX2_57711
192 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
193 #endif
194 #ifndef PCI_DEVICE_ID_NX2_57711E
195 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
196 #endif
197 #ifndef PCI_DEVICE_ID_NX2_57712
198 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
199 #endif
200 #ifndef PCI_DEVICE_ID_NX2_57712_MF
201 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
202 #endif
203 #ifndef PCI_DEVICE_ID_NX2_57712_VF
204 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
205 #endif
206 #ifndef PCI_DEVICE_ID_NX2_57800
207 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
208 #endif
209 #ifndef PCI_DEVICE_ID_NX2_57800_MF
210 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
211 #endif
212 #ifndef PCI_DEVICE_ID_NX2_57800_VF
213 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
214 #endif
215 #ifndef PCI_DEVICE_ID_NX2_57810
216 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
217 #endif
218 #ifndef PCI_DEVICE_ID_NX2_57810_MF
219 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
220 #endif
221 #ifndef PCI_DEVICE_ID_NX2_57840_O
222 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
223 #endif
224 #ifndef PCI_DEVICE_ID_NX2_57810_VF
225 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
226 #endif
227 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
228 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
229 #endif
230 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
231 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
232 #endif
233 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
234 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
235 #endif
236 #ifndef PCI_DEVICE_ID_NX2_57840_MF
237 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
238 #endif
239 #ifndef PCI_DEVICE_ID_NX2_57840_VF
240 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
241 #endif
242 #ifndef PCI_DEVICE_ID_NX2_57811
243 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
244 #endif
245 #ifndef PCI_DEVICE_ID_NX2_57811_MF
246 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
247 #endif
248 #ifndef PCI_DEVICE_ID_NX2_57811_VF
249 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
250 #endif
251 
252 static const struct pci_device_id bnx2x_pci_tbl[] = {
253         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
254         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
255         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
272         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
273         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
274         { 0 }
275 };
276 
277 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
278 
279 /* Global resources for unloading a previously loaded device */
280 #define BNX2X_PREV_WAIT_NEEDED 1
281 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
282 static LIST_HEAD(bnx2x_prev_list);
283 
284 /* Forward declaration */
285 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
286 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
287 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
288 
289 /****************************************************************************
290 * General service functions
291 ****************************************************************************/
292 
293 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
294 
295 static void __storm_memset_dma_mapping(struct bnx2x *bp,
296                                        u32 addr, dma_addr_t mapping)
297 {
298         REG_WR(bp,  addr, U64_LO(mapping));
299         REG_WR(bp,  addr + 4, U64_HI(mapping));
300 }
301 
302 static void storm_memset_spq_addr(struct bnx2x *bp,
303                                   dma_addr_t mapping, u16 abs_fid)
304 {
305         u32 addr = XSEM_REG_FAST_MEMORY +
306                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
307 
308         __storm_memset_dma_mapping(bp, addr, mapping);
309 }
310 
311 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
312                                   u16 pf_id)
313 {
314         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
315                 pf_id);
316         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
317                 pf_id);
318         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
319                 pf_id);
320         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
321                 pf_id);
322 }
323 
324 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
325                                  u8 enable)
326 {
327         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
328                 enable);
329         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
330                 enable);
331         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
332                 enable);
333         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
334                 enable);
335 }
336 
337 static void storm_memset_eq_data(struct bnx2x *bp,
338                                  struct event_ring_data *eq_data,
339                                 u16 pfid)
340 {
341         size_t size = sizeof(struct event_ring_data);
342 
343         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
344 
345         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
346 }
347 
348 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
349                                  u16 pfid)
350 {
351         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
352         REG_WR16(bp, addr, eq_prod);
353 }
354 
355 /* used only at init
356  * locking is done by mcp
357  */
358 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
359 {
360         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
361         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
362         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
363                                PCICFG_VENDOR_ID_OFFSET);
364 }
365 
366 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
367 {
368         u32 val;
369 
370         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
371         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
372         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
373                                PCICFG_VENDOR_ID_OFFSET);
374 
375         return val;
376 }
377 
378 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
379 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
380 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
381 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
382 #define DMAE_DP_DST_NONE        "dst_addr [none]"
383 
384 static void bnx2x_dp_dmae(struct bnx2x *bp,
385                           struct dmae_command *dmae, int msglvl)
386 {
387         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
388         int i;
389 
390         switch (dmae->opcode & DMAE_COMMAND_DST) {
391         case DMAE_CMD_DST_PCI:
392                 if (src_type == DMAE_CMD_SRC_PCI)
393                         DP(msglvl, "DMAE: opcode 0x%08x\n"
394                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
395                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
396                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
397                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
398                            dmae->comp_addr_hi, dmae->comp_addr_lo,
399                            dmae->comp_val);
400                 else
401                         DP(msglvl, "DMAE: opcode 0x%08x\n"
402                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
403                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
404                            dmae->opcode, dmae->src_addr_lo >> 2,
405                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
406                            dmae->comp_addr_hi, dmae->comp_addr_lo,
407                            dmae->comp_val);
408                 break;
409         case DMAE_CMD_DST_GRC:
410                 if (src_type == DMAE_CMD_SRC_PCI)
411                         DP(msglvl, "DMAE: opcode 0x%08x\n"
412                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
413                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
414                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
415                            dmae->len, dmae->dst_addr_lo >> 2,
416                            dmae->comp_addr_hi, dmae->comp_addr_lo,
417                            dmae->comp_val);
418                 else
419                         DP(msglvl, "DMAE: opcode 0x%08x\n"
420                            "src [%08x], len [%d*4], dst [%08x]\n"
421                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
422                            dmae->opcode, dmae->src_addr_lo >> 2,
423                            dmae->len, dmae->dst_addr_lo >> 2,
424                            dmae->comp_addr_hi, dmae->comp_addr_lo,
425                            dmae->comp_val);
426                 break;
427         default:
428                 if (src_type == DMAE_CMD_SRC_PCI)
429                         DP(msglvl, "DMAE: opcode 0x%08x\n"
430                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
431                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
432                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
433                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
434                            dmae->comp_val);
435                 else
436                         DP(msglvl, "DMAE: opcode 0x%08x\n"
437                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
438                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
439                            dmae->opcode, dmae->src_addr_lo >> 2,
440                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
441                            dmae->comp_val);
442                 break;
443         }
444 
445         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
446                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
447                    i, *(((u32 *)dmae) + i));
448 }
449 
450 /* copy command into DMAE command memory and set DMAE command go */
451 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
452 {
453         u32 cmd_offset;
454         int i;
455 
456         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
457         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
458                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
459         }
460         REG_WR(bp, dmae_reg_go_c[idx], 1);
461 }
462 
463 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
464 {
465         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
466                            DMAE_CMD_C_ENABLE);
467 }
468 
469 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
470 {
471         return opcode & ~DMAE_CMD_SRC_RESET;
472 }
473 
474 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
475                              bool with_comp, u8 comp_type)
476 {
477         u32 opcode = 0;
478 
479         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
480                    (dst_type << DMAE_COMMAND_DST_SHIFT));
481 
482         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
483 
484         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
485         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
486                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
487         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
488 
489 #ifdef __BIG_ENDIAN
490         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
491 #else
492         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
493 #endif
494         if (with_comp)
495                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
496         return opcode;
497 }
498 
499 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
500                                       struct dmae_command *dmae,
501                                       u8 src_type, u8 dst_type)
502 {
503         memset(dmae, 0, sizeof(struct dmae_command));
504 
505         /* set the opcode */
506         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
507                                          true, DMAE_COMP_PCI);
508 
509         /* fill in the completion parameters */
510         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
511         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
512         dmae->comp_val = DMAE_COMP_VAL;
513 }
514 
515 /* issue a dmae command over the init-channel and wait for completion */
516 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
517                                u32 *comp)
518 {
519         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
520         int rc = 0;
521 
522         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
523 
524         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
525          * as long as this code is called both from syscall context and
526          * from ndo_set_rx_mode() flow that may be called from BH.
527          */
528 
529         spin_lock_bh(&bp->dmae_lock);
530 
531         /* reset completion */
532         *comp = 0;
533 
534         /* post the command on the channel used for initializations */
535         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
536 
537         /* wait for completion */
538         udelay(5);
539         while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
540 
541                 if (!cnt ||
542                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
543                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
544                         BNX2X_ERR("DMAE timeout!\n");
545                         rc = DMAE_TIMEOUT;
546                         goto unlock;
547                 }
548                 cnt--;
549                 udelay(50);
550         }
551         if (*comp & DMAE_PCI_ERR_FLAG) {
552                 BNX2X_ERR("DMAE PCI error!\n");
553                 rc = DMAE_PCI_ERROR;
554         }
555 
556 unlock:
557 
558         spin_unlock_bh(&bp->dmae_lock);
559 
560         return rc;
561 }
562 
563 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
564                       u32 len32)
565 {
566         int rc;
567         struct dmae_command dmae;
568 
569         if (!bp->dmae_ready) {
570                 u32 *data = bnx2x_sp(bp, wb_data[0]);
571 
572                 if (CHIP_IS_E1(bp))
573                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
574                 else
575                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
576                 return;
577         }
578 
579         /* set opcode and fixed command fields */
580         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
581 
582         /* fill in addresses and len */
583         dmae.src_addr_lo = U64_LO(dma_addr);
584         dmae.src_addr_hi = U64_HI(dma_addr);
585         dmae.dst_addr_lo = dst_addr >> 2;
586         dmae.dst_addr_hi = 0;
587         dmae.len = len32;
588 
589         /* issue the command and wait for completion */
590         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
591         if (rc) {
592                 BNX2X_ERR("DMAE returned failure %d\n", rc);
593 #ifdef BNX2X_STOP_ON_ERROR
594                 bnx2x_panic();
595 #endif
596         }
597 }
598 
599 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
600 {
601         int rc;
602         struct dmae_command dmae;
603 
604         if (!bp->dmae_ready) {
605                 u32 *data = bnx2x_sp(bp, wb_data[0]);
606                 int i;
607 
608                 if (CHIP_IS_E1(bp))
609                         for (i = 0; i < len32; i++)
610                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
611                 else
612                         for (i = 0; i < len32; i++)
613                                 data[i] = REG_RD(bp, src_addr + i*4);
614 
615                 return;
616         }
617 
618         /* set opcode and fixed command fields */
619         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
620 
621         /* fill in addresses and len */
622         dmae.src_addr_lo = src_addr >> 2;
623         dmae.src_addr_hi = 0;
624         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
625         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
626         dmae.len = len32;
627 
628         /* issue the command and wait for completion */
629         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
630         if (rc) {
631                 BNX2X_ERR("DMAE returned failure %d\n", rc);
632 #ifdef BNX2X_STOP_ON_ERROR
633                 bnx2x_panic();
634 #endif
635         }
636 }
637 
638 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
639                                       u32 addr, u32 len)
640 {
641         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
642         int offset = 0;
643 
644         while (len > dmae_wr_max) {
645                 bnx2x_write_dmae(bp, phys_addr + offset,
646                                  addr + offset, dmae_wr_max);
647                 offset += dmae_wr_max * 4;
648                 len -= dmae_wr_max;
649         }
650 
651         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
652 }
653 
654 enum storms {
655            XSTORM,
656            TSTORM,
657            CSTORM,
658            USTORM,
659            MAX_STORMS
660 };
661 
662 #define STORMS_NUM 4
663 #define REGS_IN_ENTRY 4
664 
665 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
666                                               enum storms storm,
667                                               int entry)
668 {
669         switch (storm) {
670         case XSTORM:
671                 return XSTORM_ASSERT_LIST_OFFSET(entry);
672         case TSTORM:
673                 return TSTORM_ASSERT_LIST_OFFSET(entry);
674         case CSTORM:
675                 return CSTORM_ASSERT_LIST_OFFSET(entry);
676         case USTORM:
677                 return USTORM_ASSERT_LIST_OFFSET(entry);
678         case MAX_STORMS:
679         default:
680                 BNX2X_ERR("unknown storm\n");
681         }
682         return -EINVAL;
683 }
684 
685 static int bnx2x_mc_assert(struct bnx2x *bp)
686 {
687         char last_idx;
688         int i, j, rc = 0;
689         enum storms storm;
690         u32 regs[REGS_IN_ENTRY];
691         u32 bar_storm_intmem[STORMS_NUM] = {
692                 BAR_XSTRORM_INTMEM,
693                 BAR_TSTRORM_INTMEM,
694                 BAR_CSTRORM_INTMEM,
695                 BAR_USTRORM_INTMEM
696         };
697         u32 storm_assert_list_index[STORMS_NUM] = {
698                 XSTORM_ASSERT_LIST_INDEX_OFFSET,
699                 TSTORM_ASSERT_LIST_INDEX_OFFSET,
700                 CSTORM_ASSERT_LIST_INDEX_OFFSET,
701                 USTORM_ASSERT_LIST_INDEX_OFFSET
702         };
703         char *storms_string[STORMS_NUM] = {
704                 "XSTORM",
705                 "TSTORM",
706                 "CSTORM",
707                 "USTORM"
708         };
709 
710         for (storm = XSTORM; storm < MAX_STORMS; storm++) {
711                 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
712                                    storm_assert_list_index[storm]);
713                 if (last_idx)
714                         BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
715                                   storms_string[storm], last_idx);
716 
717                 /* print the asserts */
718                 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
719                         /* read a single assert entry */
720                         for (j = 0; j < REGS_IN_ENTRY; j++)
721                                 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
722                                           bnx2x_get_assert_list_entry(bp,
723                                                                       storm,
724                                                                       i) +
725                                           sizeof(u32) * j);
726 
727                         /* log entry if it contains a valid assert */
728                         if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
729                                 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
730                                           storms_string[storm], i, regs[3],
731                                           regs[2], regs[1], regs[0]);
732                                 rc++;
733                         } else {
734                                 break;
735                         }
736                 }
737         }
738 
739         BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
740                   CHIP_IS_E1(bp) ? "everest1" :
741                   CHIP_IS_E1H(bp) ? "everest1h" :
742                   CHIP_IS_E2(bp) ? "everest2" : "everest3",
743                   BCM_5710_FW_MAJOR_VERSION,
744                   BCM_5710_FW_MINOR_VERSION,
745                   BCM_5710_FW_REVISION_VERSION);
746 
747         return rc;
748 }
749 
750 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
751 #define SCRATCH_BUFFER_SIZE(bp) \
752         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
753 
754 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
755 {
756         u32 addr, val;
757         u32 mark, offset;
758         __be32 data[9];
759         int word;
760         u32 trace_shmem_base;
761         if (BP_NOMCP(bp)) {
762                 BNX2X_ERR("NO MCP - can not dump\n");
763                 return;
764         }
765         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
766                 (bp->common.bc_ver & 0xff0000) >> 16,
767                 (bp->common.bc_ver & 0xff00) >> 8,
768                 (bp->common.bc_ver & 0xff));
769 
770         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
771         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
772                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
773 
774         if (BP_PATH(bp) == 0)
775                 trace_shmem_base = bp->common.shmem_base;
776         else
777                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
778 
779         /* sanity */
780         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
781             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
782                                 SCRATCH_BUFFER_SIZE(bp)) {
783                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
784                           trace_shmem_base);
785                 return;
786         }
787 
788         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
789 
790         /* validate TRCB signature */
791         mark = REG_RD(bp, addr);
792         if (mark != MFW_TRACE_SIGNATURE) {
793                 BNX2X_ERR("Trace buffer signature is missing.");
794                 return ;
795         }
796 
797         /* read cyclic buffer pointer */
798         addr += 4;
799         mark = REG_RD(bp, addr);
800         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
801         if (mark >= trace_shmem_base || mark < addr + 4) {
802                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
803                 return;
804         }
805         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
806 
807         printk("%s", lvl);
808 
809         /* dump buffer after the mark */
810         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
811                 for (word = 0; word < 8; word++)
812                         data[word] = htonl(REG_RD(bp, offset + 4*word));
813                 data[8] = 0x0;
814                 pr_cont("%s", (char *)data);
815         }
816 
817         /* dump buffer before the mark */
818         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
819                 for (word = 0; word < 8; word++)
820                         data[word] = htonl(REG_RD(bp, offset + 4*word));
821                 data[8] = 0x0;
822                 pr_cont("%s", (char *)data);
823         }
824         printk("%s" "end of fw dump\n", lvl);
825 }
826 
827 static void bnx2x_fw_dump(struct bnx2x *bp)
828 {
829         bnx2x_fw_dump_lvl(bp, KERN_ERR);
830 }
831 
832 static void bnx2x_hc_int_disable(struct bnx2x *bp)
833 {
834         int port = BP_PORT(bp);
835         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
836         u32 val = REG_RD(bp, addr);
837 
838         /* in E1 we must use only PCI configuration space to disable
839          * MSI/MSIX capability
840          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
841          */
842         if (CHIP_IS_E1(bp)) {
843                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
844                  * Use mask register to prevent from HC sending interrupts
845                  * after we exit the function
846                  */
847                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
848 
849                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
850                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
851                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
852         } else
853                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
854                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
855                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
856                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
857 
858         DP(NETIF_MSG_IFDOWN,
859            "write %x to HC %d (addr 0x%x)\n",
860            val, port, addr);
861 
862         /* flush all outstanding writes */
863         mmiowb();
864 
865         REG_WR(bp, addr, val);
866         if (REG_RD(bp, addr) != val)
867                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
868 }
869 
870 static void bnx2x_igu_int_disable(struct bnx2x *bp)
871 {
872         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
873 
874         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
875                  IGU_PF_CONF_INT_LINE_EN |
876                  IGU_PF_CONF_ATTN_BIT_EN);
877 
878         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
879 
880         /* flush all outstanding writes */
881         mmiowb();
882 
883         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
884         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
885                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
886 }
887 
888 static void bnx2x_int_disable(struct bnx2x *bp)
889 {
890         if (bp->common.int_block == INT_BLOCK_HC)
891                 bnx2x_hc_int_disable(bp);
892         else
893                 bnx2x_igu_int_disable(bp);
894 }
895 
896 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
897 {
898         int i;
899         u16 j;
900         struct hc_sp_status_block_data sp_sb_data;
901         int func = BP_FUNC(bp);
902 #ifdef BNX2X_STOP_ON_ERROR
903         u16 start = 0, end = 0;
904         u8 cos;
905 #endif
906         if (IS_PF(bp) && disable_int)
907                 bnx2x_int_disable(bp);
908 
909         bp->stats_state = STATS_STATE_DISABLED;
910         bp->eth_stats.unrecoverable_error++;
911         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
912 
913         BNX2X_ERR("begin crash dump -----------------\n");
914 
915         /* Indices */
916         /* Common */
917         if (IS_PF(bp)) {
918                 struct host_sp_status_block *def_sb = bp->def_status_blk;
919                 int data_size, cstorm_offset;
920 
921                 BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
922                           bp->def_idx, bp->def_att_idx, bp->attn_state,
923                           bp->spq_prod_idx, bp->stats_counter);
924                 BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
925                           def_sb->atten_status_block.attn_bits,
926                           def_sb->atten_status_block.attn_bits_ack,
927                           def_sb->atten_status_block.status_block_id,
928                           def_sb->atten_status_block.attn_bits_index);
929                 BNX2X_ERR("     def (");
930                 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
931                         pr_cont("0x%x%s",
932                                 def_sb->sp_sb.index_values[i],
933                                 (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
934 
935                 data_size = sizeof(struct hc_sp_status_block_data) /
936                             sizeof(u32);
937                 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
938                 for (i = 0; i < data_size; i++)
939                         *((u32 *)&sp_sb_data + i) =
940                                 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
941                                            i * sizeof(u32));
942 
943                 pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
944                         sp_sb_data.igu_sb_id,
945                         sp_sb_data.igu_seg_id,
946                         sp_sb_data.p_func.pf_id,
947                         sp_sb_data.p_func.vnic_id,
948                         sp_sb_data.p_func.vf_id,
949                         sp_sb_data.p_func.vf_valid,
950                         sp_sb_data.state);
951         }
952 
953         for_each_eth_queue(bp, i) {
954                 struct bnx2x_fastpath *fp = &bp->fp[i];
955                 int loop;
956                 struct hc_status_block_data_e2 sb_data_e2;
957                 struct hc_status_block_data_e1x sb_data_e1x;
958                 struct hc_status_block_sm  *hc_sm_p =
959                         CHIP_IS_E1x(bp) ?
960                         sb_data_e1x.common.state_machine :
961                         sb_data_e2.common.state_machine;
962                 struct hc_index_data *hc_index_p =
963                         CHIP_IS_E1x(bp) ?
964                         sb_data_e1x.index_data :
965                         sb_data_e2.index_data;
966                 u8 data_size, cos;
967                 u32 *sb_data_p;
968                 struct bnx2x_fp_txdata txdata;
969 
970                 if (!bp->fp)
971                         break;
972 
973                 if (!fp->rx_cons_sb)
974                         continue;
975 
976                 /* Rx */
977                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
978                           i, fp->rx_bd_prod, fp->rx_bd_cons,
979                           fp->rx_comp_prod,
980                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
981                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
982                           fp->rx_sge_prod, fp->last_max_sge,
983                           le16_to_cpu(fp->fp_hc_idx));
984 
985                 /* Tx */
986                 for_each_cos_in_tx_queue(fp, cos)
987                 {
988                         if (!fp->txdata_ptr[cos])
989                                 break;
990 
991                         txdata = *fp->txdata_ptr[cos];
992 
993                         if (!txdata.tx_cons_sb)
994                                 continue;
995 
996                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
997                                   i, txdata.tx_pkt_prod,
998                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
999                                   txdata.tx_bd_cons,
1000                                   le16_to_cpu(*txdata.tx_cons_sb));
1001                 }
1002 
1003                 loop = CHIP_IS_E1x(bp) ?
1004                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1005 
1006                 /* host sb data */
1007 
1008                 if (IS_FCOE_FP(fp))
1009                         continue;
1010 
1011                 BNX2X_ERR("     run indexes (");
1012                 for (j = 0; j < HC_SB_MAX_SM; j++)
1013                         pr_cont("0x%x%s",
1014                                fp->sb_running_index[j],
1015                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1016 
1017                 BNX2X_ERR("     indexes (");
1018                 for (j = 0; j < loop; j++)
1019                         pr_cont("0x%x%s",
1020                                fp->sb_index_values[j],
1021                                (j == loop - 1) ? ")" : " ");
1022 
1023                 /* VF cannot access FW refelection for status block */
1024                 if (IS_VF(bp))
1025                         continue;
1026 
1027                 /* fw sb data */
1028                 data_size = CHIP_IS_E1x(bp) ?
1029                         sizeof(struct hc_status_block_data_e1x) :
1030                         sizeof(struct hc_status_block_data_e2);
1031                 data_size /= sizeof(u32);
1032                 sb_data_p = CHIP_IS_E1x(bp) ?
1033                         (u32 *)&sb_data_e1x :
1034                         (u32 *)&sb_data_e2;
1035                 /* copy sb data in here */
1036                 for (j = 0; j < data_size; j++)
1037                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1038                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1039                                 j * sizeof(u32));
1040 
1041                 if (!CHIP_IS_E1x(bp)) {
1042                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1043                                 sb_data_e2.common.p_func.pf_id,
1044                                 sb_data_e2.common.p_func.vf_id,
1045                                 sb_data_e2.common.p_func.vf_valid,
1046                                 sb_data_e2.common.p_func.vnic_id,
1047                                 sb_data_e2.common.same_igu_sb_1b,
1048                                 sb_data_e2.common.state);
1049                 } else {
1050                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1051                                 sb_data_e1x.common.p_func.pf_id,
1052                                 sb_data_e1x.common.p_func.vf_id,
1053                                 sb_data_e1x.common.p_func.vf_valid,
1054                                 sb_data_e1x.common.p_func.vnic_id,
1055                                 sb_data_e1x.common.same_igu_sb_1b,
1056                                 sb_data_e1x.common.state);
1057                 }
1058 
1059                 /* SB_SMs data */
1060                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1061                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1062                                 j, hc_sm_p[j].__flags,
1063                                 hc_sm_p[j].igu_sb_id,
1064                                 hc_sm_p[j].igu_seg_id,
1065                                 hc_sm_p[j].time_to_expire,
1066                                 hc_sm_p[j].timer_value);
1067                 }
1068 
1069                 /* Indices data */
1070                 for (j = 0; j < loop; j++) {
1071                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1072                                hc_index_p[j].flags,
1073                                hc_index_p[j].timeout);
1074                 }
1075         }
1076 
1077 #ifdef BNX2X_STOP_ON_ERROR
1078         if (IS_PF(bp)) {
1079                 /* event queue */
1080                 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1081                 for (i = 0; i < NUM_EQ_DESC; i++) {
1082                         u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1083 
1084                         BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1085                                   i, bp->eq_ring[i].message.opcode,
1086                                   bp->eq_ring[i].message.error);
1087                         BNX2X_ERR("data: %x %x %x\n",
1088                                   data[0], data[1], data[2]);
1089                 }
1090         }
1091 
1092         /* Rings */
1093         /* Rx */
1094         for_each_valid_rx_queue(bp, i) {
1095                 struct bnx2x_fastpath *fp = &bp->fp[i];
1096 
1097                 if (!bp->fp)
1098                         break;
1099 
1100                 if (!fp->rx_cons_sb)
1101                         continue;
1102 
1103                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1104                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1105                 for (j = start; j != end; j = RX_BD(j + 1)) {
1106                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1107                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1108 
1109                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1110                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1111                 }
1112 
1113                 start = RX_SGE(fp->rx_sge_prod);
1114                 end = RX_SGE(fp->last_max_sge);
1115                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1116                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1117                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1118 
1119                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1120                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1121                 }
1122 
1123                 start = RCQ_BD(fp->rx_comp_cons - 10);
1124                 end = RCQ_BD(fp->rx_comp_cons + 503);
1125                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1126                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1127 
1128                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1129                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1130                 }
1131         }
1132 
1133         /* Tx */
1134         for_each_valid_tx_queue(bp, i) {
1135                 struct bnx2x_fastpath *fp = &bp->fp[i];
1136 
1137                 if (!bp->fp)
1138                         break;
1139 
1140                 for_each_cos_in_tx_queue(fp, cos) {
1141                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1142 
1143                         if (!fp->txdata_ptr[cos])
1144                                 break;
1145 
1146                         if (!txdata->tx_cons_sb)
1147                                 continue;
1148 
1149                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1150                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1151                         for (j = start; j != end; j = TX_BD(j + 1)) {
1152                                 struct sw_tx_bd *sw_bd =
1153                                         &txdata->tx_buf_ring[j];
1154 
1155                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1156                                           i, cos, j, sw_bd->skb,
1157                                           sw_bd->first_bd);
1158                         }
1159 
1160                         start = TX_BD(txdata->tx_bd_cons - 10);
1161                         end = TX_BD(txdata->tx_bd_cons + 254);
1162                         for (j = start; j != end; j = TX_BD(j + 1)) {
1163                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1164 
1165                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1166                                           i, cos, j, tx_bd[0], tx_bd[1],
1167                                           tx_bd[2], tx_bd[3]);
1168                         }
1169                 }
1170         }
1171 #endif
1172         if (IS_PF(bp)) {
1173                 bnx2x_fw_dump(bp);
1174                 bnx2x_mc_assert(bp);
1175         }
1176         BNX2X_ERR("end crash dump -----------------\n");
1177 }
1178 
1179 /*
1180  * FLR Support for E2
1181  *
1182  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1183  * initialization.
1184  */
1185 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1186 #define FLR_WAIT_INTERVAL       50      /* usec */
1187 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1188 
1189 struct pbf_pN_buf_regs {
1190         int pN;
1191         u32 init_crd;
1192         u32 crd;
1193         u32 crd_freed;
1194 };
1195 
1196 struct pbf_pN_cmd_regs {
1197         int pN;
1198         u32 lines_occup;
1199         u32 lines_freed;
1200 };
1201 
1202 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1203                                      struct pbf_pN_buf_regs *regs,
1204                                      u32 poll_count)
1205 {
1206         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1207         u32 cur_cnt = poll_count;
1208 
1209         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1210         crd = crd_start = REG_RD(bp, regs->crd);
1211         init_crd = REG_RD(bp, regs->init_crd);
1212 
1213         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1214         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1215         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1216 
1217         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1218                (init_crd - crd_start))) {
1219                 if (cur_cnt--) {
1220                         udelay(FLR_WAIT_INTERVAL);
1221                         crd = REG_RD(bp, regs->crd);
1222                         crd_freed = REG_RD(bp, regs->crd_freed);
1223                 } else {
1224                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1225                            regs->pN);
1226                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1227                            regs->pN, crd);
1228                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1229                            regs->pN, crd_freed);
1230                         break;
1231                 }
1232         }
1233         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1234            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1235 }
1236 
1237 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1238                                      struct pbf_pN_cmd_regs *regs,
1239                                      u32 poll_count)
1240 {
1241         u32 occup, to_free, freed, freed_start;
1242         u32 cur_cnt = poll_count;
1243 
1244         occup = to_free = REG_RD(bp, regs->lines_occup);
1245         freed = freed_start = REG_RD(bp, regs->lines_freed);
1246 
1247         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1248         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1249 
1250         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1251                 if (cur_cnt--) {
1252                         udelay(FLR_WAIT_INTERVAL);
1253                         occup = REG_RD(bp, regs->lines_occup);
1254                         freed = REG_RD(bp, regs->lines_freed);
1255                 } else {
1256                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1257                            regs->pN);
1258                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1259                            regs->pN, occup);
1260                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1261                            regs->pN, freed);
1262                         break;
1263                 }
1264         }
1265         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1266            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1267 }
1268 
1269 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1270                                     u32 expected, u32 poll_count)
1271 {
1272         u32 cur_cnt = poll_count;
1273         u32 val;
1274 
1275         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1276                 udelay(FLR_WAIT_INTERVAL);
1277 
1278         return val;
1279 }
1280 
1281 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1282                                     char *msg, u32 poll_cnt)
1283 {
1284         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1285         if (val != 0) {
1286                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1287                 return 1;
1288         }
1289         return 0;
1290 }
1291 
1292 /* Common routines with VF FLR cleanup */
1293 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1294 {
1295         /* adjust polling timeout */
1296         if (CHIP_REV_IS_EMUL(bp))
1297                 return FLR_POLL_CNT * 2000;
1298 
1299         if (CHIP_REV_IS_FPGA(bp))
1300                 return FLR_POLL_CNT * 120;
1301 
1302         return FLR_POLL_CNT;
1303 }
1304 
1305 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1306 {
1307         struct pbf_pN_cmd_regs cmd_regs[] = {
1308                 {0, (CHIP_IS_E3B0(bp)) ?
1309                         PBF_REG_TQ_OCCUPANCY_Q0 :
1310                         PBF_REG_P0_TQ_OCCUPANCY,
1311                     (CHIP_IS_E3B0(bp)) ?
1312                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1313                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1314                 {1, (CHIP_IS_E3B0(bp)) ?
1315                         PBF_REG_TQ_OCCUPANCY_Q1 :
1316                         PBF_REG_P1_TQ_OCCUPANCY,
1317                     (CHIP_IS_E3B0(bp)) ?
1318                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1319                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1320                 {4, (CHIP_IS_E3B0(bp)) ?
1321                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1322                         PBF_REG_P4_TQ_OCCUPANCY,
1323                     (CHIP_IS_E3B0(bp)) ?
1324                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1325                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1326         };
1327 
1328         struct pbf_pN_buf_regs buf_regs[] = {
1329                 {0, (CHIP_IS_E3B0(bp)) ?
1330                         PBF_REG_INIT_CRD_Q0 :
1331                         PBF_REG_P0_INIT_CRD ,
1332                     (CHIP_IS_E3B0(bp)) ?
1333                         PBF_REG_CREDIT_Q0 :
1334                         PBF_REG_P0_CREDIT,
1335                     (CHIP_IS_E3B0(bp)) ?
1336                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1337                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1338                 {1, (CHIP_IS_E3B0(bp)) ?
1339                         PBF_REG_INIT_CRD_Q1 :
1340                         PBF_REG_P1_INIT_CRD,
1341                     (CHIP_IS_E3B0(bp)) ?
1342                         PBF_REG_CREDIT_Q1 :
1343                         PBF_REG_P1_CREDIT,
1344                     (CHIP_IS_E3B0(bp)) ?
1345                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1346                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1347                 {4, (CHIP_IS_E3B0(bp)) ?
1348                         PBF_REG_INIT_CRD_LB_Q :
1349                         PBF_REG_P4_INIT_CRD,
1350                     (CHIP_IS_E3B0(bp)) ?
1351                         PBF_REG_CREDIT_LB_Q :
1352                         PBF_REG_P4_CREDIT,
1353                     (CHIP_IS_E3B0(bp)) ?
1354                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1355                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1356         };
1357 
1358         int i;
1359 
1360         /* Verify the command queues are flushed P0, P1, P4 */
1361         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1362                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1363 
1364         /* Verify the transmission buffers are flushed P0, P1, P4 */
1365         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1366                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1367 }
1368 
1369 #define OP_GEN_PARAM(param) \
1370         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1371 
1372 #define OP_GEN_TYPE(type) \
1373         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1374 
1375 #define OP_GEN_AGG_VECT(index) \
1376         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1377 
1378 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1379 {
1380         u32 op_gen_command = 0;
1381         u32 comp_addr = BAR_CSTRORM_INTMEM +
1382                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1383         int ret = 0;
1384 
1385         if (REG_RD(bp, comp_addr)) {
1386                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1387                 return 1;
1388         }
1389 
1390         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1391         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1392         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1393         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1394 
1395         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1396         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1397 
1398         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1399                 BNX2X_ERR("FW final cleanup did not succeed\n");
1400                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1401                    (REG_RD(bp, comp_addr)));
1402                 bnx2x_panic();
1403                 return 1;
1404         }
1405         /* Zero completion for next FLR */
1406         REG_WR(bp, comp_addr, 0);
1407 
1408         return ret;
1409 }
1410 
1411 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1412 {
1413         u16 status;
1414 
1415         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1416         return status & PCI_EXP_DEVSTA_TRPND;
1417 }
1418 
1419 /* PF FLR specific routines
1420 */
1421 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1422 {
1423         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1424         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1425                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1426                         "CFC PF usage counter timed out",
1427                         poll_cnt))
1428                 return 1;
1429 
1430         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1431         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1432                         DORQ_REG_PF_USAGE_CNT,
1433                         "DQ PF usage counter timed out",
1434                         poll_cnt))
1435                 return 1;
1436 
1437         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1438         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1439                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1440                         "QM PF usage counter timed out",
1441                         poll_cnt))
1442                 return 1;
1443 
1444         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1445         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1446                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1447                         "Timers VNIC usage counter timed out",
1448                         poll_cnt))
1449                 return 1;
1450         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1451                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1452                         "Timers NUM_SCANS usage counter timed out",
1453                         poll_cnt))
1454                 return 1;
1455 
1456         /* Wait DMAE PF usage counter to zero */
1457         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1458                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1459                         "DMAE command register timed out",
1460                         poll_cnt))
1461                 return 1;
1462 
1463         return 0;
1464 }
1465 
1466 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1467 {
1468         u32 val;
1469 
1470         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1471         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1472 
1473         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1474         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1475 
1476         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1477         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1478 
1479         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1480         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1481 
1482         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1483         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1484 
1485         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1486         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1487 
1488         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1489         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1490 
1491         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1492         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1493            val);
1494 }
1495 
1496 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1497 {
1498         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1499 
1500         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1501 
1502         /* Re-enable PF target read access */
1503         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1504 
1505         /* Poll HW usage counters */
1506         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1507         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1508                 return -EBUSY;
1509 
1510         /* Zero the igu 'trailing edge' and 'leading edge' */
1511 
1512         /* Send the FW cleanup command */
1513         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1514                 return -EBUSY;
1515 
1516         /* ATC cleanup */
1517 
1518         /* Verify TX hw is flushed */
1519         bnx2x_tx_hw_flushed(bp, poll_cnt);
1520 
1521         /* Wait 100ms (not adjusted according to platform) */
1522         msleep(100);
1523 
1524         /* Verify no pending pci transactions */
1525         if (bnx2x_is_pcie_pending(bp->pdev))
1526                 BNX2X_ERR("PCIE Transactions still pending\n");
1527 
1528         /* Debug */
1529         bnx2x_hw_enable_status(bp);
1530 
1531         /*
1532          * Master enable - Due to WB DMAE writes performed before this
1533          * register is re-initialized as part of the regular function init
1534          */
1535         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1536 
1537         return 0;
1538 }
1539 
1540 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1541 {
1542         int port = BP_PORT(bp);
1543         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1544         u32 val = REG_RD(bp, addr);
1545         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1546         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1547         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1548 
1549         if (msix) {
1550                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1551                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1552                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1553                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1554                 if (single_msix)
1555                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1556         } else if (msi) {
1557                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1558                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1559                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1560                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1561         } else {
1562                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1563                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1564                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1565                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1566 
1567                 if (!CHIP_IS_E1(bp)) {
1568                         DP(NETIF_MSG_IFUP,
1569                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1570 
1571                         REG_WR(bp, addr, val);
1572 
1573                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1574                 }
1575         }
1576 
1577         if (CHIP_IS_E1(bp))
1578                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1579 
1580         DP(NETIF_MSG_IFUP,
1581            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1582            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1583 
1584         REG_WR(bp, addr, val);
1585         /*
1586          * Ensure that HC_CONFIG is written before leading/trailing edge config
1587          */
1588         mmiowb();
1589         barrier();
1590 
1591         if (!CHIP_IS_E1(bp)) {
1592                 /* init leading/trailing edge */
1593                 if (IS_MF(bp)) {
1594                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1595                         if (bp->port.pmf)
1596                                 /* enable nig and gpio3 attention */
1597                                 val |= 0x1100;
1598                 } else
1599                         val = 0xffff;
1600 
1601                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1602                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1603         }
1604 
1605         /* Make sure that interrupts are indeed enabled from here on */
1606         mmiowb();
1607 }
1608 
1609 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1610 {
1611         u32 val;
1612         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1613         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1614         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1615 
1616         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1617 
1618         if (msix) {
1619                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1620                          IGU_PF_CONF_SINGLE_ISR_EN);
1621                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1622                         IGU_PF_CONF_ATTN_BIT_EN);
1623 
1624                 if (single_msix)
1625                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1626         } else if (msi) {
1627                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1628                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1629                         IGU_PF_CONF_ATTN_BIT_EN |
1630                         IGU_PF_CONF_SINGLE_ISR_EN);
1631         } else {
1632                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1633                 val |= (IGU_PF_CONF_INT_LINE_EN |
1634                         IGU_PF_CONF_ATTN_BIT_EN |
1635                         IGU_PF_CONF_SINGLE_ISR_EN);
1636         }
1637 
1638         /* Clean previous status - need to configure igu prior to ack*/
1639         if ((!msix) || single_msix) {
1640                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1641                 bnx2x_ack_int(bp);
1642         }
1643 
1644         val |= IGU_PF_CONF_FUNC_EN;
1645 
1646         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1647            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1648 
1649         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1650 
1651         if (val & IGU_PF_CONF_INT_LINE_EN)
1652                 pci_intx(bp->pdev, true);
1653 
1654         barrier();
1655 
1656         /* init leading/trailing edge */
1657         if (IS_MF(bp)) {
1658                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1659                 if (bp->port.pmf)
1660                         /* enable nig and gpio3 attention */
1661                         val |= 0x1100;
1662         } else
1663                 val = 0xffff;
1664 
1665         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1666         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1667 
1668         /* Make sure that interrupts are indeed enabled from here on */
1669         mmiowb();
1670 }
1671 
1672 void bnx2x_int_enable(struct bnx2x *bp)
1673 {
1674         if (bp->common.int_block == INT_BLOCK_HC)
1675                 bnx2x_hc_int_enable(bp);
1676         else
1677                 bnx2x_igu_int_enable(bp);
1678 }
1679 
1680 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1681 {
1682         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1683         int i, offset;
1684 
1685         if (disable_hw)
1686                 /* prevent the HW from sending interrupts */
1687                 bnx2x_int_disable(bp);
1688 
1689         /* make sure all ISRs are done */
1690         if (msix) {
1691                 synchronize_irq(bp->msix_table[0].vector);
1692                 offset = 1;
1693                 if (CNIC_SUPPORT(bp))
1694                         offset++;
1695                 for_each_eth_queue(bp, i)
1696                         synchronize_irq(bp->msix_table[offset++].vector);
1697         } else
1698                 synchronize_irq(bp->pdev->irq);
1699 
1700         /* make sure sp_task is not running */
1701         cancel_delayed_work(&bp->sp_task);
1702         cancel_delayed_work(&bp->period_task);
1703         flush_workqueue(bnx2x_wq);
1704 }
1705 
1706 /* fast path */
1707 
1708 /*
1709  * General service functions
1710  */
1711 
1712 /* Return true if succeeded to acquire the lock */
1713 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1714 {
1715         u32 lock_status;
1716         u32 resource_bit = (1 << resource);
1717         int func = BP_FUNC(bp);
1718         u32 hw_lock_control_reg;
1719 
1720         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1721            "Trying to take a lock on resource %d\n", resource);
1722 
1723         /* Validating that the resource is within range */
1724         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1725                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1726                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1727                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1728                 return false;
1729         }
1730 
1731         if (func <= 5)
1732                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1733         else
1734                 hw_lock_control_reg =
1735                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1736 
1737         /* Try to acquire the lock */
1738         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1739         lock_status = REG_RD(bp, hw_lock_control_reg);
1740         if (lock_status & resource_bit)
1741                 return true;
1742 
1743         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1744            "Failed to get a lock on resource %d\n", resource);
1745         return false;
1746 }
1747 
1748 /**
1749  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1750  *
1751  * @bp: driver handle
1752  *
1753  * Returns the recovery leader resource id according to the engine this function
1754  * belongs to. Currently only only 2 engines is supported.
1755  */
1756 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1757 {
1758         if (BP_PATH(bp))
1759                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1760         else
1761                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1762 }
1763 
1764 /**
1765  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1766  *
1767  * @bp: driver handle
1768  *
1769  * Tries to acquire a leader lock for current engine.
1770  */
1771 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1772 {
1773         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1774 }
1775 
1776 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1777 
1778 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1779 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1780 {
1781         /* Set the interrupt occurred bit for the sp-task to recognize it
1782          * must ack the interrupt and transition according to the IGU
1783          * state machine.
1784          */
1785         atomic_set(&bp->interrupt_occurred, 1);
1786 
1787         /* The sp_task must execute only after this bit
1788          * is set, otherwise we will get out of sync and miss all
1789          * further interrupts. Hence, the barrier.
1790          */
1791         smp_wmb();
1792 
1793         /* schedule sp_task to workqueue */
1794         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1795 }
1796 
1797 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1798 {
1799         struct bnx2x *bp = fp->bp;
1800         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1801         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1802         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1803         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1804 
1805         DP(BNX2X_MSG_SP,
1806            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1807            fp->index, cid, command, bp->state,
1808            rr_cqe->ramrod_cqe.ramrod_type);
1809 
1810         /* If cid is within VF range, replace the slowpath object with the
1811          * one corresponding to this VF
1812          */
1813         if (cid >= BNX2X_FIRST_VF_CID  &&
1814             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1815                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1816 
1817         switch (command) {
1818         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1819                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1820                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1821                 break;
1822 
1823         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1824                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1825                 drv_cmd = BNX2X_Q_CMD_SETUP;
1826                 break;
1827 
1828         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1829                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1830                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1831                 break;
1832 
1833         case (RAMROD_CMD_ID_ETH_HALT):
1834                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1835                 drv_cmd = BNX2X_Q_CMD_HALT;
1836                 break;
1837 
1838         case (RAMROD_CMD_ID_ETH_TERMINATE):
1839                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1840                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1841                 break;
1842 
1843         case (RAMROD_CMD_ID_ETH_EMPTY):
1844                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1845                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1846                 break;
1847 
1848         case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1849                 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1850                 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1851                 break;
1852 
1853         default:
1854                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1855                           command, fp->index);
1856                 return;
1857         }
1858 
1859         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1860             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1861                 /* q_obj->complete_cmd() failure means that this was
1862                  * an unexpected completion.
1863                  *
1864                  * In this case we don't want to increase the bp->spq_left
1865                  * because apparently we haven't sent this command the first
1866                  * place.
1867                  */
1868 #ifdef BNX2X_STOP_ON_ERROR
1869                 bnx2x_panic();
1870 #else
1871                 return;
1872 #endif
1873 
1874         smp_mb__before_atomic();
1875         atomic_inc(&bp->cq_spq_left);
1876         /* push the change in bp->spq_left and towards the memory */
1877         smp_mb__after_atomic();
1878 
1879         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1880 
1881         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1882             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1883                 /* if Q update ramrod is completed for last Q in AFEX vif set
1884                  * flow, then ACK MCP at the end
1885                  *
1886                  * mark pending ACK to MCP bit.
1887                  * prevent case that both bits are cleared.
1888                  * At the end of load/unload driver checks that
1889                  * sp_state is cleared, and this order prevents
1890                  * races
1891                  */
1892                 smp_mb__before_atomic();
1893                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1894                 wmb();
1895                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1896                 smp_mb__after_atomic();
1897 
1898                 /* schedule the sp task as mcp ack is required */
1899                 bnx2x_schedule_sp_task(bp);
1900         }
1901 
1902         return;
1903 }
1904 
1905 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1906 {
1907         struct bnx2x *bp = netdev_priv(dev_instance);
1908         u16 status = bnx2x_ack_int(bp);
1909         u16 mask;
1910         int i;
1911         u8 cos;
1912 
1913         /* Return here if interrupt is shared and it's not for us */
1914         if (unlikely(status == 0)) {
1915                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1916                 return IRQ_NONE;
1917         }
1918         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1919 
1920 #ifdef BNX2X_STOP_ON_ERROR
1921         if (unlikely(bp->panic))
1922                 return IRQ_HANDLED;
1923 #endif
1924 
1925         for_each_eth_queue(bp, i) {
1926                 struct bnx2x_fastpath *fp = &bp->fp[i];
1927 
1928                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1929                 if (status & mask) {
1930                         /* Handle Rx or Tx according to SB id */
1931                         for_each_cos_in_tx_queue(fp, cos)
1932                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1933                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1934                         napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1935                         status &= ~mask;
1936                 }
1937         }
1938 
1939         if (CNIC_SUPPORT(bp)) {
1940                 mask = 0x2;
1941                 if (status & (mask | 0x1)) {
1942                         struct cnic_ops *c_ops = NULL;
1943 
1944                         rcu_read_lock();
1945                         c_ops = rcu_dereference(bp->cnic_ops);
1946                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1947                                       CNIC_DRV_STATE_HANDLES_IRQ))
1948                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1949                         rcu_read_unlock();
1950 
1951                         status &= ~mask;
1952                 }
1953         }
1954 
1955         if (unlikely(status & 0x1)) {
1956 
1957                 /* schedule sp task to perform default status block work, ack
1958                  * attentions and enable interrupts.
1959                  */
1960                 bnx2x_schedule_sp_task(bp);
1961 
1962                 status &= ~0x1;
1963                 if (!status)
1964                         return IRQ_HANDLED;
1965         }
1966 
1967         if (unlikely(status))
1968                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1969                    status);
1970 
1971         return IRQ_HANDLED;
1972 }
1973 
1974 /* Link */
1975 
1976 /*
1977  * General service functions
1978  */
1979 
1980 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1981 {
1982         u32 lock_status;
1983         u32 resource_bit = (1 << resource);
1984         int func = BP_FUNC(bp);
1985         u32 hw_lock_control_reg;
1986         int cnt;
1987 
1988         /* Validating that the resource is within range */
1989         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1990                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1991                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1992                 return -EINVAL;
1993         }
1994 
1995         if (func <= 5) {
1996                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1997         } else {
1998                 hw_lock_control_reg =
1999                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2000         }
2001 
2002         /* Validating that the resource is not already taken */
2003         lock_status = REG_RD(bp, hw_lock_control_reg);
2004         if (lock_status & resource_bit) {
2005                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
2006                    lock_status, resource_bit);
2007                 return -EEXIST;
2008         }
2009 
2010         /* Try for 5 second every 5ms */
2011         for (cnt = 0; cnt < 1000; cnt++) {
2012                 /* Try to acquire the lock */
2013                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2014                 lock_status = REG_RD(bp, hw_lock_control_reg);
2015                 if (lock_status & resource_bit)
2016                         return 0;
2017 
2018                 usleep_range(5000, 10000);
2019         }
2020         BNX2X_ERR("Timeout\n");
2021         return -EAGAIN;
2022 }
2023 
2024 int bnx2x_release_leader_lock(struct bnx2x *bp)
2025 {
2026         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2027 }
2028 
2029 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2030 {
2031         u32 lock_status;
2032         u32 resource_bit = (1 << resource);
2033         int func = BP_FUNC(bp);
2034         u32 hw_lock_control_reg;
2035 
2036         /* Validating that the resource is within range */
2037         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2038                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2039                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
2040                 return -EINVAL;
2041         }
2042 
2043         if (func <= 5) {
2044                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2045         } else {
2046                 hw_lock_control_reg =
2047                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2048         }
2049 
2050         /* Validating that the resource is currently taken */
2051         lock_status = REG_RD(bp, hw_lock_control_reg);
2052         if (!(lock_status & resource_bit)) {
2053                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2054                           lock_status, resource_bit);
2055                 return -EFAULT;
2056         }
2057 
2058         REG_WR(bp, hw_lock_control_reg, resource_bit);
2059         return 0;
2060 }
2061 
2062 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2063 {
2064         /* The GPIO should be swapped if swap register is set and active */
2065         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2066                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2067         int gpio_shift = gpio_num +
2068                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2069         u32 gpio_mask = (1 << gpio_shift);
2070         u32 gpio_reg;
2071         int value;
2072 
2073         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2074                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2075                 return -EINVAL;
2076         }
2077 
2078         /* read GPIO value */
2079         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2080 
2081         /* get the requested pin value */
2082         if ((gpio_reg & gpio_mask) == gpio_mask)
2083                 value = 1;
2084         else
2085                 value = 0;
2086 
2087         return value;
2088 }
2089 
2090 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2091 {
2092         /* The GPIO should be swapped if swap register is set and active */
2093         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2094                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2095         int gpio_shift = gpio_num +
2096                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2097         u32 gpio_mask = (1 << gpio_shift);
2098         u32 gpio_reg;
2099 
2100         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2101                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2102                 return -EINVAL;
2103         }
2104 
2105         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2106         /* read GPIO and mask except the float bits */
2107         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2108 
2109         switch (mode) {
2110         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2111                 DP(NETIF_MSG_LINK,
2112                    "Set GPIO %d (shift %d) -> output low\n",
2113                    gpio_num, gpio_shift);
2114                 /* clear FLOAT and set CLR */
2115                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2116                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2117                 break;
2118 
2119         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2120                 DP(NETIF_MSG_LINK,
2121                    "Set GPIO %d (shift %d) -> output high\n",
2122                    gpio_num, gpio_shift);
2123                 /* clear FLOAT and set SET */
2124                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2125                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2126                 break;
2127 
2128         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2129                 DP(NETIF_MSG_LINK,
2130                    "Set GPIO %d (shift %d) -> input\n",
2131                    gpio_num, gpio_shift);
2132                 /* set FLOAT */
2133                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2134                 break;
2135 
2136         default:
2137                 break;
2138         }
2139 
2140         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2141         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2142 
2143         return 0;
2144 }
2145 
2146 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2147 {
2148         u32 gpio_reg = 0;
2149         int rc = 0;
2150 
2151         /* Any port swapping should be handled by caller. */
2152 
2153         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2154         /* read GPIO and mask except the float bits */
2155         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2156         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2157         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2158         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2159 
2160         switch (mode) {
2161         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2162                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2163                 /* set CLR */
2164                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2165                 break;
2166 
2167         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2168                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2169                 /* set SET */
2170                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2171                 break;
2172 
2173         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2174                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2175                 /* set FLOAT */
2176                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2177                 break;
2178 
2179         default:
2180                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2181                 rc = -EINVAL;
2182                 break;
2183         }
2184 
2185         if (rc == 0)
2186                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2187 
2188         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2189 
2190         return rc;
2191 }
2192 
2193 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2194 {
2195         /* The GPIO should be swapped if swap register is set and active */
2196         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2197                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2198         int gpio_shift = gpio_num +
2199                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2200         u32 gpio_mask = (1 << gpio_shift);
2201         u32 gpio_reg;
2202 
2203         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2204                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2205                 return -EINVAL;
2206         }
2207 
2208         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2209         /* read GPIO int */
2210         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2211 
2212         switch (mode) {
2213         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2214                 DP(NETIF_MSG_LINK,
2215                    "Clear GPIO INT %d (shift %d) -> output low\n",
2216                    gpio_num, gpio_shift);
2217                 /* clear SET and set CLR */
2218                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2219                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2220                 break;
2221 
2222         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2223                 DP(NETIF_MSG_LINK,
2224                    "Set GPIO INT %d (shift %d) -> output high\n",
2225                    gpio_num, gpio_shift);
2226                 /* clear CLR and set SET */
2227                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2228                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2229                 break;
2230 
2231         default:
2232                 break;
2233         }
2234 
2235         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2236         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2237 
2238         return 0;
2239 }
2240 
2241 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2242 {
2243         u32 spio_reg;
2244 
2245         /* Only 2 SPIOs are configurable */
2246         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2247                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2248                 return -EINVAL;
2249         }
2250 
2251         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2252         /* read SPIO and mask except the float bits */
2253         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2254 
2255         switch (mode) {
2256         case MISC_SPIO_OUTPUT_LOW:
2257                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2258                 /* clear FLOAT and set CLR */
2259                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2260                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2261                 break;
2262 
2263         case MISC_SPIO_OUTPUT_HIGH:
2264                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2265                 /* clear FLOAT and set SET */
2266                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2267                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2268                 break;
2269 
2270         case MISC_SPIO_INPUT_HI_Z:
2271                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2272                 /* set FLOAT */
2273                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2274                 break;
2275 
2276         default:
2277                 break;
2278         }
2279 
2280         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2281         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2282 
2283         return 0;
2284 }
2285 
2286 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2287 {
2288         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2289         switch (bp->link_vars.ieee_fc &
2290                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2291         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2292                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2293                                                    ADVERTISED_Pause);
2294                 break;
2295 
2296         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2297                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2298                                                   ADVERTISED_Pause);
2299                 break;
2300 
2301         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2302                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2303                 break;
2304 
2305         default:
2306                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2307                                                    ADVERTISED_Pause);
2308                 break;
2309         }
2310 }
2311 
2312 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2313 {
2314         /* Initialize link parameters structure variables
2315          * It is recommended to turn off RX FC for jumbo frames
2316          *  for better performance
2317          */
2318         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2319                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2320         else
2321                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2322 }
2323 
2324 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2325 {
2326         u32 pause_enabled = 0;
2327 
2328         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2329                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2330                         pause_enabled = 1;
2331 
2332                 REG_WR(bp, BAR_USTRORM_INTMEM +
2333                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2334                        pause_enabled);
2335         }
2336 
2337         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2338            pause_enabled ? "enabled" : "disabled");
2339 }
2340 
2341 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2342 {
2343         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2344         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2345 
2346         if (!BP_NOMCP(bp)) {
2347                 bnx2x_set_requested_fc(bp);
2348                 bnx2x_acquire_phy_lock(bp);
2349 
2350                 if (load_mode == LOAD_DIAG) {
2351                         struct link_params *lp = &bp->link_params;
2352                         lp->loopback_mode = LOOPBACK_XGXS;
2353                         /* do PHY loopback at 10G speed, if possible */
2354                         if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2355                                 if (lp->speed_cap_mask[cfx_idx] &
2356                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2357                                         lp->req_line_speed[cfx_idx] =
2358                                         SPEED_10000;
2359                                 else
2360                                         lp->req_line_speed[cfx_idx] =
2361                                         SPEED_1000;
2362                         }
2363                 }
2364 
2365                 if (load_mode == LOAD_LOOPBACK_EXT) {
2366                         struct link_params *lp = &bp->link_params;
2367                         lp->loopback_mode = LOOPBACK_EXT;
2368                 }
2369 
2370                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2371 
2372                 bnx2x_release_phy_lock(bp);
2373 
2374                 bnx2x_init_dropless_fc(bp);
2375 
2376                 bnx2x_calc_fc_adv(bp);
2377 
2378                 if (bp->link_vars.link_up) {
2379                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2380                         bnx2x_link_report(bp);
2381                 }
2382                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2383                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2384                 return rc;
2385         }
2386         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2387         return -EINVAL;
2388 }
2389 
2390 void bnx2x_link_set(struct bnx2x *bp)
2391 {
2392         if (!BP_NOMCP(bp)) {
2393                 bnx2x_acquire_phy_lock(bp);
2394                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2395                 bnx2x_release_phy_lock(bp);
2396 
2397                 bnx2x_init_dropless_fc(bp);
2398 
2399                 bnx2x_calc_fc_adv(bp);
2400         } else
2401                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2402 }
2403 
2404 static void bnx2x__link_reset(struct bnx2x *bp)
2405 {
2406         if (!BP_NOMCP(bp)) {
2407                 bnx2x_acquire_phy_lock(bp);
2408                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2409                 bnx2x_release_phy_lock(bp);
2410         } else
2411                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2412 }
2413 
2414 void bnx2x_force_link_reset(struct bnx2x *bp)
2415 {
2416         bnx2x_acquire_phy_lock(bp);
2417         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2418         bnx2x_release_phy_lock(bp);
2419 }
2420 
2421 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2422 {
2423         u8 rc = 0;
2424 
2425         if (!BP_NOMCP(bp)) {
2426                 bnx2x_acquire_phy_lock(bp);
2427                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2428                                      is_serdes);
2429                 bnx2x_release_phy_lock(bp);
2430         } else
2431                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2432 
2433         return rc;
2434 }
2435 
2436 /* Calculates the sum of vn_min_rates.
2437    It's needed for further normalizing of the min_rates.
2438    Returns:
2439      sum of vn_min_rates.
2440        or
2441      0 - if all the min_rates are 0.
2442      In the later case fairness algorithm should be deactivated.
2443      If not all min_rates are zero then those that are zeroes will be set to 1.
2444  */
2445 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2446                                       struct cmng_init_input *input)
2447 {
2448         int all_zero = 1;
2449         int vn;
2450 
2451         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2452                 u32 vn_cfg = bp->mf_config[vn];
2453                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2454                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2455 
2456                 /* Skip hidden vns */
2457                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2458                         vn_min_rate = 0;
2459                 /* If min rate is zero - set it to 1 */
2460                 else if (!vn_min_rate)
2461                         vn_min_rate = DEF_MIN_RATE;
2462                 else
2463                         all_zero = 0;
2464 
2465                 input->vnic_min_rate[vn] = vn_min_rate;
2466         }
2467 
2468         /* if ETS or all min rates are zeros - disable fairness */
2469         if (BNX2X_IS_ETS_ENABLED(bp)) {
2470                 input->flags.cmng_enables &=
2471                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2472                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2473         } else if (all_zero) {
2474                 input->flags.cmng_enables &=
2475                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2476                 DP(NETIF_MSG_IFUP,
2477                    "All MIN values are zeroes fairness will be disabled\n");
2478         } else
2479                 input->flags.cmng_enables |=
2480                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2481 }
2482 
2483 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2484                                     struct cmng_init_input *input)
2485 {
2486         u16 vn_max_rate;
2487         u32 vn_cfg = bp->mf_config[vn];
2488 
2489         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2490                 vn_max_rate = 0;
2491         else {
2492                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2493 
2494                 if (IS_MF_SI(bp)) {
2495                         /* maxCfg in percents of linkspeed */
2496                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2497                 } else /* SD modes */
2498                         /* maxCfg is absolute in 100Mb units */
2499                         vn_max_rate = maxCfg * 100;
2500         }
2501 
2502         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2503 
2504         input->vnic_max_rate[vn] = vn_max_rate;
2505 }
2506 
2507 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2508 {
2509         if (CHIP_REV_IS_SLOW(bp))
2510                 return CMNG_FNS_NONE;
2511         if (IS_MF(bp))
2512                 return CMNG_FNS_MINMAX;
2513 
2514         return CMNG_FNS_NONE;
2515 }
2516 
2517 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2518 {
2519         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2520 
2521         if (BP_NOMCP(bp))
2522                 return; /* what should be the default value in this case */
2523 
2524         /* For 2 port configuration the absolute function number formula
2525          * is:
2526          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2527          *
2528          *      and there are 4 functions per port
2529          *
2530          * For 4 port configuration it is
2531          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2532          *
2533          *      and there are 2 functions per port
2534          */
2535         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2536                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2537 
2538                 if (func >= E1H_FUNC_MAX)
2539                         break;
2540 
2541                 bp->mf_config[vn] =
2542                         MF_CFG_RD(bp, func_mf_config[func].config);
2543         }
2544         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2545                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2546                 bp->flags |= MF_FUNC_DIS;
2547         } else {
2548                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2549                 bp->flags &= ~MF_FUNC_DIS;
2550         }
2551 }
2552 
2553 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2554 {
2555         struct cmng_init_input input;
2556         memset(&input, 0, sizeof(struct cmng_init_input));
2557 
2558         input.port_rate = bp->link_vars.line_speed;
2559 
2560         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2561                 int vn;
2562 
2563                 /* read mf conf from shmem */
2564                 if (read_cfg)
2565                         bnx2x_read_mf_cfg(bp);
2566 
2567                 /* vn_weight_sum and enable fairness if not 0 */
2568                 bnx2x_calc_vn_min(bp, &input);
2569 
2570                 /* calculate and set min-max rate for each vn */
2571                 if (bp->port.pmf)
2572                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2573                                 bnx2x_calc_vn_max(bp, vn, &input);
2574 
2575                 /* always enable rate shaping and fairness */
2576                 input.flags.cmng_enables |=
2577                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2578 
2579                 bnx2x_init_cmng(&input, &bp->cmng);
2580                 return;
2581         }
2582 
2583         /* rate shaping and fairness are disabled */
2584         DP(NETIF_MSG_IFUP,
2585            "rate shaping and fairness are disabled\n");
2586 }
2587 
2588 static void storm_memset_cmng(struct bnx2x *bp,
2589                               struct cmng_init *cmng,
2590                               u8 port)
2591 {
2592         int vn;
2593         size_t size = sizeof(struct cmng_struct_per_port);
2594 
2595         u32 addr = BAR_XSTRORM_INTMEM +
2596                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2597 
2598         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2599 
2600         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2601                 int func = func_by_vn(bp, vn);
2602 
2603                 addr = BAR_XSTRORM_INTMEM +
2604                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2605                 size = sizeof(struct rate_shaping_vars_per_vn);
2606                 __storm_memset_struct(bp, addr, size,
2607                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2608 
2609                 addr = BAR_XSTRORM_INTMEM +
2610                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2611                 size = sizeof(struct fairness_vars_per_vn);
2612                 __storm_memset_struct(bp, addr, size,
2613                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2614         }
2615 }
2616 
2617 /* init cmng mode in HW according to local configuration */
2618 void bnx2x_set_local_cmng(struct bnx2x *bp)
2619 {
2620         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2621 
2622         if (cmng_fns != CMNG_FNS_NONE) {
2623                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2624                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2625         } else {
2626                 /* rate shaping and fairness are disabled */
2627                 DP(NETIF_MSG_IFUP,
2628                    "single function mode without fairness\n");
2629         }
2630 }
2631 
2632 /* This function is called upon link interrupt */
2633 static void bnx2x_link_attn(struct bnx2x *bp)
2634 {
2635         /* Make sure that we are synced with the current statistics */
2636         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2637 
2638         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2639 
2640         bnx2x_init_dropless_fc(bp);
2641 
2642         if (bp->link_vars.link_up) {
2643 
2644                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2645                         struct host_port_stats *pstats;
2646 
2647                         pstats = bnx2x_sp(bp, port_stats);
2648                         /* reset old mac stats */
2649                         memset(&(pstats->mac_stx[0]), 0,
2650                                sizeof(struct mac_stx));
2651                 }
2652                 if (bp->state == BNX2X_STATE_OPEN)
2653                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2654         }
2655 
2656         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2657                 bnx2x_set_local_cmng(bp);
2658 
2659         __bnx2x_link_report(bp);
2660 
2661         if (IS_MF(bp))
2662                 bnx2x_link_sync_notify(bp);
2663 }
2664 
2665 void bnx2x__link_status_update(struct bnx2x *bp)
2666 {
2667         if (bp->state != BNX2X_STATE_OPEN)
2668                 return;
2669 
2670         /* read updated dcb configuration */
2671         if (IS_PF(bp)) {
2672                 bnx2x_dcbx_pmf_update(bp);
2673                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2674                 if (bp->link_vars.link_up)
2675                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2676                 else
2677                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2678                         /* indicate link status */
2679                 bnx2x_link_report(bp);
2680 
2681         } else { /* VF */
2682                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2683                                           SUPPORTED_10baseT_Full |
2684                                           SUPPORTED_100baseT_Half |
2685                                           SUPPORTED_100baseT_Full |
2686                                           SUPPORTED_1000baseT_Full |
2687                                           SUPPORTED_2500baseX_Full |
2688                                           SUPPORTED_10000baseT_Full |
2689                                           SUPPORTED_TP |
2690                                           SUPPORTED_FIBRE |
2691                                           SUPPORTED_Autoneg |
2692                                           SUPPORTED_Pause |
2693                                           SUPPORTED_Asym_Pause);
2694                 bp->port.advertising[0] = bp->port.supported[0];
2695 
2696                 bp->link_params.bp = bp;
2697                 bp->link_params.port = BP_PORT(bp);
2698                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2699                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2700                 bp->link_params.req_line_speed[0] = SPEED_10000;
2701                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2702                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2703                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2704                 bp->link_vars.line_speed = SPEED_10000;
2705                 bp->link_vars.link_status =
2706                         (LINK_STATUS_LINK_UP |
2707                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2708                 bp->link_vars.link_up = 1;
2709                 bp->link_vars.duplex = DUPLEX_FULL;
2710                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2711                 __bnx2x_link_report(bp);
2712 
2713                 bnx2x_sample_bulletin(bp);
2714 
2715                 /* if bulletin board did not have an update for link status
2716                  * __bnx2x_link_report will report current status
2717                  * but it will NOT duplicate report in case of already reported
2718                  * during sampling bulletin board.
2719                  */
2720                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2721         }
2722 }
2723 
2724 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2725                                   u16 vlan_val, u8 allowed_prio)
2726 {
2727         struct bnx2x_func_state_params func_params = {NULL};
2728         struct bnx2x_func_afex_update_params *f_update_params =
2729                 &func_params.params.afex_update;
2730 
2731         func_params.f_obj = &bp->func_obj;
2732         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2733 
2734         /* no need to wait for RAMROD completion, so don't
2735          * set RAMROD_COMP_WAIT flag
2736          */
2737 
2738         f_update_params->vif_id = vifid;
2739         f_update_params->afex_default_vlan = vlan_val;
2740         f_update_params->allowed_priorities = allowed_prio;
2741 
2742         /* if ramrod can not be sent, response to MCP immediately */
2743         if (bnx2x_func_state_change(bp, &func_params) < 0)
2744                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2745 
2746         return 0;
2747 }
2748 
2749 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2750                                           u16 vif_index, u8 func_bit_map)
2751 {
2752         struct bnx2x_func_state_params func_params = {NULL};
2753         struct bnx2x_func_afex_viflists_params *update_params =
2754                 &func_params.params.afex_viflists;
2755         int rc;
2756         u32 drv_msg_code;
2757 
2758         /* validate only LIST_SET and LIST_GET are received from switch */
2759         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2760                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2761                           cmd_type);
2762 
2763         func_params.f_obj = &bp->func_obj;
2764         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2765 
2766         /* set parameters according to cmd_type */
2767         update_params->afex_vif_list_command = cmd_type;
2768         update_params->vif_list_index = vif_index;
2769         update_params->func_bit_map =
2770                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2771         update_params->func_to_clear = 0;
2772         drv_msg_code =
2773                 (cmd_type == VIF_LIST_RULE_GET) ?
2774                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2775                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2776 
2777         /* if ramrod can not be sent, respond to MCP immediately for
2778          * SET and GET requests (other are not triggered from MCP)
2779          */
2780         rc = bnx2x_func_state_change(bp, &func_params);
2781         if (rc < 0)
2782                 bnx2x_fw_command(bp, drv_msg_code, 0);
2783 
2784         return 0;
2785 }
2786 
2787 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2788 {
2789         struct afex_stats afex_stats;
2790         u32 func = BP_ABS_FUNC(bp);
2791         u32 mf_config;
2792         u16 vlan_val;
2793         u32 vlan_prio;
2794         u16 vif_id;
2795         u8 allowed_prio;
2796         u8 vlan_mode;
2797         u32 addr_to_write, vifid, addrs, stats_type, i;
2798 
2799         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2800                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2801                 DP(BNX2X_MSG_MCP,
2802                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2803                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2804         }
2805 
2806         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2807                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2808                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2809                 DP(BNX2X_MSG_MCP,
2810                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2811                    vifid, addrs);
2812                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2813                                                addrs);
2814         }
2815 
2816         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2817                 addr_to_write = SHMEM2_RD(bp,
2818                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2819                 stats_type = SHMEM2_RD(bp,
2820                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2821 
2822                 DP(BNX2X_MSG_MCP,
2823                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2824                    addr_to_write);
2825 
2826                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2827 
2828                 /* write response to scratchpad, for MCP */
2829                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2830                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2831                                *(((u32 *)(&afex_stats))+i));
2832 
2833                 /* send ack message to MCP */
2834                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2835         }
2836 
2837         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2838                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2839                 bp->mf_config[BP_VN(bp)] = mf_config;
2840                 DP(BNX2X_MSG_MCP,
2841                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2842                    mf_config);
2843 
2844                 /* if VIF_SET is "enabled" */
2845                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2846                         /* set rate limit directly to internal RAM */
2847                         struct cmng_init_input cmng_input;
2848                         struct rate_shaping_vars_per_vn m_rs_vn;
2849                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2850                         u32 addr = BAR_XSTRORM_INTMEM +
2851                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2852 
2853                         bp->mf_config[BP_VN(bp)] = mf_config;
2854 
2855                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2856                         m_rs_vn.vn_counter.rate =
2857                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2858                         m_rs_vn.vn_counter.quota =
2859                                 (m_rs_vn.vn_counter.rate *
2860                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2861 
2862                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2863 
2864                         /* read relevant values from mf_cfg struct in shmem */
2865                         vif_id =
2866                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2867                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2868                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2869                         vlan_val =
2870                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2871                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2872                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2873                         vlan_prio = (mf_config &
2874                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2875                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2876                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2877                         vlan_mode =
2878                                 (MF_CFG_RD(bp,
2879                                            func_mf_config[func].afex_config) &
2880                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2881                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2882                         allowed_prio =
2883                                 (MF_CFG_RD(bp,
2884                                            func_mf_config[func].afex_config) &
2885                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2886                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2887 
2888                         /* send ramrod to FW, return in case of failure */
2889                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2890                                                    allowed_prio))
2891                                 return;
2892 
2893                         bp->afex_def_vlan_tag = vlan_val;
2894                         bp->afex_vlan_mode = vlan_mode;
2895                 } else {
2896                         /* notify link down because BP->flags is disabled */
2897                         bnx2x_link_report(bp);
2898 
2899                         /* send INVALID VIF ramrod to FW */
2900                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2901 
2902                         /* Reset the default afex VLAN */
2903                         bp->afex_def_vlan_tag = -1;
2904                 }
2905         }
2906 }
2907 
2908 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2909 {
2910         struct bnx2x_func_switch_update_params *switch_update_params;
2911         struct bnx2x_func_state_params func_params;
2912 
2913         memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2914         switch_update_params = &func_params.params.switch_update;
2915         func_params.f_obj = &bp->func_obj;
2916         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2917 
2918         if (IS_MF_UFP(bp)) {
2919                 int func = BP_ABS_FUNC(bp);
2920                 u32 val;
2921 
2922                 /* Re-learn the S-tag from shmem */
2923                 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2924                                 FUNC_MF_CFG_E1HOV_TAG_MASK;
2925                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2926                         bp->mf_ov = val;
2927                 } else {
2928                         BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2929                         goto fail;
2930                 }
2931 
2932                 /* Configure new S-tag in LLH */
2933                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2934                        bp->mf_ov);
2935 
2936                 /* Send Ramrod to update FW of change */
2937                 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2938                           &switch_update_params->changes);
2939                 switch_update_params->vlan = bp->mf_ov;
2940 
2941                 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2942                         BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2943                                   bp->mf_ov);
2944                         goto fail;
2945                 }
2946 
2947                 DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n", bp->mf_ov);
2948 
2949                 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2950 
2951                 return;
2952         }
2953 
2954         /* not supported by SW yet */
2955 fail:
2956         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2957 }
2958 
2959 static void bnx2x_pmf_update(struct bnx2x *bp)
2960 {
2961         int port = BP_PORT(bp);
2962         u32 val;
2963 
2964         bp->port.pmf = 1;
2965         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2966 
2967         /*
2968          * We need the mb() to ensure the ordering between the writing to
2969          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2970          */
2971         smp_mb();
2972 
2973         /* queue a periodic task */
2974         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2975 
2976         bnx2x_dcbx_pmf_update(bp);
2977 
2978         /* enable nig attention */
2979         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2980         if (bp->common.int_block == INT_BLOCK_HC) {
2981                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2982                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2983         } else if (!CHIP_IS_E1x(bp)) {
2984                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2985                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2986         }
2987 
2988         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2989 }
2990 
2991 /* end of Link */
2992 
2993 /* slow path */
2994 
2995 /*
2996  * General service functions
2997  */
2998 
2999 /* send the MCP a request, block until there is a reply */
3000 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
3001 {
3002         int mb_idx = BP_FW_MB_IDX(bp);
3003         u32 seq;
3004         u32 rc = 0;
3005         u32 cnt = 1;
3006         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3007 
3008         mutex_lock(&bp->fw_mb_mutex);
3009         seq = ++bp->fw_seq;
3010         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3011         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3012 
3013         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3014                         (command | seq), param);
3015 
3016         do {
3017                 /* let the FW do it's magic ... */
3018                 msleep(delay);
3019 
3020                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
3021 
3022                 /* Give the FW up to 5 second (500*10ms) */
3023         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
3024 
3025         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3026            cnt*delay, rc, seq);
3027 
3028         /* is this a reply to our command? */
3029         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3030                 rc &= FW_MSG_CODE_MASK;
3031         else {
3032                 /* FW BUG! */
3033                 BNX2X_ERR("FW failed to respond!\n");
3034                 bnx2x_fw_dump(bp);
3035                 rc = 0;
3036         }
3037         mutex_unlock(&bp->fw_mb_mutex);
3038 
3039         return rc;
3040 }
3041 
3042 static void storm_memset_func_cfg(struct bnx2x *bp,
3043                                  struct tstorm_eth_function_common_config *tcfg,
3044                                  u16 abs_fid)
3045 {
3046         size_t size = sizeof(struct tstorm_eth_function_common_config);
3047 
3048         u32 addr = BAR_TSTRORM_INTMEM +
3049                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3050 
3051         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3052 }
3053 
3054 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3055 {
3056         if (CHIP_IS_E1x(bp)) {
3057                 struct tstorm_eth_function_common_config tcfg = {0};
3058 
3059                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3060         }
3061 
3062         /* Enable the function in the FW */
3063         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3064         storm_memset_func_en(bp, p->func_id, 1);
3065 
3066         /* spq */
3067         if (p->func_flgs & FUNC_FLG_SPQ) {
3068                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3069                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3070                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3071         }
3072 }
3073 
3074 /**
3075  * bnx2x_get_common_flags - Return common flags
3076  *
3077  * @bp          device handle
3078  * @fp          queue handle
3079  * @zero_stats  TRUE if statistics zeroing is needed
3080  *
3081  * Return the flags that are common for the Tx-only and not normal connections.
3082  */
3083 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3084                                             struct bnx2x_fastpath *fp,
3085                                             bool zero_stats)
3086 {
3087         unsigned long flags = 0;
3088 
3089         /* PF driver will always initialize the Queue to an ACTIVE state */
3090         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3091 
3092         /* tx only connections collect statistics (on the same index as the
3093          * parent connection). The statistics are zeroed when the parent
3094          * connection is initialized.
3095          */
3096 
3097         __set_bit(BNX2X_Q_FLG_STATS, &flags);
3098         if (zero_stats)
3099                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3100 
3101         if (bp->flags & TX_SWITCHING)
3102                 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3103 
3104         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3105         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3106 
3107 #ifdef BNX2X_STOP_ON_ERROR
3108         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3109 #endif
3110 
3111         return flags;
3112 }
3113 
3114 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3115                                        struct bnx2x_fastpath *fp,
3116                                        bool leading)
3117 {
3118         unsigned long flags = 0;
3119 
3120         /* calculate other queue flags */
3121         if (IS_MF_SD(bp))
3122                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3123 
3124         if (IS_FCOE_FP(fp)) {
3125                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3126                 /* For FCoE - force usage of default priority (for afex) */
3127                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3128         }
3129 
3130         if (!fp->disable_tpa) {
3131                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3132                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3133                 if (fp->mode == TPA_MODE_GRO)
3134                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3135         }
3136 
3137         if (leading) {
3138                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3139                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3140         }
3141 
3142         /* Always set HW VLAN stripping */
3143         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3144 
3145         /* configure silent vlan removal */
3146         if (IS_MF_AFEX(bp))
3147                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3148 
3149         return flags | bnx2x_get_common_flags(bp, fp, true);
3150 }
3151 
3152 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3153         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3154         u8 cos)
3155 {
3156         gen_init->stat_id = bnx2x_stats_id(fp);
3157         gen_init->spcl_id = fp->cl_id;
3158 
3159         /* Always use mini-jumbo MTU for FCoE L2 ring */
3160         if (IS_FCOE_FP(fp))
3161                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3162         else
3163                 gen_init->mtu = bp->dev->mtu;
3164 
3165         gen_init->cos = cos;
3166 }
3167 
3168 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3169         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3170         struct bnx2x_rxq_setup_params *rxq_init)
3171 {
3172         u8 max_sge = 0;
3173         u16 sge_sz = 0;
3174         u16 tpa_agg_size = 0;
3175 
3176         if (!fp->disable_tpa) {
3177                 pause->sge_th_lo = SGE_TH_LO(bp);
3178                 pause->sge_th_hi = SGE_TH_HI(bp);
3179 
3180                 /* validate SGE ring has enough to cross high threshold */
3181                 WARN_ON(bp->dropless_fc &&
3182                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3183                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3184 
3185                 tpa_agg_size = TPA_AGG_SIZE;
3186                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3187                         SGE_PAGE_SHIFT;
3188                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3189                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3190                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3191         }
3192 
3193         /* pause - not for e1 */
3194         if (!CHIP_IS_E1(bp)) {
3195                 pause->bd_th_lo = BD_TH_LO(bp);
3196                 pause->bd_th_hi = BD_TH_HI(bp);
3197 
3198                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3199                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3200                 /*
3201                  * validate that rings have enough entries to cross
3202                  * high thresholds
3203                  */
3204                 WARN_ON(bp->dropless_fc &&
3205                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3206                                 bp->rx_ring_size);
3207                 WARN_ON(bp->dropless_fc &&
3208                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3209                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3210 
3211                 pause->pri_map = 1;
3212         }
3213 
3214         /* rxq setup */
3215         rxq_init->dscr_map = fp->rx_desc_mapping;
3216         rxq_init->sge_map = fp->rx_sge_mapping;
3217         rxq_init->rcq_map = fp->rx_comp_mapping;
3218         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3219 
3220         /* This should be a maximum number of data bytes that may be
3221          * placed on the BD (not including paddings).
3222          */
3223         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3224                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3225 
3226         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3227         rxq_init->tpa_agg_sz = tpa_agg_size;
3228         rxq_init->sge_buf_sz = sge_sz;
3229         rxq_init->max_sges_pkt = max_sge;
3230         rxq_init->rss_engine_id = BP_FUNC(bp);
3231         rxq_init->mcast_engine_id = BP_FUNC(bp);
3232 
3233         /* Maximum number or simultaneous TPA aggregation for this Queue.
3234          *
3235          * For PF Clients it should be the maximum available number.
3236          * VF driver(s) may want to define it to a smaller value.
3237          */
3238         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3239 
3240         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3241         rxq_init->fw_sb_id = fp->fw_sb_id;
3242 
3243         if (IS_FCOE_FP(fp))
3244                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3245         else
3246                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3247         /* configure silent vlan removal
3248          * if multi function mode is afex, then mask default vlan
3249          */
3250         if (IS_MF_AFEX(bp)) {
3251                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3252                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3253         }
3254 }
3255 
3256 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3257         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3258         u8 cos)
3259 {
3260         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3261         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3262         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3263         txq_init->fw_sb_id = fp->fw_sb_id;
3264 
3265         /*
3266          * set the tss leading client id for TX classification ==
3267          * leading RSS client id
3268          */
3269         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3270 
3271         if (IS_FCOE_FP(fp)) {
3272                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3273                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3274         }
3275 }
3276 
3277 static void bnx2x_pf_init(struct bnx2x *bp)
3278 {
3279         struct bnx2x_func_init_params func_init = {0};
3280         struct event_ring_data eq_data = { {0} };
3281         u16 flags;
3282 
3283         if (!CHIP_IS_E1x(bp)) {
3284                 /* reset IGU PF statistics: MSIX + ATTN */
3285                 /* PF */
3286                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3287                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3288                            (CHIP_MODE_IS_4_PORT(bp) ?
3289                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3290                 /* ATTN */
3291                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3292                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3293                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3294                            (CHIP_MODE_IS_4_PORT(bp) ?
3295                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3296         }
3297 
3298         /* function setup flags */
3299         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3300 
3301         /* This flag is relevant for E1x only.
3302          * E2 doesn't have a TPA configuration in a function level.
3303          */
3304         flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3305 
3306         func_init.func_flgs = flags;
3307         func_init.pf_id = BP_FUNC(bp);
3308         func_init.func_id = BP_FUNC(bp);
3309         func_init.spq_map = bp->spq_mapping;
3310         func_init.spq_prod = bp->spq_prod_idx;
3311 
3312         bnx2x_func_init(bp, &func_init);
3313 
3314         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3315 
3316         /*
3317          * Congestion management values depend on the link rate
3318          * There is no active link so initial link rate is set to 10 Gbps.
3319          * When the link comes up The congestion management values are
3320          * re-calculated according to the actual link rate.
3321          */
3322         bp->link_vars.line_speed = SPEED_10000;
3323         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3324 
3325         /* Only the PMF sets the HW */
3326         if (bp->port.pmf)
3327                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3328 
3329         /* init Event Queue - PCI bus guarantees correct endianity*/
3330         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3331         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3332         eq_data.producer = bp->eq_prod;
3333         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3334         eq_data.sb_id = DEF_SB_ID;
3335         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3336 }
3337 
3338 static void bnx2x_e1h_disable(struct bnx2x *bp)
3339 {
3340         int port = BP_PORT(bp);
3341 
3342         bnx2x_tx_disable(bp);
3343 
3344         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3345 }
3346 
3347 static void bnx2x_e1h_enable(struct bnx2x *bp)
3348 {
3349         int port = BP_PORT(bp);
3350 
3351         if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3352                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3353 
3354         /* Tx queue should be only re-enabled */
3355         netif_tx_wake_all_queues(bp->dev);
3356 
3357         /*
3358          * Should not call netif_carrier_on since it will be called if the link
3359          * is up when checking for link state
3360          */
3361 }
3362 
3363 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3364 
3365 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3366 {
3367         struct eth_stats_info *ether_stat =
3368                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3369         struct bnx2x_vlan_mac_obj *mac_obj =
3370                 &bp->sp_objs->mac_obj;
3371         int i;
3372 
3373         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3374                 ETH_STAT_INFO_VERSION_LEN);
3375 
3376         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3377          * mac_local field in ether_stat struct. The base address is offset by 2
3378          * bytes to account for the field being 8 bytes but a mac address is
3379          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3380          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3381          * allocated by the ether_stat struct, so the macs will land in their
3382          * proper positions.
3383          */
3384         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3385                 memset(ether_stat->mac_local + i, 0,
3386                        sizeof(ether_stat->mac_local[0]));
3387         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3388                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3389                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3390                                 ETH_ALEN);
3391         ether_stat->mtu_size = bp->dev->mtu;
3392         if (bp->dev->features & NETIF_F_RXCSUM)
3393                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3394         if (bp->dev->features & NETIF_F_TSO)
3395                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3396         ether_stat->feature_flags |= bp->common.boot_mode;
3397 
3398         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3399 
3400         ether_stat->txq_size = bp->tx_ring_size;
3401         ether_stat->rxq_size = bp->rx_ring_size;
3402 
3403 #ifdef CONFIG_BNX2X_SRIOV
3404         ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3405 #endif
3406 }
3407 
3408 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3409 {
3410         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3411         struct fcoe_stats_info *fcoe_stat =
3412                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3413 
3414         if (!CNIC_LOADED(bp))
3415                 return;
3416 
3417         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3418 
3419         fcoe_stat->qos_priority =
3420                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3421 
3422         /* insert FCoE stats from ramrod response */
3423         if (!NO_FCOE(bp)) {
3424                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3425                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3426                         tstorm_queue_statistics;
3427 
3428                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3429                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3430                         xstorm_queue_statistics;
3431 
3432                 struct fcoe_statistics_params *fw_fcoe_stat =
3433                         &bp->fw_stats_data->fcoe;
3434 
3435                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3436                           fcoe_stat->rx_bytes_lo,
3437                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3438 
3439                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3440                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3441                           fcoe_stat->rx_bytes_lo,
3442                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3443 
3444                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3445                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3446                           fcoe_stat->rx_bytes_lo,
3447                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3448 
3449                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3450                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3451                           fcoe_stat->rx_bytes_lo,
3452                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3453 
3454                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3455                           fcoe_stat->rx_frames_lo,
3456                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3457 
3458                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3459                           fcoe_stat->rx_frames_lo,
3460                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3461 
3462                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3463                           fcoe_stat->rx_frames_lo,
3464                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3465 
3466                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3467                           fcoe_stat->rx_frames_lo,
3468                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3469 
3470                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3471                           fcoe_stat->tx_bytes_lo,
3472                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3473 
3474                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3475                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3476                           fcoe_stat->tx_bytes_lo,
3477                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3478 
3479                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3480                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3481                           fcoe_stat->tx_bytes_lo,
3482                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3483 
3484                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3485                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3486                           fcoe_stat->tx_bytes_lo,
3487                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3488 
3489                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3490                           fcoe_stat->tx_frames_lo,
3491                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3492 
3493                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3494                           fcoe_stat->tx_frames_lo,
3495                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3496 
3497                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3498                           fcoe_stat->tx_frames_lo,
3499                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3500 
3501                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3502                           fcoe_stat->tx_frames_lo,
3503                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3504         }
3505 
3506         /* ask L5 driver to add data to the struct */
3507         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3508 }
3509 
3510 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3511 {
3512         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3513         struct iscsi_stats_info *iscsi_stat =
3514                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3515 
3516         if (!CNIC_LOADED(bp))
3517                 return;
3518 
3519         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3520                ETH_ALEN);
3521 
3522         iscsi_stat->qos_priority =
3523                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3524 
3525         /* ask L5 driver to add data to the struct */
3526         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3527 }
3528 
3529 /* called due to MCP event (on pmf):
3530  *      reread new bandwidth configuration
3531  *      configure FW
3532  *      notify others function about the change
3533  */
3534 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3535 {
3536         if (bp->link_vars.link_up) {
3537                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3538                 bnx2x_link_sync_notify(bp);
3539         }
3540         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3541 }
3542 
3543 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3544 {
3545         bnx2x_config_mf_bw(bp);
3546         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3547 }
3548 
3549 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3550 {
3551         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3552         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3553 }
3554 
3555 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH        (20)
3556 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT         (25)
3557 
3558 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3559 {
3560         enum drv_info_opcode op_code;
3561         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3562         bool release = false;
3563         int wait;
3564 
3565         /* if drv_info version supported by MFW doesn't match - send NACK */
3566         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3567                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3568                 return;
3569         }
3570 
3571         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3572                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3573 
3574         /* Must prevent other flows from accessing drv_info_to_mcp */
3575         mutex_lock(&bp->drv_info_mutex);
3576 
3577         memset(&bp->slowpath->drv_info_to_mcp, 0,
3578                sizeof(union drv_info_to_mcp));
3579 
3580         switch (op_code) {
3581         case ETH_STATS_OPCODE:
3582                 bnx2x_drv_info_ether_stat(bp);
3583                 break;
3584         case FCOE_STATS_OPCODE:
3585                 bnx2x_drv_info_fcoe_stat(bp);
3586                 break;
3587         case ISCSI_STATS_OPCODE:
3588                 bnx2x_drv_info_iscsi_stat(bp);
3589                 break;
3590         default:
3591                 /* if op code isn't supported - send NACK */
3592                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3593                 goto out;
3594         }
3595 
3596         /* if we got drv_info attn from MFW then these fields are defined in
3597          * shmem2 for sure
3598          */
3599         SHMEM2_WR(bp, drv_info_host_addr_lo,
3600                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3601         SHMEM2_WR(bp, drv_info_host_addr_hi,
3602                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3603 
3604         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3605 
3606         /* Since possible management wants both this and get_driver_version
3607          * need to wait until management notifies us it finished utilizing
3608          * the buffer.
3609          */
3610         if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3611                 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3612         } else if (!bp->drv_info_mng_owner) {
3613                 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3614 
3615                 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3616                         u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3617 
3618                         /* Management is done; need to clear indication */
3619                         if (indication & bit) {
3620                                 SHMEM2_WR(bp, mfw_drv_indication,
3621                                           indication & ~bit);
3622                                 release = true;
3623                                 break;
3624                         }
3625 
3626                         msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3627                 }
3628         }
3629         if (!release) {
3630                 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3631                 bp->drv_info_mng_owner = true;
3632         }
3633 
3634 out:
3635         mutex_unlock(&bp->drv_info_mutex);
3636 }
3637 
3638 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3639 {
3640         u8 vals[4];
3641         int i = 0;
3642 
3643         if (bnx2x_format) {
3644                 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3645                            &vals[0], &vals[1], &vals[2], &vals[3]);
3646                 if (i > 0)
3647                         vals[0] -= '';
3648         } else {
3649                 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3650                            &vals[0], &vals[1], &vals[2], &vals[3]);
3651         }
3652 
3653         while (i < 4)
3654                 vals[i++] = 0;
3655 
3656         return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3657 }
3658 
3659 void bnx2x_update_mng_version(struct bnx2x *bp)
3660 {
3661         u32 iscsiver = DRV_VER_NOT_LOADED;
3662         u32 fcoever = DRV_VER_NOT_LOADED;
3663         u32 ethver = DRV_VER_NOT_LOADED;
3664         int idx = BP_FW_MB_IDX(bp);
3665         u8 *version;
3666 
3667         if (!SHMEM2_HAS(bp, func_os_drv_ver))
3668                 return;
3669 
3670         mutex_lock(&bp->drv_info_mutex);
3671         /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3672         if (bp->drv_info_mng_owner)
3673                 goto out;
3674 
3675         if (bp->state != BNX2X_STATE_OPEN)
3676                 goto out;
3677 
3678         /* Parse ethernet driver version */
3679         ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3680         if (!CNIC_LOADED(bp))
3681                 goto out;
3682 
3683         /* Try getting storage driver version via cnic */
3684         memset(&bp->slowpath->drv_info_to_mcp, 0,
3685                sizeof(union drv_info_to_mcp));
3686         bnx2x_drv_info_iscsi_stat(bp);
3687         version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3688         iscsiver = bnx2x_update_mng_version_utility(version, false);
3689 
3690         memset(&bp->slowpath->drv_info_to_mcp, 0,
3691                sizeof(union drv_info_to_mcp));
3692         bnx2x_drv_info_fcoe_stat(bp);
3693         version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3694         fcoever = bnx2x_update_mng_version_utility(version, false);
3695 
3696 out:
3697         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3698         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3699         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3700 
3701         mutex_unlock(&bp->drv_info_mutex);
3702 
3703         DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3704            ethver, iscsiver, fcoever);
3705 }
3706 
3707 static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
3708 {
3709         u32 cmd_ok, cmd_fail;
3710 
3711         /* sanity */
3712         if (event & DRV_STATUS_DCC_EVENT_MASK &&
3713             event & DRV_STATUS_OEM_EVENT_MASK) {
3714                 BNX2X_ERR("Received simultaneous events %08x\n", event);
3715                 return;
3716         }
3717 
3718         if (event & DRV_STATUS_DCC_EVENT_MASK) {
3719                 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3720                 cmd_ok = DRV_MSG_CODE_DCC_OK;
3721         } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3722                 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3723                 cmd_ok = DRV_MSG_CODE_OEM_OK;
3724         }
3725 
3726         DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3727 
3728         if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3729                      DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3730                 /* This is the only place besides the function initialization
3731                  * where the bp->flags can change so it is done without any
3732                  * locks
3733                  */
3734                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3735                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3736                         bp->flags |= MF_FUNC_DIS;
3737 
3738                         bnx2x_e1h_disable(bp);
3739                 } else {
3740                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3741                         bp->flags &= ~MF_FUNC_DIS;
3742 
3743                         bnx2x_e1h_enable(bp);
3744                 }
3745                 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3746                            DRV_STATUS_OEM_DISABLE_ENABLE_PF);
3747         }
3748 
3749         if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3750                      DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
3751                 bnx2x_config_mf_bw(bp);
3752                 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3753                            DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
3754         }
3755 
3756         /* Report results to MCP */
3757         if (event)
3758                 bnx2x_fw_command(bp, cmd_fail, 0);
3759         else
3760                 bnx2x_fw_command(bp, cmd_ok, 0);
3761 }
3762 
3763 /* must be called under the spq lock */
3764 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3765 {
3766         struct eth_spe *next_spe = bp->spq_prod_bd;
3767 
3768         if (bp->spq_prod_bd == bp->spq_last_bd) {
3769                 bp->spq_prod_bd = bp->spq;
3770                 bp->spq_prod_idx = 0;
3771                 DP(BNX2X_MSG_SP, "end of spq\n");
3772         } else {
3773                 bp->spq_prod_bd++;
3774                 bp->spq_prod_idx++;
3775         }
3776         return next_spe;
3777 }
3778 
3779 /* must be called under the spq lock */
3780 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3781 {
3782         int func = BP_FUNC(bp);
3783 
3784         /*
3785          * Make sure that BD data is updated before writing the producer:
3786          * BD data is written to the memory, the producer is read from the
3787          * memory, thus we need a full memory barrier to ensure the ordering.
3788          */
3789         mb();
3790 
3791         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3792                  bp->spq_prod_idx);
3793         mmiowb();
3794 }
3795 
3796 /**
3797  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3798  *
3799  * @cmd:        command to check
3800  * @cmd_type:   command type
3801  */
3802 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3803 {
3804         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3805             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3806             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3807             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3808             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3809             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3810             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3811                 return true;
3812         else
3813                 return false;
3814 }
3815 
3816 /**
3817  * bnx2x_sp_post - place a single command on an SP ring
3818  *
3819  * @bp:         driver handle
3820  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3821  * @cid:        SW CID the command is related to
3822  * @data_hi:    command private data address (high 32 bits)
3823  * @data_lo:    command private data address (low 32 bits)
3824  * @cmd_type:   command type (e.g. NONE, ETH)
3825  *
3826  * SP data is handled as if it's always an address pair, thus data fields are
3827  * not swapped to little endian in upper functions. Instead this function swaps
3828  * data as if it's two u32 fields.
3829  */
3830 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3831                   u32 data_hi, u32 data_lo, int cmd_type)
3832 {
3833         struct eth_spe *spe;
3834         u16 type;
3835         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3836 
3837 #ifdef BNX2X_STOP_ON_ERROR
3838         if (unlikely(bp->panic)) {
3839                 BNX2X_ERR("Can't post SP when there is panic\n");
3840                 return -EIO;
3841         }
3842 #endif
3843 
3844         spin_lock_bh(&bp->spq_lock);
3845 
3846         if (common) {
3847                 if (!atomic_read(&bp->eq_spq_left)) {
3848                         BNX2X_ERR("BUG! EQ ring full!\n");
3849                         spin_unlock_bh(&bp->spq_lock);
3850                         bnx2x_panic();
3851                         return -EBUSY;
3852                 }
3853         } else if (!atomic_read(&bp->cq_spq_left)) {
3854                         BNX2X_ERR("BUG! SPQ ring full!\n");
3855                         spin_unlock_bh(&bp->spq_lock);
3856                         bnx2x_panic();
3857                         return -EBUSY;
3858         }
3859 
3860         spe = bnx2x_sp_get_next(bp);
3861 
3862         /* CID needs port number to be encoded int it */
3863         spe->hdr.conn_and_cmd_data =
3864                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3865                                     HW_CID(bp, cid));
3866 
3867         /* In some cases, type may already contain the func-id
3868          * mainly in SRIOV related use cases, so we add it here only
3869          * if it's not already set.
3870          */
3871         if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3872                 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3873                         SPE_HDR_CONN_TYPE;
3874                 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3875                          SPE_HDR_FUNCTION_ID);
3876         } else {
3877                 type = cmd_type;
3878         }
3879 
3880         spe->hdr.type = cpu_to_le16(type);
3881 
3882         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3883         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3884 
3885         /*
3886          * It's ok if the actual decrement is issued towards the memory
3887          * somewhere between the spin_lock and spin_unlock. Thus no
3888          * more explicit memory barrier is needed.
3889          */
3890         if (common)
3891                 atomic_dec(&bp->eq_spq_left);
3892         else
3893                 atomic_dec(&bp->cq_spq_left);
3894 
3895         DP(BNX2X_MSG_SP,
3896            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3897            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3898            (u32)(U64_LO(bp->spq_mapping) +
3899            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3900            HW_CID(bp, cid), data_hi, data_lo, type,
3901            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3902 
3903         bnx2x_sp_prod_update(bp);
3904         spin_unlock_bh(&bp->spq_lock);
3905         return 0;
3906 }
3907 
3908 /* acquire split MCP access lock register */
3909 static int bnx2x_acquire_alr(struct bnx2x *bp)
3910 {
3911         u32 j, val;
3912         int rc = 0;
3913 
3914         might_sleep();
3915         for (j = 0; j < 1000; j++) {
3916                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3917                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3918                 if (val & MCPR_ACCESS_LOCK_LOCK)
3919                         break;
3920 
3921                 usleep_range(5000, 10000);
3922         }
3923         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3924                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3925                 rc = -EBUSY;
3926         }
3927 
3928         return rc;
3929 }
3930 
3931 /* release split MCP access lock register */
3932 static void bnx2x_release_alr(struct bnx2x *bp)
3933 {
3934         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3935 }
3936 
3937 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3938 #define BNX2X_DEF_SB_IDX        0x0002
3939 
3940 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3941 {
3942         struct host_sp_status_block *def_sb = bp->def_status_blk;
3943         u16 rc = 0;
3944 
3945         barrier(); /* status block is written to by the chip */
3946         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3947                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3948                 rc |= BNX2X_DEF_SB_ATT_IDX;
3949         }
3950 
3951         if (bp->def_idx != def_sb->sp_sb.running_index) {
3952                 bp->def_idx = def_sb->sp_sb.running_index;
3953                 rc |= BNX2X_DEF_SB_IDX;
3954         }
3955 
3956         /* Do not reorder: indices reading should complete before handling */
3957         barrier();
3958         return rc;
3959 }
3960 
3961 /*
3962  * slow path service functions
3963  */
3964 
3965 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3966 {
3967         int port = BP_PORT(bp);
3968         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3969                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3970         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3971                                        NIG_REG_MASK_INTERRUPT_PORT0;
3972         u32 aeu_mask;
3973         u32 nig_mask = 0;
3974         u32 reg_addr;
3975 
3976         if (bp->attn_state & asserted)
3977                 BNX2X_ERR("IGU ERROR\n");
3978 
3979         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3980         aeu_mask = REG_RD(bp, aeu_addr);
3981 
3982         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
3983            aeu_mask, asserted);
3984         aeu_mask &= ~(asserted & 0x3ff);
3985         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3986 
3987         REG_WR(bp, aeu_addr, aeu_mask);
3988         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3989 
3990         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3991         bp->attn_state |= asserted;
3992         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3993 
3994         if (asserted & ATTN_HARD_WIRED_MASK) {
3995                 if (asserted & ATTN_NIG_FOR_FUNC) {
3996 
3997                         bnx2x_acquire_phy_lock(bp);
3998 
3999                         /* save nig interrupt mask */
4000                         nig_mask = REG_RD(bp, nig_int_mask_addr);
4001 
4002                         /* If nig_mask is not set, no need to call the update
4003                          * function.
4004                          */
4005                         if (nig_mask) {
4006                                 REG_WR(bp, nig_int_mask_addr, 0);
4007 
4008                                 bnx2x_link_attn(bp);
4009                         }
4010 
4011                         /* handle unicore attn? */
4012                 }
4013                 if (asserted & ATTN_SW_TIMER_4_FUNC)
4014                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4015 
4016                 if (asserted & GPIO_2_FUNC)
4017                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4018 
4019                 if (asserted & GPIO_3_FUNC)
4020                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4021 
4022                 if (asserted & GPIO_4_FUNC)
4023                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4024 
4025                 if (port == 0) {
4026                         if (asserted & ATTN_GENERAL_ATTN_1) {
4027                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4028                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4029                         }
4030                         if (asserted & ATTN_GENERAL_ATTN_2) {
4031                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4032                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4033                         }
4034                         if (asserted & ATTN_GENERAL_ATTN_3) {
4035                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4036                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4037                         }
4038                 } else {
4039                         if (asserted & ATTN_GENERAL_ATTN_4) {
4040                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4041                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4042                         }
4043                         if (asserted & ATTN_GENERAL_ATTN_5) {
4044                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4045                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4046                         }
4047                         if (asserted & ATTN_GENERAL_ATTN_6) {
4048                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4049                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4050                         }
4051                 }
4052 
4053         } /* if hardwired */
4054 
4055         if (bp->common.int_block == INT_BLOCK_HC)
4056                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4057                             COMMAND_REG_ATTN_BITS_SET);
4058         else
4059                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4060 
4061         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4062            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4063         REG_WR(bp, reg_addr, asserted);
4064 
4065         /* now set back the mask */
4066         if (asserted & ATTN_NIG_FOR_FUNC) {
4067                 /* Verify that IGU ack through BAR was written before restoring
4068                  * NIG mask. This loop should exit after 2-3 iterations max.
4069                  */
4070                 if (bp->common.int_block != INT_BLOCK_HC) {
4071                         u32 cnt = 0, igu_acked;
4072                         do {
4073                                 igu_acked = REG_RD(bp,
4074                                                    IGU_REG_ATTENTION_ACK_BITS);
4075                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4076                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
4077                         if (!igu_acked)
4078                                 DP(NETIF_MSG_HW,
4079                                    "Failed to verify IGU ack on time\n");
4080                         barrier();
4081                 }
4082                 REG_WR(bp, nig_int_mask_addr, nig_mask);
4083                 bnx2x_release_phy_lock(bp);
4084         }
4085 }
4086 
4087 static void bnx2x_fan_failure(struct bnx2x *bp)
4088 {
4089         int port = BP_PORT(bp);
4090         u32 ext_phy_config;
4091         /* mark the failure */
4092         ext_phy_config =
4093                 SHMEM_RD(bp,
4094                          dev_info.port_hw_config[port].external_phy_config);
4095 
4096         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4097         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4098         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4099                  ext_phy_config);
4100 
4101         /* log the failure */
4102         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4103                             "Please contact OEM Support for assistance\n");
4104 
4105         /* Schedule device reset (unload)
4106          * This is due to some boards consuming sufficient power when driver is
4107          * up to overheat if fan fails.
4108          */
4109         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4110 }
4111 
4112 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4113 {
4114         int port = BP_PORT(bp);
4115         int reg_offset;
4116         u32 val;
4117 
4118         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4119                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4120 
4121         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4122 
4123                 val = REG_RD(bp, reg_offset);
4124                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4125                 REG_WR(bp, reg_offset, val);
4126 
4127                 BNX2X_ERR("SPIO5 hw attention\n");
4128 
4129                 /* Fan failure attention */
4130                 bnx2x_hw_reset_phy(&bp->link_params);
4131                 bnx2x_fan_failure(bp);
4132         }
4133 
4134         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4135                 bnx2x_acquire_phy_lock(bp);
4136                 bnx2x_handle_module_detect_int(&bp->link_params);
4137                 bnx2x_release_phy_lock(bp);
4138         }
4139 
4140         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4141 
4142                 val = REG_RD(bp, reg_offset);
4143                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4144                 REG_WR(bp, reg_offset, val);
4145 
4146                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4147                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
4148                 bnx2x_panic();
4149         }
4150 }
4151 
4152 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4153 {
4154         u32 val;
4155 
4156         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4157 
4158                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4159                 BNX2X_ERR("DB hw attention 0x%x\n", val);
4160                 /* DORQ discard attention */
4161                 if (val & 0x2)
4162                         BNX2X_ERR("FATAL error from DORQ\n");
4163         }
4164 
4165         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4166 
4167                 int port = BP_PORT(bp);
4168                 int reg_offset;
4169 
4170                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4171                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4172 
4173                 val = REG_RD(bp, reg_offset);
4174                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4175                 REG_WR(bp, reg_offset, val);
4176 
4177                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4178                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
4179                 bnx2x_panic();
4180         }
4181 }
4182 
4183 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4184 {
4185         u32 val;
4186 
4187         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4188 
4189                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4190                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4191                 /* CFC error attention */
4192                 if (val & 0x2)
4193                         BNX2X_ERR("FATAL error from CFC\n");
4194         }
4195 
4196         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4197                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4198                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4199                 /* RQ_USDMDP_FIFO_OVERFLOW */
4200                 if (val & 0x18000)
4201                         BNX2X_ERR("FATAL error from PXP\n");
4202 
4203                 if (!CHIP_IS_E1x(bp)) {
4204                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4205                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4206                 }
4207         }
4208 
4209         if (attn & HW_INTERRUT_ASSERT_SET_2) {
4210 
4211                 int port = BP_PORT(bp);
4212                 int reg_offset;
4213 
4214                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4215                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4216 
4217                 val = REG_RD(bp, reg_offset);
4218                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4219                 REG_WR(bp, reg_offset, val);
4220 
4221                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4222                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
4223                 bnx2x_panic();
4224         }
4225 }
4226 
4227 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4228 {
4229         u32 val;
4230 
4231         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4232 
4233                 if (attn & BNX2X_PMF_LINK_ASSERT) {
4234                         int func = BP_FUNC(bp);
4235 
4236                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4237                         bnx2x_read_mf_cfg(bp);
4238                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4239                                         func_mf_config[BP_ABS_FUNC(bp)].config);
4240                         val = SHMEM_RD(bp,
4241                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
4242 
4243                         if (val & (DRV_STATUS_DCC_EVENT_MASK |
4244                                    DRV_STATUS_OEM_EVENT_MASK))
4245                                 bnx2x_oem_event(bp,
4246                                         (val & (DRV_STATUS_DCC_EVENT_MASK |
4247                                                 DRV_STATUS_OEM_EVENT_MASK)));
4248 
4249                         if (val & DRV_STATUS_SET_MF_BW)
4250                                 bnx2x_set_mf_bw(bp);
4251 
4252                         if (val & DRV_STATUS_DRV_INFO_REQ)
4253                                 bnx2x_handle_drv_info_req(bp);
4254 
4255                         if (val & DRV_STATUS_VF_DISABLED)
4256                                 bnx2x_schedule_iov_task(bp,
4257                                                         BNX2X_IOV_HANDLE_FLR);
4258 
4259                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4260                                 bnx2x_pmf_update(bp);
4261 
4262                         if (bp->port.pmf &&
4263                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4264                                 bp->dcbx_enabled > 0)
4265                                 /* start dcbx state machine */
4266                                 bnx2x_dcbx_set_params(bp,
4267                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4268                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4269                                 bnx2x_handle_afex_cmd(bp,
4270                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4271                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4272                                 bnx2x_handle_eee_event(bp);
4273 
4274                         if (val & DRV_STATUS_OEM_UPDATE_SVID)
4275                                 bnx2x_handle_update_svid_cmd(bp);
4276 
4277                         if (bp->link_vars.periodic_flags &
4278                             PERIODIC_FLAGS_LINK_EVENT) {
4279                                 /*  sync with link */
4280                                 bnx2x_acquire_phy_lock(bp);
4281                                 bp->link_vars.periodic_flags &=
4282                                         ~PERIODIC_FLAGS_LINK_EVENT;
4283                                 bnx2x_release_phy_lock(bp);
4284                                 if (IS_MF(bp))
4285                                         bnx2x_link_sync_notify(bp);
4286                                 bnx2x_link_report(bp);
4287                         }
4288                         /* Always call it here: bnx2x_link_report() will
4289                          * prevent the link indication duplication.
4290                          */
4291                         bnx2x__link_status_update(bp);
4292                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4293 
4294                         BNX2X_ERR("MC assert!\n");
4295                         bnx2x_mc_assert(bp);
4296                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4297                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4298                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4299                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4300                         bnx2x_panic();
4301 
4302                 } else if (attn & BNX2X_MCP_ASSERT) {
4303 
4304                         BNX2X_ERR("MCP assert!\n");
4305                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4306                         bnx2x_fw_dump(bp);
4307 
4308                 } else
4309                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4310         }
4311 
4312         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4313                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4314                 if (attn & BNX2X_GRC_TIMEOUT) {
4315                         val = CHIP_IS_E1(bp) ? 0 :
4316                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4317                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4318                 }
4319                 if (attn & BNX2X_GRC_RSV) {
4320                         val = CHIP_IS_E1(bp) ? 0 :
4321                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4322                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4323                 }
4324                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4325         }
4326 }
4327 
4328 /*
4329  * Bits map:
4330  * 0-7   - Engine0 load counter.
4331  * 8-15  - Engine1 load counter.
4332  * 16    - Engine0 RESET_IN_PROGRESS bit.
4333  * 17    - Engine1 RESET_IN_PROGRESS bit.
4334  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4335  *         on the engine
4336  * 19    - Engine1 ONE_IS_LOADED.
4337  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4338  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4339  *         just the one belonging to its engine).
4340  *
4341  */
4342 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4343 
4344 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4345 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4346 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4347 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4348 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4349 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4350 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4351 
4352 /*
4353  * Set the GLOBAL_RESET bit.
4354  *
4355  * Should be run under rtnl lock
4356  */
4357 void bnx2x_set_reset_global(struct bnx2x *bp)
4358 {
4359         u32 val;
4360         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4361         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4362         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4363         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4364 }
4365 
4366 /*
4367  * Clear the GLOBAL_RESET bit.
4368  *
4369  * Should be run under rtnl lock
4370  */
4371 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4372 {
4373         u32 val;
4374         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4375         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4376         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4377         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4378 }
4379 
4380 /*
4381  * Checks the GLOBAL_RESET bit.
4382  *
4383  * should be run under rtnl lock
4384  */
4385 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4386 {
4387         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4388 
4389         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4390         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4391 }
4392 
4393 /*
4394  * Clear RESET_IN_PROGRESS bit for the current engine.
4395  *
4396  * Should be run under rtnl lock
4397  */
4398 static void bnx2x_set_reset_done(struct bnx2x *bp)
4399 {
4400         u32 val;
4401         u32 bit = BP_PATH(bp) ?
4402                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4403         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4404         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4405 
4406         /* Clear the bit */
4407         val &= ~bit;
4408         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4409 
4410         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4411 }
4412 
4413 /*
4414  * Set RESET_IN_PROGRESS for the current engine.
4415  *
4416  * should be run under rtnl lock
4417  */
4418 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4419 {
4420         u32 val;
4421         u32 bit = BP_PATH(bp) ?
4422                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4423         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4424         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4425 
4426         /* Set the bit */
4427         val |= bit;
4428         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4429         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4430 }
4431 
4432 /*
4433  * Checks the RESET_IN_PROGRESS bit for the given engine.
4434  * should be run under rtnl lock
4435  */
4436 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4437 {
4438         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4439         u32 bit = engine ?
4440                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4441 
4442         /* return false if bit is set */
4443         return (val & bit) ? false : true;
4444 }
4445 
4446 /*
4447  * set pf load for the current pf.
4448  *
4449  * should be run under rtnl lock
4450  */
4451 void bnx2x_set_pf_load(struct bnx2x *bp)
4452 {
4453         u32 val1, val;
4454         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4455                              BNX2X_PATH0_LOAD_CNT_MASK;
4456         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4457                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4458 
4459         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4460         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4461 
4462         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4463 
4464         /* get the current counter value */
4465         val1 = (val & mask) >> shift;
4466 
4467         /* set bit of that PF */
4468         val1 |= (1 << bp->pf_num);
4469 
4470         /* clear the old value */
4471         val &= ~mask;
4472 
4473         /* set the new one */
4474         val |= ((val1 << shift) & mask);
4475 
4476         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4477         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4478 }
4479 
4480 /**
4481  * bnx2x_clear_pf_load - clear pf load mark
4482  *
4483  * @bp:         driver handle
4484  *
4485  * Should be run under rtnl lock.
4486  * Decrements the load counter for the current engine. Returns
4487  * whether other functions are still loaded
4488  */
4489 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4490 {
4491         u32 val1, val;
4492         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4493                              BNX2X_PATH0_LOAD_CNT_MASK;
4494         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4495                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4496 
4497         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4498         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4499         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4500 
4501         /* get the current counter value */
4502         val1 = (val & mask) >> shift;
4503 
4504         /* clear bit of that PF */
4505         val1 &= ~(1 << bp->pf_num);
4506 
4507         /* clear the old value */
4508         val &= ~mask;
4509 
4510         /* set the new one */
4511         val |= ((val1 << shift) & mask);
4512 
4513         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4514         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4515         return val1 != 0;
4516 }
4517 
4518 /*
4519  * Read the load status for the current engine.
4520  *
4521  * should be run under rtnl lock
4522  */
4523 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4524 {
4525         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4526                              BNX2X_PATH0_LOAD_CNT_MASK);
4527         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4528                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4529         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4530 
4531         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4532 
4533         val = (val & mask) >> shift;
4534 
4535         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4536            engine, val);
4537 
4538         return val != 0;
4539 }
4540 
4541 static void _print_parity(struct bnx2x *bp, u32 reg)
4542 {
4543         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4544 }
4545 
4546 static void _print_next_block(int idx, const char *blk)
4547 {
4548         pr_cont("%s%s", idx ? ", " : "", blk);
4549 }
4550 
4551 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4552                                             int *par_num, bool print)
4553 {
4554         u32 cur_bit;
4555         bool res;
4556         int i;
4557 
4558         res = false;
4559 
4560         for (i = 0; sig; i++) {
4561                 cur_bit = (0x1UL << i);
4562                 if (sig & cur_bit) {
4563                         res |= true; /* Each bit is real error! */
4564 
4565                         if (print) {
4566                                 switch (cur_bit) {
4567                                 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4568                                         _print_next_block((*par_num)++, "BRB");
4569                                         _print_parity(bp,
4570                                                       BRB1_REG_BRB1_PRTY_STS);
4571                                         break;
4572                                 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4573                                         _print_next_block((*par_num)++,
4574                                                           "PARSER");
4575                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4576                                         break;
4577                                 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4578                                         _print_next_block((*par_num)++, "TSDM");
4579                                         _print_parity(bp,
4580                                                       TSDM_REG_TSDM_PRTY_STS);
4581                                         break;
4582                                 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4583                                         _print_next_block((*par_num)++,
4584                                                           "SEARCHER");
4585                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4586                                         break;
4587                                 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4588                                         _print_next_block((*par_num)++, "TCM");
4589                                         _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4590                                         break;
4591                                 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4592                                         _print_next_block((*par_num)++,
4593                                                           "TSEMI");
4594                                         _print_parity(bp,
4595                                                       TSEM_REG_TSEM_PRTY_STS_0);
4596                                         _print_parity(bp,
4597                                                       TSEM_REG_TSEM_PRTY_STS_1);
4598                                         break;
4599                                 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4600                                         _print_next_block((*par_num)++, "XPB");
4601                                         _print_parity(bp, GRCBASE_XPB +
4602                                                           PB_REG_PB_PRTY_STS);
4603                                         break;
4604                                 }
4605                         }
4606 
4607                         /* Clear the bit */
4608                         sig &= ~cur_bit;
4609                 }
4610         }
4611 
4612         return res;
4613 }
4614 
4615 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4616                                             int *par_num, bool *global,
4617                                             bool print)
4618 {
4619         u32 cur_bit;
4620         bool res;
4621         int i;
4622 
4623         res = false;
4624 
4625         for (i = 0; sig; i++) {
4626                 cur_bit = (0x1UL << i);
4627                 if (sig & cur_bit) {
4628                         res |= true; /* Each bit is real error! */
4629                         switch (cur_bit) {
4630                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4631                                 if (print) {
4632                                         _print_next_block((*par_num)++, "PBF");
4633                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4634                                 }
4635                                 break;
4636                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4637                                 if (print) {
4638                                         _print_next_block((*par_num)++, "QM");
4639                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4640                                 }
4641                                 break;
4642                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4643                                 if (print) {
4644                                         _print_next_block((*par_num)++, "TM");
4645                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4646                                 }
4647                                 break;
4648                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4649                                 if (print) {
4650                                         _print_next_block((*par_num)++, "XSDM");
4651                                         _print_parity(bp,
4652                                                       XSDM_REG_XSDM_PRTY_STS);
4653                                 }
4654                                 break;
4655                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4656                                 if (print) {
4657                                         _print_next_block((*par_num)++, "XCM");
4658                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4659                                 }
4660                                 break;
4661                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4662                                 if (print) {
4663                                         _print_next_block((*par_num)++,
4664                                                           "XSEMI");
4665                                         _print_parity(bp,
4666                                                       XSEM_REG_XSEM_PRTY_STS_0);
4667                                         _print_parity(bp,
4668                                                       XSEM_REG_XSEM_PRTY_STS_1);
4669                                 }
4670                                 break;
4671                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4672                                 if (print) {
4673                                         _print_next_block((*par_num)++,
4674                                                           "DOORBELLQ");
4675                                         _print_parity(bp,
4676                                                       DORQ_REG_DORQ_PRTY_STS);
4677                                 }
4678                                 break;
4679                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4680                                 if (print) {
4681                                         _print_next_block((*par_num)++, "NIG");
4682                                         if (CHIP_IS_E1x(bp)) {
4683                                                 _print_parity(bp,
4684                                                         NIG_REG_NIG_PRTY_STS);
4685                                         } else {
4686                                                 _print_parity(bp,
4687                                                         NIG_REG_NIG_PRTY_STS_0);
4688                                                 _print_parity(bp,
4689                                                         NIG_REG_NIG_PRTY_STS_1);
4690                                         }
4691                                 }
4692                                 break;
4693                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4694                                 if (print)
4695                                         _print_next_block((*par_num)++,
4696                                                           "VAUX PCI CORE");
4697                                 *global = true;
4698                                 break;
4699                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4700                                 if (print) {
4701                                         _print_next_block((*par_num)++,
4702                                                           "DEBUG");
4703                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4704                                 }
4705                                 break;
4706                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4707                                 if (print) {
4708                                         _print_next_block((*par_num)++, "USDM");
4709                                         _print_parity(bp,
4710                                                       USDM_REG_USDM_PRTY_STS);
4711                                 }
4712                                 break;
4713                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4714                                 if (print) {
4715                                         _print_next_block((*par_num)++, "UCM");
4716                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4717                                 }
4718                                 break;
4719                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4720                                 if (print) {
4721                                         _print_next_block((*par_num)++,
4722                                                           "USEMI");
4723                                         _print_parity(bp,
4724                                                       USEM_REG_USEM_PRTY_STS_0);
4725                                         _print_parity(bp,
4726                                                       USEM_REG_USEM_PRTY_STS_1);
4727                                 }
4728                                 break;
4729                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4730                                 if (print) {
4731                                         _print_next_block((*par_num)++, "UPB");
4732                                         _print_parity(bp, GRCBASE_UPB +
4733                                                           PB_REG_PB_PRTY_STS);
4734                                 }
4735                                 break;
4736                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4737                                 if (print) {
4738                                         _print_next_block((*par_num)++, "CSDM");
4739                                         _print_parity(bp,
4740                                                       CSDM_REG_CSDM_PRTY_STS);
4741                                 }
4742                                 break;
4743                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4744                                 if (print) {
4745                                         _print_next_block((*par_num)++, "CCM");
4746                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4747                                 }
4748                                 break;
4749                         }
4750 
4751                         /* Clear the bit */
4752                         sig &= ~cur_bit;
4753                 }
4754         }
4755 
4756         return res;
4757 }
4758 
4759 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4760                                             int *par_num, bool print)
4761 {
4762         u32 cur_bit;
4763         bool res;
4764         int i;
4765 
4766         res = false;
4767 
4768         for (i = 0; sig; i++) {
4769                 cur_bit = (0x1UL << i);
4770                 if (sig & cur_bit) {
4771                         res = true; /* Each bit is real error! */
4772                         if (print) {
4773                                 switch (cur_bit) {
4774                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4775                                         _print_next_block((*par_num)++,
4776                                                           "CSEMI");
4777                                         _print_parity(bp,
4778                                                       CSEM_REG_CSEM_PRTY_STS_0);
4779                                         _print_parity(bp,
4780                                                       CSEM_REG_CSEM_PRTY_STS_1);
4781                                         break;
4782                                 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4783                                         _print_next_block((*par_num)++, "PXP");
4784                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4785                                         _print_parity(bp,
4786                                                       PXP2_REG_PXP2_PRTY_STS_0);
4787                                         _print_parity(bp,
4788                                                       PXP2_REG_PXP2_PRTY_STS_1);
4789                                         break;
4790                                 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4791                                         _print_next_block((*par_num)++,
4792                                                           "PXPPCICLOCKCLIENT");
4793                                         break;
4794                                 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4795                                         _print_next_block((*par_num)++, "CFC");
4796                                         _print_parity(bp,
4797                                                       CFC_REG_CFC_PRTY_STS);
4798                                         break;
4799                                 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4800                                         _print_next_block((*par_num)++, "CDU");
4801                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4802                                         break;
4803                                 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4804                                         _print_next_block((*par_num)++, "DMAE");
4805                                         _print_parity(bp,
4806                                                       DMAE_REG_DMAE_PRTY_STS);
4807                                         break;
4808                                 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4809                                         _print_next_block((*par_num)++, "IGU");
4810                                         if (CHIP_IS_E1x(bp))
4811                                                 _print_parity(bp,
4812                                                         HC_REG_HC_PRTY_STS);
4813                                         else
4814                                                 _print_parity(bp,
4815                                                         IGU_REG_IGU_PRTY_STS);
4816                                         break;
4817                                 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4818                                         _print_next_block((*par_num)++, "MISC");
4819                                         _print_parity(bp,
4820                                                       MISC_REG_MISC_PRTY_STS);
4821                                         break;
4822                                 }
4823                         }
4824 
4825                         /* Clear the bit */
4826                         sig &= ~cur_bit;
4827                 }
4828         }
4829 
4830         return res;
4831 }
4832 
4833 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4834                                             int *par_num, bool *global,
4835                                             bool print)
4836 {
4837         bool res = false;
4838         u32 cur_bit;
4839         int i;
4840 
4841         for (i = 0; sig; i++) {
4842                 cur_bit = (0x1UL << i);
4843                 if (sig & cur_bit) {
4844                         switch (cur_bit) {
4845                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4846                                 if (print)
4847                                         _print_next_block((*par_num)++,
4848                                                           "MCP ROM");
4849                                 *global = true;
4850                                 res = true;
4851                                 break;
4852                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4853                                 if (print)
4854                                         _print_next_block((*par_num)++,
4855                                                           "MCP UMP RX");
4856                                 *global = true;
4857                                 res = true;
4858                                 break;
4859                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4860                                 if (print)
4861                                         _print_next_block((*par_num)++,
4862                                                           "MCP UMP TX");
4863                                 *global = true;
4864                                 res = true;
4865                                 break;
4866                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4867                                 if (print)
4868                                         _print_next_block((*par_num)++,
4869                                                           "MCP SCPAD");
4870                                 /* clear latched SCPAD PATIRY from MCP */
4871                                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4872                                        1UL << 10);
4873                                 break;
4874                         }
4875 
4876                         /* Clear the bit */
4877                         sig &= ~cur_bit;
4878                 }
4879         }
4880 
4881         return res;
4882 }
4883 
4884 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4885                                             int *par_num, bool print)
4886 {
4887         u32 cur_bit;
4888         bool res;
4889         int i;
4890 
4891         res = false;
4892 
4893         for (i = 0; sig; i++) {
4894                 cur_bit = (0x1UL << i);
4895                 if (sig & cur_bit) {
4896                         res = true; /* Each bit is real error! */
4897                         if (print) {
4898                                 switch (cur_bit) {
4899                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4900                                         _print_next_block((*par_num)++,
4901                                                           "PGLUE_B");
4902                                         _print_parity(bp,
4903                                                       PGLUE_B_REG_PGLUE_B_PRTY_STS);
4904                                         break;
4905                                 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4906                                         _print_next_block((*par_num)++, "ATC");
4907                                         _print_parity(bp,
4908                                                       ATC_REG_ATC_PRTY_STS);
4909                                         break;
4910                                 }
4911                         }
4912                         /* Clear the bit */
4913                         sig &= ~cur_bit;
4914                 }
4915         }
4916 
4917         return res;
4918 }
4919 
4920 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4921                               u32 *sig)
4922 {
4923         bool res = false;
4924 
4925         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4926             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4927             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4928             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4929             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4930                 int par_num = 0;
4931                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4932                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4933                           sig[0] & HW_PRTY_ASSERT_SET_0,
4934                           sig[1] & HW_PRTY_ASSERT_SET_1,
4935                           sig[2] & HW_PRTY_ASSERT_SET_2,
4936                           sig[3] & HW_PRTY_ASSERT_SET_3,
4937                           sig[4] & HW_PRTY_ASSERT_SET_4);
4938                 if (print)
4939                         netdev_err(bp->dev,
4940                                    "Parity errors detected in blocks: ");
4941                 res |= bnx2x_check_blocks_with_parity0(bp,
4942                         sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4943                 res |= bnx2x_check_blocks_with_parity1(bp,
4944                         sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4945                 res |= bnx2x_check_blocks_with_parity2(bp,
4946                         sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4947                 res |= bnx2x_check_blocks_with_parity3(bp,
4948                         sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4949                 res |= bnx2x_check_blocks_with_parity4(bp,
4950                         sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4951 
4952                 if (print)
4953                         pr_cont("\n");
4954         }
4955 
4956         return res;
4957 }
4958 
4959 /**
4960  * bnx2x_chk_parity_attn - checks for parity attentions.
4961  *
4962  * @bp:         driver handle
4963  * @global:     true if there was a global attention
4964  * @print:      show parity attention in syslog
4965  */
4966 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4967 {
4968         struct attn_route attn = { {0} };
4969         int port = BP_PORT(bp);
4970 
4971         attn.sig[0] = REG_RD(bp,
4972                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4973                              port*4);
4974         attn.sig[1] = REG_RD(bp,
4975                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4976                              port*4);
4977         attn.sig[2] = REG_RD(bp,
4978                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4979                              port*4);
4980         attn.sig[3] = REG_RD(bp,
4981                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4982                              port*4);
4983         /* Since MCP attentions can't be disabled inside the block, we need to
4984          * read AEU registers to see whether they're currently disabled
4985          */
4986         attn.sig[3] &= ((REG_RD(bp,
4987                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4988                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
4989                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
4990                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
4991 
4992         if (!CHIP_IS_E1x(bp))
4993                 attn.sig[4] = REG_RD(bp,
4994                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4995                                      port*4);
4996 
4997         return bnx2x_parity_attn(bp, global, print, attn.sig);
4998 }
4999 
5000 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
5001 {
5002         u32 val;
5003         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5004 
5005                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5006                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5007                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
5008                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5009                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
5010                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5011                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
5012                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5013                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
5014                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5015                 if (val &
5016                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
5017                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5018                 if (val &
5019                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
5020                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5021                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
5022                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5023                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
5024                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5025                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
5026                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5027         }
5028         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5029                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5030                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5031                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5032                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5033                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
5034                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5035                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
5036                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5037                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
5038                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5039                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5040                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5041                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
5042                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5043         }
5044 
5045         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5046                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5047                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5048                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5049                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5050         }
5051 }
5052 
5053 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5054 {
5055         struct attn_route attn, *group_mask;
5056         int port = BP_PORT(bp);
5057         int index;
5058         u32 reg_addr;
5059         u32 val;
5060         u32 aeu_mask;
5061         bool global = false;
5062 
5063         /* need to take HW lock because MCP or other port might also
5064            try to handle this event */
5065         bnx2x_acquire_alr(bp);
5066 
5067         if (bnx2x_chk_parity_attn(bp, &global, true)) {
5068 #ifndef BNX2X_STOP_ON_ERROR
5069                 bp->recovery_state = BNX2X_RECOVERY_INIT;
5070                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5071                 /* Disable HW interrupts */
5072                 bnx2x_int_disable(bp);
5073                 /* In case of parity errors don't handle attentions so that
5074                  * other function would "see" parity errors.
5075                  */
5076 #else
5077                 bnx2x_panic();
5078 #endif
5079                 bnx2x_release_alr(bp);
5080                 return;
5081         }
5082 
5083         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5084         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5085         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5086         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5087         if (!CHIP_IS_E1x(bp))
5088                 attn.sig[4] =
5089                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5090         else
5091                 attn.sig[4] = 0;
5092 
5093         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5094            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5095 
5096         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5097                 if (deasserted & (1 << index)) {
5098                         group_mask = &bp->attn_group[index];
5099 
5100                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5101                            index,
5102                            group_mask->sig[0], group_mask->sig[1],
5103                            group_mask->sig[2], group_mask->sig[3],
5104                            group_mask->sig[4]);
5105 
5106                         bnx2x_attn_int_deasserted4(bp,
5107                                         attn.sig[4] & group_mask->sig[4]);
5108                         bnx2x_attn_int_deasserted3(bp,
5109                                         attn.sig[3] & group_mask->sig[3]);
5110                         bnx2x_attn_int_deasserted1(bp,
5111                                         attn.sig[1] & group_mask->sig[1]);
5112                         bnx2x_attn_int_deasserted2(bp,
5113                                         attn.sig[2] & group_mask->sig[2]);
5114                         bnx2x_attn_int_deasserted0(bp,
5115                                         attn.sig[0] & group_mask->sig[0]);
5116                 }
5117         }
5118 
5119         bnx2x_release_alr(bp);
5120 
5121         if (bp->common.int_block == INT_BLOCK_HC)
5122                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5123                             COMMAND_REG_ATTN_BITS_CLR);
5124         else
5125                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5126 
5127         val = ~deasserted;
5128         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5129            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5130         REG_WR(bp, reg_addr, val);
5131 
5132         if (~bp->attn_state & deasserted)
5133                 BNX2X_ERR("IGU ERROR\n");
5134 
5135         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5136                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
5137 
5138         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5139         aeu_mask = REG_RD(bp, reg_addr);
5140 
5141         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
5142            aeu_mask, deasserted);
5143         aeu_mask |= (deasserted & 0x3ff);
5144         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5145 
5146         REG_WR(bp, reg_addr, aeu_mask);
5147         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5148 
5149         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5150         bp->attn_state &= ~deasserted;
5151         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5152 }
5153 
5154 static void bnx2x_attn_int(struct bnx2x *bp)
5155 {
5156         /* read local copy of bits */
5157         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5158                                                                 attn_bits);
5159         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5160                                                                 attn_bits_ack);
5161         u32 attn_state = bp->attn_state;
5162 
5163         /* look for changed bits */
5164         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
5165         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
5166 
5167         DP(NETIF_MSG_HW,
5168            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
5169            attn_bits, attn_ack, asserted, deasserted);
5170 
5171         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5172                 BNX2X_ERR("BAD attention state\n");
5173 
5174         /* handle bits that were raised */
5175         if (asserted)
5176                 bnx2x_attn_int_asserted(bp, asserted);
5177 
5178         if (deasserted)
5179                 bnx2x_attn_int_deasserted(bp, deasserted);
5180 }
5181 
5182 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5183                       u16 index, u8 op, u8 update)
5184 {
5185         u32 igu_addr = bp->igu_base_addr;
5186         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5187         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5188                              igu_addr);
5189 }
5190 
5191 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5192 {
5193         /* No memory barriers */
5194         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5195         mmiowb(); /* keep prod updates ordered */
5196 }
5197 
5198 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5199                                       union event_ring_elem *elem)
5200 {
5201         u8 err = elem->message.error;
5202 
5203         if (!bp->cnic_eth_dev.starting_cid  ||
5204             (cid < bp->cnic_eth_dev.starting_cid &&
5205             cid != bp->cnic_eth_dev.iscsi_l2_cid))
5206                 return 1;
5207 
5208         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5209 
5210         if (unlikely(err)) {
5211 
5212                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5213                           cid);
5214                 bnx2x_panic_dump(bp, false);
5215         }
5216         bnx2x_cnic_cfc_comp(bp, cid, err);
5217         return 0;
5218 }
5219 
5220 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5221 {
5222         struct bnx2x_mcast_ramrod_params rparam;
5223         int rc;
5224 
5225         memset(&rparam, 0, sizeof(rparam));
5226 
5227         rparam.mcast_obj = &bp->mcast_obj;
5228 
5229         netif_addr_lock_bh(bp->dev);
5230 
5231         /* Clear pending state for the last command */
5232         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5233 
5234         /* If there are pending mcast commands - send them */
5235         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5236                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5237                 if (rc < 0)
5238                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5239                                   rc);
5240         }
5241 
5242         netif_addr_unlock_bh(bp->dev);
5243 }
5244 
5245 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5246                                             union event_ring_elem *elem)
5247 {
5248         unsigned long ramrod_flags = 0;
5249         int rc = 0;
5250         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5251         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5252 
5253         /* Always push next commands out, don't wait here */
5254         __set_bit(RAMROD_CONT, &ramrod_flags);
5255 
5256         switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5257                             >> BNX2X_SWCID_SHIFT) {
5258         case BNX2X_FILTER_MAC_PENDING:
5259                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5260                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5261                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5262                 else
5263                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5264 
5265                 break;
5266         case BNX2X_FILTER_MCAST_PENDING:
5267                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5268                 /* This is only relevant for 57710 where multicast MACs are
5269                  * configured as unicast MACs using the same ramrod.
5270                  */
5271                 bnx2x_handle_mcast_eqe(bp);
5272                 return;
5273         default:
5274                 BNX2X_ERR("Unsupported classification command: %d\n",
5275                           elem->message.data.eth_event.echo);
5276                 return;
5277         }
5278 
5279         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5280 
5281         if (rc < 0)
5282                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5283         else if (rc > 0)
5284                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5285 }
5286 
5287 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5288 
5289 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5290 {
5291         netif_addr_lock_bh(bp->dev);
5292 
5293         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5294 
5295         /* Send rx_mode command again if was requested */
5296         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5297                 bnx2x_set_storm_rx_mode(bp);
5298         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5299                                     &bp->sp_state))
5300                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5301         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5302                                     &bp->sp_state))
5303                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5304 
5305         netif_addr_unlock_bh(bp->dev);
5306 }
5307 
5308 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5309                                               union event_ring_elem *elem)
5310 {
5311         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5312                 DP(BNX2X_MSG_SP,
5313                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5314                    elem->message.data.vif_list_event.func_bit_map);
5315                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5316                         elem->message.data.vif_list_event.func_bit_map);
5317         } else if (elem->message.data.vif_list_event.echo ==
5318                    VIF_LIST_RULE_SET) {
5319                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5320                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5321         }
5322 }
5323 
5324 /* called with rtnl_lock */
5325 static void bnx2x_after_function_update(struct bnx2x *bp)
5326 {
5327         int q, rc;
5328         struct bnx2x_fastpath *fp;
5329         struct bnx2x_queue_state_params queue_params = {NULL};
5330         struct bnx2x_queue_update_params *q_update_params =
5331                 &queue_params.params.update;
5332 
5333         /* Send Q update command with afex vlan removal values for all Qs */
5334         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5335 
5336         /* set silent vlan removal values according to vlan mode */
5337         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5338                   &q_update_params->update_flags);
5339         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5340                   &q_update_params->update_flags);
5341         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5342 
5343         /* in access mode mark mask and value are 0 to strip all vlans */
5344         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5345                 q_update_params->silent_removal_value = 0;
5346                 q_update_params->silent_removal_mask = 0;
5347         } else {
5348                 q_update_params->silent_removal_value =
5349                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5350                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5351         }
5352 
5353         for_each_eth_queue(bp, q) {
5354                 /* Set the appropriate Queue object */
5355                 fp = &bp->fp[q];
5356                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5357 
5358                 /* send the ramrod */
5359                 rc = bnx2x_queue_state_change(bp, &queue_params);
5360                 if (rc < 0)
5361                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5362                                   q);
5363         }
5364 
5365         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5366                 fp = &bp->fp[FCOE_IDX(bp)];
5367                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5368 
5369                 /* clear pending completion bit */
5370                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5371 
5372                 /* mark latest Q bit */
5373                 smp_mb__before_atomic();
5374                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5375                 smp_mb__after_atomic();
5376 
5377                 /* send Q update ramrod for FCoE Q */
5378                 rc = bnx2x_queue_state_change(bp, &queue_params);
5379                 if (rc < 0)
5380                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5381                                   q);
5382         } else {
5383                 /* If no FCoE ring - ACK MCP now */
5384                 bnx2x_link_report(bp);
5385                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5386         }
5387 }
5388 
5389 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5390         struct bnx2x *bp, u32 cid)
5391 {
5392         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5393 
5394         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5395                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5396         else
5397                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5398 }
5399 
5400 static void bnx2x_eq_int(struct bnx2x *bp)
5401 {
5402         u16 hw_cons, sw_cons, sw_prod;
5403         union event_ring_elem *elem;
5404         u8 echo;
5405         u32 cid;
5406         u8 opcode;
5407         int rc, spqe_cnt = 0;
5408         struct bnx2x_queue_sp_obj *q_obj;
5409         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5410         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5411 
5412         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5413 
5414         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5415          * when we get the next-page we need to adjust so the loop
5416          * condition below will be met. The next element is the size of a
5417          * regular element and hence incrementing by 1
5418          */
5419         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5420                 hw_cons++;
5421 
5422         /* This function may never run in parallel with itself for a
5423          * specific bp, thus there is no need in "paired" read memory
5424          * barrier here.
5425          */
5426         sw_cons = bp->eq_cons;
5427         sw_prod = bp->eq_prod;
5428 
5429         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5430                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5431 
5432         for (; sw_cons != hw_cons;
5433               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5434 
5435                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5436 
5437                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5438                 if (!rc) {
5439                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5440                            rc);
5441                         goto next_spqe;
5442                 }
5443 
5444                 /* elem CID originates from FW; actually LE */
5445                 cid = SW_CID((__force __le32)
5446                              elem->message.data.cfc_del_event.cid);
5447                 opcode = elem->message.opcode;
5448 
5449                 /* handle eq element */
5450                 switch (opcode) {
5451                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5452                         bnx2x_vf_mbx_schedule(bp,
5453                                               &elem->message.data.vf_pf_event);
5454                         continue;
5455 
5456                 case EVENT_RING_OPCODE_STAT_QUERY:
5457                         DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5458                                "got statistics comp event %d\n",
5459                                bp->stats_comp++);
5460                         /* nothing to do with stats comp */
5461                         goto next_spqe;
5462 
5463                 case EVENT_RING_OPCODE_CFC_DEL:
5464                         /* handle according to cid range */
5465                         /*
5466                          * we may want to verify here that the bp state is
5467                          * HALTING
5468                          */
5469                         DP(BNX2X_MSG_SP,
5470                            "got delete ramrod for MULTI[%d]\n", cid);
5471 
5472                         if (CNIC_LOADED(bp) &&
5473                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5474                                 goto next_spqe;
5475 
5476                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5477 
5478                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5479                                 break;
5480 
5481                         goto next_spqe;
5482 
5483                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5484                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5485                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5486                         if (f_obj->complete_cmd(bp, f_obj,
5487                                                 BNX2X_F_CMD_TX_STOP))
5488                                 break;
5489                         goto next_spqe;
5490 
5491                 case EVENT_RING_OPCODE_START_TRAFFIC:
5492                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5493                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5494                         if (f_obj->complete_cmd(bp, f_obj,
5495                                                 BNX2X_F_CMD_TX_START))
5496                                 break;
5497                         goto next_spqe;
5498 
5499                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5500                         echo = elem->message.data.function_update_event.echo;
5501                         if (echo == SWITCH_UPDATE) {
5502                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5503                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5504                                 if (f_obj->complete_cmd(
5505                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5506                                         break;
5507 
5508                         } else {
5509                                 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5510 
5511                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5512                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5513                                 f_obj->complete_cmd(bp, f_obj,
5514                                                     BNX2X_F_CMD_AFEX_UPDATE);
5515 
5516                                 /* We will perform the Queues update from
5517                                  * sp_rtnl task as all Queue SP operations
5518                                  * should run under rtnl_lock.
5519                                  */
5520                                 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5521                         }
5522 
5523                         goto next_spqe;
5524 
5525                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5526                         f_obj->complete_cmd(bp, f_obj,
5527                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5528                         bnx2x_after_afex_vif_lists(bp, elem);
5529                         goto next_spqe;
5530                 case EVENT_RING_OPCODE_FUNCTION_START:
5531                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5532                            "got FUNC_START ramrod\n");
5533                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5534                                 break;
5535 
5536                         goto next_spqe;
5537 
5538                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5539                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5540                            "got FUNC_STOP ramrod\n");
5541                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5542                                 break;
5543 
5544                         goto next_spqe;
5545 
5546                 case EVENT_RING_OPCODE_SET_TIMESYNC:
5547                         DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5548                            "got set_timesync ramrod completion\n");
5549                         if (f_obj->complete_cmd(bp, f_obj,
5550                                                 BNX2X_F_CMD_SET_TIMESYNC))
5551                                 break;
5552                         goto next_spqe;
5553                 }
5554 
5555                 switch (opcode | bp->state) {
5556                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5557                       BNX2X_STATE_OPEN):
5558                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5559                       BNX2X_STATE_OPENING_WAIT4_PORT):
5560                         cid = elem->message.data.eth_event.echo &
5561                                 BNX2X_SWCID_MASK;
5562                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5563                            cid);
5564                         rss_raw->clear_pending(rss_raw);
5565                         break;
5566 
5567                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5568                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5569                 case (EVENT_RING_OPCODE_SET_MAC |
5570                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5571                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5572                       BNX2X_STATE_OPEN):
5573                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5574                       BNX2X_STATE_DIAG):
5575                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5576                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5577                         DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5578                         bnx2x_handle_classification_eqe(bp, elem);
5579                         break;
5580 
5581                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5582                       BNX2X_STATE_OPEN):
5583                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5584                       BNX2X_STATE_DIAG):
5585                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5586                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5587                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5588                         bnx2x_handle_mcast_eqe(bp);
5589                         break;
5590 
5591                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5592                       BNX2X_STATE_OPEN):
5593                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5594                       BNX2X_STATE_DIAG):
5595                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5596                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5597                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5598                         bnx2x_handle_rx_mode_eqe(bp);
5599                         break;
5600                 default:
5601                         /* unknown event log error and continue */
5602                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5603                                   elem->message.opcode, bp->state);
5604                 }
5605 next_spqe:
5606                 spqe_cnt++;
5607         } /* for */
5608 
5609         smp_mb__before_atomic();
5610         atomic_add(spqe_cnt, &bp->eq_spq_left);
5611 
5612         bp->eq_cons = sw_cons;
5613         bp->eq_prod = sw_prod;
5614         /* Make sure that above mem writes were issued towards the memory */
5615         smp_wmb();
5616 
5617         /* update producer */
5618         bnx2x_update_eq_prod(bp, bp->eq_prod);
5619 }
5620 
5621 static void bnx2x_sp_task(struct work_struct *work)
5622 {
5623         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5624 
5625         DP(BNX2X_MSG_SP, "sp task invoked\n");
5626 
5627         /* make sure the atomic interrupt_occurred has been written */
5628         smp_rmb();
5629         if (atomic_read(&bp->interrupt_occurred)) {
5630 
5631                 /* what work needs to be performed? */
5632                 u16 status = bnx2x_update_dsb_idx(bp);
5633 
5634                 DP(BNX2X_MSG_SP, "status %x\n", status);
5635                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5636                 atomic_set(&bp->interrupt_occurred, 0);
5637 
5638                 /* HW attentions */
5639                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5640                         bnx2x_attn_int(bp);
5641                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5642                 }
5643 
5644                 /* SP events: STAT_QUERY and others */
5645                 if (status & BNX2X_DEF_SB_IDX) {
5646                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5647 
5648                 if (FCOE_INIT(bp) &&
5649                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5650                                 /* Prevent local bottom-halves from running as
5651                                  * we are going to change the local NAPI list.
5652                                  */
5653                                 local_bh_disable();
5654                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5655                                 local_bh_enable();
5656                         }
5657 
5658                         /* Handle EQ completions */
5659                         bnx2x_eq_int(bp);
5660                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5661                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5662 
5663                         status &= ~BNX2X_DEF_SB_IDX;
5664                 }
5665 
5666                 /* if status is non zero then perhaps something went wrong */
5667                 if (unlikely(status))
5668                         DP(BNX2X_MSG_SP,
5669                            "got an unknown interrupt! (status 0x%x)\n", status);
5670 
5671                 /* ack status block only if something was actually handled */
5672                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5673                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5674         }
5675 
5676         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5677         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5678                                &bp->sp_state)) {
5679                 bnx2x_link_report(bp);
5680                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5681         }
5682 }
5683 
5684 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5685 {
5686         struct net_device *dev = dev_instance;
5687         struct bnx2x *bp = netdev_priv(dev);
5688 
5689         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5690                      IGU_INT_DISABLE, 0);
5691 
5692 #ifdef BNX2X_STOP_ON_ERROR
5693         if (unlikely(bp->panic))
5694                 return IRQ_HANDLED;
5695 #endif
5696 
5697         if (CNIC_LOADED(bp)) {
5698                 struct cnic_ops *c_ops;
5699 
5700                 rcu_read_lock();
5701                 c_ops = rcu_dereference(bp->cnic_ops);
5702                 if (c_ops)
5703                         c_ops->cnic_handler(bp->cnic_data, NULL);
5704                 rcu_read_unlock();
5705         }
5706 
5707         /* schedule sp task to perform default status block work, ack
5708          * attentions and enable interrupts.
5709          */
5710         bnx2x_schedule_sp_task(bp);
5711 
5712         return IRQ_HANDLED;
5713 }
5714 
5715 /* end of slow path */
5716 
5717 void bnx2x_drv_pulse(struct bnx2x *bp)
5718 {
5719         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5720                  bp->fw_drv_pulse_wr_seq);
5721 }
5722 
5723 static void bnx2x_timer(unsigned long data)
5724 {
5725         struct bnx2x *bp = (struct bnx2x *) data;
5726 
5727         if (!netif_running(bp->dev))
5728                 return;
5729 
5730         if (IS_PF(bp) &&
5731             !BP_NOMCP(bp)) {
5732                 int mb_idx = BP_FW_MB_IDX(bp);
5733                 u16 drv_pulse;
5734                 u16 mcp_pulse;
5735 
5736                 ++bp->fw_drv_pulse_wr_seq;
5737                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5738                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5739                 bnx2x_drv_pulse(bp);
5740 
5741                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5742                              MCP_PULSE_SEQ_MASK);
5743                 /* The delta between driver pulse and mcp response
5744                  * should not get too big. If the MFW is more than 5 pulses
5745                  * behind, we should worry about it enough to generate an error
5746                  * log.
5747                  */
5748                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5749                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5750                                   drv_pulse, mcp_pulse);
5751         }
5752 
5753         if (bp->state == BNX2X_STATE_OPEN)
5754                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5755 
5756         /* sample pf vf bulletin board for new posts from pf */
5757         if (IS_VF(bp))
5758                 bnx2x_timer_sriov(bp);
5759 
5760         mod_timer(&bp->timer, jiffies + bp->current_interval);
5761 }
5762 
5763 /* end of Statistics */
5764 
5765 /* nic init */
5766 
5767 /*
5768  * nic init service functions
5769  */
5770 
5771 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5772 {
5773         u32 i;
5774         if (!(len%4) && !(addr%4))
5775                 for (i = 0; i < len; i += 4)
5776                         REG_WR(bp, addr + i, fill);
5777         else
5778                 for (i = 0; i < len; i++)
5779                         REG_WR8(bp, addr + i, fill);
5780 }
5781 
5782 /* helper: writes FP SP data to FW - data_size in dwords */
5783 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5784                                 int fw_sb_id,
5785                                 u32 *sb_data_p,
5786                                 u32 data_size)
5787 {
5788         int index;
5789         for (index = 0; index < data_size; index++)
5790                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5791                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5792                         sizeof(u32)*index,
5793                         *(sb_data_p + index));
5794 }
5795 
5796 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5797 {
5798         u32 *sb_data_p;
5799         u32 data_size = 0;
5800         struct hc_status_block_data_e2 sb_data_e2;
5801         struct hc_status_block_data_e1x sb_data_e1x;
5802 
5803         /* disable the function first */
5804         if (!CHIP_IS_E1x(bp)) {
5805                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5806                 sb_data_e2.common.state = SB_DISABLED;
5807                 sb_data_e2.common.p_func.vf_valid = false;
5808                 sb_data_p = (u32 *)&sb_data_e2;
5809                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5810         } else {
5811                 memset(&sb_data_e1x, 0,
5812                        sizeof(struct hc_status_block_data_e1x));
5813                 sb_data_e1x.common.state = SB_DISABLED;
5814                 sb_data_e1x.common.p_func.vf_valid = false;
5815                 sb_data_p = (u32 *)&sb_data_e1x;
5816                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5817         }
5818         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5819 
5820         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5821                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5822                         CSTORM_STATUS_BLOCK_SIZE);
5823         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5824                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5825                         CSTORM_SYNC_BLOCK_SIZE);
5826 }
5827 
5828 /* helper:  writes SP SB data to FW */
5829 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5830                 struct hc_sp_status_block_data *sp_sb_data)
5831 {
5832         int func = BP_FUNC(bp);
5833         int i;
5834         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5835                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5836                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5837                         i*sizeof(u32),
5838                         *((u32 *)sp_sb_data + i));
5839 }
5840 
5841 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5842 {
5843         int func = BP_FUNC(bp);
5844         struct hc_sp_status_block_data sp_sb_data;
5845         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5846 
5847         sp_sb_data.state = SB_DISABLED;
5848         sp_sb_data.p_func.vf_valid = false;
5849 
5850         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5851 
5852         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5853                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5854                         CSTORM_SP_STATUS_BLOCK_SIZE);
5855         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5856                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5857                         CSTORM_SP_SYNC_BLOCK_SIZE);
5858 }
5859 
5860 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5861                                            int igu_sb_id, int igu_seg_id)
5862 {
5863         hc_sm->igu_sb_id = igu_sb_id;
5864         hc_sm->igu_seg_id = igu_seg_id;
5865         hc_sm->timer_value = 0xFF;
5866         hc_sm->time_to_expire = 0xFFFFFFFF;
5867 }
5868 
5869 /* allocates state machine ids. */
5870 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5871 {
5872         /* zero out state machine indices */
5873         /* rx indices */
5874         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5875 
5876         /* tx indices */
5877         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5878         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5879         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5880         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5881 
5882         /* map indices */
5883         /* rx indices */
5884         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5885                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5886 
5887         /* tx indices */
5888         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5889                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5890         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5891                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5892         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5893                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5894         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5895                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5896 }
5897 
5898 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5899                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5900 {
5901         int igu_seg_id;
5902 
5903         struct hc_status_block_data_e2 sb_data_e2;
5904         struct hc_status_block_data_e1x sb_data_e1x;
5905         struct hc_status_block_sm  *hc_sm_p;
5906         int data_size;
5907         u32 *sb_data_p;
5908 
5909         if (CHIP_INT_MODE_IS_BC(bp))
5910                 igu_seg_id = HC_SEG_ACCESS_NORM;
5911         else
5912                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5913 
5914         bnx2x_zero_fp_sb(bp, fw_sb_id);
5915 
5916         if (!CHIP_IS_E1x(bp)) {
5917                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5918                 sb_data_e2.common.state = SB_ENABLED;
5919                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5920                 sb_data_e2.common.p_func.vf_id = vfid;
5921                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5922                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5923                 sb_data_e2.common.same_igu_sb_1b = true;
5924                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5925                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5926                 hc_sm_p = sb_data_e2.common.state_machine;
5927                 sb_data_p = (u32 *)&sb_data_e2;
5928                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5929                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5930         } else {
5931                 memset(&sb_data_e1x, 0,
5932                        sizeof(struct hc_status_block_data_e1x));
5933                 sb_data_e1x.common.state = SB_ENABLED;
5934                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5935                 sb_data_e1x.common.p_func.vf_id = 0xff;
5936                 sb_data_e1x.common.p_func.vf_valid = false;
5937                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5938                 sb_data_e1x.common.same_igu_sb_1b = true;
5939                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5940                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5941                 hc_sm_p = sb_data_e1x.common.state_machine;
5942                 sb_data_p = (u32 *)&sb_data_e1x;
5943                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5944                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5945         }
5946 
5947         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5948                                        igu_sb_id, igu_seg_id);
5949         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5950                                        igu_sb_id, igu_seg_id);
5951 
5952         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5953 
5954         /* write indices to HW - PCI guarantees endianity of regpairs */
5955         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5956 }
5957 
5958 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5959                                      u16 tx_usec, u16 rx_usec)
5960 {
5961         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5962                                     false, rx_usec);
5963         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5964                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5965                                        tx_usec);
5966         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5967                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5968                                        tx_usec);
5969         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5970                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5971                                        tx_usec);
5972 }
5973 
5974 static void bnx2x_init_def_sb(struct bnx2x *bp)
5975 {
5976         struct host_sp_status_block *def_sb = bp->def_status_blk;
5977         dma_addr_t mapping = bp->def_status_blk_mapping;
5978         int igu_sp_sb_index;
5979         int igu_seg_id;
5980         int port = BP_PORT(bp);
5981         int func = BP_FUNC(bp);
5982         int reg_offset, reg_offset_en5;
5983         u64 section;
5984         int index;
5985         struct hc_sp_status_block_data sp_sb_data;
5986         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5987 
5988         if (CHIP_INT_MODE_IS_BC(bp)) {
5989                 igu_sp_sb_index = DEF_SB_IGU_ID;
5990                 igu_seg_id = HC_SEG_ACCESS_DEF;
5991         } else {
5992                 igu_sp_sb_index = bp->igu_dsb_id;
5993                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5994         }
5995 
5996         /* ATTN */
5997         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5998                                             atten_status_block);
5999         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
6000 
6001         bp->attn_state = 0;
6002 
6003         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6004                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6005         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6006                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
6007         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
6008                 int sindex;
6009                 /* take care of sig[0]..sig[4] */
6010                 for (sindex = 0; sindex < 4; sindex++)
6011                         bp->attn_group[index].sig[sindex] =
6012                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
6013 
6014                 if (!CHIP_IS_E1x(bp))
6015                         /*
6016                          * enable5 is separate from the rest of the registers,
6017                          * and therefore the address skip is 4
6018                          * and not 16 between the different groups
6019                          */
6020                         bp->attn_group[index].sig[4] = REG_RD(bp,
6021                                         reg_offset_en5 + 0x4*index);
6022                 else
6023                         bp->attn_group[index].sig[4] = 0;
6024         }
6025 
6026         if (bp->common.int_block == INT_BLOCK_HC) {
6027                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6028                                      HC_REG_ATTN_MSG0_ADDR_L);
6029 
6030                 REG_WR(bp, reg_offset, U64_LO(section));
6031                 REG_WR(bp, reg_offset + 4, U64_HI(section));
6032         } else if (!CHIP_IS_E1x(bp)) {
6033                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6034                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6035         }
6036 
6037         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6038                                             sp_sb);
6039 
6040         bnx2x_zero_sp_sb(bp);
6041 
6042         /* PCI guarantees endianity of regpairs */
6043         sp_sb_data.state                = SB_ENABLED;
6044         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
6045         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
6046         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
6047         sp_sb_data.igu_seg_id           = igu_seg_id;
6048         sp_sb_data.p_func.pf_id         = func;
6049         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
6050         sp_sb_data.p_func.vf_id         = 0xff;
6051 
6052         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
6053 
6054         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6055 }
6056 
6057 void bnx2x_update_coalesce(struct bnx2x *bp)
6058 {
6059         int i;
6060 
6061         for_each_eth_queue(bp, i)
6062                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
6063                                          bp->tx_ticks, bp->rx_ticks);
6064 }
6065 
6066 static void bnx2x_init_sp_ring(struct bnx2x *bp)
6067 {
6068         spin_lock_init(&bp->spq_lock);
6069         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
6070 
6071         bp->spq_prod_idx = 0;
6072         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6073         bp->spq_prod_bd = bp->spq;
6074         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
6075 }
6076 
6077 static void bnx2x_init_eq_ring(struct bnx2x *bp)
6078 {
6079         int i;
6080         for (i = 1; i <= NUM_EQ_PAGES; i++) {
6081                 union event_ring_elem *elem =
6082                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6083 
6084                 elem->next_page.addr.hi =
6085                         cpu_to_le32(U64_HI(bp->eq_mapping +
6086                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6087                 elem->next_page.addr.lo =
6088                         cpu_to_le32(U64_LO(bp->eq_mapping +
6089                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
6090         }
6091         bp->eq_cons = 0;
6092         bp->eq_prod = NUM_EQ_DESC;
6093         bp->eq_cons_sb = BNX2X_EQ_INDEX;
6094         /* we want a warning message before it gets wrought... */
6095         atomic_set(&bp->eq_spq_left,
6096                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
6097 }
6098 
6099 /* called with netif_addr_lock_bh() */
6100 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6101                                unsigned long rx_mode_flags,
6102                                unsigned long rx_accept_flags,
6103                                unsigned long tx_accept_flags,
6104                                unsigned long ramrod_flags)
6105 {
6106         struct bnx2x_rx_mode_ramrod_params ramrod_param;
6107         int rc;
6108 
6109         memset(&ramrod_param, 0, sizeof(ramrod_param));
6110 
6111         /* Prepare ramrod parameters */
6112         ramrod_param.cid = 0;
6113         ramrod_param.cl_id = cl_id;
6114         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6115         ramrod_param.func_id = BP_FUNC(bp);
6116 
6117         ramrod_param.pstate = &bp->sp_state;
6118         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6119 
6120         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6121         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6122 
6123         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6124 
6125         ramrod_param.ramrod_flags = ramrod_flags;
6126         ramrod_param.rx_mode_flags = rx_mode_flags;
6127 
6128         ramrod_param.rx_accept_flags = rx_accept_flags;
6129         ramrod_param.tx_accept_flags = tx_accept_flags;
6130 
6131         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6132         if (rc < 0) {
6133                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6134                 return rc;
6135         }
6136 
6137         return 0;
6138 }
6139 
6140 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6141                                    unsigned long *rx_accept_flags,
6142                                    unsigned long *tx_accept_flags)
6143 {
6144         /* Clear the flags first */
6145         *rx_accept_flags = 0;
6146         *tx_accept_flags = 0;
6147 
6148         switch (rx_mode) {
6149         case BNX2X_RX_MODE_NONE:
6150                 /*
6151                  * 'drop all' supersedes any accept flags that may have been
6152                  * passed to the function.
6153                  */
6154                 break;
6155         case BNX2X_RX_MODE_NORMAL:
6156                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6157                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6158                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6159 
6160                 /* internal switching mode */
6161                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6162                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6163                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6164 
6165                 break;
6166         case BNX2X_RX_MODE_ALLMULTI:
6167                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6168                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6169                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6170 
6171                 /* internal switching mode */
6172                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6173                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6174                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6175 
6176                 break;
6177         case BNX2X_RX_MODE_PROMISC:
6178                 /* According to definition of SI mode, iface in promisc mode
6179                  * should receive matched and unmatched (in resolution of port)
6180                  * unicast packets.
6181                  */
6182                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6183                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6184                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6185                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6186 
6187                 /* internal switching mode */
6188                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6189                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6190 
6191                 if (IS_MF_SI(bp))
6192                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6193                 else
6194                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6195 
6196                 break;
6197         default:
6198                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6199                 return -EINVAL;
6200         }
6201 
6202         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
6203         if (rx_mode != BNX2X_RX_MODE_NONE) {
6204                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6205                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6206         }
6207 
6208         return 0;
6209 }
6210 
6211 /* called with netif_addr_lock_bh() */
6212 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6213 {
6214         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6215         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6216         int rc;
6217 
6218         if (!NO_FCOE(bp))
6219                 /* Configure rx_mode of FCoE Queue */
6220                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6221 
6222         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6223                                      &tx_accept_flags);
6224         if (rc)
6225                 return rc;
6226 
6227         __set_bit(RAMROD_RX, &ramrod_flags);
6228         __set_bit(RAMROD_TX, &ramrod_flags);
6229 
6230         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6231                                    rx_accept_flags, tx_accept_flags,
6232                                    ramrod_flags);
6233 }
6234 
6235 static void bnx2x_init_internal_common(struct bnx2x *bp)
6236 {
6237         int i;
6238 
6239         /* Zero this manually as its initialization is
6240            currently missing in the initTool */
6241         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6242                 REG_WR(bp, BAR_USTRORM_INTMEM +
6243                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
6244         if (!CHIP_IS_E1x(bp)) {
6245                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6246                         CHIP_INT_MODE_IS_BC(bp) ?
6247                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6248         }
6249 }
6250 
6251 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6252 {
6253         switch (load_code) {
6254         case FW_MSG_CODE_DRV_LOAD_COMMON:
6255         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6256                 bnx2x_init_internal_common(bp);
6257                 /* no break */
6258 
6259         case FW_MSG_CODE_DRV_LOAD_PORT:
6260                 /* nothing to do */
6261                 /* no break */
6262 
6263         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6264                 /* internal memory per function is
6265                    initialized inside bnx2x_pf_init */
6266                 break;
6267 
6268         default:
6269                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6270                 break;
6271         }
6272 }
6273 
6274 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6275 {
6276         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6277 }
6278 
6279 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6280 {
6281         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6282 }
6283 
6284 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6285 {
6286         if (CHIP_IS_E1x(fp->bp))
6287                 return BP_L_ID(fp->bp) + fp->index;
6288         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6289                 return bnx2x_fp_igu_sb_id(fp);
6290 }
6291 
6292 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6293 {
6294         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6295         u8 cos;
6296         unsigned long q_type = 0;
6297         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6298         fp->rx_queue = fp_idx;
6299         fp->cid = fp_idx;
6300         fp->cl_id = bnx2x_fp_cl_id(fp);
6301         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6302         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6303         /* qZone id equals to FW (per path) client id */
6304         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
6305 
6306         /* init shortcut */
6307         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6308 
6309         /* Setup SB indices */
6310         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6311 
6312         /* Configure Queue State object */
6313         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6314         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6315 
6316         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6317 
6318         /* init tx data */
6319         for_each_cos_in_tx_queue(fp, cos) {
6320                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6321                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6322                                   FP_COS_TO_TXQ(fp, cos, bp),
6323                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
6324                 cids[cos] = fp->txdata_ptr[cos]->cid;
6325         }
6326 
6327         /* nothing more for vf to do here */
6328         if (IS_VF(bp))
6329                 return;
6330 
6331         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6332                       fp->fw_sb_id, fp->igu_sb_id);
6333         bnx2x_update_fpsb_idx(fp);
6334         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6335                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6336                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6337 
6338         /**
6339          * Configure classification DBs: Always enable Tx switching
6340          */
6341         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6342 
6343         DP(NETIF_MSG_IFUP,
6344            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
6345            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6346            fp->igu_sb_id);