Version:  2.0.40 2.2.26 2.4.37 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10

Linux/drivers/net/ethernet/apple/mace.c

  1 /*
  2  * Network device driver for the MACE ethernet controller on
  3  * Apple Powermacs.  Assumes it's under a DBDMA controller.
  4  *
  5  * Copyright (C) 1996 Paul Mackerras.
  6  */
  7 
  8 #include <linux/module.h>
  9 #include <linux/kernel.h>
 10 #include <linux/netdevice.h>
 11 #include <linux/etherdevice.h>
 12 #include <linux/delay.h>
 13 #include <linux/string.h>
 14 #include <linux/timer.h>
 15 #include <linux/init.h>
 16 #include <linux/interrupt.h>
 17 #include <linux/crc32.h>
 18 #include <linux/spinlock.h>
 19 #include <linux/bitrev.h>
 20 #include <linux/slab.h>
 21 #include <asm/prom.h>
 22 #include <asm/dbdma.h>
 23 #include <asm/io.h>
 24 #include <asm/pgtable.h>
 25 #include <asm/macio.h>
 26 
 27 #include "mace.h"
 28 
 29 static int port_aaui = -1;
 30 
 31 #define N_RX_RING       8
 32 #define N_TX_RING       6
 33 #define MAX_TX_ACTIVE   1
 34 #define NCMDS_TX        1       /* dma commands per element in tx ring */
 35 #define RX_BUFLEN       (ETH_FRAME_LEN + 8)
 36 #define TX_TIMEOUT      HZ      /* 1 second */
 37 
 38 /* Chip rev needs workaround on HW & multicast addr change */
 39 #define BROKEN_ADDRCHG_REV      0x0941
 40 
 41 /* Bits in transmit DMA status */
 42 #define TX_DMA_ERR      0x80
 43 
 44 struct mace_data {
 45     volatile struct mace __iomem *mace;
 46     volatile struct dbdma_regs __iomem *tx_dma;
 47     int tx_dma_intr;
 48     volatile struct dbdma_regs __iomem *rx_dma;
 49     int rx_dma_intr;
 50     volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */
 51     volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */
 52     struct sk_buff *rx_bufs[N_RX_RING];
 53     int rx_fill;
 54     int rx_empty;
 55     struct sk_buff *tx_bufs[N_TX_RING];
 56     int tx_fill;
 57     int tx_empty;
 58     unsigned char maccc;
 59     unsigned char tx_fullup;
 60     unsigned char tx_active;
 61     unsigned char tx_bad_runt;
 62     struct timer_list tx_timeout;
 63     int timeout_active;
 64     int port_aaui;
 65     int chipid;
 66     struct macio_dev *mdev;
 67     spinlock_t lock;
 68 };
 69 
 70 /*
 71  * Number of bytes of private data per MACE: allow enough for
 72  * the rx and tx dma commands plus a branch dma command each,
 73  * and another 16 bytes to allow us to align the dma command
 74  * buffers on a 16 byte boundary.
 75  */
 76 #define PRIV_BYTES      (sizeof(struct mace_data) \
 77         + (N_RX_RING + NCMDS_TX * N_TX_RING + 3) * sizeof(struct dbdma_cmd))
 78 
 79 static int mace_open(struct net_device *dev);
 80 static int mace_close(struct net_device *dev);
 81 static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev);
 82 static void mace_set_multicast(struct net_device *dev);
 83 static void mace_reset(struct net_device *dev);
 84 static int mace_set_address(struct net_device *dev, void *addr);
 85 static irqreturn_t mace_interrupt(int irq, void *dev_id);
 86 static irqreturn_t mace_txdma_intr(int irq, void *dev_id);
 87 static irqreturn_t mace_rxdma_intr(int irq, void *dev_id);
 88 static void mace_set_timeout(struct net_device *dev);
 89 static void mace_tx_timeout(unsigned long data);
 90 static inline void dbdma_reset(volatile struct dbdma_regs __iomem *dma);
 91 static inline void mace_clean_rings(struct mace_data *mp);
 92 static void __mace_set_address(struct net_device *dev, void *addr);
 93 
 94 /*
 95  * If we can't get a skbuff when we need it, we use this area for DMA.
 96  */
 97 static unsigned char *dummy_buf;
 98 
 99 static const struct net_device_ops mace_netdev_ops = {
100         .ndo_open               = mace_open,
101         .ndo_stop               = mace_close,
102         .ndo_start_xmit         = mace_xmit_start,
103         .ndo_set_rx_mode        = mace_set_multicast,
104         .ndo_set_mac_address    = mace_set_address,
105         .ndo_validate_addr      = eth_validate_addr,
106 };
107 
108 static int mace_probe(struct macio_dev *mdev, const struct of_device_id *match)
109 {
110         struct device_node *mace = macio_get_of_node(mdev);
111         struct net_device *dev;
112         struct mace_data *mp;
113         const unsigned char *addr;
114         int j, rev, rc = -EBUSY;
115 
116         if (macio_resource_count(mdev) != 3 || macio_irq_count(mdev) != 3) {
117                 printk(KERN_ERR "can't use MACE %s: need 3 addrs and 3 irqs\n",
118                        mace->full_name);
119                 return -ENODEV;
120         }
121 
122         addr = of_get_property(mace, "mac-address", NULL);
123         if (addr == NULL) {
124                 addr = of_get_property(mace, "local-mac-address", NULL);
125                 if (addr == NULL) {
126                         printk(KERN_ERR "Can't get mac-address for MACE %s\n",
127                                mace->full_name);
128                         return -ENODEV;
129                 }
130         }
131 
132         /*
133          * lazy allocate the driver-wide dummy buffer. (Note that we
134          * never have more than one MACE in the system anyway)
135          */
136         if (dummy_buf == NULL) {
137                 dummy_buf = kmalloc(RX_BUFLEN+2, GFP_KERNEL);
138                 if (dummy_buf == NULL)
139                         return -ENOMEM;
140         }
141 
142         if (macio_request_resources(mdev, "mace")) {
143                 printk(KERN_ERR "MACE: can't request IO resources !\n");
144                 return -EBUSY;
145         }
146 
147         dev = alloc_etherdev(PRIV_BYTES);
148         if (!dev) {
149                 rc = -ENOMEM;
150                 goto err_release;
151         }
152         SET_NETDEV_DEV(dev, &mdev->ofdev.dev);
153 
154         mp = netdev_priv(dev);
155         mp->mdev = mdev;
156         macio_set_drvdata(mdev, dev);
157 
158         dev->base_addr = macio_resource_start(mdev, 0);
159         mp->mace = ioremap(dev->base_addr, 0x1000);
160         if (mp->mace == NULL) {
161                 printk(KERN_ERR "MACE: can't map IO resources !\n");
162                 rc = -ENOMEM;
163                 goto err_free;
164         }
165         dev->irq = macio_irq(mdev, 0);
166 
167         rev = addr[0] == 0 && addr[1] == 0xA0;
168         for (j = 0; j < 6; ++j) {
169                 dev->dev_addr[j] = rev ? bitrev8(addr[j]): addr[j];
170         }
171         mp->chipid = (in_8(&mp->mace->chipid_hi) << 8) |
172                         in_8(&mp->mace->chipid_lo);
173 
174 
175         mp = netdev_priv(dev);
176         mp->maccc = ENXMT | ENRCV;
177 
178         mp->tx_dma = ioremap(macio_resource_start(mdev, 1), 0x1000);
179         if (mp->tx_dma == NULL) {
180                 printk(KERN_ERR "MACE: can't map TX DMA resources !\n");
181                 rc = -ENOMEM;
182                 goto err_unmap_io;
183         }
184         mp->tx_dma_intr = macio_irq(mdev, 1);
185 
186         mp->rx_dma = ioremap(macio_resource_start(mdev, 2), 0x1000);
187         if (mp->rx_dma == NULL) {
188                 printk(KERN_ERR "MACE: can't map RX DMA resources !\n");
189                 rc = -ENOMEM;
190                 goto err_unmap_tx_dma;
191         }
192         mp->rx_dma_intr = macio_irq(mdev, 2);
193 
194         mp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(mp + 1);
195         mp->rx_cmds = mp->tx_cmds + NCMDS_TX * N_TX_RING + 1;
196 
197         memset((char *) mp->tx_cmds, 0,
198                (NCMDS_TX*N_TX_RING + N_RX_RING + 2) * sizeof(struct dbdma_cmd));
199         init_timer(&mp->tx_timeout);
200         spin_lock_init(&mp->lock);
201         mp->timeout_active = 0;
202 
203         if (port_aaui >= 0)
204                 mp->port_aaui = port_aaui;
205         else {
206                 /* Apple Network Server uses the AAUI port */
207                 if (of_machine_is_compatible("AAPL,ShinerESB"))
208                         mp->port_aaui = 1;
209                 else {
210 #ifdef CONFIG_MACE_AAUI_PORT
211                         mp->port_aaui = 1;
212 #else
213                         mp->port_aaui = 0;
214 #endif
215                 }
216         }
217 
218         dev->netdev_ops = &mace_netdev_ops;
219 
220         /*
221          * Most of what is below could be moved to mace_open()
222          */
223         mace_reset(dev);
224 
225         rc = request_irq(dev->irq, mace_interrupt, 0, "MACE", dev);
226         if (rc) {
227                 printk(KERN_ERR "MACE: can't get irq %d\n", dev->irq);
228                 goto err_unmap_rx_dma;
229         }
230         rc = request_irq(mp->tx_dma_intr, mace_txdma_intr, 0, "MACE-txdma", dev);
231         if (rc) {
232                 printk(KERN_ERR "MACE: can't get irq %d\n", mp->tx_dma_intr);
233                 goto err_free_irq;
234         }
235         rc = request_irq(mp->rx_dma_intr, mace_rxdma_intr, 0, "MACE-rxdma", dev);
236         if (rc) {
237                 printk(KERN_ERR "MACE: can't get irq %d\n", mp->rx_dma_intr);
238                 goto err_free_tx_irq;
239         }
240 
241         rc = register_netdev(dev);
242         if (rc) {
243                 printk(KERN_ERR "MACE: Cannot register net device, aborting.\n");
244                 goto err_free_rx_irq;
245         }
246 
247         printk(KERN_INFO "%s: MACE at %pM, chip revision %d.%d\n",
248                dev->name, dev->dev_addr,
249                mp->chipid >> 8, mp->chipid & 0xff);
250 
251         return 0;
252 
253  err_free_rx_irq:
254         free_irq(macio_irq(mdev, 2), dev);
255  err_free_tx_irq:
256         free_irq(macio_irq(mdev, 1), dev);
257  err_free_irq:
258         free_irq(macio_irq(mdev, 0), dev);
259  err_unmap_rx_dma:
260         iounmap(mp->rx_dma);
261  err_unmap_tx_dma:
262         iounmap(mp->tx_dma);
263  err_unmap_io:
264         iounmap(mp->mace);
265  err_free:
266         free_netdev(dev);
267  err_release:
268         macio_release_resources(mdev);
269 
270         return rc;
271 }
272 
273 static int mace_remove(struct macio_dev *mdev)
274 {
275         struct net_device *dev = macio_get_drvdata(mdev);
276         struct mace_data *mp;
277 
278         BUG_ON(dev == NULL);
279 
280         macio_set_drvdata(mdev, NULL);
281 
282         mp = netdev_priv(dev);
283 
284         unregister_netdev(dev);
285 
286         free_irq(dev->irq, dev);
287         free_irq(mp->tx_dma_intr, dev);
288         free_irq(mp->rx_dma_intr, dev);
289 
290         iounmap(mp->rx_dma);
291         iounmap(mp->tx_dma);
292         iounmap(mp->mace);
293 
294         free_netdev(dev);
295 
296         macio_release_resources(mdev);
297 
298         return 0;
299 }
300 
301 static void dbdma_reset(volatile struct dbdma_regs __iomem *dma)
302 {
303     int i;
304 
305     out_le32(&dma->control, (WAKE|FLUSH|PAUSE|RUN) << 16);
306 
307     /*
308      * Yes this looks peculiar, but apparently it needs to be this
309      * way on some machines.
310      */
311     for (i = 200; i > 0; --i)
312         if (le32_to_cpu(dma->control) & RUN)
313             udelay(1);
314 }
315 
316 static void mace_reset(struct net_device *dev)
317 {
318     struct mace_data *mp = netdev_priv(dev);
319     volatile struct mace __iomem *mb = mp->mace;
320     int i;
321 
322     /* soft-reset the chip */
323     i = 200;
324     while (--i) {
325         out_8(&mb->biucc, SWRST);
326         if (in_8(&mb->biucc) & SWRST) {
327             udelay(10);
328             continue;
329         }
330         break;
331     }
332     if (!i) {
333         printk(KERN_ERR "mace: cannot reset chip!\n");
334         return;
335     }
336 
337     out_8(&mb->imr, 0xff);      /* disable all intrs for now */
338     i = in_8(&mb->ir);
339     out_8(&mb->maccc, 0);       /* turn off tx, rx */
340 
341     out_8(&mb->biucc, XMTSP_64);
342     out_8(&mb->utr, RTRD);
343     out_8(&mb->fifocc, RCVFW_32 | XMTFW_16 | XMTFWU | RCVFWU | XMTBRST);
344     out_8(&mb->xmtfc, AUTO_PAD_XMIT); /* auto-pad short frames */
345     out_8(&mb->rcvfc, 0);
346 
347     /* load up the hardware address */
348     __mace_set_address(dev, dev->dev_addr);
349 
350     /* clear the multicast filter */
351     if (mp->chipid == BROKEN_ADDRCHG_REV)
352         out_8(&mb->iac, LOGADDR);
353     else {
354         out_8(&mb->iac, ADDRCHG | LOGADDR);
355         while ((in_8(&mb->iac) & ADDRCHG) != 0)
356                 ;
357     }
358     for (i = 0; i < 8; ++i)
359         out_8(&mb->ladrf, 0);
360 
361     /* done changing address */
362     if (mp->chipid != BROKEN_ADDRCHG_REV)
363         out_8(&mb->iac, 0);
364 
365     if (mp->port_aaui)
366         out_8(&mb->plscc, PORTSEL_AUI + ENPLSIO);
367     else
368         out_8(&mb->plscc, PORTSEL_GPSI + ENPLSIO);
369 }
370 
371 static void __mace_set_address(struct net_device *dev, void *addr)
372 {
373     struct mace_data *mp = netdev_priv(dev);
374     volatile struct mace __iomem *mb = mp->mace;
375     unsigned char *p = addr;
376     int i;
377 
378     /* load up the hardware address */
379     if (mp->chipid == BROKEN_ADDRCHG_REV)
380         out_8(&mb->iac, PHYADDR);
381     else {
382         out_8(&mb->iac, ADDRCHG | PHYADDR);
383         while ((in_8(&mb->iac) & ADDRCHG) != 0)
384             ;
385     }
386     for (i = 0; i < 6; ++i)
387         out_8(&mb->padr, dev->dev_addr[i] = p[i]);
388     if (mp->chipid != BROKEN_ADDRCHG_REV)
389         out_8(&mb->iac, 0);
390 }
391 
392 static int mace_set_address(struct net_device *dev, void *addr)
393 {
394     struct mace_data *mp = netdev_priv(dev);
395     volatile struct mace __iomem *mb = mp->mace;
396     unsigned long flags;
397 
398     spin_lock_irqsave(&mp->lock, flags);
399 
400     __mace_set_address(dev, addr);
401 
402     /* note: setting ADDRCHG clears ENRCV */
403     out_8(&mb->maccc, mp->maccc);
404 
405     spin_unlock_irqrestore(&mp->lock, flags);
406     return 0;
407 }
408 
409 static inline void mace_clean_rings(struct mace_data *mp)
410 {
411     int i;
412 
413     /* free some skb's */
414     for (i = 0; i < N_RX_RING; ++i) {
415         if (mp->rx_bufs[i] != NULL) {
416             dev_kfree_skb(mp->rx_bufs[i]);
417             mp->rx_bufs[i] = NULL;
418         }
419     }
420     for (i = mp->tx_empty; i != mp->tx_fill; ) {
421         dev_kfree_skb(mp->tx_bufs[i]);
422         if (++i >= N_TX_RING)
423             i = 0;
424     }
425 }
426 
427 static int mace_open(struct net_device *dev)
428 {
429     struct mace_data *mp = netdev_priv(dev);
430     volatile struct mace __iomem *mb = mp->mace;
431     volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
432     volatile struct dbdma_regs __iomem *td = mp->tx_dma;
433     volatile struct dbdma_cmd *cp;
434     int i;
435     struct sk_buff *skb;
436     unsigned char *data;
437 
438     /* reset the chip */
439     mace_reset(dev);
440 
441     /* initialize list of sk_buffs for receiving and set up recv dma */
442     mace_clean_rings(mp);
443     memset((char *)mp->rx_cmds, 0, N_RX_RING * sizeof(struct dbdma_cmd));
444     cp = mp->rx_cmds;
445     for (i = 0; i < N_RX_RING - 1; ++i) {
446         skb = netdev_alloc_skb(dev, RX_BUFLEN + 2);
447         if (!skb) {
448             data = dummy_buf;
449         } else {
450             skb_reserve(skb, 2);        /* so IP header lands on 4-byte bdry */
451             data = skb->data;
452         }
453         mp->rx_bufs[i] = skb;
454         cp->req_count = cpu_to_le16(RX_BUFLEN);
455         cp->command = cpu_to_le16(INPUT_LAST + INTR_ALWAYS);
456         cp->phy_addr = cpu_to_le32(virt_to_bus(data));
457         cp->xfer_status = 0;
458         ++cp;
459     }
460     mp->rx_bufs[i] = NULL;
461     cp->command = cpu_to_le16(DBDMA_STOP);
462     mp->rx_fill = i;
463     mp->rx_empty = 0;
464 
465     /* Put a branch back to the beginning of the receive command list */
466     ++cp;
467     cp->command = cpu_to_le16(DBDMA_NOP + BR_ALWAYS);
468     cp->cmd_dep = cpu_to_le32(virt_to_bus(mp->rx_cmds));
469 
470     /* start rx dma */
471     out_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
472     out_le32(&rd->cmdptr, virt_to_bus(mp->rx_cmds));
473     out_le32(&rd->control, (RUN << 16) | RUN);
474 
475     /* put a branch at the end of the tx command list */
476     cp = mp->tx_cmds + NCMDS_TX * N_TX_RING;
477     cp->command = cpu_to_le16(DBDMA_NOP + BR_ALWAYS);
478     cp->cmd_dep = cpu_to_le32(virt_to_bus(mp->tx_cmds));
479 
480     /* reset tx dma */
481     out_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16);
482     out_le32(&td->cmdptr, virt_to_bus(mp->tx_cmds));
483     mp->tx_fill = 0;
484     mp->tx_empty = 0;
485     mp->tx_fullup = 0;
486     mp->tx_active = 0;
487     mp->tx_bad_runt = 0;
488 
489     /* turn it on! */
490     out_8(&mb->maccc, mp->maccc);
491     /* enable all interrupts except receive interrupts */
492     out_8(&mb->imr, RCVINT);
493 
494     return 0;
495 }
496 
497 static int mace_close(struct net_device *dev)
498 {
499     struct mace_data *mp = netdev_priv(dev);
500     volatile struct mace __iomem *mb = mp->mace;
501     volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
502     volatile struct dbdma_regs __iomem *td = mp->tx_dma;
503 
504     /* disable rx and tx */
505     out_8(&mb->maccc, 0);
506     out_8(&mb->imr, 0xff);              /* disable all intrs */
507 
508     /* disable rx and tx dma */
509     rd->control = cpu_to_le32((RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
510     td->control = cpu_to_le32((RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
511 
512     mace_clean_rings(mp);
513 
514     return 0;
515 }
516 
517 static inline void mace_set_timeout(struct net_device *dev)
518 {
519     struct mace_data *mp = netdev_priv(dev);
520 
521     if (mp->timeout_active)
522         del_timer(&mp->tx_timeout);
523     mp->tx_timeout.expires = jiffies + TX_TIMEOUT;
524     mp->tx_timeout.function = mace_tx_timeout;
525     mp->tx_timeout.data = (unsigned long) dev;
526     add_timer(&mp->tx_timeout);
527     mp->timeout_active = 1;
528 }
529 
530 static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev)
531 {
532     struct mace_data *mp = netdev_priv(dev);
533     volatile struct dbdma_regs __iomem *td = mp->tx_dma;
534     volatile struct dbdma_cmd *cp, *np;
535     unsigned long flags;
536     int fill, next, len;
537 
538     /* see if there's a free slot in the tx ring */
539     spin_lock_irqsave(&mp->lock, flags);
540     fill = mp->tx_fill;
541     next = fill + 1;
542     if (next >= N_TX_RING)
543         next = 0;
544     if (next == mp->tx_empty) {
545         netif_stop_queue(dev);
546         mp->tx_fullup = 1;
547         spin_unlock_irqrestore(&mp->lock, flags);
548         return NETDEV_TX_BUSY;          /* can't take it at the moment */
549     }
550     spin_unlock_irqrestore(&mp->lock, flags);
551 
552     /* partially fill in the dma command block */
553     len = skb->len;
554     if (len > ETH_FRAME_LEN) {
555         printk(KERN_DEBUG "mace: xmit frame too long (%d)\n", len);
556         len = ETH_FRAME_LEN;
557     }
558     mp->tx_bufs[fill] = skb;
559     cp = mp->tx_cmds + NCMDS_TX * fill;
560     cp->req_count = cpu_to_le16(len);
561     cp->phy_addr = cpu_to_le32(virt_to_bus(skb->data));
562 
563     np = mp->tx_cmds + NCMDS_TX * next;
564     out_le16(&np->command, DBDMA_STOP);
565 
566     /* poke the tx dma channel */
567     spin_lock_irqsave(&mp->lock, flags);
568     mp->tx_fill = next;
569     if (!mp->tx_bad_runt && mp->tx_active < MAX_TX_ACTIVE) {
570         out_le16(&cp->xfer_status, 0);
571         out_le16(&cp->command, OUTPUT_LAST);
572         out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));
573         ++mp->tx_active;
574         mace_set_timeout(dev);
575     }
576     if (++next >= N_TX_RING)
577         next = 0;
578     if (next == mp->tx_empty)
579         netif_stop_queue(dev);
580     spin_unlock_irqrestore(&mp->lock, flags);
581 
582     return NETDEV_TX_OK;
583 }
584 
585 static void mace_set_multicast(struct net_device *dev)
586 {
587     struct mace_data *mp = netdev_priv(dev);
588     volatile struct mace __iomem *mb = mp->mace;
589     int i;
590     u32 crc;
591     unsigned long flags;
592 
593     spin_lock_irqsave(&mp->lock, flags);
594     mp->maccc &= ~PROM;
595     if (dev->flags & IFF_PROMISC) {
596         mp->maccc |= PROM;
597     } else {
598         unsigned char multicast_filter[8];
599         struct netdev_hw_addr *ha;
600 
601         if (dev->flags & IFF_ALLMULTI) {
602             for (i = 0; i < 8; i++)
603                 multicast_filter[i] = 0xff;
604         } else {
605             for (i = 0; i < 8; i++)
606                 multicast_filter[i] = 0;
607             netdev_for_each_mc_addr(ha, dev) {
608                 crc = ether_crc_le(6, ha->addr);
609                 i = crc >> 26;  /* bit number in multicast_filter */
610                 multicast_filter[i >> 3] |= 1 << (i & 7);
611             }
612         }
613 #if 0
614         printk("Multicast filter :");
615         for (i = 0; i < 8; i++)
616             printk("%02x ", multicast_filter[i]);
617         printk("\n");
618 #endif
619 
620         if (mp->chipid == BROKEN_ADDRCHG_REV)
621             out_8(&mb->iac, LOGADDR);
622         else {
623             out_8(&mb->iac, ADDRCHG | LOGADDR);
624             while ((in_8(&mb->iac) & ADDRCHG) != 0)
625                 ;
626         }
627         for (i = 0; i < 8; ++i)
628             out_8(&mb->ladrf, multicast_filter[i]);
629         if (mp->chipid != BROKEN_ADDRCHG_REV)
630             out_8(&mb->iac, 0);
631     }
632     /* reset maccc */
633     out_8(&mb->maccc, mp->maccc);
634     spin_unlock_irqrestore(&mp->lock, flags);
635 }
636 
637 static void mace_handle_misc_intrs(struct mace_data *mp, int intr, struct net_device *dev)
638 {
639     volatile struct mace __iomem *mb = mp->mace;
640     static int mace_babbles, mace_jabbers;
641 
642     if (intr & MPCO)
643         dev->stats.rx_missed_errors += 256;
644     dev->stats.rx_missed_errors += in_8(&mb->mpc);   /* reading clears it */
645     if (intr & RNTPCO)
646         dev->stats.rx_length_errors += 256;
647     dev->stats.rx_length_errors += in_8(&mb->rntpc); /* reading clears it */
648     if (intr & CERR)
649         ++dev->stats.tx_heartbeat_errors;
650     if (intr & BABBLE)
651         if (mace_babbles++ < 4)
652             printk(KERN_DEBUG "mace: babbling transmitter\n");
653     if (intr & JABBER)
654         if (mace_jabbers++ < 4)
655             printk(KERN_DEBUG "mace: jabbering transceiver\n");
656 }
657 
658 static irqreturn_t mace_interrupt(int irq, void *dev_id)
659 {
660     struct net_device *dev = (struct net_device *) dev_id;
661     struct mace_data *mp = netdev_priv(dev);
662     volatile struct mace __iomem *mb = mp->mace;
663     volatile struct dbdma_regs __iomem *td = mp->tx_dma;
664     volatile struct dbdma_cmd *cp;
665     int intr, fs, i, stat, x;
666     int xcount, dstat;
667     unsigned long flags;
668     /* static int mace_last_fs, mace_last_xcount; */
669 
670     spin_lock_irqsave(&mp->lock, flags);
671     intr = in_8(&mb->ir);               /* read interrupt register */
672     in_8(&mb->xmtrc);                   /* get retries */
673     mace_handle_misc_intrs(mp, intr, dev);
674 
675     i = mp->tx_empty;
676     while (in_8(&mb->pr) & XMTSV) {
677         del_timer(&mp->tx_timeout);
678         mp->timeout_active = 0;
679         /*
680          * Clear any interrupt indication associated with this status
681          * word.  This appears to unlatch any error indication from
682          * the DMA controller.
683          */
684         intr = in_8(&mb->ir);
685         if (intr != 0)
686             mace_handle_misc_intrs(mp, intr, dev);
687         if (mp->tx_bad_runt) {
688             fs = in_8(&mb->xmtfs);
689             mp->tx_bad_runt = 0;
690             out_8(&mb->xmtfc, AUTO_PAD_XMIT);
691             continue;
692         }
693         dstat = le32_to_cpu(td->status);
694         /* stop DMA controller */
695         out_le32(&td->control, RUN << 16);
696         /*
697          * xcount is the number of complete frames which have been
698          * written to the fifo but for which status has not been read.
699          */
700         xcount = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;
701         if (xcount == 0 || (dstat & DEAD)) {
702             /*
703              * If a packet was aborted before the DMA controller has
704              * finished transferring it, it seems that there are 2 bytes
705              * which are stuck in some buffer somewhere.  These will get
706              * transmitted as soon as we read the frame status (which
707              * reenables the transmit data transfer request).  Turning
708              * off the DMA controller and/or resetting the MACE doesn't
709              * help.  So we disable auto-padding and FCS transmission
710              * so the two bytes will only be a runt packet which should
711              * be ignored by other stations.
712              */
713             out_8(&mb->xmtfc, DXMTFCS);
714         }
715         fs = in_8(&mb->xmtfs);
716         if ((fs & XMTSV) == 0) {
717             printk(KERN_ERR "mace: xmtfs not valid! (fs=%x xc=%d ds=%x)\n",
718                    fs, xcount, dstat);
719             mace_reset(dev);
720                 /*
721                  * XXX mace likes to hang the machine after a xmtfs error.
722                  * This is hard to reproduce, resetting *may* help
723                  */
724         }
725         cp = mp->tx_cmds + NCMDS_TX * i;
726         stat = le16_to_cpu(cp->xfer_status);
727         if ((fs & (UFLO|LCOL|LCAR|RTRY)) || (dstat & DEAD) || xcount == 0) {
728             /*
729              * Check whether there were in fact 2 bytes written to
730              * the transmit FIFO.
731              */
732             udelay(1);
733             x = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;
734             if (x != 0) {
735                 /* there were two bytes with an end-of-packet indication */
736                 mp->tx_bad_runt = 1;
737                 mace_set_timeout(dev);
738             } else {
739                 /*
740                  * Either there weren't the two bytes buffered up, or they
741                  * didn't have an end-of-packet indication.
742                  * We flush the transmit FIFO just in case (by setting the
743                  * XMTFWU bit with the transmitter disabled).
744                  */
745                 out_8(&mb->maccc, in_8(&mb->maccc) & ~ENXMT);
746                 out_8(&mb->fifocc, in_8(&mb->fifocc) | XMTFWU);
747                 udelay(1);
748                 out_8(&mb->maccc, in_8(&mb->maccc) | ENXMT);
749                 out_8(&mb->xmtfc, AUTO_PAD_XMIT);
750             }
751         }
752         /* dma should have finished */
753         if (i == mp->tx_fill) {
754             printk(KERN_DEBUG "mace: tx ring ran out? (fs=%x xc=%d ds=%x)\n",
755                    fs, xcount, dstat);
756             continue;
757         }
758         /* Update stats */
759         if (fs & (UFLO|LCOL|LCAR|RTRY)) {
760             ++dev->stats.tx_errors;
761             if (fs & LCAR)
762                 ++dev->stats.tx_carrier_errors;
763             if (fs & (UFLO|LCOL|RTRY))
764                 ++dev->stats.tx_aborted_errors;
765         } else {
766             dev->stats.tx_bytes += mp->tx_bufs[i]->len;
767             ++dev->stats.tx_packets;
768         }
769         dev_kfree_skb_irq(mp->tx_bufs[i]);
770         --mp->tx_active;
771         if (++i >= N_TX_RING)
772             i = 0;
773 #if 0
774         mace_last_fs = fs;
775         mace_last_xcount = xcount;
776 #endif
777     }
778 
779     if (i != mp->tx_empty) {
780         mp->tx_fullup = 0;
781         netif_wake_queue(dev);
782     }
783     mp->tx_empty = i;
784     i += mp->tx_active;
785     if (i >= N_TX_RING)
786         i -= N_TX_RING;
787     if (!mp->tx_bad_runt && i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE) {
788         do {
789             /* set up the next one */
790             cp = mp->tx_cmds + NCMDS_TX * i;
791             out_le16(&cp->xfer_status, 0);
792             out_le16(&cp->command, OUTPUT_LAST);
793             ++mp->tx_active;
794             if (++i >= N_TX_RING)
795                 i = 0;
796         } while (i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE);
797         out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));
798         mace_set_timeout(dev);
799     }
800     spin_unlock_irqrestore(&mp->lock, flags);
801     return IRQ_HANDLED;
802 }
803 
804 static void mace_tx_timeout(unsigned long data)
805 {
806     struct net_device *dev = (struct net_device *) data;
807     struct mace_data *mp = netdev_priv(dev);
808     volatile struct mace __iomem *mb = mp->mace;
809     volatile struct dbdma_regs __iomem *td = mp->tx_dma;
810     volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
811     volatile struct dbdma_cmd *cp;
812     unsigned long flags;
813     int i;
814 
815     spin_lock_irqsave(&mp->lock, flags);
816     mp->timeout_active = 0;
817     if (mp->tx_active == 0 && !mp->tx_bad_runt)
818         goto out;
819 
820     /* update various counters */
821     mace_handle_misc_intrs(mp, in_8(&mb->ir), dev);
822 
823     cp = mp->tx_cmds + NCMDS_TX * mp->tx_empty;
824 
825     /* turn off both tx and rx and reset the chip */
826     out_8(&mb->maccc, 0);
827     printk(KERN_ERR "mace: transmit timeout - resetting\n");
828     dbdma_reset(td);
829     mace_reset(dev);
830 
831     /* restart rx dma */
832     cp = bus_to_virt(le32_to_cpu(rd->cmdptr));
833     dbdma_reset(rd);
834     out_le16(&cp->xfer_status, 0);
835     out_le32(&rd->cmdptr, virt_to_bus(cp));
836     out_le32(&rd->control, (RUN << 16) | RUN);
837 
838     /* fix up the transmit side */
839     i = mp->tx_empty;
840     mp->tx_active = 0;
841     ++dev->stats.tx_errors;
842     if (mp->tx_bad_runt) {
843         mp->tx_bad_runt = 0;
844     } else if (i != mp->tx_fill) {
845         dev_kfree_skb(mp->tx_bufs[i]);
846         if (++i >= N_TX_RING)
847             i = 0;
848         mp->tx_empty = i;
849     }
850     mp->tx_fullup = 0;
851     netif_wake_queue(dev);
852     if (i != mp->tx_fill) {
853         cp = mp->tx_cmds + NCMDS_TX * i;
854         out_le16(&cp->xfer_status, 0);
855         out_le16(&cp->command, OUTPUT_LAST);
856         out_le32(&td->cmdptr, virt_to_bus(cp));
857         out_le32(&td->control, (RUN << 16) | RUN);
858         ++mp->tx_active;
859         mace_set_timeout(dev);
860     }
861 
862     /* turn it back on */
863     out_8(&mb->imr, RCVINT);
864     out_8(&mb->maccc, mp->maccc);
865 
866 out:
867     spin_unlock_irqrestore(&mp->lock, flags);
868 }
869 
870 static irqreturn_t mace_txdma_intr(int irq, void *dev_id)
871 {
872         return IRQ_HANDLED;
873 }
874 
875 static irqreturn_t mace_rxdma_intr(int irq, void *dev_id)
876 {
877     struct net_device *dev = (struct net_device *) dev_id;
878     struct mace_data *mp = netdev_priv(dev);
879     volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
880     volatile struct dbdma_cmd *cp, *np;
881     int i, nb, stat, next;
882     struct sk_buff *skb;
883     unsigned frame_status;
884     static int mace_lost_status;
885     unsigned char *data;
886     unsigned long flags;
887 
888     spin_lock_irqsave(&mp->lock, flags);
889     for (i = mp->rx_empty; i != mp->rx_fill; ) {
890         cp = mp->rx_cmds + i;
891         stat = le16_to_cpu(cp->xfer_status);
892         if ((stat & ACTIVE) == 0) {
893             next = i + 1;
894             if (next >= N_RX_RING)
895                 next = 0;
896             np = mp->rx_cmds + next;
897             if (next != mp->rx_fill &&
898                 (le16_to_cpu(np->xfer_status) & ACTIVE) != 0) {
899                 printk(KERN_DEBUG "mace: lost a status word\n");
900                 ++mace_lost_status;
901             } else
902                 break;
903         }
904         nb = le16_to_cpu(cp->req_count) - le16_to_cpu(cp->res_count);
905         out_le16(&cp->command, DBDMA_STOP);
906         /* got a packet, have a look at it */
907         skb = mp->rx_bufs[i];
908         if (!skb) {
909             ++dev->stats.rx_dropped;
910         } else if (nb > 8) {
911             data = skb->data;
912             frame_status = (data[nb-3] << 8) + data[nb-4];
913             if (frame_status & (RS_OFLO|RS_CLSN|RS_FRAMERR|RS_FCSERR)) {
914                 ++dev->stats.rx_errors;
915                 if (frame_status & RS_OFLO)
916                     ++dev->stats.rx_over_errors;
917                 if (frame_status & RS_FRAMERR)
918                     ++dev->stats.rx_frame_errors;
919                 if (frame_status & RS_FCSERR)
920                     ++dev->stats.rx_crc_errors;
921             } else {
922                 /* Mace feature AUTO_STRIP_RCV is on by default, dropping the
923                  * FCS on frames with 802.3 headers. This means that Ethernet
924                  * frames have 8 extra octets at the end, while 802.3 frames
925                  * have only 4. We need to correctly account for this. */
926                 if (*(unsigned short *)(data+12) < 1536) /* 802.3 header */
927                     nb -= 4;
928                 else    /* Ethernet header; mace includes FCS */
929                     nb -= 8;
930                 skb_put(skb, nb);
931                 skb->protocol = eth_type_trans(skb, dev);
932                 dev->stats.rx_bytes += skb->len;
933                 netif_rx(skb);
934                 mp->rx_bufs[i] = NULL;
935                 ++dev->stats.rx_packets;
936             }
937         } else {
938             ++dev->stats.rx_errors;
939             ++dev->stats.rx_length_errors;
940         }
941 
942         /* advance to next */
943         if (++i >= N_RX_RING)
944             i = 0;
945     }
946     mp->rx_empty = i;
947 
948     i = mp->rx_fill;
949     for (;;) {
950         next = i + 1;
951         if (next >= N_RX_RING)
952             next = 0;
953         if (next == mp->rx_empty)
954             break;
955         cp = mp->rx_cmds + i;
956         skb = mp->rx_bufs[i];
957         if (!skb) {
958             skb = netdev_alloc_skb(dev, RX_BUFLEN + 2);
959             if (skb) {
960                 skb_reserve(skb, 2);
961                 mp->rx_bufs[i] = skb;
962             }
963         }
964         cp->req_count = cpu_to_le16(RX_BUFLEN);
965         data = skb? skb->data: dummy_buf;
966         cp->phy_addr = cpu_to_le32(virt_to_bus(data));
967         out_le16(&cp->xfer_status, 0);
968         out_le16(&cp->command, INPUT_LAST + INTR_ALWAYS);
969 #if 0
970         if ((le32_to_cpu(rd->status) & ACTIVE) != 0) {
971             out_le32(&rd->control, (PAUSE << 16) | PAUSE);
972             while ((in_le32(&rd->status) & ACTIVE) != 0)
973                 ;
974         }
975 #endif
976         i = next;
977     }
978     if (i != mp->rx_fill) {
979         out_le32(&rd->control, ((RUN|WAKE) << 16) | (RUN|WAKE));
980         mp->rx_fill = i;
981     }
982     spin_unlock_irqrestore(&mp->lock, flags);
983     return IRQ_HANDLED;
984 }
985 
986 static const struct of_device_id mace_match[] =
987 {
988         {
989         .name           = "mace",
990         },
991         {},
992 };
993 MODULE_DEVICE_TABLE (of, mace_match);
994 
995 static struct macio_driver mace_driver =
996 {
997         .driver = {
998                 .name           = "mace",
999                 .owner          = THIS_MODULE,
1000                 .of_match_table = mace_match,
1001         },
1002         .probe          = mace_probe,
1003         .remove         = mace_remove,
1004 };
1005 
1006 
1007 static int __init mace_init(void)
1008 {
1009         return macio_register_driver(&mace_driver);
1010 }
1011 
1012 static void __exit mace_cleanup(void)
1013 {
1014         macio_unregister_driver(&mace_driver);
1015 
1016         kfree(dummy_buf);
1017         dummy_buf = NULL;
1018 }
1019 
1020 MODULE_AUTHOR("Paul Mackerras");
1021 MODULE_DESCRIPTION("PowerMac MACE driver.");
1022 module_param(port_aaui, int, 0);
1023 MODULE_PARM_DESC(port_aaui, "MACE uses AAUI port (0-1)");
1024 MODULE_LICENSE("GPL");
1025 
1026 module_init(mace_init);
1027 module_exit(mace_cleanup);
1028 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us