Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/drivers/net/ethernet/apple/mace.c

  1 /*
  2  * Network device driver for the MACE ethernet controller on
  3  * Apple Powermacs.  Assumes it's under a DBDMA controller.
  4  *
  5  * Copyright (C) 1996 Paul Mackerras.
  6  */
  7 
  8 #include <linux/module.h>
  9 #include <linux/kernel.h>
 10 #include <linux/netdevice.h>
 11 #include <linux/etherdevice.h>
 12 #include <linux/delay.h>
 13 #include <linux/string.h>
 14 #include <linux/timer.h>
 15 #include <linux/init.h>
 16 #include <linux/interrupt.h>
 17 #include <linux/crc32.h>
 18 #include <linux/spinlock.h>
 19 #include <linux/bitrev.h>
 20 #include <linux/slab.h>
 21 #include <asm/prom.h>
 22 #include <asm/dbdma.h>
 23 #include <asm/io.h>
 24 #include <asm/pgtable.h>
 25 #include <asm/macio.h>
 26 
 27 #include "mace.h"
 28 
 29 static int port_aaui = -1;
 30 
 31 #define N_RX_RING       8
 32 #define N_TX_RING       6
 33 #define MAX_TX_ACTIVE   1
 34 #define NCMDS_TX        1       /* dma commands per element in tx ring */
 35 #define RX_BUFLEN       (ETH_FRAME_LEN + 8)
 36 #define TX_TIMEOUT      HZ      /* 1 second */
 37 
 38 /* Chip rev needs workaround on HW & multicast addr change */
 39 #define BROKEN_ADDRCHG_REV      0x0941
 40 
 41 /* Bits in transmit DMA status */
 42 #define TX_DMA_ERR      0x80
 43 
 44 struct mace_data {
 45     volatile struct mace __iomem *mace;
 46     volatile struct dbdma_regs __iomem *tx_dma;
 47     int tx_dma_intr;
 48     volatile struct dbdma_regs __iomem *rx_dma;
 49     int rx_dma_intr;
 50     volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */
 51     volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */
 52     struct sk_buff *rx_bufs[N_RX_RING];
 53     int rx_fill;
 54     int rx_empty;
 55     struct sk_buff *tx_bufs[N_TX_RING];
 56     int tx_fill;
 57     int tx_empty;
 58     unsigned char maccc;
 59     unsigned char tx_fullup;
 60     unsigned char tx_active;
 61     unsigned char tx_bad_runt;
 62     struct timer_list tx_timeout;
 63     int timeout_active;
 64     int port_aaui;
 65     int chipid;
 66     struct macio_dev *mdev;
 67     spinlock_t lock;
 68 };
 69 
 70 /*
 71  * Number of bytes of private data per MACE: allow enough for
 72  * the rx and tx dma commands plus a branch dma command each,
 73  * and another 16 bytes to allow us to align the dma command
 74  * buffers on a 16 byte boundary.
 75  */
 76 #define PRIV_BYTES      (sizeof(struct mace_data) \
 77         + (N_RX_RING + NCMDS_TX * N_TX_RING + 3) * sizeof(struct dbdma_cmd))
 78 
 79 static int mace_open(struct net_device *dev);
 80 static int mace_close(struct net_device *dev);
 81 static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev);
 82 static void mace_set_multicast(struct net_device *dev);
 83 static void mace_reset(struct net_device *dev);
 84 static int mace_set_address(struct net_device *dev, void *addr);
 85 static irqreturn_t mace_interrupt(int irq, void *dev_id);
 86 static irqreturn_t mace_txdma_intr(int irq, void *dev_id);
 87 static irqreturn_t mace_rxdma_intr(int irq, void *dev_id);
 88 static void mace_set_timeout(struct net_device *dev);
 89 static void mace_tx_timeout(unsigned long data);
 90 static inline void dbdma_reset(volatile struct dbdma_regs __iomem *dma);
 91 static inline void mace_clean_rings(struct mace_data *mp);
 92 static void __mace_set_address(struct net_device *dev, void *addr);
 93 
 94 /*
 95  * If we can't get a skbuff when we need it, we use this area for DMA.
 96  */
 97 static unsigned char *dummy_buf;
 98 
 99 static const struct net_device_ops mace_netdev_ops = {
100         .ndo_open               = mace_open,
101         .ndo_stop               = mace_close,
102         .ndo_start_xmit         = mace_xmit_start,
103         .ndo_set_rx_mode        = mace_set_multicast,
104         .ndo_set_mac_address    = mace_set_address,
105         .ndo_change_mtu         = eth_change_mtu,
106         .ndo_validate_addr      = eth_validate_addr,
107 };
108 
109 static int mace_probe(struct macio_dev *mdev, const struct of_device_id *match)
110 {
111         struct device_node *mace = macio_get_of_node(mdev);
112         struct net_device *dev;
113         struct mace_data *mp;
114         const unsigned char *addr;
115         int j, rev, rc = -EBUSY;
116 
117         if (macio_resource_count(mdev) != 3 || macio_irq_count(mdev) != 3) {
118                 printk(KERN_ERR "can't use MACE %s: need 3 addrs and 3 irqs\n",
119                        mace->full_name);
120                 return -ENODEV;
121         }
122 
123         addr = of_get_property(mace, "mac-address", NULL);
124         if (addr == NULL) {
125                 addr = of_get_property(mace, "local-mac-address", NULL);
126                 if (addr == NULL) {
127                         printk(KERN_ERR "Can't get mac-address for MACE %s\n",
128                                mace->full_name);
129                         return -ENODEV;
130                 }
131         }
132 
133         /*
134          * lazy allocate the driver-wide dummy buffer. (Note that we
135          * never have more than one MACE in the system anyway)
136          */
137         if (dummy_buf == NULL) {
138                 dummy_buf = kmalloc(RX_BUFLEN+2, GFP_KERNEL);
139                 if (dummy_buf == NULL)
140                         return -ENOMEM;
141         }
142 
143         if (macio_request_resources(mdev, "mace")) {
144                 printk(KERN_ERR "MACE: can't request IO resources !\n");
145                 return -EBUSY;
146         }
147 
148         dev = alloc_etherdev(PRIV_BYTES);
149         if (!dev) {
150                 rc = -ENOMEM;
151                 goto err_release;
152         }
153         SET_NETDEV_DEV(dev, &mdev->ofdev.dev);
154 
155         mp = netdev_priv(dev);
156         mp->mdev = mdev;
157         macio_set_drvdata(mdev, dev);
158 
159         dev->base_addr = macio_resource_start(mdev, 0);
160         mp->mace = ioremap(dev->base_addr, 0x1000);
161         if (mp->mace == NULL) {
162                 printk(KERN_ERR "MACE: can't map IO resources !\n");
163                 rc = -ENOMEM;
164                 goto err_free;
165         }
166         dev->irq = macio_irq(mdev, 0);
167 
168         rev = addr[0] == 0 && addr[1] == 0xA0;
169         for (j = 0; j < 6; ++j) {
170                 dev->dev_addr[j] = rev ? bitrev8(addr[j]): addr[j];
171         }
172         mp->chipid = (in_8(&mp->mace->chipid_hi) << 8) |
173                         in_8(&mp->mace->chipid_lo);
174 
175 
176         mp = netdev_priv(dev);
177         mp->maccc = ENXMT | ENRCV;
178 
179         mp->tx_dma = ioremap(macio_resource_start(mdev, 1), 0x1000);
180         if (mp->tx_dma == NULL) {
181                 printk(KERN_ERR "MACE: can't map TX DMA resources !\n");
182                 rc = -ENOMEM;
183                 goto err_unmap_io;
184         }
185         mp->tx_dma_intr = macio_irq(mdev, 1);
186 
187         mp->rx_dma = ioremap(macio_resource_start(mdev, 2), 0x1000);
188         if (mp->rx_dma == NULL) {
189                 printk(KERN_ERR "MACE: can't map RX DMA resources !\n");
190                 rc = -ENOMEM;
191                 goto err_unmap_tx_dma;
192         }
193         mp->rx_dma_intr = macio_irq(mdev, 2);
194 
195         mp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(mp + 1);
196         mp->rx_cmds = mp->tx_cmds + NCMDS_TX * N_TX_RING + 1;
197 
198         memset((char *) mp->tx_cmds, 0,
199                (NCMDS_TX*N_TX_RING + N_RX_RING + 2) * sizeof(struct dbdma_cmd));
200         init_timer(&mp->tx_timeout);
201         spin_lock_init(&mp->lock);
202         mp->timeout_active = 0;
203 
204         if (port_aaui >= 0)
205                 mp->port_aaui = port_aaui;
206         else {
207                 /* Apple Network Server uses the AAUI port */
208                 if (of_machine_is_compatible("AAPL,ShinerESB"))
209                         mp->port_aaui = 1;
210                 else {
211 #ifdef CONFIG_MACE_AAUI_PORT
212                         mp->port_aaui = 1;
213 #else
214                         mp->port_aaui = 0;
215 #endif
216                 }
217         }
218 
219         dev->netdev_ops = &mace_netdev_ops;
220 
221         /*
222          * Most of what is below could be moved to mace_open()
223          */
224         mace_reset(dev);
225 
226         rc = request_irq(dev->irq, mace_interrupt, 0, "MACE", dev);
227         if (rc) {
228                 printk(KERN_ERR "MACE: can't get irq %d\n", dev->irq);
229                 goto err_unmap_rx_dma;
230         }
231         rc = request_irq(mp->tx_dma_intr, mace_txdma_intr, 0, "MACE-txdma", dev);
232         if (rc) {
233                 printk(KERN_ERR "MACE: can't get irq %d\n", mp->tx_dma_intr);
234                 goto err_free_irq;
235         }
236         rc = request_irq(mp->rx_dma_intr, mace_rxdma_intr, 0, "MACE-rxdma", dev);
237         if (rc) {
238                 printk(KERN_ERR "MACE: can't get irq %d\n", mp->rx_dma_intr);
239                 goto err_free_tx_irq;
240         }
241 
242         rc = register_netdev(dev);
243         if (rc) {
244                 printk(KERN_ERR "MACE: Cannot register net device, aborting.\n");
245                 goto err_free_rx_irq;
246         }
247 
248         printk(KERN_INFO "%s: MACE at %pM, chip revision %d.%d\n",
249                dev->name, dev->dev_addr,
250                mp->chipid >> 8, mp->chipid & 0xff);
251 
252         return 0;
253 
254  err_free_rx_irq:
255         free_irq(macio_irq(mdev, 2), dev);
256  err_free_tx_irq:
257         free_irq(macio_irq(mdev, 1), dev);
258  err_free_irq:
259         free_irq(macio_irq(mdev, 0), dev);
260  err_unmap_rx_dma:
261         iounmap(mp->rx_dma);
262  err_unmap_tx_dma:
263         iounmap(mp->tx_dma);
264  err_unmap_io:
265         iounmap(mp->mace);
266  err_free:
267         free_netdev(dev);
268  err_release:
269         macio_release_resources(mdev);
270 
271         return rc;
272 }
273 
274 static int mace_remove(struct macio_dev *mdev)
275 {
276         struct net_device *dev = macio_get_drvdata(mdev);
277         struct mace_data *mp;
278 
279         BUG_ON(dev == NULL);
280 
281         macio_set_drvdata(mdev, NULL);
282 
283         mp = netdev_priv(dev);
284 
285         unregister_netdev(dev);
286 
287         free_irq(dev->irq, dev);
288         free_irq(mp->tx_dma_intr, dev);
289         free_irq(mp->rx_dma_intr, dev);
290 
291         iounmap(mp->rx_dma);
292         iounmap(mp->tx_dma);
293         iounmap(mp->mace);
294 
295         free_netdev(dev);
296 
297         macio_release_resources(mdev);
298 
299         return 0;
300 }
301 
302 static void dbdma_reset(volatile struct dbdma_regs __iomem *dma)
303 {
304     int i;
305 
306     out_le32(&dma->control, (WAKE|FLUSH|PAUSE|RUN) << 16);
307 
308     /*
309      * Yes this looks peculiar, but apparently it needs to be this
310      * way on some machines.
311      */
312     for (i = 200; i > 0; --i)
313         if (ld_le32(&dma->control) & RUN)
314             udelay(1);
315 }
316 
317 static void mace_reset(struct net_device *dev)
318 {
319     struct mace_data *mp = netdev_priv(dev);
320     volatile struct mace __iomem *mb = mp->mace;
321     int i;
322 
323     /* soft-reset the chip */
324     i = 200;
325     while (--i) {
326         out_8(&mb->biucc, SWRST);
327         if (in_8(&mb->biucc) & SWRST) {
328             udelay(10);
329             continue;
330         }
331         break;
332     }
333     if (!i) {
334         printk(KERN_ERR "mace: cannot reset chip!\n");
335         return;
336     }
337 
338     out_8(&mb->imr, 0xff);      /* disable all intrs for now */
339     i = in_8(&mb->ir);
340     out_8(&mb->maccc, 0);       /* turn off tx, rx */
341 
342     out_8(&mb->biucc, XMTSP_64);
343     out_8(&mb->utr, RTRD);
344     out_8(&mb->fifocc, RCVFW_32 | XMTFW_16 | XMTFWU | RCVFWU | XMTBRST);
345     out_8(&mb->xmtfc, AUTO_PAD_XMIT); /* auto-pad short frames */
346     out_8(&mb->rcvfc, 0);
347 
348     /* load up the hardware address */
349     __mace_set_address(dev, dev->dev_addr);
350 
351     /* clear the multicast filter */
352     if (mp->chipid == BROKEN_ADDRCHG_REV)
353         out_8(&mb->iac, LOGADDR);
354     else {
355         out_8(&mb->iac, ADDRCHG | LOGADDR);
356         while ((in_8(&mb->iac) & ADDRCHG) != 0)
357                 ;
358     }
359     for (i = 0; i < 8; ++i)
360         out_8(&mb->ladrf, 0);
361 
362     /* done changing address */
363     if (mp->chipid != BROKEN_ADDRCHG_REV)
364         out_8(&mb->iac, 0);
365 
366     if (mp->port_aaui)
367         out_8(&mb->plscc, PORTSEL_AUI + ENPLSIO);
368     else
369         out_8(&mb->plscc, PORTSEL_GPSI + ENPLSIO);
370 }
371 
372 static void __mace_set_address(struct net_device *dev, void *addr)
373 {
374     struct mace_data *mp = netdev_priv(dev);
375     volatile struct mace __iomem *mb = mp->mace;
376     unsigned char *p = addr;
377     int i;
378 
379     /* load up the hardware address */
380     if (mp->chipid == BROKEN_ADDRCHG_REV)
381         out_8(&mb->iac, PHYADDR);
382     else {
383         out_8(&mb->iac, ADDRCHG | PHYADDR);
384         while ((in_8(&mb->iac) & ADDRCHG) != 0)
385             ;
386     }
387     for (i = 0; i < 6; ++i)
388         out_8(&mb->padr, dev->dev_addr[i] = p[i]);
389     if (mp->chipid != BROKEN_ADDRCHG_REV)
390         out_8(&mb->iac, 0);
391 }
392 
393 static int mace_set_address(struct net_device *dev, void *addr)
394 {
395     struct mace_data *mp = netdev_priv(dev);
396     volatile struct mace __iomem *mb = mp->mace;
397     unsigned long flags;
398 
399     spin_lock_irqsave(&mp->lock, flags);
400 
401     __mace_set_address(dev, addr);
402 
403     /* note: setting ADDRCHG clears ENRCV */
404     out_8(&mb->maccc, mp->maccc);
405 
406     spin_unlock_irqrestore(&mp->lock, flags);
407     return 0;
408 }
409 
410 static inline void mace_clean_rings(struct mace_data *mp)
411 {
412     int i;
413 
414     /* free some skb's */
415     for (i = 0; i < N_RX_RING; ++i) {
416         if (mp->rx_bufs[i] != NULL) {
417             dev_kfree_skb(mp->rx_bufs[i]);
418             mp->rx_bufs[i] = NULL;
419         }
420     }
421     for (i = mp->tx_empty; i != mp->tx_fill; ) {
422         dev_kfree_skb(mp->tx_bufs[i]);
423         if (++i >= N_TX_RING)
424             i = 0;
425     }
426 }
427 
428 static int mace_open(struct net_device *dev)
429 {
430     struct mace_data *mp = netdev_priv(dev);
431     volatile struct mace __iomem *mb = mp->mace;
432     volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
433     volatile struct dbdma_regs __iomem *td = mp->tx_dma;
434     volatile struct dbdma_cmd *cp;
435     int i;
436     struct sk_buff *skb;
437     unsigned char *data;
438 
439     /* reset the chip */
440     mace_reset(dev);
441 
442     /* initialize list of sk_buffs for receiving and set up recv dma */
443     mace_clean_rings(mp);
444     memset((char *)mp->rx_cmds, 0, N_RX_RING * sizeof(struct dbdma_cmd));
445     cp = mp->rx_cmds;
446     for (i = 0; i < N_RX_RING - 1; ++i) {
447         skb = netdev_alloc_skb(dev, RX_BUFLEN + 2);
448         if (!skb) {
449             data = dummy_buf;
450         } else {
451             skb_reserve(skb, 2);        /* so IP header lands on 4-byte bdry */
452             data = skb->data;
453         }
454         mp->rx_bufs[i] = skb;
455         st_le16(&cp->req_count, RX_BUFLEN);
456         st_le16(&cp->command, INPUT_LAST + INTR_ALWAYS);
457         st_le32(&cp->phy_addr, virt_to_bus(data));
458         cp->xfer_status = 0;
459         ++cp;
460     }
461     mp->rx_bufs[i] = NULL;
462     st_le16(&cp->command, DBDMA_STOP);
463     mp->rx_fill = i;
464     mp->rx_empty = 0;
465 
466     /* Put a branch back to the beginning of the receive command list */
467     ++cp;
468     st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS);
469     st_le32(&cp->cmd_dep, virt_to_bus(mp->rx_cmds));
470 
471     /* start rx dma */
472     out_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
473     out_le32(&rd->cmdptr, virt_to_bus(mp->rx_cmds));
474     out_le32(&rd->control, (RUN << 16) | RUN);
475 
476     /* put a branch at the end of the tx command list */
477     cp = mp->tx_cmds + NCMDS_TX * N_TX_RING;
478     st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS);
479     st_le32(&cp->cmd_dep, virt_to_bus(mp->tx_cmds));
480 
481     /* reset tx dma */
482     out_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16);
483     out_le32(&td->cmdptr, virt_to_bus(mp->tx_cmds));
484     mp->tx_fill = 0;
485     mp->tx_empty = 0;
486     mp->tx_fullup = 0;
487     mp->tx_active = 0;
488     mp->tx_bad_runt = 0;
489 
490     /* turn it on! */
491     out_8(&mb->maccc, mp->maccc);
492     /* enable all interrupts except receive interrupts */
493     out_8(&mb->imr, RCVINT);
494 
495     return 0;
496 }
497 
498 static int mace_close(struct net_device *dev)
499 {
500     struct mace_data *mp = netdev_priv(dev);
501     volatile struct mace __iomem *mb = mp->mace;
502     volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
503     volatile struct dbdma_regs __iomem *td = mp->tx_dma;
504 
505     /* disable rx and tx */
506     out_8(&mb->maccc, 0);
507     out_8(&mb->imr, 0xff);              /* disable all intrs */
508 
509     /* disable rx and tx dma */
510     st_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
511     st_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
512 
513     mace_clean_rings(mp);
514 
515     return 0;
516 }
517 
518 static inline void mace_set_timeout(struct net_device *dev)
519 {
520     struct mace_data *mp = netdev_priv(dev);
521 
522     if (mp->timeout_active)
523         del_timer(&mp->tx_timeout);
524     mp->tx_timeout.expires = jiffies + TX_TIMEOUT;
525     mp->tx_timeout.function = mace_tx_timeout;
526     mp->tx_timeout.data = (unsigned long) dev;
527     add_timer(&mp->tx_timeout);
528     mp->timeout_active = 1;
529 }
530 
531 static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev)
532 {
533     struct mace_data *mp = netdev_priv(dev);
534     volatile struct dbdma_regs __iomem *td = mp->tx_dma;
535     volatile struct dbdma_cmd *cp, *np;
536     unsigned long flags;
537     int fill, next, len;
538 
539     /* see if there's a free slot in the tx ring */
540     spin_lock_irqsave(&mp->lock, flags);
541     fill = mp->tx_fill;
542     next = fill + 1;
543     if (next >= N_TX_RING)
544         next = 0;
545     if (next == mp->tx_empty) {
546         netif_stop_queue(dev);
547         mp->tx_fullup = 1;
548         spin_unlock_irqrestore(&mp->lock, flags);
549         return NETDEV_TX_BUSY;          /* can't take it at the moment */
550     }
551     spin_unlock_irqrestore(&mp->lock, flags);
552 
553     /* partially fill in the dma command block */
554     len = skb->len;
555     if (len > ETH_FRAME_LEN) {
556         printk(KERN_DEBUG "mace: xmit frame too long (%d)\n", len);
557         len = ETH_FRAME_LEN;
558     }
559     mp->tx_bufs[fill] = skb;
560     cp = mp->tx_cmds + NCMDS_TX * fill;
561     st_le16(&cp->req_count, len);
562     st_le32(&cp->phy_addr, virt_to_bus(skb->data));
563 
564     np = mp->tx_cmds + NCMDS_TX * next;
565     out_le16(&np->command, DBDMA_STOP);
566 
567     /* poke the tx dma channel */
568     spin_lock_irqsave(&mp->lock, flags);
569     mp->tx_fill = next;
570     if (!mp->tx_bad_runt && mp->tx_active < MAX_TX_ACTIVE) {
571         out_le16(&cp->xfer_status, 0);
572         out_le16(&cp->command, OUTPUT_LAST);
573         out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));
574         ++mp->tx_active;
575         mace_set_timeout(dev);
576     }
577     if (++next >= N_TX_RING)
578         next = 0;
579     if (next == mp->tx_empty)
580         netif_stop_queue(dev);
581     spin_unlock_irqrestore(&mp->lock, flags);
582 
583     return NETDEV_TX_OK;
584 }
585 
586 static void mace_set_multicast(struct net_device *dev)
587 {
588     struct mace_data *mp = netdev_priv(dev);
589     volatile struct mace __iomem *mb = mp->mace;
590     int i;
591     u32 crc;
592     unsigned long flags;
593 
594     spin_lock_irqsave(&mp->lock, flags);
595     mp->maccc &= ~PROM;
596     if (dev->flags & IFF_PROMISC) {
597         mp->maccc |= PROM;
598     } else {
599         unsigned char multicast_filter[8];
600         struct netdev_hw_addr *ha;
601 
602         if (dev->flags & IFF_ALLMULTI) {
603             for (i = 0; i < 8; i++)
604                 multicast_filter[i] = 0xff;
605         } else {
606             for (i = 0; i < 8; i++)
607                 multicast_filter[i] = 0;
608             netdev_for_each_mc_addr(ha, dev) {
609                 crc = ether_crc_le(6, ha->addr);
610                 i = crc >> 26;  /* bit number in multicast_filter */
611                 multicast_filter[i >> 3] |= 1 << (i & 7);
612             }
613         }
614 #if 0
615         printk("Multicast filter :");
616         for (i = 0; i < 8; i++)
617             printk("%02x ", multicast_filter[i]);
618         printk("\n");
619 #endif
620 
621         if (mp->chipid == BROKEN_ADDRCHG_REV)
622             out_8(&mb->iac, LOGADDR);
623         else {
624             out_8(&mb->iac, ADDRCHG | LOGADDR);
625             while ((in_8(&mb->iac) & ADDRCHG) != 0)
626                 ;
627         }
628         for (i = 0; i < 8; ++i)
629             out_8(&mb->ladrf, multicast_filter[i]);
630         if (mp->chipid != BROKEN_ADDRCHG_REV)
631             out_8(&mb->iac, 0);
632     }
633     /* reset maccc */
634     out_8(&mb->maccc, mp->maccc);
635     spin_unlock_irqrestore(&mp->lock, flags);
636 }
637 
638 static void mace_handle_misc_intrs(struct mace_data *mp, int intr, struct net_device *dev)
639 {
640     volatile struct mace __iomem *mb = mp->mace;
641     static int mace_babbles, mace_jabbers;
642 
643     if (intr & MPCO)
644         dev->stats.rx_missed_errors += 256;
645     dev->stats.rx_missed_errors += in_8(&mb->mpc);   /* reading clears it */
646     if (intr & RNTPCO)
647         dev->stats.rx_length_errors += 256;
648     dev->stats.rx_length_errors += in_8(&mb->rntpc); /* reading clears it */
649     if (intr & CERR)
650         ++dev->stats.tx_heartbeat_errors;
651     if (intr & BABBLE)
652         if (mace_babbles++ < 4)
653             printk(KERN_DEBUG "mace: babbling transmitter\n");
654     if (intr & JABBER)
655         if (mace_jabbers++ < 4)
656             printk(KERN_DEBUG "mace: jabbering transceiver\n");
657 }
658 
659 static irqreturn_t mace_interrupt(int irq, void *dev_id)
660 {
661     struct net_device *dev = (struct net_device *) dev_id;
662     struct mace_data *mp = netdev_priv(dev);
663     volatile struct mace __iomem *mb = mp->mace;
664     volatile struct dbdma_regs __iomem *td = mp->tx_dma;
665     volatile struct dbdma_cmd *cp;
666     int intr, fs, i, stat, x;
667     int xcount, dstat;
668     unsigned long flags;
669     /* static int mace_last_fs, mace_last_xcount; */
670 
671     spin_lock_irqsave(&mp->lock, flags);
672     intr = in_8(&mb->ir);               /* read interrupt register */
673     in_8(&mb->xmtrc);                   /* get retries */
674     mace_handle_misc_intrs(mp, intr, dev);
675 
676     i = mp->tx_empty;
677     while (in_8(&mb->pr) & XMTSV) {
678         del_timer(&mp->tx_timeout);
679         mp->timeout_active = 0;
680         /*
681          * Clear any interrupt indication associated with this status
682          * word.  This appears to unlatch any error indication from
683          * the DMA controller.
684          */
685         intr = in_8(&mb->ir);
686         if (intr != 0)
687             mace_handle_misc_intrs(mp, intr, dev);
688         if (mp->tx_bad_runt) {
689             fs = in_8(&mb->xmtfs);
690             mp->tx_bad_runt = 0;
691             out_8(&mb->xmtfc, AUTO_PAD_XMIT);
692             continue;
693         }
694         dstat = ld_le32(&td->status);
695         /* stop DMA controller */
696         out_le32(&td->control, RUN << 16);
697         /*
698          * xcount is the number of complete frames which have been
699          * written to the fifo but for which status has not been read.
700          */
701         xcount = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;
702         if (xcount == 0 || (dstat & DEAD)) {
703             /*
704              * If a packet was aborted before the DMA controller has
705              * finished transferring it, it seems that there are 2 bytes
706              * which are stuck in some buffer somewhere.  These will get
707              * transmitted as soon as we read the frame status (which
708              * reenables the transmit data transfer request).  Turning
709              * off the DMA controller and/or resetting the MACE doesn't
710              * help.  So we disable auto-padding and FCS transmission
711              * so the two bytes will only be a runt packet which should
712              * be ignored by other stations.
713              */
714             out_8(&mb->xmtfc, DXMTFCS);
715         }
716         fs = in_8(&mb->xmtfs);
717         if ((fs & XMTSV) == 0) {
718             printk(KERN_ERR "mace: xmtfs not valid! (fs=%x xc=%d ds=%x)\n",
719                    fs, xcount, dstat);
720             mace_reset(dev);
721                 /*
722                  * XXX mace likes to hang the machine after a xmtfs error.
723                  * This is hard to reproduce, reseting *may* help
724                  */
725         }
726         cp = mp->tx_cmds + NCMDS_TX * i;
727         stat = ld_le16(&cp->xfer_status);
728         if ((fs & (UFLO|LCOL|LCAR|RTRY)) || (dstat & DEAD) || xcount == 0) {
729             /*
730              * Check whether there were in fact 2 bytes written to
731              * the transmit FIFO.
732              */
733             udelay(1);
734             x = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;
735             if (x != 0) {
736                 /* there were two bytes with an end-of-packet indication */
737                 mp->tx_bad_runt = 1;
738                 mace_set_timeout(dev);
739             } else {
740                 /*
741                  * Either there weren't the two bytes buffered up, or they
742                  * didn't have an end-of-packet indication.
743                  * We flush the transmit FIFO just in case (by setting the
744                  * XMTFWU bit with the transmitter disabled).
745                  */
746                 out_8(&mb->maccc, in_8(&mb->maccc) & ~ENXMT);
747                 out_8(&mb->fifocc, in_8(&mb->fifocc) | XMTFWU);
748                 udelay(1);
749                 out_8(&mb->maccc, in_8(&mb->maccc) | ENXMT);
750                 out_8(&mb->xmtfc, AUTO_PAD_XMIT);
751             }
752         }
753         /* dma should have finished */
754         if (i == mp->tx_fill) {
755             printk(KERN_DEBUG "mace: tx ring ran out? (fs=%x xc=%d ds=%x)\n",
756                    fs, xcount, dstat);
757             continue;
758         }
759         /* Update stats */
760         if (fs & (UFLO|LCOL|LCAR|RTRY)) {
761             ++dev->stats.tx_errors;
762             if (fs & LCAR)
763                 ++dev->stats.tx_carrier_errors;
764             if (fs & (UFLO|LCOL|RTRY))
765                 ++dev->stats.tx_aborted_errors;
766         } else {
767             dev->stats.tx_bytes += mp->tx_bufs[i]->len;
768             ++dev->stats.tx_packets;
769         }
770         dev_kfree_skb_irq(mp->tx_bufs[i]);
771         --mp->tx_active;
772         if (++i >= N_TX_RING)
773             i = 0;
774 #if 0
775         mace_last_fs = fs;
776         mace_last_xcount = xcount;
777 #endif
778     }
779 
780     if (i != mp->tx_empty) {
781         mp->tx_fullup = 0;
782         netif_wake_queue(dev);
783     }
784     mp->tx_empty = i;
785     i += mp->tx_active;
786     if (i >= N_TX_RING)
787         i -= N_TX_RING;
788     if (!mp->tx_bad_runt && i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE) {
789         do {
790             /* set up the next one */
791             cp = mp->tx_cmds + NCMDS_TX * i;
792             out_le16(&cp->xfer_status, 0);
793             out_le16(&cp->command, OUTPUT_LAST);
794             ++mp->tx_active;
795             if (++i >= N_TX_RING)
796                 i = 0;
797         } while (i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE);
798         out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));
799         mace_set_timeout(dev);
800     }
801     spin_unlock_irqrestore(&mp->lock, flags);
802     return IRQ_HANDLED;
803 }
804 
805 static void mace_tx_timeout(unsigned long data)
806 {
807     struct net_device *dev = (struct net_device *) data;
808     struct mace_data *mp = netdev_priv(dev);
809     volatile struct mace __iomem *mb = mp->mace;
810     volatile struct dbdma_regs __iomem *td = mp->tx_dma;
811     volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
812     volatile struct dbdma_cmd *cp;
813     unsigned long flags;
814     int i;
815 
816     spin_lock_irqsave(&mp->lock, flags);
817     mp->timeout_active = 0;
818     if (mp->tx_active == 0 && !mp->tx_bad_runt)
819         goto out;
820 
821     /* update various counters */
822     mace_handle_misc_intrs(mp, in_8(&mb->ir), dev);
823 
824     cp = mp->tx_cmds + NCMDS_TX * mp->tx_empty;
825 
826     /* turn off both tx and rx and reset the chip */
827     out_8(&mb->maccc, 0);
828     printk(KERN_ERR "mace: transmit timeout - resetting\n");
829     dbdma_reset(td);
830     mace_reset(dev);
831 
832     /* restart rx dma */
833     cp = bus_to_virt(ld_le32(&rd->cmdptr));
834     dbdma_reset(rd);
835     out_le16(&cp->xfer_status, 0);
836     out_le32(&rd->cmdptr, virt_to_bus(cp));
837     out_le32(&rd->control, (RUN << 16) | RUN);
838 
839     /* fix up the transmit side */
840     i = mp->tx_empty;
841     mp->tx_active = 0;
842     ++dev->stats.tx_errors;
843     if (mp->tx_bad_runt) {
844         mp->tx_bad_runt = 0;
845     } else if (i != mp->tx_fill) {
846         dev_kfree_skb(mp->tx_bufs[i]);
847         if (++i >= N_TX_RING)
848             i = 0;
849         mp->tx_empty = i;
850     }
851     mp->tx_fullup = 0;
852     netif_wake_queue(dev);
853     if (i != mp->tx_fill) {
854         cp = mp->tx_cmds + NCMDS_TX * i;
855         out_le16(&cp->xfer_status, 0);
856         out_le16(&cp->command, OUTPUT_LAST);
857         out_le32(&td->cmdptr, virt_to_bus(cp));
858         out_le32(&td->control, (RUN << 16) | RUN);
859         ++mp->tx_active;
860         mace_set_timeout(dev);
861     }
862 
863     /* turn it back on */
864     out_8(&mb->imr, RCVINT);
865     out_8(&mb->maccc, mp->maccc);
866 
867 out:
868     spin_unlock_irqrestore(&mp->lock, flags);
869 }
870 
871 static irqreturn_t mace_txdma_intr(int irq, void *dev_id)
872 {
873         return IRQ_HANDLED;
874 }
875 
876 static irqreturn_t mace_rxdma_intr(int irq, void *dev_id)
877 {
878     struct net_device *dev = (struct net_device *) dev_id;
879     struct mace_data *mp = netdev_priv(dev);
880     volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
881     volatile struct dbdma_cmd *cp, *np;
882     int i, nb, stat, next;
883     struct sk_buff *skb;
884     unsigned frame_status;
885     static int mace_lost_status;
886     unsigned char *data;
887     unsigned long flags;
888 
889     spin_lock_irqsave(&mp->lock, flags);
890     for (i = mp->rx_empty; i != mp->rx_fill; ) {
891         cp = mp->rx_cmds + i;
892         stat = ld_le16(&cp->xfer_status);
893         if ((stat & ACTIVE) == 0) {
894             next = i + 1;
895             if (next >= N_RX_RING)
896                 next = 0;
897             np = mp->rx_cmds + next;
898             if (next != mp->rx_fill &&
899                 (ld_le16(&np->xfer_status) & ACTIVE) != 0) {
900                 printk(KERN_DEBUG "mace: lost a status word\n");
901                 ++mace_lost_status;
902             } else
903                 break;
904         }
905         nb = ld_le16(&cp->req_count) - ld_le16(&cp->res_count);
906         out_le16(&cp->command, DBDMA_STOP);
907         /* got a packet, have a look at it */
908         skb = mp->rx_bufs[i];
909         if (!skb) {
910             ++dev->stats.rx_dropped;
911         } else if (nb > 8) {
912             data = skb->data;
913             frame_status = (data[nb-3] << 8) + data[nb-4];
914             if (frame_status & (RS_OFLO|RS_CLSN|RS_FRAMERR|RS_FCSERR)) {
915                 ++dev->stats.rx_errors;
916                 if (frame_status & RS_OFLO)
917                     ++dev->stats.rx_over_errors;
918                 if (frame_status & RS_FRAMERR)
919                     ++dev->stats.rx_frame_errors;
920                 if (frame_status & RS_FCSERR)
921                     ++dev->stats.rx_crc_errors;
922             } else {
923                 /* Mace feature AUTO_STRIP_RCV is on by default, dropping the
924                  * FCS on frames with 802.3 headers. This means that Ethernet
925                  * frames have 8 extra octets at the end, while 802.3 frames
926                  * have only 4. We need to correctly account for this. */
927                 if (*(unsigned short *)(data+12) < 1536) /* 802.3 header */
928                     nb -= 4;
929                 else    /* Ethernet header; mace includes FCS */
930                     nb -= 8;
931                 skb_put(skb, nb);
932                 skb->protocol = eth_type_trans(skb, dev);
933                 dev->stats.rx_bytes += skb->len;
934                 netif_rx(skb);
935                 mp->rx_bufs[i] = NULL;
936                 ++dev->stats.rx_packets;
937             }
938         } else {
939             ++dev->stats.rx_errors;
940             ++dev->stats.rx_length_errors;
941         }
942 
943         /* advance to next */
944         if (++i >= N_RX_RING)
945             i = 0;
946     }
947     mp->rx_empty = i;
948 
949     i = mp->rx_fill;
950     for (;;) {
951         next = i + 1;
952         if (next >= N_RX_RING)
953             next = 0;
954         if (next == mp->rx_empty)
955             break;
956         cp = mp->rx_cmds + i;
957         skb = mp->rx_bufs[i];
958         if (!skb) {
959             skb = netdev_alloc_skb(dev, RX_BUFLEN + 2);
960             if (skb) {
961                 skb_reserve(skb, 2);
962                 mp->rx_bufs[i] = skb;
963             }
964         }
965         st_le16(&cp->req_count, RX_BUFLEN);
966         data = skb? skb->data: dummy_buf;
967         st_le32(&cp->phy_addr, virt_to_bus(data));
968         out_le16(&cp->xfer_status, 0);
969         out_le16(&cp->command, INPUT_LAST + INTR_ALWAYS);
970 #if 0
971         if ((ld_le32(&rd->status) & ACTIVE) != 0) {
972             out_le32(&rd->control, (PAUSE << 16) | PAUSE);
973             while ((in_le32(&rd->status) & ACTIVE) != 0)
974                 ;
975         }
976 #endif
977         i = next;
978     }
979     if (i != mp->rx_fill) {
980         out_le32(&rd->control, ((RUN|WAKE) << 16) | (RUN|WAKE));
981         mp->rx_fill = i;
982     }
983     spin_unlock_irqrestore(&mp->lock, flags);
984     return IRQ_HANDLED;
985 }
986 
987 static struct of_device_id mace_match[] =
988 {
989         {
990         .name           = "mace",
991         },
992         {},
993 };
994 MODULE_DEVICE_TABLE (of, mace_match);
995 
996 static struct macio_driver mace_driver =
997 {
998         .driver = {
999                 .name           = "mace",
1000                 .owner          = THIS_MODULE,
1001                 .of_match_table = mace_match,
1002         },
1003         .probe          = mace_probe,
1004         .remove         = mace_remove,
1005 };
1006 
1007 
1008 static int __init mace_init(void)
1009 {
1010         return macio_register_driver(&mace_driver);
1011 }
1012 
1013 static void __exit mace_cleanup(void)
1014 {
1015         macio_unregister_driver(&mace_driver);
1016 
1017         kfree(dummy_buf);
1018         dummy_buf = NULL;
1019 }
1020 
1021 MODULE_AUTHOR("Paul Mackerras");
1022 MODULE_DESCRIPTION("PowerMac MACE driver.");
1023 module_param(port_aaui, int, 0);
1024 MODULE_PARM_DESC(port_aaui, "MACE uses AAUI port (0-1)");
1025 MODULE_LICENSE("GPL");
1026 
1027 module_init(mace_init);
1028 module_exit(mace_cleanup);
1029 

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