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Linux/drivers/net/ethernet/amd/nmclan_cs.c

  1 /* ----------------------------------------------------------------------------
  2 Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN.
  3   nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao
  4 
  5   The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media
  6   Access Controller for Ethernet (MACE).  It is essentially the Am2150
  7   PCMCIA Ethernet card contained in the Am2150 Demo Kit.
  8 
  9 Written by Roger C. Pao <rpao@paonet.org>
 10   Copyright 1995 Roger C. Pao
 11   Linux 2.5 cleanups Copyright Red Hat 2003
 12 
 13   This software may be used and distributed according to the terms of
 14   the GNU General Public License.
 15 
 16 Ported to Linux 1.3.* network driver environment by
 17   Matti Aarnio <mea@utu.fi>
 18 
 19 References
 20 
 21   Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993
 22   Am79C940 (MACE) Data Sheet, 1994
 23   Am79C90 (C-LANCE) Data Sheet, 1994
 24   Linux PCMCIA Programmer's Guide v1.17
 25   /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8
 26 
 27   Eric Mears, New Media Corporation
 28   Tom Pollard, New Media Corporation
 29   Dean Siasoyco, New Media Corporation
 30   Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com>
 31   Donald Becker <becker@scyld.com>
 32   David Hinds <dahinds@users.sourceforge.net>
 33 
 34   The Linux client driver is based on the 3c589_cs.c client driver by
 35   David Hinds.
 36 
 37   The Linux network driver outline is based on the 3c589_cs.c driver,
 38   the 8390.c driver, and the example skeleton.c kernel code, which are
 39   by Donald Becker.
 40 
 41   The Am2150 network driver hardware interface code is based on the
 42   OS/9000 driver for the New Media Ethernet LAN by Eric Mears.
 43 
 44   Special thanks for testing and help in debugging this driver goes
 45   to Ken Lesniak.
 46 
 47 -------------------------------------------------------------------------------
 48 Driver Notes and Issues
 49 -------------------------------------------------------------------------------
 50 
 51 1. Developed on a Dell 320SLi
 52    PCMCIA Card Services 2.6.2
 53    Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386
 54 
 55 2. rc.pcmcia may require loading pcmcia_core with io_speed=300:
 56    'insmod pcmcia_core.o io_speed=300'.
 57    This will avoid problems with fast systems which causes rx_framecnt
 58    to return random values.
 59 
 60 3. If hot extraction does not work for you, use 'ifconfig eth0 down'
 61    before extraction.
 62 
 63 4. There is a bad slow-down problem in this driver.
 64 
 65 5. Future: Multicast processing.  In the meantime, do _not_ compile your
 66    kernel with multicast ip enabled.
 67 
 68 -------------------------------------------------------------------------------
 69 History
 70 -------------------------------------------------------------------------------
 71 Log: nmclan_cs.c,v
 72  * 2.5.75-ac1 2003/07/11 Alan Cox <alan@lxorguk.ukuu.org.uk>
 73  * Fixed hang on card eject as we probe it
 74  * Cleaned up to use new style locking.
 75  *
 76  * Revision 0.16  1995/07/01  06:42:17  rpao
 77  * Bug fix: nmclan_reset() called CardServices incorrectly.
 78  *
 79  * Revision 0.15  1995/05/24  08:09:47  rpao
 80  * Re-implement MULTI_TX dev->tbusy handling.
 81  *
 82  * Revision 0.14  1995/05/23  03:19:30  rpao
 83  * Added, in nmclan_config(), "tuple.Attributes = 0;".
 84  * Modified MACE ID check to ignore chip revision level.
 85  * Avoid tx_free_frames race condition between _start_xmit and _interrupt.
 86  *
 87  * Revision 0.13  1995/05/18  05:56:34  rpao
 88  * Statistics changes.
 89  * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list.
 90  * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT.  Fixes driver lockup.
 91  *
 92  * Revision 0.12  1995/05/14  00:12:23  rpao
 93  * Statistics overhaul.
 94  *
 95 
 96 95/05/13 rpao   V0.10a
 97                 Bug fix: MACE statistics counters used wrong I/O ports.
 98                 Bug fix: mace_interrupt() needed to allow statistics to be
 99                 processed without RX or TX interrupts pending.
100 95/05/11 rpao   V0.10
101                 Multiple transmit request processing.
102                 Modified statistics to use MACE counters where possible.
103 95/05/10 rpao   V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO.
104                 *Released
105 95/05/10 rpao   V0.08
106                 Bug fix: Make all non-exported functions private by using
107                 static keyword.
108                 Bug fix: Test IntrCnt _before_ reading MACE_IR.
109 95/05/10 rpao   V0.07 Statistics.
110 95/05/09 rpao   V0.06 Fix rx_framecnt problem by addition of PCIC wait states.
111 
112 ---------------------------------------------------------------------------- */
113 
114 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
115 
116 #define DRV_NAME        "nmclan_cs"
117 #define DRV_VERSION     "0.16"
118 
119 
120 /* ----------------------------------------------------------------------------
121 Conditional Compilation Options
122 ---------------------------------------------------------------------------- */
123 
124 #define MULTI_TX                        0
125 #define RESET_ON_TIMEOUT                1
126 #define TX_INTERRUPTABLE                1
127 #define RESET_XILINX                    0
128 
129 /* ----------------------------------------------------------------------------
130 Include Files
131 ---------------------------------------------------------------------------- */
132 
133 #include <linux/module.h>
134 #include <linux/kernel.h>
135 #include <linux/ptrace.h>
136 #include <linux/slab.h>
137 #include <linux/string.h>
138 #include <linux/timer.h>
139 #include <linux/interrupt.h>
140 #include <linux/in.h>
141 #include <linux/delay.h>
142 #include <linux/ethtool.h>
143 #include <linux/netdevice.h>
144 #include <linux/etherdevice.h>
145 #include <linux/skbuff.h>
146 #include <linux/if_arp.h>
147 #include <linux/ioport.h>
148 #include <linux/bitops.h>
149 
150 #include <pcmcia/cisreg.h>
151 #include <pcmcia/cistpl.h>
152 #include <pcmcia/ds.h>
153 
154 #include <linux/uaccess.h>
155 #include <asm/io.h>
156 
157 /* ----------------------------------------------------------------------------
158 Defines
159 ---------------------------------------------------------------------------- */
160 
161 #define MACE_LADRF_LEN                  8
162                                         /* 8 bytes in Logical Address Filter */
163 
164 /* Loop Control Defines */
165 #define MACE_MAX_IR_ITERATIONS          10
166 #define MACE_MAX_RX_ITERATIONS          12
167         /*
168         TBD: Dean brought this up, and I assumed the hardware would
169         handle it:
170 
171         If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be
172         non-zero when the isr exits.  We may not get another interrupt
173         to process the remaining packets for some time.
174         */
175 
176 /*
177 The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA)
178 which manages the interface between the MACE and the PCMCIA bus.  It
179 also includes buffer management for the 32K x 8 SRAM to control up to
180 four transmit and 12 receive frames at a time.
181 */
182 #define AM2150_MAX_TX_FRAMES            4
183 #define AM2150_MAX_RX_FRAMES            12
184 
185 /* Am2150 Ethernet Card I/O Mapping */
186 #define AM2150_RCV                      0x00
187 #define AM2150_XMT                      0x04
188 #define AM2150_XMT_SKIP                 0x09
189 #define AM2150_RCV_NEXT                 0x0A
190 #define AM2150_RCV_FRAME_COUNT          0x0B
191 #define AM2150_MACE_BANK                0x0C
192 #define AM2150_MACE_BASE                0x10
193 
194 /* MACE Registers */
195 #define MACE_RCVFIFO                    0
196 #define MACE_XMTFIFO                    1
197 #define MACE_XMTFC                      2
198 #define MACE_XMTFS                      3
199 #define MACE_XMTRC                      4
200 #define MACE_RCVFC                      5
201 #define MACE_RCVFS                      6
202 #define MACE_FIFOFC                     7
203 #define MACE_IR                         8
204 #define MACE_IMR                        9
205 #define MACE_PR                         10
206 #define MACE_BIUCC                      11
207 #define MACE_FIFOCC                     12
208 #define MACE_MACCC                      13
209 #define MACE_PLSCC                      14
210 #define MACE_PHYCC                      15
211 #define MACE_CHIPIDL                    16
212 #define MACE_CHIPIDH                    17
213 #define MACE_IAC                        18
214 /* Reserved */
215 #define MACE_LADRF                      20
216 #define MACE_PADR                       21
217 /* Reserved */
218 /* Reserved */
219 #define MACE_MPC                        24
220 /* Reserved */
221 #define MACE_RNTPC                      26
222 #define MACE_RCVCC                      27
223 /* Reserved */
224 #define MACE_UTR                        29
225 #define MACE_RTR1                       30
226 #define MACE_RTR2                       31
227 
228 /* MACE Bit Masks */
229 #define MACE_XMTRC_EXDEF                0x80
230 #define MACE_XMTRC_XMTRC                0x0F
231 
232 #define MACE_XMTFS_XMTSV                0x80
233 #define MACE_XMTFS_UFLO                 0x40
234 #define MACE_XMTFS_LCOL                 0x20
235 #define MACE_XMTFS_MORE                 0x10
236 #define MACE_XMTFS_ONE                  0x08
237 #define MACE_XMTFS_DEFER                0x04
238 #define MACE_XMTFS_LCAR                 0x02
239 #define MACE_XMTFS_RTRY                 0x01
240 
241 #define MACE_RCVFS_RCVSTS               0xF000
242 #define MACE_RCVFS_OFLO                 0x8000
243 #define MACE_RCVFS_CLSN                 0x4000
244 #define MACE_RCVFS_FRAM                 0x2000
245 #define MACE_RCVFS_FCS                  0x1000
246 
247 #define MACE_FIFOFC_RCVFC               0xF0
248 #define MACE_FIFOFC_XMTFC               0x0F
249 
250 #define MACE_IR_JAB                     0x80
251 #define MACE_IR_BABL                    0x40
252 #define MACE_IR_CERR                    0x20
253 #define MACE_IR_RCVCCO                  0x10
254 #define MACE_IR_RNTPCO                  0x08
255 #define MACE_IR_MPCO                    0x04
256 #define MACE_IR_RCVINT                  0x02
257 #define MACE_IR_XMTINT                  0x01
258 
259 #define MACE_MACCC_PROM                 0x80
260 #define MACE_MACCC_DXMT2PD              0x40
261 #define MACE_MACCC_EMBA                 0x20
262 #define MACE_MACCC_RESERVED             0x10
263 #define MACE_MACCC_DRCVPA               0x08
264 #define MACE_MACCC_DRCVBC               0x04
265 #define MACE_MACCC_ENXMT                0x02
266 #define MACE_MACCC_ENRCV                0x01
267 
268 #define MACE_PHYCC_LNKFL                0x80
269 #define MACE_PHYCC_DLNKTST              0x40
270 #define MACE_PHYCC_REVPOL               0x20
271 #define MACE_PHYCC_DAPC                 0x10
272 #define MACE_PHYCC_LRT                  0x08
273 #define MACE_PHYCC_ASEL                 0x04
274 #define MACE_PHYCC_RWAKE                0x02
275 #define MACE_PHYCC_AWAKE                0x01
276 
277 #define MACE_IAC_ADDRCHG                0x80
278 #define MACE_IAC_PHYADDR                0x04
279 #define MACE_IAC_LOGADDR                0x02
280 
281 #define MACE_UTR_RTRE                   0x80
282 #define MACE_UTR_RTRD                   0x40
283 #define MACE_UTR_RPA                    0x20
284 #define MACE_UTR_FCOLL                  0x10
285 #define MACE_UTR_RCVFCSE                0x08
286 #define MACE_UTR_LOOP_INCL_MENDEC       0x06
287 #define MACE_UTR_LOOP_NO_MENDEC         0x04
288 #define MACE_UTR_LOOP_EXTERNAL          0x02
289 #define MACE_UTR_LOOP_NONE              0x00
290 #define MACE_UTR_RESERVED               0x01
291 
292 /* Switch MACE register bank (only 0 and 1 are valid) */
293 #define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
294 
295 #define MACE_IMR_DEFAULT \
296   (0xFF - \
297     ( \
298       MACE_IR_CERR | \
299       MACE_IR_RCVCCO | \
300       MACE_IR_RNTPCO | \
301       MACE_IR_MPCO | \
302       MACE_IR_RCVINT | \
303       MACE_IR_XMTINT \
304     ) \
305   )
306 #undef MACE_IMR_DEFAULT
307 #define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */
308 
309 #define TX_TIMEOUT              ((400*HZ)/1000)
310 
311 /* ----------------------------------------------------------------------------
312 Type Definitions
313 ---------------------------------------------------------------------------- */
314 
315 typedef struct _mace_statistics {
316     /* MACE_XMTFS */
317     int xmtsv;
318     int uflo;
319     int lcol;
320     int more;
321     int one;
322     int defer;
323     int lcar;
324     int rtry;
325 
326     /* MACE_XMTRC */
327     int exdef;
328     int xmtrc;
329 
330     /* RFS1--Receive Status (RCVSTS) */
331     int oflo;
332     int clsn;
333     int fram;
334     int fcs;
335 
336     /* RFS2--Runt Packet Count (RNTPC) */
337     int rfs_rntpc;
338 
339     /* RFS3--Receive Collision Count (RCVCC) */
340     int rfs_rcvcc;
341 
342     /* MACE_IR */
343     int jab;
344     int babl;
345     int cerr;
346     int rcvcco;
347     int rntpco;
348     int mpco;
349 
350     /* MACE_MPC */
351     int mpc;
352 
353     /* MACE_RNTPC */
354     int rntpc;
355 
356     /* MACE_RCVCC */
357     int rcvcc;
358 } mace_statistics;
359 
360 typedef struct _mace_private {
361         struct pcmcia_device    *p_dev;
362     struct net_device_stats linux_stats; /* Linux statistics counters */
363     mace_statistics mace_stats; /* MACE chip statistics counters */
364 
365     /* restore_multicast_list() state variables */
366     int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */
367     int multicast_num_addrs;
368 
369     char tx_free_frames; /* Number of free transmit frame buffers */
370     char tx_irq_disabled; /* MACE TX interrupt disabled */
371     
372     spinlock_t bank_lock; /* Must be held if you step off bank 0 */
373 } mace_private;
374 
375 /* ----------------------------------------------------------------------------
376 Private Global Variables
377 ---------------------------------------------------------------------------- */
378 
379 static const char *if_names[]={
380     "Auto", "10baseT", "BNC",
381 };
382 
383 /* ----------------------------------------------------------------------------
384 Parameters
385         These are the parameters that can be set during loading with
386         'insmod'.
387 ---------------------------------------------------------------------------- */
388 
389 MODULE_DESCRIPTION("New Media PCMCIA ethernet driver");
390 MODULE_LICENSE("GPL");
391 
392 #define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
393 
394 /* 0=auto, 1=10baseT, 2 = 10base2, default=auto */
395 INT_MODULE_PARM(if_port, 0);
396 
397 
398 /* ----------------------------------------------------------------------------
399 Function Prototypes
400 ---------------------------------------------------------------------------- */
401 
402 static int nmclan_config(struct pcmcia_device *link);
403 static void nmclan_release(struct pcmcia_device *link);
404 
405 static void nmclan_reset(struct net_device *dev);
406 static int mace_config(struct net_device *dev, struct ifmap *map);
407 static int mace_open(struct net_device *dev);
408 static int mace_close(struct net_device *dev);
409 static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
410                                          struct net_device *dev);
411 static void mace_tx_timeout(struct net_device *dev);
412 static irqreturn_t mace_interrupt(int irq, void *dev_id);
413 static struct net_device_stats *mace_get_stats(struct net_device *dev);
414 static int mace_rx(struct net_device *dev, unsigned char RxCnt);
415 static void restore_multicast_list(struct net_device *dev);
416 static void set_multicast_list(struct net_device *dev);
417 static const struct ethtool_ops netdev_ethtool_ops;
418 
419 
420 static void nmclan_detach(struct pcmcia_device *p_dev);
421 
422 static const struct net_device_ops mace_netdev_ops = {
423         .ndo_open               = mace_open,
424         .ndo_stop               = mace_close,
425         .ndo_start_xmit         = mace_start_xmit,
426         .ndo_tx_timeout         = mace_tx_timeout,
427         .ndo_set_config         = mace_config,
428         .ndo_get_stats          = mace_get_stats,
429         .ndo_set_rx_mode        = set_multicast_list,
430         .ndo_set_mac_address    = eth_mac_addr,
431         .ndo_validate_addr      = eth_validate_addr,
432 };
433 
434 static int nmclan_probe(struct pcmcia_device *link)
435 {
436     mace_private *lp;
437     struct net_device *dev;
438 
439     dev_dbg(&link->dev, "nmclan_attach()\n");
440 
441     /* Create new ethernet device */
442     dev = alloc_etherdev(sizeof(mace_private));
443     if (!dev)
444             return -ENOMEM;
445     lp = netdev_priv(dev);
446     lp->p_dev = link;
447     link->priv = dev;
448     
449     spin_lock_init(&lp->bank_lock);
450     link->resource[0]->end = 32;
451     link->resource[0]->flags |= IO_DATA_PATH_WIDTH_AUTO;
452     link->config_flags |= CONF_ENABLE_IRQ;
453     link->config_index = 1;
454     link->config_regs = PRESENT_OPTION;
455 
456     lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
457 
458     dev->netdev_ops = &mace_netdev_ops;
459     dev->ethtool_ops = &netdev_ethtool_ops;
460     dev->watchdog_timeo = TX_TIMEOUT;
461 
462     return nmclan_config(link);
463 } /* nmclan_attach */
464 
465 static void nmclan_detach(struct pcmcia_device *link)
466 {
467     struct net_device *dev = link->priv;
468 
469     dev_dbg(&link->dev, "nmclan_detach\n");
470 
471     unregister_netdev(dev);
472 
473     nmclan_release(link);
474 
475     free_netdev(dev);
476 } /* nmclan_detach */
477 
478 /* ----------------------------------------------------------------------------
479 mace_read
480         Reads a MACE register.  This is bank independent; however, the
481         caller must ensure that this call is not interruptable.  We are
482         assuming that during normal operation, the MACE is always in
483         bank 0.
484 ---------------------------------------------------------------------------- */
485 static int mace_read(mace_private *lp, unsigned int ioaddr, int reg)
486 {
487   int data = 0xFF;
488   unsigned long flags;
489 
490   switch (reg >> 4) {
491     case 0: /* register 0-15 */
492       data = inb(ioaddr + AM2150_MACE_BASE + reg);
493       break;
494     case 1: /* register 16-31 */
495       spin_lock_irqsave(&lp->bank_lock, flags);
496       MACEBANK(1);
497       data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
498       MACEBANK(0);
499       spin_unlock_irqrestore(&lp->bank_lock, flags);
500       break;
501   }
502   return data & 0xFF;
503 } /* mace_read */
504 
505 /* ----------------------------------------------------------------------------
506 mace_write
507         Writes to a MACE register.  This is bank independent; however,
508         the caller must ensure that this call is not interruptable.  We
509         are assuming that during normal operation, the MACE is always in
510         bank 0.
511 ---------------------------------------------------------------------------- */
512 static void mace_write(mace_private *lp, unsigned int ioaddr, int reg,
513                        int data)
514 {
515   unsigned long flags;
516 
517   switch (reg >> 4) {
518     case 0: /* register 0-15 */
519       outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
520       break;
521     case 1: /* register 16-31 */
522       spin_lock_irqsave(&lp->bank_lock, flags);
523       MACEBANK(1);
524       outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
525       MACEBANK(0);
526       spin_unlock_irqrestore(&lp->bank_lock, flags);
527       break;
528   }
529 } /* mace_write */
530 
531 /* ----------------------------------------------------------------------------
532 mace_init
533         Resets the MACE chip.
534 ---------------------------------------------------------------------------- */
535 static int mace_init(mace_private *lp, unsigned int ioaddr, char *enet_addr)
536 {
537   int i;
538   int ct = 0;
539 
540   /* MACE Software reset */
541   mace_write(lp, ioaddr, MACE_BIUCC, 1);
542   while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {
543     /* Wait for reset bit to be cleared automatically after <= 200ns */;
544     if(++ct > 500)
545     {
546         pr_err("reset failed, card removed?\n");
547         return -1;
548     }
549     udelay(1);
550   }
551   mace_write(lp, ioaddr, MACE_BIUCC, 0);
552 
553   /* The Am2150 requires that the MACE FIFOs operate in burst mode. */
554   mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
555 
556   mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
557   mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
558 
559   /*
560    * Bit 2-1 PORTSEL[1-0] Port Select.
561    * 00 AUI/10Base-2
562    * 01 10Base-T
563    * 10 DAI Port (reserved in Am2150)
564    * 11 GPSI
565    * For this card, only the first two are valid.
566    * So, PLSCC should be set to
567    * 0x00 for 10Base-2
568    * 0x02 for 10Base-T
569    * Or just set ASEL in PHYCC below!
570    */
571   switch (if_port) {
572     case 1:
573       mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
574       break;
575     case 2:
576       mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
577       break;
578     default:
579       mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);
580       /* ASEL Auto Select.  When set, the PORTSEL[1-0] bits are overridden,
581          and the MACE device will automatically select the operating media
582          interface port. */
583       break;
584   }
585 
586   mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
587   /* Poll ADDRCHG bit */
588   ct = 0;
589   while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
590   {
591         if(++ ct > 500)
592         {
593                 pr_err("ADDRCHG timeout, card removed?\n");
594                 return -1;
595         }
596   }
597   /* Set PADR register */
598   for (i = 0; i < ETH_ALEN; i++)
599     mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
600 
601   /* MAC Configuration Control Register should be written last */
602   /* Let set_multicast_list set this. */
603   /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
604   mace_write(lp, ioaddr, MACE_MACCC, 0x00);
605   return 0;
606 } /* mace_init */
607 
608 static int nmclan_config(struct pcmcia_device *link)
609 {
610   struct net_device *dev = link->priv;
611   mace_private *lp = netdev_priv(dev);
612   u8 *buf;
613   size_t len;
614   int i, ret;
615   unsigned int ioaddr;
616 
617   dev_dbg(&link->dev, "nmclan_config\n");
618 
619   link->io_lines = 5;
620   ret = pcmcia_request_io(link);
621   if (ret)
622           goto failed;
623   ret = pcmcia_request_irq(link, mace_interrupt);
624   if (ret)
625           goto failed;
626   ret = pcmcia_enable_device(link);
627   if (ret)
628           goto failed;
629 
630   dev->irq = link->irq;
631   dev->base_addr = link->resource[0]->start;
632 
633   ioaddr = dev->base_addr;
634 
635   /* Read the ethernet address from the CIS. */
636   len = pcmcia_get_tuple(link, 0x80, &buf);
637   if (!buf || len < ETH_ALEN) {
638           kfree(buf);
639           goto failed;
640   }
641   memcpy(dev->dev_addr, buf, ETH_ALEN);
642   kfree(buf);
643 
644   /* Verify configuration by reading the MACE ID. */
645   {
646     char sig[2];
647 
648     sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL);
649     sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH);
650     if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
651       dev_dbg(&link->dev, "nmclan_cs configured: mace id=%x %x\n",
652             sig[0], sig[1]);
653     } else {
654       pr_notice("mace id not found: %x %x should be 0x40 0x?9\n",
655                 sig[0], sig[1]);
656       return -ENODEV;
657     }
658   }
659 
660   if(mace_init(lp, ioaddr, dev->dev_addr) == -1)
661         goto failed;
662 
663   /* The if_port symbol can be set when the module is loaded */
664   if (if_port <= 2)
665     dev->if_port = if_port;
666   else
667     pr_notice("invalid if_port requested\n");
668 
669   SET_NETDEV_DEV(dev, &link->dev);
670 
671   i = register_netdev(dev);
672   if (i != 0) {
673     pr_notice("register_netdev() failed\n");
674     goto failed;
675   }
676 
677   netdev_info(dev, "nmclan: port %#3lx, irq %d, %s port, hw_addr %pM\n",
678               dev->base_addr, dev->irq, if_names[dev->if_port], dev->dev_addr);
679   return 0;
680 
681 failed:
682         nmclan_release(link);
683         return -ENODEV;
684 } /* nmclan_config */
685 
686 static void nmclan_release(struct pcmcia_device *link)
687 {
688         dev_dbg(&link->dev, "nmclan_release\n");
689         pcmcia_disable_device(link);
690 }
691 
692 static int nmclan_suspend(struct pcmcia_device *link)
693 {
694         struct net_device *dev = link->priv;
695 
696         if (link->open)
697                 netif_device_detach(dev);
698 
699         return 0;
700 }
701 
702 static int nmclan_resume(struct pcmcia_device *link)
703 {
704         struct net_device *dev = link->priv;
705 
706         if (link->open) {
707                 nmclan_reset(dev);
708                 netif_device_attach(dev);
709         }
710 
711         return 0;
712 }
713 
714 
715 /* ----------------------------------------------------------------------------
716 nmclan_reset
717         Reset and restore all of the Xilinx and MACE registers.
718 ---------------------------------------------------------------------------- */
719 static void nmclan_reset(struct net_device *dev)
720 {
721   mace_private *lp = netdev_priv(dev);
722 
723 #if RESET_XILINX
724   struct pcmcia_device *link = &lp->link;
725   u8 OrigCorValue;
726 
727   /* Save original COR value */
728   pcmcia_read_config_byte(link, CISREG_COR, &OrigCorValue);
729 
730   /* Reset Xilinx */
731   dev_dbg(&link->dev, "nmclan_reset: OrigCorValue=0x%x, resetting...\n",
732         OrigCorValue);
733   pcmcia_write_config_byte(link, CISREG_COR, COR_SOFT_RESET);
734   /* Need to wait for 20 ms for PCMCIA to finish reset. */
735 
736   /* Restore original COR configuration index */
737   pcmcia_write_config_byte(link, CISREG_COR,
738                           (COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK)));
739   /* Xilinx is now completely reset along with the MACE chip. */
740   lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
741 
742 #endif /* #if RESET_XILINX */
743 
744   /* Xilinx is now completely reset along with the MACE chip. */
745   lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
746 
747   /* Reinitialize the MACE chip for operation. */
748   mace_init(lp, dev->base_addr, dev->dev_addr);
749   mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
750 
751   /* Restore the multicast list and enable TX and RX. */
752   restore_multicast_list(dev);
753 } /* nmclan_reset */
754 
755 /* ----------------------------------------------------------------------------
756 mace_config
757         [Someone tell me what this is supposed to do?  Is if_port a defined
758         standard?  If so, there should be defines to indicate 1=10Base-T,
759         2=10Base-2, etc. including limited automatic detection.]
760 ---------------------------------------------------------------------------- */
761 static int mace_config(struct net_device *dev, struct ifmap *map)
762 {
763   if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
764     if (map->port <= 2) {
765       dev->if_port = map->port;
766       netdev_info(dev, "switched to %s port\n", if_names[dev->if_port]);
767     } else
768       return -EINVAL;
769   }
770   return 0;
771 } /* mace_config */
772 
773 /* ----------------------------------------------------------------------------
774 mace_open
775         Open device driver.
776 ---------------------------------------------------------------------------- */
777 static int mace_open(struct net_device *dev)
778 {
779   unsigned int ioaddr = dev->base_addr;
780   mace_private *lp = netdev_priv(dev);
781   struct pcmcia_device *link = lp->p_dev;
782 
783   if (!pcmcia_dev_present(link))
784     return -ENODEV;
785 
786   link->open++;
787 
788   MACEBANK(0);
789 
790   netif_start_queue(dev);
791   nmclan_reset(dev);
792 
793   return 0; /* Always succeed */
794 } /* mace_open */
795 
796 /* ----------------------------------------------------------------------------
797 mace_close
798         Closes device driver.
799 ---------------------------------------------------------------------------- */
800 static int mace_close(struct net_device *dev)
801 {
802   unsigned int ioaddr = dev->base_addr;
803   mace_private *lp = netdev_priv(dev);
804   struct pcmcia_device *link = lp->p_dev;
805 
806   dev_dbg(&link->dev, "%s: shutting down ethercard.\n", dev->name);
807 
808   /* Mask off all interrupts from the MACE chip. */
809   outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
810 
811   link->open--;
812   netif_stop_queue(dev);
813 
814   return 0;
815 } /* mace_close */
816 
817 static void netdev_get_drvinfo(struct net_device *dev,
818                                struct ethtool_drvinfo *info)
819 {
820         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
821         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
822         snprintf(info->bus_info, sizeof(info->bus_info),
823                 "PCMCIA 0x%lx", dev->base_addr);
824 }
825 
826 static const struct ethtool_ops netdev_ethtool_ops = {
827         .get_drvinfo            = netdev_get_drvinfo,
828 };
829 
830 /* ----------------------------------------------------------------------------
831 mace_start_xmit
832         This routine begins the packet transmit function.  When completed,
833         it will generate a transmit interrupt.
834 
835         According to /usr/src/linux/net/inet/dev.c, if _start_xmit
836         returns 0, the "packet is now solely the responsibility of the
837         driver."  If _start_xmit returns non-zero, the "transmission
838         failed, put skb back into a list."
839 ---------------------------------------------------------------------------- */
840 
841 static void mace_tx_timeout(struct net_device *dev)
842 {
843   mace_private *lp = netdev_priv(dev);
844   struct pcmcia_device *link = lp->p_dev;
845 
846   netdev_notice(dev, "transmit timed out -- ");
847 #if RESET_ON_TIMEOUT
848   pr_cont("resetting card\n");
849   pcmcia_reset_card(link->socket);
850 #else /* #if RESET_ON_TIMEOUT */
851   pr_cont("NOT resetting card\n");
852 #endif /* #if RESET_ON_TIMEOUT */
853   netif_trans_update(dev); /* prevent tx timeout */
854   netif_wake_queue(dev);
855 }
856 
857 static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
858                                          struct net_device *dev)
859 {
860   mace_private *lp = netdev_priv(dev);
861   unsigned int ioaddr = dev->base_addr;
862 
863   netif_stop_queue(dev);
864 
865   pr_debug("%s: mace_start_xmit(length = %ld) called.\n",
866         dev->name, (long)skb->len);
867 
868 #if (!TX_INTERRUPTABLE)
869   /* Disable MACE TX interrupts. */
870   outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
871     ioaddr + AM2150_MACE_BASE + MACE_IMR);
872   lp->tx_irq_disabled=1;
873 #endif /* #if (!TX_INTERRUPTABLE) */
874 
875   {
876     /* This block must not be interrupted by another transmit request!
877        mace_tx_timeout will take care of timer-based retransmissions from
878        the upper layers.  The interrupt handler is guaranteed never to
879        service a transmit interrupt while we are in here.
880     */
881 
882     lp->linux_stats.tx_bytes += skb->len;
883     lp->tx_free_frames--;
884 
885     /* WARNING: Write the _exact_ number of bytes written in the header! */
886     /* Put out the word header [must be an outw()] . . . */
887     outw(skb->len, ioaddr + AM2150_XMT);
888     /* . . . and the packet [may be any combination of outw() and outb()] */
889     outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
890     if (skb->len & 1) {
891       /* Odd byte transfer */
892       outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
893     }
894 
895 #if MULTI_TX
896     if (lp->tx_free_frames > 0)
897       netif_start_queue(dev);
898 #endif /* #if MULTI_TX */
899   }
900 
901 #if (!TX_INTERRUPTABLE)
902   /* Re-enable MACE TX interrupts. */
903   lp->tx_irq_disabled=0;
904   outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
905 #endif /* #if (!TX_INTERRUPTABLE) */
906 
907   dev_kfree_skb(skb);
908 
909   return NETDEV_TX_OK;
910 } /* mace_start_xmit */
911 
912 /* ----------------------------------------------------------------------------
913 mace_interrupt
914         The interrupt handler.
915 ---------------------------------------------------------------------------- */
916 static irqreturn_t mace_interrupt(int irq, void *dev_id)
917 {
918   struct net_device *dev = (struct net_device *) dev_id;
919   mace_private *lp = netdev_priv(dev);
920   unsigned int ioaddr;
921   int status;
922   int IntrCnt = MACE_MAX_IR_ITERATIONS;
923 
924   if (dev == NULL) {
925     pr_debug("mace_interrupt(): irq 0x%X for unknown device.\n",
926           irq);
927     return IRQ_NONE;
928   }
929 
930   ioaddr = dev->base_addr;
931 
932   if (lp->tx_irq_disabled) {
933     const char *msg;
934     if (lp->tx_irq_disabled)
935       msg = "Interrupt with tx_irq_disabled";
936     else
937       msg = "Re-entering the interrupt handler";
938     netdev_notice(dev, "%s [isr=%02X, imr=%02X]\n",
939                   msg,
940                   inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
941                   inb(ioaddr + AM2150_MACE_BASE + MACE_IMR));
942     /* WARNING: MACE_IR has been read! */
943     return IRQ_NONE;
944   }
945 
946   if (!netif_device_present(dev)) {
947     netdev_dbg(dev, "interrupt from dead card\n");
948     return IRQ_NONE;
949   }
950 
951   do {
952     /* WARNING: MACE_IR is a READ/CLEAR port! */
953     status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
954     if (!(status & ~MACE_IMR_DEFAULT) && IntrCnt == MACE_MAX_IR_ITERATIONS)
955       return IRQ_NONE;
956 
957     pr_debug("mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
958 
959     if (status & MACE_IR_RCVINT) {
960       mace_rx(dev, MACE_MAX_RX_ITERATIONS);
961     }
962 
963     if (status & MACE_IR_XMTINT) {
964       unsigned char fifofc;
965       unsigned char xmtrc;
966       unsigned char xmtfs;
967 
968       fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
969       if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
970         lp->linux_stats.tx_errors++;
971         outb(0xFF, ioaddr + AM2150_XMT_SKIP);
972       }
973 
974       /* Transmit Retry Count (XMTRC, reg 4) */
975       xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
976       if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
977       lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
978 
979       if (
980         (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
981         MACE_XMTFS_XMTSV /* Transmit Status Valid */
982       ) {
983         lp->mace_stats.xmtsv++;
984 
985         if (xmtfs & ~MACE_XMTFS_XMTSV) {
986           if (xmtfs & MACE_XMTFS_UFLO) {
987             /* Underflow.  Indicates that the Transmit FIFO emptied before
988                the end of frame was reached. */
989             lp->mace_stats.uflo++;
990           }
991           if (xmtfs & MACE_XMTFS_LCOL) {
992             /* Late Collision */
993             lp->mace_stats.lcol++;
994           }
995           if (xmtfs & MACE_XMTFS_MORE) {
996             /* MORE than one retry was needed */
997             lp->mace_stats.more++;
998           }
999           if (xmtfs & MACE_XMTFS_ONE) {
1000             /* Exactly ONE retry occurred */
1001             lp->mace_stats.one++;
1002           }
1003           if (xmtfs & MACE_XMTFS_DEFER) {
1004             /* Transmission was defered */
1005             lp->mace_stats.defer++;
1006           }
1007           if (xmtfs & MACE_XMTFS_LCAR) {
1008             /* Loss of carrier */
1009             lp->mace_stats.lcar++;
1010           }
1011           if (xmtfs & MACE_XMTFS_RTRY) {
1012             /* Retry error: transmit aborted after 16 attempts */
1013             lp->mace_stats.rtry++;
1014           }
1015         } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */
1016 
1017       } /* if (xmtfs & MACE_XMTFS_XMTSV) */
1018 
1019       lp->linux_stats.tx_packets++;
1020       lp->tx_free_frames++;
1021       netif_wake_queue(dev);
1022     } /* if (status & MACE_IR_XMTINT) */
1023 
1024     if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1025       if (status & MACE_IR_JAB) {
1026         /* Jabber Error.  Excessive transmit duration (20-150ms). */
1027         lp->mace_stats.jab++;
1028       }
1029       if (status & MACE_IR_BABL) {
1030         /* Babble Error.  >1518 bytes transmitted. */
1031         lp->mace_stats.babl++;
1032       }
1033       if (status & MACE_IR_CERR) {
1034         /* Collision Error.  CERR indicates the absence of the
1035            Signal Quality Error Test message after a packet
1036            transmission. */
1037         lp->mace_stats.cerr++;
1038       }
1039       if (status & MACE_IR_RCVCCO) {
1040         /* Receive Collision Count Overflow; */
1041         lp->mace_stats.rcvcco++;
1042       }
1043       if (status & MACE_IR_RNTPCO) {
1044         /* Runt Packet Count Overflow */
1045         lp->mace_stats.rntpco++;
1046       }
1047       if (status & MACE_IR_MPCO) {
1048         /* Missed Packet Count Overflow */
1049         lp->mace_stats.mpco++;
1050       }
1051     } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */
1052 
1053   } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1054 
1055   return IRQ_HANDLED;
1056 } /* mace_interrupt */
1057 
1058 /* ----------------------------------------------------------------------------
1059 mace_rx
1060         Receives packets.
1061 ---------------------------------------------------------------------------- */
1062 static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1063 {
1064   mace_private *lp = netdev_priv(dev);
1065   unsigned int ioaddr = dev->base_addr;
1066   unsigned char rx_framecnt;
1067   unsigned short rx_status;
1068 
1069   while (
1070     ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1071     (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
1072     (RxCnt--)
1073   ) {
1074     rx_status = inw(ioaddr + AM2150_RCV);
1075 
1076     pr_debug("%s: in mace_rx(), framecnt 0x%X, rx_status"
1077           " 0x%X.\n", dev->name, rx_framecnt, rx_status);
1078 
1079     if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
1080       lp->linux_stats.rx_errors++;
1081       if (rx_status & MACE_RCVFS_OFLO) {
1082         lp->mace_stats.oflo++;
1083       }
1084       if (rx_status & MACE_RCVFS_CLSN) {
1085         lp->mace_stats.clsn++;
1086       }
1087       if (rx_status & MACE_RCVFS_FRAM) {
1088         lp->mace_stats.fram++;
1089       }
1090       if (rx_status & MACE_RCVFS_FCS) {
1091         lp->mace_stats.fcs++;
1092       }
1093     } else {
1094       short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1095         /* Auto Strip is off, always subtract 4 */
1096       struct sk_buff *skb;
1097 
1098       lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1099         /* runt packet count */
1100       lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1101         /* rcv collision count */
1102 
1103       pr_debug("    receiving packet size 0x%X rx_status"
1104             " 0x%X.\n", pkt_len, rx_status);
1105 
1106       skb = netdev_alloc_skb(dev, pkt_len + 2);
1107 
1108       if (skb != NULL) {
1109         skb_reserve(skb, 2);
1110         insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1111         if (pkt_len & 1)
1112             *(skb_tail_pointer(skb) - 1) = inb(ioaddr + AM2150_RCV);
1113         skb->protocol = eth_type_trans(skb, dev);
1114         
1115         netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
1116 
1117         lp->linux_stats.rx_packets++;
1118         lp->linux_stats.rx_bytes += pkt_len;
1119         outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1120         continue;
1121       } else {
1122         pr_debug("%s: couldn't allocate a sk_buff of size"
1123               " %d.\n", dev->name, pkt_len);
1124         lp->linux_stats.rx_dropped++;
1125       }
1126     }
1127     outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1128   } /* while */
1129 
1130   return 0;
1131 } /* mace_rx */
1132 
1133 /* ----------------------------------------------------------------------------
1134 pr_linux_stats
1135 ---------------------------------------------------------------------------- */
1136 static void pr_linux_stats(struct net_device_stats *pstats)
1137 {
1138   pr_debug("pr_linux_stats\n");
1139   pr_debug(" rx_packets=%-7ld        tx_packets=%ld\n",
1140         (long)pstats->rx_packets, (long)pstats->tx_packets);
1141   pr_debug(" rx_errors=%-7ld         tx_errors=%ld\n",
1142         (long)pstats->rx_errors, (long)pstats->tx_errors);
1143   pr_debug(" rx_dropped=%-7ld        tx_dropped=%ld\n",
1144         (long)pstats->rx_dropped, (long)pstats->tx_dropped);
1145   pr_debug(" multicast=%-7ld         collisions=%ld\n",
1146         (long)pstats->multicast, (long)pstats->collisions);
1147 
1148   pr_debug(" rx_length_errors=%-7ld  rx_over_errors=%ld\n",
1149         (long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
1150   pr_debug(" rx_crc_errors=%-7ld     rx_frame_errors=%ld\n",
1151         (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
1152   pr_debug(" rx_fifo_errors=%-7ld    rx_missed_errors=%ld\n",
1153         (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1154 
1155   pr_debug(" tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1156         (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
1157   pr_debug(" tx_fifo_errors=%-7ld    tx_heartbeat_errors=%ld\n",
1158         (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
1159   pr_debug(" tx_window_errors=%ld\n",
1160         (long)pstats->tx_window_errors);
1161 } /* pr_linux_stats */
1162 
1163 /* ----------------------------------------------------------------------------
1164 pr_mace_stats
1165 ---------------------------------------------------------------------------- */
1166 static void pr_mace_stats(mace_statistics *pstats)
1167 {
1168   pr_debug("pr_mace_stats\n");
1169 
1170   pr_debug(" xmtsv=%-7d             uflo=%d\n",
1171         pstats->xmtsv, pstats->uflo);
1172   pr_debug(" lcol=%-7d              more=%d\n",
1173         pstats->lcol, pstats->more);
1174   pr_debug(" one=%-7d               defer=%d\n",
1175         pstats->one, pstats->defer);
1176   pr_debug(" lcar=%-7d              rtry=%d\n",
1177         pstats->lcar, pstats->rtry);
1178 
1179   /* MACE_XMTRC */
1180   pr_debug(" exdef=%-7d             xmtrc=%d\n",
1181         pstats->exdef, pstats->xmtrc);
1182 
1183   /* RFS1--Receive Status (RCVSTS) */
1184   pr_debug(" oflo=%-7d              clsn=%d\n",
1185         pstats->oflo, pstats->clsn);
1186   pr_debug(" fram=%-7d              fcs=%d\n",
1187         pstats->fram, pstats->fcs);
1188 
1189   /* RFS2--Runt Packet Count (RNTPC) */
1190   /* RFS3--Receive Collision Count (RCVCC) */
1191   pr_debug(" rfs_rntpc=%-7d         rfs_rcvcc=%d\n",
1192         pstats->rfs_rntpc, pstats->rfs_rcvcc);
1193 
1194   /* MACE_IR */
1195   pr_debug(" jab=%-7d               babl=%d\n",
1196         pstats->jab, pstats->babl);
1197   pr_debug(" cerr=%-7d              rcvcco=%d\n",
1198         pstats->cerr, pstats->rcvcco);
1199   pr_debug(" rntpco=%-7d            mpco=%d\n",
1200         pstats->rntpco, pstats->mpco);
1201 
1202   /* MACE_MPC */
1203   pr_debug(" mpc=%d\n", pstats->mpc);
1204 
1205   /* MACE_RNTPC */
1206   pr_debug(" rntpc=%d\n", pstats->rntpc);
1207 
1208   /* MACE_RCVCC */
1209   pr_debug(" rcvcc=%d\n", pstats->rcvcc);
1210 
1211 } /* pr_mace_stats */
1212 
1213 /* ----------------------------------------------------------------------------
1214 update_stats
1215         Update statistics.  We change to register window 1, so this
1216         should be run single-threaded if the device is active. This is
1217         expected to be a rare operation, and it's simpler for the rest
1218         of the driver to assume that window 0 is always valid rather
1219         than use a special window-state variable.
1220 
1221         oflo & uflo should _never_ occur since it would mean the Xilinx
1222         was not able to transfer data between the MACE FIFO and the
1223         card's SRAM fast enough.  If this happens, something is
1224         seriously wrong with the hardware.
1225 ---------------------------------------------------------------------------- */
1226 static void update_stats(unsigned int ioaddr, struct net_device *dev)
1227 {
1228   mace_private *lp = netdev_priv(dev);
1229 
1230   lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC);
1231   lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC);
1232   lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC);
1233   /* At this point, mace_stats is fully updated for this call.
1234      We may now update the linux_stats. */
1235 
1236   /* The MACE has no equivalent for linux_stats field which are commented
1237      out. */
1238 
1239   /* lp->linux_stats.multicast; */
1240   lp->linux_stats.collisions = 
1241     lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1242     /* Collision: The MACE may retry sending a packet 15 times
1243        before giving up.  The retry count is in XMTRC.
1244        Does each retry constitute a collision?
1245        If so, why doesn't the RCVCC record these collisions? */
1246 
1247   /* detailed rx_errors: */
1248   lp->linux_stats.rx_length_errors = 
1249     lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1250   /* lp->linux_stats.rx_over_errors */
1251   lp->linux_stats.rx_crc_errors = lp->mace_stats.fcs;
1252   lp->linux_stats.rx_frame_errors = lp->mace_stats.fram;
1253   lp->linux_stats.rx_fifo_errors = lp->mace_stats.oflo;
1254   lp->linux_stats.rx_missed_errors = 
1255     lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1256 
1257   /* detailed tx_errors */
1258   lp->linux_stats.tx_aborted_errors = lp->mace_stats.rtry;
1259   lp->linux_stats.tx_carrier_errors = lp->mace_stats.lcar;
1260     /* LCAR usually results from bad cabling. */
1261   lp->linux_stats.tx_fifo_errors = lp->mace_stats.uflo;
1262   lp->linux_stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1263   /* lp->linux_stats.tx_window_errors; */
1264 } /* update_stats */
1265 
1266 /* ----------------------------------------------------------------------------
1267 mace_get_stats
1268         Gathers ethernet statistics from the MACE chip.
1269 ---------------------------------------------------------------------------- */
1270 static struct net_device_stats *mace_get_stats(struct net_device *dev)
1271 {
1272   mace_private *lp = netdev_priv(dev);
1273 
1274   update_stats(dev->base_addr, dev);
1275 
1276   pr_debug("%s: updating the statistics.\n", dev->name);
1277   pr_linux_stats(&lp->linux_stats);
1278   pr_mace_stats(&lp->mace_stats);
1279 
1280   return &lp->linux_stats;
1281 } /* net_device_stats */
1282 
1283 /* ----------------------------------------------------------------------------
1284 updateCRC
1285         Modified from Am79C90 data sheet.
1286 ---------------------------------------------------------------------------- */
1287 
1288 #ifdef BROKEN_MULTICAST
1289 
1290 static void updateCRC(int *CRC, int bit)
1291 {
1292   static const int poly[]={
1293     1,1,1,0, 1,1,0,1,
1294     1,0,1,1, 1,0,0,0,
1295     1,0,0,0, 0,0,1,1,
1296     0,0,1,0, 0,0,0,0
1297   }; /* CRC polynomial.  poly[n] = coefficient of the x**n term of the
1298         CRC generator polynomial. */
1299 
1300   int j;
1301 
1302   /* shift CRC and control bit (CRC[32]) */
1303   for (j = 32; j > 0; j--)
1304     CRC[j] = CRC[j-1];
1305   CRC[0] = 0;
1306 
1307   /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */
1308   if (bit ^ CRC[32])
1309     for (j = 0; j < 32; j++)
1310       CRC[j] ^= poly[j];
1311 } /* updateCRC */
1312 
1313 /* ----------------------------------------------------------------------------
1314 BuildLAF
1315         Build logical address filter.
1316         Modified from Am79C90 data sheet.
1317 
1318 Input
1319         ladrf: logical address filter (contents initialized to 0)
1320         adr: ethernet address
1321 ---------------------------------------------------------------------------- */
1322 static void BuildLAF(int *ladrf, int *adr)
1323 {
1324   int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */
1325 
1326   int i, byte; /* temporary array indices */
1327   int hashcode; /* the output object */
1328 
1329   CRC[32]=0;
1330 
1331   for (byte = 0; byte < 6; byte++)
1332     for (i = 0; i < 8; i++)
1333       updateCRC(CRC, (adr[byte] >> i) & 1);
1334 
1335   hashcode = 0;
1336   for (i = 0; i < 6; i++)
1337     hashcode = (hashcode << 1) + CRC[i];
1338 
1339   byte = hashcode >> 3;
1340   ladrf[byte] |= (1 << (hashcode & 7));
1341 
1342 #ifdef PCMCIA_DEBUG
1343   if (0)
1344     printk(KERN_DEBUG "    adr =%pM\n", adr);
1345   printk(KERN_DEBUG "    hashcode = %d(decimal), ladrf[0:63] =", hashcode);
1346   for (i = 0; i < 8; i++)
1347     pr_cont(" %02X", ladrf[i]);
1348   pr_cont("\n");
1349 #endif
1350 } /* BuildLAF */
1351 
1352 /* ----------------------------------------------------------------------------
1353 restore_multicast_list
1354         Restores the multicast filter for MACE chip to the last
1355         set_multicast_list() call.
1356 
1357 Input
1358         multicast_num_addrs
1359         multicast_ladrf[]
1360 ---------------------------------------------------------------------------- */
1361 static void restore_multicast_list(struct net_device *dev)
1362 {
1363   mace_private *lp = netdev_priv(dev);
1364   int num_addrs = lp->multicast_num_addrs;
1365   int *ladrf = lp->multicast_ladrf;
1366   unsigned int ioaddr = dev->base_addr;
1367   int i;
1368 
1369   pr_debug("%s: restoring Rx mode to %d addresses.\n",
1370         dev->name, num_addrs);
1371 
1372   if (num_addrs > 0) {
1373 
1374     pr_debug("Attempt to restore multicast list detected.\n");
1375 
1376     mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1377     /* Poll ADDRCHG bit */
1378     while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1379       ;
1380     /* Set LADRF register */
1381     for (i = 0; i < MACE_LADRF_LEN; i++)
1382       mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]);
1383 
1384     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1385     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1386 
1387   } else if (num_addrs < 0) {
1388 
1389     /* Promiscuous mode: receive all packets */
1390     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1391     mace_write(lp, ioaddr, MACE_MACCC,
1392       MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1393     );
1394 
1395   } else {
1396 
1397     /* Normal mode */
1398     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1399     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1400 
1401   }
1402 } /* restore_multicast_list */
1403 
1404 /* ----------------------------------------------------------------------------
1405 set_multicast_list
1406         Set or clear the multicast filter for this adaptor.
1407 
1408 Input
1409         num_addrs == -1 Promiscuous mode, receive all packets
1410         num_addrs == 0  Normal mode, clear multicast list
1411         num_addrs > 0   Multicast mode, receive normal and MC packets, and do
1412                         best-effort filtering.
1413 Output
1414         multicast_num_addrs
1415         multicast_ladrf[]
1416 ---------------------------------------------------------------------------- */
1417 
1418 static void set_multicast_list(struct net_device *dev)
1419 {
1420   mace_private *lp = netdev_priv(dev);
1421   int adr[ETH_ALEN] = {0}; /* Ethernet address */
1422   struct netdev_hw_addr *ha;
1423 
1424 #ifdef PCMCIA_DEBUG
1425   {
1426     static int old;
1427     if (netdev_mc_count(dev) != old) {
1428       old = netdev_mc_count(dev);
1429       pr_debug("%s: setting Rx mode to %d addresses.\n",
1430             dev->name, old);
1431     }
1432   }
1433 #endif
1434 
1435   /* Set multicast_num_addrs. */
1436   lp->multicast_num_addrs = netdev_mc_count(dev);
1437 
1438   /* Set multicast_ladrf. */
1439   if (num_addrs > 0) {
1440     /* Calculate multicast logical address filter */
1441     memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
1442     netdev_for_each_mc_addr(ha, dev) {
1443       memcpy(adr, ha->addr, ETH_ALEN);
1444       BuildLAF(lp->multicast_ladrf, adr);
1445     }
1446   }
1447 
1448   restore_multicast_list(dev);
1449 
1450 } /* set_multicast_list */
1451 
1452 #endif /* BROKEN_MULTICAST */
1453 
1454 static void restore_multicast_list(struct net_device *dev)
1455 {
1456   unsigned int ioaddr = dev->base_addr;
1457   mace_private *lp = netdev_priv(dev);
1458 
1459   pr_debug("%s: restoring Rx mode to %d addresses.\n", dev->name,
1460         lp->multicast_num_addrs);
1461 
1462   if (dev->flags & IFF_PROMISC) {
1463     /* Promiscuous mode: receive all packets */
1464     mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1465     mace_write(lp, ioaddr, MACE_MACCC,
1466       MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1467     );
1468   } else {
1469     /* Normal mode */
1470     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1471     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1472   }
1473 } /* restore_multicast_list */
1474 
1475 static void set_multicast_list(struct net_device *dev)
1476 {
1477   mace_private *lp = netdev_priv(dev);
1478 
1479 #ifdef PCMCIA_DEBUG
1480   {
1481     static int old;
1482     if (netdev_mc_count(dev) != old) {
1483       old = netdev_mc_count(dev);
1484       pr_debug("%s: setting Rx mode to %d addresses.\n",
1485             dev->name, old);
1486     }
1487   }
1488 #endif
1489 
1490   lp->multicast_num_addrs = netdev_mc_count(dev);
1491   restore_multicast_list(dev);
1492 
1493 } /* set_multicast_list */
1494 
1495 static const struct pcmcia_device_id nmclan_ids[] = {
1496         PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941),
1497         PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf),
1498         PCMCIA_DEVICE_NULL,
1499 };
1500 MODULE_DEVICE_TABLE(pcmcia, nmclan_ids);
1501 
1502 static struct pcmcia_driver nmclan_cs_driver = {
1503         .owner          = THIS_MODULE,
1504         .name           = "nmclan_cs",
1505         .probe          = nmclan_probe,
1506         .remove         = nmclan_detach,
1507         .id_table       = nmclan_ids,
1508         .suspend        = nmclan_suspend,
1509         .resume         = nmclan_resume,
1510 };
1511 module_pcmcia_driver(nmclan_cs_driver);
1512 

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