Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4

Linux/drivers/net/ethernet/amd/au1000_eth.c

  1 /*
  2  *
  3  * Alchemy Au1x00 ethernet driver
  4  *
  5  * Copyright 2001-2003, 2006 MontaVista Software Inc.
  6  * Copyright 2002 TimeSys Corp.
  7  * Added ethtool/mii-tool support,
  8  * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
  9  * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
 10  * or riemer@riemer-nt.de: fixed the link beat detection with
 11  * ioctls (SIOCGMIIPHY)
 12  * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org>
 13  *  converted to use linux-2.6.x's PHY framework
 14  *
 15  * Author: MontaVista Software, Inc.
 16  *              ppopov@mvista.com or source@mvista.com
 17  *
 18  * ########################################################################
 19  *
 20  *  This program is free software; you can distribute it and/or modify it
 21  *  under the terms of the GNU General Public License (Version 2) as
 22  *  published by the Free Software Foundation.
 23  *
 24  *  This program is distributed in the hope it will be useful, but WITHOUT
 25  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 26  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 27  *  for more details.
 28  *
 29  *  You should have received a copy of the GNU General Public License along
 30  *  with this program; if not, see <http://www.gnu.org/licenses/>.
 31  *
 32  * ########################################################################
 33  *
 34  *
 35  */
 36 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 37 
 38 #include <linux/capability.h>
 39 #include <linux/dma-mapping.h>
 40 #include <linux/module.h>
 41 #include <linux/kernel.h>
 42 #include <linux/string.h>
 43 #include <linux/timer.h>
 44 #include <linux/errno.h>
 45 #include <linux/in.h>
 46 #include <linux/ioport.h>
 47 #include <linux/bitops.h>
 48 #include <linux/slab.h>
 49 #include <linux/interrupt.h>
 50 #include <linux/netdevice.h>
 51 #include <linux/etherdevice.h>
 52 #include <linux/ethtool.h>
 53 #include <linux/mii.h>
 54 #include <linux/skbuff.h>
 55 #include <linux/delay.h>
 56 #include <linux/crc32.h>
 57 #include <linux/phy.h>
 58 #include <linux/platform_device.h>
 59 #include <linux/cpu.h>
 60 #include <linux/io.h>
 61 
 62 #include <asm/mipsregs.h>
 63 #include <asm/irq.h>
 64 #include <asm/processor.h>
 65 
 66 #include <au1000.h>
 67 #include <au1xxx_eth.h>
 68 #include <prom.h>
 69 
 70 #include "au1000_eth.h"
 71 
 72 #ifdef AU1000_ETH_DEBUG
 73 static int au1000_debug = 5;
 74 #else
 75 static int au1000_debug = 3;
 76 #endif
 77 
 78 #define AU1000_DEF_MSG_ENABLE   (NETIF_MSG_DRV  | \
 79                                 NETIF_MSG_PROBE | \
 80                                 NETIF_MSG_LINK)
 81 
 82 #define DRV_NAME        "au1000_eth"
 83 #define DRV_VERSION     "1.7"
 84 #define DRV_AUTHOR      "Pete Popov <ppopov@embeddedalley.com>"
 85 #define DRV_DESC        "Au1xxx on-chip Ethernet driver"
 86 
 87 MODULE_AUTHOR(DRV_AUTHOR);
 88 MODULE_DESCRIPTION(DRV_DESC);
 89 MODULE_LICENSE("GPL");
 90 MODULE_VERSION(DRV_VERSION);
 91 
 92 /* AU1000 MAC registers and bits */
 93 #define MAC_CONTROL             0x0
 94 #  define MAC_RX_ENABLE         (1 << 2)
 95 #  define MAC_TX_ENABLE         (1 << 3)
 96 #  define MAC_DEF_CHECK         (1 << 5)
 97 #  define MAC_SET_BL(X)         (((X) & 0x3) << 6)
 98 #  define MAC_AUTO_PAD          (1 << 8)
 99 #  define MAC_DISABLE_RETRY     (1 << 10)
100 #  define MAC_DISABLE_BCAST     (1 << 11)
101 #  define MAC_LATE_COL          (1 << 12)
102 #  define MAC_HASH_MODE         (1 << 13)
103 #  define MAC_HASH_ONLY         (1 << 15)
104 #  define MAC_PASS_ALL          (1 << 16)
105 #  define MAC_INVERSE_FILTER    (1 << 17)
106 #  define MAC_PROMISCUOUS       (1 << 18)
107 #  define MAC_PASS_ALL_MULTI    (1 << 19)
108 #  define MAC_FULL_DUPLEX       (1 << 20)
109 #  define MAC_NORMAL_MODE       0
110 #  define MAC_INT_LOOPBACK      (1 << 21)
111 #  define MAC_EXT_LOOPBACK      (1 << 22)
112 #  define MAC_DISABLE_RX_OWN    (1 << 23)
113 #  define MAC_BIG_ENDIAN        (1 << 30)
114 #  define MAC_RX_ALL            (1 << 31)
115 #define MAC_ADDRESS_HIGH        0x4
116 #define MAC_ADDRESS_LOW         0x8
117 #define MAC_MCAST_HIGH          0xC
118 #define MAC_MCAST_LOW           0x10
119 #define MAC_MII_CNTRL           0x14
120 #  define MAC_MII_BUSY          (1 << 0)
121 #  define MAC_MII_READ          0
122 #  define MAC_MII_WRITE         (1 << 1)
123 #  define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
124 #  define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
125 #define MAC_MII_DATA            0x18
126 #define MAC_FLOW_CNTRL          0x1C
127 #  define MAC_FLOW_CNTRL_BUSY   (1 << 0)
128 #  define MAC_FLOW_CNTRL_ENABLE (1 << 1)
129 #  define MAC_PASS_CONTROL      (1 << 2)
130 #  define MAC_SET_PAUSE(X)      (((X) & 0xffff) << 16)
131 #define MAC_VLAN1_TAG           0x20
132 #define MAC_VLAN2_TAG           0x24
133 
134 /* Ethernet Controller Enable */
135 #  define MAC_EN_CLOCK_ENABLE   (1 << 0)
136 #  define MAC_EN_RESET0         (1 << 1)
137 #  define MAC_EN_TOSS           (0 << 2)
138 #  define MAC_EN_CACHEABLE      (1 << 3)
139 #  define MAC_EN_RESET1         (1 << 4)
140 #  define MAC_EN_RESET2         (1 << 5)
141 #  define MAC_DMA_RESET         (1 << 6)
142 
143 /* Ethernet Controller DMA Channels */
144 /* offsets from MAC_TX_RING_ADDR address */
145 #define MAC_TX_BUFF0_STATUS     0x0
146 #  define TX_FRAME_ABORTED      (1 << 0)
147 #  define TX_JAB_TIMEOUT        (1 << 1)
148 #  define TX_NO_CARRIER         (1 << 2)
149 #  define TX_LOSS_CARRIER       (1 << 3)
150 #  define TX_EXC_DEF            (1 << 4)
151 #  define TX_LATE_COLL_ABORT    (1 << 5)
152 #  define TX_EXC_COLL           (1 << 6)
153 #  define TX_UNDERRUN           (1 << 7)
154 #  define TX_DEFERRED           (1 << 8)
155 #  define TX_LATE_COLL          (1 << 9)
156 #  define TX_COLL_CNT_MASK      (0xF << 10)
157 #  define TX_PKT_RETRY          (1 << 31)
158 #define MAC_TX_BUFF0_ADDR       0x4
159 #  define TX_DMA_ENABLE         (1 << 0)
160 #  define TX_T_DONE             (1 << 1)
161 #  define TX_GET_DMA_BUFFER(X)  (((X) >> 2) & 0x3)
162 #define MAC_TX_BUFF0_LEN        0x8
163 #define MAC_TX_BUFF1_STATUS     0x10
164 #define MAC_TX_BUFF1_ADDR       0x14
165 #define MAC_TX_BUFF1_LEN        0x18
166 #define MAC_TX_BUFF2_STATUS     0x20
167 #define MAC_TX_BUFF2_ADDR       0x24
168 #define MAC_TX_BUFF2_LEN        0x28
169 #define MAC_TX_BUFF3_STATUS     0x30
170 #define MAC_TX_BUFF3_ADDR       0x34
171 #define MAC_TX_BUFF3_LEN        0x38
172 
173 /* offsets from MAC_RX_RING_ADDR */
174 #define MAC_RX_BUFF0_STATUS     0x0
175 #  define RX_FRAME_LEN_MASK     0x3fff
176 #  define RX_WDOG_TIMER         (1 << 14)
177 #  define RX_RUNT               (1 << 15)
178 #  define RX_OVERLEN            (1 << 16)
179 #  define RX_COLL               (1 << 17)
180 #  define RX_ETHER              (1 << 18)
181 #  define RX_MII_ERROR          (1 << 19)
182 #  define RX_DRIBBLING          (1 << 20)
183 #  define RX_CRC_ERROR          (1 << 21)
184 #  define RX_VLAN1              (1 << 22)
185 #  define RX_VLAN2              (1 << 23)
186 #  define RX_LEN_ERROR          (1 << 24)
187 #  define RX_CNTRL_FRAME        (1 << 25)
188 #  define RX_U_CNTRL_FRAME      (1 << 26)
189 #  define RX_MCAST_FRAME        (1 << 27)
190 #  define RX_BCAST_FRAME        (1 << 28)
191 #  define RX_FILTER_FAIL        (1 << 29)
192 #  define RX_PACKET_FILTER      (1 << 30)
193 #  define RX_MISSED_FRAME       (1 << 31)
194 
195 #  define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN |  \
196                     RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
197                     RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
198 #define MAC_RX_BUFF0_ADDR       0x4
199 #  define RX_DMA_ENABLE         (1 << 0)
200 #  define RX_T_DONE             (1 << 1)
201 #  define RX_GET_DMA_BUFFER(X)  (((X) >> 2) & 0x3)
202 #  define RX_SET_BUFF_ADDR(X)   ((X) & 0xffffffc0)
203 #define MAC_RX_BUFF1_STATUS     0x10
204 #define MAC_RX_BUFF1_ADDR       0x14
205 #define MAC_RX_BUFF2_STATUS     0x20
206 #define MAC_RX_BUFF2_ADDR       0x24
207 #define MAC_RX_BUFF3_STATUS     0x30
208 #define MAC_RX_BUFF3_ADDR       0x34
209 
210 /*
211  * Theory of operation
212  *
213  * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
214  * There are four receive and four transmit descriptors.  These
215  * descriptors are not in memory; rather, they are just a set of
216  * hardware registers.
217  *
218  * Since the Au1000 has a coherent data cache, the receive and
219  * transmit buffers are allocated from the KSEG0 segment. The
220  * hardware registers, however, are still mapped at KSEG1 to
221  * make sure there's no out-of-order writes, and that all writes
222  * complete immediately.
223  */
224 
225 /*
226  * board-specific configurations
227  *
228  * PHY detection algorithm
229  *
230  * If phy_static_config is undefined, the PHY setup is
231  * autodetected:
232  *
233  * mii_probe() first searches the current MAC's MII bus for a PHY,
234  * selecting the first (or last, if phy_search_highest_addr is
235  * defined) PHY address not already claimed by another netdev.
236  *
237  * If nothing was found that way when searching for the 2nd ethernet
238  * controller's PHY and phy1_search_mac0 is defined, then
239  * the first MII bus is searched as well for an unclaimed PHY; this is
240  * needed in case of a dual-PHY accessible only through the MAC0's MII
241  * bus.
242  *
243  * Finally, if no PHY is found, then the corresponding ethernet
244  * controller is not registered to the network subsystem.
245  */
246 
247 /* autodetection defaults: phy1_search_mac0 */
248 
249 /* static PHY setup
250  *
251  * most boards PHY setup should be detectable properly with the
252  * autodetection algorithm in mii_probe(), but in some cases (e.g. if
253  * you have a switch attached, or want to use the PHY's interrupt
254  * notification capabilities) you can provide a static PHY
255  * configuration here
256  *
257  * IRQs may only be set, if a PHY address was configured
258  * If a PHY address is given, also a bus id is required to be set
259  *
260  * ps: make sure the used irqs are configured properly in the board
261  * specific irq-map
262  */
263 
264 static void au1000_enable_mac(struct net_device *dev, int force_reset)
265 {
266         unsigned long flags;
267         struct au1000_private *aup = netdev_priv(dev);
268 
269         spin_lock_irqsave(&aup->lock, flags);
270 
271         if (force_reset || (!aup->mac_enabled)) {
272                 writel(MAC_EN_CLOCK_ENABLE, aup->enable);
273                 wmb(); /* drain writebuffer */
274                 mdelay(2);
275                 writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
276                                 | MAC_EN_CLOCK_ENABLE), aup->enable);
277                 wmb(); /* drain writebuffer */
278                 mdelay(2);
279 
280                 aup->mac_enabled = 1;
281         }
282 
283         spin_unlock_irqrestore(&aup->lock, flags);
284 }
285 
286 /*
287  * MII operations
288  */
289 static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg)
290 {
291         struct au1000_private *aup = netdev_priv(dev);
292         u32 *const mii_control_reg = &aup->mac->mii_control;
293         u32 *const mii_data_reg = &aup->mac->mii_data;
294         u32 timedout = 20;
295         u32 mii_control;
296 
297         while (readl(mii_control_reg) & MAC_MII_BUSY) {
298                 mdelay(1);
299                 if (--timedout == 0) {
300                         netdev_err(dev, "read_MII busy timeout!!\n");
301                         return -1;
302                 }
303         }
304 
305         mii_control = MAC_SET_MII_SELECT_REG(reg) |
306                 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ;
307 
308         writel(mii_control, mii_control_reg);
309 
310         timedout = 20;
311         while (readl(mii_control_reg) & MAC_MII_BUSY) {
312                 mdelay(1);
313                 if (--timedout == 0) {
314                         netdev_err(dev, "mdio_read busy timeout!!\n");
315                         return -1;
316                 }
317         }
318         return readl(mii_data_reg);
319 }
320 
321 static void au1000_mdio_write(struct net_device *dev, int phy_addr,
322                               int reg, u16 value)
323 {
324         struct au1000_private *aup = netdev_priv(dev);
325         u32 *const mii_control_reg = &aup->mac->mii_control;
326         u32 *const mii_data_reg = &aup->mac->mii_data;
327         u32 timedout = 20;
328         u32 mii_control;
329 
330         while (readl(mii_control_reg) & MAC_MII_BUSY) {
331                 mdelay(1);
332                 if (--timedout == 0) {
333                         netdev_err(dev, "mdio_write busy timeout!!\n");
334                         return;
335                 }
336         }
337 
338         mii_control = MAC_SET_MII_SELECT_REG(reg) |
339                 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE;
340 
341         writel(value, mii_data_reg);
342         writel(mii_control, mii_control_reg);
343 }
344 
345 static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
346 {
347         /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does
348          * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus)
349          */
350         struct net_device *const dev = bus->priv;
351 
352         /* make sure the MAC associated with this
353          * mii_bus is enabled
354          */
355         au1000_enable_mac(dev, 0);
356 
357         return au1000_mdio_read(dev, phy_addr, regnum);
358 }
359 
360 static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
361                                 u16 value)
362 {
363         struct net_device *const dev = bus->priv;
364 
365         /* make sure the MAC associated with this
366          * mii_bus is enabled
367          */
368         au1000_enable_mac(dev, 0);
369 
370         au1000_mdio_write(dev, phy_addr, regnum, value);
371         return 0;
372 }
373 
374 static int au1000_mdiobus_reset(struct mii_bus *bus)
375 {
376         struct net_device *const dev = bus->priv;
377 
378         /* make sure the MAC associated with this
379          * mii_bus is enabled
380          */
381         au1000_enable_mac(dev, 0);
382 
383         return 0;
384 }
385 
386 static void au1000_hard_stop(struct net_device *dev)
387 {
388         struct au1000_private *aup = netdev_priv(dev);
389         u32 reg;
390 
391         netif_dbg(aup, drv, dev, "hard stop\n");
392 
393         reg = readl(&aup->mac->control);
394         reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
395         writel(reg, &aup->mac->control);
396         wmb(); /* drain writebuffer */
397         mdelay(10);
398 }
399 
400 static void au1000_enable_rx_tx(struct net_device *dev)
401 {
402         struct au1000_private *aup = netdev_priv(dev);
403         u32 reg;
404 
405         netif_dbg(aup, hw, dev, "enable_rx_tx\n");
406 
407         reg = readl(&aup->mac->control);
408         reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
409         writel(reg, &aup->mac->control);
410         wmb(); /* drain writebuffer */
411         mdelay(10);
412 }
413 
414 static void
415 au1000_adjust_link(struct net_device *dev)
416 {
417         struct au1000_private *aup = netdev_priv(dev);
418         struct phy_device *phydev = aup->phy_dev;
419         unsigned long flags;
420         u32 reg;
421 
422         int status_change = 0;
423 
424         BUG_ON(!aup->phy_dev);
425 
426         spin_lock_irqsave(&aup->lock, flags);
427 
428         if (phydev->link && (aup->old_speed != phydev->speed)) {
429                 /* speed changed */
430 
431                 switch (phydev->speed) {
432                 case SPEED_10:
433                 case SPEED_100:
434                         break;
435                 default:
436                         netdev_warn(dev, "Speed (%d) is not 10/100 ???\n",
437                                                         phydev->speed);
438                         break;
439                 }
440 
441                 aup->old_speed = phydev->speed;
442 
443                 status_change = 1;
444         }
445 
446         if (phydev->link && (aup->old_duplex != phydev->duplex)) {
447                 /* duplex mode changed */
448 
449                 /* switching duplex mode requires to disable rx and tx! */
450                 au1000_hard_stop(dev);
451 
452                 reg = readl(&aup->mac->control);
453                 if (DUPLEX_FULL == phydev->duplex) {
454                         reg |= MAC_FULL_DUPLEX;
455                         reg &= ~MAC_DISABLE_RX_OWN;
456                 } else {
457                         reg &= ~MAC_FULL_DUPLEX;
458                         reg |= MAC_DISABLE_RX_OWN;
459                 }
460                 writel(reg, &aup->mac->control);
461                 wmb(); /* drain writebuffer */
462                 mdelay(1);
463 
464                 au1000_enable_rx_tx(dev);
465                 aup->old_duplex = phydev->duplex;
466 
467                 status_change = 1;
468         }
469 
470         if (phydev->link != aup->old_link) {
471                 /* link state changed */
472 
473                 if (!phydev->link) {
474                         /* link went down */
475                         aup->old_speed = 0;
476                         aup->old_duplex = -1;
477                 }
478 
479                 aup->old_link = phydev->link;
480                 status_change = 1;
481         }
482 
483         spin_unlock_irqrestore(&aup->lock, flags);
484 
485         if (status_change) {
486                 if (phydev->link)
487                         netdev_info(dev, "link up (%d/%s)\n",
488                                phydev->speed,
489                                DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
490                 else
491                         netdev_info(dev, "link down\n");
492         }
493 }
494 
495 static int au1000_mii_probe(struct net_device *dev)
496 {
497         struct au1000_private *const aup = netdev_priv(dev);
498         struct phy_device *phydev = NULL;
499         int phy_addr;
500 
501         if (aup->phy_static_config) {
502                 BUG_ON(aup->mac_id < 0 || aup->mac_id > 1);
503 
504                 if (aup->phy_addr)
505                         phydev = aup->mii_bus->phy_map[aup->phy_addr];
506                 else
507                         netdev_info(dev, "using PHY-less setup\n");
508                 return 0;
509         }
510 
511         /* find the first (lowest address) PHY
512          * on the current MAC's MII bus
513          */
514         for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
515                 if (aup->mii_bus->phy_map[phy_addr]) {
516                         phydev = aup->mii_bus->phy_map[phy_addr];
517                         if (!aup->phy_search_highest_addr)
518                                 /* break out with first one found */
519                                 break;
520                 }
521 
522         if (aup->phy1_search_mac0) {
523                 /* try harder to find a PHY */
524                 if (!phydev && (aup->mac_id == 1)) {
525                         /* no PHY found, maybe we have a dual PHY? */
526                         dev_info(&dev->dev, ": no PHY found on MAC1, "
527                                 "let's see if it's attached to MAC0...\n");
528 
529                         /* find the first (lowest address) non-attached
530                          * PHY on the MAC0 MII bus
531                          */
532                         for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
533                                 struct phy_device *const tmp_phydev =
534                                         aup->mii_bus->phy_map[phy_addr];
535 
536                                 if (aup->mac_id == 1)
537                                         break;
538 
539                                 /* no PHY here... */
540                                 if (!tmp_phydev)
541                                         continue;
542 
543                                 /* already claimed by MAC0 */
544                                 if (tmp_phydev->attached_dev)
545                                         continue;
546 
547                                 phydev = tmp_phydev;
548                                 break; /* found it */
549                         }
550                 }
551         }
552 
553         if (!phydev) {
554                 netdev_err(dev, "no PHY found\n");
555                 return -1;
556         }
557 
558         /* now we are supposed to have a proper phydev, to attach to... */
559         BUG_ON(phydev->attached_dev);
560 
561         phydev = phy_connect(dev, dev_name(&phydev->dev),
562                              &au1000_adjust_link, PHY_INTERFACE_MODE_MII);
563 
564         if (IS_ERR(phydev)) {
565                 netdev_err(dev, "Could not attach to PHY\n");
566                 return PTR_ERR(phydev);
567         }
568 
569         /* mask with MAC supported features */
570         phydev->supported &= (SUPPORTED_10baseT_Half
571                               | SUPPORTED_10baseT_Full
572                               | SUPPORTED_100baseT_Half
573                               | SUPPORTED_100baseT_Full
574                               | SUPPORTED_Autoneg
575                               /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
576                               | SUPPORTED_MII
577                               | SUPPORTED_TP);
578 
579         phydev->advertising = phydev->supported;
580 
581         aup->old_link = 0;
582         aup->old_speed = 0;
583         aup->old_duplex = -1;
584         aup->phy_dev = phydev;
585 
586         netdev_info(dev, "attached PHY driver [%s] "
587                "(mii_bus:phy_addr=%s, irq=%d)\n",
588                phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
589 
590         return 0;
591 }
592 
593 
594 /*
595  * Buffer allocation/deallocation routines. The buffer descriptor returned
596  * has the virtual and dma address of a buffer suitable for
597  * both, receive and transmit operations.
598  */
599 static struct db_dest *au1000_GetFreeDB(struct au1000_private *aup)
600 {
601         struct db_dest *pDB;
602         pDB = aup->pDBfree;
603 
604         if (pDB)
605                 aup->pDBfree = pDB->pnext;
606 
607         return pDB;
608 }
609 
610 void au1000_ReleaseDB(struct au1000_private *aup, struct db_dest *pDB)
611 {
612         struct db_dest *pDBfree = aup->pDBfree;
613         if (pDBfree)
614                 pDBfree->pnext = pDB;
615         aup->pDBfree = pDB;
616 }
617 
618 static void au1000_reset_mac_unlocked(struct net_device *dev)
619 {
620         struct au1000_private *const aup = netdev_priv(dev);
621         int i;
622 
623         au1000_hard_stop(dev);
624 
625         writel(MAC_EN_CLOCK_ENABLE, aup->enable);
626         wmb(); /* drain writebuffer */
627         mdelay(2);
628         writel(0, aup->enable);
629         wmb(); /* drain writebuffer */
630         mdelay(2);
631 
632         aup->tx_full = 0;
633         for (i = 0; i < NUM_RX_DMA; i++) {
634                 /* reset control bits */
635                 aup->rx_dma_ring[i]->buff_stat &= ~0xf;
636         }
637         for (i = 0; i < NUM_TX_DMA; i++) {
638                 /* reset control bits */
639                 aup->tx_dma_ring[i]->buff_stat &= ~0xf;
640         }
641 
642         aup->mac_enabled = 0;
643 
644 }
645 
646 static void au1000_reset_mac(struct net_device *dev)
647 {
648         struct au1000_private *const aup = netdev_priv(dev);
649         unsigned long flags;
650 
651         netif_dbg(aup, hw, dev, "reset mac, aup %x\n",
652                                         (unsigned)aup);
653 
654         spin_lock_irqsave(&aup->lock, flags);
655 
656         au1000_reset_mac_unlocked(dev);
657 
658         spin_unlock_irqrestore(&aup->lock, flags);
659 }
660 
661 /*
662  * Setup the receive and transmit "rings".  These pointers are the addresses
663  * of the rx and tx MAC DMA registers so they are fixed by the hardware --
664  * these are not descriptors sitting in memory.
665  */
666 static void
667 au1000_setup_hw_rings(struct au1000_private *aup, void __iomem *tx_base)
668 {
669         int i;
670 
671         for (i = 0; i < NUM_RX_DMA; i++) {
672                 aup->rx_dma_ring[i] = (struct rx_dma *)
673                         (tx_base + 0x100 + sizeof(struct rx_dma) * i);
674         }
675         for (i = 0; i < NUM_TX_DMA; i++) {
676                 aup->tx_dma_ring[i] = (struct tx_dma *)
677                         (tx_base + sizeof(struct tx_dma) * i);
678         }
679 }
680 
681 /*
682  * ethtool operations
683  */
684 
685 static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
686 {
687         struct au1000_private *aup = netdev_priv(dev);
688 
689         if (aup->phy_dev)
690                 return phy_ethtool_gset(aup->phy_dev, cmd);
691 
692         return -EINVAL;
693 }
694 
695 static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
696 {
697         struct au1000_private *aup = netdev_priv(dev);
698 
699         if (!capable(CAP_NET_ADMIN))
700                 return -EPERM;
701 
702         if (aup->phy_dev)
703                 return phy_ethtool_sset(aup->phy_dev, cmd);
704 
705         return -EINVAL;
706 }
707 
708 static void
709 au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
710 {
711         struct au1000_private *aup = netdev_priv(dev);
712 
713         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
714         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
715         snprintf(info->bus_info, sizeof(info->bus_info), "%s %d", DRV_NAME,
716                  aup->mac_id);
717 }
718 
719 static void au1000_set_msglevel(struct net_device *dev, u32 value)
720 {
721         struct au1000_private *aup = netdev_priv(dev);
722         aup->msg_enable = value;
723 }
724 
725 static u32 au1000_get_msglevel(struct net_device *dev)
726 {
727         struct au1000_private *aup = netdev_priv(dev);
728         return aup->msg_enable;
729 }
730 
731 static const struct ethtool_ops au1000_ethtool_ops = {
732         .get_settings = au1000_get_settings,
733         .set_settings = au1000_set_settings,
734         .get_drvinfo = au1000_get_drvinfo,
735         .get_link = ethtool_op_get_link,
736         .get_msglevel = au1000_get_msglevel,
737         .set_msglevel = au1000_set_msglevel,
738 };
739 
740 
741 /*
742  * Initialize the interface.
743  *
744  * When the device powers up, the clocks are disabled and the
745  * mac is in reset state.  When the interface is closed, we
746  * do the same -- reset the device and disable the clocks to
747  * conserve power. Thus, whenever au1000_init() is called,
748  * the device should already be in reset state.
749  */
750 static int au1000_init(struct net_device *dev)
751 {
752         struct au1000_private *aup = netdev_priv(dev);
753         unsigned long flags;
754         int i;
755         u32 control;
756 
757         netif_dbg(aup, hw, dev, "au1000_init\n");
758 
759         /* bring the device out of reset */
760         au1000_enable_mac(dev, 1);
761 
762         spin_lock_irqsave(&aup->lock, flags);
763 
764         writel(0, &aup->mac->control);
765         aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
766         aup->tx_tail = aup->tx_head;
767         aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
768 
769         writel(dev->dev_addr[5]<<8 | dev->dev_addr[4],
770                                         &aup->mac->mac_addr_high);
771         writel(dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
772                 dev->dev_addr[1]<<8 | dev->dev_addr[0],
773                                         &aup->mac->mac_addr_low);
774 
775 
776         for (i = 0; i < NUM_RX_DMA; i++)
777                 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
778 
779         wmb(); /* drain writebuffer */
780 
781         control = MAC_RX_ENABLE | MAC_TX_ENABLE;
782 #ifndef CONFIG_CPU_LITTLE_ENDIAN
783         control |= MAC_BIG_ENDIAN;
784 #endif
785         if (aup->phy_dev) {
786                 if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex))
787                         control |= MAC_FULL_DUPLEX;
788                 else
789                         control |= MAC_DISABLE_RX_OWN;
790         } else { /* PHY-less op, assume full-duplex */
791                 control |= MAC_FULL_DUPLEX;
792         }
793 
794         writel(control, &aup->mac->control);
795         writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */
796         wmb(); /* drain writebuffer */
797 
798         spin_unlock_irqrestore(&aup->lock, flags);
799         return 0;
800 }
801 
802 static inline void au1000_update_rx_stats(struct net_device *dev, u32 status)
803 {
804         struct net_device_stats *ps = &dev->stats;
805 
806         ps->rx_packets++;
807         if (status & RX_MCAST_FRAME)
808                 ps->multicast++;
809 
810         if (status & RX_ERROR) {
811                 ps->rx_errors++;
812                 if (status & RX_MISSED_FRAME)
813                         ps->rx_missed_errors++;
814                 if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR))
815                         ps->rx_length_errors++;
816                 if (status & RX_CRC_ERROR)
817                         ps->rx_crc_errors++;
818                 if (status & RX_COLL)
819                         ps->collisions++;
820         } else
821                 ps->rx_bytes += status & RX_FRAME_LEN_MASK;
822 
823 }
824 
825 /*
826  * Au1000 receive routine.
827  */
828 static int au1000_rx(struct net_device *dev)
829 {
830         struct au1000_private *aup = netdev_priv(dev);
831         struct sk_buff *skb;
832         struct rx_dma *prxd;
833         u32 buff_stat, status;
834         struct db_dest *pDB;
835         u32     frmlen;
836 
837         netif_dbg(aup, rx_status, dev, "au1000_rx head %d\n", aup->rx_head);
838 
839         prxd = aup->rx_dma_ring[aup->rx_head];
840         buff_stat = prxd->buff_stat;
841         while (buff_stat & RX_T_DONE)  {
842                 status = prxd->status;
843                 pDB = aup->rx_db_inuse[aup->rx_head];
844                 au1000_update_rx_stats(dev, status);
845                 if (!(status & RX_ERROR))  {
846 
847                         /* good frame */
848                         frmlen = (status & RX_FRAME_LEN_MASK);
849                         frmlen -= 4; /* Remove FCS */
850                         skb = netdev_alloc_skb(dev, frmlen + 2);
851                         if (skb == NULL) {
852                                 dev->stats.rx_dropped++;
853                                 continue;
854                         }
855                         skb_reserve(skb, 2);    /* 16 byte IP header align */
856                         skb_copy_to_linear_data(skb,
857                                 (unsigned char *)pDB->vaddr, frmlen);
858                         skb_put(skb, frmlen);
859                         skb->protocol = eth_type_trans(skb, dev);
860                         netif_rx(skb);  /* pass the packet to upper layers */
861                 } else {
862                         if (au1000_debug > 4) {
863                                 pr_err("rx_error(s):");
864                                 if (status & RX_MISSED_FRAME)
865                                         pr_cont(" miss");
866                                 if (status & RX_WDOG_TIMER)
867                                         pr_cont(" wdog");
868                                 if (status & RX_RUNT)
869                                         pr_cont(" runt");
870                                 if (status & RX_OVERLEN)
871                                         pr_cont(" overlen");
872                                 if (status & RX_COLL)
873                                         pr_cont(" coll");
874                                 if (status & RX_MII_ERROR)
875                                         pr_cont(" mii error");
876                                 if (status & RX_CRC_ERROR)
877                                         pr_cont(" crc error");
878                                 if (status & RX_LEN_ERROR)
879                                         pr_cont(" len error");
880                                 if (status & RX_U_CNTRL_FRAME)
881                                         pr_cont(" u control frame");
882                                 pr_cont("\n");
883                         }
884                 }
885                 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
886                 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
887                 wmb(); /* drain writebuffer */
888 
889                 /* next descriptor */
890                 prxd = aup->rx_dma_ring[aup->rx_head];
891                 buff_stat = prxd->buff_stat;
892         }
893         return 0;
894 }
895 
896 static void au1000_update_tx_stats(struct net_device *dev, u32 status)
897 {
898         struct au1000_private *aup = netdev_priv(dev);
899         struct net_device_stats *ps = &dev->stats;
900 
901         if (status & TX_FRAME_ABORTED) {
902                 if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) {
903                         if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
904                                 /* any other tx errors are only valid
905                                  * in half duplex mode
906                                  */
907                                 ps->tx_errors++;
908                                 ps->tx_aborted_errors++;
909                         }
910                 } else {
911                         ps->tx_errors++;
912                         ps->tx_aborted_errors++;
913                         if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
914                                 ps->tx_carrier_errors++;
915                 }
916         }
917 }
918 
919 /*
920  * Called from the interrupt service routine to acknowledge
921  * the TX DONE bits.  This is a must if the irq is setup as
922  * edge triggered.
923  */
924 static void au1000_tx_ack(struct net_device *dev)
925 {
926         struct au1000_private *aup = netdev_priv(dev);
927         struct tx_dma *ptxd;
928 
929         ptxd = aup->tx_dma_ring[aup->tx_tail];
930 
931         while (ptxd->buff_stat & TX_T_DONE) {
932                 au1000_update_tx_stats(dev, ptxd->status);
933                 ptxd->buff_stat &= ~TX_T_DONE;
934                 ptxd->len = 0;
935                 wmb(); /* drain writebuffer */
936 
937                 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
938                 ptxd = aup->tx_dma_ring[aup->tx_tail];
939 
940                 if (aup->tx_full) {
941                         aup->tx_full = 0;
942                         netif_wake_queue(dev);
943                 }
944         }
945 }
946 
947 /*
948  * Au1000 interrupt service routine.
949  */
950 static irqreturn_t au1000_interrupt(int irq, void *dev_id)
951 {
952         struct net_device *dev = dev_id;
953 
954         /* Handle RX interrupts first to minimize chance of overrun */
955 
956         au1000_rx(dev);
957         au1000_tx_ack(dev);
958         return IRQ_RETVAL(1);
959 }
960 
961 static int au1000_open(struct net_device *dev)
962 {
963         int retval;
964         struct au1000_private *aup = netdev_priv(dev);
965 
966         netif_dbg(aup, drv, dev, "open: dev=%p\n", dev);
967 
968         retval = request_irq(dev->irq, au1000_interrupt, 0,
969                                         dev->name, dev);
970         if (retval) {
971                 netdev_err(dev, "unable to get IRQ %d\n", dev->irq);
972                 return retval;
973         }
974 
975         retval = au1000_init(dev);
976         if (retval) {
977                 netdev_err(dev, "error in au1000_init\n");
978                 free_irq(dev->irq, dev);
979                 return retval;
980         }
981 
982         if (aup->phy_dev) {
983                 /* cause the PHY state machine to schedule a link state check */
984                 aup->phy_dev->state = PHY_CHANGELINK;
985                 phy_start(aup->phy_dev);
986         }
987 
988         netif_start_queue(dev);
989 
990         netif_dbg(aup, drv, dev, "open: Initialization done.\n");
991 
992         return 0;
993 }
994 
995 static int au1000_close(struct net_device *dev)
996 {
997         unsigned long flags;
998         struct au1000_private *const aup = netdev_priv(dev);
999 
1000         netif_dbg(aup, drv, dev, "close: dev=%p\n", dev);
1001 
1002         if (aup->phy_dev)
1003                 phy_stop(aup->phy_dev);
1004 
1005         spin_lock_irqsave(&aup->lock, flags);
1006 
1007         au1000_reset_mac_unlocked(dev);
1008 
1009         /* stop the device */
1010         netif_stop_queue(dev);
1011 
1012         /* disable the interrupt */
1013         free_irq(dev->irq, dev);
1014         spin_unlock_irqrestore(&aup->lock, flags);
1015 
1016         return 0;
1017 }
1018 
1019 /*
1020  * Au1000 transmit routine.
1021  */
1022 static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev)
1023 {
1024         struct au1000_private *aup = netdev_priv(dev);
1025         struct net_device_stats *ps = &dev->stats;
1026         struct tx_dma *ptxd;
1027         u32 buff_stat;
1028         struct db_dest *pDB;
1029         int i;
1030 
1031         netif_dbg(aup, tx_queued, dev, "tx: aup %x len=%d, data=%p, head %d\n",
1032                                 (unsigned)aup, skb->len,
1033                                 skb->data, aup->tx_head);
1034 
1035         ptxd = aup->tx_dma_ring[aup->tx_head];
1036         buff_stat = ptxd->buff_stat;
1037         if (buff_stat & TX_DMA_ENABLE) {
1038                 /* We've wrapped around and the transmitter is still busy */
1039                 netif_stop_queue(dev);
1040                 aup->tx_full = 1;
1041                 return NETDEV_TX_BUSY;
1042         } else if (buff_stat & TX_T_DONE) {
1043                 au1000_update_tx_stats(dev, ptxd->status);
1044                 ptxd->len = 0;
1045         }
1046 
1047         if (aup->tx_full) {
1048                 aup->tx_full = 0;
1049                 netif_wake_queue(dev);
1050         }
1051 
1052         pDB = aup->tx_db_inuse[aup->tx_head];
1053         skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len);
1054         if (skb->len < ETH_ZLEN) {
1055                 for (i = skb->len; i < ETH_ZLEN; i++)
1056                         ((char *)pDB->vaddr)[i] = 0;
1057 
1058                 ptxd->len = ETH_ZLEN;
1059         } else
1060                 ptxd->len = skb->len;
1061 
1062         ps->tx_packets++;
1063         ps->tx_bytes += ptxd->len;
1064 
1065         ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
1066         wmb(); /* drain writebuffer */
1067         dev_kfree_skb(skb);
1068         aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
1069         return NETDEV_TX_OK;
1070 }
1071 
1072 /*
1073  * The Tx ring has been full longer than the watchdog timeout
1074  * value. The transmitter must be hung?
1075  */
1076 static void au1000_tx_timeout(struct net_device *dev)
1077 {
1078         netdev_err(dev, "au1000_tx_timeout: dev=%p\n", dev);
1079         au1000_reset_mac(dev);
1080         au1000_init(dev);
1081         dev->trans_start = jiffies; /* prevent tx timeout */
1082         netif_wake_queue(dev);
1083 }
1084 
1085 static void au1000_multicast_list(struct net_device *dev)
1086 {
1087         struct au1000_private *aup = netdev_priv(dev);
1088         u32 reg;
1089 
1090         netif_dbg(aup, drv, dev, "%s: flags=%x\n", __func__, dev->flags);
1091         reg = readl(&aup->mac->control);
1092         if (dev->flags & IFF_PROMISC) {                 /* Set promiscuous. */
1093                 reg |= MAC_PROMISCUOUS;
1094         } else if ((dev->flags & IFF_ALLMULTI)  ||
1095                            netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) {
1096                 reg |= MAC_PASS_ALL_MULTI;
1097                 reg &= ~MAC_PROMISCUOUS;
1098                 netdev_info(dev, "Pass all multicast\n");
1099         } else {
1100                 struct netdev_hw_addr *ha;
1101                 u32 mc_filter[2];       /* Multicast hash filter */
1102 
1103                 mc_filter[1] = mc_filter[0] = 0;
1104                 netdev_for_each_mc_addr(ha, dev)
1105                         set_bit(ether_crc(ETH_ALEN, ha->addr)>>26,
1106                                         (long *)mc_filter);
1107                 writel(mc_filter[1], &aup->mac->multi_hash_high);
1108                 writel(mc_filter[0], &aup->mac->multi_hash_low);
1109                 reg &= ~MAC_PROMISCUOUS;
1110                 reg |= MAC_HASH_MODE;
1111         }
1112         writel(reg, &aup->mac->control);
1113 }
1114 
1115 static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1116 {
1117         struct au1000_private *aup = netdev_priv(dev);
1118 
1119         if (!netif_running(dev))
1120                 return -EINVAL;
1121 
1122         if (!aup->phy_dev)
1123                 return -EINVAL; /* PHY not controllable */
1124 
1125         return phy_mii_ioctl(aup->phy_dev, rq, cmd);
1126 }
1127 
1128 static const struct net_device_ops au1000_netdev_ops = {
1129         .ndo_open               = au1000_open,
1130         .ndo_stop               = au1000_close,
1131         .ndo_start_xmit         = au1000_tx,
1132         .ndo_set_rx_mode        = au1000_multicast_list,
1133         .ndo_do_ioctl           = au1000_ioctl,
1134         .ndo_tx_timeout         = au1000_tx_timeout,
1135         .ndo_set_mac_address    = eth_mac_addr,
1136         .ndo_validate_addr      = eth_validate_addr,
1137         .ndo_change_mtu         = eth_change_mtu,
1138 };
1139 
1140 static int au1000_probe(struct platform_device *pdev)
1141 {
1142         struct au1000_private *aup = NULL;
1143         struct au1000_eth_platform_data *pd;
1144         struct net_device *dev = NULL;
1145         struct db_dest *pDB, *pDBfree;
1146         int irq, i, err = 0;
1147         struct resource *base, *macen, *macdma;
1148 
1149         base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1150         if (!base) {
1151                 dev_err(&pdev->dev, "failed to retrieve base register\n");
1152                 err = -ENODEV;
1153                 goto out;
1154         }
1155 
1156         macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1157         if (!macen) {
1158                 dev_err(&pdev->dev, "failed to retrieve MAC Enable register\n");
1159                 err = -ENODEV;
1160                 goto out;
1161         }
1162 
1163         irq = platform_get_irq(pdev, 0);
1164         if (irq < 0) {
1165                 dev_err(&pdev->dev, "failed to retrieve IRQ\n");
1166                 err = -ENODEV;
1167                 goto out;
1168         }
1169 
1170         macdma = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1171         if (!macdma) {
1172                 dev_err(&pdev->dev, "failed to retrieve MACDMA registers\n");
1173                 err = -ENODEV;
1174                 goto out;
1175         }
1176 
1177         if (!request_mem_region(base->start, resource_size(base),
1178                                                         pdev->name)) {
1179                 dev_err(&pdev->dev, "failed to request memory region for base registers\n");
1180                 err = -ENXIO;
1181                 goto out;
1182         }
1183 
1184         if (!request_mem_region(macen->start, resource_size(macen),
1185                                                         pdev->name)) {
1186                 dev_err(&pdev->dev, "failed to request memory region for MAC enable register\n");
1187                 err = -ENXIO;
1188                 goto err_request;
1189         }
1190 
1191         if (!request_mem_region(macdma->start, resource_size(macdma),
1192                                                         pdev->name)) {
1193                 dev_err(&pdev->dev, "failed to request MACDMA memory region\n");
1194                 err = -ENXIO;
1195                 goto err_macdma;
1196         }
1197 
1198         dev = alloc_etherdev(sizeof(struct au1000_private));
1199         if (!dev) {
1200                 err = -ENOMEM;
1201                 goto err_alloc;
1202         }
1203 
1204         SET_NETDEV_DEV(dev, &pdev->dev);
1205         platform_set_drvdata(pdev, dev);
1206         aup = netdev_priv(dev);
1207 
1208         spin_lock_init(&aup->lock);
1209         aup->msg_enable = (au1000_debug < 4 ?
1210                                 AU1000_DEF_MSG_ENABLE : au1000_debug);
1211 
1212         /* Allocate the data buffers
1213          * Snooping works fine with eth on all au1xxx
1214          */
1215         aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
1216                                                 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1217                                                 &aup->dma_addr, 0);
1218         if (!aup->vaddr) {
1219                 dev_err(&pdev->dev, "failed to allocate data buffers\n");
1220                 err = -ENOMEM;
1221                 goto err_vaddr;
1222         }
1223 
1224         /* aup->mac is the base address of the MAC's registers */
1225         aup->mac = (struct mac_reg *)
1226                         ioremap_nocache(base->start, resource_size(base));
1227         if (!aup->mac) {
1228                 dev_err(&pdev->dev, "failed to ioremap MAC registers\n");
1229                 err = -ENXIO;
1230                 goto err_remap1;
1231         }
1232 
1233         /* Setup some variables for quick register address access */
1234         aup->enable = (u32 *)ioremap_nocache(macen->start,
1235                                                 resource_size(macen));
1236         if (!aup->enable) {
1237                 dev_err(&pdev->dev, "failed to ioremap MAC enable register\n");
1238                 err = -ENXIO;
1239                 goto err_remap2;
1240         }
1241         aup->mac_id = pdev->id;
1242 
1243         aup->macdma = ioremap_nocache(macdma->start, resource_size(macdma));
1244         if (!aup->macdma) {
1245                 dev_err(&pdev->dev, "failed to ioremap MACDMA registers\n");
1246                 err = -ENXIO;
1247                 goto err_remap3;
1248         }
1249 
1250         au1000_setup_hw_rings(aup, aup->macdma);
1251 
1252         writel(0, aup->enable);
1253         aup->mac_enabled = 0;
1254 
1255         pd = dev_get_platdata(&pdev->dev);
1256         if (!pd) {
1257                 dev_info(&pdev->dev, "no platform_data passed,"
1258                                         " PHY search on MAC0\n");
1259                 aup->phy1_search_mac0 = 1;
1260         } else {
1261                 if (is_valid_ether_addr(pd->mac)) {
1262                         memcpy(dev->dev_addr, pd->mac, ETH_ALEN);
1263                 } else {
1264                         /* Set a random MAC since no valid provided by platform_data. */
1265                         eth_hw_addr_random(dev);
1266                 }
1267 
1268                 aup->phy_static_config = pd->phy_static_config;
1269                 aup->phy_search_highest_addr = pd->phy_search_highest_addr;
1270                 aup->phy1_search_mac0 = pd->phy1_search_mac0;
1271                 aup->phy_addr = pd->phy_addr;
1272                 aup->phy_busid = pd->phy_busid;
1273                 aup->phy_irq = pd->phy_irq;
1274         }
1275 
1276         if (aup->phy_busid && aup->phy_busid > 0) {
1277                 dev_err(&pdev->dev, "MAC0-associated PHY attached 2nd MACs MII bus not supported yet\n");
1278                 err = -ENODEV;
1279                 goto err_mdiobus_alloc;
1280         }
1281 
1282         aup->mii_bus = mdiobus_alloc();
1283         if (aup->mii_bus == NULL) {
1284                 dev_err(&pdev->dev, "failed to allocate mdiobus structure\n");
1285                 err = -ENOMEM;
1286                 goto err_mdiobus_alloc;
1287         }
1288 
1289         aup->mii_bus->priv = dev;
1290         aup->mii_bus->read = au1000_mdiobus_read;
1291         aup->mii_bus->write = au1000_mdiobus_write;
1292         aup->mii_bus->reset = au1000_mdiobus_reset;
1293         aup->mii_bus->name = "au1000_eth_mii";
1294         snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1295                 pdev->name, aup->mac_id);
1296         aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1297         if (aup->mii_bus->irq == NULL) {
1298                 err = -ENOMEM;
1299                 goto err_out;
1300         }
1301 
1302         for (i = 0; i < PHY_MAX_ADDR; ++i)
1303                 aup->mii_bus->irq[i] = PHY_POLL;
1304         /* if known, set corresponding PHY IRQs */
1305         if (aup->phy_static_config)
1306                 if (aup->phy_irq && aup->phy_busid == aup->mac_id)
1307                         aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq;
1308 
1309         err = mdiobus_register(aup->mii_bus);
1310         if (err) {
1311                 dev_err(&pdev->dev, "failed to register MDIO bus\n");
1312                 goto err_mdiobus_reg;
1313         }
1314 
1315         err = au1000_mii_probe(dev);
1316         if (err != 0)
1317                 goto err_out;
1318 
1319         pDBfree = NULL;
1320         /* setup the data buffer descriptors and attach a buffer to each one */
1321         pDB = aup->db;
1322         for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
1323                 pDB->pnext = pDBfree;
1324                 pDBfree = pDB;
1325                 pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
1326                 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
1327                 pDB++;
1328         }
1329         aup->pDBfree = pDBfree;
1330 
1331         err = -ENODEV;
1332         for (i = 0; i < NUM_RX_DMA; i++) {
1333                 pDB = au1000_GetFreeDB(aup);
1334                 if (!pDB)
1335                         goto err_out;
1336 
1337                 aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1338                 aup->rx_db_inuse[i] = pDB;
1339         }
1340 
1341         err = -ENODEV;
1342         for (i = 0; i < NUM_TX_DMA; i++) {
1343                 pDB = au1000_GetFreeDB(aup);
1344                 if (!pDB)
1345                         goto err_out;
1346 
1347                 aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1348                 aup->tx_dma_ring[i]->len = 0;
1349                 aup->tx_db_inuse[i] = pDB;
1350         }
1351 
1352         dev->base_addr = base->start;
1353         dev->irq = irq;
1354         dev->netdev_ops = &au1000_netdev_ops;
1355         dev->ethtool_ops = &au1000_ethtool_ops;
1356         dev->watchdog_timeo = ETH_TX_TIMEOUT;
1357 
1358         /*
1359          * The boot code uses the ethernet controller, so reset it to start
1360          * fresh.  au1000_init() expects that the device is in reset state.
1361          */
1362         au1000_reset_mac(dev);
1363 
1364         err = register_netdev(dev);
1365         if (err) {
1366                 netdev_err(dev, "Cannot register net device, aborting.\n");
1367                 goto err_out;
1368         }
1369 
1370         netdev_info(dev, "Au1xx0 Ethernet found at 0x%lx, irq %d\n",
1371                         (unsigned long)base->start, irq);
1372 
1373         pr_info_once("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR);
1374 
1375         return 0;
1376 
1377 err_out:
1378         if (aup->mii_bus != NULL)
1379                 mdiobus_unregister(aup->mii_bus);
1380 
1381         /* here we should have a valid dev plus aup-> register addresses
1382          * so we can reset the mac properly.
1383          */
1384         au1000_reset_mac(dev);
1385 
1386         for (i = 0; i < NUM_RX_DMA; i++) {
1387                 if (aup->rx_db_inuse[i])
1388                         au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
1389         }
1390         for (i = 0; i < NUM_TX_DMA; i++) {
1391                 if (aup->tx_db_inuse[i])
1392                         au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
1393         }
1394 err_mdiobus_reg:
1395         mdiobus_free(aup->mii_bus);
1396 err_mdiobus_alloc:
1397         iounmap(aup->macdma);
1398 err_remap3:
1399         iounmap(aup->enable);
1400 err_remap2:
1401         iounmap(aup->mac);
1402 err_remap1:
1403         dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
1404                              (void *)aup->vaddr, aup->dma_addr);
1405 err_vaddr:
1406         free_netdev(dev);
1407 err_alloc:
1408         release_mem_region(macdma->start, resource_size(macdma));
1409 err_macdma:
1410         release_mem_region(macen->start, resource_size(macen));
1411 err_request:
1412         release_mem_region(base->start, resource_size(base));
1413 out:
1414         return err;
1415 }
1416 
1417 static int au1000_remove(struct platform_device *pdev)
1418 {
1419         struct net_device *dev = platform_get_drvdata(pdev);
1420         struct au1000_private *aup = netdev_priv(dev);
1421         int i;
1422         struct resource *base, *macen;
1423 
1424         unregister_netdev(dev);
1425         mdiobus_unregister(aup->mii_bus);
1426         mdiobus_free(aup->mii_bus);
1427 
1428         for (i = 0; i < NUM_RX_DMA; i++)
1429                 if (aup->rx_db_inuse[i])
1430                         au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
1431 
1432         for (i = 0; i < NUM_TX_DMA; i++)
1433                 if (aup->tx_db_inuse[i])
1434                         au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
1435 
1436         dma_free_noncoherent(NULL, MAX_BUF_SIZE *
1437                         (NUM_TX_BUFFS + NUM_RX_BUFFS),
1438                         (void *)aup->vaddr, aup->dma_addr);
1439 
1440         iounmap(aup->macdma);
1441         iounmap(aup->mac);
1442         iounmap(aup->enable);
1443 
1444         base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1445         release_mem_region(base->start, resource_size(base));
1446 
1447         base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1448         release_mem_region(base->start, resource_size(base));
1449 
1450         macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1451         release_mem_region(macen->start, resource_size(macen));
1452 
1453         free_netdev(dev);
1454 
1455         return 0;
1456 }
1457 
1458 static struct platform_driver au1000_eth_driver = {
1459         .probe  = au1000_probe,
1460         .remove = au1000_remove,
1461         .driver = {
1462                 .name   = "au1000-eth",
1463         },
1464 };
1465 
1466 module_platform_driver(au1000_eth_driver);
1467 
1468 MODULE_ALIAS("platform:au1000-eth");
1469 

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