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Linux/drivers/net/ethernet/amd/au1000_eth.c

  1 /*
  2  *
  3  * Alchemy Au1x00 ethernet driver
  4  *
  5  * Copyright 2001-2003, 2006 MontaVista Software Inc.
  6  * Copyright 2002 TimeSys Corp.
  7  * Added ethtool/mii-tool support,
  8  * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
  9  * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
 10  * or riemer@riemer-nt.de: fixed the link beat detection with
 11  * ioctls (SIOCGMIIPHY)
 12  * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org>
 13  *  converted to use linux-2.6.x's PHY framework
 14  *
 15  * Author: MontaVista Software, Inc.
 16  *              ppopov@mvista.com or source@mvista.com
 17  *
 18  * ########################################################################
 19  *
 20  *  This program is free software; you can distribute it and/or modify it
 21  *  under the terms of the GNU General Public License (Version 2) as
 22  *  published by the Free Software Foundation.
 23  *
 24  *  This program is distributed in the hope it will be useful, but WITHOUT
 25  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 26  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 27  *  for more details.
 28  *
 29  *  You should have received a copy of the GNU General Public License along
 30  *  with this program; if not, see <http://www.gnu.org/licenses/>.
 31  *
 32  * ########################################################################
 33  *
 34  *
 35  */
 36 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 37 
 38 #include <linux/capability.h>
 39 #include <linux/dma-mapping.h>
 40 #include <linux/module.h>
 41 #include <linux/kernel.h>
 42 #include <linux/string.h>
 43 #include <linux/timer.h>
 44 #include <linux/errno.h>
 45 #include <linux/in.h>
 46 #include <linux/ioport.h>
 47 #include <linux/bitops.h>
 48 #include <linux/slab.h>
 49 #include <linux/interrupt.h>
 50 #include <linux/netdevice.h>
 51 #include <linux/etherdevice.h>
 52 #include <linux/ethtool.h>
 53 #include <linux/mii.h>
 54 #include <linux/skbuff.h>
 55 #include <linux/delay.h>
 56 #include <linux/crc32.h>
 57 #include <linux/phy.h>
 58 #include <linux/platform_device.h>
 59 #include <linux/cpu.h>
 60 #include <linux/io.h>
 61 
 62 #include <asm/mipsregs.h>
 63 #include <asm/irq.h>
 64 #include <asm/processor.h>
 65 
 66 #include <au1000.h>
 67 #include <au1xxx_eth.h>
 68 #include <prom.h>
 69 
 70 #include "au1000_eth.h"
 71 
 72 #ifdef AU1000_ETH_DEBUG
 73 static int au1000_debug = 5;
 74 #else
 75 static int au1000_debug = 3;
 76 #endif
 77 
 78 #define AU1000_DEF_MSG_ENABLE   (NETIF_MSG_DRV  | \
 79                                 NETIF_MSG_PROBE | \
 80                                 NETIF_MSG_LINK)
 81 
 82 #define DRV_NAME        "au1000_eth"
 83 #define DRV_VERSION     "1.7"
 84 #define DRV_AUTHOR      "Pete Popov <ppopov@embeddedalley.com>"
 85 #define DRV_DESC        "Au1xxx on-chip Ethernet driver"
 86 
 87 MODULE_AUTHOR(DRV_AUTHOR);
 88 MODULE_DESCRIPTION(DRV_DESC);
 89 MODULE_LICENSE("GPL");
 90 MODULE_VERSION(DRV_VERSION);
 91 
 92 /* AU1000 MAC registers and bits */
 93 #define MAC_CONTROL             0x0
 94 #  define MAC_RX_ENABLE         (1 << 2)
 95 #  define MAC_TX_ENABLE         (1 << 3)
 96 #  define MAC_DEF_CHECK         (1 << 5)
 97 #  define MAC_SET_BL(X)         (((X) & 0x3) << 6)
 98 #  define MAC_AUTO_PAD          (1 << 8)
 99 #  define MAC_DISABLE_RETRY     (1 << 10)
100 #  define MAC_DISABLE_BCAST     (1 << 11)
101 #  define MAC_LATE_COL          (1 << 12)
102 #  define MAC_HASH_MODE         (1 << 13)
103 #  define MAC_HASH_ONLY         (1 << 15)
104 #  define MAC_PASS_ALL          (1 << 16)
105 #  define MAC_INVERSE_FILTER    (1 << 17)
106 #  define MAC_PROMISCUOUS       (1 << 18)
107 #  define MAC_PASS_ALL_MULTI    (1 << 19)
108 #  define MAC_FULL_DUPLEX       (1 << 20)
109 #  define MAC_NORMAL_MODE       0
110 #  define MAC_INT_LOOPBACK      (1 << 21)
111 #  define MAC_EXT_LOOPBACK      (1 << 22)
112 #  define MAC_DISABLE_RX_OWN    (1 << 23)
113 #  define MAC_BIG_ENDIAN        (1 << 30)
114 #  define MAC_RX_ALL            (1 << 31)
115 #define MAC_ADDRESS_HIGH        0x4
116 #define MAC_ADDRESS_LOW         0x8
117 #define MAC_MCAST_HIGH          0xC
118 #define MAC_MCAST_LOW           0x10
119 #define MAC_MII_CNTRL           0x14
120 #  define MAC_MII_BUSY          (1 << 0)
121 #  define MAC_MII_READ          0
122 #  define MAC_MII_WRITE         (1 << 1)
123 #  define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
124 #  define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
125 #define MAC_MII_DATA            0x18
126 #define MAC_FLOW_CNTRL          0x1C
127 #  define MAC_FLOW_CNTRL_BUSY   (1 << 0)
128 #  define MAC_FLOW_CNTRL_ENABLE (1 << 1)
129 #  define MAC_PASS_CONTROL      (1 << 2)
130 #  define MAC_SET_PAUSE(X)      (((X) & 0xffff) << 16)
131 #define MAC_VLAN1_TAG           0x20
132 #define MAC_VLAN2_TAG           0x24
133 
134 /* Ethernet Controller Enable */
135 #  define MAC_EN_CLOCK_ENABLE   (1 << 0)
136 #  define MAC_EN_RESET0         (1 << 1)
137 #  define MAC_EN_TOSS           (0 << 2)
138 #  define MAC_EN_CACHEABLE      (1 << 3)
139 #  define MAC_EN_RESET1         (1 << 4)
140 #  define MAC_EN_RESET2         (1 << 5)
141 #  define MAC_DMA_RESET         (1 << 6)
142 
143 /* Ethernet Controller DMA Channels */
144 /* offsets from MAC_TX_RING_ADDR address */
145 #define MAC_TX_BUFF0_STATUS     0x0
146 #  define TX_FRAME_ABORTED      (1 << 0)
147 #  define TX_JAB_TIMEOUT        (1 << 1)
148 #  define TX_NO_CARRIER         (1 << 2)
149 #  define TX_LOSS_CARRIER       (1 << 3)
150 #  define TX_EXC_DEF            (1 << 4)
151 #  define TX_LATE_COLL_ABORT    (1 << 5)
152 #  define TX_EXC_COLL           (1 << 6)
153 #  define TX_UNDERRUN           (1 << 7)
154 #  define TX_DEFERRED           (1 << 8)
155 #  define TX_LATE_COLL          (1 << 9)
156 #  define TX_COLL_CNT_MASK      (0xF << 10)
157 #  define TX_PKT_RETRY          (1 << 31)
158 #define MAC_TX_BUFF0_ADDR       0x4
159 #  define TX_DMA_ENABLE         (1 << 0)
160 #  define TX_T_DONE             (1 << 1)
161 #  define TX_GET_DMA_BUFFER(X)  (((X) >> 2) & 0x3)
162 #define MAC_TX_BUFF0_LEN        0x8
163 #define MAC_TX_BUFF1_STATUS     0x10
164 #define MAC_TX_BUFF1_ADDR       0x14
165 #define MAC_TX_BUFF1_LEN        0x18
166 #define MAC_TX_BUFF2_STATUS     0x20
167 #define MAC_TX_BUFF2_ADDR       0x24
168 #define MAC_TX_BUFF2_LEN        0x28
169 #define MAC_TX_BUFF3_STATUS     0x30
170 #define MAC_TX_BUFF3_ADDR       0x34
171 #define MAC_TX_BUFF3_LEN        0x38
172 
173 /* offsets from MAC_RX_RING_ADDR */
174 #define MAC_RX_BUFF0_STATUS     0x0
175 #  define RX_FRAME_LEN_MASK     0x3fff
176 #  define RX_WDOG_TIMER         (1 << 14)
177 #  define RX_RUNT               (1 << 15)
178 #  define RX_OVERLEN            (1 << 16)
179 #  define RX_COLL               (1 << 17)
180 #  define RX_ETHER              (1 << 18)
181 #  define RX_MII_ERROR          (1 << 19)
182 #  define RX_DRIBBLING          (1 << 20)
183 #  define RX_CRC_ERROR          (1 << 21)
184 #  define RX_VLAN1              (1 << 22)
185 #  define RX_VLAN2              (1 << 23)
186 #  define RX_LEN_ERROR          (1 << 24)
187 #  define RX_CNTRL_FRAME        (1 << 25)
188 #  define RX_U_CNTRL_FRAME      (1 << 26)
189 #  define RX_MCAST_FRAME        (1 << 27)
190 #  define RX_BCAST_FRAME        (1 << 28)
191 #  define RX_FILTER_FAIL        (1 << 29)
192 #  define RX_PACKET_FILTER      (1 << 30)
193 #  define RX_MISSED_FRAME       (1 << 31)
194 
195 #  define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN |  \
196                     RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
197                     RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
198 #define MAC_RX_BUFF0_ADDR       0x4
199 #  define RX_DMA_ENABLE         (1 << 0)
200 #  define RX_T_DONE             (1 << 1)
201 #  define RX_GET_DMA_BUFFER(X)  (((X) >> 2) & 0x3)
202 #  define RX_SET_BUFF_ADDR(X)   ((X) & 0xffffffc0)
203 #define MAC_RX_BUFF1_STATUS     0x10
204 #define MAC_RX_BUFF1_ADDR       0x14
205 #define MAC_RX_BUFF2_STATUS     0x20
206 #define MAC_RX_BUFF2_ADDR       0x24
207 #define MAC_RX_BUFF3_STATUS     0x30
208 #define MAC_RX_BUFF3_ADDR       0x34
209 
210 /*
211  * Theory of operation
212  *
213  * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
214  * There are four receive and four transmit descriptors.  These
215  * descriptors are not in memory; rather, they are just a set of
216  * hardware registers.
217  *
218  * Since the Au1000 has a coherent data cache, the receive and
219  * transmit buffers are allocated from the KSEG0 segment. The
220  * hardware registers, however, are still mapped at KSEG1 to
221  * make sure there's no out-of-order writes, and that all writes
222  * complete immediately.
223  */
224 
225 /*
226  * board-specific configurations
227  *
228  * PHY detection algorithm
229  *
230  * If phy_static_config is undefined, the PHY setup is
231  * autodetected:
232  *
233  * mii_probe() first searches the current MAC's MII bus for a PHY,
234  * selecting the first (or last, if phy_search_highest_addr is
235  * defined) PHY address not already claimed by another netdev.
236  *
237  * If nothing was found that way when searching for the 2nd ethernet
238  * controller's PHY and phy1_search_mac0 is defined, then
239  * the first MII bus is searched as well for an unclaimed PHY; this is
240  * needed in case of a dual-PHY accessible only through the MAC0's MII
241  * bus.
242  *
243  * Finally, if no PHY is found, then the corresponding ethernet
244  * controller is not registered to the network subsystem.
245  */
246 
247 /* autodetection defaults: phy1_search_mac0 */
248 
249 /* static PHY setup
250  *
251  * most boards PHY setup should be detectable properly with the
252  * autodetection algorithm in mii_probe(), but in some cases (e.g. if
253  * you have a switch attached, or want to use the PHY's interrupt
254  * notification capabilities) you can provide a static PHY
255  * configuration here
256  *
257  * IRQs may only be set, if a PHY address was configured
258  * If a PHY address is given, also a bus id is required to be set
259  *
260  * ps: make sure the used irqs are configured properly in the board
261  * specific irq-map
262  */
263 
264 static void au1000_enable_mac(struct net_device *dev, int force_reset)
265 {
266         unsigned long flags;
267         struct au1000_private *aup = netdev_priv(dev);
268 
269         spin_lock_irqsave(&aup->lock, flags);
270 
271         if (force_reset || (!aup->mac_enabled)) {
272                 writel(MAC_EN_CLOCK_ENABLE, aup->enable);
273                 wmb(); /* drain writebuffer */
274                 mdelay(2);
275                 writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
276                                 | MAC_EN_CLOCK_ENABLE), aup->enable);
277                 wmb(); /* drain writebuffer */
278                 mdelay(2);
279 
280                 aup->mac_enabled = 1;
281         }
282 
283         spin_unlock_irqrestore(&aup->lock, flags);
284 }
285 
286 /*
287  * MII operations
288  */
289 static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg)
290 {
291         struct au1000_private *aup = netdev_priv(dev);
292         u32 *const mii_control_reg = &aup->mac->mii_control;
293         u32 *const mii_data_reg = &aup->mac->mii_data;
294         u32 timedout = 20;
295         u32 mii_control;
296 
297         while (readl(mii_control_reg) & MAC_MII_BUSY) {
298                 mdelay(1);
299                 if (--timedout == 0) {
300                         netdev_err(dev, "read_MII busy timeout!!\n");
301                         return -1;
302                 }
303         }
304 
305         mii_control = MAC_SET_MII_SELECT_REG(reg) |
306                 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ;
307 
308         writel(mii_control, mii_control_reg);
309 
310         timedout = 20;
311         while (readl(mii_control_reg) & MAC_MII_BUSY) {
312                 mdelay(1);
313                 if (--timedout == 0) {
314                         netdev_err(dev, "mdio_read busy timeout!!\n");
315                         return -1;
316                 }
317         }
318         return readl(mii_data_reg);
319 }
320 
321 static void au1000_mdio_write(struct net_device *dev, int phy_addr,
322                               int reg, u16 value)
323 {
324         struct au1000_private *aup = netdev_priv(dev);
325         u32 *const mii_control_reg = &aup->mac->mii_control;
326         u32 *const mii_data_reg = &aup->mac->mii_data;
327         u32 timedout = 20;
328         u32 mii_control;
329 
330         while (readl(mii_control_reg) & MAC_MII_BUSY) {
331                 mdelay(1);
332                 if (--timedout == 0) {
333                         netdev_err(dev, "mdio_write busy timeout!!\n");
334                         return;
335                 }
336         }
337 
338         mii_control = MAC_SET_MII_SELECT_REG(reg) |
339                 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE;
340 
341         writel(value, mii_data_reg);
342         writel(mii_control, mii_control_reg);
343 }
344 
345 static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
346 {
347         struct net_device *const dev = bus->priv;
348 
349         /* make sure the MAC associated with this
350          * mii_bus is enabled
351          */
352         au1000_enable_mac(dev, 0);
353 
354         return au1000_mdio_read(dev, phy_addr, regnum);
355 }
356 
357 static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
358                                 u16 value)
359 {
360         struct net_device *const dev = bus->priv;
361 
362         /* make sure the MAC associated with this
363          * mii_bus is enabled
364          */
365         au1000_enable_mac(dev, 0);
366 
367         au1000_mdio_write(dev, phy_addr, regnum, value);
368         return 0;
369 }
370 
371 static int au1000_mdiobus_reset(struct mii_bus *bus)
372 {
373         struct net_device *const dev = bus->priv;
374 
375         /* make sure the MAC associated with this
376          * mii_bus is enabled
377          */
378         au1000_enable_mac(dev, 0);
379 
380         return 0;
381 }
382 
383 static void au1000_hard_stop(struct net_device *dev)
384 {
385         struct au1000_private *aup = netdev_priv(dev);
386         u32 reg;
387 
388         netif_dbg(aup, drv, dev, "hard stop\n");
389 
390         reg = readl(&aup->mac->control);
391         reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
392         writel(reg, &aup->mac->control);
393         wmb(); /* drain writebuffer */
394         mdelay(10);
395 }
396 
397 static void au1000_enable_rx_tx(struct net_device *dev)
398 {
399         struct au1000_private *aup = netdev_priv(dev);
400         u32 reg;
401 
402         netif_dbg(aup, hw, dev, "enable_rx_tx\n");
403 
404         reg = readl(&aup->mac->control);
405         reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
406         writel(reg, &aup->mac->control);
407         wmb(); /* drain writebuffer */
408         mdelay(10);
409 }
410 
411 static void
412 au1000_adjust_link(struct net_device *dev)
413 {
414         struct au1000_private *aup = netdev_priv(dev);
415         struct phy_device *phydev = aup->phy_dev;
416         unsigned long flags;
417         u32 reg;
418 
419         int status_change = 0;
420 
421         BUG_ON(!aup->phy_dev);
422 
423         spin_lock_irqsave(&aup->lock, flags);
424 
425         if (phydev->link && (aup->old_speed != phydev->speed)) {
426                 /* speed changed */
427 
428                 switch (phydev->speed) {
429                 case SPEED_10:
430                 case SPEED_100:
431                         break;
432                 default:
433                         netdev_warn(dev, "Speed (%d) is not 10/100 ???\n",
434                                                         phydev->speed);
435                         break;
436                 }
437 
438                 aup->old_speed = phydev->speed;
439 
440                 status_change = 1;
441         }
442 
443         if (phydev->link && (aup->old_duplex != phydev->duplex)) {
444                 /* duplex mode changed */
445 
446                 /* switching duplex mode requires to disable rx and tx! */
447                 au1000_hard_stop(dev);
448 
449                 reg = readl(&aup->mac->control);
450                 if (DUPLEX_FULL == phydev->duplex) {
451                         reg |= MAC_FULL_DUPLEX;
452                         reg &= ~MAC_DISABLE_RX_OWN;
453                 } else {
454                         reg &= ~MAC_FULL_DUPLEX;
455                         reg |= MAC_DISABLE_RX_OWN;
456                 }
457                 writel(reg, &aup->mac->control);
458                 wmb(); /* drain writebuffer */
459                 mdelay(1);
460 
461                 au1000_enable_rx_tx(dev);
462                 aup->old_duplex = phydev->duplex;
463 
464                 status_change = 1;
465         }
466 
467         if (phydev->link != aup->old_link) {
468                 /* link state changed */
469 
470                 if (!phydev->link) {
471                         /* link went down */
472                         aup->old_speed = 0;
473                         aup->old_duplex = -1;
474                 }
475 
476                 aup->old_link = phydev->link;
477                 status_change = 1;
478         }
479 
480         spin_unlock_irqrestore(&aup->lock, flags);
481 
482         if (status_change) {
483                 if (phydev->link)
484                         netdev_info(dev, "link up (%d/%s)\n",
485                                phydev->speed,
486                                DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
487                 else
488                         netdev_info(dev, "link down\n");
489         }
490 }
491 
492 static int au1000_mii_probe(struct net_device *dev)
493 {
494         struct au1000_private *const aup = netdev_priv(dev);
495         struct phy_device *phydev = NULL;
496         int phy_addr;
497 
498         if (aup->phy_static_config) {
499                 BUG_ON(aup->mac_id < 0 || aup->mac_id > 1);
500 
501                 if (aup->phy_addr)
502                         phydev = mdiobus_get_phy(aup->mii_bus, aup->phy_addr);
503                 else
504                         netdev_info(dev, "using PHY-less setup\n");
505                 return 0;
506         }
507 
508         /* find the first (lowest address) PHY
509          * on the current MAC's MII bus
510          */
511         for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
512                 if (mdiobus_get_phy(aup->mii_bus, aup->phy_addr)) {
513                         phydev = mdiobus_get_phy(aup->mii_bus, aup->phy_addr);
514                         if (!aup->phy_search_highest_addr)
515                                 /* break out with first one found */
516                                 break;
517                 }
518 
519         if (aup->phy1_search_mac0) {
520                 /* try harder to find a PHY */
521                 if (!phydev && (aup->mac_id == 1)) {
522                         /* no PHY found, maybe we have a dual PHY? */
523                         dev_info(&dev->dev, ": no PHY found on MAC1, "
524                                 "let's see if it's attached to MAC0...\n");
525 
526                         /* find the first (lowest address) non-attached
527                          * PHY on the MAC0 MII bus
528                          */
529                         for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
530                                 struct phy_device *const tmp_phydev =
531                                         mdiobus_get_phy(aup->mii_bus,
532                                                         phy_addr);
533 
534                                 if (aup->mac_id == 1)
535                                         break;
536 
537                                 /* no PHY here... */
538                                 if (!tmp_phydev)
539                                         continue;
540 
541                                 /* already claimed by MAC0 */
542                                 if (tmp_phydev->attached_dev)
543                                         continue;
544 
545                                 phydev = tmp_phydev;
546                                 break; /* found it */
547                         }
548                 }
549         }
550 
551         if (!phydev) {
552                 netdev_err(dev, "no PHY found\n");
553                 return -1;
554         }
555 
556         /* now we are supposed to have a proper phydev, to attach to... */
557         BUG_ON(phydev->attached_dev);
558 
559         phydev = phy_connect(dev, phydev_name(phydev),
560                              &au1000_adjust_link, PHY_INTERFACE_MODE_MII);
561 
562         if (IS_ERR(phydev)) {
563                 netdev_err(dev, "Could not attach to PHY\n");
564                 return PTR_ERR(phydev);
565         }
566 
567         /* mask with MAC supported features */
568         phydev->supported &= (SUPPORTED_10baseT_Half
569                               | SUPPORTED_10baseT_Full
570                               | SUPPORTED_100baseT_Half
571                               | SUPPORTED_100baseT_Full
572                               | SUPPORTED_Autoneg
573                               /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
574                               | SUPPORTED_MII
575                               | SUPPORTED_TP);
576 
577         phydev->advertising = phydev->supported;
578 
579         aup->old_link = 0;
580         aup->old_speed = 0;
581         aup->old_duplex = -1;
582         aup->phy_dev = phydev;
583 
584         phy_attached_info(phydev);
585 
586         return 0;
587 }
588 
589 
590 /*
591  * Buffer allocation/deallocation routines. The buffer descriptor returned
592  * has the virtual and dma address of a buffer suitable for
593  * both, receive and transmit operations.
594  */
595 static struct db_dest *au1000_GetFreeDB(struct au1000_private *aup)
596 {
597         struct db_dest *pDB;
598         pDB = aup->pDBfree;
599 
600         if (pDB)
601                 aup->pDBfree = pDB->pnext;
602 
603         return pDB;
604 }
605 
606 void au1000_ReleaseDB(struct au1000_private *aup, struct db_dest *pDB)
607 {
608         struct db_dest *pDBfree = aup->pDBfree;
609         if (pDBfree)
610                 pDBfree->pnext = pDB;
611         aup->pDBfree = pDB;
612 }
613 
614 static void au1000_reset_mac_unlocked(struct net_device *dev)
615 {
616         struct au1000_private *const aup = netdev_priv(dev);
617         int i;
618 
619         au1000_hard_stop(dev);
620 
621         writel(MAC_EN_CLOCK_ENABLE, aup->enable);
622         wmb(); /* drain writebuffer */
623         mdelay(2);
624         writel(0, aup->enable);
625         wmb(); /* drain writebuffer */
626         mdelay(2);
627 
628         aup->tx_full = 0;
629         for (i = 0; i < NUM_RX_DMA; i++) {
630                 /* reset control bits */
631                 aup->rx_dma_ring[i]->buff_stat &= ~0xf;
632         }
633         for (i = 0; i < NUM_TX_DMA; i++) {
634                 /* reset control bits */
635                 aup->tx_dma_ring[i]->buff_stat &= ~0xf;
636         }
637 
638         aup->mac_enabled = 0;
639 
640 }
641 
642 static void au1000_reset_mac(struct net_device *dev)
643 {
644         struct au1000_private *const aup = netdev_priv(dev);
645         unsigned long flags;
646 
647         netif_dbg(aup, hw, dev, "reset mac, aup %x\n",
648                                         (unsigned)aup);
649 
650         spin_lock_irqsave(&aup->lock, flags);
651 
652         au1000_reset_mac_unlocked(dev);
653 
654         spin_unlock_irqrestore(&aup->lock, flags);
655 }
656 
657 /*
658  * Setup the receive and transmit "rings".  These pointers are the addresses
659  * of the rx and tx MAC DMA registers so they are fixed by the hardware --
660  * these are not descriptors sitting in memory.
661  */
662 static void
663 au1000_setup_hw_rings(struct au1000_private *aup, void __iomem *tx_base)
664 {
665         int i;
666 
667         for (i = 0; i < NUM_RX_DMA; i++) {
668                 aup->rx_dma_ring[i] = (struct rx_dma *)
669                         (tx_base + 0x100 + sizeof(struct rx_dma) * i);
670         }
671         for (i = 0; i < NUM_TX_DMA; i++) {
672                 aup->tx_dma_ring[i] = (struct tx_dma *)
673                         (tx_base + sizeof(struct tx_dma) * i);
674         }
675 }
676 
677 /*
678  * ethtool operations
679  */
680 
681 static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
682 {
683         struct au1000_private *aup = netdev_priv(dev);
684 
685         if (aup->phy_dev)
686                 return phy_ethtool_gset(aup->phy_dev, cmd);
687 
688         return -EINVAL;
689 }
690 
691 static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
692 {
693         struct au1000_private *aup = netdev_priv(dev);
694 
695         if (!capable(CAP_NET_ADMIN))
696                 return -EPERM;
697 
698         if (aup->phy_dev)
699                 return phy_ethtool_sset(aup->phy_dev, cmd);
700 
701         return -EINVAL;
702 }
703 
704 static void
705 au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
706 {
707         struct au1000_private *aup = netdev_priv(dev);
708 
709         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
710         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
711         snprintf(info->bus_info, sizeof(info->bus_info), "%s %d", DRV_NAME,
712                  aup->mac_id);
713 }
714 
715 static void au1000_set_msglevel(struct net_device *dev, u32 value)
716 {
717         struct au1000_private *aup = netdev_priv(dev);
718         aup->msg_enable = value;
719 }
720 
721 static u32 au1000_get_msglevel(struct net_device *dev)
722 {
723         struct au1000_private *aup = netdev_priv(dev);
724         return aup->msg_enable;
725 }
726 
727 static const struct ethtool_ops au1000_ethtool_ops = {
728         .get_settings = au1000_get_settings,
729         .set_settings = au1000_set_settings,
730         .get_drvinfo = au1000_get_drvinfo,
731         .get_link = ethtool_op_get_link,
732         .get_msglevel = au1000_get_msglevel,
733         .set_msglevel = au1000_set_msglevel,
734 };
735 
736 
737 /*
738  * Initialize the interface.
739  *
740  * When the device powers up, the clocks are disabled and the
741  * mac is in reset state.  When the interface is closed, we
742  * do the same -- reset the device and disable the clocks to
743  * conserve power. Thus, whenever au1000_init() is called,
744  * the device should already be in reset state.
745  */
746 static int au1000_init(struct net_device *dev)
747 {
748         struct au1000_private *aup = netdev_priv(dev);
749         unsigned long flags;
750         int i;
751         u32 control;
752 
753         netif_dbg(aup, hw, dev, "au1000_init\n");
754 
755         /* bring the device out of reset */
756         au1000_enable_mac(dev, 1);
757 
758         spin_lock_irqsave(&aup->lock, flags);
759 
760         writel(0, &aup->mac->control);
761         aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
762         aup->tx_tail = aup->tx_head;
763         aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
764 
765         writel(dev->dev_addr[5]<<8 | dev->dev_addr[4],
766                                         &aup->mac->mac_addr_high);
767         writel(dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
768                 dev->dev_addr[1]<<8 | dev->dev_addr[0],
769                                         &aup->mac->mac_addr_low);
770 
771 
772         for (i = 0; i < NUM_RX_DMA; i++)
773                 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
774 
775         wmb(); /* drain writebuffer */
776 
777         control = MAC_RX_ENABLE | MAC_TX_ENABLE;
778 #ifndef CONFIG_CPU_LITTLE_ENDIAN
779         control |= MAC_BIG_ENDIAN;
780 #endif
781         if (aup->phy_dev) {
782                 if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex))
783                         control |= MAC_FULL_DUPLEX;
784                 else
785                         control |= MAC_DISABLE_RX_OWN;
786         } else { /* PHY-less op, assume full-duplex */
787                 control |= MAC_FULL_DUPLEX;
788         }
789 
790         writel(control, &aup->mac->control);
791         writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */
792         wmb(); /* drain writebuffer */
793 
794         spin_unlock_irqrestore(&aup->lock, flags);
795         return 0;
796 }
797 
798 static inline void au1000_update_rx_stats(struct net_device *dev, u32 status)
799 {
800         struct net_device_stats *ps = &dev->stats;
801 
802         ps->rx_packets++;
803         if (status & RX_MCAST_FRAME)
804                 ps->multicast++;
805 
806         if (status & RX_ERROR) {
807                 ps->rx_errors++;
808                 if (status & RX_MISSED_FRAME)
809                         ps->rx_missed_errors++;
810                 if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR))
811                         ps->rx_length_errors++;
812                 if (status & RX_CRC_ERROR)
813                         ps->rx_crc_errors++;
814                 if (status & RX_COLL)
815                         ps->collisions++;
816         } else
817                 ps->rx_bytes += status & RX_FRAME_LEN_MASK;
818 
819 }
820 
821 /*
822  * Au1000 receive routine.
823  */
824 static int au1000_rx(struct net_device *dev)
825 {
826         struct au1000_private *aup = netdev_priv(dev);
827         struct sk_buff *skb;
828         struct rx_dma *prxd;
829         u32 buff_stat, status;
830         struct db_dest *pDB;
831         u32     frmlen;
832 
833         netif_dbg(aup, rx_status, dev, "au1000_rx head %d\n", aup->rx_head);
834 
835         prxd = aup->rx_dma_ring[aup->rx_head];
836         buff_stat = prxd->buff_stat;
837         while (buff_stat & RX_T_DONE)  {
838                 status = prxd->status;
839                 pDB = aup->rx_db_inuse[aup->rx_head];
840                 au1000_update_rx_stats(dev, status);
841                 if (!(status & RX_ERROR))  {
842 
843                         /* good frame */
844                         frmlen = (status & RX_FRAME_LEN_MASK);
845                         frmlen -= 4; /* Remove FCS */
846                         skb = netdev_alloc_skb(dev, frmlen + 2);
847                         if (skb == NULL) {
848                                 dev->stats.rx_dropped++;
849                                 continue;
850                         }
851                         skb_reserve(skb, 2);    /* 16 byte IP header align */
852                         skb_copy_to_linear_data(skb,
853                                 (unsigned char *)pDB->vaddr, frmlen);
854                         skb_put(skb, frmlen);
855                         skb->protocol = eth_type_trans(skb, dev);
856                         netif_rx(skb);  /* pass the packet to upper layers */
857                 } else {
858                         if (au1000_debug > 4) {
859                                 pr_err("rx_error(s):");
860                                 if (status & RX_MISSED_FRAME)
861                                         pr_cont(" miss");
862                                 if (status & RX_WDOG_TIMER)
863                                         pr_cont(" wdog");
864                                 if (status & RX_RUNT)
865                                         pr_cont(" runt");
866                                 if (status & RX_OVERLEN)
867                                         pr_cont(" overlen");
868                                 if (status & RX_COLL)
869                                         pr_cont(" coll");
870                                 if (status & RX_MII_ERROR)
871                                         pr_cont(" mii error");
872                                 if (status & RX_CRC_ERROR)
873                                         pr_cont(" crc error");
874                                 if (status & RX_LEN_ERROR)
875                                         pr_cont(" len error");
876                                 if (status & RX_U_CNTRL_FRAME)
877                                         pr_cont(" u control frame");
878                                 pr_cont("\n");
879                         }
880                 }
881                 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
882                 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
883                 wmb(); /* drain writebuffer */
884 
885                 /* next descriptor */
886                 prxd = aup->rx_dma_ring[aup->rx_head];
887                 buff_stat = prxd->buff_stat;
888         }
889         return 0;
890 }
891 
892 static void au1000_update_tx_stats(struct net_device *dev, u32 status)
893 {
894         struct au1000_private *aup = netdev_priv(dev);
895         struct net_device_stats *ps = &dev->stats;
896 
897         if (status & TX_FRAME_ABORTED) {
898                 if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) {
899                         if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
900                                 /* any other tx errors are only valid
901                                  * in half duplex mode
902                                  */
903                                 ps->tx_errors++;
904                                 ps->tx_aborted_errors++;
905                         }
906                 } else {
907                         ps->tx_errors++;
908                         ps->tx_aborted_errors++;
909                         if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
910                                 ps->tx_carrier_errors++;
911                 }
912         }
913 }
914 
915 /*
916  * Called from the interrupt service routine to acknowledge
917  * the TX DONE bits.  This is a must if the irq is setup as
918  * edge triggered.
919  */
920 static void au1000_tx_ack(struct net_device *dev)
921 {
922         struct au1000_private *aup = netdev_priv(dev);
923         struct tx_dma *ptxd;
924 
925         ptxd = aup->tx_dma_ring[aup->tx_tail];
926 
927         while (ptxd->buff_stat & TX_T_DONE) {
928                 au1000_update_tx_stats(dev, ptxd->status);
929                 ptxd->buff_stat &= ~TX_T_DONE;
930                 ptxd->len = 0;
931                 wmb(); /* drain writebuffer */
932 
933                 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
934                 ptxd = aup->tx_dma_ring[aup->tx_tail];
935 
936                 if (aup->tx_full) {
937                         aup->tx_full = 0;
938                         netif_wake_queue(dev);
939                 }
940         }
941 }
942 
943 /*
944  * Au1000 interrupt service routine.
945  */
946 static irqreturn_t au1000_interrupt(int irq, void *dev_id)
947 {
948         struct net_device *dev = dev_id;
949 
950         /* Handle RX interrupts first to minimize chance of overrun */
951 
952         au1000_rx(dev);
953         au1000_tx_ack(dev);
954         return IRQ_RETVAL(1);
955 }
956 
957 static int au1000_open(struct net_device *dev)
958 {
959         int retval;
960         struct au1000_private *aup = netdev_priv(dev);
961 
962         netif_dbg(aup, drv, dev, "open: dev=%p\n", dev);
963 
964         retval = request_irq(dev->irq, au1000_interrupt, 0,
965                                         dev->name, dev);
966         if (retval) {
967                 netdev_err(dev, "unable to get IRQ %d\n", dev->irq);
968                 return retval;
969         }
970 
971         retval = au1000_init(dev);
972         if (retval) {
973                 netdev_err(dev, "error in au1000_init\n");
974                 free_irq(dev->irq, dev);
975                 return retval;
976         }
977 
978         if (aup->phy_dev) {
979                 /* cause the PHY state machine to schedule a link state check */
980                 aup->phy_dev->state = PHY_CHANGELINK;
981                 phy_start(aup->phy_dev);
982         }
983 
984         netif_start_queue(dev);
985 
986         netif_dbg(aup, drv, dev, "open: Initialization done.\n");
987 
988         return 0;
989 }
990 
991 static int au1000_close(struct net_device *dev)
992 {
993         unsigned long flags;
994         struct au1000_private *const aup = netdev_priv(dev);
995 
996         netif_dbg(aup, drv, dev, "close: dev=%p\n", dev);
997 
998         if (aup->phy_dev)
999                 phy_stop(aup->phy_dev);
1000 
1001         spin_lock_irqsave(&aup->lock, flags);
1002 
1003         au1000_reset_mac_unlocked(dev);
1004 
1005         /* stop the device */
1006         netif_stop_queue(dev);
1007 
1008         /* disable the interrupt */
1009         free_irq(dev->irq, dev);
1010         spin_unlock_irqrestore(&aup->lock, flags);
1011 
1012         return 0;
1013 }
1014 
1015 /*
1016  * Au1000 transmit routine.
1017  */
1018 static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev)
1019 {
1020         struct au1000_private *aup = netdev_priv(dev);
1021         struct net_device_stats *ps = &dev->stats;
1022         struct tx_dma *ptxd;
1023         u32 buff_stat;
1024         struct db_dest *pDB;
1025         int i;
1026 
1027         netif_dbg(aup, tx_queued, dev, "tx: aup %x len=%d, data=%p, head %d\n",
1028                                 (unsigned)aup, skb->len,
1029                                 skb->data, aup->tx_head);
1030 
1031         ptxd = aup->tx_dma_ring[aup->tx_head];
1032         buff_stat = ptxd->buff_stat;
1033         if (buff_stat & TX_DMA_ENABLE) {
1034                 /* We've wrapped around and the transmitter is still busy */
1035                 netif_stop_queue(dev);
1036                 aup->tx_full = 1;
1037                 return NETDEV_TX_BUSY;
1038         } else if (buff_stat & TX_T_DONE) {
1039                 au1000_update_tx_stats(dev, ptxd->status);
1040                 ptxd->len = 0;
1041         }
1042 
1043         if (aup->tx_full) {
1044                 aup->tx_full = 0;
1045                 netif_wake_queue(dev);
1046         }
1047 
1048         pDB = aup->tx_db_inuse[aup->tx_head];
1049         skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len);
1050         if (skb->len < ETH_ZLEN) {
1051                 for (i = skb->len; i < ETH_ZLEN; i++)
1052                         ((char *)pDB->vaddr)[i] = 0;
1053 
1054                 ptxd->len = ETH_ZLEN;
1055         } else
1056                 ptxd->len = skb->len;
1057 
1058         ps->tx_packets++;
1059         ps->tx_bytes += ptxd->len;
1060 
1061         ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
1062         wmb(); /* drain writebuffer */
1063         dev_kfree_skb(skb);
1064         aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
1065         return NETDEV_TX_OK;
1066 }
1067 
1068 /*
1069  * The Tx ring has been full longer than the watchdog timeout
1070  * value. The transmitter must be hung?
1071  */
1072 static void au1000_tx_timeout(struct net_device *dev)
1073 {
1074         netdev_err(dev, "au1000_tx_timeout: dev=%p\n", dev);
1075         au1000_reset_mac(dev);
1076         au1000_init(dev);
1077         dev->trans_start = jiffies; /* prevent tx timeout */
1078         netif_wake_queue(dev);
1079 }
1080 
1081 static void au1000_multicast_list(struct net_device *dev)
1082 {
1083         struct au1000_private *aup = netdev_priv(dev);
1084         u32 reg;
1085 
1086         netif_dbg(aup, drv, dev, "%s: flags=%x\n", __func__, dev->flags);
1087         reg = readl(&aup->mac->control);
1088         if (dev->flags & IFF_PROMISC) {                 /* Set promiscuous. */
1089                 reg |= MAC_PROMISCUOUS;
1090         } else if ((dev->flags & IFF_ALLMULTI)  ||
1091                            netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) {
1092                 reg |= MAC_PASS_ALL_MULTI;
1093                 reg &= ~MAC_PROMISCUOUS;
1094                 netdev_info(dev, "Pass all multicast\n");
1095         } else {
1096                 struct netdev_hw_addr *ha;
1097                 u32 mc_filter[2];       /* Multicast hash filter */
1098 
1099                 mc_filter[1] = mc_filter[0] = 0;
1100                 netdev_for_each_mc_addr(ha, dev)
1101                         set_bit(ether_crc(ETH_ALEN, ha->addr)>>26,
1102                                         (long *)mc_filter);
1103                 writel(mc_filter[1], &aup->mac->multi_hash_high);
1104                 writel(mc_filter[0], &aup->mac->multi_hash_low);
1105                 reg &= ~MAC_PROMISCUOUS;
1106                 reg |= MAC_HASH_MODE;
1107         }
1108         writel(reg, &aup->mac->control);
1109 }
1110 
1111 static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1112 {
1113         struct au1000_private *aup = netdev_priv(dev);
1114 
1115         if (!netif_running(dev))
1116                 return -EINVAL;
1117 
1118         if (!aup->phy_dev)
1119                 return -EINVAL; /* PHY not controllable */
1120 
1121         return phy_mii_ioctl(aup->phy_dev, rq, cmd);
1122 }
1123 
1124 static const struct net_device_ops au1000_netdev_ops = {
1125         .ndo_open               = au1000_open,
1126         .ndo_stop               = au1000_close,
1127         .ndo_start_xmit         = au1000_tx,
1128         .ndo_set_rx_mode        = au1000_multicast_list,
1129         .ndo_do_ioctl           = au1000_ioctl,
1130         .ndo_tx_timeout         = au1000_tx_timeout,
1131         .ndo_set_mac_address    = eth_mac_addr,
1132         .ndo_validate_addr      = eth_validate_addr,
1133         .ndo_change_mtu         = eth_change_mtu,
1134 };
1135 
1136 static int au1000_probe(struct platform_device *pdev)
1137 {
1138         struct au1000_private *aup = NULL;
1139         struct au1000_eth_platform_data *pd;
1140         struct net_device *dev = NULL;
1141         struct db_dest *pDB, *pDBfree;
1142         int irq, i, err = 0;
1143         struct resource *base, *macen, *macdma;
1144 
1145         base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1146         if (!base) {
1147                 dev_err(&pdev->dev, "failed to retrieve base register\n");
1148                 err = -ENODEV;
1149                 goto out;
1150         }
1151 
1152         macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1153         if (!macen) {
1154                 dev_err(&pdev->dev, "failed to retrieve MAC Enable register\n");
1155                 err = -ENODEV;
1156                 goto out;
1157         }
1158 
1159         irq = platform_get_irq(pdev, 0);
1160         if (irq < 0) {
1161                 dev_err(&pdev->dev, "failed to retrieve IRQ\n");
1162                 err = -ENODEV;
1163                 goto out;
1164         }
1165 
1166         macdma = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1167         if (!macdma) {
1168                 dev_err(&pdev->dev, "failed to retrieve MACDMA registers\n");
1169                 err = -ENODEV;
1170                 goto out;
1171         }
1172 
1173         if (!request_mem_region(base->start, resource_size(base),
1174                                                         pdev->name)) {
1175                 dev_err(&pdev->dev, "failed to request memory region for base registers\n");
1176                 err = -ENXIO;
1177                 goto out;
1178         }
1179 
1180         if (!request_mem_region(macen->start, resource_size(macen),
1181                                                         pdev->name)) {
1182                 dev_err(&pdev->dev, "failed to request memory region for MAC enable register\n");
1183                 err = -ENXIO;
1184                 goto err_request;
1185         }
1186 
1187         if (!request_mem_region(macdma->start, resource_size(macdma),
1188                                                         pdev->name)) {
1189                 dev_err(&pdev->dev, "failed to request MACDMA memory region\n");
1190                 err = -ENXIO;
1191                 goto err_macdma;
1192         }
1193 
1194         dev = alloc_etherdev(sizeof(struct au1000_private));
1195         if (!dev) {
1196                 err = -ENOMEM;
1197                 goto err_alloc;
1198         }
1199 
1200         SET_NETDEV_DEV(dev, &pdev->dev);
1201         platform_set_drvdata(pdev, dev);
1202         aup = netdev_priv(dev);
1203 
1204         spin_lock_init(&aup->lock);
1205         aup->msg_enable = (au1000_debug < 4 ?
1206                                 AU1000_DEF_MSG_ENABLE : au1000_debug);
1207 
1208         /* Allocate the data buffers
1209          * Snooping works fine with eth on all au1xxx
1210          */
1211         aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
1212                                                 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1213                                                 &aup->dma_addr, 0);
1214         if (!aup->vaddr) {
1215                 dev_err(&pdev->dev, "failed to allocate data buffers\n");
1216                 err = -ENOMEM;
1217                 goto err_vaddr;
1218         }
1219 
1220         /* aup->mac is the base address of the MAC's registers */
1221         aup->mac = (struct mac_reg *)
1222                         ioremap_nocache(base->start, resource_size(base));
1223         if (!aup->mac) {
1224                 dev_err(&pdev->dev, "failed to ioremap MAC registers\n");
1225                 err = -ENXIO;
1226                 goto err_remap1;
1227         }
1228 
1229         /* Setup some variables for quick register address access */
1230         aup->enable = (u32 *)ioremap_nocache(macen->start,
1231                                                 resource_size(macen));
1232         if (!aup->enable) {
1233                 dev_err(&pdev->dev, "failed to ioremap MAC enable register\n");
1234                 err = -ENXIO;
1235                 goto err_remap2;
1236         }
1237         aup->mac_id = pdev->id;
1238 
1239         aup->macdma = ioremap_nocache(macdma->start, resource_size(macdma));
1240         if (!aup->macdma) {
1241                 dev_err(&pdev->dev, "failed to ioremap MACDMA registers\n");
1242                 err = -ENXIO;
1243                 goto err_remap3;
1244         }
1245 
1246         au1000_setup_hw_rings(aup, aup->macdma);
1247 
1248         writel(0, aup->enable);
1249         aup->mac_enabled = 0;
1250 
1251         pd = dev_get_platdata(&pdev->dev);
1252         if (!pd) {
1253                 dev_info(&pdev->dev, "no platform_data passed,"
1254                                         " PHY search on MAC0\n");
1255                 aup->phy1_search_mac0 = 1;
1256         } else {
1257                 if (is_valid_ether_addr(pd->mac)) {
1258                         memcpy(dev->dev_addr, pd->mac, ETH_ALEN);
1259                 } else {
1260                         /* Set a random MAC since no valid provided by platform_data. */
1261                         eth_hw_addr_random(dev);
1262                 }
1263 
1264                 aup->phy_static_config = pd->phy_static_config;
1265                 aup->phy_search_highest_addr = pd->phy_search_highest_addr;
1266                 aup->phy1_search_mac0 = pd->phy1_search_mac0;
1267                 aup->phy_addr = pd->phy_addr;
1268                 aup->phy_busid = pd->phy_busid;
1269                 aup->phy_irq = pd->phy_irq;
1270         }
1271 
1272         if (aup->phy_busid && aup->phy_busid > 0) {
1273                 dev_err(&pdev->dev, "MAC0-associated PHY attached 2nd MACs MII bus not supported yet\n");
1274                 err = -ENODEV;
1275                 goto err_mdiobus_alloc;
1276         }
1277 
1278         aup->mii_bus = mdiobus_alloc();
1279         if (aup->mii_bus == NULL) {
1280                 dev_err(&pdev->dev, "failed to allocate mdiobus structure\n");
1281                 err = -ENOMEM;
1282                 goto err_mdiobus_alloc;
1283         }
1284 
1285         aup->mii_bus->priv = dev;
1286         aup->mii_bus->read = au1000_mdiobus_read;
1287         aup->mii_bus->write = au1000_mdiobus_write;
1288         aup->mii_bus->reset = au1000_mdiobus_reset;
1289         aup->mii_bus->name = "au1000_eth_mii";
1290         snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1291                 pdev->name, aup->mac_id);
1292 
1293         /* if known, set corresponding PHY IRQs */
1294         if (aup->phy_static_config)
1295                 if (aup->phy_irq && aup->phy_busid == aup->mac_id)
1296                         aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq;
1297 
1298         err = mdiobus_register(aup->mii_bus);
1299         if (err) {
1300                 dev_err(&pdev->dev, "failed to register MDIO bus\n");
1301                 goto err_mdiobus_reg;
1302         }
1303 
1304         err = au1000_mii_probe(dev);
1305         if (err != 0)
1306                 goto err_out;
1307 
1308         pDBfree = NULL;
1309         /* setup the data buffer descriptors and attach a buffer to each one */
1310         pDB = aup->db;
1311         for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
1312                 pDB->pnext = pDBfree;
1313                 pDBfree = pDB;
1314                 pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
1315                 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
1316                 pDB++;
1317         }
1318         aup->pDBfree = pDBfree;
1319 
1320         err = -ENODEV;
1321         for (i = 0; i < NUM_RX_DMA; i++) {
1322                 pDB = au1000_GetFreeDB(aup);
1323                 if (!pDB)
1324                         goto err_out;
1325 
1326                 aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1327                 aup->rx_db_inuse[i] = pDB;
1328         }
1329 
1330         err = -ENODEV;
1331         for (i = 0; i < NUM_TX_DMA; i++) {
1332                 pDB = au1000_GetFreeDB(aup);
1333                 if (!pDB)
1334                         goto err_out;
1335 
1336                 aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1337                 aup->tx_dma_ring[i]->len = 0;
1338                 aup->tx_db_inuse[i] = pDB;
1339         }
1340 
1341         dev->base_addr = base->start;
1342         dev->irq = irq;
1343         dev->netdev_ops = &au1000_netdev_ops;
1344         dev->ethtool_ops = &au1000_ethtool_ops;
1345         dev->watchdog_timeo = ETH_TX_TIMEOUT;
1346 
1347         /*
1348          * The boot code uses the ethernet controller, so reset it to start
1349          * fresh.  au1000_init() expects that the device is in reset state.
1350          */
1351         au1000_reset_mac(dev);
1352 
1353         err = register_netdev(dev);
1354         if (err) {
1355                 netdev_err(dev, "Cannot register net device, aborting.\n");
1356                 goto err_out;
1357         }
1358 
1359         netdev_info(dev, "Au1xx0 Ethernet found at 0x%lx, irq %d\n",
1360                         (unsigned long)base->start, irq);
1361 
1362         pr_info_once("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR);
1363 
1364         return 0;
1365 
1366 err_out:
1367         if (aup->mii_bus != NULL)
1368                 mdiobus_unregister(aup->mii_bus);
1369 
1370         /* here we should have a valid dev plus aup-> register addresses
1371          * so we can reset the mac properly.
1372          */
1373         au1000_reset_mac(dev);
1374 
1375         for (i = 0; i < NUM_RX_DMA; i++) {
1376                 if (aup->rx_db_inuse[i])
1377                         au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
1378         }
1379         for (i = 0; i < NUM_TX_DMA; i++) {
1380                 if (aup->tx_db_inuse[i])
1381                         au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
1382         }
1383 err_mdiobus_reg:
1384         mdiobus_free(aup->mii_bus);
1385 err_mdiobus_alloc:
1386         iounmap(aup->macdma);
1387 err_remap3:
1388         iounmap(aup->enable);
1389 err_remap2:
1390         iounmap(aup->mac);
1391 err_remap1:
1392         dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
1393                              (void *)aup->vaddr, aup->dma_addr);
1394 err_vaddr:
1395         free_netdev(dev);
1396 err_alloc:
1397         release_mem_region(macdma->start, resource_size(macdma));
1398 err_macdma:
1399         release_mem_region(macen->start, resource_size(macen));
1400 err_request:
1401         release_mem_region(base->start, resource_size(base));
1402 out:
1403         return err;
1404 }
1405 
1406 static int au1000_remove(struct platform_device *pdev)
1407 {
1408         struct net_device *dev = platform_get_drvdata(pdev);
1409         struct au1000_private *aup = netdev_priv(dev);
1410         int i;
1411         struct resource *base, *macen;
1412 
1413         unregister_netdev(dev);
1414         mdiobus_unregister(aup->mii_bus);
1415         mdiobus_free(aup->mii_bus);
1416 
1417         for (i = 0; i < NUM_RX_DMA; i++)
1418                 if (aup->rx_db_inuse[i])
1419                         au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
1420 
1421         for (i = 0; i < NUM_TX_DMA; i++)
1422                 if (aup->tx_db_inuse[i])
1423                         au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
1424 
1425         dma_free_noncoherent(NULL, MAX_BUF_SIZE *
1426                         (NUM_TX_BUFFS + NUM_RX_BUFFS),
1427                         (void *)aup->vaddr, aup->dma_addr);
1428 
1429         iounmap(aup->macdma);
1430         iounmap(aup->mac);
1431         iounmap(aup->enable);
1432 
1433         base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1434         release_mem_region(base->start, resource_size(base));
1435 
1436         base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1437         release_mem_region(base->start, resource_size(base));
1438 
1439         macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1440         release_mem_region(macen->start, resource_size(macen));
1441 
1442         free_netdev(dev);
1443 
1444         return 0;
1445 }
1446 
1447 static struct platform_driver au1000_eth_driver = {
1448         .probe  = au1000_probe,
1449         .remove = au1000_remove,
1450         .driver = {
1451                 .name   = "au1000-eth",
1452         },
1453 };
1454 
1455 module_platform_driver(au1000_eth_driver);
1456 
1457 MODULE_ALIAS("platform:au1000-eth");
1458 

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