Version:  2.6.34 2.6.35 2.6.36 2.6.37 2.6.38 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14

Linux/drivers/net/ethernet/adi/bfin_mac.c

  1 /*
  2  * Blackfin On-Chip MAC Driver
  3  *
  4  * Copyright 2004-2010 Analog Devices Inc.
  5  *
  6  * Enter bugs at http://blackfin.uclinux.org/
  7  *
  8  * Licensed under the GPL-2 or later.
  9  */
 10 
 11 #define DRV_VERSION     "1.1"
 12 #define DRV_DESC        "Blackfin on-chip Ethernet MAC driver"
 13 
 14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 15 
 16 #include <linux/init.h>
 17 #include <linux/module.h>
 18 #include <linux/kernel.h>
 19 #include <linux/sched.h>
 20 #include <linux/slab.h>
 21 #include <linux/delay.h>
 22 #include <linux/timer.h>
 23 #include <linux/errno.h>
 24 #include <linux/irq.h>
 25 #include <linux/io.h>
 26 #include <linux/ioport.h>
 27 #include <linux/crc32.h>
 28 #include <linux/device.h>
 29 #include <linux/spinlock.h>
 30 #include <linux/mii.h>
 31 #include <linux/netdevice.h>
 32 #include <linux/etherdevice.h>
 33 #include <linux/ethtool.h>
 34 #include <linux/skbuff.h>
 35 #include <linux/platform_device.h>
 36 
 37 #include <asm/dma.h>
 38 #include <linux/dma-mapping.h>
 39 
 40 #include <asm/div64.h>
 41 #include <asm/dpmc.h>
 42 #include <asm/blackfin.h>
 43 #include <asm/cacheflush.h>
 44 #include <asm/portmux.h>
 45 #include <mach/pll.h>
 46 
 47 #include "bfin_mac.h"
 48 
 49 MODULE_AUTHOR("Bryan Wu, Luke Yang");
 50 MODULE_LICENSE("GPL");
 51 MODULE_DESCRIPTION(DRV_DESC);
 52 MODULE_ALIAS("platform:bfin_mac");
 53 
 54 #if defined(CONFIG_BFIN_MAC_USE_L1)
 55 # define bfin_mac_alloc(dma_handle, size, num)  l1_data_sram_zalloc(size*num)
 56 # define bfin_mac_free(dma_handle, ptr, num)    l1_data_sram_free(ptr)
 57 #else
 58 # define bfin_mac_alloc(dma_handle, size, num) \
 59         dma_alloc_coherent(NULL, size*num, dma_handle, GFP_KERNEL)
 60 # define bfin_mac_free(dma_handle, ptr, num) \
 61         dma_free_coherent(NULL, sizeof(*ptr)*num, ptr, dma_handle)
 62 #endif
 63 
 64 #define PKT_BUF_SZ 1580
 65 
 66 #define MAX_TIMEOUT_CNT 500
 67 
 68 /* pointers to maintain transmit list */
 69 static struct net_dma_desc_tx *tx_list_head;
 70 static struct net_dma_desc_tx *tx_list_tail;
 71 static struct net_dma_desc_rx *rx_list_head;
 72 static struct net_dma_desc_rx *rx_list_tail;
 73 static struct net_dma_desc_rx *current_rx_ptr;
 74 static struct net_dma_desc_tx *current_tx_ptr;
 75 static struct net_dma_desc_tx *tx_desc;
 76 static struct net_dma_desc_rx *rx_desc;
 77 
 78 static void desc_list_free(void)
 79 {
 80         struct net_dma_desc_rx *r;
 81         struct net_dma_desc_tx *t;
 82         int i;
 83 #if !defined(CONFIG_BFIN_MAC_USE_L1)
 84         dma_addr_t dma_handle = 0;
 85 #endif
 86 
 87         if (tx_desc) {
 88                 t = tx_list_head;
 89                 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
 90                         if (t) {
 91                                 if (t->skb) {
 92                                         dev_kfree_skb(t->skb);
 93                                         t->skb = NULL;
 94                                 }
 95                                 t = t->next;
 96                         }
 97                 }
 98                 bfin_mac_free(dma_handle, tx_desc, CONFIG_BFIN_TX_DESC_NUM);
 99         }
100 
101         if (rx_desc) {
102                 r = rx_list_head;
103                 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
104                         if (r) {
105                                 if (r->skb) {
106                                         dev_kfree_skb(r->skb);
107                                         r->skb = NULL;
108                                 }
109                                 r = r->next;
110                         }
111                 }
112                 bfin_mac_free(dma_handle, rx_desc, CONFIG_BFIN_RX_DESC_NUM);
113         }
114 }
115 
116 static int desc_list_init(struct net_device *dev)
117 {
118         int i;
119         struct sk_buff *new_skb;
120 #if !defined(CONFIG_BFIN_MAC_USE_L1)
121         /*
122          * This dma_handle is useless in Blackfin dma_alloc_coherent().
123          * The real dma handler is the return value of dma_alloc_coherent().
124          */
125         dma_addr_t dma_handle;
126 #endif
127 
128         tx_desc = bfin_mac_alloc(&dma_handle,
129                                 sizeof(struct net_dma_desc_tx),
130                                 CONFIG_BFIN_TX_DESC_NUM);
131         if (tx_desc == NULL)
132                 goto init_error;
133 
134         rx_desc = bfin_mac_alloc(&dma_handle,
135                                 sizeof(struct net_dma_desc_rx),
136                                 CONFIG_BFIN_RX_DESC_NUM);
137         if (rx_desc == NULL)
138                 goto init_error;
139 
140         /* init tx_list */
141         tx_list_head = tx_list_tail = tx_desc;
142 
143         for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
144                 struct net_dma_desc_tx *t = tx_desc + i;
145                 struct dma_descriptor *a = &(t->desc_a);
146                 struct dma_descriptor *b = &(t->desc_b);
147 
148                 /*
149                  * disable DMA
150                  * read from memory WNR = 0
151                  * wordsize is 32 bits
152                  * 6 half words is desc size
153                  * large desc flow
154                  */
155                 a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
156                 a->start_addr = (unsigned long)t->packet;
157                 a->x_count = 0;
158                 a->next_dma_desc = b;
159 
160                 /*
161                  * enabled DMA
162                  * write to memory WNR = 1
163                  * wordsize is 32 bits
164                  * disable interrupt
165                  * 6 half words is desc size
166                  * large desc flow
167                  */
168                 b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
169                 b->start_addr = (unsigned long)(&(t->status));
170                 b->x_count = 0;
171 
172                 t->skb = NULL;
173                 tx_list_tail->desc_b.next_dma_desc = a;
174                 tx_list_tail->next = t;
175                 tx_list_tail = t;
176         }
177         tx_list_tail->next = tx_list_head;      /* tx_list is a circle */
178         tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a);
179         current_tx_ptr = tx_list_head;
180 
181         /* init rx_list */
182         rx_list_head = rx_list_tail = rx_desc;
183 
184         for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
185                 struct net_dma_desc_rx *r = rx_desc + i;
186                 struct dma_descriptor *a = &(r->desc_a);
187                 struct dma_descriptor *b = &(r->desc_b);
188 
189                 /* allocate a new skb for next time receive */
190                 new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN);
191                 if (!new_skb)
192                         goto init_error;
193 
194                 skb_reserve(new_skb, NET_IP_ALIGN);
195                 /* Invidate the data cache of skb->data range when it is write back
196                  * cache. It will prevent overwritting the new data from DMA
197                  */
198                 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
199                                          (unsigned long)new_skb->end);
200                 r->skb = new_skb;
201 
202                 /*
203                  * enabled DMA
204                  * write to memory WNR = 1
205                  * wordsize is 32 bits
206                  * disable interrupt
207                  * 6 half words is desc size
208                  * large desc flow
209                  */
210                 a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
211                 /* since RXDWA is enabled */
212                 a->start_addr = (unsigned long)new_skb->data - 2;
213                 a->x_count = 0;
214                 a->next_dma_desc = b;
215 
216                 /*
217                  * enabled DMA
218                  * write to memory WNR = 1
219                  * wordsize is 32 bits
220                  * enable interrupt
221                  * 6 half words is desc size
222                  * large desc flow
223                  */
224                 b->config = DMAEN | WNR | WDSIZE_32 | DI_EN |
225                                 NDSIZE_6 | DMAFLOW_LARGE;
226                 b->start_addr = (unsigned long)(&(r->status));
227                 b->x_count = 0;
228 
229                 rx_list_tail->desc_b.next_dma_desc = a;
230                 rx_list_tail->next = r;
231                 rx_list_tail = r;
232         }
233         rx_list_tail->next = rx_list_head;      /* rx_list is a circle */
234         rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a);
235         current_rx_ptr = rx_list_head;
236 
237         return 0;
238 
239 init_error:
240         desc_list_free();
241         pr_err("kmalloc failed\n");
242         return -ENOMEM;
243 }
244 
245 
246 /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
247 
248 /*
249  * MII operations
250  */
251 /* Wait until the previous MDC/MDIO transaction has completed */
252 static int bfin_mdio_poll(void)
253 {
254         int timeout_cnt = MAX_TIMEOUT_CNT;
255 
256         /* poll the STABUSY bit */
257         while ((bfin_read_EMAC_STAADD()) & STABUSY) {
258                 udelay(1);
259                 if (timeout_cnt-- < 0) {
260                         pr_err("wait MDC/MDIO transaction to complete timeout\n");
261                         return -ETIMEDOUT;
262                 }
263         }
264 
265         return 0;
266 }
267 
268 /* Read an off-chip register in a PHY through the MDC/MDIO port */
269 static int bfin_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
270 {
271         int ret;
272 
273         ret = bfin_mdio_poll();
274         if (ret)
275                 return ret;
276 
277         /* read mode */
278         bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
279                                 SET_REGAD((u16) regnum) |
280                                 STABUSY);
281 
282         ret = bfin_mdio_poll();
283         if (ret)
284                 return ret;
285 
286         return (int) bfin_read_EMAC_STADAT();
287 }
288 
289 /* Write an off-chip register in a PHY through the MDC/MDIO port */
290 static int bfin_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
291                               u16 value)
292 {
293         int ret;
294 
295         ret = bfin_mdio_poll();
296         if (ret)
297                 return ret;
298 
299         bfin_write_EMAC_STADAT((u32) value);
300 
301         /* write mode */
302         bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
303                                 SET_REGAD((u16) regnum) |
304                                 STAOP |
305                                 STABUSY);
306 
307         return bfin_mdio_poll();
308 }
309 
310 static int bfin_mdiobus_reset(struct mii_bus *bus)
311 {
312         return 0;
313 }
314 
315 static void bfin_mac_adjust_link(struct net_device *dev)
316 {
317         struct bfin_mac_local *lp = netdev_priv(dev);
318         struct phy_device *phydev = lp->phydev;
319         unsigned long flags;
320         int new_state = 0;
321 
322         spin_lock_irqsave(&lp->lock, flags);
323         if (phydev->link) {
324                 /* Now we make sure that we can be in full duplex mode.
325                  * If not, we operate in half-duplex mode. */
326                 if (phydev->duplex != lp->old_duplex) {
327                         u32 opmode = bfin_read_EMAC_OPMODE();
328                         new_state = 1;
329 
330                         if (phydev->duplex)
331                                 opmode |= FDMODE;
332                         else
333                                 opmode &= ~(FDMODE);
334 
335                         bfin_write_EMAC_OPMODE(opmode);
336                         lp->old_duplex = phydev->duplex;
337                 }
338 
339                 if (phydev->speed != lp->old_speed) {
340                         if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
341                                 u32 opmode = bfin_read_EMAC_OPMODE();
342                                 switch (phydev->speed) {
343                                 case 10:
344                                         opmode |= RMII_10;
345                                         break;
346                                 case 100:
347                                         opmode &= ~RMII_10;
348                                         break;
349                                 default:
350                                         netdev_warn(dev,
351                                                 "Ack! Speed (%d) is not 10/100!\n",
352                                                 phydev->speed);
353                                         break;
354                                 }
355                                 bfin_write_EMAC_OPMODE(opmode);
356                         }
357 
358                         new_state = 1;
359                         lp->old_speed = phydev->speed;
360                 }
361 
362                 if (!lp->old_link) {
363                         new_state = 1;
364                         lp->old_link = 1;
365                 }
366         } else if (lp->old_link) {
367                 new_state = 1;
368                 lp->old_link = 0;
369                 lp->old_speed = 0;
370                 lp->old_duplex = -1;
371         }
372 
373         if (new_state) {
374                 u32 opmode = bfin_read_EMAC_OPMODE();
375                 phy_print_status(phydev);
376                 pr_debug("EMAC_OPMODE = 0x%08x\n", opmode);
377         }
378 
379         spin_unlock_irqrestore(&lp->lock, flags);
380 }
381 
382 /* MDC  = 2.5 MHz */
383 #define MDC_CLK 2500000
384 
385 static int mii_probe(struct net_device *dev, int phy_mode)
386 {
387         struct bfin_mac_local *lp = netdev_priv(dev);
388         struct phy_device *phydev = NULL;
389         unsigned short sysctl;
390         int i;
391         u32 sclk, mdc_div;
392 
393         /* Enable PHY output early */
394         if (!(bfin_read_VR_CTL() & CLKBUFOE))
395                 bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
396 
397         sclk = get_sclk();
398         mdc_div = ((sclk / MDC_CLK) / 2) - 1;
399 
400         sysctl = bfin_read_EMAC_SYSCTL();
401         sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div);
402         bfin_write_EMAC_SYSCTL(sysctl);
403 
404         /* search for connected PHY device */
405         for (i = 0; i < PHY_MAX_ADDR; ++i) {
406                 struct phy_device *const tmp_phydev = lp->mii_bus->phy_map[i];
407 
408                 if (!tmp_phydev)
409                         continue; /* no PHY here... */
410 
411                 phydev = tmp_phydev;
412                 break; /* found it */
413         }
414 
415         /* now we are supposed to have a proper phydev, to attach to... */
416         if (!phydev) {
417                 netdev_err(dev, "no phy device found\n");
418                 return -ENODEV;
419         }
420 
421         if (phy_mode != PHY_INTERFACE_MODE_RMII &&
422                 phy_mode != PHY_INTERFACE_MODE_MII) {
423                 netdev_err(dev, "invalid phy interface mode\n");
424                 return -EINVAL;
425         }
426 
427         phydev = phy_connect(dev, dev_name(&phydev->dev),
428                              &bfin_mac_adjust_link, phy_mode);
429 
430         if (IS_ERR(phydev)) {
431                 netdev_err(dev, "could not attach PHY\n");
432                 return PTR_ERR(phydev);
433         }
434 
435         /* mask with MAC supported features */
436         phydev->supported &= (SUPPORTED_10baseT_Half
437                               | SUPPORTED_10baseT_Full
438                               | SUPPORTED_100baseT_Half
439                               | SUPPORTED_100baseT_Full
440                               | SUPPORTED_Autoneg
441                               | SUPPORTED_Pause | SUPPORTED_Asym_Pause
442                               | SUPPORTED_MII
443                               | SUPPORTED_TP);
444 
445         phydev->advertising = phydev->supported;
446 
447         lp->old_link = 0;
448         lp->old_speed = 0;
449         lp->old_duplex = -1;
450         lp->phydev = phydev;
451 
452         pr_info("attached PHY driver [%s] "
453                 "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)@sclk=%dMHz)\n",
454                 phydev->drv->name, dev_name(&phydev->dev), phydev->irq,
455                 MDC_CLK, mdc_div, sclk/1000000);
456 
457         return 0;
458 }
459 
460 /*
461  * Ethtool support
462  */
463 
464 /*
465  * interrupt routine for magic packet wakeup
466  */
467 static irqreturn_t bfin_mac_wake_interrupt(int irq, void *dev_id)
468 {
469         return IRQ_HANDLED;
470 }
471 
472 static int
473 bfin_mac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
474 {
475         struct bfin_mac_local *lp = netdev_priv(dev);
476 
477         if (lp->phydev)
478                 return phy_ethtool_gset(lp->phydev, cmd);
479 
480         return -EINVAL;
481 }
482 
483 static int
484 bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
485 {
486         struct bfin_mac_local *lp = netdev_priv(dev);
487 
488         if (!capable(CAP_NET_ADMIN))
489                 return -EPERM;
490 
491         if (lp->phydev)
492                 return phy_ethtool_sset(lp->phydev, cmd);
493 
494         return -EINVAL;
495 }
496 
497 static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev,
498                                         struct ethtool_drvinfo *info)
499 {
500         strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
501         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
502         strlcpy(info->fw_version, "N/A", sizeof(info->fw_version));
503         strlcpy(info->bus_info, dev_name(&dev->dev), sizeof(info->bus_info));
504 }
505 
506 static void bfin_mac_ethtool_getwol(struct net_device *dev,
507         struct ethtool_wolinfo *wolinfo)
508 {
509         struct bfin_mac_local *lp = netdev_priv(dev);
510 
511         wolinfo->supported = WAKE_MAGIC;
512         wolinfo->wolopts = lp->wol;
513 }
514 
515 static int bfin_mac_ethtool_setwol(struct net_device *dev,
516         struct ethtool_wolinfo *wolinfo)
517 {
518         struct bfin_mac_local *lp = netdev_priv(dev);
519         int rc;
520 
521         if (wolinfo->wolopts & (WAKE_MAGICSECURE |
522                                 WAKE_UCAST |
523                                 WAKE_MCAST |
524                                 WAKE_BCAST |
525                                 WAKE_ARP))
526                 return -EOPNOTSUPP;
527 
528         lp->wol = wolinfo->wolopts;
529 
530         if (lp->wol && !lp->irq_wake_requested) {
531                 /* register wake irq handler */
532                 rc = request_irq(IRQ_MAC_WAKEDET, bfin_mac_wake_interrupt,
533                                  0, "EMAC_WAKE", dev);
534                 if (rc)
535                         return rc;
536                 lp->irq_wake_requested = true;
537         }
538 
539         if (!lp->wol && lp->irq_wake_requested) {
540                 free_irq(IRQ_MAC_WAKEDET, dev);
541                 lp->irq_wake_requested = false;
542         }
543 
544         /* Make sure the PHY driver doesn't suspend */
545         device_init_wakeup(&dev->dev, lp->wol);
546 
547         return 0;
548 }
549 
550 #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
551 static int bfin_mac_ethtool_get_ts_info(struct net_device *dev,
552         struct ethtool_ts_info *info)
553 {
554         struct bfin_mac_local *lp = netdev_priv(dev);
555 
556         info->so_timestamping =
557                 SOF_TIMESTAMPING_TX_HARDWARE |
558                 SOF_TIMESTAMPING_RX_HARDWARE |
559                 SOF_TIMESTAMPING_RAW_HARDWARE;
560         info->phc_index = lp->phc_index;
561         info->tx_types =
562                 (1 << HWTSTAMP_TX_OFF) |
563                 (1 << HWTSTAMP_TX_ON);
564         info->rx_filters =
565                 (1 << HWTSTAMP_FILTER_NONE) |
566                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
567                 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
568                 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
569         return 0;
570 }
571 #endif
572 
573 static const struct ethtool_ops bfin_mac_ethtool_ops = {
574         .get_settings = bfin_mac_ethtool_getsettings,
575         .set_settings = bfin_mac_ethtool_setsettings,
576         .get_link = ethtool_op_get_link,
577         .get_drvinfo = bfin_mac_ethtool_getdrvinfo,
578         .get_wol = bfin_mac_ethtool_getwol,
579         .set_wol = bfin_mac_ethtool_setwol,
580 #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
581         .get_ts_info = bfin_mac_ethtool_get_ts_info,
582 #endif
583 };
584 
585 /**************************************************************************/
586 static void setup_system_regs(struct net_device *dev)
587 {
588         struct bfin_mac_local *lp = netdev_priv(dev);
589         int i;
590         unsigned short sysctl;
591 
592         /*
593          * Odd word alignment for Receive Frame DMA word
594          * Configure checksum support and rcve frame word alignment
595          */
596         sysctl = bfin_read_EMAC_SYSCTL();
597         /*
598          * check if interrupt is requested for any PHY,
599          * enable PHY interrupt only if needed
600          */
601         for (i = 0; i < PHY_MAX_ADDR; ++i)
602                 if (lp->mii_bus->irq[i] != PHY_POLL)
603                         break;
604         if (i < PHY_MAX_ADDR)
605                 sysctl |= PHYIE;
606         sysctl |= RXDWA;
607 #if defined(BFIN_MAC_CSUM_OFFLOAD)
608         sysctl |= RXCKS;
609 #else
610         sysctl &= ~RXCKS;
611 #endif
612         bfin_write_EMAC_SYSCTL(sysctl);
613 
614         bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
615 
616         /* Set vlan regs to let 1522 bytes long packets pass through */
617         bfin_write_EMAC_VLAN1(lp->vlan1_mask);
618         bfin_write_EMAC_VLAN2(lp->vlan2_mask);
619 
620         /* Initialize the TX DMA channel registers */
621         bfin_write_DMA2_X_COUNT(0);
622         bfin_write_DMA2_X_MODIFY(4);
623         bfin_write_DMA2_Y_COUNT(0);
624         bfin_write_DMA2_Y_MODIFY(0);
625 
626         /* Initialize the RX DMA channel registers */
627         bfin_write_DMA1_X_COUNT(0);
628         bfin_write_DMA1_X_MODIFY(4);
629         bfin_write_DMA1_Y_COUNT(0);
630         bfin_write_DMA1_Y_MODIFY(0);
631 }
632 
633 static void setup_mac_addr(u8 *mac_addr)
634 {
635         u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]);
636         u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]);
637 
638         /* this depends on a little-endian machine */
639         bfin_write_EMAC_ADDRLO(addr_low);
640         bfin_write_EMAC_ADDRHI(addr_hi);
641 }
642 
643 static int bfin_mac_set_mac_address(struct net_device *dev, void *p)
644 {
645         struct sockaddr *addr = p;
646         if (netif_running(dev))
647                 return -EBUSY;
648         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
649         setup_mac_addr(dev->dev_addr);
650         return 0;
651 }
652 
653 #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
654 #define bfin_mac_hwtstamp_is_none(cfg) ((cfg) == HWTSTAMP_FILTER_NONE)
655 
656 static u32 bfin_select_phc_clock(u32 input_clk, unsigned int *shift_result)
657 {
658         u32 ipn = 1000000000UL / input_clk;
659         u32 ppn = 1;
660         unsigned int shift = 0;
661 
662         while (ppn <= ipn) {
663                 ppn <<= 1;
664                 shift++;
665         }
666         *shift_result = shift;
667         return 1000000000UL / ppn;
668 }
669 
670 static int bfin_mac_hwtstamp_set(struct net_device *netdev,
671                                  struct ifreq *ifr)
672 {
673         struct hwtstamp_config config;
674         struct bfin_mac_local *lp = netdev_priv(netdev);
675         u16 ptpctl;
676         u32 ptpfv1, ptpfv2, ptpfv3, ptpfoff;
677 
678         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
679                 return -EFAULT;
680 
681         pr_debug("%s config flag:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
682                         __func__, config.flags, config.tx_type, config.rx_filter);
683 
684         /* reserved for future extensions */
685         if (config.flags)
686                 return -EINVAL;
687 
688         if ((config.tx_type != HWTSTAMP_TX_OFF) &&
689                         (config.tx_type != HWTSTAMP_TX_ON))
690                 return -ERANGE;
691 
692         ptpctl = bfin_read_EMAC_PTP_CTL();
693 
694         switch (config.rx_filter) {
695         case HWTSTAMP_FILTER_NONE:
696                 /*
697                  * Dont allow any timestamping
698                  */
699                 ptpfv3 = 0xFFFFFFFF;
700                 bfin_write_EMAC_PTP_FV3(ptpfv3);
701                 break;
702         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
703         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
704         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
705                 /*
706                  * Clear the five comparison mask bits (bits[12:8]) in EMAC_PTP_CTL)
707                  * to enable all the field matches.
708                  */
709                 ptpctl &= ~0x1F00;
710                 bfin_write_EMAC_PTP_CTL(ptpctl);
711                 /*
712                  * Keep the default values of the EMAC_PTP_FOFF register.
713                  */
714                 ptpfoff = 0x4A24170C;
715                 bfin_write_EMAC_PTP_FOFF(ptpfoff);
716                 /*
717                  * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
718                  * registers.
719                  */
720                 ptpfv1 = 0x11040800;
721                 bfin_write_EMAC_PTP_FV1(ptpfv1);
722                 ptpfv2 = 0x0140013F;
723                 bfin_write_EMAC_PTP_FV2(ptpfv2);
724                 /*
725                  * The default value (0xFFFC) allows the timestamping of both
726                  * received Sync messages and Delay_Req messages.
727                  */
728                 ptpfv3 = 0xFFFFFFFC;
729                 bfin_write_EMAC_PTP_FV3(ptpfv3);
730 
731                 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
732                 break;
733         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
734         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
735         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
736                 /* Clear all five comparison mask bits (bits[12:8]) in the
737                  * EMAC_PTP_CTL register to enable all the field matches.
738                  */
739                 ptpctl &= ~0x1F00;
740                 bfin_write_EMAC_PTP_CTL(ptpctl);
741                 /*
742                  * Keep the default values of the EMAC_PTP_FOFF register, except set
743                  * the PTPCOF field to 0x2A.
744                  */
745                 ptpfoff = 0x2A24170C;
746                 bfin_write_EMAC_PTP_FOFF(ptpfoff);
747                 /*
748                  * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
749                  * registers.
750                  */
751                 ptpfv1 = 0x11040800;
752                 bfin_write_EMAC_PTP_FV1(ptpfv1);
753                 ptpfv2 = 0x0140013F;
754                 bfin_write_EMAC_PTP_FV2(ptpfv2);
755                 /*
756                  * To allow the timestamping of Pdelay_Req and Pdelay_Resp, set
757                  * the value to 0xFFF0.
758                  */
759                 ptpfv3 = 0xFFFFFFF0;
760                 bfin_write_EMAC_PTP_FV3(ptpfv3);
761 
762                 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
763                 break;
764         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
765         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
766         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
767                 /*
768                  * Clear bits 8 and 12 of the EMAC_PTP_CTL register to enable only the
769                  * EFTM and PTPCM field comparison.
770                  */
771                 ptpctl &= ~0x1100;
772                 bfin_write_EMAC_PTP_CTL(ptpctl);
773                 /*
774                  * Keep the default values of all the fields of the EMAC_PTP_FOFF
775                  * register, except set the PTPCOF field to 0x0E.
776                  */
777                 ptpfoff = 0x0E24170C;
778                 bfin_write_EMAC_PTP_FOFF(ptpfoff);
779                 /*
780                  * Program bits [15:0] of the EMAC_PTP_FV1 register to 0x88F7, which
781                  * corresponds to PTP messages on the MAC layer.
782                  */
783                 ptpfv1 = 0x110488F7;
784                 bfin_write_EMAC_PTP_FV1(ptpfv1);
785                 ptpfv2 = 0x0140013F;
786                 bfin_write_EMAC_PTP_FV2(ptpfv2);
787                 /*
788                  * To allow the timestamping of Pdelay_Req and Pdelay_Resp
789                  * messages, set the value to 0xFFF0.
790                  */
791                 ptpfv3 = 0xFFFFFFF0;
792                 bfin_write_EMAC_PTP_FV3(ptpfv3);
793 
794                 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
795                 break;
796         default:
797                 return -ERANGE;
798         }
799 
800         if (config.tx_type == HWTSTAMP_TX_OFF &&
801             bfin_mac_hwtstamp_is_none(config.rx_filter)) {
802                 ptpctl &= ~PTP_EN;
803                 bfin_write_EMAC_PTP_CTL(ptpctl);
804 
805                 SSYNC();
806         } else {
807                 ptpctl |= PTP_EN;
808                 bfin_write_EMAC_PTP_CTL(ptpctl);
809 
810                 /*
811                  * clear any existing timestamp
812                  */
813                 bfin_read_EMAC_PTP_RXSNAPLO();
814                 bfin_read_EMAC_PTP_RXSNAPHI();
815 
816                 bfin_read_EMAC_PTP_TXSNAPLO();
817                 bfin_read_EMAC_PTP_TXSNAPHI();
818 
819                 SSYNC();
820         }
821 
822         lp->stamp_cfg = config;
823         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
824                 -EFAULT : 0;
825 }
826 
827 static int bfin_mac_hwtstamp_get(struct net_device *netdev,
828                                  struct ifreq *ifr)
829 {
830         struct bfin_mac_local *lp = netdev_priv(netdev);
831 
832         return copy_to_user(ifr->ifr_data, &lp->stamp_cfg,
833                             sizeof(lp->stamp_cfg)) ?
834                 -EFAULT : 0;
835 }
836 
837 static void bfin_tx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
838 {
839         struct bfin_mac_local *lp = netdev_priv(netdev);
840 
841         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
842                 int timeout_cnt = MAX_TIMEOUT_CNT;
843 
844                 /* When doing time stamping, keep the connection to the socket
845                  * a while longer
846                  */
847                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
848 
849                 /*
850                  * The timestamping is done at the EMAC module's MII/RMII interface
851                  * when the module sees the Start of Frame of an event message packet. This
852                  * interface is the closest possible place to the physical Ethernet transmission
853                  * medium, providing the best timing accuracy.
854                  */
855                 while ((!(bfin_read_EMAC_PTP_ISTAT() & TXTL)) && (--timeout_cnt))
856                         udelay(1);
857                 if (timeout_cnt == 0)
858                         netdev_err(netdev, "timestamp the TX packet failed\n");
859                 else {
860                         struct skb_shared_hwtstamps shhwtstamps;
861                         u64 ns;
862                         u64 regval;
863 
864                         regval = bfin_read_EMAC_PTP_TXSNAPLO();
865                         regval |= (u64)bfin_read_EMAC_PTP_TXSNAPHI() << 32;
866                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
867                         ns = regval << lp->shift;
868                         shhwtstamps.hwtstamp = ns_to_ktime(ns);
869                         skb_tstamp_tx(skb, &shhwtstamps);
870                 }
871         }
872 }
873 
874 static void bfin_rx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
875 {
876         struct bfin_mac_local *lp = netdev_priv(netdev);
877         u32 valid;
878         u64 regval, ns;
879         struct skb_shared_hwtstamps *shhwtstamps;
880 
881         if (bfin_mac_hwtstamp_is_none(lp->stamp_cfg.rx_filter))
882                 return;
883 
884         valid = bfin_read_EMAC_PTP_ISTAT() & RXEL;
885         if (!valid)
886                 return;
887 
888         shhwtstamps = skb_hwtstamps(skb);
889 
890         regval = bfin_read_EMAC_PTP_RXSNAPLO();
891         regval |= (u64)bfin_read_EMAC_PTP_RXSNAPHI() << 32;
892         ns = regval << lp->shift;
893         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
894         shhwtstamps->hwtstamp = ns_to_ktime(ns);
895 }
896 
897 static void bfin_mac_hwtstamp_init(struct net_device *netdev)
898 {
899         struct bfin_mac_local *lp = netdev_priv(netdev);
900         u64 addend, ppb;
901         u32 input_clk, phc_clk;
902 
903         /* Initialize hardware timer */
904         input_clk = get_sclk();
905         phc_clk = bfin_select_phc_clock(input_clk, &lp->shift);
906         addend = phc_clk * (1ULL << 32);
907         do_div(addend, input_clk);
908         bfin_write_EMAC_PTP_ADDEND((u32)addend);
909 
910         lp->addend = addend;
911         ppb = 1000000000ULL * input_clk;
912         do_div(ppb, phc_clk);
913         lp->max_ppb = ppb - 1000000000ULL - 1ULL;
914 
915         /* Initialize hwstamp config */
916         lp->stamp_cfg.rx_filter = HWTSTAMP_FILTER_NONE;
917         lp->stamp_cfg.tx_type = HWTSTAMP_TX_OFF;
918 }
919 
920 static u64 bfin_ptp_time_read(struct bfin_mac_local *lp)
921 {
922         u64 ns;
923         u32 lo, hi;
924 
925         lo = bfin_read_EMAC_PTP_TIMELO();
926         hi = bfin_read_EMAC_PTP_TIMEHI();
927 
928         ns = ((u64) hi) << 32;
929         ns |= lo;
930         ns <<= lp->shift;
931 
932         return ns;
933 }
934 
935 static void bfin_ptp_time_write(struct bfin_mac_local *lp, u64 ns)
936 {
937         u32 hi, lo;
938 
939         ns >>= lp->shift;
940         hi = ns >> 32;
941         lo = ns & 0xffffffff;
942 
943         bfin_write_EMAC_PTP_TIMELO(lo);
944         bfin_write_EMAC_PTP_TIMEHI(hi);
945 }
946 
947 /* PTP Hardware Clock operations */
948 
949 static int bfin_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
950 {
951         u64 adj;
952         u32 diff, addend;
953         int neg_adj = 0;
954         struct bfin_mac_local *lp =
955                 container_of(ptp, struct bfin_mac_local, caps);
956 
957         if (ppb < 0) {
958                 neg_adj = 1;
959                 ppb = -ppb;
960         }
961         addend = lp->addend;
962         adj = addend;
963         adj *= ppb;
964         diff = div_u64(adj, 1000000000ULL);
965 
966         addend = neg_adj ? addend - diff : addend + diff;
967 
968         bfin_write_EMAC_PTP_ADDEND(addend);
969 
970         return 0;
971 }
972 
973 static int bfin_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
974 {
975         s64 now;
976         unsigned long flags;
977         struct bfin_mac_local *lp =
978                 container_of(ptp, struct bfin_mac_local, caps);
979 
980         spin_lock_irqsave(&lp->phc_lock, flags);
981 
982         now = bfin_ptp_time_read(lp);
983         now += delta;
984         bfin_ptp_time_write(lp, now);
985 
986         spin_unlock_irqrestore(&lp->phc_lock, flags);
987 
988         return 0;
989 }
990 
991 static int bfin_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
992 {
993         u64 ns;
994         u32 remainder;
995         unsigned long flags;
996         struct bfin_mac_local *lp =
997                 container_of(ptp, struct bfin_mac_local, caps);
998 
999         spin_lock_irqsave(&lp->phc_lock, flags);
1000 
1001         ns = bfin_ptp_time_read(lp);
1002 
1003         spin_unlock_irqrestore(&lp->phc_lock, flags);
1004 
1005         ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
1006         ts->tv_nsec = remainder;
1007         return 0;
1008 }
1009 
1010 static int bfin_ptp_settime(struct ptp_clock_info *ptp,
1011                            const struct timespec *ts)
1012 {
1013         u64 ns;
1014         unsigned long flags;
1015         struct bfin_mac_local *lp =
1016                 container_of(ptp, struct bfin_mac_local, caps);
1017 
1018         ns = ts->tv_sec * 1000000000ULL;
1019         ns += ts->tv_nsec;
1020 
1021         spin_lock_irqsave(&lp->phc_lock, flags);
1022 
1023         bfin_ptp_time_write(lp, ns);
1024 
1025         spin_unlock_irqrestore(&lp->phc_lock, flags);
1026 
1027         return 0;
1028 }
1029 
1030 static int bfin_ptp_enable(struct ptp_clock_info *ptp,
1031                           struct ptp_clock_request *rq, int on)
1032 {
1033         return -EOPNOTSUPP;
1034 }
1035 
1036 static struct ptp_clock_info bfin_ptp_caps = {
1037         .owner          = THIS_MODULE,
1038         .name           = "BF518 clock",
1039         .max_adj        = 0,
1040         .n_alarm        = 0,
1041         .n_ext_ts       = 0,
1042         .n_per_out      = 0,
1043         .pps            = 0,
1044         .adjfreq        = bfin_ptp_adjfreq,
1045         .adjtime        = bfin_ptp_adjtime,
1046         .gettime        = bfin_ptp_gettime,
1047         .settime        = bfin_ptp_settime,
1048         .enable         = bfin_ptp_enable,
1049 };
1050 
1051 static int bfin_phc_init(struct net_device *netdev, struct device *dev)
1052 {
1053         struct bfin_mac_local *lp = netdev_priv(netdev);
1054 
1055         lp->caps = bfin_ptp_caps;
1056         lp->caps.max_adj = lp->max_ppb;
1057         lp->clock = ptp_clock_register(&lp->caps, dev);
1058         if (IS_ERR(lp->clock))
1059                 return PTR_ERR(lp->clock);
1060 
1061         lp->phc_index = ptp_clock_index(lp->clock);
1062         spin_lock_init(&lp->phc_lock);
1063 
1064         return 0;
1065 }
1066 
1067 static void bfin_phc_release(struct bfin_mac_local *lp)
1068 {
1069         ptp_clock_unregister(lp->clock);
1070 }
1071 
1072 #else
1073 # define bfin_mac_hwtstamp_is_none(cfg) 0
1074 # define bfin_mac_hwtstamp_init(dev)
1075 # define bfin_mac_hwtstamp_set(dev, ifr) (-EOPNOTSUPP)
1076 # define bfin_mac_hwtstamp_get(dev, ifr) (-EOPNOTSUPP)
1077 # define bfin_rx_hwtstamp(dev, skb)
1078 # define bfin_tx_hwtstamp(dev, skb)
1079 # define bfin_phc_init(netdev, dev) 0
1080 # define bfin_phc_release(lp)
1081 #endif
1082 
1083 static inline void _tx_reclaim_skb(void)
1084 {
1085         do {
1086                 tx_list_head->desc_a.config &= ~DMAEN;
1087                 tx_list_head->status.status_word = 0;
1088                 if (tx_list_head->skb) {
1089                         dev_kfree_skb(tx_list_head->skb);
1090                         tx_list_head->skb = NULL;
1091                 }
1092                 tx_list_head = tx_list_head->next;
1093 
1094         } while (tx_list_head->status.status_word != 0);
1095 }
1096 
1097 static void tx_reclaim_skb(struct bfin_mac_local *lp)
1098 {
1099         int timeout_cnt = MAX_TIMEOUT_CNT;
1100 
1101         if (tx_list_head->status.status_word != 0)
1102                 _tx_reclaim_skb();
1103 
1104         if (current_tx_ptr->next == tx_list_head) {
1105                 while (tx_list_head->status.status_word == 0) {
1106                         /* slow down polling to avoid too many queue stop. */
1107                         udelay(10);
1108                         /* reclaim skb if DMA is not running. */
1109                         if (!(bfin_read_DMA2_IRQ_STATUS() & DMA_RUN))
1110                                 break;
1111                         if (timeout_cnt-- < 0)
1112                                 break;
1113                 }
1114 
1115                 if (timeout_cnt >= 0)
1116                         _tx_reclaim_skb();
1117                 else
1118                         netif_stop_queue(lp->ndev);
1119         }
1120 
1121         if (current_tx_ptr->next != tx_list_head &&
1122                 netif_queue_stopped(lp->ndev))
1123                 netif_wake_queue(lp->ndev);
1124 
1125         if (tx_list_head != current_tx_ptr) {
1126                 /* shorten the timer interval if tx queue is stopped */
1127                 if (netif_queue_stopped(lp->ndev))
1128                         lp->tx_reclaim_timer.expires =
1129                                 jiffies + (TX_RECLAIM_JIFFIES >> 4);
1130                 else
1131                         lp->tx_reclaim_timer.expires =
1132                                 jiffies + TX_RECLAIM_JIFFIES;
1133 
1134                 mod_timer(&lp->tx_reclaim_timer,
1135                         lp->tx_reclaim_timer.expires);
1136         }
1137 
1138         return;
1139 }
1140 
1141 static void tx_reclaim_skb_timeout(unsigned long lp)
1142 {
1143         tx_reclaim_skb((struct bfin_mac_local *)lp);
1144 }
1145 
1146 static int bfin_mac_hard_start_xmit(struct sk_buff *skb,
1147                                 struct net_device *dev)
1148 {
1149         struct bfin_mac_local *lp = netdev_priv(dev);
1150         u16 *data;
1151         u32 data_align = (unsigned long)(skb->data) & 0x3;
1152 
1153         current_tx_ptr->skb = skb;
1154 
1155         if (data_align == 0x2) {
1156                 /* move skb->data to current_tx_ptr payload */
1157                 data = (u16 *)(skb->data) - 1;
1158                 *data = (u16)(skb->len);
1159                 /*
1160                  * When transmitting an Ethernet packet, the PTP_TSYNC module requires
1161                  * a DMA_Length_Word field associated with the packet. The lower 12 bits
1162                  * of this field are the length of the packet payload in bytes and the higher
1163                  * 4 bits are the timestamping enable field.
1164                  */
1165                 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
1166                         *data |= 0x1000;
1167 
1168                 current_tx_ptr->desc_a.start_addr = (u32)data;
1169                 /* this is important! */
1170                 blackfin_dcache_flush_range((u32)data,
1171                                 (u32)((u8 *)data + skb->len + 4));
1172         } else {
1173                 *((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len);
1174                 /* enable timestamping for the sent packet */
1175                 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
1176                         *((u16 *)(current_tx_ptr->packet)) |= 0x1000;
1177                 memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data,
1178                         skb->len);
1179                 current_tx_ptr->desc_a.start_addr =
1180                         (u32)current_tx_ptr->packet;
1181                 blackfin_dcache_flush_range(
1182                         (u32)current_tx_ptr->packet,
1183                         (u32)(current_tx_ptr->packet + skb->len + 2));
1184         }
1185 
1186         /* make sure the internal data buffers in the core are drained
1187          * so that the DMA descriptors are completely written when the
1188          * DMA engine goes to fetch them below
1189          */
1190         SSYNC();
1191 
1192         /* always clear status buffer before start tx dma */
1193         current_tx_ptr->status.status_word = 0;
1194 
1195         /* enable this packet's dma */
1196         current_tx_ptr->desc_a.config |= DMAEN;
1197 
1198         /* tx dma is running, just return */
1199         if (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)
1200                 goto out;
1201 
1202         /* tx dma is not running */
1203         bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a));
1204         /* dma enabled, read from memory, size is 6 */
1205         bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config);
1206         /* Turn on the EMAC tx */
1207         bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
1208 
1209 out:
1210         bfin_tx_hwtstamp(dev, skb);
1211 
1212         current_tx_ptr = current_tx_ptr->next;
1213         dev->stats.tx_packets++;
1214         dev->stats.tx_bytes += (skb->len);
1215 
1216         tx_reclaim_skb(lp);
1217 
1218         return NETDEV_TX_OK;
1219 }
1220 
1221 #define IP_HEADER_OFF  0
1222 #define RX_ERROR_MASK (RX_LONG | RX_ALIGN | RX_CRC | RX_LEN | \
1223         RX_FRAG | RX_ADDR | RX_DMAO | RX_PHY | RX_LATE | RX_RANGE)
1224 
1225 static void bfin_mac_rx(struct net_device *dev)
1226 {
1227         struct sk_buff *skb, *new_skb;
1228         unsigned short len;
1229         struct bfin_mac_local *lp __maybe_unused = netdev_priv(dev);
1230 #if defined(BFIN_MAC_CSUM_OFFLOAD)
1231         unsigned int i;
1232         unsigned char fcs[ETH_FCS_LEN + 1];
1233 #endif
1234 
1235         /* check if frame status word reports an error condition
1236          * we which case we simply drop the packet
1237          */
1238         if (current_rx_ptr->status.status_word & RX_ERROR_MASK) {
1239                 netdev_notice(dev, "rx: receive error - packet dropped\n");
1240                 dev->stats.rx_dropped++;
1241                 goto out;
1242         }
1243 
1244         /* allocate a new skb for next time receive */
1245         skb = current_rx_ptr->skb;
1246 
1247         new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN);
1248         if (!new_skb) {
1249                 dev->stats.rx_dropped++;
1250                 goto out;
1251         }
1252         /* reserve 2 bytes for RXDWA padding */
1253         skb_reserve(new_skb, NET_IP_ALIGN);
1254         /* Invidate the data cache of skb->data range when it is write back
1255          * cache. It will prevent overwritting the new data from DMA
1256          */
1257         blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
1258                                          (unsigned long)new_skb->end);
1259 
1260         current_rx_ptr->skb = new_skb;
1261         current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2;
1262 
1263         len = (unsigned short)((current_rx_ptr->status.status_word) & RX_FRLEN);
1264         /* Deduce Ethernet FCS length from Ethernet payload length */
1265         len -= ETH_FCS_LEN;
1266         skb_put(skb, len);
1267 
1268         skb->protocol = eth_type_trans(skb, dev);
1269 
1270         bfin_rx_hwtstamp(dev, skb);
1271 
1272 #if defined(BFIN_MAC_CSUM_OFFLOAD)
1273         /* Checksum offloading only works for IPv4 packets with the standard IP header
1274          * length of 20 bytes, because the blackfin MAC checksum calculation is
1275          * based on that assumption. We must NOT use the calculated checksum if our
1276          * IP version or header break that assumption.
1277          */
1278         if (skb->data[IP_HEADER_OFF] == 0x45) {
1279                 skb->csum = current_rx_ptr->status.ip_payload_csum;
1280                 /*
1281                  * Deduce Ethernet FCS from hardware generated IP payload checksum.
1282                  * IP checksum is based on 16-bit one's complement algorithm.
1283                  * To deduce a value from checksum is equal to add its inversion.
1284                  * If the IP payload len is odd, the inversed FCS should also
1285                  * begin from odd address and leave first byte zero.
1286                  */
1287                 if (skb->len % 2) {
1288                         fcs[0] = 0;
1289                         for (i = 0; i < ETH_FCS_LEN; i++)
1290                                 fcs[i + 1] = ~skb->data[skb->len + i];
1291                         skb->csum = csum_partial(fcs, ETH_FCS_LEN + 1, skb->csum);
1292                 } else {
1293                         for (i = 0; i < ETH_FCS_LEN; i++)
1294                                 fcs[i] = ~skb->data[skb->len + i];
1295                         skb->csum = csum_partial(fcs, ETH_FCS_LEN, skb->csum);
1296                 }
1297                 skb->ip_summed = CHECKSUM_COMPLETE;
1298         }
1299 #endif
1300 
1301         netif_rx(skb);
1302         dev->stats.rx_packets++;
1303         dev->stats.rx_bytes += len;
1304 out:
1305         current_rx_ptr->status.status_word = 0x00000000;
1306         current_rx_ptr = current_rx_ptr->next;
1307 }
1308 
1309 /* interrupt routine to handle rx and error signal */
1310 static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id)
1311 {
1312         struct net_device *dev = dev_id;
1313         int number = 0;
1314 
1315 get_one_packet:
1316         if (current_rx_ptr->status.status_word == 0) {
1317                 /* no more new packet received */
1318                 if (number == 0) {
1319                         if (current_rx_ptr->next->status.status_word != 0) {
1320                                 current_rx_ptr = current_rx_ptr->next;
1321                                 goto real_rx;
1322                         }
1323                 }
1324                 bfin_write_DMA1_IRQ_STATUS(bfin_read_DMA1_IRQ_STATUS() |
1325                                            DMA_DONE | DMA_ERR);
1326                 return IRQ_HANDLED;
1327         }
1328 
1329 real_rx:
1330         bfin_mac_rx(dev);
1331         number++;
1332         goto get_one_packet;
1333 }
1334 
1335 #ifdef CONFIG_NET_POLL_CONTROLLER
1336 static void bfin_mac_poll(struct net_device *dev)
1337 {
1338         struct bfin_mac_local *lp = netdev_priv(dev);
1339 
1340         disable_irq(IRQ_MAC_RX);
1341         bfin_mac_interrupt(IRQ_MAC_RX, dev);
1342         tx_reclaim_skb(lp);
1343         enable_irq(IRQ_MAC_RX);
1344 }
1345 #endif                          /* CONFIG_NET_POLL_CONTROLLER */
1346 
1347 static void bfin_mac_disable(void)
1348 {
1349         unsigned int opmode;
1350 
1351         opmode = bfin_read_EMAC_OPMODE();
1352         opmode &= (~RE);
1353         opmode &= (~TE);
1354         /* Turn off the EMAC */
1355         bfin_write_EMAC_OPMODE(opmode);
1356 }
1357 
1358 /*
1359  * Enable Interrupts, Receive, and Transmit
1360  */
1361 static int bfin_mac_enable(struct phy_device *phydev)
1362 {
1363         int ret;
1364         u32 opmode;
1365 
1366         pr_debug("%s\n", __func__);
1367 
1368         /* Set RX DMA */
1369         bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a));
1370         bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config);
1371 
1372         /* Wait MII done */
1373         ret = bfin_mdio_poll();
1374         if (ret)
1375                 return ret;
1376 
1377         /* We enable only RX here */
1378         /* ASTP   : Enable Automatic Pad Stripping
1379            PR     : Promiscuous Mode for test
1380            PSF    : Receive frames with total length less than 64 bytes.
1381            FDMODE : Full Duplex Mode
1382            LB     : Internal Loopback for test
1383            RE     : Receiver Enable */
1384         opmode = bfin_read_EMAC_OPMODE();
1385         if (opmode & FDMODE)
1386                 opmode |= PSF;
1387         else
1388                 opmode |= DRO | DC | PSF;
1389         opmode |= RE;
1390 
1391         if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
1392                 opmode |= RMII; /* For Now only 100MBit are supported */
1393 #if defined(CONFIG_BF537) || defined(CONFIG_BF536)
1394                 if (__SILICON_REVISION__ < 3) {
1395                         /*
1396                          * This isn't publicly documented (fun times!), but in
1397                          * silicon <=0.2, the RX and TX pins are clocked together.
1398                          * So in order to recv, we must enable the transmit side
1399                          * as well.  This will cause a spurious TX interrupt too,
1400                          * but we can easily consume that.
1401                          */
1402                         opmode |= TE;
1403                 }
1404 #endif
1405         }
1406 
1407         /* Turn on the EMAC rx */
1408         bfin_write_EMAC_OPMODE(opmode);
1409 
1410         return 0;
1411 }
1412 
1413 /* Our watchdog timed out. Called by the networking layer */
1414 static void bfin_mac_timeout(struct net_device *dev)
1415 {
1416         struct bfin_mac_local *lp = netdev_priv(dev);
1417 
1418         pr_debug("%s: %s\n", dev->name, __func__);
1419 
1420         bfin_mac_disable();
1421 
1422         del_timer(&lp->tx_reclaim_timer);
1423 
1424         /* reset tx queue and free skb */
1425         while (tx_list_head != current_tx_ptr) {
1426                 tx_list_head->desc_a.config &= ~DMAEN;
1427                 tx_list_head->status.status_word = 0;
1428                 if (tx_list_head->skb) {
1429                         dev_kfree_skb(tx_list_head->skb);
1430                         tx_list_head->skb = NULL;
1431                 }
1432                 tx_list_head = tx_list_head->next;
1433         }
1434 
1435         if (netif_queue_stopped(lp->ndev))
1436                 netif_wake_queue(lp->ndev);
1437 
1438         bfin_mac_enable(lp->phydev);
1439 
1440         /* We can accept TX packets again */
1441         dev->trans_start = jiffies; /* prevent tx timeout */
1442         netif_wake_queue(dev);
1443 }
1444 
1445 static void bfin_mac_multicast_hash(struct net_device *dev)
1446 {
1447         u32 emac_hashhi, emac_hashlo;
1448         struct netdev_hw_addr *ha;
1449         u32 crc;
1450 
1451         emac_hashhi = emac_hashlo = 0;
1452 
1453         netdev_for_each_mc_addr(ha, dev) {
1454                 crc = ether_crc(ETH_ALEN, ha->addr);
1455                 crc >>= 26;
1456 
1457                 if (crc & 0x20)
1458                         emac_hashhi |= 1 << (crc & 0x1f);
1459                 else
1460                         emac_hashlo |= 1 << (crc & 0x1f);
1461         }
1462 
1463         bfin_write_EMAC_HASHHI(emac_hashhi);
1464         bfin_write_EMAC_HASHLO(emac_hashlo);
1465 }
1466 
1467 /*
1468  * This routine will, depending on the values passed to it,
1469  * either make it accept multicast packets, go into
1470  * promiscuous mode (for TCPDUMP and cousins) or accept
1471  * a select set of multicast packets
1472  */
1473 static void bfin_mac_set_multicast_list(struct net_device *dev)
1474 {
1475         u32 sysctl;
1476 
1477         if (dev->flags & IFF_PROMISC) {
1478                 netdev_info(dev, "set promisc mode\n");
1479                 sysctl = bfin_read_EMAC_OPMODE();
1480                 sysctl |= PR;
1481                 bfin_write_EMAC_OPMODE(sysctl);
1482         } else if (dev->flags & IFF_ALLMULTI) {
1483                 /* accept all multicast */
1484                 sysctl = bfin_read_EMAC_OPMODE();
1485                 sysctl |= PAM;
1486                 bfin_write_EMAC_OPMODE(sysctl);
1487         } else if (!netdev_mc_empty(dev)) {
1488                 /* set up multicast hash table */
1489                 sysctl = bfin_read_EMAC_OPMODE();
1490                 sysctl |= HM;
1491                 bfin_write_EMAC_OPMODE(sysctl);
1492                 bfin_mac_multicast_hash(dev);
1493         } else {
1494                 /* clear promisc or multicast mode */
1495                 sysctl = bfin_read_EMAC_OPMODE();
1496                 sysctl &= ~(RAF | PAM);
1497                 bfin_write_EMAC_OPMODE(sysctl);
1498         }
1499 }
1500 
1501 static int bfin_mac_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1502 {
1503         struct bfin_mac_local *lp = netdev_priv(netdev);
1504 
1505         if (!netif_running(netdev))
1506                 return -EINVAL;
1507 
1508         switch (cmd) {
1509         case SIOCSHWTSTAMP:
1510                 return bfin_mac_hwtstamp_set(netdev, ifr);
1511         case SIOCGHWTSTAMP:
1512                 return bfin_mac_hwtstamp_get(netdev, ifr);
1513         default:
1514                 if (lp->phydev)
1515                         return phy_mii_ioctl(lp->phydev, ifr, cmd);
1516                 else
1517                         return -EOPNOTSUPP;
1518         }
1519 }
1520 
1521 /*
1522  * this puts the device in an inactive state
1523  */
1524 static void bfin_mac_shutdown(struct net_device *dev)
1525 {
1526         /* Turn off the EMAC */
1527         bfin_write_EMAC_OPMODE(0x00000000);
1528         /* Turn off the EMAC RX DMA */
1529         bfin_write_DMA1_CONFIG(0x0000);
1530         bfin_write_DMA2_CONFIG(0x0000);
1531 }
1532 
1533 /*
1534  * Open and Initialize the interface
1535  *
1536  * Set up everything, reset the card, etc..
1537  */
1538 static int bfin_mac_open(struct net_device *dev)
1539 {
1540         struct bfin_mac_local *lp = netdev_priv(dev);
1541         int ret;
1542         pr_debug("%s: %s\n", dev->name, __func__);
1543 
1544         /*
1545          * Check that the address is valid.  If its not, refuse
1546          * to bring the device up.  The user must specify an
1547          * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
1548          */
1549         if (!is_valid_ether_addr(dev->dev_addr)) {
1550                 netdev_warn(dev, "no valid ethernet hw addr\n");
1551                 return -EINVAL;
1552         }
1553 
1554         /* initial rx and tx list */
1555         ret = desc_list_init(dev);
1556         if (ret)
1557                 return ret;
1558 
1559         phy_start(lp->phydev);
1560         setup_system_regs(dev);
1561         setup_mac_addr(dev->dev_addr);
1562 
1563         bfin_mac_disable();
1564         ret = bfin_mac_enable(lp->phydev);
1565         if (ret)
1566                 return ret;
1567         pr_debug("hardware init finished\n");
1568 
1569         netif_start_queue(dev);
1570         netif_carrier_on(dev);
1571 
1572         return 0;
1573 }
1574 
1575 /*
1576  * this makes the board clean up everything that it can
1577  * and not talk to the outside world.   Caused by
1578  * an 'ifconfig ethX down'
1579  */
1580 static int bfin_mac_close(struct net_device *dev)
1581 {
1582         struct bfin_mac_local *lp = netdev_priv(dev);
1583         pr_debug("%s: %s\n", dev->name, __func__);
1584 
1585         netif_stop_queue(dev);
1586         netif_carrier_off(dev);
1587 
1588         phy_stop(lp->phydev);
1589         phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN);
1590 
1591         /* clear everything */
1592         bfin_mac_shutdown(dev);
1593 
1594         /* free the rx/tx buffers */
1595         desc_list_free();
1596 
1597         return 0;
1598 }
1599 
1600 static const struct net_device_ops bfin_mac_netdev_ops = {
1601         .ndo_open               = bfin_mac_open,
1602         .ndo_stop               = bfin_mac_close,
1603         .ndo_start_xmit         = bfin_mac_hard_start_xmit,
1604         .ndo_set_mac_address    = bfin_mac_set_mac_address,
1605         .ndo_tx_timeout         = bfin_mac_timeout,
1606         .ndo_set_rx_mode        = bfin_mac_set_multicast_list,
1607         .ndo_do_ioctl           = bfin_mac_ioctl,
1608         .ndo_validate_addr      = eth_validate_addr,
1609         .ndo_change_mtu         = eth_change_mtu,
1610 #ifdef CONFIG_NET_POLL_CONTROLLER
1611         .ndo_poll_controller    = bfin_mac_poll,
1612 #endif
1613 };
1614 
1615 static int bfin_mac_probe(struct platform_device *pdev)
1616 {
1617         struct net_device *ndev;
1618         struct bfin_mac_local *lp;
1619         struct platform_device *pd;
1620         struct bfin_mii_bus_platform_data *mii_bus_data;
1621         int rc;
1622 
1623         ndev = alloc_etherdev(sizeof(struct bfin_mac_local));
1624         if (!ndev)
1625                 return -ENOMEM;
1626 
1627         SET_NETDEV_DEV(ndev, &pdev->dev);
1628         platform_set_drvdata(pdev, ndev);
1629         lp = netdev_priv(ndev);
1630         lp->ndev = ndev;
1631 
1632         /* Grab the MAC address in the MAC */
1633         *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO());
1634         *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI());
1635 
1636         /* probe mac */
1637         /*todo: how to proble? which is revision_register */
1638         bfin_write_EMAC_ADDRLO(0x12345678);
1639         if (bfin_read_EMAC_ADDRLO() != 0x12345678) {
1640                 dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n");
1641                 rc = -ENODEV;
1642                 goto out_err_probe_mac;
1643         }
1644 
1645 
1646         /*
1647          * Is it valid? (Did bootloader initialize it?)
1648          * Grab the MAC from the board somehow
1649          * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c
1650          */
1651         if (!is_valid_ether_addr(ndev->dev_addr)) {
1652                 if (bfin_get_ether_addr(ndev->dev_addr) ||
1653                      !is_valid_ether_addr(ndev->dev_addr)) {
1654                         /* Still not valid, get a random one */
1655                         netdev_warn(ndev, "Setting Ethernet MAC to a random one\n");
1656                         eth_hw_addr_random(ndev);
1657                 }
1658         }
1659 
1660         setup_mac_addr(ndev->dev_addr);
1661 
1662         if (!dev_get_platdata(&pdev->dev)) {
1663                 dev_err(&pdev->dev, "Cannot get platform device bfin_mii_bus!\n");
1664                 rc = -ENODEV;
1665                 goto out_err_probe_mac;
1666         }
1667         pd = dev_get_platdata(&pdev->dev);
1668         lp->mii_bus = platform_get_drvdata(pd);
1669         if (!lp->mii_bus) {
1670                 dev_err(&pdev->dev, "Cannot get mii_bus!\n");
1671                 rc = -ENODEV;
1672                 goto out_err_probe_mac;
1673         }
1674         lp->mii_bus->priv = ndev;
1675         mii_bus_data = dev_get_platdata(&pd->dev);
1676 
1677         rc = mii_probe(ndev, mii_bus_data->phy_mode);
1678         if (rc) {
1679                 dev_err(&pdev->dev, "MII Probe failed!\n");
1680                 goto out_err_mii_probe;
1681         }
1682 
1683         lp->vlan1_mask = ETH_P_8021Q | mii_bus_data->vlan1_mask;
1684         lp->vlan2_mask = ETH_P_8021Q | mii_bus_data->vlan2_mask;
1685 
1686         /* Fill in the fields of the device structure with ethernet values. */
1687         ether_setup(ndev);
1688 
1689         ndev->netdev_ops = &bfin_mac_netdev_ops;
1690         ndev->ethtool_ops = &bfin_mac_ethtool_ops;
1691 
1692         init_timer(&lp->tx_reclaim_timer);
1693         lp->tx_reclaim_timer.data = (unsigned long)lp;
1694         lp->tx_reclaim_timer.function = tx_reclaim_skb_timeout;
1695 
1696         spin_lock_init(&lp->lock);
1697 
1698         /* now, enable interrupts */
1699         /* register irq handler */
1700         rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt,
1701                         0, "EMAC_RX", ndev);
1702         if (rc) {
1703                 dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n");
1704                 rc = -EBUSY;
1705                 goto out_err_request_irq;
1706         }
1707 
1708         rc = register_netdev(ndev);
1709         if (rc) {
1710                 dev_err(&pdev->dev, "Cannot register net device!\n");
1711                 goto out_err_reg_ndev;
1712         }
1713 
1714         bfin_mac_hwtstamp_init(ndev);
1715         rc = bfin_phc_init(ndev, &pdev->dev);
1716         if (rc) {
1717                 dev_err(&pdev->dev, "Cannot register PHC device!\n");
1718                 goto out_err_phc;
1719         }
1720 
1721         /* now, print out the card info, in a short format.. */
1722         netdev_info(ndev, "%s, Version %s\n", DRV_DESC, DRV_VERSION);
1723 
1724         return 0;
1725 
1726 out_err_phc:
1727 out_err_reg_ndev:
1728         free_irq(IRQ_MAC_RX, ndev);
1729 out_err_request_irq:
1730 out_err_mii_probe:
1731         mdiobus_unregister(lp->mii_bus);
1732         mdiobus_free(lp->mii_bus);
1733 out_err_probe_mac:
1734         free_netdev(ndev);
1735 
1736         return rc;
1737 }
1738 
1739 static int bfin_mac_remove(struct platform_device *pdev)
1740 {
1741         struct net_device *ndev = platform_get_drvdata(pdev);
1742         struct bfin_mac_local *lp = netdev_priv(ndev);
1743 
1744         bfin_phc_release(lp);
1745 
1746         lp->mii_bus->priv = NULL;
1747 
1748         unregister_netdev(ndev);
1749 
1750         free_irq(IRQ_MAC_RX, ndev);
1751 
1752         free_netdev(ndev);
1753 
1754         return 0;
1755 }
1756 
1757 #ifdef CONFIG_PM
1758 static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg)
1759 {
1760         struct net_device *net_dev = platform_get_drvdata(pdev);
1761         struct bfin_mac_local *lp = netdev_priv(net_dev);
1762 
1763         if (lp->wol) {
1764                 bfin_write_EMAC_OPMODE((bfin_read_EMAC_OPMODE() & ~TE) | RE);
1765                 bfin_write_EMAC_WKUP_CTL(MPKE);
1766                 enable_irq_wake(IRQ_MAC_WAKEDET);
1767         } else {
1768                 if (netif_running(net_dev))
1769                         bfin_mac_close(net_dev);
1770         }
1771 
1772         return 0;
1773 }
1774 
1775 static int bfin_mac_resume(struct platform_device *pdev)
1776 {
1777         struct net_device *net_dev = platform_get_drvdata(pdev);
1778         struct bfin_mac_local *lp = netdev_priv(net_dev);
1779 
1780         if (lp->wol) {
1781                 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
1782                 bfin_write_EMAC_WKUP_CTL(0);
1783                 disable_irq_wake(IRQ_MAC_WAKEDET);
1784         } else {
1785                 if (netif_running(net_dev))
1786                         bfin_mac_open(net_dev);
1787         }
1788 
1789         return 0;
1790 }
1791 #else
1792 #define bfin_mac_suspend NULL
1793 #define bfin_mac_resume NULL
1794 #endif  /* CONFIG_PM */
1795 
1796 static int bfin_mii_bus_probe(struct platform_device *pdev)
1797 {
1798         struct mii_bus *miibus;
1799         struct bfin_mii_bus_platform_data *mii_bus_pd;
1800         const unsigned short *pin_req;
1801         int rc, i;
1802 
1803         mii_bus_pd = dev_get_platdata(&pdev->dev);
1804         if (!mii_bus_pd) {
1805                 dev_err(&pdev->dev, "No peripherals in platform data!\n");
1806                 return -EINVAL;
1807         }
1808 
1809         /*
1810          * We are setting up a network card,
1811          * so set the GPIO pins to Ethernet mode
1812          */
1813         pin_req = mii_bus_pd->mac_peripherals;
1814         rc = peripheral_request_list(pin_req, KBUILD_MODNAME);
1815         if (rc) {
1816                 dev_err(&pdev->dev, "Requesting peripherals failed!\n");
1817                 return rc;
1818         }
1819 
1820         rc = -ENOMEM;
1821         miibus = mdiobus_alloc();
1822         if (miibus == NULL)
1823                 goto out_err_alloc;
1824         miibus->read = bfin_mdiobus_read;
1825         miibus->write = bfin_mdiobus_write;
1826         miibus->reset = bfin_mdiobus_reset;
1827 
1828         miibus->parent = &pdev->dev;
1829         miibus->name = "bfin_mii_bus";
1830         miibus->phy_mask = mii_bus_pd->phy_mask;
1831 
1832         snprintf(miibus->id, MII_BUS_ID_SIZE, "%s-%x",
1833                 pdev->name, pdev->id);
1834         miibus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1835         if (!miibus->irq)
1836                 goto out_err_irq_alloc;
1837 
1838         for (i = rc; i < PHY_MAX_ADDR; ++i)
1839                 miibus->irq[i] = PHY_POLL;
1840 
1841         rc = clamp(mii_bus_pd->phydev_number, 0, PHY_MAX_ADDR);
1842         if (rc != mii_bus_pd->phydev_number)
1843                 dev_err(&pdev->dev, "Invalid number (%i) of phydevs\n",
1844                         mii_bus_pd->phydev_number);
1845         for (i = 0; i < rc; ++i) {
1846                 unsigned short phyaddr = mii_bus_pd->phydev_data[i].addr;
1847                 if (phyaddr < PHY_MAX_ADDR)
1848                         miibus->irq[phyaddr] = mii_bus_pd->phydev_data[i].irq;
1849                 else
1850                         dev_err(&pdev->dev,
1851                                 "Invalid PHY address %i for phydev %i\n",
1852                                 phyaddr, i);
1853         }
1854 
1855         rc = mdiobus_register(miibus);
1856         if (rc) {
1857                 dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
1858                 goto out_err_mdiobus_register;
1859         }
1860 
1861         platform_set_drvdata(pdev, miibus);
1862         return 0;
1863 
1864 out_err_mdiobus_register:
1865         kfree(miibus->irq);
1866 out_err_irq_alloc:
1867         mdiobus_free(miibus);
1868 out_err_alloc:
1869         peripheral_free_list(pin_req);
1870 
1871         return rc;
1872 }
1873 
1874 static int bfin_mii_bus_remove(struct platform_device *pdev)
1875 {
1876         struct mii_bus *miibus = platform_get_drvdata(pdev);
1877         struct bfin_mii_bus_platform_data *mii_bus_pd =
1878                 dev_get_platdata(&pdev->dev);
1879 
1880         mdiobus_unregister(miibus);
1881         kfree(miibus->irq);
1882         mdiobus_free(miibus);
1883         peripheral_free_list(mii_bus_pd->mac_peripherals);
1884 
1885         return 0;
1886 }
1887 
1888 static struct platform_driver bfin_mii_bus_driver = {
1889         .probe = bfin_mii_bus_probe,
1890         .remove = bfin_mii_bus_remove,
1891         .driver = {
1892                 .name = "bfin_mii_bus",
1893                 .owner  = THIS_MODULE,
1894         },
1895 };
1896 
1897 static struct platform_driver bfin_mac_driver = {
1898         .probe = bfin_mac_probe,
1899         .remove = bfin_mac_remove,
1900         .resume = bfin_mac_resume,
1901         .suspend = bfin_mac_suspend,
1902         .driver = {
1903                 .name = KBUILD_MODNAME,
1904                 .owner  = THIS_MODULE,
1905         },
1906 };
1907 
1908 static int __init bfin_mac_init(void)
1909 {
1910         int ret;
1911         ret = platform_driver_register(&bfin_mii_bus_driver);
1912         if (!ret)
1913                 return platform_driver_register(&bfin_mac_driver);
1914         return -ENODEV;
1915 }
1916 
1917 module_init(bfin_mac_init);
1918 
1919 static void __exit bfin_mac_cleanup(void)
1920 {
1921         platform_driver_unregister(&bfin_mac_driver);
1922         platform_driver_unregister(&bfin_mii_bus_driver);
1923 }
1924 
1925 module_exit(bfin_mac_cleanup);
1926 
1927 

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