Version:  2.0.40 2.2.26 2.4.37 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0

Linux/drivers/net/can/pch_can.c

  1 /*
  2  * Copyright (C) 1999 - 2010 Intel Corporation.
  3  * Copyright (C) 2010 LAPIS SEMICONDUCTOR CO., LTD.
  4  *
  5  * This program is free software; you can redistribute it and/or modify
  6  * it under the terms of the GNU General Public License as published by
  7  * the Free Software Foundation; version 2 of the License.
  8  *
  9  * This program is distributed in the hope that it will be useful,
 10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 12  * GNU General Public License for more details.
 13  *
 14  * You should have received a copy of the GNU General Public License
 15  * along with this program; if not, see <http://www.gnu.org/licenses/>.
 16  */
 17 
 18 #include <linux/interrupt.h>
 19 #include <linux/delay.h>
 20 #include <linux/io.h>
 21 #include <linux/module.h>
 22 #include <linux/sched.h>
 23 #include <linux/pci.h>
 24 #include <linux/kernel.h>
 25 #include <linux/types.h>
 26 #include <linux/errno.h>
 27 #include <linux/netdevice.h>
 28 #include <linux/skbuff.h>
 29 #include <linux/can.h>
 30 #include <linux/can/dev.h>
 31 #include <linux/can/error.h>
 32 
 33 #define PCH_CTRL_INIT           BIT(0) /* The INIT bit of CANCONT register. */
 34 #define PCH_CTRL_IE             BIT(1) /* The IE bit of CAN control register */
 35 #define PCH_CTRL_IE_SIE_EIE     (BIT(3) | BIT(2) | BIT(1))
 36 #define PCH_CTRL_CCE            BIT(6)
 37 #define PCH_CTRL_OPT            BIT(7) /* The OPT bit of CANCONT register. */
 38 #define PCH_OPT_SILENT          BIT(3) /* The Silent bit of CANOPT reg. */
 39 #define PCH_OPT_LBACK           BIT(4) /* The LoopBack bit of CANOPT reg. */
 40 
 41 #define PCH_CMASK_RX_TX_SET     0x00f3
 42 #define PCH_CMASK_RX_TX_GET     0x0073
 43 #define PCH_CMASK_ALL           0xff
 44 #define PCH_CMASK_NEWDAT        BIT(2)
 45 #define PCH_CMASK_CLRINTPND     BIT(3)
 46 #define PCH_CMASK_CTRL          BIT(4)
 47 #define PCH_CMASK_ARB           BIT(5)
 48 #define PCH_CMASK_MASK          BIT(6)
 49 #define PCH_CMASK_RDWR          BIT(7)
 50 #define PCH_IF_MCONT_NEWDAT     BIT(15)
 51 #define PCH_IF_MCONT_MSGLOST    BIT(14)
 52 #define PCH_IF_MCONT_INTPND     BIT(13)
 53 #define PCH_IF_MCONT_UMASK      BIT(12)
 54 #define PCH_IF_MCONT_TXIE       BIT(11)
 55 #define PCH_IF_MCONT_RXIE       BIT(10)
 56 #define PCH_IF_MCONT_RMTEN      BIT(9)
 57 #define PCH_IF_MCONT_TXRQXT     BIT(8)
 58 #define PCH_IF_MCONT_EOB        BIT(7)
 59 #define PCH_IF_MCONT_DLC        (BIT(0) | BIT(1) | BIT(2) | BIT(3))
 60 #define PCH_MASK2_MDIR_MXTD     (BIT(14) | BIT(15))
 61 #define PCH_ID2_DIR             BIT(13)
 62 #define PCH_ID2_XTD             BIT(14)
 63 #define PCH_ID_MSGVAL           BIT(15)
 64 #define PCH_IF_CREQ_BUSY        BIT(15)
 65 
 66 #define PCH_STATUS_INT          0x8000
 67 #define PCH_RP                  0x00008000
 68 #define PCH_REC                 0x00007f00
 69 #define PCH_TEC                 0x000000ff
 70 
 71 #define PCH_TX_OK               BIT(3)
 72 #define PCH_RX_OK               BIT(4)
 73 #define PCH_EPASSIV             BIT(5)
 74 #define PCH_EWARN               BIT(6)
 75 #define PCH_BUS_OFF             BIT(7)
 76 
 77 /* bit position of certain controller bits. */
 78 #define PCH_BIT_BRP_SHIFT       0
 79 #define PCH_BIT_SJW_SHIFT       6
 80 #define PCH_BIT_TSEG1_SHIFT     8
 81 #define PCH_BIT_TSEG2_SHIFT     12
 82 #define PCH_BIT_BRPE_BRPE_SHIFT 6
 83 
 84 #define PCH_MSK_BITT_BRP        0x3f
 85 #define PCH_MSK_BRPE_BRPE       0x3c0
 86 #define PCH_MSK_CTRL_IE_SIE_EIE 0x07
 87 #define PCH_COUNTER_LIMIT       10
 88 
 89 #define PCH_CAN_CLK             50000000        /* 50MHz */
 90 
 91 /*
 92  * Define the number of message object.
 93  * PCH CAN communications are done via Message RAM.
 94  * The Message RAM consists of 32 message objects.
 95  */
 96 #define PCH_RX_OBJ_NUM          26
 97 #define PCH_TX_OBJ_NUM          6
 98 #define PCH_RX_OBJ_START        1
 99 #define PCH_RX_OBJ_END          PCH_RX_OBJ_NUM
100 #define PCH_TX_OBJ_START        (PCH_RX_OBJ_END + 1)
101 #define PCH_TX_OBJ_END          (PCH_RX_OBJ_NUM + PCH_TX_OBJ_NUM)
102 
103 #define PCH_FIFO_THRESH         16
104 
105 /* TxRqst2 show status of MsgObjNo.17~32 */
106 #define PCH_TREQ2_TX_MASK       (((1 << PCH_TX_OBJ_NUM) - 1) <<\
107                                                         (PCH_RX_OBJ_END - 16))
108 
109 enum pch_ifreg {
110         PCH_RX_IFREG,
111         PCH_TX_IFREG,
112 };
113 
114 enum pch_can_err {
115         PCH_STUF_ERR = 1,
116         PCH_FORM_ERR,
117         PCH_ACK_ERR,
118         PCH_BIT1_ERR,
119         PCH_BIT0_ERR,
120         PCH_CRC_ERR,
121         PCH_LEC_ALL,
122 };
123 
124 enum pch_can_mode {
125         PCH_CAN_ENABLE,
126         PCH_CAN_DISABLE,
127         PCH_CAN_ALL,
128         PCH_CAN_NONE,
129         PCH_CAN_STOP,
130         PCH_CAN_RUN,
131 };
132 
133 struct pch_can_if_regs {
134         u32 creq;
135         u32 cmask;
136         u32 mask1;
137         u32 mask2;
138         u32 id1;
139         u32 id2;
140         u32 mcont;
141         u32 data[4];
142         u32 rsv[13];
143 };
144 
145 struct pch_can_regs {
146         u32 cont;
147         u32 stat;
148         u32 errc;
149         u32 bitt;
150         u32 intr;
151         u32 opt;
152         u32 brpe;
153         u32 reserve;
154         struct pch_can_if_regs ifregs[2]; /* [0]=if1  [1]=if2 */
155         u32 reserve1[8];
156         u32 treq1;
157         u32 treq2;
158         u32 reserve2[6];
159         u32 data1;
160         u32 data2;
161         u32 reserve3[6];
162         u32 canipend1;
163         u32 canipend2;
164         u32 reserve4[6];
165         u32 canmval1;
166         u32 canmval2;
167         u32 reserve5[37];
168         u32 srst;
169 };
170 
171 struct pch_can_priv {
172         struct can_priv can;
173         struct pci_dev *dev;
174         u32 tx_enable[PCH_TX_OBJ_END];
175         u32 rx_enable[PCH_TX_OBJ_END];
176         u32 rx_link[PCH_TX_OBJ_END];
177         u32 int_enables;
178         struct net_device *ndev;
179         struct pch_can_regs __iomem *regs;
180         struct napi_struct napi;
181         int tx_obj;     /* Point next Tx Obj index */
182         int use_msi;
183 };
184 
185 static const struct can_bittiming_const pch_can_bittiming_const = {
186         .name = KBUILD_MODNAME,
187         .tseg1_min = 2,
188         .tseg1_max = 16,
189         .tseg2_min = 1,
190         .tseg2_max = 8,
191         .sjw_max = 4,
192         .brp_min = 1,
193         .brp_max = 1024, /* 6bit + extended 4bit */
194         .brp_inc = 1,
195 };
196 
197 static const struct pci_device_id pch_pci_tbl[] = {
198         {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,},
199         {0,}
200 };
201 MODULE_DEVICE_TABLE(pci, pch_pci_tbl);
202 
203 static inline void pch_can_bit_set(void __iomem *addr, u32 mask)
204 {
205         iowrite32(ioread32(addr) | mask, addr);
206 }
207 
208 static inline void pch_can_bit_clear(void __iomem *addr, u32 mask)
209 {
210         iowrite32(ioread32(addr) & ~mask, addr);
211 }
212 
213 static void pch_can_set_run_mode(struct pch_can_priv *priv,
214                                  enum pch_can_mode mode)
215 {
216         switch (mode) {
217         case PCH_CAN_RUN:
218                 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT);
219                 break;
220 
221         case PCH_CAN_STOP:
222                 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT);
223                 break;
224 
225         default:
226                 netdev_err(priv->ndev, "%s -> Invalid Mode.\n", __func__);
227                 break;
228         }
229 }
230 
231 static void pch_can_set_optmode(struct pch_can_priv *priv)
232 {
233         u32 reg_val = ioread32(&priv->regs->opt);
234 
235         if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
236                 reg_val |= PCH_OPT_SILENT;
237 
238         if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
239                 reg_val |= PCH_OPT_LBACK;
240 
241         pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT);
242         iowrite32(reg_val, &priv->regs->opt);
243 }
244 
245 static void pch_can_rw_msg_obj(void __iomem *creq_addr, u32 num)
246 {
247         int counter = PCH_COUNTER_LIMIT;
248         u32 ifx_creq;
249 
250         iowrite32(num, creq_addr);
251         while (counter) {
252                 ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY;
253                 if (!ifx_creq)
254                         break;
255                 counter--;
256                 udelay(1);
257         }
258         if (!counter)
259                 pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__);
260 }
261 
262 static void pch_can_set_int_enables(struct pch_can_priv *priv,
263                                     enum pch_can_mode interrupt_no)
264 {
265         switch (interrupt_no) {
266         case PCH_CAN_DISABLE:
267                 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE);
268                 break;
269 
270         case PCH_CAN_ALL:
271                 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
272                 break;
273 
274         case PCH_CAN_NONE:
275                 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
276                 break;
277 
278         default:
279                 netdev_err(priv->ndev, "Invalid interrupt number.\n");
280                 break;
281         }
282 }
283 
284 static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num,
285                              int set, enum pch_ifreg dir)
286 {
287         u32 ie;
288 
289         if (dir)
290                 ie = PCH_IF_MCONT_TXIE;
291         else
292                 ie = PCH_IF_MCONT_RXIE;
293 
294         /* Reading the Msg buffer from Message RAM to IF1/2 registers. */
295         iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
296         pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
297 
298         /* Setting the IF1/2MASK1 register to access MsgVal and RxIE bits */
299         iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL,
300                   &priv->regs->ifregs[dir].cmask);
301 
302         if (set) {
303                 /* Setting the MsgVal and RxIE/TxIE bits */
304                 pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie);
305                 pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
306         } else {
307                 /* Clearing the MsgVal and RxIE/TxIE bits */
308                 pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie);
309                 pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
310         }
311 
312         pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
313 }
314 
315 static void pch_can_set_rx_all(struct pch_can_priv *priv, int set)
316 {
317         int i;
318 
319         /* Traversing to obtain the object configured as receivers. */
320         for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++)
321                 pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG);
322 }
323 
324 static void pch_can_set_tx_all(struct pch_can_priv *priv, int set)
325 {
326         int i;
327 
328         /* Traversing to obtain the object configured as transmit object. */
329         for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
330                 pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG);
331 }
332 
333 static u32 pch_can_int_pending(struct pch_can_priv *priv)
334 {
335         return ioread32(&priv->regs->intr) & 0xffff;
336 }
337 
338 static void pch_can_clear_if_buffers(struct pch_can_priv *priv)
339 {
340         int i; /* Msg Obj ID (1~32) */
341 
342         for (i = PCH_RX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
343                 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask);
344                 iowrite32(0xffff, &priv->regs->ifregs[0].mask1);
345                 iowrite32(0xffff, &priv->regs->ifregs[0].mask2);
346                 iowrite32(0x0, &priv->regs->ifregs[0].id1);
347                 iowrite32(0x0, &priv->regs->ifregs[0].id2);
348                 iowrite32(0x0, &priv->regs->ifregs[0].mcont);
349                 iowrite32(0x0, &priv->regs->ifregs[0].data[0]);
350                 iowrite32(0x0, &priv->regs->ifregs[0].data[1]);
351                 iowrite32(0x0, &priv->regs->ifregs[0].data[2]);
352                 iowrite32(0x0, &priv->regs->ifregs[0].data[3]);
353                 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
354                           PCH_CMASK_ARB | PCH_CMASK_CTRL,
355                           &priv->regs->ifregs[0].cmask);
356                 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
357         }
358 }
359 
360 static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
361 {
362         int i;
363 
364         for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
365                 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
366                 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
367 
368                 iowrite32(0x0, &priv->regs->ifregs[0].id1);
369                 iowrite32(0x0, &priv->regs->ifregs[0].id2);
370 
371                 pch_can_bit_set(&priv->regs->ifregs[0].mcont,
372                                 PCH_IF_MCONT_UMASK);
373 
374                 /* In case FIFO mode, Last EoB of Rx Obj must be 1 */
375                 if (i == PCH_RX_OBJ_END)
376                         pch_can_bit_set(&priv->regs->ifregs[0].mcont,
377                                         PCH_IF_MCONT_EOB);
378                 else
379                         pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
380                                           PCH_IF_MCONT_EOB);
381 
382                 iowrite32(0, &priv->regs->ifregs[0].mask1);
383                 pch_can_bit_clear(&priv->regs->ifregs[0].mask2,
384                                   0x1fff | PCH_MASK2_MDIR_MXTD);
385 
386                 /* Setting CMASK for writing */
387                 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB |
388                           PCH_CMASK_CTRL, &priv->regs->ifregs[0].cmask);
389 
390                 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
391         }
392 
393         for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
394                 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask);
395                 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
396 
397                 /* Resetting DIR bit for reception */
398                 iowrite32(0x0, &priv->regs->ifregs[1].id1);
399                 iowrite32(PCH_ID2_DIR, &priv->regs->ifregs[1].id2);
400 
401                 /* Setting EOB bit for transmitter */
402                 iowrite32(PCH_IF_MCONT_EOB | PCH_IF_MCONT_UMASK,
403                           &priv->regs->ifregs[1].mcont);
404 
405                 iowrite32(0, &priv->regs->ifregs[1].mask1);
406                 pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff);
407 
408                 /* Setting CMASK for writing */
409                 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB |
410                           PCH_CMASK_CTRL, &priv->regs->ifregs[1].cmask);
411 
412                 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
413         }
414 }
415 
416 static void pch_can_init(struct pch_can_priv *priv)
417 {
418         /* Stopping the Can device. */
419         pch_can_set_run_mode(priv, PCH_CAN_STOP);
420 
421         /* Clearing all the message object buffers. */
422         pch_can_clear_if_buffers(priv);
423 
424         /* Configuring the respective message object as either rx/tx object. */
425         pch_can_config_rx_tx_buffers(priv);
426 
427         /* Enabling the interrupts. */
428         pch_can_set_int_enables(priv, PCH_CAN_ALL);
429 }
430 
431 static void pch_can_release(struct pch_can_priv *priv)
432 {
433         /* Stooping the CAN device. */
434         pch_can_set_run_mode(priv, PCH_CAN_STOP);
435 
436         /* Disabling the interrupts. */
437         pch_can_set_int_enables(priv, PCH_CAN_NONE);
438 
439         /* Disabling all the receive object. */
440         pch_can_set_rx_all(priv, 0);
441 
442         /* Disabling all the transmit object. */
443         pch_can_set_tx_all(priv, 0);
444 }
445 
446 /* This function clears interrupt(s) from the CAN device. */
447 static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
448 {
449         /* Clear interrupt for transmit object */
450         if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) {
451                 /* Setting CMASK for clearing the reception interrupts. */
452                 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
453                           &priv->regs->ifregs[0].cmask);
454 
455                 /* Clearing the Dir bit. */
456                 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
457 
458                 /* Clearing NewDat & IntPnd */
459                 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
460                                   PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND);
461 
462                 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, mask);
463         } else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) {
464                 /*
465                  * Setting CMASK for clearing interrupts for frame transmission.
466                  */
467                 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
468                           &priv->regs->ifregs[1].cmask);
469 
470                 /* Resetting the ID registers. */
471                 pch_can_bit_set(&priv->regs->ifregs[1].id2,
472                                PCH_ID2_DIR | (0x7ff << 2));
473                 iowrite32(0x0, &priv->regs->ifregs[1].id1);
474 
475                 /* Claring NewDat, TxRqst & IntPnd */
476                 pch_can_bit_clear(&priv->regs->ifregs[1].mcont,
477                                   PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
478                                   PCH_IF_MCONT_TXRQXT);
479                 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, mask);
480         }
481 }
482 
483 static void pch_can_reset(struct pch_can_priv *priv)
484 {
485         /* write to sw reset register */
486         iowrite32(1, &priv->regs->srst);
487         iowrite32(0, &priv->regs->srst);
488 }
489 
490 static void pch_can_error(struct net_device *ndev, u32 status)
491 {
492         struct sk_buff *skb;
493         struct pch_can_priv *priv = netdev_priv(ndev);
494         struct can_frame *cf;
495         u32 errc, lec;
496         struct net_device_stats *stats = &(priv->ndev->stats);
497         enum can_state state = priv->can.state;
498 
499         skb = alloc_can_err_skb(ndev, &cf);
500         if (!skb)
501                 return;
502 
503         if (status & PCH_BUS_OFF) {
504                 pch_can_set_tx_all(priv, 0);
505                 pch_can_set_rx_all(priv, 0);
506                 state = CAN_STATE_BUS_OFF;
507                 cf->can_id |= CAN_ERR_BUSOFF;
508                 priv->can.can_stats.bus_off++;
509                 can_bus_off(ndev);
510         }
511 
512         errc = ioread32(&priv->regs->errc);
513         /* Warning interrupt. */
514         if (status & PCH_EWARN) {
515                 state = CAN_STATE_ERROR_WARNING;
516                 priv->can.can_stats.error_warning++;
517                 cf->can_id |= CAN_ERR_CRTL;
518                 if (((errc & PCH_REC) >> 8) > 96)
519                         cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
520                 if ((errc & PCH_TEC) > 96)
521                         cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
522                 netdev_dbg(ndev,
523                         "%s -> Error Counter is more than 96.\n", __func__);
524         }
525         /* Error passive interrupt. */
526         if (status & PCH_EPASSIV) {
527                 priv->can.can_stats.error_passive++;
528                 state = CAN_STATE_ERROR_PASSIVE;
529                 cf->can_id |= CAN_ERR_CRTL;
530                 if (errc & PCH_RP)
531                         cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
532                 if ((errc & PCH_TEC) > 127)
533                         cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
534                 netdev_dbg(ndev,
535                         "%s -> CAN controller is ERROR PASSIVE .\n", __func__);
536         }
537 
538         lec = status & PCH_LEC_ALL;
539         switch (lec) {
540         case PCH_STUF_ERR:
541                 cf->data[2] |= CAN_ERR_PROT_STUFF;
542                 priv->can.can_stats.bus_error++;
543                 stats->rx_errors++;
544                 break;
545         case PCH_FORM_ERR:
546                 cf->data[2] |= CAN_ERR_PROT_FORM;
547                 priv->can.can_stats.bus_error++;
548                 stats->rx_errors++;
549                 break;
550         case PCH_ACK_ERR:
551                 cf->can_id |= CAN_ERR_ACK;
552                 priv->can.can_stats.bus_error++;
553                 stats->rx_errors++;
554                 break;
555         case PCH_BIT1_ERR:
556         case PCH_BIT0_ERR:
557                 cf->data[2] |= CAN_ERR_PROT_BIT;
558                 priv->can.can_stats.bus_error++;
559                 stats->rx_errors++;
560                 break;
561         case PCH_CRC_ERR:
562                 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ |
563                                CAN_ERR_PROT_LOC_CRC_DEL;
564                 priv->can.can_stats.bus_error++;
565                 stats->rx_errors++;
566                 break;
567         case PCH_LEC_ALL: /* Written by CPU. No error status */
568                 break;
569         }
570 
571         cf->data[6] = errc & PCH_TEC;
572         cf->data[7] = (errc & PCH_REC) >> 8;
573 
574         priv->can.state = state;
575         netif_receive_skb(skb);
576 
577         stats->rx_packets++;
578         stats->rx_bytes += cf->can_dlc;
579 }
580 
581 static irqreturn_t pch_can_interrupt(int irq, void *dev_id)
582 {
583         struct net_device *ndev = (struct net_device *)dev_id;
584         struct pch_can_priv *priv = netdev_priv(ndev);
585 
586         if (!pch_can_int_pending(priv))
587                 return IRQ_NONE;
588 
589         pch_can_set_int_enables(priv, PCH_CAN_NONE);
590         napi_schedule(&priv->napi);
591         return IRQ_HANDLED;
592 }
593 
594 static void pch_fifo_thresh(struct pch_can_priv *priv, int obj_id)
595 {
596         if (obj_id < PCH_FIFO_THRESH) {
597                 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL |
598                           PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask);
599 
600                 /* Clearing the Dir bit. */
601                 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
602 
603                 /* Clearing NewDat & IntPnd */
604                 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
605                                   PCH_IF_MCONT_INTPND);
606                 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
607         } else if (obj_id > PCH_FIFO_THRESH) {
608                 pch_can_int_clr(priv, obj_id);
609         } else if (obj_id == PCH_FIFO_THRESH) {
610                 int cnt;
611                 for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++)
612                         pch_can_int_clr(priv, cnt + 1);
613         }
614 }
615 
616 static void pch_can_rx_msg_lost(struct net_device *ndev, int obj_id)
617 {
618         struct pch_can_priv *priv = netdev_priv(ndev);
619         struct net_device_stats *stats = &(priv->ndev->stats);
620         struct sk_buff *skb;
621         struct can_frame *cf;
622 
623         netdev_dbg(priv->ndev, "Msg Obj is overwritten.\n");
624         pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
625                           PCH_IF_MCONT_MSGLOST);
626         iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
627                   &priv->regs->ifregs[0].cmask);
628         pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
629 
630         skb = alloc_can_err_skb(ndev, &cf);
631         if (!skb)
632                 return;
633 
634         cf->can_id |= CAN_ERR_CRTL;
635         cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
636         stats->rx_over_errors++;
637         stats->rx_errors++;
638 
639         netif_receive_skb(skb);
640 }
641 
642 static int pch_can_rx_normal(struct net_device *ndev, u32 obj_num, int quota)
643 {
644         u32 reg;
645         canid_t id;
646         int rcv_pkts = 0;
647         struct sk_buff *skb;
648         struct can_frame *cf;
649         struct pch_can_priv *priv = netdev_priv(ndev);
650         struct net_device_stats *stats = &(priv->ndev->stats);
651         int i;
652         u32 id2;
653         u16 data_reg;
654 
655         do {
656                 /* Reading the message object from the Message RAM */
657                 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
658                 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_num);
659 
660                 /* Reading the MCONT register. */
661                 reg = ioread32(&priv->regs->ifregs[0].mcont);
662 
663                 if (reg & PCH_IF_MCONT_EOB)
664                         break;
665 
666                 /* If MsgLost bit set. */
667                 if (reg & PCH_IF_MCONT_MSGLOST) {
668                         pch_can_rx_msg_lost(ndev, obj_num);
669                         rcv_pkts++;
670                         quota--;
671                         obj_num++;
672                         continue;
673                 } else if (!(reg & PCH_IF_MCONT_NEWDAT)) {
674                         obj_num++;
675                         continue;
676                 }
677 
678                 skb = alloc_can_skb(priv->ndev, &cf);
679                 if (!skb) {
680                         netdev_err(ndev, "alloc_can_skb Failed\n");
681                         return rcv_pkts;
682                 }
683 
684                 /* Get Received data */
685                 id2 = ioread32(&priv->regs->ifregs[0].id2);
686                 if (id2 & PCH_ID2_XTD) {
687                         id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff);
688                         id |= (((id2) & 0x1fff) << 16);
689                         cf->can_id = id | CAN_EFF_FLAG;
690                 } else {
691                         id = (id2 >> 2) & CAN_SFF_MASK;
692                         cf->can_id = id;
693                 }
694 
695                 if (id2 & PCH_ID2_DIR)
696                         cf->can_id |= CAN_RTR_FLAG;
697 
698                 cf->can_dlc = get_can_dlc((ioread32(&priv->regs->
699                                                     ifregs[0].mcont)) & 0xF);
700 
701                 for (i = 0; i < cf->can_dlc; i += 2) {
702                         data_reg = ioread16(&priv->regs->ifregs[0].data[i / 2]);
703                         cf->data[i] = data_reg;
704                         cf->data[i + 1] = data_reg >> 8;
705                 }
706 
707                 netif_receive_skb(skb);
708                 rcv_pkts++;
709                 stats->rx_packets++;
710                 quota--;
711                 stats->rx_bytes += cf->can_dlc;
712 
713                 pch_fifo_thresh(priv, obj_num);
714                 obj_num++;
715         } while (quota > 0);
716 
717         return rcv_pkts;
718 }
719 
720 static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat)
721 {
722         struct pch_can_priv *priv = netdev_priv(ndev);
723         struct net_device_stats *stats = &(priv->ndev->stats);
724         u32 dlc;
725 
726         can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1);
727         iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND,
728                   &priv->regs->ifregs[1].cmask);
729         pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, int_stat);
730         dlc = get_can_dlc(ioread32(&priv->regs->ifregs[1].mcont) &
731                           PCH_IF_MCONT_DLC);
732         stats->tx_bytes += dlc;
733         stats->tx_packets++;
734         if (int_stat == PCH_TX_OBJ_END)
735                 netif_wake_queue(ndev);
736 }
737 
738 static int pch_can_poll(struct napi_struct *napi, int quota)
739 {
740         struct net_device *ndev = napi->dev;
741         struct pch_can_priv *priv = netdev_priv(ndev);
742         u32 int_stat;
743         u32 reg_stat;
744         int quota_save = quota;
745 
746         int_stat = pch_can_int_pending(priv);
747         if (!int_stat)
748                 goto end;
749 
750         if (int_stat == PCH_STATUS_INT) {
751                 reg_stat = ioread32(&priv->regs->stat);
752 
753                 if ((reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) &&
754                    ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL)) {
755                         pch_can_error(ndev, reg_stat);
756                         quota--;
757                 }
758 
759                 if (reg_stat & (PCH_TX_OK | PCH_RX_OK))
760                         pch_can_bit_clear(&priv->regs->stat,
761                                           reg_stat & (PCH_TX_OK | PCH_RX_OK));
762 
763                 int_stat = pch_can_int_pending(priv);
764         }
765 
766         if (quota == 0)
767                 goto end;
768 
769         if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) {
770                 quota -= pch_can_rx_normal(ndev, int_stat, quota);
771         } else if ((int_stat >= PCH_TX_OBJ_START) &&
772                    (int_stat <= PCH_TX_OBJ_END)) {
773                 /* Handle transmission interrupt */
774                 pch_can_tx_complete(ndev, int_stat);
775         }
776 
777 end:
778         napi_complete(napi);
779         pch_can_set_int_enables(priv, PCH_CAN_ALL);
780 
781         return quota_save - quota;
782 }
783 
784 static int pch_set_bittiming(struct net_device *ndev)
785 {
786         struct pch_can_priv *priv = netdev_priv(ndev);
787         const struct can_bittiming *bt = &priv->can.bittiming;
788         u32 canbit;
789         u32 bepe;
790 
791         /* Setting the CCE bit for accessing the Can Timing register. */
792         pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE);
793 
794         canbit = (bt->brp - 1) & PCH_MSK_BITT_BRP;
795         canbit |= (bt->sjw - 1) << PCH_BIT_SJW_SHIFT;
796         canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1_SHIFT;
797         canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2_SHIFT;
798         bepe = ((bt->brp - 1) & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE_SHIFT;
799         iowrite32(canbit, &priv->regs->bitt);
800         iowrite32(bepe, &priv->regs->brpe);
801         pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE);
802 
803         return 0;
804 }
805 
806 static void pch_can_start(struct net_device *ndev)
807 {
808         struct pch_can_priv *priv = netdev_priv(ndev);
809 
810         if (priv->can.state != CAN_STATE_STOPPED)
811                 pch_can_reset(priv);
812 
813         pch_set_bittiming(ndev);
814         pch_can_set_optmode(priv);
815 
816         pch_can_set_tx_all(priv, 1);
817         pch_can_set_rx_all(priv, 1);
818 
819         /* Setting the CAN to run mode. */
820         pch_can_set_run_mode(priv, PCH_CAN_RUN);
821 
822         priv->can.state = CAN_STATE_ERROR_ACTIVE;
823 
824         return;
825 }
826 
827 static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode)
828 {
829         int ret = 0;
830 
831         switch (mode) {
832         case CAN_MODE_START:
833                 pch_can_start(ndev);
834                 netif_wake_queue(ndev);
835                 break;
836         default:
837                 ret = -EOPNOTSUPP;
838                 break;
839         }
840 
841         return ret;
842 }
843 
844 static int pch_can_open(struct net_device *ndev)
845 {
846         struct pch_can_priv *priv = netdev_priv(ndev);
847         int retval;
848 
849         /* Regstering the interrupt. */
850         retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED,
851                              ndev->name, ndev);
852         if (retval) {
853                 netdev_err(ndev, "request_irq failed.\n");
854                 goto req_irq_err;
855         }
856 
857         /* Open common can device */
858         retval = open_candev(ndev);
859         if (retval) {
860                 netdev_err(ndev, "open_candev() failed %d\n", retval);
861                 goto err_open_candev;
862         }
863 
864         pch_can_init(priv);
865         pch_can_start(ndev);
866         napi_enable(&priv->napi);
867         netif_start_queue(ndev);
868 
869         return 0;
870 
871 err_open_candev:
872         free_irq(priv->dev->irq, ndev);
873 req_irq_err:
874         pch_can_release(priv);
875 
876         return retval;
877 }
878 
879 static int pch_close(struct net_device *ndev)
880 {
881         struct pch_can_priv *priv = netdev_priv(ndev);
882 
883         netif_stop_queue(ndev);
884         napi_disable(&priv->napi);
885         pch_can_release(priv);
886         free_irq(priv->dev->irq, ndev);
887         close_candev(ndev);
888         priv->can.state = CAN_STATE_STOPPED;
889         return 0;
890 }
891 
892 static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
893 {
894         struct pch_can_priv *priv = netdev_priv(ndev);
895         struct can_frame *cf = (struct can_frame *)skb->data;
896         int tx_obj_no;
897         int i;
898         u32 id2;
899 
900         if (can_dropped_invalid_skb(ndev, skb))
901                 return NETDEV_TX_OK;
902 
903         tx_obj_no = priv->tx_obj;
904         if (priv->tx_obj == PCH_TX_OBJ_END) {
905                 if (ioread32(&priv->regs->treq2) & PCH_TREQ2_TX_MASK)
906                         netif_stop_queue(ndev);
907 
908                 priv->tx_obj = PCH_TX_OBJ_START;
909         } else {
910                 priv->tx_obj++;
911         }
912 
913         /* Setting the CMASK register. */
914         pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL);
915 
916         /* If ID extended is set. */
917         if (cf->can_id & CAN_EFF_FLAG) {
918                 iowrite32(cf->can_id & 0xffff, &priv->regs->ifregs[1].id1);
919                 id2 = ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD;
920         } else {
921                 iowrite32(0, &priv->regs->ifregs[1].id1);
922                 id2 = (cf->can_id & CAN_SFF_MASK) << 2;
923         }
924 
925         id2 |= PCH_ID_MSGVAL;
926 
927         /* If remote frame has to be transmitted.. */
928         if (!(cf->can_id & CAN_RTR_FLAG))
929                 id2 |= PCH_ID2_DIR;
930 
931         iowrite32(id2, &priv->regs->ifregs[1].id2);
932 
933         /* Copy data to register */
934         for (i = 0; i < cf->can_dlc; i += 2) {
935                 iowrite16(cf->data[i] | (cf->data[i + 1] << 8),
936                           &priv->regs->ifregs[1].data[i / 2]);
937         }
938 
939         can_put_echo_skb(skb, ndev, tx_obj_no - PCH_RX_OBJ_END - 1);
940 
941         /* Set the size of the data. Update if2_mcont */
942         iowrite32(cf->can_dlc | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT |
943                   PCH_IF_MCONT_TXIE, &priv->regs->ifregs[1].mcont);
944 
945         pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, tx_obj_no);
946 
947         return NETDEV_TX_OK;
948 }
949 
950 static const struct net_device_ops pch_can_netdev_ops = {
951         .ndo_open               = pch_can_open,
952         .ndo_stop               = pch_close,
953         .ndo_start_xmit         = pch_xmit,
954         .ndo_change_mtu         = can_change_mtu,
955 };
956 
957 static void pch_can_remove(struct pci_dev *pdev)
958 {
959         struct net_device *ndev = pci_get_drvdata(pdev);
960         struct pch_can_priv *priv = netdev_priv(ndev);
961 
962         unregister_candev(priv->ndev);
963         if (priv->use_msi)
964                 pci_disable_msi(priv->dev);
965         pci_release_regions(pdev);
966         pci_disable_device(pdev);
967         pch_can_reset(priv);
968         pci_iounmap(pdev, priv->regs);
969         free_candev(priv->ndev);
970 }
971 
972 #ifdef CONFIG_PM
973 static void pch_can_set_int_custom(struct pch_can_priv *priv)
974 {
975         /* Clearing the IE, SIE and EIE bits of Can control register. */
976         pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
977 
978         /* Appropriately setting them. */
979         pch_can_bit_set(&priv->regs->cont,
980                         ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1));
981 }
982 
983 /* This function retrieves interrupt enabled for the CAN device. */
984 static u32 pch_can_get_int_enables(struct pch_can_priv *priv)
985 {
986         /* Obtaining the status of IE, SIE and EIE interrupt bits. */
987         return (ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1;
988 }
989 
990 static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num,
991                                enum pch_ifreg dir)
992 {
993         u32 ie, enable;
994 
995         if (dir)
996                 ie = PCH_IF_MCONT_RXIE;
997         else
998                 ie = PCH_IF_MCONT_TXIE;
999 
1000         iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
1001         pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
1002 
1003         if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) &&
1004                         ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie))
1005                 enable = 1;
1006         else
1007                 enable = 0;
1008 
1009         return enable;
1010 }
1011 
1012 static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
1013                                        u32 buffer_num, int set)
1014 {
1015         iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
1016         pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
1017         iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
1018                   &priv->regs->ifregs[0].cmask);
1019         if (set)
1020                 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
1021                                   PCH_IF_MCONT_EOB);
1022         else
1023                 pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB);
1024 
1025         pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
1026 }
1027 
1028 static u32 pch_can_get_rx_buffer_link(struct pch_can_priv *priv, u32 buffer_num)
1029 {
1030         u32 link;
1031 
1032         iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
1033         pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
1034 
1035         if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB)
1036                 link = 0;
1037         else
1038                 link = 1;
1039         return link;
1040 }
1041 
1042 static int pch_can_get_buffer_status(struct pch_can_priv *priv)
1043 {
1044         return (ioread32(&priv->regs->treq1) & 0xffff) |
1045                (ioread32(&priv->regs->treq2) << 16);
1046 }
1047 
1048 static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
1049 {
1050         int i;
1051         int retval;
1052         u32 buf_stat;   /* Variable for reading the transmit buffer status. */
1053         int counter = PCH_COUNTER_LIMIT;
1054 
1055         struct net_device *dev = pci_get_drvdata(pdev);
1056         struct pch_can_priv *priv = netdev_priv(dev);
1057 
1058         /* Stop the CAN controller */
1059         pch_can_set_run_mode(priv, PCH_CAN_STOP);
1060 
1061         /* Indicate that we are aboutto/in suspend */
1062         priv->can.state = CAN_STATE_STOPPED;
1063 
1064         /* Waiting for all transmission to complete. */
1065         while (counter) {
1066                 buf_stat = pch_can_get_buffer_status(priv);
1067                 if (!buf_stat)
1068                         break;
1069                 counter--;
1070                 udelay(1);
1071         }
1072         if (!counter)
1073                 dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__);
1074 
1075         /* Save interrupt configuration and then disable them */
1076         priv->int_enables = pch_can_get_int_enables(priv);
1077         pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
1078 
1079         /* Save Tx buffer enable state */
1080         for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
1081                 priv->tx_enable[i - 1] = pch_can_get_rxtx_ir(priv, i,
1082                                                              PCH_TX_IFREG);
1083 
1084         /* Disable all Transmit buffers */
1085         pch_can_set_tx_all(priv, 0);
1086 
1087         /* Save Rx buffer enable state */
1088         for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
1089                 priv->rx_enable[i - 1] = pch_can_get_rxtx_ir(priv, i,
1090                                                              PCH_RX_IFREG);
1091                 priv->rx_link[i - 1] = pch_can_get_rx_buffer_link(priv, i);
1092         }
1093 
1094         /* Disable all Receive buffers */
1095         pch_can_set_rx_all(priv, 0);
1096         retval = pci_save_state(pdev);
1097         if (retval) {
1098                 dev_err(&pdev->dev, "pci_save_state failed.\n");
1099         } else {
1100                 pci_enable_wake(pdev, PCI_D3hot, 0);
1101                 pci_disable_device(pdev);
1102                 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1103         }
1104 
1105         return retval;
1106 }
1107 
1108 static int pch_can_resume(struct pci_dev *pdev)
1109 {
1110         int i;
1111         int retval;
1112         struct net_device *dev = pci_get_drvdata(pdev);
1113         struct pch_can_priv *priv = netdev_priv(dev);
1114 
1115         pci_set_power_state(pdev, PCI_D0);
1116         pci_restore_state(pdev);
1117         retval = pci_enable_device(pdev);
1118         if (retval) {
1119                 dev_err(&pdev->dev, "pci_enable_device failed.\n");
1120                 return retval;
1121         }
1122 
1123         pci_enable_wake(pdev, PCI_D3hot, 0);
1124 
1125         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1126 
1127         /* Disabling all interrupts. */
1128         pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
1129 
1130         /* Setting the CAN device in Stop Mode. */
1131         pch_can_set_run_mode(priv, PCH_CAN_STOP);
1132 
1133         /* Configuring the transmit and receive buffers. */
1134         pch_can_config_rx_tx_buffers(priv);
1135 
1136         /* Restore the CAN state */
1137         pch_set_bittiming(dev);
1138 
1139         /* Listen/Active */
1140         pch_can_set_optmode(priv);
1141 
1142         /* Enabling the transmit buffer. */
1143         for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
1144                 pch_can_set_rxtx(priv, i, priv->tx_enable[i - 1], PCH_TX_IFREG);
1145 
1146         /* Configuring the receive buffer and enabling them. */
1147         for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
1148                 /* Restore buffer link */
1149                 pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i - 1]);
1150 
1151                 /* Restore buffer enables */
1152                 pch_can_set_rxtx(priv, i, priv->rx_enable[i - 1], PCH_RX_IFREG);
1153         }
1154 
1155         /* Enable CAN Interrupts */
1156         pch_can_set_int_custom(priv);
1157 
1158         /* Restore Run Mode */
1159         pch_can_set_run_mode(priv, PCH_CAN_RUN);
1160 
1161         return retval;
1162 }
1163 #else
1164 #define pch_can_suspend NULL
1165 #define pch_can_resume NULL
1166 #endif
1167 
1168 static int pch_can_get_berr_counter(const struct net_device *dev,
1169                                     struct can_berr_counter *bec)
1170 {
1171         struct pch_can_priv *priv = netdev_priv(dev);
1172         u32 errc = ioread32(&priv->regs->errc);
1173 
1174         bec->txerr = errc & PCH_TEC;
1175         bec->rxerr = (errc & PCH_REC) >> 8;
1176 
1177         return 0;
1178 }
1179 
1180 static int pch_can_probe(struct pci_dev *pdev,
1181                                    const struct pci_device_id *id)
1182 {
1183         struct net_device *ndev;
1184         struct pch_can_priv *priv;
1185         int rc;
1186         void __iomem *addr;
1187 
1188         rc = pci_enable_device(pdev);
1189         if (rc) {
1190                 dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc);
1191                 goto probe_exit_endev;
1192         }
1193 
1194         rc = pci_request_regions(pdev, KBUILD_MODNAME);
1195         if (rc) {
1196                 dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc);
1197                 goto probe_exit_pcireq;
1198         }
1199 
1200         addr = pci_iomap(pdev, 1, 0);
1201         if (!addr) {
1202                 rc = -EIO;
1203                 dev_err(&pdev->dev, "Failed pci_iomap\n");
1204                 goto probe_exit_ipmap;
1205         }
1206 
1207         ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_END);
1208         if (!ndev) {
1209                 rc = -ENOMEM;
1210                 dev_err(&pdev->dev, "Failed alloc_candev\n");
1211                 goto probe_exit_alloc_candev;
1212         }
1213 
1214         priv = netdev_priv(ndev);
1215         priv->ndev = ndev;
1216         priv->regs = addr;
1217         priv->dev = pdev;
1218         priv->can.bittiming_const = &pch_can_bittiming_const;
1219         priv->can.do_set_mode = pch_can_do_set_mode;
1220         priv->can.do_get_berr_counter = pch_can_get_berr_counter;
1221         priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
1222                                        CAN_CTRLMODE_LOOPBACK;
1223         priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj */
1224 
1225         ndev->irq = pdev->irq;
1226         ndev->flags |= IFF_ECHO;
1227 
1228         pci_set_drvdata(pdev, ndev);
1229         SET_NETDEV_DEV(ndev, &pdev->dev);
1230         ndev->netdev_ops = &pch_can_netdev_ops;
1231         priv->can.clock.freq = PCH_CAN_CLK; /* Hz */
1232 
1233         netif_napi_add(ndev, &priv->napi, pch_can_poll, PCH_RX_OBJ_END);
1234 
1235         rc = pci_enable_msi(priv->dev);
1236         if (rc) {
1237                 netdev_err(ndev, "PCH CAN opened without MSI\n");
1238                 priv->use_msi = 0;
1239         } else {
1240                 netdev_err(ndev, "PCH CAN opened with MSI\n");
1241                 pci_set_master(pdev);
1242                 priv->use_msi = 1;
1243         }
1244 
1245         rc = register_candev(ndev);
1246         if (rc) {
1247                 dev_err(&pdev->dev, "Failed register_candev %d\n", rc);
1248                 goto probe_exit_reg_candev;
1249         }
1250 
1251         return 0;
1252 
1253 probe_exit_reg_candev:
1254         if (priv->use_msi)
1255                 pci_disable_msi(priv->dev);
1256         free_candev(ndev);
1257 probe_exit_alloc_candev:
1258         pci_iounmap(pdev, addr);
1259 probe_exit_ipmap:
1260         pci_release_regions(pdev);
1261 probe_exit_pcireq:
1262         pci_disable_device(pdev);
1263 probe_exit_endev:
1264         return rc;
1265 }
1266 
1267 static struct pci_driver pch_can_pci_driver = {
1268         .name = "pch_can",
1269         .id_table = pch_pci_tbl,
1270         .probe = pch_can_probe,
1271         .remove = pch_can_remove,
1272         .suspend = pch_can_suspend,
1273         .resume = pch_can_resume,
1274 };
1275 
1276 module_pci_driver(pch_can_pci_driver);
1277 
1278 MODULE_DESCRIPTION("Intel EG20T PCH CAN(Controller Area Network) Driver");
1279 MODULE_LICENSE("GPL v2");
1280 MODULE_VERSION("0.94");
1281 

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