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Linux/drivers/mtd/nand/txx9ndfmc.c

  1 /*
  2  * TXx9 NAND flash memory controller driver
  3  * Based on RBTX49xx patch from CELF patch archive.
  4  *
  5  * This program is free software; you can redistribute it and/or modify
  6  * it under the terms of the GNU General Public License version 2 as
  7  * published by the Free Software Foundation.
  8  *
  9  * (C) Copyright TOSHIBA CORPORATION 2004-2007
 10  * All Rights Reserved.
 11  */
 12 #include <linux/err.h>
 13 #include <linux/init.h>
 14 #include <linux/slab.h>
 15 #include <linux/module.h>
 16 #include <linux/platform_device.h>
 17 #include <linux/delay.h>
 18 #include <linux/mtd/mtd.h>
 19 #include <linux/mtd/nand.h>
 20 #include <linux/mtd/nand_ecc.h>
 21 #include <linux/mtd/partitions.h>
 22 #include <linux/io.h>
 23 #include <asm/txx9/ndfmc.h>
 24 
 25 /* TXX9 NDFMC Registers */
 26 #define TXX9_NDFDTR     0x00
 27 #define TXX9_NDFMCR     0x04
 28 #define TXX9_NDFSR      0x08
 29 #define TXX9_NDFISR     0x0c
 30 #define TXX9_NDFIMR     0x10
 31 #define TXX9_NDFSPR     0x14
 32 #define TXX9_NDFRSTR    0x18    /* not TX4939 */
 33 
 34 /* NDFMCR : NDFMC Mode Control */
 35 #define TXX9_NDFMCR_WE  0x80
 36 #define TXX9_NDFMCR_ECC_ALL     0x60
 37 #define TXX9_NDFMCR_ECC_RESET   0x60
 38 #define TXX9_NDFMCR_ECC_READ    0x40
 39 #define TXX9_NDFMCR_ECC_ON      0x20
 40 #define TXX9_NDFMCR_ECC_OFF     0x00
 41 #define TXX9_NDFMCR_CE  0x10
 42 #define TXX9_NDFMCR_BSPRT       0x04    /* TX4925/TX4926 only */
 43 #define TXX9_NDFMCR_ALE 0x02
 44 #define TXX9_NDFMCR_CLE 0x01
 45 /* TX4939 only */
 46 #define TXX9_NDFMCR_X16 0x0400
 47 #define TXX9_NDFMCR_DMAREQ_MASK 0x0300
 48 #define TXX9_NDFMCR_DMAREQ_NODMA        0x0000
 49 #define TXX9_NDFMCR_DMAREQ_128  0x0100
 50 #define TXX9_NDFMCR_DMAREQ_256  0x0200
 51 #define TXX9_NDFMCR_DMAREQ_512  0x0300
 52 #define TXX9_NDFMCR_CS_MASK     0x0c
 53 #define TXX9_NDFMCR_CS(ch)      ((ch) << 2)
 54 
 55 /* NDFMCR : NDFMC Status */
 56 #define TXX9_NDFSR_BUSY 0x80
 57 /* TX4939 only */
 58 #define TXX9_NDFSR_DMARUN       0x40
 59 
 60 /* NDFMCR : NDFMC Reset */
 61 #define TXX9_NDFRSTR_RST        0x01
 62 
 63 struct txx9ndfmc_priv {
 64         struct platform_device *dev;
 65         struct nand_chip chip;
 66         struct mtd_info mtd;
 67         int cs;
 68         const char *mtdname;
 69 };
 70 
 71 #define MAX_TXX9NDFMC_DEV       4
 72 struct txx9ndfmc_drvdata {
 73         struct mtd_info *mtds[MAX_TXX9NDFMC_DEV];
 74         void __iomem *base;
 75         unsigned char hold;     /* in gbusclock */
 76         unsigned char spw;      /* in gbusclock */
 77         struct nand_hw_control hw_control;
 78 };
 79 
 80 static struct platform_device *mtd_to_platdev(struct mtd_info *mtd)
 81 {
 82         struct nand_chip *chip = mtd->priv;
 83         struct txx9ndfmc_priv *txx9_priv = chip->priv;
 84         return txx9_priv->dev;
 85 }
 86 
 87 static void __iomem *ndregaddr(struct platform_device *dev, unsigned int reg)
 88 {
 89         struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
 90         struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev);
 91 
 92         return drvdata->base + (reg << plat->shift);
 93 }
 94 
 95 static u32 txx9ndfmc_read(struct platform_device *dev, unsigned int reg)
 96 {
 97         return __raw_readl(ndregaddr(dev, reg));
 98 }
 99 
100 static void txx9ndfmc_write(struct platform_device *dev,
101                             u32 val, unsigned int reg)
102 {
103         __raw_writel(val, ndregaddr(dev, reg));
104 }
105 
106 static uint8_t txx9ndfmc_read_byte(struct mtd_info *mtd)
107 {
108         struct platform_device *dev = mtd_to_platdev(mtd);
109 
110         return txx9ndfmc_read(dev, TXX9_NDFDTR);
111 }
112 
113 static void txx9ndfmc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
114                                 int len)
115 {
116         struct platform_device *dev = mtd_to_platdev(mtd);
117         void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
118         u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
119 
120         txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_WE, TXX9_NDFMCR);
121         while (len--)
122                 __raw_writel(*buf++, ndfdtr);
123         txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
124 }
125 
126 static void txx9ndfmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
127 {
128         struct platform_device *dev = mtd_to_platdev(mtd);
129         void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
130 
131         while (len--)
132                 *buf++ = __raw_readl(ndfdtr);
133 }
134 
135 static void txx9ndfmc_cmd_ctrl(struct mtd_info *mtd, int cmd,
136                                unsigned int ctrl)
137 {
138         struct nand_chip *chip = mtd->priv;
139         struct txx9ndfmc_priv *txx9_priv = chip->priv;
140         struct platform_device *dev = txx9_priv->dev;
141         struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev);
142 
143         if (ctrl & NAND_CTRL_CHANGE) {
144                 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
145 
146                 mcr &= ~(TXX9_NDFMCR_CLE | TXX9_NDFMCR_ALE | TXX9_NDFMCR_CE);
147                 mcr |= ctrl & NAND_CLE ? TXX9_NDFMCR_CLE : 0;
148                 mcr |= ctrl & NAND_ALE ? TXX9_NDFMCR_ALE : 0;
149                 /* TXX9_NDFMCR_CE bit is 0:high 1:low */
150                 mcr |= ctrl & NAND_NCE ? TXX9_NDFMCR_CE : 0;
151                 if (txx9_priv->cs >= 0 && (ctrl & NAND_NCE)) {
152                         mcr &= ~TXX9_NDFMCR_CS_MASK;
153                         mcr |= TXX9_NDFMCR_CS(txx9_priv->cs);
154                 }
155                 txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
156         }
157         if (cmd != NAND_CMD_NONE)
158                 txx9ndfmc_write(dev, cmd & 0xff, TXX9_NDFDTR);
159         if (plat->flags & NDFMC_PLAT_FLAG_DUMMYWRITE) {
160                 /* dummy write to update external latch */
161                 if ((ctrl & NAND_CTRL_CHANGE) && cmd == NAND_CMD_NONE)
162                         txx9ndfmc_write(dev, 0, TXX9_NDFDTR);
163         }
164         mmiowb();
165 }
166 
167 static int txx9ndfmc_dev_ready(struct mtd_info *mtd)
168 {
169         struct platform_device *dev = mtd_to_platdev(mtd);
170 
171         return !(txx9ndfmc_read(dev, TXX9_NDFSR) & TXX9_NDFSR_BUSY);
172 }
173 
174 static int txx9ndfmc_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
175                                    uint8_t *ecc_code)
176 {
177         struct platform_device *dev = mtd_to_platdev(mtd);
178         struct nand_chip *chip = mtd->priv;
179         int eccbytes;
180         u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
181 
182         mcr &= ~TXX9_NDFMCR_ECC_ALL;
183         txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
184         txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_READ, TXX9_NDFMCR);
185         for (eccbytes = chip->ecc.bytes; eccbytes > 0; eccbytes -= 3) {
186                 ecc_code[1] = txx9ndfmc_read(dev, TXX9_NDFDTR);
187                 ecc_code[0] = txx9ndfmc_read(dev, TXX9_NDFDTR);
188                 ecc_code[2] = txx9ndfmc_read(dev, TXX9_NDFDTR);
189                 ecc_code += 3;
190         }
191         txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
192         return 0;
193 }
194 
195 static int txx9ndfmc_correct_data(struct mtd_info *mtd, unsigned char *buf,
196                 unsigned char *read_ecc, unsigned char *calc_ecc)
197 {
198         struct nand_chip *chip = mtd->priv;
199         int eccsize;
200         int corrected = 0;
201         int stat;
202 
203         for (eccsize = chip->ecc.size; eccsize > 0; eccsize -= 256) {
204                 stat = __nand_correct_data(buf, read_ecc, calc_ecc, 256);
205                 if (stat < 0)
206                         return stat;
207                 corrected += stat;
208                 buf += 256;
209                 read_ecc += 3;
210                 calc_ecc += 3;
211         }
212         return corrected;
213 }
214 
215 static void txx9ndfmc_enable_hwecc(struct mtd_info *mtd, int mode)
216 {
217         struct platform_device *dev = mtd_to_platdev(mtd);
218         u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
219 
220         mcr &= ~TXX9_NDFMCR_ECC_ALL;
221         txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_RESET, TXX9_NDFMCR);
222         txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
223         txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_ON, TXX9_NDFMCR);
224 }
225 
226 static void txx9ndfmc_initialize(struct platform_device *dev)
227 {
228         struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev);
229         struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
230         int tmout = 100;
231 
232         if (plat->flags & NDFMC_PLAT_FLAG_NO_RSTR)
233                 ; /* no NDFRSTR.  Write to NDFSPR resets the NDFMC. */
234         else {
235                 /* reset NDFMC */
236                 txx9ndfmc_write(dev,
237                                 txx9ndfmc_read(dev, TXX9_NDFRSTR) |
238                                 TXX9_NDFRSTR_RST,
239                                 TXX9_NDFRSTR);
240                 while (txx9ndfmc_read(dev, TXX9_NDFRSTR) & TXX9_NDFRSTR_RST) {
241                         if (--tmout == 0) {
242                                 dev_err(&dev->dev, "reset failed.\n");
243                                 break;
244                         }
245                         udelay(1);
246                 }
247         }
248         /* setup Hold Time, Strobe Pulse Width */
249         txx9ndfmc_write(dev, (drvdata->hold << 4) | drvdata->spw, TXX9_NDFSPR);
250         txx9ndfmc_write(dev,
251                         (plat->flags & NDFMC_PLAT_FLAG_USE_BSPRT) ?
252                         TXX9_NDFMCR_BSPRT : 0, TXX9_NDFMCR);
253 }
254 
255 #define TXX9NDFMC_NS_TO_CYC(gbusclk, ns) \
256         DIV_ROUND_UP((ns) * DIV_ROUND_UP(gbusclk, 1000), 1000000)
257 
258 static int txx9ndfmc_nand_scan(struct mtd_info *mtd)
259 {
260         struct nand_chip *chip = mtd->priv;
261         int ret;
262 
263         ret = nand_scan_ident(mtd, 1, NULL);
264         if (!ret) {
265                 if (mtd->writesize >= 512) {
266                         /* Hardware ECC 6 byte ECC per 512 Byte data */
267                         chip->ecc.size = 512;
268                         chip->ecc.bytes = 6;
269                 }
270                 ret = nand_scan_tail(mtd);
271         }
272         return ret;
273 }
274 
275 static int __init txx9ndfmc_probe(struct platform_device *dev)
276 {
277         struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev);
278         int hold, spw;
279         int i;
280         struct txx9ndfmc_drvdata *drvdata;
281         unsigned long gbusclk = plat->gbus_clock;
282         struct resource *res;
283 
284         drvdata = devm_kzalloc(&dev->dev, sizeof(*drvdata), GFP_KERNEL);
285         if (!drvdata)
286                 return -ENOMEM;
287         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
288         drvdata->base = devm_ioremap_resource(&dev->dev, res);
289         if (IS_ERR(drvdata->base))
290                 return PTR_ERR(drvdata->base);
291 
292         hold = plat->hold ?: 20; /* tDH */
293         spw = plat->spw ?: 90; /* max(tREADID, tWP, tRP) */
294 
295         hold = TXX9NDFMC_NS_TO_CYC(gbusclk, hold);
296         spw = TXX9NDFMC_NS_TO_CYC(gbusclk, spw);
297         if (plat->flags & NDFMC_PLAT_FLAG_HOLDADD)
298                 hold -= 2;      /* actual hold time : (HOLD + 2) BUSCLK */
299         spw -= 1;       /* actual wait time : (SPW + 1) BUSCLK */
300         hold = clamp(hold, 1, 15);
301         drvdata->hold = hold;
302         spw = clamp(spw, 1, 15);
303         drvdata->spw = spw;
304         dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n",
305                  (gbusclk + 500000) / 1000000, hold, spw);
306 
307         spin_lock_init(&drvdata->hw_control.lock);
308         init_waitqueue_head(&drvdata->hw_control.wq);
309 
310         platform_set_drvdata(dev, drvdata);
311         txx9ndfmc_initialize(dev);
312 
313         for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
314                 struct txx9ndfmc_priv *txx9_priv;
315                 struct nand_chip *chip;
316                 struct mtd_info *mtd;
317 
318                 if (!(plat->ch_mask & (1 << i)))
319                         continue;
320                 txx9_priv = kzalloc(sizeof(struct txx9ndfmc_priv),
321                                     GFP_KERNEL);
322                 if (!txx9_priv)
323                         continue;
324                 chip = &txx9_priv->chip;
325                 mtd = &txx9_priv->mtd;
326                 mtd->owner = THIS_MODULE;
327 
328                 mtd->priv = chip;
329 
330                 chip->read_byte = txx9ndfmc_read_byte;
331                 chip->read_buf = txx9ndfmc_read_buf;
332                 chip->write_buf = txx9ndfmc_write_buf;
333                 chip->cmd_ctrl = txx9ndfmc_cmd_ctrl;
334                 chip->dev_ready = txx9ndfmc_dev_ready;
335                 chip->ecc.calculate = txx9ndfmc_calculate_ecc;
336                 chip->ecc.correct = txx9ndfmc_correct_data;
337                 chip->ecc.hwctl = txx9ndfmc_enable_hwecc;
338                 chip->ecc.mode = NAND_ECC_HW;
339                 /* txx9ndfmc_nand_scan will overwrite ecc.size and ecc.bytes */
340                 chip->ecc.size = 256;
341                 chip->ecc.bytes = 3;
342                 chip->ecc.strength = 1;
343                 chip->chip_delay = 100;
344                 chip->controller = &drvdata->hw_control;
345 
346                 chip->priv = txx9_priv;
347                 txx9_priv->dev = dev;
348 
349                 if (plat->ch_mask != 1) {
350                         txx9_priv->cs = i;
351                         txx9_priv->mtdname = kasprintf(GFP_KERNEL, "%s.%u",
352                                                        dev_name(&dev->dev), i);
353                 } else {
354                         txx9_priv->cs = -1;
355                         txx9_priv->mtdname = kstrdup(dev_name(&dev->dev),
356                                                      GFP_KERNEL);
357                 }
358                 if (!txx9_priv->mtdname) {
359                         kfree(txx9_priv);
360                         dev_err(&dev->dev, "Unable to allocate MTD name.\n");
361                         continue;
362                 }
363                 if (plat->wide_mask & (1 << i))
364                         chip->options |= NAND_BUSWIDTH_16;
365 
366                 if (txx9ndfmc_nand_scan(mtd)) {
367                         kfree(txx9_priv->mtdname);
368                         kfree(txx9_priv);
369                         continue;
370                 }
371                 mtd->name = txx9_priv->mtdname;
372 
373                 mtd_device_parse_register(mtd, NULL, NULL, NULL, 0);
374                 drvdata->mtds[i] = mtd;
375         }
376 
377         return 0;
378 }
379 
380 static int __exit txx9ndfmc_remove(struct platform_device *dev)
381 {
382         struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
383         int i;
384 
385         if (!drvdata)
386                 return 0;
387         for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
388                 struct mtd_info *mtd = drvdata->mtds[i];
389                 struct nand_chip *chip;
390                 struct txx9ndfmc_priv *txx9_priv;
391 
392                 if (!mtd)
393                         continue;
394                 chip = mtd->priv;
395                 txx9_priv = chip->priv;
396 
397                 nand_release(mtd);
398                 kfree(txx9_priv->mtdname);
399                 kfree(txx9_priv);
400         }
401         return 0;
402 }
403 
404 #ifdef CONFIG_PM
405 static int txx9ndfmc_resume(struct platform_device *dev)
406 {
407         if (platform_get_drvdata(dev))
408                 txx9ndfmc_initialize(dev);
409         return 0;
410 }
411 #else
412 #define txx9ndfmc_resume NULL
413 #endif
414 
415 static struct platform_driver txx9ndfmc_driver = {
416         .remove         = __exit_p(txx9ndfmc_remove),
417         .resume         = txx9ndfmc_resume,
418         .driver         = {
419                 .name   = "txx9ndfmc",
420                 .owner  = THIS_MODULE,
421         },
422 };
423 
424 module_platform_driver_probe(txx9ndfmc_driver, txx9ndfmc_probe);
425 
426 MODULE_LICENSE("GPL");
427 MODULE_DESCRIPTION("TXx9 SoC NAND flash controller driver");
428 MODULE_ALIAS("platform:txx9ndfmc");
429 

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