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Linux/drivers/mtd/nand/s3c2410.c

  1 /* linux/drivers/mtd/nand/s3c2410.c
  2  *
  3  * Copyright © 2004-2008 Simtec Electronics
  4  *      http://armlinux.simtec.co.uk/
  5  *      Ben Dooks <ben@simtec.co.uk>
  6  *
  7  * Samsung S3C2410/S3C2440/S3C2412 NAND driver
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License as published by
 11  * the Free Software Foundation; either version 2 of the License, or
 12  * (at your option) any later version.
 13  *
 14  * This program is distributed in the hope that it will be useful,
 15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 17  * GNU General Public License for more details.
 18  *
 19  * You should have received a copy of the GNU General Public License
 20  * along with this program; if not, write to the Free Software
 21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 22 */
 23 
 24 #define pr_fmt(fmt) "nand-s3c2410: " fmt
 25 
 26 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
 27 #define DEBUG
 28 #endif
 29 
 30 #include <linux/module.h>
 31 #include <linux/types.h>
 32 #include <linux/kernel.h>
 33 #include <linux/string.h>
 34 #include <linux/io.h>
 35 #include <linux/ioport.h>
 36 #include <linux/platform_device.h>
 37 #include <linux/delay.h>
 38 #include <linux/err.h>
 39 #include <linux/slab.h>
 40 #include <linux/clk.h>
 41 #include <linux/cpufreq.h>
 42 #include <linux/of.h>
 43 #include <linux/of_device.h>
 44 
 45 #include <linux/mtd/mtd.h>
 46 #include <linux/mtd/nand.h>
 47 #include <linux/mtd/nand_ecc.h>
 48 #include <linux/mtd/partitions.h>
 49 
 50 #include <linux/platform_data/mtd-nand-s3c2410.h>
 51 
 52 #define S3C2410_NFREG(x) (x)
 53 
 54 #define S3C2410_NFCONF          S3C2410_NFREG(0x00)
 55 #define S3C2410_NFCMD           S3C2410_NFREG(0x04)
 56 #define S3C2410_NFADDR          S3C2410_NFREG(0x08)
 57 #define S3C2410_NFDATA          S3C2410_NFREG(0x0C)
 58 #define S3C2410_NFSTAT          S3C2410_NFREG(0x10)
 59 #define S3C2410_NFECC           S3C2410_NFREG(0x14)
 60 #define S3C2440_NFCONT          S3C2410_NFREG(0x04)
 61 #define S3C2440_NFCMD           S3C2410_NFREG(0x08)
 62 #define S3C2440_NFADDR          S3C2410_NFREG(0x0C)
 63 #define S3C2440_NFDATA          S3C2410_NFREG(0x10)
 64 #define S3C2440_NFSTAT          S3C2410_NFREG(0x20)
 65 #define S3C2440_NFMECC0         S3C2410_NFREG(0x2C)
 66 #define S3C2412_NFSTAT          S3C2410_NFREG(0x28)
 67 #define S3C2412_NFMECC0         S3C2410_NFREG(0x34)
 68 #define S3C2410_NFCONF_EN               (1<<15)
 69 #define S3C2410_NFCONF_INITECC          (1<<12)
 70 #define S3C2410_NFCONF_nFCE             (1<<11)
 71 #define S3C2410_NFCONF_TACLS(x)         ((x)<<8)
 72 #define S3C2410_NFCONF_TWRPH0(x)        ((x)<<4)
 73 #define S3C2410_NFCONF_TWRPH1(x)        ((x)<<0)
 74 #define S3C2410_NFSTAT_BUSY             (1<<0)
 75 #define S3C2440_NFCONF_TACLS(x)         ((x)<<12)
 76 #define S3C2440_NFCONF_TWRPH0(x)        ((x)<<8)
 77 #define S3C2440_NFCONF_TWRPH1(x)        ((x)<<4)
 78 #define S3C2440_NFCONT_INITECC          (1<<4)
 79 #define S3C2440_NFCONT_nFCE             (1<<1)
 80 #define S3C2440_NFCONT_ENABLE           (1<<0)
 81 #define S3C2440_NFSTAT_READY            (1<<0)
 82 #define S3C2412_NFCONF_NANDBOOT         (1<<31)
 83 #define S3C2412_NFCONT_INIT_MAIN_ECC    (1<<5)
 84 #define S3C2412_NFCONT_nFCE0            (1<<1)
 85 #define S3C2412_NFSTAT_READY            (1<<0)
 86 
 87 /* new oob placement block for use with hardware ecc generation
 88  */
 89 static int s3c2410_ooblayout_ecc(struct mtd_info *mtd, int section,
 90                                  struct mtd_oob_region *oobregion)
 91 {
 92         if (section)
 93                 return -ERANGE;
 94 
 95         oobregion->offset = 0;
 96         oobregion->length = 3;
 97 
 98         return 0;
 99 }
100 
101 static int s3c2410_ooblayout_free(struct mtd_info *mtd, int section,
102                                   struct mtd_oob_region *oobregion)
103 {
104         if (section)
105                 return -ERANGE;
106 
107         oobregion->offset = 8;
108         oobregion->length = 8;
109 
110         return 0;
111 }
112 
113 static const struct mtd_ooblayout_ops s3c2410_ooblayout_ops = {
114         .ecc = s3c2410_ooblayout_ecc,
115         .free = s3c2410_ooblayout_free,
116 };
117 
118 /* controller and mtd information */
119 
120 struct s3c2410_nand_info;
121 
122 /**
123  * struct s3c2410_nand_mtd - driver MTD structure
124  * @mtd: The MTD instance to pass to the MTD layer.
125  * @chip: The NAND chip information.
126  * @set: The platform information supplied for this set of NAND chips.
127  * @info: Link back to the hardware information.
128  * @scan_res: The result from calling nand_scan_ident().
129 */
130 struct s3c2410_nand_mtd {
131         struct nand_chip                chip;
132         struct s3c2410_nand_set         *set;
133         struct s3c2410_nand_info        *info;
134         int                             scan_res;
135 };
136 
137 enum s3c_cpu_type {
138         TYPE_S3C2410,
139         TYPE_S3C2412,
140         TYPE_S3C2440,
141 };
142 
143 enum s3c_nand_clk_state {
144         CLOCK_DISABLE   = 0,
145         CLOCK_ENABLE,
146         CLOCK_SUSPEND,
147 };
148 
149 /* overview of the s3c2410 nand state */
150 
151 /**
152  * struct s3c2410_nand_info - NAND controller state.
153  * @mtds: An array of MTD instances on this controoler.
154  * @platform: The platform data for this board.
155  * @device: The platform device we bound to.
156  * @clk: The clock resource for this controller.
157  * @regs: The area mapped for the hardware registers.
158  * @sel_reg: Pointer to the register controlling the NAND selection.
159  * @sel_bit: The bit in @sel_reg to select the NAND chip.
160  * @mtd_count: The number of MTDs created from this controller.
161  * @save_sel: The contents of @sel_reg to be saved over suspend.
162  * @clk_rate: The clock rate from @clk.
163  * @clk_state: The current clock state.
164  * @cpu_type: The exact type of this controller.
165  */
166 struct s3c2410_nand_info {
167         /* mtd info */
168         struct nand_hw_control          controller;
169         struct s3c2410_nand_mtd         *mtds;
170         struct s3c2410_platform_nand    *platform;
171 
172         /* device info */
173         struct device                   *device;
174         struct clk                      *clk;
175         void __iomem                    *regs;
176         void __iomem                    *sel_reg;
177         int                             sel_bit;
178         int                             mtd_count;
179         unsigned long                   save_sel;
180         unsigned long                   clk_rate;
181         enum s3c_nand_clk_state         clk_state;
182 
183         enum s3c_cpu_type               cpu_type;
184 
185 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
186         struct notifier_block   freq_transition;
187 #endif
188 };
189 
190 struct s3c24XX_nand_devtype_data {
191         enum s3c_cpu_type type;
192 };
193 
194 static const struct s3c24XX_nand_devtype_data s3c2410_nand_devtype_data = {
195         .type = TYPE_S3C2410,
196 };
197 
198 static const struct s3c24XX_nand_devtype_data s3c2412_nand_devtype_data = {
199         .type = TYPE_S3C2412,
200 };
201 
202 static const struct s3c24XX_nand_devtype_data s3c2440_nand_devtype_data = {
203         .type = TYPE_S3C2440,
204 };
205 
206 /* conversion functions */
207 
208 static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
209 {
210         return container_of(mtd_to_nand(mtd), struct s3c2410_nand_mtd,
211                             chip);
212 }
213 
214 static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
215 {
216         return s3c2410_nand_mtd_toours(mtd)->info;
217 }
218 
219 static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
220 {
221         return platform_get_drvdata(dev);
222 }
223 
224 static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
225 {
226         return dev_get_platdata(&dev->dev);
227 }
228 
229 static inline int allow_clk_suspend(struct s3c2410_nand_info *info)
230 {
231 #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
232         return 1;
233 #else
234         return 0;
235 #endif
236 }
237 
238 /**
239  * s3c2410_nand_clk_set_state - Enable, disable or suspend NAND clock.
240  * @info: The controller instance.
241  * @new_state: State to which clock should be set.
242  */
243 static void s3c2410_nand_clk_set_state(struct s3c2410_nand_info *info,
244                 enum s3c_nand_clk_state new_state)
245 {
246         if (!allow_clk_suspend(info) && new_state == CLOCK_SUSPEND)
247                 return;
248 
249         if (info->clk_state == CLOCK_ENABLE) {
250                 if (new_state != CLOCK_ENABLE)
251                         clk_disable_unprepare(info->clk);
252         } else {
253                 if (new_state == CLOCK_ENABLE)
254                         clk_prepare_enable(info->clk);
255         }
256 
257         info->clk_state = new_state;
258 }
259 
260 /* timing calculations */
261 
262 #define NS_IN_KHZ 1000000
263 
264 /**
265  * s3c_nand_calc_rate - calculate timing data.
266  * @wanted: The cycle time in nanoseconds.
267  * @clk: The clock rate in kHz.
268  * @max: The maximum divider value.
269  *
270  * Calculate the timing value from the given parameters.
271  */
272 static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max)
273 {
274         int result;
275 
276         result = DIV_ROUND_UP((wanted * clk), NS_IN_KHZ);
277 
278         pr_debug("result %d from %ld, %d\n", result, clk, wanted);
279 
280         if (result > max) {
281                 pr_err("%d ns is too big for current clock rate %ld\n",
282                         wanted, clk);
283                 return -1;
284         }
285 
286         if (result < 1)
287                 result = 1;
288 
289         return result;
290 }
291 
292 #define to_ns(ticks, clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
293 
294 /* controller setup */
295 
296 /**
297  * s3c2410_nand_setrate - setup controller timing information.
298  * @info: The controller instance.
299  *
300  * Given the information supplied by the platform, calculate and set
301  * the necessary timing registers in the hardware to generate the
302  * necessary timing cycles to the hardware.
303  */
304 static int s3c2410_nand_setrate(struct s3c2410_nand_info *info)
305 {
306         struct s3c2410_platform_nand *plat = info->platform;
307         int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;
308         int tacls, twrph0, twrph1;
309         unsigned long clkrate = clk_get_rate(info->clk);
310         unsigned long uninitialized_var(set), cfg, uninitialized_var(mask);
311         unsigned long flags;
312 
313         /* calculate the timing information for the controller */
314 
315         info->clk_rate = clkrate;
316         clkrate /= 1000;        /* turn clock into kHz for ease of use */
317 
318         if (plat != NULL) {
319                 tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max);
320                 twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8);
321                 twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8);
322         } else {
323                 /* default timings */
324                 tacls = tacls_max;
325                 twrph0 = 8;
326                 twrph1 = 8;
327         }
328 
329         if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
330                 dev_err(info->device, "cannot get suitable timings\n");
331                 return -EINVAL;
332         }
333 
334         dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
335                 tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate),
336                                                 twrph1, to_ns(twrph1, clkrate));
337 
338         switch (info->cpu_type) {
339         case TYPE_S3C2410:
340                 mask = (S3C2410_NFCONF_TACLS(3) |
341                         S3C2410_NFCONF_TWRPH0(7) |
342                         S3C2410_NFCONF_TWRPH1(7));
343                 set = S3C2410_NFCONF_EN;
344                 set |= S3C2410_NFCONF_TACLS(tacls - 1);
345                 set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
346                 set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
347                 break;
348 
349         case TYPE_S3C2440:
350         case TYPE_S3C2412:
351                 mask = (S3C2440_NFCONF_TACLS(tacls_max - 1) |
352                         S3C2440_NFCONF_TWRPH0(7) |
353                         S3C2440_NFCONF_TWRPH1(7));
354 
355                 set = S3C2440_NFCONF_TACLS(tacls - 1);
356                 set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
357                 set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
358                 break;
359 
360         default:
361                 BUG();
362         }
363 
364         local_irq_save(flags);
365 
366         cfg = readl(info->regs + S3C2410_NFCONF);
367         cfg &= ~mask;
368         cfg |= set;
369         writel(cfg, info->regs + S3C2410_NFCONF);
370 
371         local_irq_restore(flags);
372 
373         dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
374 
375         return 0;
376 }
377 
378 /**
379  * s3c2410_nand_inithw - basic hardware initialisation
380  * @info: The hardware state.
381  *
382  * Do the basic initialisation of the hardware, using s3c2410_nand_setrate()
383  * to setup the hardware access speeds and set the controller to be enabled.
384 */
385 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info)
386 {
387         int ret;
388 
389         ret = s3c2410_nand_setrate(info);
390         if (ret < 0)
391                 return ret;
392 
393         switch (info->cpu_type) {
394         case TYPE_S3C2410:
395         default:
396                 break;
397 
398         case TYPE_S3C2440:
399         case TYPE_S3C2412:
400                 /* enable the controller and de-assert nFCE */
401 
402                 writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);
403         }
404 
405         return 0;
406 }
407 
408 /**
409  * s3c2410_nand_select_chip - select the given nand chip
410  * @mtd: The MTD instance for this chip.
411  * @chip: The chip number.
412  *
413  * This is called by the MTD layer to either select a given chip for the
414  * @mtd instance, or to indicate that the access has finished and the
415  * chip can be de-selected.
416  *
417  * The routine ensures that the nFCE line is correctly setup, and any
418  * platform specific selection code is called to route nFCE to the specific
419  * chip.
420  */
421 static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
422 {
423         struct s3c2410_nand_info *info;
424         struct s3c2410_nand_mtd *nmtd;
425         struct nand_chip *this = mtd_to_nand(mtd);
426         unsigned long cur;
427 
428         nmtd = nand_get_controller_data(this);
429         info = nmtd->info;
430 
431         if (chip != -1)
432                 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
433 
434         cur = readl(info->sel_reg);
435 
436         if (chip == -1) {
437                 cur |= info->sel_bit;
438         } else {
439                 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
440                         dev_err(info->device, "invalid chip %d\n", chip);
441                         return;
442                 }
443 
444                 if (info->platform != NULL) {
445                         if (info->platform->select_chip != NULL)
446                                 (info->platform->select_chip) (nmtd->set, chip);
447                 }
448 
449                 cur &= ~info->sel_bit;
450         }
451 
452         writel(cur, info->sel_reg);
453 
454         if (chip == -1)
455                 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
456 }
457 
458 /* s3c2410_nand_hwcontrol
459  *
460  * Issue command and address cycles to the chip
461 */
462 
463 static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd,
464                                    unsigned int ctrl)
465 {
466         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
467 
468         if (cmd == NAND_CMD_NONE)
469                 return;
470 
471         if (ctrl & NAND_CLE)
472                 writeb(cmd, info->regs + S3C2410_NFCMD);
473         else
474                 writeb(cmd, info->regs + S3C2410_NFADDR);
475 }
476 
477 /* command and control functions */
478 
479 static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd,
480                                    unsigned int ctrl)
481 {
482         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
483 
484         if (cmd == NAND_CMD_NONE)
485                 return;
486 
487         if (ctrl & NAND_CLE)
488                 writeb(cmd, info->regs + S3C2440_NFCMD);
489         else
490                 writeb(cmd, info->regs + S3C2440_NFADDR);
491 }
492 
493 /* s3c2410_nand_devready()
494  *
495  * returns 0 if the nand is busy, 1 if it is ready
496 */
497 
498 static int s3c2410_nand_devready(struct mtd_info *mtd)
499 {
500         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
501         return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
502 }
503 
504 static int s3c2440_nand_devready(struct mtd_info *mtd)
505 {
506         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
507         return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
508 }
509 
510 static int s3c2412_nand_devready(struct mtd_info *mtd)
511 {
512         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
513         return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY;
514 }
515 
516 /* ECC handling functions */
517 
518 static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
519                                      u_char *read_ecc, u_char *calc_ecc)
520 {
521         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
522         unsigned int diff0, diff1, diff2;
523         unsigned int bit, byte;
524 
525         pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc);
526 
527         diff0 = read_ecc[0] ^ calc_ecc[0];
528         diff1 = read_ecc[1] ^ calc_ecc[1];
529         diff2 = read_ecc[2] ^ calc_ecc[2];
530 
531         pr_debug("%s: rd %*phN calc %*phN diff %02x%02x%02x\n",
532                  __func__, 3, read_ecc, 3, calc_ecc,
533                  diff0, diff1, diff2);
534 
535         if (diff0 == 0 && diff1 == 0 && diff2 == 0)
536                 return 0;               /* ECC is ok */
537 
538         /* sometimes people do not think about using the ECC, so check
539          * to see if we have an 0xff,0xff,0xff read ECC and then ignore
540          * the error, on the assumption that this is an un-eccd page.
541          */
542         if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff
543             && info->platform->ignore_unset_ecc)
544                 return 0;
545 
546         /* Can we correct this ECC (ie, one row and column change).
547          * Note, this is similar to the 256 error code on smartmedia */
548 
549         if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 &&
550             ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 &&
551             ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) {
552                 /* calculate the bit position of the error */
553 
554                 bit  = ((diff2 >> 3) & 1) |
555                        ((diff2 >> 4) & 2) |
556                        ((diff2 >> 5) & 4);
557 
558                 /* calculate the byte position of the error */
559 
560                 byte = ((diff2 << 7) & 0x100) |
561                        ((diff1 << 0) & 0x80)  |
562                        ((diff1 << 1) & 0x40)  |
563                        ((diff1 << 2) & 0x20)  |
564                        ((diff1 << 3) & 0x10)  |
565                        ((diff0 >> 4) & 0x08)  |
566                        ((diff0 >> 3) & 0x04)  |
567                        ((diff0 >> 2) & 0x02)  |
568                        ((diff0 >> 1) & 0x01);
569 
570                 dev_dbg(info->device, "correcting error bit %d, byte %d\n",
571                         bit, byte);
572 
573                 dat[byte] ^= (1 << bit);
574                 return 1;
575         }
576 
577         /* if there is only one bit difference in the ECC, then
578          * one of only a row or column parity has changed, which
579          * means the error is most probably in the ECC itself */
580 
581         diff0 |= (diff1 << 8);
582         diff0 |= (diff2 << 16);
583 
584         /* equal to "(diff0 & ~(1 << __ffs(diff0)))" */
585         if ((diff0 & (diff0 - 1)) == 0)
586                 return 1;
587 
588         return -1;
589 }
590 
591 /* ECC functions
592  *
593  * These allow the s3c2410 and s3c2440 to use the controller's ECC
594  * generator block to ECC the data as it passes through]
595 */
596 
597 static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
598 {
599         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
600         unsigned long ctrl;
601 
602         ctrl = readl(info->regs + S3C2410_NFCONF);
603         ctrl |= S3C2410_NFCONF_INITECC;
604         writel(ctrl, info->regs + S3C2410_NFCONF);
605 }
606 
607 static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode)
608 {
609         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
610         unsigned long ctrl;
611 
612         ctrl = readl(info->regs + S3C2440_NFCONT);
613         writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC,
614                info->regs + S3C2440_NFCONT);
615 }
616 
617 static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode)
618 {
619         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
620         unsigned long ctrl;
621 
622         ctrl = readl(info->regs + S3C2440_NFCONT);
623         writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
624 }
625 
626 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
627                                       u_char *ecc_code)
628 {
629         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
630 
631         ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
632         ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
633         ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
634 
635         pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code);
636 
637         return 0;
638 }
639 
640 static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
641                                       u_char *ecc_code)
642 {
643         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
644         unsigned long ecc = readl(info->regs + S3C2412_NFMECC0);
645 
646         ecc_code[0] = ecc;
647         ecc_code[1] = ecc >> 8;
648         ecc_code[2] = ecc >> 16;
649 
650         pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code);
651 
652         return 0;
653 }
654 
655 static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
656                                       u_char *ecc_code)
657 {
658         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
659         unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
660 
661         ecc_code[0] = ecc;
662         ecc_code[1] = ecc >> 8;
663         ecc_code[2] = ecc >> 16;
664 
665         pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff);
666 
667         return 0;
668 }
669 
670 /* over-ride the standard functions for a little more speed. We can
671  * use read/write block to move the data buffers to/from the controller
672 */
673 
674 static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
675 {
676         struct nand_chip *this = mtd_to_nand(mtd);
677         readsb(this->IO_ADDR_R, buf, len);
678 }
679 
680 static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
681 {
682         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
683 
684         readsl(info->regs + S3C2440_NFDATA, buf, len >> 2);
685 
686         /* cleanup if we've got less than a word to do */
687         if (len & 3) {
688                 buf += len & ~3;
689 
690                 for (; len & 3; len--)
691                         *buf++ = readb(info->regs + S3C2440_NFDATA);
692         }
693 }
694 
695 static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
696                                    int len)
697 {
698         struct nand_chip *this = mtd_to_nand(mtd);
699         writesb(this->IO_ADDR_W, buf, len);
700 }
701 
702 static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
703                                    int len)
704 {
705         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
706 
707         writesl(info->regs + S3C2440_NFDATA, buf, len >> 2);
708 
709         /* cleanup any fractional write */
710         if (len & 3) {
711                 buf += len & ~3;
712 
713                 for (; len & 3; len--, buf++)
714                         writeb(*buf, info->regs + S3C2440_NFDATA);
715         }
716 }
717 
718 /* cpufreq driver support */
719 
720 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
721 
722 static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb,
723                                           unsigned long val, void *data)
724 {
725         struct s3c2410_nand_info *info;
726         unsigned long newclk;
727 
728         info = container_of(nb, struct s3c2410_nand_info, freq_transition);
729         newclk = clk_get_rate(info->clk);
730 
731         if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) ||
732             (val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) {
733                 s3c2410_nand_setrate(info);
734         }
735 
736         return 0;
737 }
738 
739 static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
740 {
741         info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition;
742 
743         return cpufreq_register_notifier(&info->freq_transition,
744                                          CPUFREQ_TRANSITION_NOTIFIER);
745 }
746 
747 static inline void
748 s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
749 {
750         cpufreq_unregister_notifier(&info->freq_transition,
751                                     CPUFREQ_TRANSITION_NOTIFIER);
752 }
753 
754 #else
755 static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
756 {
757         return 0;
758 }
759 
760 static inline void
761 s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
762 {
763 }
764 #endif
765 
766 /* device management functions */
767 
768 static int s3c24xx_nand_remove(struct platform_device *pdev)
769 {
770         struct s3c2410_nand_info *info = to_nand_info(pdev);
771 
772         if (info == NULL)
773                 return 0;
774 
775         s3c2410_nand_cpufreq_deregister(info);
776 
777         /* Release all our mtds  and their partitions, then go through
778          * freeing the resources used
779          */
780 
781         if (info->mtds != NULL) {
782                 struct s3c2410_nand_mtd *ptr = info->mtds;
783                 int mtdno;
784 
785                 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
786                         pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
787                         nand_release(nand_to_mtd(&ptr->chip));
788                 }
789         }
790 
791         /* free the common resources */
792 
793         if (!IS_ERR(info->clk))
794                 s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);
795 
796         return 0;
797 }
798 
799 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
800                                       struct s3c2410_nand_mtd *mtd,
801                                       struct s3c2410_nand_set *set)
802 {
803         if (set) {
804                 struct mtd_info *mtdinfo = nand_to_mtd(&mtd->chip);
805 
806                 mtdinfo->name = set->name;
807 
808                 return mtd_device_parse_register(mtdinfo, NULL, NULL,
809                                          set->partitions, set->nr_partitions);
810         }
811 
812         return -ENODEV;
813 }
814 
815 static int s3c2410_nand_setup_data_interface(struct mtd_info *mtd,
816                                         const struct nand_data_interface *conf,
817                                         bool check_only)
818 {
819         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
820         struct s3c2410_platform_nand *pdata = info->platform;
821         const struct nand_sdr_timings *timings;
822         int tacls;
823 
824         timings = nand_get_sdr_timings(conf);
825         if (IS_ERR(timings))
826                 return -ENOTSUPP;
827 
828         tacls = timings->tCLS_min - timings->tWP_min;
829         if (tacls < 0)
830                 tacls = 0;
831 
832         pdata->tacls  = DIV_ROUND_UP(tacls, 1000);
833         pdata->twrph0 = DIV_ROUND_UP(timings->tWP_min, 1000);
834         pdata->twrph1 = DIV_ROUND_UP(timings->tCLH_min, 1000);
835 
836         return s3c2410_nand_setrate(info);
837 }
838 
839 /**
840  * s3c2410_nand_init_chip - initialise a single instance of an chip
841  * @info: The base NAND controller the chip is on.
842  * @nmtd: The new controller MTD instance to fill in.
843  * @set: The information passed from the board specific platform data.
844  *
845  * Initialise the given @nmtd from the information in @info and @set. This
846  * readies the structure for use with the MTD layer functions by ensuring
847  * all pointers are setup and the necessary control routines selected.
848  */
849 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
850                                    struct s3c2410_nand_mtd *nmtd,
851                                    struct s3c2410_nand_set *set)
852 {
853         struct device_node *np = info->device->of_node;
854         struct nand_chip *chip = &nmtd->chip;
855         void __iomem *regs = info->regs;
856 
857         nand_set_flash_node(chip, set->of_node);
858 
859         chip->write_buf    = s3c2410_nand_write_buf;
860         chip->read_buf     = s3c2410_nand_read_buf;
861         chip->select_chip  = s3c2410_nand_select_chip;
862         chip->chip_delay   = 50;
863         nand_set_controller_data(chip, nmtd);
864         chip->options      = set->options;
865         chip->controller   = &info->controller;
866 
867         /*
868          * let's keep behavior unchanged for legacy boards booting via pdata and
869          * auto-detect timings only when booting with a device tree.
870          */
871         if (np)
872                 chip->setup_data_interface = s3c2410_nand_setup_data_interface;
873 
874         switch (info->cpu_type) {
875         case TYPE_S3C2410:
876                 chip->IO_ADDR_W = regs + S3C2410_NFDATA;
877                 info->sel_reg   = regs + S3C2410_NFCONF;
878                 info->sel_bit   = S3C2410_NFCONF_nFCE;
879                 chip->cmd_ctrl  = s3c2410_nand_hwcontrol;
880                 chip->dev_ready = s3c2410_nand_devready;
881                 break;
882 
883         case TYPE_S3C2440:
884                 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
885                 info->sel_reg   = regs + S3C2440_NFCONT;
886                 info->sel_bit   = S3C2440_NFCONT_nFCE;
887                 chip->cmd_ctrl  = s3c2440_nand_hwcontrol;
888                 chip->dev_ready = s3c2440_nand_devready;
889                 chip->read_buf  = s3c2440_nand_read_buf;
890                 chip->write_buf = s3c2440_nand_write_buf;
891                 break;
892 
893         case TYPE_S3C2412:
894                 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
895                 info->sel_reg   = regs + S3C2440_NFCONT;
896                 info->sel_bit   = S3C2412_NFCONT_nFCE0;
897                 chip->cmd_ctrl  = s3c2440_nand_hwcontrol;
898                 chip->dev_ready = s3c2412_nand_devready;
899 
900                 if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT)
901                         dev_info(info->device, "System booted from NAND\n");
902 
903                 break;
904         }
905 
906         chip->IO_ADDR_R = chip->IO_ADDR_W;
907 
908         nmtd->info         = info;
909         nmtd->set          = set;
910 
911         chip->ecc.mode = info->platform->ecc_mode;
912 
913         /*
914          * If you use u-boot BBT creation code, specifying this flag will
915          * let the kernel fish out the BBT from the NAND.
916          */
917         if (set->flash_bbt)
918                 chip->bbt_options |= NAND_BBT_USE_FLASH;
919 }
920 
921 /**
922  * s3c2410_nand_update_chip - post probe update
923  * @info: The controller instance.
924  * @nmtd: The driver version of the MTD instance.
925  *
926  * This routine is called after the chip probe has successfully completed
927  * and the relevant per-chip information updated. This call ensure that
928  * we update the internal state accordingly.
929  *
930  * The internal state is currently limited to the ECC state information.
931 */
932 static int s3c2410_nand_update_chip(struct s3c2410_nand_info *info,
933                                     struct s3c2410_nand_mtd *nmtd)
934 {
935         struct nand_chip *chip = &nmtd->chip;
936 
937         switch (chip->ecc.mode) {
938 
939         case NAND_ECC_NONE:
940                 dev_info(info->device, "ECC disabled\n");
941                 break;
942 
943         case NAND_ECC_SOFT:
944                 /*
945                  * This driver expects Hamming based ECC when ecc_mode is set
946                  * to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_HAMMING to
947                  * avoid adding an extra ecc_algo field to
948                  * s3c2410_platform_nand.
949                  */
950                 chip->ecc.algo = NAND_ECC_HAMMING;
951                 dev_info(info->device, "soft ECC\n");
952                 break;
953 
954         case NAND_ECC_HW:
955                 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
956                 chip->ecc.correct   = s3c2410_nand_correct_data;
957                 chip->ecc.strength  = 1;
958 
959                 switch (info->cpu_type) {
960                 case TYPE_S3C2410:
961                         chip->ecc.hwctl     = s3c2410_nand_enable_hwecc;
962                         chip->ecc.calculate = s3c2410_nand_calculate_ecc;
963                         break;
964 
965                 case TYPE_S3C2412:
966                         chip->ecc.hwctl     = s3c2412_nand_enable_hwecc;
967                         chip->ecc.calculate = s3c2412_nand_calculate_ecc;
968                         break;
969 
970                 case TYPE_S3C2440:
971                         chip->ecc.hwctl     = s3c2440_nand_enable_hwecc;
972                         chip->ecc.calculate = s3c2440_nand_calculate_ecc;
973                         break;
974                 }
975 
976                 dev_dbg(info->device, "chip %p => page shift %d\n",
977                         chip, chip->page_shift);
978 
979                 /* change the behaviour depending on whether we are using
980                  * the large or small page nand device */
981                 if (chip->page_shift > 10) {
982                         chip->ecc.size      = 256;
983                         chip->ecc.bytes     = 3;
984                 } else {
985                         chip->ecc.size      = 512;
986                         chip->ecc.bytes     = 3;
987                         mtd_set_ooblayout(nand_to_mtd(chip),
988                                           &s3c2410_ooblayout_ops);
989                 }
990 
991                 dev_info(info->device, "hardware ECC\n");
992                 break;
993 
994         default:
995                 dev_err(info->device, "invalid ECC mode!\n");
996                 return -EINVAL;
997         }
998 
999         if (chip->bbt_options & NAND_BBT_USE_FLASH)
1000                 chip->options |= NAND_SKIP_BBTSCAN;
1001 
1002         return 0;
1003 }
1004 
1005 static const struct of_device_id s3c24xx_nand_dt_ids[] = {
1006         {
1007                 .compatible = "samsung,s3c2410-nand",
1008                 .data = &s3c2410_nand_devtype_data,
1009         }, {
1010                 /* also compatible with s3c6400 */
1011                 .compatible = "samsung,s3c2412-nand",
1012                 .data = &s3c2412_nand_devtype_data,
1013         }, {
1014                 .compatible = "samsung,s3c2440-nand",
1015                 .data = &s3c2440_nand_devtype_data,
1016         },
1017         { /* sentinel */ }
1018 };
1019 MODULE_DEVICE_TABLE(of, s3c24xx_nand_dt_ids);
1020 
1021 static int s3c24xx_nand_probe_dt(struct platform_device *pdev)
1022 {
1023         const struct s3c24XX_nand_devtype_data *devtype_data;
1024         struct s3c2410_platform_nand *pdata;
1025         struct s3c2410_nand_info *info = platform_get_drvdata(pdev);
1026         struct device_node *np = pdev->dev.of_node, *child;
1027         struct s3c2410_nand_set *sets;
1028 
1029         devtype_data = of_device_get_match_data(&pdev->dev);
1030         if (!devtype_data)
1031                 return -ENODEV;
1032 
1033         info->cpu_type = devtype_data->type;
1034 
1035         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1036         if (!pdata)
1037                 return -ENOMEM;
1038 
1039         pdev->dev.platform_data = pdata;
1040 
1041         pdata->nr_sets = of_get_child_count(np);
1042         if (!pdata->nr_sets)
1043                 return 0;
1044 
1045         sets = devm_kzalloc(&pdev->dev, sizeof(*sets) * pdata->nr_sets,
1046                             GFP_KERNEL);
1047         if (!sets)
1048                 return -ENOMEM;
1049 
1050         pdata->sets = sets;
1051 
1052         for_each_available_child_of_node(np, child) {
1053                 sets->name = (char *)child->name;
1054                 sets->of_node = child;
1055                 sets->nr_chips = 1;
1056 
1057                 of_node_get(child);
1058 
1059                 sets++;
1060         }
1061 
1062         return 0;
1063 }
1064 
1065 static int s3c24xx_nand_probe_pdata(struct platform_device *pdev)
1066 {
1067         struct s3c2410_nand_info *info = platform_get_drvdata(pdev);
1068 
1069         info->cpu_type = platform_get_device_id(pdev)->driver_data;
1070 
1071         return 0;
1072 }
1073 
1074 /* s3c24xx_nand_probe
1075  *
1076  * called by device layer when it finds a device matching
1077  * one our driver can handled. This code checks to see if
1078  * it can allocate all necessary resources then calls the
1079  * nand layer to look for devices
1080 */
1081 static int s3c24xx_nand_probe(struct platform_device *pdev)
1082 {
1083         struct s3c2410_platform_nand *plat;
1084         struct s3c2410_nand_info *info;
1085         struct s3c2410_nand_mtd *nmtd;
1086         struct s3c2410_nand_set *sets;
1087         struct resource *res;
1088         int err = 0;
1089         int size;
1090         int nr_sets;
1091         int setno;
1092 
1093         info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1094         if (info == NULL) {
1095                 err = -ENOMEM;
1096                 goto exit_error;
1097         }
1098 
1099         platform_set_drvdata(pdev, info);
1100 
1101         nand_hw_control_init(&info->controller);
1102 
1103         /* get the clock source and enable it */
1104 
1105         info->clk = devm_clk_get(&pdev->dev, "nand");
1106         if (IS_ERR(info->clk)) {
1107                 dev_err(&pdev->dev, "failed to get clock\n");
1108                 err = -ENOENT;
1109                 goto exit_error;
1110         }
1111 
1112         s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
1113 
1114         if (pdev->dev.of_node)
1115                 err = s3c24xx_nand_probe_dt(pdev);
1116         else
1117                 err = s3c24xx_nand_probe_pdata(pdev);
1118 
1119         if (err)
1120                 goto exit_error;
1121 
1122         plat = to_nand_plat(pdev);
1123 
1124         /* allocate and map the resource */
1125 
1126         /* currently we assume we have the one resource */
1127         res = pdev->resource;
1128         size = resource_size(res);
1129 
1130         info->device    = &pdev->dev;
1131         info->platform  = plat;
1132 
1133         info->regs = devm_ioremap_resource(&pdev->dev, res);
1134         if (IS_ERR(info->regs)) {
1135                 err = PTR_ERR(info->regs);
1136                 goto exit_error;
1137         }
1138 
1139         dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
1140 
1141         sets = (plat != NULL) ? plat->sets : NULL;
1142         nr_sets = (plat != NULL) ? plat->nr_sets : 1;
1143 
1144         info->mtd_count = nr_sets;
1145 
1146         /* allocate our information */
1147 
1148         size = nr_sets * sizeof(*info->mtds);
1149         info->mtds = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1150         if (info->mtds == NULL) {
1151                 err = -ENOMEM;
1152                 goto exit_error;
1153         }
1154 
1155         /* initialise all possible chips */
1156 
1157         nmtd = info->mtds;
1158 
1159         for (setno = 0; setno < nr_sets; setno++, nmtd++) {
1160                 struct mtd_info *mtd = nand_to_mtd(&nmtd->chip);
1161 
1162                 pr_debug("initialising set %d (%p, info %p)\n",
1163                          setno, nmtd, info);
1164 
1165                 mtd->dev.parent = &pdev->dev;
1166                 s3c2410_nand_init_chip(info, nmtd, sets);
1167 
1168                 nmtd->scan_res = nand_scan_ident(mtd,
1169                                                  (sets) ? sets->nr_chips : 1,
1170                                                  NULL);
1171 
1172                 if (nmtd->scan_res == 0) {
1173                         err = s3c2410_nand_update_chip(info, nmtd);
1174                         if (err < 0)
1175                                 goto exit_error;
1176                         nand_scan_tail(mtd);
1177                         s3c2410_nand_add_partition(info, nmtd, sets);
1178                 }
1179 
1180                 if (sets != NULL)
1181                         sets++;
1182         }
1183 
1184         /* initialise the hardware */
1185         err = s3c2410_nand_inithw(info);
1186         if (err != 0)
1187                 goto exit_error;
1188 
1189         err = s3c2410_nand_cpufreq_register(info);
1190         if (err < 0) {
1191                 dev_err(&pdev->dev, "failed to init cpufreq support\n");
1192                 goto exit_error;
1193         }
1194 
1195         if (allow_clk_suspend(info)) {
1196                 dev_info(&pdev->dev, "clock idle support enabled\n");
1197                 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
1198         }
1199 
1200         return 0;
1201 
1202  exit_error:
1203         s3c24xx_nand_remove(pdev);
1204 
1205         if (err == 0)
1206                 err = -EINVAL;
1207         return err;
1208 }
1209 
1210 /* PM Support */
1211 #ifdef CONFIG_PM
1212 
1213 static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
1214 {
1215         struct s3c2410_nand_info *info = platform_get_drvdata(dev);
1216 
1217         if (info) {
1218                 info->save_sel = readl(info->sel_reg);
1219 
1220                 /* For the moment, we must ensure nFCE is high during
1221                  * the time we are suspended. This really should be
1222                  * handled by suspending the MTDs we are using, but
1223                  * that is currently not the case. */
1224 
1225                 writel(info->save_sel | info->sel_bit, info->sel_reg);
1226 
1227                 s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);
1228         }
1229 
1230         return 0;
1231 }
1232 
1233 static int s3c24xx_nand_resume(struct platform_device *dev)
1234 {
1235         struct s3c2410_nand_info *info = platform_get_drvdata(dev);
1236         unsigned long sel;
1237 
1238         if (info) {
1239                 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
1240                 s3c2410_nand_inithw(info);
1241 
1242                 /* Restore the state of the nFCE line. */
1243 
1244                 sel = readl(info->sel_reg);
1245                 sel &= ~info->sel_bit;
1246                 sel |= info->save_sel & info->sel_bit;
1247                 writel(sel, info->sel_reg);
1248 
1249                 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
1250         }
1251 
1252         return 0;
1253 }
1254 
1255 #else
1256 #define s3c24xx_nand_suspend NULL
1257 #define s3c24xx_nand_resume NULL
1258 #endif
1259 
1260 /* driver device registration */
1261 
1262 static const struct platform_device_id s3c24xx_driver_ids[] = {
1263         {
1264                 .name           = "s3c2410-nand",
1265                 .driver_data    = TYPE_S3C2410,
1266         }, {
1267                 .name           = "s3c2440-nand",
1268                 .driver_data    = TYPE_S3C2440,
1269         }, {
1270                 .name           = "s3c2412-nand",
1271                 .driver_data    = TYPE_S3C2412,
1272         }, {
1273                 .name           = "s3c6400-nand",
1274                 .driver_data    = TYPE_S3C2412, /* compatible with 2412 */
1275         },
1276         { }
1277 };
1278 
1279 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
1280 
1281 static struct platform_driver s3c24xx_nand_driver = {
1282         .probe          = s3c24xx_nand_probe,
1283         .remove         = s3c24xx_nand_remove,
1284         .suspend        = s3c24xx_nand_suspend,
1285         .resume         = s3c24xx_nand_resume,
1286         .id_table       = s3c24xx_driver_ids,
1287         .driver         = {
1288                 .name   = "s3c24xx-nand",
1289                 .of_match_table = s3c24xx_nand_dt_ids,
1290         },
1291 };
1292 
1293 module_platform_driver(s3c24xx_nand_driver);
1294 
1295 MODULE_LICENSE("GPL");
1296 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1297 MODULE_DESCRIPTION("S3C24XX MTD NAND driver");
1298 

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