Version:  2.0.40 2.2.26 2.4.37 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8

Linux/drivers/mtd/nand/omap2.c

  1 /*
  2  * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
  3  * Copyright © 2004 Micron Technology Inc.
  4  * Copyright © 2004 David Brownell
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License version 2 as
  8  * published by the Free Software Foundation.
  9  */
 10 
 11 #include <linux/platform_device.h>
 12 #include <linux/dmaengine.h>
 13 #include <linux/dma-mapping.h>
 14 #include <linux/delay.h>
 15 #include <linux/gpio/consumer.h>
 16 #include <linux/module.h>
 17 #include <linux/interrupt.h>
 18 #include <linux/jiffies.h>
 19 #include <linux/sched.h>
 20 #include <linux/mtd/mtd.h>
 21 #include <linux/mtd/nand.h>
 22 #include <linux/mtd/partitions.h>
 23 #include <linux/omap-dma.h>
 24 #include <linux/io.h>
 25 #include <linux/slab.h>
 26 #include <linux/of.h>
 27 #include <linux/of_device.h>
 28 
 29 #include <linux/mtd/nand_bch.h>
 30 #include <linux/platform_data/elm.h>
 31 
 32 #include <linux/omap-gpmc.h>
 33 #include <linux/platform_data/mtd-nand-omap2.h>
 34 
 35 #define DRIVER_NAME     "omap2-nand"
 36 #define OMAP_NAND_TIMEOUT_MS    5000
 37 
 38 #define NAND_Ecc_P1e            (1 << 0)
 39 #define NAND_Ecc_P2e            (1 << 1)
 40 #define NAND_Ecc_P4e            (1 << 2)
 41 #define NAND_Ecc_P8e            (1 << 3)
 42 #define NAND_Ecc_P16e           (1 << 4)
 43 #define NAND_Ecc_P32e           (1 << 5)
 44 #define NAND_Ecc_P64e           (1 << 6)
 45 #define NAND_Ecc_P128e          (1 << 7)
 46 #define NAND_Ecc_P256e          (1 << 8)
 47 #define NAND_Ecc_P512e          (1 << 9)
 48 #define NAND_Ecc_P1024e         (1 << 10)
 49 #define NAND_Ecc_P2048e         (1 << 11)
 50 
 51 #define NAND_Ecc_P1o            (1 << 16)
 52 #define NAND_Ecc_P2o            (1 << 17)
 53 #define NAND_Ecc_P4o            (1 << 18)
 54 #define NAND_Ecc_P8o            (1 << 19)
 55 #define NAND_Ecc_P16o           (1 << 20)
 56 #define NAND_Ecc_P32o           (1 << 21)
 57 #define NAND_Ecc_P64o           (1 << 22)
 58 #define NAND_Ecc_P128o          (1 << 23)
 59 #define NAND_Ecc_P256o          (1 << 24)
 60 #define NAND_Ecc_P512o          (1 << 25)
 61 #define NAND_Ecc_P1024o         (1 << 26)
 62 #define NAND_Ecc_P2048o         (1 << 27)
 63 
 64 #define TF(value)       (value ? 1 : 0)
 65 
 66 #define P2048e(a)       (TF(a & NAND_Ecc_P2048e)        << 0)
 67 #define P2048o(a)       (TF(a & NAND_Ecc_P2048o)        << 1)
 68 #define P1e(a)          (TF(a & NAND_Ecc_P1e)           << 2)
 69 #define P1o(a)          (TF(a & NAND_Ecc_P1o)           << 3)
 70 #define P2e(a)          (TF(a & NAND_Ecc_P2e)           << 4)
 71 #define P2o(a)          (TF(a & NAND_Ecc_P2o)           << 5)
 72 #define P4e(a)          (TF(a & NAND_Ecc_P4e)           << 6)
 73 #define P4o(a)          (TF(a & NAND_Ecc_P4o)           << 7)
 74 
 75 #define P8e(a)          (TF(a & NAND_Ecc_P8e)           << 0)
 76 #define P8o(a)          (TF(a & NAND_Ecc_P8o)           << 1)
 77 #define P16e(a)         (TF(a & NAND_Ecc_P16e)          << 2)
 78 #define P16o(a)         (TF(a & NAND_Ecc_P16o)          << 3)
 79 #define P32e(a)         (TF(a & NAND_Ecc_P32e)          << 4)
 80 #define P32o(a)         (TF(a & NAND_Ecc_P32o)          << 5)
 81 #define P64e(a)         (TF(a & NAND_Ecc_P64e)          << 6)
 82 #define P64o(a)         (TF(a & NAND_Ecc_P64o)          << 7)
 83 
 84 #define P128e(a)        (TF(a & NAND_Ecc_P128e)         << 0)
 85 #define P128o(a)        (TF(a & NAND_Ecc_P128o)         << 1)
 86 #define P256e(a)        (TF(a & NAND_Ecc_P256e)         << 2)
 87 #define P256o(a)        (TF(a & NAND_Ecc_P256o)         << 3)
 88 #define P512e(a)        (TF(a & NAND_Ecc_P512e)         << 4)
 89 #define P512o(a)        (TF(a & NAND_Ecc_P512o)         << 5)
 90 #define P1024e(a)       (TF(a & NAND_Ecc_P1024e)        << 6)
 91 #define P1024o(a)       (TF(a & NAND_Ecc_P1024o)        << 7)
 92 
 93 #define P8e_s(a)        (TF(a & NAND_Ecc_P8e)           << 0)
 94 #define P8o_s(a)        (TF(a & NAND_Ecc_P8o)           << 1)
 95 #define P16e_s(a)       (TF(a & NAND_Ecc_P16e)          << 2)
 96 #define P16o_s(a)       (TF(a & NAND_Ecc_P16o)          << 3)
 97 #define P1e_s(a)        (TF(a & NAND_Ecc_P1e)           << 4)
 98 #define P1o_s(a)        (TF(a & NAND_Ecc_P1o)           << 5)
 99 #define P2e_s(a)        (TF(a & NAND_Ecc_P2e)           << 6)
100 #define P2o_s(a)        (TF(a & NAND_Ecc_P2o)           << 7)
101 
102 #define P4e_s(a)        (TF(a & NAND_Ecc_P4e)           << 0)
103 #define P4o_s(a)        (TF(a & NAND_Ecc_P4o)           << 1)
104 
105 #define PREFETCH_CONFIG1_CS_SHIFT       24
106 #define ECC_CONFIG_CS_SHIFT             1
107 #define CS_MASK                         0x7
108 #define ENABLE_PREFETCH                 (0x1 << 7)
109 #define DMA_MPU_MODE_SHIFT              2
110 #define ECCSIZE0_SHIFT                  12
111 #define ECCSIZE1_SHIFT                  22
112 #define ECC1RESULTSIZE                  0x1
113 #define ECCCLEAR                        0x100
114 #define ECC1                            0x1
115 #define PREFETCH_FIFOTHRESHOLD_MAX      0x40
116 #define PREFETCH_FIFOTHRESHOLD(val)     ((val) << 8)
117 #define PREFETCH_STATUS_COUNT(val)      (val & 0x00003fff)
118 #define PREFETCH_STATUS_FIFO_CNT(val)   ((val >> 24) & 0x7F)
119 #define STATUS_BUFF_EMPTY               0x00000001
120 
121 #define SECTOR_BYTES            512
122 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
123 #define BCH4_BIT_PAD            4
124 
125 /* GPMC ecc engine settings for read */
126 #define BCH_WRAPMODE_1          1       /* BCH wrap mode 1 */
127 #define BCH8R_ECC_SIZE0         0x1a    /* ecc_size0 = 26 */
128 #define BCH8R_ECC_SIZE1         0x2     /* ecc_size1 = 2 */
129 #define BCH4R_ECC_SIZE0         0xd     /* ecc_size0 = 13 */
130 #define BCH4R_ECC_SIZE1         0x3     /* ecc_size1 = 3 */
131 
132 /* GPMC ecc engine settings for write */
133 #define BCH_WRAPMODE_6          6       /* BCH wrap mode 6 */
134 #define BCH_ECC_SIZE0           0x0     /* ecc_size0 = 0, no oob protection */
135 #define BCH_ECC_SIZE1           0x20    /* ecc_size1 = 32 */
136 
137 #define BADBLOCK_MARKER_LENGTH          2
138 
139 static u_char bch16_vector[] = {0xf5, 0x24, 0x1c, 0xd0, 0x61, 0xb3, 0xf1, 0x55,
140                                 0x2e, 0x2c, 0x86, 0xa3, 0xed, 0x36, 0x1b, 0x78,
141                                 0x48, 0x76, 0xa9, 0x3b, 0x97, 0xd1, 0x7a, 0x93,
142                                 0x07, 0x0e};
143 static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
144         0xac, 0x6b, 0xff, 0x99, 0x7b};
145 static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
146 
147 /* Shared among all NAND instances to synchronize access to the ECC Engine */
148 static struct nand_hw_control omap_gpmc_controller = {
149         .lock = __SPIN_LOCK_UNLOCKED(omap_gpmc_controller.lock),
150         .wq = __WAIT_QUEUE_HEAD_INITIALIZER(omap_gpmc_controller.wq),
151 };
152 
153 struct omap_nand_info {
154         struct nand_chip                nand;
155         struct platform_device          *pdev;
156 
157         int                             gpmc_cs;
158         bool                            dev_ready;
159         enum nand_io                    xfer_type;
160         int                             devsize;
161         enum omap_ecc                   ecc_opt;
162         struct device_node              *elm_of_node;
163 
164         unsigned long                   phys_base;
165         struct completion               comp;
166         struct dma_chan                 *dma;
167         int                             gpmc_irq_fifo;
168         int                             gpmc_irq_count;
169         enum {
170                 OMAP_NAND_IO_READ = 0,  /* read */
171                 OMAP_NAND_IO_WRITE,     /* write */
172         } iomode;
173         u_char                          *buf;
174         int                                     buf_len;
175         /* Interface to GPMC */
176         struct gpmc_nand_regs           reg;
177         struct gpmc_nand_ops            *ops;
178         bool                            flash_bbt;
179         /* fields specific for BCHx_HW ECC scheme */
180         struct device                   *elm_dev;
181         /* NAND ready gpio */
182         struct gpio_desc                *ready_gpiod;
183 };
184 
185 static inline struct omap_nand_info *mtd_to_omap(struct mtd_info *mtd)
186 {
187         return container_of(mtd_to_nand(mtd), struct omap_nand_info, nand);
188 }
189 
190 /**
191  * omap_prefetch_enable - configures and starts prefetch transfer
192  * @cs: cs (chip select) number
193  * @fifo_th: fifo threshold to be used for read/ write
194  * @dma_mode: dma mode enable (1) or disable (0)
195  * @u32_count: number of bytes to be transferred
196  * @is_write: prefetch read(0) or write post(1) mode
197  */
198 static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode,
199         unsigned int u32_count, int is_write, struct omap_nand_info *info)
200 {
201         u32 val;
202 
203         if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
204                 return -1;
205 
206         if (readl(info->reg.gpmc_prefetch_control))
207                 return -EBUSY;
208 
209         /* Set the amount of bytes to be prefetched */
210         writel(u32_count, info->reg.gpmc_prefetch_config2);
211 
212         /* Set dma/mpu mode, the prefetch read / post write and
213          * enable the engine. Set which cs is has requested for.
214          */
215         val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) |
216                 PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH |
217                 (dma_mode << DMA_MPU_MODE_SHIFT) | (is_write & 0x1));
218         writel(val, info->reg.gpmc_prefetch_config1);
219 
220         /*  Start the prefetch engine */
221         writel(0x1, info->reg.gpmc_prefetch_control);
222 
223         return 0;
224 }
225 
226 /**
227  * omap_prefetch_reset - disables and stops the prefetch engine
228  */
229 static int omap_prefetch_reset(int cs, struct omap_nand_info *info)
230 {
231         u32 config1;
232 
233         /* check if the same module/cs is trying to reset */
234         config1 = readl(info->reg.gpmc_prefetch_config1);
235         if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs)
236                 return -EINVAL;
237 
238         /* Stop the PFPW engine */
239         writel(0x0, info->reg.gpmc_prefetch_control);
240 
241         /* Reset/disable the PFPW engine */
242         writel(0x0, info->reg.gpmc_prefetch_config1);
243 
244         return 0;
245 }
246 
247 /**
248  * omap_hwcontrol - hardware specific access to control-lines
249  * @mtd: MTD device structure
250  * @cmd: command to device
251  * @ctrl:
252  * NAND_NCE: bit 0 -> don't care
253  * NAND_CLE: bit 1 -> Command Latch
254  * NAND_ALE: bit 2 -> Address Latch
255  *
256  * NOTE: boards may use different bits for these!!
257  */
258 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
259 {
260         struct omap_nand_info *info = mtd_to_omap(mtd);
261 
262         if (cmd != NAND_CMD_NONE) {
263                 if (ctrl & NAND_CLE)
264                         writeb(cmd, info->reg.gpmc_nand_command);
265 
266                 else if (ctrl & NAND_ALE)
267                         writeb(cmd, info->reg.gpmc_nand_address);
268 
269                 else /* NAND_NCE */
270                         writeb(cmd, info->reg.gpmc_nand_data);
271         }
272 }
273 
274 /**
275  * omap_read_buf8 - read data from NAND controller into buffer
276  * @mtd: MTD device structure
277  * @buf: buffer to store date
278  * @len: number of bytes to read
279  */
280 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
281 {
282         struct nand_chip *nand = mtd_to_nand(mtd);
283 
284         ioread8_rep(nand->IO_ADDR_R, buf, len);
285 }
286 
287 /**
288  * omap_write_buf8 - write buffer to NAND controller
289  * @mtd: MTD device structure
290  * @buf: data buffer
291  * @len: number of bytes to write
292  */
293 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
294 {
295         struct omap_nand_info *info = mtd_to_omap(mtd);
296         u_char *p = (u_char *)buf;
297         bool status;
298 
299         while (len--) {
300                 iowrite8(*p++, info->nand.IO_ADDR_W);
301                 /* wait until buffer is available for write */
302                 do {
303                         status = info->ops->nand_writebuffer_empty();
304                 } while (!status);
305         }
306 }
307 
308 /**
309  * omap_read_buf16 - read data from NAND controller into buffer
310  * @mtd: MTD device structure
311  * @buf: buffer to store date
312  * @len: number of bytes to read
313  */
314 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
315 {
316         struct nand_chip *nand = mtd_to_nand(mtd);
317 
318         ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
319 }
320 
321 /**
322  * omap_write_buf16 - write buffer to NAND controller
323  * @mtd: MTD device structure
324  * @buf: data buffer
325  * @len: number of bytes to write
326  */
327 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
328 {
329         struct omap_nand_info *info = mtd_to_omap(mtd);
330         u16 *p = (u16 *) buf;
331         bool status;
332         /* FIXME try bursts of writesw() or DMA ... */
333         len >>= 1;
334 
335         while (len--) {
336                 iowrite16(*p++, info->nand.IO_ADDR_W);
337                 /* wait until buffer is available for write */
338                 do {
339                         status = info->ops->nand_writebuffer_empty();
340                 } while (!status);
341         }
342 }
343 
344 /**
345  * omap_read_buf_pref - read data from NAND controller into buffer
346  * @mtd: MTD device structure
347  * @buf: buffer to store date
348  * @len: number of bytes to read
349  */
350 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
351 {
352         struct omap_nand_info *info = mtd_to_omap(mtd);
353         uint32_t r_count = 0;
354         int ret = 0;
355         u32 *p = (u32 *)buf;
356 
357         /* take care of subpage reads */
358         if (len % 4) {
359                 if (info->nand.options & NAND_BUSWIDTH_16)
360                         omap_read_buf16(mtd, buf, len % 4);
361                 else
362                         omap_read_buf8(mtd, buf, len % 4);
363                 p = (u32 *) (buf + len % 4);
364                 len -= len % 4;
365         }
366 
367         /* configure and start prefetch transfer */
368         ret = omap_prefetch_enable(info->gpmc_cs,
369                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info);
370         if (ret) {
371                 /* PFPW engine is busy, use cpu copy method */
372                 if (info->nand.options & NAND_BUSWIDTH_16)
373                         omap_read_buf16(mtd, (u_char *)p, len);
374                 else
375                         omap_read_buf8(mtd, (u_char *)p, len);
376         } else {
377                 do {
378                         r_count = readl(info->reg.gpmc_prefetch_status);
379                         r_count = PREFETCH_STATUS_FIFO_CNT(r_count);
380                         r_count = r_count >> 2;
381                         ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
382                         p += r_count;
383                         len -= r_count << 2;
384                 } while (len);
385                 /* disable and stop the PFPW engine */
386                 omap_prefetch_reset(info->gpmc_cs, info);
387         }
388 }
389 
390 /**
391  * omap_write_buf_pref - write buffer to NAND controller
392  * @mtd: MTD device structure
393  * @buf: data buffer
394  * @len: number of bytes to write
395  */
396 static void omap_write_buf_pref(struct mtd_info *mtd,
397                                         const u_char *buf, int len)
398 {
399         struct omap_nand_info *info = mtd_to_omap(mtd);
400         uint32_t w_count = 0;
401         int i = 0, ret = 0;
402         u16 *p = (u16 *)buf;
403         unsigned long tim, limit;
404         u32 val;
405 
406         /* take care of subpage writes */
407         if (len % 2 != 0) {
408                 writeb(*buf, info->nand.IO_ADDR_W);
409                 p = (u16 *)(buf + 1);
410                 len--;
411         }
412 
413         /*  configure and start prefetch transfer */
414         ret = omap_prefetch_enable(info->gpmc_cs,
415                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info);
416         if (ret) {
417                 /* PFPW engine is busy, use cpu copy method */
418                 if (info->nand.options & NAND_BUSWIDTH_16)
419                         omap_write_buf16(mtd, (u_char *)p, len);
420                 else
421                         omap_write_buf8(mtd, (u_char *)p, len);
422         } else {
423                 while (len) {
424                         w_count = readl(info->reg.gpmc_prefetch_status);
425                         w_count = PREFETCH_STATUS_FIFO_CNT(w_count);
426                         w_count = w_count >> 1;
427                         for (i = 0; (i < w_count) && len; i++, len -= 2)
428                                 iowrite16(*p++, info->nand.IO_ADDR_W);
429                 }
430                 /* wait for data to flushed-out before reset the prefetch */
431                 tim = 0;
432                 limit = (loops_per_jiffy *
433                                         msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
434                 do {
435                         cpu_relax();
436                         val = readl(info->reg.gpmc_prefetch_status);
437                         val = PREFETCH_STATUS_COUNT(val);
438                 } while (val && (tim++ < limit));
439 
440                 /* disable and stop the PFPW engine */
441                 omap_prefetch_reset(info->gpmc_cs, info);
442         }
443 }
444 
445 /*
446  * omap_nand_dma_callback: callback on the completion of dma transfer
447  * @data: pointer to completion data structure
448  */
449 static void omap_nand_dma_callback(void *data)
450 {
451         complete((struct completion *) data);
452 }
453 
454 /*
455  * omap_nand_dma_transfer: configure and start dma transfer
456  * @mtd: MTD device structure
457  * @addr: virtual address in RAM of source/destination
458  * @len: number of data bytes to be transferred
459  * @is_write: flag for read/write operation
460  */
461 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
462                                         unsigned int len, int is_write)
463 {
464         struct omap_nand_info *info = mtd_to_omap(mtd);
465         struct dma_async_tx_descriptor *tx;
466         enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
467                                                         DMA_FROM_DEVICE;
468         struct scatterlist sg;
469         unsigned long tim, limit;
470         unsigned n;
471         int ret;
472         u32 val;
473 
474         if (!virt_addr_valid(addr))
475                 goto out_copy;
476 
477         sg_init_one(&sg, addr, len);
478         n = dma_map_sg(info->dma->device->dev, &sg, 1, dir);
479         if (n == 0) {
480                 dev_err(&info->pdev->dev,
481                         "Couldn't DMA map a %d byte buffer\n", len);
482                 goto out_copy;
483         }
484 
485         tx = dmaengine_prep_slave_sg(info->dma, &sg, n,
486                 is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
487                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
488         if (!tx)
489                 goto out_copy_unmap;
490 
491         tx->callback = omap_nand_dma_callback;
492         tx->callback_param = &info->comp;
493         dmaengine_submit(tx);
494 
495         init_completion(&info->comp);
496 
497         /* setup and start DMA using dma_addr */
498         dma_async_issue_pending(info->dma);
499 
500         /*  configure and start prefetch transfer */
501         ret = omap_prefetch_enable(info->gpmc_cs,
502                 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info);
503         if (ret)
504                 /* PFPW engine is busy, use cpu copy method */
505                 goto out_copy_unmap;
506 
507         wait_for_completion(&info->comp);
508         tim = 0;
509         limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
510 
511         do {
512                 cpu_relax();
513                 val = readl(info->reg.gpmc_prefetch_status);
514                 val = PREFETCH_STATUS_COUNT(val);
515         } while (val && (tim++ < limit));
516 
517         /* disable and stop the PFPW engine */
518         omap_prefetch_reset(info->gpmc_cs, info);
519 
520         dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
521         return 0;
522 
523 out_copy_unmap:
524         dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
525 out_copy:
526         if (info->nand.options & NAND_BUSWIDTH_16)
527                 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
528                         : omap_write_buf16(mtd, (u_char *) addr, len);
529         else
530                 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
531                         : omap_write_buf8(mtd, (u_char *) addr, len);
532         return 0;
533 }
534 
535 /**
536  * omap_read_buf_dma_pref - read data from NAND controller into buffer
537  * @mtd: MTD device structure
538  * @buf: buffer to store date
539  * @len: number of bytes to read
540  */
541 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
542 {
543         if (len <= mtd->oobsize)
544                 omap_read_buf_pref(mtd, buf, len);
545         else
546                 /* start transfer in DMA mode */
547                 omap_nand_dma_transfer(mtd, buf, len, 0x0);
548 }
549 
550 /**
551  * omap_write_buf_dma_pref - write buffer to NAND controller
552  * @mtd: MTD device structure
553  * @buf: data buffer
554  * @len: number of bytes to write
555  */
556 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
557                                         const u_char *buf, int len)
558 {
559         if (len <= mtd->oobsize)
560                 omap_write_buf_pref(mtd, buf, len);
561         else
562                 /* start transfer in DMA mode */
563                 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
564 }
565 
566 /*
567  * omap_nand_irq - GPMC irq handler
568  * @this_irq: gpmc irq number
569  * @dev: omap_nand_info structure pointer is passed here
570  */
571 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
572 {
573         struct omap_nand_info *info = (struct omap_nand_info *) dev;
574         u32 bytes;
575 
576         bytes = readl(info->reg.gpmc_prefetch_status);
577         bytes = PREFETCH_STATUS_FIFO_CNT(bytes);
578         bytes = bytes  & 0xFFFC; /* io in multiple of 4 bytes */
579         if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
580                 if (this_irq == info->gpmc_irq_count)
581                         goto done;
582 
583                 if (info->buf_len && (info->buf_len < bytes))
584                         bytes = info->buf_len;
585                 else if (!info->buf_len)
586                         bytes = 0;
587                 iowrite32_rep(info->nand.IO_ADDR_W,
588                                                 (u32 *)info->buf, bytes >> 2);
589                 info->buf = info->buf + bytes;
590                 info->buf_len -= bytes;
591 
592         } else {
593                 ioread32_rep(info->nand.IO_ADDR_R,
594                                                 (u32 *)info->buf, bytes >> 2);
595                 info->buf = info->buf + bytes;
596 
597                 if (this_irq == info->gpmc_irq_count)
598                         goto done;
599         }
600 
601         return IRQ_HANDLED;
602 
603 done:
604         complete(&info->comp);
605 
606         disable_irq_nosync(info->gpmc_irq_fifo);
607         disable_irq_nosync(info->gpmc_irq_count);
608 
609         return IRQ_HANDLED;
610 }
611 
612 /*
613  * omap_read_buf_irq_pref - read data from NAND controller into buffer
614  * @mtd: MTD device structure
615  * @buf: buffer to store date
616  * @len: number of bytes to read
617  */
618 static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
619 {
620         struct omap_nand_info *info = mtd_to_omap(mtd);
621         int ret = 0;
622 
623         if (len <= mtd->oobsize) {
624                 omap_read_buf_pref(mtd, buf, len);
625                 return;
626         }
627 
628         info->iomode = OMAP_NAND_IO_READ;
629         info->buf = buf;
630         init_completion(&info->comp);
631 
632         /*  configure and start prefetch transfer */
633         ret = omap_prefetch_enable(info->gpmc_cs,
634                         PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info);
635         if (ret)
636                 /* PFPW engine is busy, use cpu copy method */
637                 goto out_copy;
638 
639         info->buf_len = len;
640 
641         enable_irq(info->gpmc_irq_count);
642         enable_irq(info->gpmc_irq_fifo);
643 
644         /* waiting for read to complete */
645         wait_for_completion(&info->comp);
646 
647         /* disable and stop the PFPW engine */
648         omap_prefetch_reset(info->gpmc_cs, info);
649         return;
650 
651 out_copy:
652         if (info->nand.options & NAND_BUSWIDTH_16)
653                 omap_read_buf16(mtd, buf, len);
654         else
655                 omap_read_buf8(mtd, buf, len);
656 }
657 
658 /*
659  * omap_write_buf_irq_pref - write buffer to NAND controller
660  * @mtd: MTD device structure
661  * @buf: data buffer
662  * @len: number of bytes to write
663  */
664 static void omap_write_buf_irq_pref(struct mtd_info *mtd,
665                                         const u_char *buf, int len)
666 {
667         struct omap_nand_info *info = mtd_to_omap(mtd);
668         int ret = 0;
669         unsigned long tim, limit;
670         u32 val;
671 
672         if (len <= mtd->oobsize) {
673                 omap_write_buf_pref(mtd, buf, len);
674                 return;
675         }
676 
677         info->iomode = OMAP_NAND_IO_WRITE;
678         info->buf = (u_char *) buf;
679         init_completion(&info->comp);
680 
681         /* configure and start prefetch transfer : size=24 */
682         ret = omap_prefetch_enable(info->gpmc_cs,
683                 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info);
684         if (ret)
685                 /* PFPW engine is busy, use cpu copy method */
686                 goto out_copy;
687 
688         info->buf_len = len;
689 
690         enable_irq(info->gpmc_irq_count);
691         enable_irq(info->gpmc_irq_fifo);
692 
693         /* waiting for write to complete */
694         wait_for_completion(&info->comp);
695 
696         /* wait for data to flushed-out before reset the prefetch */
697         tim = 0;
698         limit = (loops_per_jiffy *  msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
699         do {
700                 val = readl(info->reg.gpmc_prefetch_status);
701                 val = PREFETCH_STATUS_COUNT(val);
702                 cpu_relax();
703         } while (val && (tim++ < limit));
704 
705         /* disable and stop the PFPW engine */
706         omap_prefetch_reset(info->gpmc_cs, info);
707         return;
708 
709 out_copy:
710         if (info->nand.options & NAND_BUSWIDTH_16)
711                 omap_write_buf16(mtd, buf, len);
712         else
713                 omap_write_buf8(mtd, buf, len);
714 }
715 
716 /**
717  * gen_true_ecc - This function will generate true ECC value
718  * @ecc_buf: buffer to store ecc code
719  *
720  * This generated true ECC value can be used when correcting
721  * data read from NAND flash memory core
722  */
723 static void gen_true_ecc(u8 *ecc_buf)
724 {
725         u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
726                 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
727 
728         ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
729                         P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
730         ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
731                         P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
732         ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
733                         P1e(tmp) | P2048o(tmp) | P2048e(tmp));
734 }
735 
736 /**
737  * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
738  * @ecc_data1:  ecc code from nand spare area
739  * @ecc_data2:  ecc code from hardware register obtained from hardware ecc
740  * @page_data:  page data
741  *
742  * This function compares two ECC's and indicates if there is an error.
743  * If the error can be corrected it will be corrected to the buffer.
744  * If there is no error, %0 is returned. If there is an error but it
745  * was corrected, %1 is returned. Otherwise, %-1 is returned.
746  */
747 static int omap_compare_ecc(u8 *ecc_data1,      /* read from NAND memory */
748                             u8 *ecc_data2,      /* read from register */
749                             u8 *page_data)
750 {
751         uint    i;
752         u8      tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
753         u8      comp0_bit[8], comp1_bit[8], comp2_bit[8];
754         u8      ecc_bit[24];
755         u8      ecc_sum = 0;
756         u8      find_bit = 0;
757         uint    find_byte = 0;
758         int     isEccFF;
759 
760         isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
761 
762         gen_true_ecc(ecc_data1);
763         gen_true_ecc(ecc_data2);
764 
765         for (i = 0; i <= 2; i++) {
766                 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
767                 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
768         }
769 
770         for (i = 0; i < 8; i++) {
771                 tmp0_bit[i]     = *ecc_data1 % 2;
772                 *ecc_data1      = *ecc_data1 / 2;
773         }
774 
775         for (i = 0; i < 8; i++) {
776                 tmp1_bit[i]      = *(ecc_data1 + 1) % 2;
777                 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
778         }
779 
780         for (i = 0; i < 8; i++) {
781                 tmp2_bit[i]      = *(ecc_data1 + 2) % 2;
782                 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
783         }
784 
785         for (i = 0; i < 8; i++) {
786                 comp0_bit[i]     = *ecc_data2 % 2;
787                 *ecc_data2       = *ecc_data2 / 2;
788         }
789 
790         for (i = 0; i < 8; i++) {
791                 comp1_bit[i]     = *(ecc_data2 + 1) % 2;
792                 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
793         }
794 
795         for (i = 0; i < 8; i++) {
796                 comp2_bit[i]     = *(ecc_data2 + 2) % 2;
797                 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
798         }
799 
800         for (i = 0; i < 6; i++)
801                 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
802 
803         for (i = 0; i < 8; i++)
804                 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
805 
806         for (i = 0; i < 8; i++)
807                 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
808 
809         ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
810         ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
811 
812         for (i = 0; i < 24; i++)
813                 ecc_sum += ecc_bit[i];
814 
815         switch (ecc_sum) {
816         case 0:
817                 /* Not reached because this function is not called if
818                  *  ECC values are equal
819                  */
820                 return 0;
821 
822         case 1:
823                 /* Uncorrectable error */
824                 pr_debug("ECC UNCORRECTED_ERROR 1\n");
825                 return -EBADMSG;
826 
827         case 11:
828                 /* UN-Correctable error */
829                 pr_debug("ECC UNCORRECTED_ERROR B\n");
830                 return -EBADMSG;
831 
832         case 12:
833                 /* Correctable error */
834                 find_byte = (ecc_bit[23] << 8) +
835                             (ecc_bit[21] << 7) +
836                             (ecc_bit[19] << 6) +
837                             (ecc_bit[17] << 5) +
838                             (ecc_bit[15] << 4) +
839                             (ecc_bit[13] << 3) +
840                             (ecc_bit[11] << 2) +
841                             (ecc_bit[9]  << 1) +
842                             ecc_bit[7];
843 
844                 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
845 
846                 pr_debug("Correcting single bit ECC error at offset: "
847                                 "%d, bit: %d\n", find_byte, find_bit);
848 
849                 page_data[find_byte] ^= (1 << find_bit);
850 
851                 return 1;
852         default:
853                 if (isEccFF) {
854                         if (ecc_data2[0] == 0 &&
855                             ecc_data2[1] == 0 &&
856                             ecc_data2[2] == 0)
857                                 return 0;
858                 }
859                 pr_debug("UNCORRECTED_ERROR default\n");
860                 return -EBADMSG;
861         }
862 }
863 
864 /**
865  * omap_correct_data - Compares the ECC read with HW generated ECC
866  * @mtd: MTD device structure
867  * @dat: page data
868  * @read_ecc: ecc read from nand flash
869  * @calc_ecc: ecc read from HW ECC registers
870  *
871  * Compares the ecc read from nand spare area with ECC registers values
872  * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
873  * detection and correction. If there are no errors, %0 is returned. If
874  * there were errors and all of the errors were corrected, the number of
875  * corrected errors is returned. If uncorrectable errors exist, %-1 is
876  * returned.
877  */
878 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
879                                 u_char *read_ecc, u_char *calc_ecc)
880 {
881         struct omap_nand_info *info = mtd_to_omap(mtd);
882         int blockCnt = 0, i = 0, ret = 0;
883         int stat = 0;
884 
885         /* Ex NAND_ECC_HW12_2048 */
886         if ((info->nand.ecc.mode == NAND_ECC_HW) &&
887                         (info->nand.ecc.size  == 2048))
888                 blockCnt = 4;
889         else
890                 blockCnt = 1;
891 
892         for (i = 0; i < blockCnt; i++) {
893                 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
894                         ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
895                         if (ret < 0)
896                                 return ret;
897                         /* keep track of the number of corrected errors */
898                         stat += ret;
899                 }
900                 read_ecc += 3;
901                 calc_ecc += 3;
902                 dat      += 512;
903         }
904         return stat;
905 }
906 
907 /**
908  * omap_calcuate_ecc - Generate non-inverted ECC bytes.
909  * @mtd: MTD device structure
910  * @dat: The pointer to data on which ecc is computed
911  * @ecc_code: The ecc_code buffer
912  *
913  * Using noninverted ECC can be considered ugly since writing a blank
914  * page ie. padding will clear the ECC bytes. This is no problem as long
915  * nobody is trying to write data on the seemingly unused page. Reading
916  * an erased page will produce an ECC mismatch between generated and read
917  * ECC bytes that has to be dealt with separately.
918  */
919 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
920                                 u_char *ecc_code)
921 {
922         struct omap_nand_info *info = mtd_to_omap(mtd);
923         u32 val;
924 
925         val = readl(info->reg.gpmc_ecc_config);
926         if (((val >> ECC_CONFIG_CS_SHIFT) & CS_MASK) != info->gpmc_cs)
927                 return -EINVAL;
928 
929         /* read ecc result */
930         val = readl(info->reg.gpmc_ecc1_result);
931         *ecc_code++ = val;          /* P128e, ..., P1e */
932         *ecc_code++ = val >> 16;    /* P128o, ..., P1o */
933         /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
934         *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
935 
936         return 0;
937 }
938 
939 /**
940  * omap_enable_hwecc - This function enables the hardware ecc functionality
941  * @mtd: MTD device structure
942  * @mode: Read/Write mode
943  */
944 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
945 {
946         struct omap_nand_info *info = mtd_to_omap(mtd);
947         struct nand_chip *chip = mtd_to_nand(mtd);
948         unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
949         u32 val;
950 
951         /* clear ecc and enable bits */
952         val = ECCCLEAR | ECC1;
953         writel(val, info->reg.gpmc_ecc_control);
954 
955         /* program ecc and result sizes */
956         val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
957                          ECC1RESULTSIZE);
958         writel(val, info->reg.gpmc_ecc_size_config);
959 
960         switch (mode) {
961         case NAND_ECC_READ:
962         case NAND_ECC_WRITE:
963                 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
964                 break;
965         case NAND_ECC_READSYN:
966                 writel(ECCCLEAR, info->reg.gpmc_ecc_control);
967                 break;
968         default:
969                 dev_info(&info->pdev->dev,
970                         "error: unrecognized Mode[%d]!\n", mode);
971                 break;
972         }
973 
974         /* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
975         val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
976         writel(val, info->reg.gpmc_ecc_config);
977 }
978 
979 /**
980  * omap_wait - wait until the command is done
981  * @mtd: MTD device structure
982  * @chip: NAND Chip structure
983  *
984  * Wait function is called during Program and erase operations and
985  * the way it is called from MTD layer, we should wait till the NAND
986  * chip is ready after the programming/erase operation has completed.
987  *
988  * Erase can take up to 400ms and program up to 20ms according to
989  * general NAND and SmartMedia specs
990  */
991 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
992 {
993         struct nand_chip *this = mtd_to_nand(mtd);
994         struct omap_nand_info *info = mtd_to_omap(mtd);
995         unsigned long timeo = jiffies;
996         int status, state = this->state;
997 
998         if (state == FL_ERASING)
999                 timeo += msecs_to_jiffies(400);
1000         else
1001                 timeo += msecs_to_jiffies(20);
1002 
1003         writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command);
1004         while (time_before(jiffies, timeo)) {
1005                 status = readb(info->reg.gpmc_nand_data);
1006                 if (status & NAND_STATUS_READY)
1007                         break;
1008                 cond_resched();
1009         }
1010 
1011         status = readb(info->reg.gpmc_nand_data);
1012         return status;
1013 }
1014 
1015 /**
1016  * omap_dev_ready - checks the NAND Ready GPIO line
1017  * @mtd: MTD device structure
1018  *
1019  * Returns true if ready and false if busy.
1020  */
1021 static int omap_dev_ready(struct mtd_info *mtd)
1022 {
1023         struct omap_nand_info *info = mtd_to_omap(mtd);
1024 
1025         return gpiod_get_value(info->ready_gpiod);
1026 }
1027 
1028 /**
1029  * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation
1030  * @mtd: MTD device structure
1031  * @mode: Read/Write mode
1032  *
1033  * When using BCH with SW correction (i.e. no ELM), sector size is set
1034  * to 512 bytes and we use BCH_WRAPMODE_6 wrapping mode
1035  * for both reading and writing with:
1036  * eccsize0 = 0  (no additional protected byte in spare area)
1037  * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1038  */
1039 static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd, int mode)
1040 {
1041         unsigned int bch_type;
1042         unsigned int dev_width, nsectors;
1043         struct omap_nand_info *info = mtd_to_omap(mtd);
1044         enum omap_ecc ecc_opt = info->ecc_opt;
1045         struct nand_chip *chip = mtd_to_nand(mtd);
1046         u32 val, wr_mode;
1047         unsigned int ecc_size1, ecc_size0;
1048 
1049         /* GPMC configurations for calculating ECC */
1050         switch (ecc_opt) {
1051         case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1052                 bch_type = 0;
1053                 nsectors = 1;
1054                 wr_mode   = BCH_WRAPMODE_6;
1055                 ecc_size0 = BCH_ECC_SIZE0;
1056                 ecc_size1 = BCH_ECC_SIZE1;
1057                 break;
1058         case OMAP_ECC_BCH4_CODE_HW:
1059                 bch_type = 0;
1060                 nsectors = chip->ecc.steps;
1061                 if (mode == NAND_ECC_READ) {
1062                         wr_mode   = BCH_WRAPMODE_1;
1063                         ecc_size0 = BCH4R_ECC_SIZE0;
1064                         ecc_size1 = BCH4R_ECC_SIZE1;
1065                 } else {
1066                         wr_mode   = BCH_WRAPMODE_6;
1067                         ecc_size0 = BCH_ECC_SIZE0;
1068                         ecc_size1 = BCH_ECC_SIZE1;
1069                 }
1070                 break;
1071         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1072                 bch_type = 1;
1073                 nsectors = 1;
1074                 wr_mode   = BCH_WRAPMODE_6;
1075                 ecc_size0 = BCH_ECC_SIZE0;
1076                 ecc_size1 = BCH_ECC_SIZE1;
1077                 break;
1078         case OMAP_ECC_BCH8_CODE_HW:
1079                 bch_type = 1;
1080                 nsectors = chip->ecc.steps;
1081                 if (mode == NAND_ECC_READ) {
1082                         wr_mode   = BCH_WRAPMODE_1;
1083                         ecc_size0 = BCH8R_ECC_SIZE0;
1084                         ecc_size1 = BCH8R_ECC_SIZE1;
1085                 } else {
1086                         wr_mode   = BCH_WRAPMODE_6;
1087                         ecc_size0 = BCH_ECC_SIZE0;
1088                         ecc_size1 = BCH_ECC_SIZE1;
1089                 }
1090                 break;
1091         case OMAP_ECC_BCH16_CODE_HW:
1092                 bch_type = 0x2;
1093                 nsectors = chip->ecc.steps;
1094                 if (mode == NAND_ECC_READ) {
1095                         wr_mode   = 0x01;
1096                         ecc_size0 = 52; /* ECC bits in nibbles per sector */
1097                         ecc_size1 = 0;  /* non-ECC bits in nibbles per sector */
1098                 } else {
1099                         wr_mode   = 0x01;
1100                         ecc_size0 = 0;  /* extra bits in nibbles per sector */
1101                         ecc_size1 = 52; /* OOB bits in nibbles per sector */
1102                 }
1103                 break;
1104         default:
1105                 return;
1106         }
1107 
1108         writel(ECC1, info->reg.gpmc_ecc_control);
1109 
1110         /* Configure ecc size for BCH */
1111         val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT);
1112         writel(val, info->reg.gpmc_ecc_size_config);
1113 
1114         dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
1115 
1116         /* BCH configuration */
1117         val = ((1                        << 16) | /* enable BCH */
1118                (bch_type                 << 12) | /* BCH4/BCH8/BCH16 */
1119                (wr_mode                  <<  8) | /* wrap mode */
1120                (dev_width                <<  7) | /* bus width */
1121                (((nsectors-1) & 0x7)     <<  4) | /* number of sectors */
1122                (info->gpmc_cs            <<  1) | /* ECC CS */
1123                (0x1));                            /* enable ECC */
1124 
1125         writel(val, info->reg.gpmc_ecc_config);
1126 
1127         /* Clear ecc and enable bits */
1128         writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
1129 }
1130 
1131 static u8  bch4_polynomial[] = {0x28, 0x13, 0xcc, 0x39, 0x96, 0xac, 0x7f};
1132 static u8  bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
1133                                 0x97, 0x79, 0xe5, 0x24, 0xb5};
1134 
1135 /**
1136  * omap_calculate_ecc_bch - Generate bytes of ECC bytes
1137  * @mtd:        MTD device structure
1138  * @dat:        The pointer to data on which ecc is computed
1139  * @ecc_code:   The ecc_code buffer
1140  *
1141  * Support calculating of BCH4/8 ecc vectors for the page
1142  */
1143 static int __maybe_unused omap_calculate_ecc_bch(struct mtd_info *mtd,
1144                                         const u_char *dat, u_char *ecc_calc)
1145 {
1146         struct omap_nand_info *info = mtd_to_omap(mtd);
1147         int eccbytes    = info->nand.ecc.bytes;
1148         struct gpmc_nand_regs   *gpmc_regs = &info->reg;
1149         u8 *ecc_code;
1150         unsigned long nsectors, bch_val1, bch_val2, bch_val3, bch_val4;
1151         u32 val;
1152         int i, j;
1153 
1154         nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1155         for (i = 0; i < nsectors; i++) {
1156                 ecc_code = ecc_calc;
1157                 switch (info->ecc_opt) {
1158                 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1159                 case OMAP_ECC_BCH8_CODE_HW:
1160                         bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1161                         bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1162                         bch_val3 = readl(gpmc_regs->gpmc_bch_result2[i]);
1163                         bch_val4 = readl(gpmc_regs->gpmc_bch_result3[i]);
1164                         *ecc_code++ = (bch_val4 & 0xFF);
1165                         *ecc_code++ = ((bch_val3 >> 24) & 0xFF);
1166                         *ecc_code++ = ((bch_val3 >> 16) & 0xFF);
1167                         *ecc_code++ = ((bch_val3 >> 8) & 0xFF);
1168                         *ecc_code++ = (bch_val3 & 0xFF);
1169                         *ecc_code++ = ((bch_val2 >> 24) & 0xFF);
1170                         *ecc_code++ = ((bch_val2 >> 16) & 0xFF);
1171                         *ecc_code++ = ((bch_val2 >> 8) & 0xFF);
1172                         *ecc_code++ = (bch_val2 & 0xFF);
1173                         *ecc_code++ = ((bch_val1 >> 24) & 0xFF);
1174                         *ecc_code++ = ((bch_val1 >> 16) & 0xFF);
1175                         *ecc_code++ = ((bch_val1 >> 8) & 0xFF);
1176                         *ecc_code++ = (bch_val1 & 0xFF);
1177                         break;
1178                 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1179                 case OMAP_ECC_BCH4_CODE_HW:
1180                         bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1181                         bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1182                         *ecc_code++ = ((bch_val2 >> 12) & 0xFF);
1183                         *ecc_code++ = ((bch_val2 >> 4) & 0xFF);
1184                         *ecc_code++ = ((bch_val2 & 0xF) << 4) |
1185                                 ((bch_val1 >> 28) & 0xF);
1186                         *ecc_code++ = ((bch_val1 >> 20) & 0xFF);
1187                         *ecc_code++ = ((bch_val1 >> 12) & 0xFF);
1188                         *ecc_code++ = ((bch_val1 >> 4) & 0xFF);
1189                         *ecc_code++ = ((bch_val1 & 0xF) << 4);
1190                         break;
1191                 case OMAP_ECC_BCH16_CODE_HW:
1192                         val = readl(gpmc_regs->gpmc_bch_result6[i]);
1193                         ecc_code[0]  = ((val >>  8) & 0xFF);
1194                         ecc_code[1]  = ((val >>  0) & 0xFF);
1195                         val = readl(gpmc_regs->gpmc_bch_result5[i]);
1196                         ecc_code[2]  = ((val >> 24) & 0xFF);
1197                         ecc_code[3]  = ((val >> 16) & 0xFF);
1198                         ecc_code[4]  = ((val >>  8) & 0xFF);
1199                         ecc_code[5]  = ((val >>  0) & 0xFF);
1200                         val = readl(gpmc_regs->gpmc_bch_result4[i]);
1201                         ecc_code[6]  = ((val >> 24) & 0xFF);
1202                         ecc_code[7]  = ((val >> 16) & 0xFF);
1203                         ecc_code[8]  = ((val >>  8) & 0xFF);
1204                         ecc_code[9]  = ((val >>  0) & 0xFF);
1205                         val = readl(gpmc_regs->gpmc_bch_result3[i]);
1206                         ecc_code[10] = ((val >> 24) & 0xFF);
1207                         ecc_code[11] = ((val >> 16) & 0xFF);
1208                         ecc_code[12] = ((val >>  8) & 0xFF);
1209                         ecc_code[13] = ((val >>  0) & 0xFF);
1210                         val = readl(gpmc_regs->gpmc_bch_result2[i]);
1211                         ecc_code[14] = ((val >> 24) & 0xFF);
1212                         ecc_code[15] = ((val >> 16) & 0xFF);
1213                         ecc_code[16] = ((val >>  8) & 0xFF);
1214                         ecc_code[17] = ((val >>  0) & 0xFF);
1215                         val = readl(gpmc_regs->gpmc_bch_result1[i]);
1216                         ecc_code[18] = ((val >> 24) & 0xFF);
1217                         ecc_code[19] = ((val >> 16) & 0xFF);
1218                         ecc_code[20] = ((val >>  8) & 0xFF);
1219                         ecc_code[21] = ((val >>  0) & 0xFF);
1220                         val = readl(gpmc_regs->gpmc_bch_result0[i]);
1221                         ecc_code[22] = ((val >> 24) & 0xFF);
1222                         ecc_code[23] = ((val >> 16) & 0xFF);
1223                         ecc_code[24] = ((val >>  8) & 0xFF);
1224                         ecc_code[25] = ((val >>  0) & 0xFF);
1225                         break;
1226                 default:
1227                         return -EINVAL;
1228                 }
1229 
1230                 /* ECC scheme specific syndrome customizations */
1231                 switch (info->ecc_opt) {
1232                 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1233                         /* Add constant polynomial to remainder, so that
1234                          * ECC of blank pages results in 0x0 on reading back */
1235                         for (j = 0; j < eccbytes; j++)
1236                                 ecc_calc[j] ^= bch4_polynomial[j];
1237                         break;
1238                 case OMAP_ECC_BCH4_CODE_HW:
1239                         /* Set  8th ECC byte as 0x0 for ROM compatibility */
1240                         ecc_calc[eccbytes - 1] = 0x0;
1241                         break;
1242                 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1243                         /* Add constant polynomial to remainder, so that
1244                          * ECC of blank pages results in 0x0 on reading back */
1245                         for (j = 0; j < eccbytes; j++)
1246                                 ecc_calc[j] ^= bch8_polynomial[j];
1247                         break;
1248                 case OMAP_ECC_BCH8_CODE_HW:
1249                         /* Set 14th ECC byte as 0x0 for ROM compatibility */
1250                         ecc_calc[eccbytes - 1] = 0x0;
1251                         break;
1252                 case OMAP_ECC_BCH16_CODE_HW:
1253                         break;
1254                 default:
1255                         return -EINVAL;
1256                 }
1257 
1258         ecc_calc += eccbytes;
1259         }
1260 
1261         return 0;
1262 }
1263 
1264 /**
1265  * erased_sector_bitflips - count bit flips
1266  * @data:       data sector buffer
1267  * @oob:        oob buffer
1268  * @info:       omap_nand_info
1269  *
1270  * Check the bit flips in erased page falls below correctable level.
1271  * If falls below, report the page as erased with correctable bit
1272  * flip, else report as uncorrectable page.
1273  */
1274 static int erased_sector_bitflips(u_char *data, u_char *oob,
1275                 struct omap_nand_info *info)
1276 {
1277         int flip_bits = 0, i;
1278 
1279         for (i = 0; i < info->nand.ecc.size; i++) {
1280                 flip_bits += hweight8(~data[i]);
1281                 if (flip_bits > info->nand.ecc.strength)
1282                         return 0;
1283         }
1284 
1285         for (i = 0; i < info->nand.ecc.bytes - 1; i++) {
1286                 flip_bits += hweight8(~oob[i]);
1287                 if (flip_bits > info->nand.ecc.strength)
1288                         return 0;
1289         }
1290 
1291         /*
1292          * Bit flips falls in correctable level.
1293          * Fill data area with 0xFF
1294          */
1295         if (flip_bits) {
1296                 memset(data, 0xFF, info->nand.ecc.size);
1297                 memset(oob, 0xFF, info->nand.ecc.bytes);
1298         }
1299 
1300         return flip_bits;
1301 }
1302 
1303 /**
1304  * omap_elm_correct_data - corrects page data area in case error reported
1305  * @mtd:        MTD device structure
1306  * @data:       page data
1307  * @read_ecc:   ecc read from nand flash
1308  * @calc_ecc:   ecc read from HW ECC registers
1309  *
1310  * Calculated ecc vector reported as zero in case of non-error pages.
1311  * In case of non-zero ecc vector, first filter out erased-pages, and
1312  * then process data via ELM to detect bit-flips.
1313  */
1314 static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data,
1315                                 u_char *read_ecc, u_char *calc_ecc)
1316 {
1317         struct omap_nand_info *info = mtd_to_omap(mtd);
1318         struct nand_ecc_ctrl *ecc = &info->nand.ecc;
1319         int eccsteps = info->nand.ecc.steps;
1320         int i , j, stat = 0;
1321         int eccflag, actual_eccbytes;
1322         struct elm_errorvec err_vec[ERROR_VECTOR_MAX];
1323         u_char *ecc_vec = calc_ecc;
1324         u_char *spare_ecc = read_ecc;
1325         u_char *erased_ecc_vec;
1326         u_char *buf;
1327         int bitflip_count;
1328         bool is_error_reported = false;
1329         u32 bit_pos, byte_pos, error_max, pos;
1330         int err;
1331 
1332         switch (info->ecc_opt) {
1333         case OMAP_ECC_BCH4_CODE_HW:
1334                 /* omit  7th ECC byte reserved for ROM code compatibility */
1335                 actual_eccbytes = ecc->bytes - 1;
1336                 erased_ecc_vec = bch4_vector;
1337                 break;
1338         case OMAP_ECC_BCH8_CODE_HW:
1339                 /* omit 14th ECC byte reserved for ROM code compatibility */
1340                 actual_eccbytes = ecc->bytes - 1;
1341                 erased_ecc_vec = bch8_vector;
1342                 break;
1343         case OMAP_ECC_BCH16_CODE_HW:
1344                 actual_eccbytes = ecc->bytes;
1345                 erased_ecc_vec = bch16_vector;
1346                 break;
1347         default:
1348                 dev_err(&info->pdev->dev, "invalid driver configuration\n");
1349                 return -EINVAL;
1350         }
1351 
1352         /* Initialize elm error vector to zero */
1353         memset(err_vec, 0, sizeof(err_vec));
1354 
1355         for (i = 0; i < eccsteps ; i++) {
1356                 eccflag = 0;    /* initialize eccflag */
1357 
1358                 /*
1359                  * Check any error reported,
1360                  * In case of error, non zero ecc reported.
1361                  */
1362                 for (j = 0; j < actual_eccbytes; j++) {
1363                         if (calc_ecc[j] != 0) {
1364                                 eccflag = 1; /* non zero ecc, error present */
1365                                 break;
1366                         }
1367                 }
1368 
1369                 if (eccflag == 1) {
1370                         if (memcmp(calc_ecc, erased_ecc_vec,
1371                                                 actual_eccbytes) == 0) {
1372                                 /*
1373                                  * calc_ecc[] matches pattern for ECC(all 0xff)
1374                                  * so this is definitely an erased-page
1375                                  */
1376                         } else {
1377                                 buf = &data[info->nand.ecc.size * i];
1378                                 /*
1379                                  * count number of 0-bits in read_buf.
1380                                  * This check can be removed once a similar
1381                                  * check is introduced in generic NAND driver
1382                                  */
1383                                 bitflip_count = erased_sector_bitflips(
1384                                                 buf, read_ecc, info);
1385                                 if (bitflip_count) {
1386                                         /*
1387                                          * number of 0-bits within ECC limits
1388                                          * So this may be an erased-page
1389                                          */
1390                                         stat += bitflip_count;
1391                                 } else {
1392                                         /*
1393                                          * Too many 0-bits. It may be a
1394                                          * - programmed-page, OR
1395                                          * - erased-page with many bit-flips
1396                                          * So this page requires check by ELM
1397                                          */
1398                                         err_vec[i].error_reported = true;
1399                                         is_error_reported = true;
1400                                 }
1401                         }
1402                 }
1403 
1404                 /* Update the ecc vector */
1405                 calc_ecc += ecc->bytes;
1406                 read_ecc += ecc->bytes;
1407         }
1408 
1409         /* Check if any error reported */
1410         if (!is_error_reported)
1411                 return stat;
1412 
1413         /* Decode BCH error using ELM module */
1414         elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec);
1415 
1416         err = 0;
1417         for (i = 0; i < eccsteps; i++) {
1418                 if (err_vec[i].error_uncorrectable) {
1419                         dev_err(&info->pdev->dev,
1420                                 "uncorrectable bit-flips found\n");
1421                         err = -EBADMSG;
1422                 } else if (err_vec[i].error_reported) {
1423                         for (j = 0; j < err_vec[i].error_count; j++) {
1424                                 switch (info->ecc_opt) {
1425                                 case OMAP_ECC_BCH4_CODE_HW:
1426                                         /* Add 4 bits to take care of padding */
1427                                         pos = err_vec[i].error_loc[j] +
1428                                                 BCH4_BIT_PAD;
1429                                         break;
1430                                 case OMAP_ECC_BCH8_CODE_HW:
1431                                 case OMAP_ECC_BCH16_CODE_HW:
1432                                         pos = err_vec[i].error_loc[j];
1433                                         break;
1434                                 default:
1435                                         return -EINVAL;
1436                                 }
1437                                 error_max = (ecc->size + actual_eccbytes) * 8;
1438                                 /* Calculate bit position of error */
1439                                 bit_pos = pos % 8;
1440 
1441                                 /* Calculate byte position of error */
1442                                 byte_pos = (error_max - pos - 1) / 8;
1443 
1444                                 if (pos < error_max) {
1445                                         if (byte_pos < 512) {
1446                                                 pr_debug("bitflip@dat[%d]=%x\n",
1447                                                      byte_pos, data[byte_pos]);
1448                                                 data[byte_pos] ^= 1 << bit_pos;
1449                                         } else {
1450                                                 pr_debug("bitflip@oob[%d]=%x\n",
1451                                                         (byte_pos - 512),
1452                                                      spare_ecc[byte_pos - 512]);
1453                                                 spare_ecc[byte_pos - 512] ^=
1454                                                         1 << bit_pos;
1455                                         }
1456                                 } else {
1457                                         dev_err(&info->pdev->dev,
1458                                                 "invalid bit-flip @ %d:%d\n",
1459                                                 byte_pos, bit_pos);
1460                                         err = -EBADMSG;
1461                                 }
1462                         }
1463                 }
1464 
1465                 /* Update number of correctable errors */
1466                 stat += err_vec[i].error_count;
1467 
1468                 /* Update page data with sector size */
1469                 data += ecc->size;
1470                 spare_ecc += ecc->bytes;
1471         }
1472 
1473         return (err) ? err : stat;
1474 }
1475 
1476 /**
1477  * omap_write_page_bch - BCH ecc based write page function for entire page
1478  * @mtd:                mtd info structure
1479  * @chip:               nand chip info structure
1480  * @buf:                data buffer
1481  * @oob_required:       must write chip->oob_poi to OOB
1482  * @page:               page
1483  *
1484  * Custom write page method evolved to support multi sector writing in one shot
1485  */
1486 static int omap_write_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1487                                const uint8_t *buf, int oob_required, int page)
1488 {
1489         int ret;
1490         uint8_t *ecc_calc = chip->buffers->ecccalc;
1491 
1492         /* Enable GPMC ecc engine */
1493         chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1494 
1495         /* Write data */
1496         chip->write_buf(mtd, buf, mtd->writesize);
1497 
1498         /* Update ecc vector from GPMC result registers */
1499         chip->ecc.calculate(mtd, buf, &ecc_calc[0]);
1500 
1501         ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
1502                                          chip->ecc.total);
1503         if (ret)
1504                 return ret;
1505 
1506         /* Write ecc vector to OOB area */
1507         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1508         return 0;
1509 }
1510 
1511 /**
1512  * omap_read_page_bch - BCH ecc based page read function for entire page
1513  * @mtd:                mtd info structure
1514  * @chip:               nand chip info structure
1515  * @buf:                buffer to store read data
1516  * @oob_required:       caller requires OOB data read to chip->oob_poi
1517  * @page:               page number to read
1518  *
1519  * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module
1520  * used for error correction.
1521  * Custom method evolved to support ELM error correction & multi sector
1522  * reading. On reading page data area is read along with OOB data with
1523  * ecc engine enabled. ecc vector updated after read of OOB data.
1524  * For non error pages ecc vector reported as zero.
1525  */
1526 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1527                                 uint8_t *buf, int oob_required, int page)
1528 {
1529         uint8_t *ecc_calc = chip->buffers->ecccalc;
1530         uint8_t *ecc_code = chip->buffers->ecccode;
1531         int stat, ret;
1532         unsigned int max_bitflips = 0;
1533 
1534         /* Enable GPMC ecc engine */
1535         chip->ecc.hwctl(mtd, NAND_ECC_READ);
1536 
1537         /* Read data */
1538         chip->read_buf(mtd, buf, mtd->writesize);
1539 
1540         /* Read oob bytes */
1541         chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1542                       mtd->writesize + BADBLOCK_MARKER_LENGTH, -1);
1543         chip->read_buf(mtd, chip->oob_poi + BADBLOCK_MARKER_LENGTH,
1544                        chip->ecc.total);
1545 
1546         /* Calculate ecc bytes */
1547         chip->ecc.calculate(mtd, buf, ecc_calc);
1548 
1549         ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
1550                                          chip->ecc.total);
1551         if (ret)
1552                 return ret;
1553 
1554         stat = chip->ecc.correct(mtd, buf, ecc_code, ecc_calc);
1555 
1556         if (stat < 0) {
1557                 mtd->ecc_stats.failed++;
1558         } else {
1559                 mtd->ecc_stats.corrected += stat;
1560                 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1561         }
1562 
1563         return max_bitflips;
1564 }
1565 
1566 /**
1567  * is_elm_present - checks for presence of ELM module by scanning DT nodes
1568  * @omap_nand_info: NAND device structure containing platform data
1569  */
1570 static bool is_elm_present(struct omap_nand_info *info,
1571                            struct device_node *elm_node)
1572 {
1573         struct platform_device *pdev;
1574 
1575         /* check whether elm-id is passed via DT */
1576         if (!elm_node) {
1577                 dev_err(&info->pdev->dev, "ELM devicetree node not found\n");
1578                 return false;
1579         }
1580         pdev = of_find_device_by_node(elm_node);
1581         /* check whether ELM device is registered */
1582         if (!pdev) {
1583                 dev_err(&info->pdev->dev, "ELM device not found\n");
1584                 return false;
1585         }
1586         /* ELM module available, now configure it */
1587         info->elm_dev = &pdev->dev;
1588         return true;
1589 }
1590 
1591 static bool omap2_nand_ecc_check(struct omap_nand_info *info,
1592                                  struct omap_nand_platform_data *pdata)
1593 {
1594         bool ecc_needs_bch, ecc_needs_omap_bch, ecc_needs_elm;
1595 
1596         switch (info->ecc_opt) {
1597         case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1598         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1599                 ecc_needs_omap_bch = false;
1600                 ecc_needs_bch = true;
1601                 ecc_needs_elm = false;
1602                 break;
1603         case OMAP_ECC_BCH4_CODE_HW:
1604         case OMAP_ECC_BCH8_CODE_HW:
1605         case OMAP_ECC_BCH16_CODE_HW:
1606                 ecc_needs_omap_bch = true;
1607                 ecc_needs_bch = false;
1608                 ecc_needs_elm = true;
1609                 break;
1610         default:
1611                 ecc_needs_omap_bch = false;
1612                 ecc_needs_bch = false;
1613                 ecc_needs_elm = false;
1614                 break;
1615         }
1616 
1617         if (ecc_needs_bch && !IS_ENABLED(CONFIG_MTD_NAND_ECC_BCH)) {
1618                 dev_err(&info->pdev->dev,
1619                         "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
1620                 return false;
1621         }
1622         if (ecc_needs_omap_bch && !IS_ENABLED(CONFIG_MTD_NAND_OMAP_BCH)) {
1623                 dev_err(&info->pdev->dev,
1624                         "CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1625                 return false;
1626         }
1627         if (ecc_needs_elm && !is_elm_present(info, info->elm_of_node)) {
1628                 dev_err(&info->pdev->dev, "ELM not available\n");
1629                 return false;
1630         }
1631 
1632         return true;
1633 }
1634 
1635 static const char * const nand_xfer_types[] = {
1636         [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled",
1637         [NAND_OMAP_POLLED] = "polled",
1638         [NAND_OMAP_PREFETCH_DMA] = "prefetch-dma",
1639         [NAND_OMAP_PREFETCH_IRQ] = "prefetch-irq",
1640 };
1641 
1642 static int omap_get_dt_info(struct device *dev, struct omap_nand_info *info)
1643 {
1644         struct device_node *child = dev->of_node;
1645         int i;
1646         const char *s;
1647         u32 cs;
1648 
1649         if (of_property_read_u32(child, "reg", &cs) < 0) {
1650                 dev_err(dev, "reg not found in DT\n");
1651                 return -EINVAL;
1652         }
1653 
1654         info->gpmc_cs = cs;
1655 
1656         /* detect availability of ELM module. Won't be present pre-OMAP4 */
1657         info->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0);
1658         if (!info->elm_of_node) {
1659                 info->elm_of_node = of_parse_phandle(child, "elm_id", 0);
1660                 if (!info->elm_of_node)
1661                         dev_dbg(dev, "ti,elm-id not in DT\n");
1662         }
1663 
1664         /* select ecc-scheme for NAND */
1665         if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) {
1666                 dev_err(dev, "ti,nand-ecc-opt not found\n");
1667                 return -EINVAL;
1668         }
1669 
1670         if (!strcmp(s, "sw")) {
1671                 info->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
1672         } else if (!strcmp(s, "ham1") ||
1673                    !strcmp(s, "hw") || !strcmp(s, "hw-romcode")) {
1674                 info->ecc_opt = OMAP_ECC_HAM1_CODE_HW;
1675         } else if (!strcmp(s, "bch4")) {
1676                 if (info->elm_of_node)
1677                         info->ecc_opt = OMAP_ECC_BCH4_CODE_HW;
1678                 else
1679                         info->ecc_opt = OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;
1680         } else if (!strcmp(s, "bch8")) {
1681                 if (info->elm_of_node)
1682                         info->ecc_opt = OMAP_ECC_BCH8_CODE_HW;
1683                 else
1684                         info->ecc_opt = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
1685         } else if (!strcmp(s, "bch16")) {
1686                 info->ecc_opt = OMAP_ECC_BCH16_CODE_HW;
1687         } else {
1688                 dev_err(dev, "unrecognized value for ti,nand-ecc-opt\n");
1689                 return -EINVAL;
1690         }
1691 
1692         /* select data transfer mode */
1693         if (!of_property_read_string(child, "ti,nand-xfer-type", &s)) {
1694                 for (i = 0; i < ARRAY_SIZE(nand_xfer_types); i++) {
1695                         if (!strcasecmp(s, nand_xfer_types[i])) {
1696                                 info->xfer_type = i;
1697                                 return 0;
1698                         }
1699                 }
1700 
1701                 dev_err(dev, "unrecognized value for ti,nand-xfer-type\n");
1702                 return -EINVAL;
1703         }
1704 
1705         return 0;
1706 }
1707 
1708 static int omap_ooblayout_ecc(struct mtd_info *mtd, int section,
1709                               struct mtd_oob_region *oobregion)
1710 {
1711         struct omap_nand_info *info = mtd_to_omap(mtd);
1712         struct nand_chip *chip = &info->nand;
1713         int off = BADBLOCK_MARKER_LENGTH;
1714 
1715         if (info->ecc_opt == OMAP_ECC_HAM1_CODE_HW &&
1716             !(chip->options & NAND_BUSWIDTH_16))
1717                 off = 1;
1718 
1719         if (section)
1720                 return -ERANGE;
1721 
1722         oobregion->offset = off;
1723         oobregion->length = chip->ecc.total;
1724 
1725         return 0;
1726 }
1727 
1728 static int omap_ooblayout_free(struct mtd_info *mtd, int section,
1729                                struct mtd_oob_region *oobregion)
1730 {
1731         struct omap_nand_info *info = mtd_to_omap(mtd);
1732         struct nand_chip *chip = &info->nand;
1733         int off = BADBLOCK_MARKER_LENGTH;
1734 
1735         if (info->ecc_opt == OMAP_ECC_HAM1_CODE_HW &&
1736             !(chip->options & NAND_BUSWIDTH_16))
1737                 off = 1;
1738 
1739         if (section)
1740                 return -ERANGE;
1741 
1742         off += chip->ecc.total;
1743         if (off >= mtd->oobsize)
1744                 return -ERANGE;
1745 
1746         oobregion->offset = off;
1747         oobregion->length = mtd->oobsize - off;
1748 
1749         return 0;
1750 }
1751 
1752 static const struct mtd_ooblayout_ops omap_ooblayout_ops = {
1753         .ecc = omap_ooblayout_ecc,
1754         .free = omap_ooblayout_free,
1755 };
1756 
1757 static int omap_sw_ooblayout_ecc(struct mtd_info *mtd, int section,
1758                                  struct mtd_oob_region *oobregion)
1759 {
1760         struct nand_chip *chip = mtd_to_nand(mtd);
1761         int off = BADBLOCK_MARKER_LENGTH;
1762 
1763         if (section >= chip->ecc.steps)
1764                 return -ERANGE;
1765 
1766         /*
1767          * When SW correction is employed, one OMAP specific marker byte is
1768          * reserved after each ECC step.
1769          */
1770         oobregion->offset = off + (section * (chip->ecc.bytes + 1));
1771         oobregion->length = chip->ecc.bytes;
1772 
1773         return 0;
1774 }
1775 
1776 static int omap_sw_ooblayout_free(struct mtd_info *mtd, int section,
1777                                   struct mtd_oob_region *oobregion)
1778 {
1779         struct nand_chip *chip = mtd_to_nand(mtd);
1780         int off = BADBLOCK_MARKER_LENGTH;
1781 
1782         if (section)
1783                 return -ERANGE;
1784 
1785         /*
1786          * When SW correction is employed, one OMAP specific marker byte is
1787          * reserved after each ECC step.
1788          */
1789         off += ((chip->ecc.bytes + 1) * chip->ecc.steps);
1790         if (off >= mtd->oobsize)
1791                 return -ERANGE;
1792 
1793         oobregion->offset = off;
1794         oobregion->length = mtd->oobsize - off;
1795 
1796         return 0;
1797 }
1798 
1799 static const struct mtd_ooblayout_ops omap_sw_ooblayout_ops = {
1800         .ecc = omap_sw_ooblayout_ecc,
1801         .free = omap_sw_ooblayout_free,
1802 };
1803 
1804 static int omap_nand_probe(struct platform_device *pdev)
1805 {
1806         struct omap_nand_info           *info;
1807         struct omap_nand_platform_data  *pdata = NULL;
1808         struct mtd_info                 *mtd;
1809         struct nand_chip                *nand_chip;
1810         int                             err;
1811         dma_cap_mask_t                  mask;
1812         struct resource                 *res;
1813         struct device                   *dev = &pdev->dev;
1814         int                             min_oobbytes = BADBLOCK_MARKER_LENGTH;
1815         int                             oobbytes_per_step;
1816 
1817         info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info),
1818                                 GFP_KERNEL);
1819         if (!info)
1820                 return -ENOMEM;
1821 
1822         info->pdev = pdev;
1823 
1824         if (dev->of_node) {
1825                 if (omap_get_dt_info(dev, info))
1826                         return -EINVAL;
1827         } else {
1828                 pdata = dev_get_platdata(&pdev->dev);
1829                 if (!pdata) {
1830                         dev_err(&pdev->dev, "platform data missing\n");
1831                         return -EINVAL;
1832                 }
1833 
1834                 info->gpmc_cs = pdata->cs;
1835                 info->reg = pdata->reg;
1836                 info->ecc_opt = pdata->ecc_opt;
1837                 if (pdata->dev_ready)
1838                         dev_info(&pdev->dev, "pdata->dev_ready is deprecated\n");
1839 
1840                 info->xfer_type = pdata->xfer_type;
1841                 info->devsize = pdata->devsize;
1842                 info->elm_of_node = pdata->elm_of_node;
1843                 info->flash_bbt = pdata->flash_bbt;
1844         }
1845 
1846         platform_set_drvdata(pdev, info);
1847         info->ops = gpmc_omap_get_nand_ops(&info->reg, info->gpmc_cs);
1848         if (!info->ops) {
1849                 dev_err(&pdev->dev, "Failed to get GPMC->NAND interface\n");
1850                 return -ENODEV;
1851         }
1852 
1853         nand_chip               = &info->nand;
1854         mtd                     = nand_to_mtd(nand_chip);
1855         mtd->dev.parent         = &pdev->dev;
1856         nand_chip->ecc.priv     = NULL;
1857         nand_set_flash_node(nand_chip, dev->of_node);
1858 
1859         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1860         nand_chip->IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res);
1861         if (IS_ERR(nand_chip->IO_ADDR_R))
1862                 return PTR_ERR(nand_chip->IO_ADDR_R);
1863 
1864         info->phys_base = res->start;
1865 
1866         nand_chip->controller = &omap_gpmc_controller;
1867 
1868         nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R;
1869         nand_chip->cmd_ctrl  = omap_hwcontrol;
1870 
1871         info->ready_gpiod = devm_gpiod_get_optional(&pdev->dev, "rb",
1872                                                     GPIOD_IN);
1873         if (IS_ERR(info->ready_gpiod)) {
1874                 dev_err(dev, "failed to get ready gpio\n");
1875                 return PTR_ERR(info->ready_gpiod);
1876         }
1877 
1878         /*
1879          * If RDY/BSY line is connected to OMAP then use the omap ready
1880          * function and the generic nand_wait function which reads the status
1881          * register after monitoring the RDY/BSY line. Otherwise use a standard
1882          * chip delay which is slightly more than tR (AC Timing) of the NAND
1883          * device and read status register until you get a failure or success
1884          */
1885         if (info->ready_gpiod) {
1886                 nand_chip->dev_ready = omap_dev_ready;
1887                 nand_chip->chip_delay = 0;
1888         } else {
1889                 nand_chip->waitfunc = omap_wait;
1890                 nand_chip->chip_delay = 50;
1891         }
1892 
1893         if (info->flash_bbt)
1894                 nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
1895 
1896         /* scan NAND device connected to chip controller */
1897         nand_chip->options |= info->devsize & NAND_BUSWIDTH_16;
1898         if (nand_scan_ident(mtd, 1, NULL)) {
1899                 dev_err(&info->pdev->dev,
1900                         "scan failed, may be bus-width mismatch\n");
1901                 err = -ENXIO;
1902                 goto return_error;
1903         }
1904 
1905         if (nand_chip->bbt_options & NAND_BBT_USE_FLASH)
1906                 nand_chip->bbt_options |= NAND_BBT_NO_OOB;
1907         else
1908                 nand_chip->options |= NAND_SKIP_BBTSCAN;
1909 
1910         /* re-populate low-level callbacks based on xfer modes */
1911         switch (info->xfer_type) {
1912         case NAND_OMAP_PREFETCH_POLLED:
1913                 nand_chip->read_buf   = omap_read_buf_pref;
1914                 nand_chip->write_buf  = omap_write_buf_pref;
1915                 break;
1916 
1917         case NAND_OMAP_POLLED:
1918                 /* Use nand_base defaults for {read,write}_buf */
1919                 break;
1920 
1921         case NAND_OMAP_PREFETCH_DMA:
1922                 dma_cap_zero(mask);
1923                 dma_cap_set(DMA_SLAVE, mask);
1924                 info->dma = dma_request_chan(pdev->dev.parent, "rxtx");
1925 
1926                 if (IS_ERR(info->dma)) {
1927                         dev_err(&pdev->dev, "DMA engine request failed\n");
1928                         err = PTR_ERR(info->dma);
1929                         goto return_error;
1930                 } else {
1931                         struct dma_slave_config cfg;
1932 
1933                         memset(&cfg, 0, sizeof(cfg));
1934                         cfg.src_addr = info->phys_base;
1935                         cfg.dst_addr = info->phys_base;
1936                         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1937                         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1938                         cfg.src_maxburst = 16;
1939                         cfg.dst_maxburst = 16;
1940                         err = dmaengine_slave_config(info->dma, &cfg);
1941                         if (err) {
1942                                 dev_err(&pdev->dev, "DMA engine slave config failed: %d\n",
1943                                         err);
1944                                 goto return_error;
1945                         }
1946                         nand_chip->read_buf   = omap_read_buf_dma_pref;
1947                         nand_chip->write_buf  = omap_write_buf_dma_pref;
1948                 }
1949                 break;
1950 
1951         case NAND_OMAP_PREFETCH_IRQ:
1952                 info->gpmc_irq_fifo = platform_get_irq(pdev, 0);
1953                 if (info->gpmc_irq_fifo <= 0) {
1954                         dev_err(&pdev->dev, "error getting fifo irq\n");
1955                         err = -ENODEV;
1956                         goto return_error;
1957                 }
1958                 err = devm_request_irq(&pdev->dev, info->gpmc_irq_fifo,
1959                                         omap_nand_irq, IRQF_SHARED,
1960                                         "gpmc-nand-fifo", info);
1961                 if (err) {
1962                         dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1963                                                 info->gpmc_irq_fifo, err);
1964                         info->gpmc_irq_fifo = 0;
1965                         goto return_error;
1966                 }
1967 
1968                 info->gpmc_irq_count = platform_get_irq(pdev, 1);
1969                 if (info->gpmc_irq_count <= 0) {
1970                         dev_err(&pdev->dev, "error getting count irq\n");
1971                         err = -ENODEV;
1972                         goto return_error;
1973                 }
1974                 err = devm_request_irq(&pdev->dev, info->gpmc_irq_count,
1975                                         omap_nand_irq, IRQF_SHARED,
1976                                         "gpmc-nand-count", info);
1977                 if (err) {
1978                         dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1979                                                 info->gpmc_irq_count, err);
1980                         info->gpmc_irq_count = 0;
1981                         goto return_error;
1982                 }
1983 
1984                 nand_chip->read_buf  = omap_read_buf_irq_pref;
1985                 nand_chip->write_buf = omap_write_buf_irq_pref;
1986 
1987                 break;
1988 
1989         default:
1990                 dev_err(&pdev->dev,
1991                         "xfer_type(%d) not supported!\n", info->xfer_type);
1992                 err = -EINVAL;
1993                 goto return_error;
1994         }
1995 
1996         if (!omap2_nand_ecc_check(info, pdata)) {
1997                 err = -EINVAL;
1998                 goto return_error;
1999         }
2000 
2001         /*
2002          * Bail out earlier to let NAND_ECC_SOFT code create its own
2003          * ooblayout instead of using ours.
2004          */
2005         if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW) {
2006                 nand_chip->ecc.mode = NAND_ECC_SOFT;
2007                 nand_chip->ecc.algo = NAND_ECC_HAMMING;
2008                 goto scan_tail;
2009         }
2010 
2011         /* populate MTD interface based on ECC scheme */
2012         switch (info->ecc_opt) {
2013         case OMAP_ECC_HAM1_CODE_HW:
2014                 pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n");
2015                 nand_chip->ecc.mode             = NAND_ECC_HW;
2016                 nand_chip->ecc.bytes            = 3;
2017                 nand_chip->ecc.size             = 512;
2018                 nand_chip->ecc.strength         = 1;
2019                 nand_chip->ecc.calculate        = omap_calculate_ecc;
2020                 nand_chip->ecc.hwctl            = omap_enable_hwecc;
2021                 nand_chip->ecc.correct          = omap_correct_data;
2022                 mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
2023                 oobbytes_per_step               = nand_chip->ecc.bytes;
2024 
2025                 if (!(nand_chip->options & NAND_BUSWIDTH_16))
2026                         min_oobbytes            = 1;
2027 
2028                 break;
2029 
2030         case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
2031                 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n");
2032                 nand_chip->ecc.mode             = NAND_ECC_HW;
2033                 nand_chip->ecc.size             = 512;
2034                 nand_chip->ecc.bytes            = 7;
2035                 nand_chip->ecc.strength         = 4;
2036                 nand_chip->ecc.hwctl            = omap_enable_hwecc_bch;
2037                 nand_chip->ecc.correct          = nand_bch_correct_data;
2038                 nand_chip->ecc.calculate        = omap_calculate_ecc_bch;
2039                 mtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops);
2040                 /* Reserve one byte for the OMAP marker */
2041                 oobbytes_per_step               = nand_chip->ecc.bytes + 1;
2042                 /* software bch library is used for locating errors */
2043                 nand_chip->ecc.priv             = nand_bch_init(mtd);
2044                 if (!nand_chip->ecc.priv) {
2045                         dev_err(&info->pdev->dev, "unable to use BCH library\n");
2046                         err = -EINVAL;
2047                         goto return_error;
2048                 }
2049                 break;
2050 
2051         case OMAP_ECC_BCH4_CODE_HW:
2052                 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n");
2053                 nand_chip->ecc.mode             = NAND_ECC_HW;
2054                 nand_chip->ecc.size             = 512;
2055                 /* 14th bit is kept reserved for ROM-code compatibility */
2056                 nand_chip->ecc.bytes            = 7 + 1;
2057                 nand_chip->ecc.strength         = 4;
2058                 nand_chip->ecc.hwctl            = omap_enable_hwecc_bch;
2059                 nand_chip->ecc.correct          = omap_elm_correct_data;
2060                 nand_chip->ecc.calculate        = omap_calculate_ecc_bch;
2061                 nand_chip->ecc.read_page        = omap_read_page_bch;
2062                 nand_chip->ecc.write_page       = omap_write_page_bch;
2063                 mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
2064                 oobbytes_per_step               = nand_chip->ecc.bytes;
2065 
2066                 err = elm_config(info->elm_dev, BCH4_ECC,
2067                                  mtd->writesize / nand_chip->ecc.size,
2068                                  nand_chip->ecc.size, nand_chip->ecc.bytes);
2069                 if (err < 0)
2070                         goto return_error;
2071                 break;
2072 
2073         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
2074                 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
2075                 nand_chip->ecc.mode             = NAND_ECC_HW;
2076                 nand_chip->ecc.size             = 512;
2077                 nand_chip->ecc.bytes            = 13;
2078                 nand_chip->ecc.strength         = 8;
2079                 nand_chip->ecc.hwctl            = omap_enable_hwecc_bch;
2080                 nand_chip->ecc.correct          = nand_bch_correct_data;
2081                 nand_chip->ecc.calculate        = omap_calculate_ecc_bch;
2082                 mtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops);
2083                 /* Reserve one byte for the OMAP marker */
2084                 oobbytes_per_step               = nand_chip->ecc.bytes + 1;
2085                 /* software bch library is used for locating errors */
2086                 nand_chip->ecc.priv             = nand_bch_init(mtd);
2087                 if (!nand_chip->ecc.priv) {
2088                         dev_err(&info->pdev->dev, "unable to use BCH library\n");
2089                         err = -EINVAL;
2090                         goto return_error;
2091                 }
2092                 break;
2093 
2094         case OMAP_ECC_BCH8_CODE_HW:
2095                 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n");
2096                 nand_chip->ecc.mode             = NAND_ECC_HW;
2097                 nand_chip->ecc.size             = 512;
2098                 /* 14th bit is kept reserved for ROM-code compatibility */
2099                 nand_chip->ecc.bytes            = 13 + 1;
2100                 nand_chip->ecc.strength         = 8;
2101                 nand_chip->ecc.hwctl            = omap_enable_hwecc_bch;
2102                 nand_chip->ecc.correct          = omap_elm_correct_data;
2103                 nand_chip->ecc.calculate        = omap_calculate_ecc_bch;
2104                 nand_chip->ecc.read_page        = omap_read_page_bch;
2105                 nand_chip->ecc.write_page       = omap_write_page_bch;
2106                 mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
2107                 oobbytes_per_step               = nand_chip->ecc.bytes;
2108 
2109                 err = elm_config(info->elm_dev, BCH8_ECC,
2110                                  mtd->writesize / nand_chip->ecc.size,
2111                                  nand_chip->ecc.size, nand_chip->ecc.bytes);
2112                 if (err < 0)
2113                         goto return_error;
2114 
2115                 break;
2116 
2117         case OMAP_ECC_BCH16_CODE_HW:
2118                 pr_info("using OMAP_ECC_BCH16_CODE_HW ECC scheme\n");
2119                 nand_chip->ecc.mode             = NAND_ECC_HW;
2120                 nand_chip->ecc.size             = 512;
2121                 nand_chip->ecc.bytes            = 26;
2122                 nand_chip->ecc.strength         = 16;
2123                 nand_chip->ecc.hwctl            = omap_enable_hwecc_bch;
2124                 nand_chip->ecc.correct          = omap_elm_correct_data;
2125                 nand_chip->ecc.calculate        = omap_calculate_ecc_bch;
2126                 nand_chip->ecc.read_page        = omap_read_page_bch;
2127                 nand_chip->ecc.write_page       = omap_write_page_bch;
2128                 mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
2129                 oobbytes_per_step               = nand_chip->ecc.bytes;
2130 
2131                 err = elm_config(info->elm_dev, BCH16_ECC,
2132                                  mtd->writesize / nand_chip->ecc.size,
2133                                  nand_chip->ecc.size, nand_chip->ecc.bytes);
2134                 if (err < 0)
2135                         goto return_error;
2136 
2137                 break;
2138         default:
2139                 dev_err(&info->pdev->dev, "invalid or unsupported ECC scheme\n");
2140                 err = -EINVAL;
2141                 goto return_error;
2142         }
2143 
2144         /* check if NAND device's OOB is enough to store ECC signatures */
2145         min_oobbytes += (oobbytes_per_step *
2146                          (mtd->writesize / nand_chip->ecc.size));
2147         if (mtd->oobsize < min_oobbytes) {
2148                 dev_err(&info->pdev->dev,
2149                         "not enough OOB bytes required = %d, available=%d\n",
2150                         min_oobbytes, mtd->oobsize);
2151                 err = -EINVAL;
2152                 goto return_error;
2153         }
2154 
2155 scan_tail:
2156         /* second phase scan */
2157         if (nand_scan_tail(mtd)) {
2158                 err = -ENXIO;
2159                 goto return_error;
2160         }
2161 
2162         if (dev->of_node)
2163                 mtd_device_register(mtd, NULL, 0);
2164         else
2165                 mtd_device_register(mtd, pdata->parts, pdata->nr_parts);
2166 
2167         platform_set_drvdata(pdev, mtd);
2168 
2169         return 0;
2170 
2171 return_error:
2172         if (!IS_ERR_OR_NULL(info->dma))
2173                 dma_release_channel(info->dma);
2174         if (nand_chip->ecc.priv) {
2175                 nand_bch_free(nand_chip->ecc.priv);
2176                 nand_chip->ecc.priv = NULL;
2177         }
2178         return err;
2179 }
2180 
2181 static int omap_nand_remove(struct platform_device *pdev)
2182 {
2183         struct mtd_info *mtd = platform_get_drvdata(pdev);
2184         struct nand_chip *nand_chip = mtd_to_nand(mtd);
2185         struct omap_nand_info *info = mtd_to_omap(mtd);
2186         if (nand_chip->ecc.priv) {
2187                 nand_bch_free(nand_chip->ecc.priv);
2188                 nand_chip->ecc.priv = NULL;
2189         }
2190         if (info->dma)
2191                 dma_release_channel(info->dma);
2192         nand_release(mtd);
2193         return 0;
2194 }
2195 
2196 static const struct of_device_id omap_nand_ids[] = {
2197         { .compatible = "ti,omap2-nand", },
2198         {},
2199 };
2200 
2201 static struct platform_driver omap_nand_driver = {
2202         .probe          = omap_nand_probe,
2203         .remove         = omap_nand_remove,
2204         .driver         = {
2205                 .name   = DRIVER_NAME,
2206                 .of_match_table = of_match_ptr(omap_nand_ids),
2207         },
2208 };
2209 
2210 module_platform_driver(omap_nand_driver);
2211 
2212 MODULE_ALIAS("platform:" DRIVER_NAME);
2213 MODULE_LICENSE("GPL");
2214 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");
2215 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us