Version:  2.0.40 2.2.26 2.4.37 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7

Linux/drivers/mtd/nand/omap2.c

  1 /*
  2  * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
  3  * Copyright © 2004 Micron Technology Inc.
  4  * Copyright © 2004 David Brownell
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License version 2 as
  8  * published by the Free Software Foundation.
  9  */
 10 
 11 #include <linux/platform_device.h>
 12 #include <linux/dmaengine.h>
 13 #include <linux/dma-mapping.h>
 14 #include <linux/delay.h>
 15 #include <linux/gpio/consumer.h>
 16 #include <linux/module.h>
 17 #include <linux/interrupt.h>
 18 #include <linux/jiffies.h>
 19 #include <linux/sched.h>
 20 #include <linux/mtd/mtd.h>
 21 #include <linux/mtd/nand.h>
 22 #include <linux/mtd/partitions.h>
 23 #include <linux/omap-dma.h>
 24 #include <linux/io.h>
 25 #include <linux/slab.h>
 26 #include <linux/of.h>
 27 #include <linux/of_device.h>
 28 
 29 #include <linux/mtd/nand_bch.h>
 30 #include <linux/platform_data/elm.h>
 31 
 32 #include <linux/omap-gpmc.h>
 33 #include <linux/platform_data/mtd-nand-omap2.h>
 34 
 35 #define DRIVER_NAME     "omap2-nand"
 36 #define OMAP_NAND_TIMEOUT_MS    5000
 37 
 38 #define NAND_Ecc_P1e            (1 << 0)
 39 #define NAND_Ecc_P2e            (1 << 1)
 40 #define NAND_Ecc_P4e            (1 << 2)
 41 #define NAND_Ecc_P8e            (1 << 3)
 42 #define NAND_Ecc_P16e           (1 << 4)
 43 #define NAND_Ecc_P32e           (1 << 5)
 44 #define NAND_Ecc_P64e           (1 << 6)
 45 #define NAND_Ecc_P128e          (1 << 7)
 46 #define NAND_Ecc_P256e          (1 << 8)
 47 #define NAND_Ecc_P512e          (1 << 9)
 48 #define NAND_Ecc_P1024e         (1 << 10)
 49 #define NAND_Ecc_P2048e         (1 << 11)
 50 
 51 #define NAND_Ecc_P1o            (1 << 16)
 52 #define NAND_Ecc_P2o            (1 << 17)
 53 #define NAND_Ecc_P4o            (1 << 18)
 54 #define NAND_Ecc_P8o            (1 << 19)
 55 #define NAND_Ecc_P16o           (1 << 20)
 56 #define NAND_Ecc_P32o           (1 << 21)
 57 #define NAND_Ecc_P64o           (1 << 22)
 58 #define NAND_Ecc_P128o          (1 << 23)
 59 #define NAND_Ecc_P256o          (1 << 24)
 60 #define NAND_Ecc_P512o          (1 << 25)
 61 #define NAND_Ecc_P1024o         (1 << 26)
 62 #define NAND_Ecc_P2048o         (1 << 27)
 63 
 64 #define TF(value)       (value ? 1 : 0)
 65 
 66 #define P2048e(a)       (TF(a & NAND_Ecc_P2048e)        << 0)
 67 #define P2048o(a)       (TF(a & NAND_Ecc_P2048o)        << 1)
 68 #define P1e(a)          (TF(a & NAND_Ecc_P1e)           << 2)
 69 #define P1o(a)          (TF(a & NAND_Ecc_P1o)           << 3)
 70 #define P2e(a)          (TF(a & NAND_Ecc_P2e)           << 4)
 71 #define P2o(a)          (TF(a & NAND_Ecc_P2o)           << 5)
 72 #define P4e(a)          (TF(a & NAND_Ecc_P4e)           << 6)
 73 #define P4o(a)          (TF(a & NAND_Ecc_P4o)           << 7)
 74 
 75 #define P8e(a)          (TF(a & NAND_Ecc_P8e)           << 0)
 76 #define P8o(a)          (TF(a & NAND_Ecc_P8o)           << 1)
 77 #define P16e(a)         (TF(a & NAND_Ecc_P16e)          << 2)
 78 #define P16o(a)         (TF(a & NAND_Ecc_P16o)          << 3)
 79 #define P32e(a)         (TF(a & NAND_Ecc_P32e)          << 4)
 80 #define P32o(a)         (TF(a & NAND_Ecc_P32o)          << 5)
 81 #define P64e(a)         (TF(a & NAND_Ecc_P64e)          << 6)
 82 #define P64o(a)         (TF(a & NAND_Ecc_P64o)          << 7)
 83 
 84 #define P128e(a)        (TF(a & NAND_Ecc_P128e)         << 0)
 85 #define P128o(a)        (TF(a & NAND_Ecc_P128o)         << 1)
 86 #define P256e(a)        (TF(a & NAND_Ecc_P256e)         << 2)
 87 #define P256o(a)        (TF(a & NAND_Ecc_P256o)         << 3)
 88 #define P512e(a)        (TF(a & NAND_Ecc_P512e)         << 4)
 89 #define P512o(a)        (TF(a & NAND_Ecc_P512o)         << 5)
 90 #define P1024e(a)       (TF(a & NAND_Ecc_P1024e)        << 6)
 91 #define P1024o(a)       (TF(a & NAND_Ecc_P1024o)        << 7)
 92 
 93 #define P8e_s(a)        (TF(a & NAND_Ecc_P8e)           << 0)
 94 #define P8o_s(a)        (TF(a & NAND_Ecc_P8o)           << 1)
 95 #define P16e_s(a)       (TF(a & NAND_Ecc_P16e)          << 2)
 96 #define P16o_s(a)       (TF(a & NAND_Ecc_P16o)          << 3)
 97 #define P1e_s(a)        (TF(a & NAND_Ecc_P1e)           << 4)
 98 #define P1o_s(a)        (TF(a & NAND_Ecc_P1o)           << 5)
 99 #define P2e_s(a)        (TF(a & NAND_Ecc_P2e)           << 6)
100 #define P2o_s(a)        (TF(a & NAND_Ecc_P2o)           << 7)
101 
102 #define P4e_s(a)        (TF(a & NAND_Ecc_P4e)           << 0)
103 #define P4o_s(a)        (TF(a & NAND_Ecc_P4o)           << 1)
104 
105 #define PREFETCH_CONFIG1_CS_SHIFT       24
106 #define ECC_CONFIG_CS_SHIFT             1
107 #define CS_MASK                         0x7
108 #define ENABLE_PREFETCH                 (0x1 << 7)
109 #define DMA_MPU_MODE_SHIFT              2
110 #define ECCSIZE0_SHIFT                  12
111 #define ECCSIZE1_SHIFT                  22
112 #define ECC1RESULTSIZE                  0x1
113 #define ECCCLEAR                        0x100
114 #define ECC1                            0x1
115 #define PREFETCH_FIFOTHRESHOLD_MAX      0x40
116 #define PREFETCH_FIFOTHRESHOLD(val)     ((val) << 8)
117 #define PREFETCH_STATUS_COUNT(val)      (val & 0x00003fff)
118 #define PREFETCH_STATUS_FIFO_CNT(val)   ((val >> 24) & 0x7F)
119 #define STATUS_BUFF_EMPTY               0x00000001
120 
121 #define OMAP24XX_DMA_GPMC               4
122 
123 #define SECTOR_BYTES            512
124 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
125 #define BCH4_BIT_PAD            4
126 
127 /* GPMC ecc engine settings for read */
128 #define BCH_WRAPMODE_1          1       /* BCH wrap mode 1 */
129 #define BCH8R_ECC_SIZE0         0x1a    /* ecc_size0 = 26 */
130 #define BCH8R_ECC_SIZE1         0x2     /* ecc_size1 = 2 */
131 #define BCH4R_ECC_SIZE0         0xd     /* ecc_size0 = 13 */
132 #define BCH4R_ECC_SIZE1         0x3     /* ecc_size1 = 3 */
133 
134 /* GPMC ecc engine settings for write */
135 #define BCH_WRAPMODE_6          6       /* BCH wrap mode 6 */
136 #define BCH_ECC_SIZE0           0x0     /* ecc_size0 = 0, no oob protection */
137 #define BCH_ECC_SIZE1           0x20    /* ecc_size1 = 32 */
138 
139 #define BADBLOCK_MARKER_LENGTH          2
140 
141 static u_char bch16_vector[] = {0xf5, 0x24, 0x1c, 0xd0, 0x61, 0xb3, 0xf1, 0x55,
142                                 0x2e, 0x2c, 0x86, 0xa3, 0xed, 0x36, 0x1b, 0x78,
143                                 0x48, 0x76, 0xa9, 0x3b, 0x97, 0xd1, 0x7a, 0x93,
144                                 0x07, 0x0e};
145 static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
146         0xac, 0x6b, 0xff, 0x99, 0x7b};
147 static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
148 
149 /* Shared among all NAND instances to synchronize access to the ECC Engine */
150 static struct nand_hw_control omap_gpmc_controller = {
151         .lock = __SPIN_LOCK_UNLOCKED(omap_gpmc_controller.lock),
152         .wq = __WAIT_QUEUE_HEAD_INITIALIZER(omap_gpmc_controller.wq),
153 };
154 
155 struct omap_nand_info {
156         struct nand_chip                nand;
157         struct platform_device          *pdev;
158 
159         int                             gpmc_cs;
160         bool                            dev_ready;
161         enum nand_io                    xfer_type;
162         int                             devsize;
163         enum omap_ecc                   ecc_opt;
164         struct device_node              *elm_of_node;
165 
166         unsigned long                   phys_base;
167         struct completion               comp;
168         struct dma_chan                 *dma;
169         int                             gpmc_irq_fifo;
170         int                             gpmc_irq_count;
171         enum {
172                 OMAP_NAND_IO_READ = 0,  /* read */
173                 OMAP_NAND_IO_WRITE,     /* write */
174         } iomode;
175         u_char                          *buf;
176         int                                     buf_len;
177         /* Interface to GPMC */
178         struct gpmc_nand_regs           reg;
179         struct gpmc_nand_ops            *ops;
180         bool                            flash_bbt;
181         /* fields specific for BCHx_HW ECC scheme */
182         struct device                   *elm_dev;
183         /* NAND ready gpio */
184         struct gpio_desc                *ready_gpiod;
185 };
186 
187 static inline struct omap_nand_info *mtd_to_omap(struct mtd_info *mtd)
188 {
189         return container_of(mtd_to_nand(mtd), struct omap_nand_info, nand);
190 }
191 
192 /**
193  * omap_prefetch_enable - configures and starts prefetch transfer
194  * @cs: cs (chip select) number
195  * @fifo_th: fifo threshold to be used for read/ write
196  * @dma_mode: dma mode enable (1) or disable (0)
197  * @u32_count: number of bytes to be transferred
198  * @is_write: prefetch read(0) or write post(1) mode
199  */
200 static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode,
201         unsigned int u32_count, int is_write, struct omap_nand_info *info)
202 {
203         u32 val;
204 
205         if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
206                 return -1;
207 
208         if (readl(info->reg.gpmc_prefetch_control))
209                 return -EBUSY;
210 
211         /* Set the amount of bytes to be prefetched */
212         writel(u32_count, info->reg.gpmc_prefetch_config2);
213 
214         /* Set dma/mpu mode, the prefetch read / post write and
215          * enable the engine. Set which cs is has requested for.
216          */
217         val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) |
218                 PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH |
219                 (dma_mode << DMA_MPU_MODE_SHIFT) | (is_write & 0x1));
220         writel(val, info->reg.gpmc_prefetch_config1);
221 
222         /*  Start the prefetch engine */
223         writel(0x1, info->reg.gpmc_prefetch_control);
224 
225         return 0;
226 }
227 
228 /**
229  * omap_prefetch_reset - disables and stops the prefetch engine
230  */
231 static int omap_prefetch_reset(int cs, struct omap_nand_info *info)
232 {
233         u32 config1;
234 
235         /* check if the same module/cs is trying to reset */
236         config1 = readl(info->reg.gpmc_prefetch_config1);
237         if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs)
238                 return -EINVAL;
239 
240         /* Stop the PFPW engine */
241         writel(0x0, info->reg.gpmc_prefetch_control);
242 
243         /* Reset/disable the PFPW engine */
244         writel(0x0, info->reg.gpmc_prefetch_config1);
245 
246         return 0;
247 }
248 
249 /**
250  * omap_hwcontrol - hardware specific access to control-lines
251  * @mtd: MTD device structure
252  * @cmd: command to device
253  * @ctrl:
254  * NAND_NCE: bit 0 -> don't care
255  * NAND_CLE: bit 1 -> Command Latch
256  * NAND_ALE: bit 2 -> Address Latch
257  *
258  * NOTE: boards may use different bits for these!!
259  */
260 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
261 {
262         struct omap_nand_info *info = mtd_to_omap(mtd);
263 
264         if (cmd != NAND_CMD_NONE) {
265                 if (ctrl & NAND_CLE)
266                         writeb(cmd, info->reg.gpmc_nand_command);
267 
268                 else if (ctrl & NAND_ALE)
269                         writeb(cmd, info->reg.gpmc_nand_address);
270 
271                 else /* NAND_NCE */
272                         writeb(cmd, info->reg.gpmc_nand_data);
273         }
274 }
275 
276 /**
277  * omap_read_buf8 - read data from NAND controller into buffer
278  * @mtd: MTD device structure
279  * @buf: buffer to store date
280  * @len: number of bytes to read
281  */
282 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
283 {
284         struct nand_chip *nand = mtd_to_nand(mtd);
285 
286         ioread8_rep(nand->IO_ADDR_R, buf, len);
287 }
288 
289 /**
290  * omap_write_buf8 - write buffer to NAND controller
291  * @mtd: MTD device structure
292  * @buf: data buffer
293  * @len: number of bytes to write
294  */
295 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
296 {
297         struct omap_nand_info *info = mtd_to_omap(mtd);
298         u_char *p = (u_char *)buf;
299         bool status;
300 
301         while (len--) {
302                 iowrite8(*p++, info->nand.IO_ADDR_W);
303                 /* wait until buffer is available for write */
304                 do {
305                         status = info->ops->nand_writebuffer_empty();
306                 } while (!status);
307         }
308 }
309 
310 /**
311  * omap_read_buf16 - read data from NAND controller into buffer
312  * @mtd: MTD device structure
313  * @buf: buffer to store date
314  * @len: number of bytes to read
315  */
316 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
317 {
318         struct nand_chip *nand = mtd_to_nand(mtd);
319 
320         ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
321 }
322 
323 /**
324  * omap_write_buf16 - write buffer to NAND controller
325  * @mtd: MTD device structure
326  * @buf: data buffer
327  * @len: number of bytes to write
328  */
329 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
330 {
331         struct omap_nand_info *info = mtd_to_omap(mtd);
332         u16 *p = (u16 *) buf;
333         bool status;
334         /* FIXME try bursts of writesw() or DMA ... */
335         len >>= 1;
336 
337         while (len--) {
338                 iowrite16(*p++, info->nand.IO_ADDR_W);
339                 /* wait until buffer is available for write */
340                 do {
341                         status = info->ops->nand_writebuffer_empty();
342                 } while (!status);
343         }
344 }
345 
346 /**
347  * omap_read_buf_pref - read data from NAND controller into buffer
348  * @mtd: MTD device structure
349  * @buf: buffer to store date
350  * @len: number of bytes to read
351  */
352 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
353 {
354         struct omap_nand_info *info = mtd_to_omap(mtd);
355         uint32_t r_count = 0;
356         int ret = 0;
357         u32 *p = (u32 *)buf;
358 
359         /* take care of subpage reads */
360         if (len % 4) {
361                 if (info->nand.options & NAND_BUSWIDTH_16)
362                         omap_read_buf16(mtd, buf, len % 4);
363                 else
364                         omap_read_buf8(mtd, buf, len % 4);
365                 p = (u32 *) (buf + len % 4);
366                 len -= len % 4;
367         }
368 
369         /* configure and start prefetch transfer */
370         ret = omap_prefetch_enable(info->gpmc_cs,
371                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info);
372         if (ret) {
373                 /* PFPW engine is busy, use cpu copy method */
374                 if (info->nand.options & NAND_BUSWIDTH_16)
375                         omap_read_buf16(mtd, (u_char *)p, len);
376                 else
377                         omap_read_buf8(mtd, (u_char *)p, len);
378         } else {
379                 do {
380                         r_count = readl(info->reg.gpmc_prefetch_status);
381                         r_count = PREFETCH_STATUS_FIFO_CNT(r_count);
382                         r_count = r_count >> 2;
383                         ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
384                         p += r_count;
385                         len -= r_count << 2;
386                 } while (len);
387                 /* disable and stop the PFPW engine */
388                 omap_prefetch_reset(info->gpmc_cs, info);
389         }
390 }
391 
392 /**
393  * omap_write_buf_pref - write buffer to NAND controller
394  * @mtd: MTD device structure
395  * @buf: data buffer
396  * @len: number of bytes to write
397  */
398 static void omap_write_buf_pref(struct mtd_info *mtd,
399                                         const u_char *buf, int len)
400 {
401         struct omap_nand_info *info = mtd_to_omap(mtd);
402         uint32_t w_count = 0;
403         int i = 0, ret = 0;
404         u16 *p = (u16 *)buf;
405         unsigned long tim, limit;
406         u32 val;
407 
408         /* take care of subpage writes */
409         if (len % 2 != 0) {
410                 writeb(*buf, info->nand.IO_ADDR_W);
411                 p = (u16 *)(buf + 1);
412                 len--;
413         }
414 
415         /*  configure and start prefetch transfer */
416         ret = omap_prefetch_enable(info->gpmc_cs,
417                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info);
418         if (ret) {
419                 /* PFPW engine is busy, use cpu copy method */
420                 if (info->nand.options & NAND_BUSWIDTH_16)
421                         omap_write_buf16(mtd, (u_char *)p, len);
422                 else
423                         omap_write_buf8(mtd, (u_char *)p, len);
424         } else {
425                 while (len) {
426                         w_count = readl(info->reg.gpmc_prefetch_status);
427                         w_count = PREFETCH_STATUS_FIFO_CNT(w_count);
428                         w_count = w_count >> 1;
429                         for (i = 0; (i < w_count) && len; i++, len -= 2)
430                                 iowrite16(*p++, info->nand.IO_ADDR_W);
431                 }
432                 /* wait for data to flushed-out before reset the prefetch */
433                 tim = 0;
434                 limit = (loops_per_jiffy *
435                                         msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
436                 do {
437                         cpu_relax();
438                         val = readl(info->reg.gpmc_prefetch_status);
439                         val = PREFETCH_STATUS_COUNT(val);
440                 } while (val && (tim++ < limit));
441 
442                 /* disable and stop the PFPW engine */
443                 omap_prefetch_reset(info->gpmc_cs, info);
444         }
445 }
446 
447 /*
448  * omap_nand_dma_callback: callback on the completion of dma transfer
449  * @data: pointer to completion data structure
450  */
451 static void omap_nand_dma_callback(void *data)
452 {
453         complete((struct completion *) data);
454 }
455 
456 /*
457  * omap_nand_dma_transfer: configure and start dma transfer
458  * @mtd: MTD device structure
459  * @addr: virtual address in RAM of source/destination
460  * @len: number of data bytes to be transferred
461  * @is_write: flag for read/write operation
462  */
463 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
464                                         unsigned int len, int is_write)
465 {
466         struct omap_nand_info *info = mtd_to_omap(mtd);
467         struct dma_async_tx_descriptor *tx;
468         enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
469                                                         DMA_FROM_DEVICE;
470         struct scatterlist sg;
471         unsigned long tim, limit;
472         unsigned n;
473         int ret;
474         u32 val;
475 
476         if (!virt_addr_valid(addr))
477                 goto out_copy;
478 
479         sg_init_one(&sg, addr, len);
480         n = dma_map_sg(info->dma->device->dev, &sg, 1, dir);
481         if (n == 0) {
482                 dev_err(&info->pdev->dev,
483                         "Couldn't DMA map a %d byte buffer\n", len);
484                 goto out_copy;
485         }
486 
487         tx = dmaengine_prep_slave_sg(info->dma, &sg, n,
488                 is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
489                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
490         if (!tx)
491                 goto out_copy_unmap;
492 
493         tx->callback = omap_nand_dma_callback;
494         tx->callback_param = &info->comp;
495         dmaengine_submit(tx);
496 
497         init_completion(&info->comp);
498 
499         /* setup and start DMA using dma_addr */
500         dma_async_issue_pending(info->dma);
501 
502         /*  configure and start prefetch transfer */
503         ret = omap_prefetch_enable(info->gpmc_cs,
504                 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info);
505         if (ret)
506                 /* PFPW engine is busy, use cpu copy method */
507                 goto out_copy_unmap;
508 
509         wait_for_completion(&info->comp);
510         tim = 0;
511         limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
512 
513         do {
514                 cpu_relax();
515                 val = readl(info->reg.gpmc_prefetch_status);
516                 val = PREFETCH_STATUS_COUNT(val);
517         } while (val && (tim++ < limit));
518 
519         /* disable and stop the PFPW engine */
520         omap_prefetch_reset(info->gpmc_cs, info);
521 
522         dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
523         return 0;
524 
525 out_copy_unmap:
526         dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
527 out_copy:
528         if (info->nand.options & NAND_BUSWIDTH_16)
529                 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
530                         : omap_write_buf16(mtd, (u_char *) addr, len);
531         else
532                 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
533                         : omap_write_buf8(mtd, (u_char *) addr, len);
534         return 0;
535 }
536 
537 /**
538  * omap_read_buf_dma_pref - read data from NAND controller into buffer
539  * @mtd: MTD device structure
540  * @buf: buffer to store date
541  * @len: number of bytes to read
542  */
543 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
544 {
545         if (len <= mtd->oobsize)
546                 omap_read_buf_pref(mtd, buf, len);
547         else
548                 /* start transfer in DMA mode */
549                 omap_nand_dma_transfer(mtd, buf, len, 0x0);
550 }
551 
552 /**
553  * omap_write_buf_dma_pref - write buffer to NAND controller
554  * @mtd: MTD device structure
555  * @buf: data buffer
556  * @len: number of bytes to write
557  */
558 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
559                                         const u_char *buf, int len)
560 {
561         if (len <= mtd->oobsize)
562                 omap_write_buf_pref(mtd, buf, len);
563         else
564                 /* start transfer in DMA mode */
565                 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
566 }
567 
568 /*
569  * omap_nand_irq - GPMC irq handler
570  * @this_irq: gpmc irq number
571  * @dev: omap_nand_info structure pointer is passed here
572  */
573 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
574 {
575         struct omap_nand_info *info = (struct omap_nand_info *) dev;
576         u32 bytes;
577 
578         bytes = readl(info->reg.gpmc_prefetch_status);
579         bytes = PREFETCH_STATUS_FIFO_CNT(bytes);
580         bytes = bytes  & 0xFFFC; /* io in multiple of 4 bytes */
581         if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
582                 if (this_irq == info->gpmc_irq_count)
583                         goto done;
584 
585                 if (info->buf_len && (info->buf_len < bytes))
586                         bytes = info->buf_len;
587                 else if (!info->buf_len)
588                         bytes = 0;
589                 iowrite32_rep(info->nand.IO_ADDR_W,
590                                                 (u32 *)info->buf, bytes >> 2);
591                 info->buf = info->buf + bytes;
592                 info->buf_len -= bytes;
593 
594         } else {
595                 ioread32_rep(info->nand.IO_ADDR_R,
596                                                 (u32 *)info->buf, bytes >> 2);
597                 info->buf = info->buf + bytes;
598 
599                 if (this_irq == info->gpmc_irq_count)
600                         goto done;
601         }
602 
603         return IRQ_HANDLED;
604 
605 done:
606         complete(&info->comp);
607 
608         disable_irq_nosync(info->gpmc_irq_fifo);
609         disable_irq_nosync(info->gpmc_irq_count);
610 
611         return IRQ_HANDLED;
612 }
613 
614 /*
615  * omap_read_buf_irq_pref - read data from NAND controller into buffer
616  * @mtd: MTD device structure
617  * @buf: buffer to store date
618  * @len: number of bytes to read
619  */
620 static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
621 {
622         struct omap_nand_info *info = mtd_to_omap(mtd);
623         int ret = 0;
624 
625         if (len <= mtd->oobsize) {
626                 omap_read_buf_pref(mtd, buf, len);
627                 return;
628         }
629 
630         info->iomode = OMAP_NAND_IO_READ;
631         info->buf = buf;
632         init_completion(&info->comp);
633 
634         /*  configure and start prefetch transfer */
635         ret = omap_prefetch_enable(info->gpmc_cs,
636                         PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info);
637         if (ret)
638                 /* PFPW engine is busy, use cpu copy method */
639                 goto out_copy;
640 
641         info->buf_len = len;
642 
643         enable_irq(info->gpmc_irq_count);
644         enable_irq(info->gpmc_irq_fifo);
645 
646         /* waiting for read to complete */
647         wait_for_completion(&info->comp);
648 
649         /* disable and stop the PFPW engine */
650         omap_prefetch_reset(info->gpmc_cs, info);
651         return;
652 
653 out_copy:
654         if (info->nand.options & NAND_BUSWIDTH_16)
655                 omap_read_buf16(mtd, buf, len);
656         else
657                 omap_read_buf8(mtd, buf, len);
658 }
659 
660 /*
661  * omap_write_buf_irq_pref - write buffer to NAND controller
662  * @mtd: MTD device structure
663  * @buf: data buffer
664  * @len: number of bytes to write
665  */
666 static void omap_write_buf_irq_pref(struct mtd_info *mtd,
667                                         const u_char *buf, int len)
668 {
669         struct omap_nand_info *info = mtd_to_omap(mtd);
670         int ret = 0;
671         unsigned long tim, limit;
672         u32 val;
673 
674         if (len <= mtd->oobsize) {
675                 omap_write_buf_pref(mtd, buf, len);
676                 return;
677         }
678 
679         info->iomode = OMAP_NAND_IO_WRITE;
680         info->buf = (u_char *) buf;
681         init_completion(&info->comp);
682 
683         /* configure and start prefetch transfer : size=24 */
684         ret = omap_prefetch_enable(info->gpmc_cs,
685                 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info);
686         if (ret)
687                 /* PFPW engine is busy, use cpu copy method */
688                 goto out_copy;
689 
690         info->buf_len = len;
691 
692         enable_irq(info->gpmc_irq_count);
693         enable_irq(info->gpmc_irq_fifo);
694 
695         /* waiting for write to complete */
696         wait_for_completion(&info->comp);
697 
698         /* wait for data to flushed-out before reset the prefetch */
699         tim = 0;
700         limit = (loops_per_jiffy *  msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
701         do {
702                 val = readl(info->reg.gpmc_prefetch_status);
703                 val = PREFETCH_STATUS_COUNT(val);
704                 cpu_relax();
705         } while (val && (tim++ < limit));
706 
707         /* disable and stop the PFPW engine */
708         omap_prefetch_reset(info->gpmc_cs, info);
709         return;
710 
711 out_copy:
712         if (info->nand.options & NAND_BUSWIDTH_16)
713                 omap_write_buf16(mtd, buf, len);
714         else
715                 omap_write_buf8(mtd, buf, len);
716 }
717 
718 /**
719  * gen_true_ecc - This function will generate true ECC value
720  * @ecc_buf: buffer to store ecc code
721  *
722  * This generated true ECC value can be used when correcting
723  * data read from NAND flash memory core
724  */
725 static void gen_true_ecc(u8 *ecc_buf)
726 {
727         u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
728                 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
729 
730         ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
731                         P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
732         ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
733                         P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
734         ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
735                         P1e(tmp) | P2048o(tmp) | P2048e(tmp));
736 }
737 
738 /**
739  * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
740  * @ecc_data1:  ecc code from nand spare area
741  * @ecc_data2:  ecc code from hardware register obtained from hardware ecc
742  * @page_data:  page data
743  *
744  * This function compares two ECC's and indicates if there is an error.
745  * If the error can be corrected it will be corrected to the buffer.
746  * If there is no error, %0 is returned. If there is an error but it
747  * was corrected, %1 is returned. Otherwise, %-1 is returned.
748  */
749 static int omap_compare_ecc(u8 *ecc_data1,      /* read from NAND memory */
750                             u8 *ecc_data2,      /* read from register */
751                             u8 *page_data)
752 {
753         uint    i;
754         u8      tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
755         u8      comp0_bit[8], comp1_bit[8], comp2_bit[8];
756         u8      ecc_bit[24];
757         u8      ecc_sum = 0;
758         u8      find_bit = 0;
759         uint    find_byte = 0;
760         int     isEccFF;
761 
762         isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
763 
764         gen_true_ecc(ecc_data1);
765         gen_true_ecc(ecc_data2);
766 
767         for (i = 0; i <= 2; i++) {
768                 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
769                 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
770         }
771 
772         for (i = 0; i < 8; i++) {
773                 tmp0_bit[i]     = *ecc_data1 % 2;
774                 *ecc_data1      = *ecc_data1 / 2;
775         }
776 
777         for (i = 0; i < 8; i++) {
778                 tmp1_bit[i]      = *(ecc_data1 + 1) % 2;
779                 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
780         }
781 
782         for (i = 0; i < 8; i++) {
783                 tmp2_bit[i]      = *(ecc_data1 + 2) % 2;
784                 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
785         }
786 
787         for (i = 0; i < 8; i++) {
788                 comp0_bit[i]     = *ecc_data2 % 2;
789                 *ecc_data2       = *ecc_data2 / 2;
790         }
791 
792         for (i = 0; i < 8; i++) {
793                 comp1_bit[i]     = *(ecc_data2 + 1) % 2;
794                 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
795         }
796 
797         for (i = 0; i < 8; i++) {
798                 comp2_bit[i]     = *(ecc_data2 + 2) % 2;
799                 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
800         }
801 
802         for (i = 0; i < 6; i++)
803                 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
804 
805         for (i = 0; i < 8; i++)
806                 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
807 
808         for (i = 0; i < 8; i++)
809                 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
810 
811         ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
812         ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
813 
814         for (i = 0; i < 24; i++)
815                 ecc_sum += ecc_bit[i];
816 
817         switch (ecc_sum) {
818         case 0:
819                 /* Not reached because this function is not called if
820                  *  ECC values are equal
821                  */
822                 return 0;
823 
824         case 1:
825                 /* Uncorrectable error */
826                 pr_debug("ECC UNCORRECTED_ERROR 1\n");
827                 return -EBADMSG;
828 
829         case 11:
830                 /* UN-Correctable error */
831                 pr_debug("ECC UNCORRECTED_ERROR B\n");
832                 return -EBADMSG;
833 
834         case 12:
835                 /* Correctable error */
836                 find_byte = (ecc_bit[23] << 8) +
837                             (ecc_bit[21] << 7) +
838                             (ecc_bit[19] << 6) +
839                             (ecc_bit[17] << 5) +
840                             (ecc_bit[15] << 4) +
841                             (ecc_bit[13] << 3) +
842                             (ecc_bit[11] << 2) +
843                             (ecc_bit[9]  << 1) +
844                             ecc_bit[7];
845 
846                 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
847 
848                 pr_debug("Correcting single bit ECC error at offset: "
849                                 "%d, bit: %d\n", find_byte, find_bit);
850 
851                 page_data[find_byte] ^= (1 << find_bit);
852 
853                 return 1;
854         default:
855                 if (isEccFF) {
856                         if (ecc_data2[0] == 0 &&
857                             ecc_data2[1] == 0 &&
858                             ecc_data2[2] == 0)
859                                 return 0;
860                 }
861                 pr_debug("UNCORRECTED_ERROR default\n");
862                 return -EBADMSG;
863         }
864 }
865 
866 /**
867  * omap_correct_data - Compares the ECC read with HW generated ECC
868  * @mtd: MTD device structure
869  * @dat: page data
870  * @read_ecc: ecc read from nand flash
871  * @calc_ecc: ecc read from HW ECC registers
872  *
873  * Compares the ecc read from nand spare area with ECC registers values
874  * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
875  * detection and correction. If there are no errors, %0 is returned. If
876  * there were errors and all of the errors were corrected, the number of
877  * corrected errors is returned. If uncorrectable errors exist, %-1 is
878  * returned.
879  */
880 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
881                                 u_char *read_ecc, u_char *calc_ecc)
882 {
883         struct omap_nand_info *info = mtd_to_omap(mtd);
884         int blockCnt = 0, i = 0, ret = 0;
885         int stat = 0;
886 
887         /* Ex NAND_ECC_HW12_2048 */
888         if ((info->nand.ecc.mode == NAND_ECC_HW) &&
889                         (info->nand.ecc.size  == 2048))
890                 blockCnt = 4;
891         else
892                 blockCnt = 1;
893 
894         for (i = 0; i < blockCnt; i++) {
895                 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
896                         ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
897                         if (ret < 0)
898                                 return ret;
899                         /* keep track of the number of corrected errors */
900                         stat += ret;
901                 }
902                 read_ecc += 3;
903                 calc_ecc += 3;
904                 dat      += 512;
905         }
906         return stat;
907 }
908 
909 /**
910  * omap_calcuate_ecc - Generate non-inverted ECC bytes.
911  * @mtd: MTD device structure
912  * @dat: The pointer to data on which ecc is computed
913  * @ecc_code: The ecc_code buffer
914  *
915  * Using noninverted ECC can be considered ugly since writing a blank
916  * page ie. padding will clear the ECC bytes. This is no problem as long
917  * nobody is trying to write data on the seemingly unused page. Reading
918  * an erased page will produce an ECC mismatch between generated and read
919  * ECC bytes that has to be dealt with separately.
920  */
921 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
922                                 u_char *ecc_code)
923 {
924         struct omap_nand_info *info = mtd_to_omap(mtd);
925         u32 val;
926 
927         val = readl(info->reg.gpmc_ecc_config);
928         if (((val >> ECC_CONFIG_CS_SHIFT) & CS_MASK) != info->gpmc_cs)
929                 return -EINVAL;
930 
931         /* read ecc result */
932         val = readl(info->reg.gpmc_ecc1_result);
933         *ecc_code++ = val;          /* P128e, ..., P1e */
934         *ecc_code++ = val >> 16;    /* P128o, ..., P1o */
935         /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
936         *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
937 
938         return 0;
939 }
940 
941 /**
942  * omap_enable_hwecc - This function enables the hardware ecc functionality
943  * @mtd: MTD device structure
944  * @mode: Read/Write mode
945  */
946 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
947 {
948         struct omap_nand_info *info = mtd_to_omap(mtd);
949         struct nand_chip *chip = mtd_to_nand(mtd);
950         unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
951         u32 val;
952 
953         /* clear ecc and enable bits */
954         val = ECCCLEAR | ECC1;
955         writel(val, info->reg.gpmc_ecc_control);
956 
957         /* program ecc and result sizes */
958         val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
959                          ECC1RESULTSIZE);
960         writel(val, info->reg.gpmc_ecc_size_config);
961 
962         switch (mode) {
963         case NAND_ECC_READ:
964         case NAND_ECC_WRITE:
965                 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
966                 break;
967         case NAND_ECC_READSYN:
968                 writel(ECCCLEAR, info->reg.gpmc_ecc_control);
969                 break;
970         default:
971                 dev_info(&info->pdev->dev,
972                         "error: unrecognized Mode[%d]!\n", mode);
973                 break;
974         }
975 
976         /* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
977         val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
978         writel(val, info->reg.gpmc_ecc_config);
979 }
980 
981 /**
982  * omap_wait - wait until the command is done
983  * @mtd: MTD device structure
984  * @chip: NAND Chip structure
985  *
986  * Wait function is called during Program and erase operations and
987  * the way it is called from MTD layer, we should wait till the NAND
988  * chip is ready after the programming/erase operation has completed.
989  *
990  * Erase can take up to 400ms and program up to 20ms according to
991  * general NAND and SmartMedia specs
992  */
993 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
994 {
995         struct nand_chip *this = mtd_to_nand(mtd);
996         struct omap_nand_info *info = mtd_to_omap(mtd);
997         unsigned long timeo = jiffies;
998         int status, state = this->state;
999 
1000         if (state == FL_ERASING)
1001                 timeo += msecs_to_jiffies(400);
1002         else
1003                 timeo += msecs_to_jiffies(20);
1004 
1005         writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command);
1006         while (time_before(jiffies, timeo)) {
1007                 status = readb(info->reg.gpmc_nand_data);
1008                 if (status & NAND_STATUS_READY)
1009                         break;
1010                 cond_resched();
1011         }
1012 
1013         status = readb(info->reg.gpmc_nand_data);
1014         return status;
1015 }
1016 
1017 /**
1018  * omap_dev_ready - checks the NAND Ready GPIO line
1019  * @mtd: MTD device structure
1020  *
1021  * Returns true if ready and false if busy.
1022  */
1023 static int omap_dev_ready(struct mtd_info *mtd)
1024 {
1025         struct omap_nand_info *info = mtd_to_omap(mtd);
1026 
1027         return gpiod_get_value(info->ready_gpiod);
1028 }
1029 
1030 /**
1031  * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation
1032  * @mtd: MTD device structure
1033  * @mode: Read/Write mode
1034  *
1035  * When using BCH with SW correction (i.e. no ELM), sector size is set
1036  * to 512 bytes and we use BCH_WRAPMODE_6 wrapping mode
1037  * for both reading and writing with:
1038  * eccsize0 = 0  (no additional protected byte in spare area)
1039  * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1040  */
1041 static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd, int mode)
1042 {
1043         unsigned int bch_type;
1044         unsigned int dev_width, nsectors;
1045         struct omap_nand_info *info = mtd_to_omap(mtd);
1046         enum omap_ecc ecc_opt = info->ecc_opt;
1047         struct nand_chip *chip = mtd_to_nand(mtd);
1048         u32 val, wr_mode;
1049         unsigned int ecc_size1, ecc_size0;
1050 
1051         /* GPMC configurations for calculating ECC */
1052         switch (ecc_opt) {
1053         case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1054                 bch_type = 0;
1055                 nsectors = 1;
1056                 wr_mode   = BCH_WRAPMODE_6;
1057                 ecc_size0 = BCH_ECC_SIZE0;
1058                 ecc_size1 = BCH_ECC_SIZE1;
1059                 break;
1060         case OMAP_ECC_BCH4_CODE_HW:
1061                 bch_type = 0;
1062                 nsectors = chip->ecc.steps;
1063                 if (mode == NAND_ECC_READ) {
1064                         wr_mode   = BCH_WRAPMODE_1;
1065                         ecc_size0 = BCH4R_ECC_SIZE0;
1066                         ecc_size1 = BCH4R_ECC_SIZE1;
1067                 } else {
1068                         wr_mode   = BCH_WRAPMODE_6;
1069                         ecc_size0 = BCH_ECC_SIZE0;
1070                         ecc_size1 = BCH_ECC_SIZE1;
1071                 }
1072                 break;
1073         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1074                 bch_type = 1;
1075                 nsectors = 1;
1076                 wr_mode   = BCH_WRAPMODE_6;
1077                 ecc_size0 = BCH_ECC_SIZE0;
1078                 ecc_size1 = BCH_ECC_SIZE1;
1079                 break;
1080         case OMAP_ECC_BCH8_CODE_HW:
1081                 bch_type = 1;
1082                 nsectors = chip->ecc.steps;
1083                 if (mode == NAND_ECC_READ) {
1084                         wr_mode   = BCH_WRAPMODE_1;
1085                         ecc_size0 = BCH8R_ECC_SIZE0;
1086                         ecc_size1 = BCH8R_ECC_SIZE1;
1087                 } else {
1088                         wr_mode   = BCH_WRAPMODE_6;
1089                         ecc_size0 = BCH_ECC_SIZE0;
1090                         ecc_size1 = BCH_ECC_SIZE1;
1091                 }
1092                 break;
1093         case OMAP_ECC_BCH16_CODE_HW:
1094                 bch_type = 0x2;
1095                 nsectors = chip->ecc.steps;
1096                 if (mode == NAND_ECC_READ) {
1097                         wr_mode   = 0x01;
1098                         ecc_size0 = 52; /* ECC bits in nibbles per sector */
1099                         ecc_size1 = 0;  /* non-ECC bits in nibbles per sector */
1100                 } else {
1101                         wr_mode   = 0x01;
1102                         ecc_size0 = 0;  /* extra bits in nibbles per sector */
1103                         ecc_size1 = 52; /* OOB bits in nibbles per sector */
1104                 }
1105                 break;
1106         default:
1107                 return;
1108         }
1109 
1110         writel(ECC1, info->reg.gpmc_ecc_control);
1111 
1112         /* Configure ecc size for BCH */
1113         val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT);
1114         writel(val, info->reg.gpmc_ecc_size_config);
1115 
1116         dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
1117 
1118         /* BCH configuration */
1119         val = ((1                        << 16) | /* enable BCH */
1120                (bch_type                 << 12) | /* BCH4/BCH8/BCH16 */
1121                (wr_mode                  <<  8) | /* wrap mode */
1122                (dev_width                <<  7) | /* bus width */
1123                (((nsectors-1) & 0x7)     <<  4) | /* number of sectors */
1124                (info->gpmc_cs            <<  1) | /* ECC CS */
1125                (0x1));                            /* enable ECC */
1126 
1127         writel(val, info->reg.gpmc_ecc_config);
1128 
1129         /* Clear ecc and enable bits */
1130         writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
1131 }
1132 
1133 static u8  bch4_polynomial[] = {0x28, 0x13, 0xcc, 0x39, 0x96, 0xac, 0x7f};
1134 static u8  bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
1135                                 0x97, 0x79, 0xe5, 0x24, 0xb5};
1136 
1137 /**
1138  * omap_calculate_ecc_bch - Generate bytes of ECC bytes
1139  * @mtd:        MTD device structure
1140  * @dat:        The pointer to data on which ecc is computed
1141  * @ecc_code:   The ecc_code buffer
1142  *
1143  * Support calculating of BCH4/8 ecc vectors for the page
1144  */
1145 static int __maybe_unused omap_calculate_ecc_bch(struct mtd_info *mtd,
1146                                         const u_char *dat, u_char *ecc_calc)
1147 {
1148         struct omap_nand_info *info = mtd_to_omap(mtd);
1149         int eccbytes    = info->nand.ecc.bytes;
1150         struct gpmc_nand_regs   *gpmc_regs = &info->reg;
1151         u8 *ecc_code;
1152         unsigned long nsectors, bch_val1, bch_val2, bch_val3, bch_val4;
1153         u32 val;
1154         int i, j;
1155 
1156         nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1157         for (i = 0; i < nsectors; i++) {
1158                 ecc_code = ecc_calc;
1159                 switch (info->ecc_opt) {
1160                 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1161                 case OMAP_ECC_BCH8_CODE_HW:
1162                         bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1163                         bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1164                         bch_val3 = readl(gpmc_regs->gpmc_bch_result2[i]);
1165                         bch_val4 = readl(gpmc_regs->gpmc_bch_result3[i]);
1166                         *ecc_code++ = (bch_val4 & 0xFF);
1167                         *ecc_code++ = ((bch_val3 >> 24) & 0xFF);
1168                         *ecc_code++ = ((bch_val3 >> 16) & 0xFF);
1169                         *ecc_code++ = ((bch_val3 >> 8) & 0xFF);
1170                         *ecc_code++ = (bch_val3 & 0xFF);
1171                         *ecc_code++ = ((bch_val2 >> 24) & 0xFF);
1172                         *ecc_code++ = ((bch_val2 >> 16) & 0xFF);
1173                         *ecc_code++ = ((bch_val2 >> 8) & 0xFF);
1174                         *ecc_code++ = (bch_val2 & 0xFF);
1175                         *ecc_code++ = ((bch_val1 >> 24) & 0xFF);
1176                         *ecc_code++ = ((bch_val1 >> 16) & 0xFF);
1177                         *ecc_code++ = ((bch_val1 >> 8) & 0xFF);
1178                         *ecc_code++ = (bch_val1 & 0xFF);
1179                         break;
1180                 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1181                 case OMAP_ECC_BCH4_CODE_HW:
1182                         bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1183                         bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1184                         *ecc_code++ = ((bch_val2 >> 12) & 0xFF);
1185                         *ecc_code++ = ((bch_val2 >> 4) & 0xFF);
1186                         *ecc_code++ = ((bch_val2 & 0xF) << 4) |
1187                                 ((bch_val1 >> 28) & 0xF);
1188                         *ecc_code++ = ((bch_val1 >> 20) & 0xFF);
1189                         *ecc_code++ = ((bch_val1 >> 12) & 0xFF);
1190                         *ecc_code++ = ((bch_val1 >> 4) & 0xFF);
1191                         *ecc_code++ = ((bch_val1 & 0xF) << 4);
1192                         break;
1193                 case OMAP_ECC_BCH16_CODE_HW:
1194                         val = readl(gpmc_regs->gpmc_bch_result6[i]);
1195                         ecc_code[0]  = ((val >>  8) & 0xFF);
1196                         ecc_code[1]  = ((val >>  0) & 0xFF);
1197                         val = readl(gpmc_regs->gpmc_bch_result5[i]);
1198                         ecc_code[2]  = ((val >> 24) & 0xFF);
1199                         ecc_code[3]  = ((val >> 16) & 0xFF);
1200                         ecc_code[4]  = ((val >>  8) & 0xFF);
1201                         ecc_code[5]  = ((val >>  0) & 0xFF);
1202                         val = readl(gpmc_regs->gpmc_bch_result4[i]);
1203                         ecc_code[6]  = ((val >> 24) & 0xFF);
1204                         ecc_code[7]  = ((val >> 16) & 0xFF);
1205                         ecc_code[8]  = ((val >>  8) & 0xFF);
1206                         ecc_code[9]  = ((val >>  0) & 0xFF);
1207                         val = readl(gpmc_regs->gpmc_bch_result3[i]);
1208                         ecc_code[10] = ((val >> 24) & 0xFF);
1209                         ecc_code[11] = ((val >> 16) & 0xFF);
1210                         ecc_code[12] = ((val >>  8) & 0xFF);
1211                         ecc_code[13] = ((val >>  0) & 0xFF);
1212                         val = readl(gpmc_regs->gpmc_bch_result2[i]);
1213                         ecc_code[14] = ((val >> 24) & 0xFF);
1214                         ecc_code[15] = ((val >> 16) & 0xFF);
1215                         ecc_code[16] = ((val >>  8) & 0xFF);
1216                         ecc_code[17] = ((val >>  0) & 0xFF);
1217                         val = readl(gpmc_regs->gpmc_bch_result1[i]);
1218                         ecc_code[18] = ((val >> 24) & 0xFF);
1219                         ecc_code[19] = ((val >> 16) & 0xFF);
1220                         ecc_code[20] = ((val >>  8) & 0xFF);
1221                         ecc_code[21] = ((val >>  0) & 0xFF);
1222                         val = readl(gpmc_regs->gpmc_bch_result0[i]);
1223                         ecc_code[22] = ((val >> 24) & 0xFF);
1224                         ecc_code[23] = ((val >> 16) & 0xFF);
1225                         ecc_code[24] = ((val >>  8) & 0xFF);
1226                         ecc_code[25] = ((val >>  0) & 0xFF);
1227                         break;
1228                 default:
1229                         return -EINVAL;
1230                 }
1231 
1232                 /* ECC scheme specific syndrome customizations */
1233                 switch (info->ecc_opt) {
1234                 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1235                         /* Add constant polynomial to remainder, so that
1236                          * ECC of blank pages results in 0x0 on reading back */
1237                         for (j = 0; j < eccbytes; j++)
1238                                 ecc_calc[j] ^= bch4_polynomial[j];
1239                         break;
1240                 case OMAP_ECC_BCH4_CODE_HW:
1241                         /* Set  8th ECC byte as 0x0 for ROM compatibility */
1242                         ecc_calc[eccbytes - 1] = 0x0;
1243                         break;
1244                 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1245                         /* Add constant polynomial to remainder, so that
1246                          * ECC of blank pages results in 0x0 on reading back */
1247                         for (j = 0; j < eccbytes; j++)
1248                                 ecc_calc[j] ^= bch8_polynomial[j];
1249                         break;
1250                 case OMAP_ECC_BCH8_CODE_HW:
1251                         /* Set 14th ECC byte as 0x0 for ROM compatibility */
1252                         ecc_calc[eccbytes - 1] = 0x0;
1253                         break;
1254                 case OMAP_ECC_BCH16_CODE_HW:
1255                         break;
1256                 default:
1257                         return -EINVAL;
1258                 }
1259 
1260         ecc_calc += eccbytes;
1261         }
1262 
1263         return 0;
1264 }
1265 
1266 /**
1267  * erased_sector_bitflips - count bit flips
1268  * @data:       data sector buffer
1269  * @oob:        oob buffer
1270  * @info:       omap_nand_info
1271  *
1272  * Check the bit flips in erased page falls below correctable level.
1273  * If falls below, report the page as erased with correctable bit
1274  * flip, else report as uncorrectable page.
1275  */
1276 static int erased_sector_bitflips(u_char *data, u_char *oob,
1277                 struct omap_nand_info *info)
1278 {
1279         int flip_bits = 0, i;
1280 
1281         for (i = 0; i < info->nand.ecc.size; i++) {
1282                 flip_bits += hweight8(~data[i]);
1283                 if (flip_bits > info->nand.ecc.strength)
1284                         return 0;
1285         }
1286 
1287         for (i = 0; i < info->nand.ecc.bytes - 1; i++) {
1288                 flip_bits += hweight8(~oob[i]);
1289                 if (flip_bits > info->nand.ecc.strength)
1290                         return 0;
1291         }
1292 
1293         /*
1294          * Bit flips falls in correctable level.
1295          * Fill data area with 0xFF
1296          */
1297         if (flip_bits) {
1298                 memset(data, 0xFF, info->nand.ecc.size);
1299                 memset(oob, 0xFF, info->nand.ecc.bytes);
1300         }
1301 
1302         return flip_bits;
1303 }
1304 
1305 /**
1306  * omap_elm_correct_data - corrects page data area in case error reported
1307  * @mtd:        MTD device structure
1308  * @data:       page data
1309  * @read_ecc:   ecc read from nand flash
1310  * @calc_ecc:   ecc read from HW ECC registers
1311  *
1312  * Calculated ecc vector reported as zero in case of non-error pages.
1313  * In case of non-zero ecc vector, first filter out erased-pages, and
1314  * then process data via ELM to detect bit-flips.
1315  */
1316 static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data,
1317                                 u_char *read_ecc, u_char *calc_ecc)
1318 {
1319         struct omap_nand_info *info = mtd_to_omap(mtd);
1320         struct nand_ecc_ctrl *ecc = &info->nand.ecc;
1321         int eccsteps = info->nand.ecc.steps;
1322         int i , j, stat = 0;
1323         int eccflag, actual_eccbytes;
1324         struct elm_errorvec err_vec[ERROR_VECTOR_MAX];
1325         u_char *ecc_vec = calc_ecc;
1326         u_char *spare_ecc = read_ecc;
1327         u_char *erased_ecc_vec;
1328         u_char *buf;
1329         int bitflip_count;
1330         bool is_error_reported = false;
1331         u32 bit_pos, byte_pos, error_max, pos;
1332         int err;
1333 
1334         switch (info->ecc_opt) {
1335         case OMAP_ECC_BCH4_CODE_HW:
1336                 /* omit  7th ECC byte reserved for ROM code compatibility */
1337                 actual_eccbytes = ecc->bytes - 1;
1338                 erased_ecc_vec = bch4_vector;
1339                 break;
1340         case OMAP_ECC_BCH8_CODE_HW:
1341                 /* omit 14th ECC byte reserved for ROM code compatibility */
1342                 actual_eccbytes = ecc->bytes - 1;
1343                 erased_ecc_vec = bch8_vector;
1344                 break;
1345         case OMAP_ECC_BCH16_CODE_HW:
1346                 actual_eccbytes = ecc->bytes;
1347                 erased_ecc_vec = bch16_vector;
1348                 break;
1349         default:
1350                 dev_err(&info->pdev->dev, "invalid driver configuration\n");
1351                 return -EINVAL;
1352         }
1353 
1354         /* Initialize elm error vector to zero */
1355         memset(err_vec, 0, sizeof(err_vec));
1356 
1357         for (i = 0; i < eccsteps ; i++) {
1358                 eccflag = 0;    /* initialize eccflag */
1359 
1360                 /*
1361                  * Check any error reported,
1362                  * In case of error, non zero ecc reported.
1363                  */
1364                 for (j = 0; j < actual_eccbytes; j++) {
1365                         if (calc_ecc[j] != 0) {
1366                                 eccflag = 1; /* non zero ecc, error present */
1367                                 break;
1368                         }
1369                 }
1370 
1371                 if (eccflag == 1) {
1372                         if (memcmp(calc_ecc, erased_ecc_vec,
1373                                                 actual_eccbytes) == 0) {
1374                                 /*
1375                                  * calc_ecc[] matches pattern for ECC(all 0xff)
1376                                  * so this is definitely an erased-page
1377                                  */
1378                         } else {
1379                                 buf = &data[info->nand.ecc.size * i];
1380                                 /*
1381                                  * count number of 0-bits in read_buf.
1382                                  * This check can be removed once a similar
1383                                  * check is introduced in generic NAND driver
1384                                  */
1385                                 bitflip_count = erased_sector_bitflips(
1386                                                 buf, read_ecc, info);
1387                                 if (bitflip_count) {
1388                                         /*
1389                                          * number of 0-bits within ECC limits
1390                                          * So this may be an erased-page
1391                                          */
1392                                         stat += bitflip_count;
1393                                 } else {
1394                                         /*
1395                                          * Too many 0-bits. It may be a
1396                                          * - programmed-page, OR
1397                                          * - erased-page with many bit-flips
1398                                          * So this page requires check by ELM
1399                                          */
1400                                         err_vec[i].error_reported = true;
1401                                         is_error_reported = true;
1402                                 }
1403                         }
1404                 }
1405 
1406                 /* Update the ecc vector */
1407                 calc_ecc += ecc->bytes;
1408                 read_ecc += ecc->bytes;
1409         }
1410 
1411         /* Check if any error reported */
1412         if (!is_error_reported)
1413                 return stat;
1414 
1415         /* Decode BCH error using ELM module */
1416         elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec);
1417 
1418         err = 0;
1419         for (i = 0; i < eccsteps; i++) {
1420                 if (err_vec[i].error_uncorrectable) {
1421                         dev_err(&info->pdev->dev,
1422                                 "uncorrectable bit-flips found\n");
1423                         err = -EBADMSG;
1424                 } else if (err_vec[i].error_reported) {
1425                         for (j = 0; j < err_vec[i].error_count; j++) {
1426                                 switch (info->ecc_opt) {
1427                                 case OMAP_ECC_BCH4_CODE_HW:
1428                                         /* Add 4 bits to take care of padding */
1429                                         pos = err_vec[i].error_loc[j] +
1430                                                 BCH4_BIT_PAD;
1431                                         break;
1432                                 case OMAP_ECC_BCH8_CODE_HW:
1433                                 case OMAP_ECC_BCH16_CODE_HW:
1434                                         pos = err_vec[i].error_loc[j];
1435                                         break;
1436                                 default:
1437                                         return -EINVAL;
1438                                 }
1439                                 error_max = (ecc->size + actual_eccbytes) * 8;
1440                                 /* Calculate bit position of error */
1441                                 bit_pos = pos % 8;
1442 
1443                                 /* Calculate byte position of error */
1444                                 byte_pos = (error_max - pos - 1) / 8;
1445 
1446                                 if (pos < error_max) {
1447                                         if (byte_pos < 512) {
1448                                                 pr_debug("bitflip@dat[%d]=%x\n",
1449                                                      byte_pos, data[byte_pos]);
1450                                                 data[byte_pos] ^= 1 << bit_pos;
1451                                         } else {
1452                                                 pr_debug("bitflip@oob[%d]=%x\n",
1453                                                         (byte_pos - 512),
1454                                                      spare_ecc[byte_pos - 512]);
1455                                                 spare_ecc[byte_pos - 512] ^=
1456                                                         1 << bit_pos;
1457                                         }
1458                                 } else {
1459                                         dev_err(&info->pdev->dev,
1460                                                 "invalid bit-flip @ %d:%d\n",
1461                                                 byte_pos, bit_pos);
1462                                         err = -EBADMSG;
1463                                 }
1464                         }
1465                 }
1466 
1467                 /* Update number of correctable errors */
1468                 stat += err_vec[i].error_count;
1469 
1470                 /* Update page data with sector size */
1471                 data += ecc->size;
1472                 spare_ecc += ecc->bytes;
1473         }
1474 
1475         return (err) ? err : stat;
1476 }
1477 
1478 /**
1479  * omap_write_page_bch - BCH ecc based write page function for entire page
1480  * @mtd:                mtd info structure
1481  * @chip:               nand chip info structure
1482  * @buf:                data buffer
1483  * @oob_required:       must write chip->oob_poi to OOB
1484  * @page:               page
1485  *
1486  * Custom write page method evolved to support multi sector writing in one shot
1487  */
1488 static int omap_write_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1489                                const uint8_t *buf, int oob_required, int page)
1490 {
1491         int ret;
1492         uint8_t *ecc_calc = chip->buffers->ecccalc;
1493 
1494         /* Enable GPMC ecc engine */
1495         chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1496 
1497         /* Write data */
1498         chip->write_buf(mtd, buf, mtd->writesize);
1499 
1500         /* Update ecc vector from GPMC result registers */
1501         chip->ecc.calculate(mtd, buf, &ecc_calc[0]);
1502 
1503         ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
1504                                          chip->ecc.total);
1505         if (ret)
1506                 return ret;
1507 
1508         /* Write ecc vector to OOB area */
1509         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1510         return 0;
1511 }
1512 
1513 /**
1514  * omap_read_page_bch - BCH ecc based page read function for entire page
1515  * @mtd:                mtd info structure
1516  * @chip:               nand chip info structure
1517  * @buf:                buffer to store read data
1518  * @oob_required:       caller requires OOB data read to chip->oob_poi
1519  * @page:               page number to read
1520  *
1521  * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module
1522  * used for error correction.
1523  * Custom method evolved to support ELM error correction & multi sector
1524  * reading. On reading page data area is read along with OOB data with
1525  * ecc engine enabled. ecc vector updated after read of OOB data.
1526  * For non error pages ecc vector reported as zero.
1527  */
1528 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1529                                 uint8_t *buf, int oob_required, int page)
1530 {
1531         uint8_t *ecc_calc = chip->buffers->ecccalc;
1532         uint8_t *ecc_code = chip->buffers->ecccode;
1533         int stat, ret;
1534         unsigned int max_bitflips = 0;
1535 
1536         /* Enable GPMC ecc engine */
1537         chip->ecc.hwctl(mtd, NAND_ECC_READ);
1538 
1539         /* Read data */
1540         chip->read_buf(mtd, buf, mtd->writesize);
1541 
1542         /* Read oob bytes */
1543         chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1544                       mtd->writesize + BADBLOCK_MARKER_LENGTH, -1);
1545         chip->read_buf(mtd, chip->oob_poi + BADBLOCK_MARKER_LENGTH,
1546                        chip->ecc.total);
1547 
1548         /* Calculate ecc bytes */
1549         chip->ecc.calculate(mtd, buf, ecc_calc);
1550 
1551         ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
1552                                          chip->ecc.total);
1553         if (ret)
1554                 return ret;
1555 
1556         stat = chip->ecc.correct(mtd, buf, ecc_code, ecc_calc);
1557 
1558         if (stat < 0) {
1559                 mtd->ecc_stats.failed++;
1560         } else {
1561                 mtd->ecc_stats.corrected += stat;
1562                 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1563         }
1564 
1565         return max_bitflips;
1566 }
1567 
1568 /**
1569  * is_elm_present - checks for presence of ELM module by scanning DT nodes
1570  * @omap_nand_info: NAND device structure containing platform data
1571  */
1572 static bool is_elm_present(struct omap_nand_info *info,
1573                            struct device_node *elm_node)
1574 {
1575         struct platform_device *pdev;
1576 
1577         /* check whether elm-id is passed via DT */
1578         if (!elm_node) {
1579                 dev_err(&info->pdev->dev, "ELM devicetree node not found\n");
1580                 return false;
1581         }
1582         pdev = of_find_device_by_node(elm_node);
1583         /* check whether ELM device is registered */
1584         if (!pdev) {
1585                 dev_err(&info->pdev->dev, "ELM device not found\n");
1586                 return false;
1587         }
1588         /* ELM module available, now configure it */
1589         info->elm_dev = &pdev->dev;
1590         return true;
1591 }
1592 
1593 static bool omap2_nand_ecc_check(struct omap_nand_info *info,
1594                                  struct omap_nand_platform_data *pdata)
1595 {
1596         bool ecc_needs_bch, ecc_needs_omap_bch, ecc_needs_elm;
1597 
1598         switch (info->ecc_opt) {
1599         case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1600         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1601                 ecc_needs_omap_bch = false;
1602                 ecc_needs_bch = true;
1603                 ecc_needs_elm = false;
1604                 break;
1605         case OMAP_ECC_BCH4_CODE_HW:
1606         case OMAP_ECC_BCH8_CODE_HW:
1607         case OMAP_ECC_BCH16_CODE_HW:
1608                 ecc_needs_omap_bch = true;
1609                 ecc_needs_bch = false;
1610                 ecc_needs_elm = true;
1611                 break;
1612         default:
1613                 ecc_needs_omap_bch = false;
1614                 ecc_needs_bch = false;
1615                 ecc_needs_elm = false;
1616                 break;
1617         }
1618 
1619         if (ecc_needs_bch && !IS_ENABLED(CONFIG_MTD_NAND_ECC_BCH)) {
1620                 dev_err(&info->pdev->dev,
1621                         "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
1622                 return false;
1623         }
1624         if (ecc_needs_omap_bch && !IS_ENABLED(CONFIG_MTD_NAND_OMAP_BCH)) {
1625                 dev_err(&info->pdev->dev,
1626                         "CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1627                 return false;
1628         }
1629         if (ecc_needs_elm && !is_elm_present(info, info->elm_of_node)) {
1630                 dev_err(&info->pdev->dev, "ELM not available\n");
1631                 return false;
1632         }
1633 
1634         return true;
1635 }
1636 
1637 static const char * const nand_xfer_types[] = {
1638         [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled",
1639         [NAND_OMAP_POLLED] = "polled",
1640         [NAND_OMAP_PREFETCH_DMA] = "prefetch-dma",
1641         [NAND_OMAP_PREFETCH_IRQ] = "prefetch-irq",
1642 };
1643 
1644 static int omap_get_dt_info(struct device *dev, struct omap_nand_info *info)
1645 {
1646         struct device_node *child = dev->of_node;
1647         int i;
1648         const char *s;
1649         u32 cs;
1650 
1651         if (of_property_read_u32(child, "reg", &cs) < 0) {
1652                 dev_err(dev, "reg not found in DT\n");
1653                 return -EINVAL;
1654         }
1655 
1656         info->gpmc_cs = cs;
1657 
1658         /* detect availability of ELM module. Won't be present pre-OMAP4 */
1659         info->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0);
1660         if (!info->elm_of_node) {
1661                 info->elm_of_node = of_parse_phandle(child, "elm_id", 0);
1662                 if (!info->elm_of_node)
1663                         dev_dbg(dev, "ti,elm-id not in DT\n");
1664         }
1665 
1666         /* select ecc-scheme for NAND */
1667         if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) {
1668                 dev_err(dev, "ti,nand-ecc-opt not found\n");
1669                 return -EINVAL;
1670         }
1671 
1672         if (!strcmp(s, "sw")) {
1673                 info->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
1674         } else if (!strcmp(s, "ham1") ||
1675                    !strcmp(s, "hw") || !strcmp(s, "hw-romcode")) {
1676                 info->ecc_opt = OMAP_ECC_HAM1_CODE_HW;
1677         } else if (!strcmp(s, "bch4")) {
1678                 if (info->elm_of_node)
1679                         info->ecc_opt = OMAP_ECC_BCH4_CODE_HW;
1680                 else
1681                         info->ecc_opt = OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;
1682         } else if (!strcmp(s, "bch8")) {
1683                 if (info->elm_of_node)
1684                         info->ecc_opt = OMAP_ECC_BCH8_CODE_HW;
1685                 else
1686                         info->ecc_opt = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
1687         } else if (!strcmp(s, "bch16")) {
1688                 info->ecc_opt = OMAP_ECC_BCH16_CODE_HW;
1689         } else {
1690                 dev_err(dev, "unrecognized value for ti,nand-ecc-opt\n");
1691                 return -EINVAL;
1692         }
1693 
1694         /* select data transfer mode */
1695         if (!of_property_read_string(child, "ti,nand-xfer-type", &s)) {
1696                 for (i = 0; i < ARRAY_SIZE(nand_xfer_types); i++) {
1697                         if (!strcasecmp(s, nand_xfer_types[i])) {
1698                                 info->xfer_type = i;
1699                                 return 0;
1700                         }
1701                 }
1702 
1703                 dev_err(dev, "unrecognized value for ti,nand-xfer-type\n");
1704                 return -EINVAL;
1705         }
1706 
1707         return 0;
1708 }
1709 
1710 static int omap_ooblayout_ecc(struct mtd_info *mtd, int section,
1711                               struct mtd_oob_region *oobregion)
1712 {
1713         struct omap_nand_info *info = mtd_to_omap(mtd);
1714         struct nand_chip *chip = &info->nand;
1715         int off = BADBLOCK_MARKER_LENGTH;
1716 
1717         if (info->ecc_opt == OMAP_ECC_HAM1_CODE_HW &&
1718             !(chip->options & NAND_BUSWIDTH_16))
1719                 off = 1;
1720 
1721         if (section)
1722                 return -ERANGE;
1723 
1724         oobregion->offset = off;
1725         oobregion->length = chip->ecc.total;
1726 
1727         return 0;
1728 }
1729 
1730 static int omap_ooblayout_free(struct mtd_info *mtd, int section,
1731                                struct mtd_oob_region *oobregion)
1732 {
1733         struct omap_nand_info *info = mtd_to_omap(mtd);
1734         struct nand_chip *chip = &info->nand;
1735         int off = BADBLOCK_MARKER_LENGTH;
1736 
1737         if (info->ecc_opt == OMAP_ECC_HAM1_CODE_HW &&
1738             !(chip->options & NAND_BUSWIDTH_16))
1739                 off = 1;
1740 
1741         if (section)
1742                 return -ERANGE;
1743 
1744         off += chip->ecc.total;
1745         if (off >= mtd->oobsize)
1746                 return -ERANGE;
1747 
1748         oobregion->offset = off;
1749         oobregion->length = mtd->oobsize - off;
1750 
1751         return 0;
1752 }
1753 
1754 static const struct mtd_ooblayout_ops omap_ooblayout_ops = {
1755         .ecc = omap_ooblayout_ecc,
1756         .free = omap_ooblayout_free,
1757 };
1758 
1759 static int omap_sw_ooblayout_ecc(struct mtd_info *mtd, int section,
1760                                  struct mtd_oob_region *oobregion)
1761 {
1762         struct nand_chip *chip = mtd_to_nand(mtd);
1763         int off = BADBLOCK_MARKER_LENGTH;
1764 
1765         if (section >= chip->ecc.steps)
1766                 return -ERANGE;
1767 
1768         /*
1769          * When SW correction is employed, one OMAP specific marker byte is
1770          * reserved after each ECC step.
1771          */
1772         oobregion->offset = off + (section * (chip->ecc.bytes + 1));
1773         oobregion->length = chip->ecc.bytes;
1774 
1775         return 0;
1776 }
1777 
1778 static int omap_sw_ooblayout_free(struct mtd_info *mtd, int section,
1779                                   struct mtd_oob_region *oobregion)
1780 {
1781         struct nand_chip *chip = mtd_to_nand(mtd);
1782         int off = BADBLOCK_MARKER_LENGTH;
1783 
1784         if (section)
1785                 return -ERANGE;
1786 
1787         /*
1788          * When SW correction is employed, one OMAP specific marker byte is
1789          * reserved after each ECC step.
1790          */
1791         off += ((chip->ecc.bytes + 1) * chip->ecc.steps);
1792         if (off >= mtd->oobsize)
1793                 return -ERANGE;
1794 
1795         oobregion->offset = off;
1796         oobregion->length = mtd->oobsize - off;
1797 
1798         return 0;
1799 }
1800 
1801 static const struct mtd_ooblayout_ops omap_sw_ooblayout_ops = {
1802         .ecc = omap_sw_ooblayout_ecc,
1803         .free = omap_sw_ooblayout_free,
1804 };
1805 
1806 static int omap_nand_probe(struct platform_device *pdev)
1807 {
1808         struct omap_nand_info           *info;
1809         struct omap_nand_platform_data  *pdata = NULL;
1810         struct mtd_info                 *mtd;
1811         struct nand_chip                *nand_chip;
1812         int                             err;
1813         dma_cap_mask_t                  mask;
1814         unsigned                        sig;
1815         struct resource                 *res;
1816         struct device                   *dev = &pdev->dev;
1817         int                             min_oobbytes = BADBLOCK_MARKER_LENGTH;
1818         int                             oobbytes_per_step;
1819 
1820         info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info),
1821                                 GFP_KERNEL);
1822         if (!info)
1823                 return -ENOMEM;
1824 
1825         info->pdev = pdev;
1826 
1827         if (dev->of_node) {
1828                 if (omap_get_dt_info(dev, info))
1829                         return -EINVAL;
1830         } else {
1831                 pdata = dev_get_platdata(&pdev->dev);
1832                 if (!pdata) {
1833                         dev_err(&pdev->dev, "platform data missing\n");
1834                         return -EINVAL;
1835                 }
1836 
1837                 info->gpmc_cs = pdata->cs;
1838                 info->reg = pdata->reg;
1839                 info->ecc_opt = pdata->ecc_opt;
1840                 if (pdata->dev_ready)
1841                         dev_info(&pdev->dev, "pdata->dev_ready is deprecated\n");
1842 
1843                 info->xfer_type = pdata->xfer_type;
1844                 info->devsize = pdata->devsize;
1845                 info->elm_of_node = pdata->elm_of_node;
1846                 info->flash_bbt = pdata->flash_bbt;
1847         }
1848 
1849         platform_set_drvdata(pdev, info);
1850         info->ops = gpmc_omap_get_nand_ops(&info->reg, info->gpmc_cs);
1851         if (!info->ops) {
1852                 dev_err(&pdev->dev, "Failed to get GPMC->NAND interface\n");
1853                 return -ENODEV;
1854         }
1855 
1856         nand_chip               = &info->nand;
1857         mtd                     = nand_to_mtd(nand_chip);
1858         mtd->dev.parent         = &pdev->dev;
1859         nand_chip->ecc.priv     = NULL;
1860         nand_set_flash_node(nand_chip, dev->of_node);
1861 
1862         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1863         nand_chip->IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res);
1864         if (IS_ERR(nand_chip->IO_ADDR_R))
1865                 return PTR_ERR(nand_chip->IO_ADDR_R);
1866 
1867         info->phys_base = res->start;
1868 
1869         nand_chip->controller = &omap_gpmc_controller;
1870 
1871         nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R;
1872         nand_chip->cmd_ctrl  = omap_hwcontrol;
1873 
1874         info->ready_gpiod = devm_gpiod_get_optional(&pdev->dev, "rb",
1875                                                     GPIOD_IN);
1876         if (IS_ERR(info->ready_gpiod)) {
1877                 dev_err(dev, "failed to get ready gpio\n");
1878                 return PTR_ERR(info->ready_gpiod);
1879         }
1880 
1881         /*
1882          * If RDY/BSY line is connected to OMAP then use the omap ready
1883          * function and the generic nand_wait function which reads the status
1884          * register after monitoring the RDY/BSY line. Otherwise use a standard
1885          * chip delay which is slightly more than tR (AC Timing) of the NAND
1886          * device and read status register until you get a failure or success
1887          */
1888         if (info->ready_gpiod) {
1889                 nand_chip->dev_ready = omap_dev_ready;
1890                 nand_chip->chip_delay = 0;
1891         } else {
1892                 nand_chip->waitfunc = omap_wait;
1893                 nand_chip->chip_delay = 50;
1894         }
1895 
1896         if (info->flash_bbt)
1897                 nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
1898 
1899         /* scan NAND device connected to chip controller */
1900         nand_chip->options |= info->devsize & NAND_BUSWIDTH_16;
1901         if (nand_scan_ident(mtd, 1, NULL)) {
1902                 dev_err(&info->pdev->dev,
1903                         "scan failed, may be bus-width mismatch\n");
1904                 err = -ENXIO;
1905                 goto return_error;
1906         }
1907 
1908         if (nand_chip->bbt_options & NAND_BBT_USE_FLASH)
1909                 nand_chip->bbt_options |= NAND_BBT_NO_OOB;
1910         else
1911                 nand_chip->options |= NAND_SKIP_BBTSCAN;
1912 
1913         /* re-populate low-level callbacks based on xfer modes */
1914         switch (info->xfer_type) {
1915         case NAND_OMAP_PREFETCH_POLLED:
1916                 nand_chip->read_buf   = omap_read_buf_pref;
1917                 nand_chip->write_buf  = omap_write_buf_pref;
1918                 break;
1919 
1920         case NAND_OMAP_POLLED:
1921                 /* Use nand_base defaults for {read,write}_buf */
1922                 break;
1923 
1924         case NAND_OMAP_PREFETCH_DMA:
1925                 dma_cap_zero(mask);
1926                 dma_cap_set(DMA_SLAVE, mask);
1927                 sig = OMAP24XX_DMA_GPMC;
1928                 info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1929                 if (!info->dma) {
1930                         dev_err(&pdev->dev, "DMA engine request failed\n");
1931                         err = -ENXIO;
1932                         goto return_error;
1933                 } else {
1934                         struct dma_slave_config cfg;
1935 
1936                         memset(&cfg, 0, sizeof(cfg));
1937                         cfg.src_addr = info->phys_base;
1938                         cfg.dst_addr = info->phys_base;
1939                         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1940                         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1941                         cfg.src_maxburst = 16;
1942                         cfg.dst_maxburst = 16;
1943                         err = dmaengine_slave_config(info->dma, &cfg);
1944                         if (err) {
1945                                 dev_err(&pdev->dev, "DMA engine slave config failed: %d\n",
1946                                         err);
1947                                 goto return_error;
1948                         }
1949                         nand_chip->read_buf   = omap_read_buf_dma_pref;
1950                         nand_chip->write_buf  = omap_write_buf_dma_pref;
1951                 }
1952                 break;
1953 
1954         case NAND_OMAP_PREFETCH_IRQ:
1955                 info->gpmc_irq_fifo = platform_get_irq(pdev, 0);
1956                 if (info->gpmc_irq_fifo <= 0) {
1957                         dev_err(&pdev->dev, "error getting fifo irq\n");
1958                         err = -ENODEV;
1959                         goto return_error;
1960                 }
1961                 err = devm_request_irq(&pdev->dev, info->gpmc_irq_fifo,
1962                                         omap_nand_irq, IRQF_SHARED,
1963                                         "gpmc-nand-fifo", info);
1964                 if (err) {
1965                         dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1966                                                 info->gpmc_irq_fifo, err);
1967                         info->gpmc_irq_fifo = 0;
1968                         goto return_error;
1969                 }
1970 
1971                 info->gpmc_irq_count = platform_get_irq(pdev, 1);
1972                 if (info->gpmc_irq_count <= 0) {
1973                         dev_err(&pdev->dev, "error getting count irq\n");
1974                         err = -ENODEV;
1975                         goto return_error;
1976                 }
1977                 err = devm_request_irq(&pdev->dev, info->gpmc_irq_count,
1978                                         omap_nand_irq, IRQF_SHARED,
1979                                         "gpmc-nand-count", info);
1980                 if (err) {
1981                         dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1982                                                 info->gpmc_irq_count, err);
1983                         info->gpmc_irq_count = 0;
1984                         goto return_error;
1985                 }
1986 
1987                 nand_chip->read_buf  = omap_read_buf_irq_pref;
1988                 nand_chip->write_buf = omap_write_buf_irq_pref;
1989 
1990                 break;
1991 
1992         default:
1993                 dev_err(&pdev->dev,
1994                         "xfer_type(%d) not supported!\n", info->xfer_type);
1995                 err = -EINVAL;
1996                 goto return_error;
1997         }
1998 
1999         if (!omap2_nand_ecc_check(info, pdata)) {
2000                 err = -EINVAL;
2001                 goto return_error;
2002         }
2003 
2004         /*
2005          * Bail out earlier to let NAND_ECC_SOFT code create its own
2006          * ooblayout instead of using ours.
2007          */
2008         if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW) {
2009                 nand_chip->ecc.mode = NAND_ECC_SOFT;
2010                 nand_chip->ecc.algo = NAND_ECC_HAMMING;
2011                 goto scan_tail;
2012         }
2013 
2014         /* populate MTD interface based on ECC scheme */
2015         switch (info->ecc_opt) {
2016         case OMAP_ECC_HAM1_CODE_HW:
2017                 pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n");
2018                 nand_chip->ecc.mode             = NAND_ECC_HW;
2019                 nand_chip->ecc.bytes            = 3;
2020                 nand_chip->ecc.size             = 512;
2021                 nand_chip->ecc.strength         = 1;
2022                 nand_chip->ecc.calculate        = omap_calculate_ecc;
2023                 nand_chip->ecc.hwctl            = omap_enable_hwecc;
2024                 nand_chip->ecc.correct          = omap_correct_data;
2025                 mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
2026                 oobbytes_per_step               = nand_chip->ecc.bytes;
2027 
2028                 if (!(nand_chip->options & NAND_BUSWIDTH_16))
2029                         min_oobbytes            = 1;
2030 
2031                 break;
2032 
2033         case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
2034                 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n");
2035                 nand_chip->ecc.mode             = NAND_ECC_HW;
2036                 nand_chip->ecc.size             = 512;
2037                 nand_chip->ecc.bytes            = 7;
2038                 nand_chip->ecc.strength         = 4;
2039                 nand_chip->ecc.hwctl            = omap_enable_hwecc_bch;
2040                 nand_chip->ecc.correct          = nand_bch_correct_data;
2041                 nand_chip->ecc.calculate        = omap_calculate_ecc_bch;
2042                 mtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops);
2043                 /* Reserve one byte for the OMAP marker */
2044                 oobbytes_per_step               = nand_chip->ecc.bytes + 1;
2045                 /* software bch library is used for locating errors */
2046                 nand_chip->ecc.priv             = nand_bch_init(mtd);
2047                 if (!nand_chip->ecc.priv) {
2048                         dev_err(&info->pdev->dev, "unable to use BCH library\n");
2049                         err = -EINVAL;
2050                         goto return_error;
2051                 }
2052                 break;
2053 
2054         case OMAP_ECC_BCH4_CODE_HW:
2055                 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n");
2056                 nand_chip->ecc.mode             = NAND_ECC_HW;
2057                 nand_chip->ecc.size             = 512;
2058                 /* 14th bit is kept reserved for ROM-code compatibility */
2059                 nand_chip->ecc.bytes            = 7 + 1;
2060                 nand_chip->ecc.strength         = 4;
2061                 nand_chip->ecc.hwctl            = omap_enable_hwecc_bch;
2062                 nand_chip->ecc.correct          = omap_elm_correct_data;
2063                 nand_chip->ecc.calculate        = omap_calculate_ecc_bch;
2064                 nand_chip->ecc.read_page        = omap_read_page_bch;
2065                 nand_chip->ecc.write_page       = omap_write_page_bch;
2066                 mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
2067                 oobbytes_per_step               = nand_chip->ecc.bytes;
2068 
2069                 err = elm_config(info->elm_dev, BCH4_ECC,
2070                                  mtd->writesize / nand_chip->ecc.size,
2071                                  nand_chip->ecc.size, nand_chip->ecc.bytes);
2072                 if (err < 0)
2073                         goto return_error;
2074                 break;
2075 
2076         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
2077                 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
2078                 nand_chip->ecc.mode             = NAND_ECC_HW;
2079                 nand_chip->ecc.size             = 512;
2080                 nand_chip->ecc.bytes            = 13;
2081                 nand_chip->ecc.strength         = 8;
2082                 nand_chip->ecc.hwctl            = omap_enable_hwecc_bch;
2083                 nand_chip->ecc.correct          = nand_bch_correct_data;
2084                 nand_chip->ecc.calculate        = omap_calculate_ecc_bch;
2085                 mtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops);
2086                 /* Reserve one byte for the OMAP marker */
2087                 oobbytes_per_step               = nand_chip->ecc.bytes + 1;
2088                 /* software bch library is used for locating errors */
2089                 nand_chip->ecc.priv             = nand_bch_init(mtd);
2090                 if (!nand_chip->ecc.priv) {
2091                         dev_err(&info->pdev->dev, "unable to use BCH library\n");
2092                         err = -EINVAL;
2093                         goto return_error;
2094                 }
2095                 break;
2096 
2097         case OMAP_ECC_BCH8_CODE_HW:
2098                 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n");
2099                 nand_chip->ecc.mode             = NAND_ECC_HW;
2100                 nand_chip->ecc.size             = 512;
2101                 /* 14th bit is kept reserved for ROM-code compatibility */
2102                 nand_chip->ecc.bytes            = 13 + 1;
2103                 nand_chip->ecc.strength         = 8;
2104                 nand_chip->ecc.hwctl            = omap_enable_hwecc_bch;
2105                 nand_chip->ecc.correct          = omap_elm_correct_data;
2106                 nand_chip->ecc.calculate        = omap_calculate_ecc_bch;
2107                 nand_chip->ecc.read_page        = omap_read_page_bch;
2108                 nand_chip->ecc.write_page       = omap_write_page_bch;
2109                 mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
2110                 oobbytes_per_step               = nand_chip->ecc.bytes;
2111 
2112                 err = elm_config(info->elm_dev, BCH8_ECC,
2113                                  mtd->writesize / nand_chip->ecc.size,
2114                                  nand_chip->ecc.size, nand_chip->ecc.bytes);
2115                 if (err < 0)
2116                         goto return_error;
2117 
2118                 break;
2119 
2120         case OMAP_ECC_BCH16_CODE_HW:
2121                 pr_info("using OMAP_ECC_BCH16_CODE_HW ECC scheme\n");
2122                 nand_chip->ecc.mode             = NAND_ECC_HW;
2123                 nand_chip->ecc.size             = 512;
2124                 nand_chip->ecc.bytes            = 26;
2125                 nand_chip->ecc.strength         = 16;
2126                 nand_chip->ecc.hwctl            = omap_enable_hwecc_bch;
2127                 nand_chip->ecc.correct          = omap_elm_correct_data;
2128                 nand_chip->ecc.calculate        = omap_calculate_ecc_bch;
2129                 nand_chip->ecc.read_page        = omap_read_page_bch;
2130                 nand_chip->ecc.write_page       = omap_write_page_bch;
2131                 mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
2132                 oobbytes_per_step               = nand_chip->ecc.bytes;
2133 
2134                 err = elm_config(info->elm_dev, BCH16_ECC,
2135                                  mtd->writesize / nand_chip->ecc.size,
2136                                  nand_chip->ecc.size, nand_chip->ecc.bytes);
2137                 if (err < 0)
2138                         goto return_error;
2139 
2140                 break;
2141         default:
2142                 dev_err(&info->pdev->dev, "invalid or unsupported ECC scheme\n");
2143                 err = -EINVAL;
2144                 goto return_error;
2145         }
2146 
2147         /* check if NAND device's OOB is enough to store ECC signatures */
2148         min_oobbytes += (oobbytes_per_step *
2149                          (mtd->writesize / nand_chip->ecc.size));
2150         if (mtd->oobsize < min_oobbytes) {
2151                 dev_err(&info->pdev->dev,
2152                         "not enough OOB bytes required = %d, available=%d\n",
2153                         min_oobbytes, mtd->oobsize);
2154                 err = -EINVAL;
2155                 goto return_error;
2156         }
2157 
2158 scan_tail:
2159         /* second phase scan */
2160         if (nand_scan_tail(mtd)) {
2161                 err = -ENXIO;
2162                 goto return_error;
2163         }
2164 
2165         if (dev->of_node)
2166                 mtd_device_register(mtd, NULL, 0);
2167         else
2168                 mtd_device_register(mtd, pdata->parts, pdata->nr_parts);
2169 
2170         platform_set_drvdata(pdev, mtd);
2171 
2172         return 0;
2173 
2174 return_error:
2175         if (info->dma)
2176                 dma_release_channel(info->dma);
2177         if (nand_chip->ecc.priv) {
2178                 nand_bch_free(nand_chip->ecc.priv);
2179                 nand_chip->ecc.priv = NULL;
2180         }
2181         return err;
2182 }
2183 
2184 static int omap_nand_remove(struct platform_device *pdev)
2185 {
2186         struct mtd_info *mtd = platform_get_drvdata(pdev);
2187         struct nand_chip *nand_chip = mtd_to_nand(mtd);
2188         struct omap_nand_info *info = mtd_to_omap(mtd);
2189         if (nand_chip->ecc.priv) {
2190                 nand_bch_free(nand_chip->ecc.priv);
2191                 nand_chip->ecc.priv = NULL;
2192         }
2193         if (info->dma)
2194                 dma_release_channel(info->dma);
2195         nand_release(mtd);
2196         return 0;
2197 }
2198 
2199 static const struct of_device_id omap_nand_ids[] = {
2200         { .compatible = "ti,omap2-nand", },
2201         {},
2202 };
2203 
2204 static struct platform_driver omap_nand_driver = {
2205         .probe          = omap_nand_probe,
2206         .remove         = omap_nand_remove,
2207         .driver         = {
2208                 .name   = DRIVER_NAME,
2209                 .of_match_table = of_match_ptr(omap_nand_ids),
2210         },
2211 };
2212 
2213 module_platform_driver(omap_nand_driver);
2214 
2215 MODULE_ALIAS("platform:" DRIVER_NAME);
2216 MODULE_LICENSE("GPL");
2217 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");
2218 

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