Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/drivers/mtd/nand/mxc_nand.c

  1 /*
  2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  3  * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
  4  *
  5  * This program is free software; you can redistribute it and/or
  6  * modify it under the terms of the GNU General Public License
  7  * as published by the Free Software Foundation; either version 2
  8  * of the License, or (at your option) any later version.
  9  * This program is distributed in the hope that it will be useful,
 10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 12  * GNU General Public License for more details.
 13  *
 14  * You should have received a copy of the GNU General Public License
 15  * along with this program; if not, write to the Free Software
 16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 17  * MA 02110-1301, USA.
 18  */
 19 
 20 #include <linux/delay.h>
 21 #include <linux/slab.h>
 22 #include <linux/init.h>
 23 #include <linux/module.h>
 24 #include <linux/mtd/mtd.h>
 25 #include <linux/mtd/nand.h>
 26 #include <linux/mtd/partitions.h>
 27 #include <linux/interrupt.h>
 28 #include <linux/device.h>
 29 #include <linux/platform_device.h>
 30 #include <linux/clk.h>
 31 #include <linux/err.h>
 32 #include <linux/io.h>
 33 #include <linux/irq.h>
 34 #include <linux/completion.h>
 35 #include <linux/of.h>
 36 #include <linux/of_device.h>
 37 #include <linux/of_mtd.h>
 38 
 39 #include <asm/mach/flash.h>
 40 #include <linux/platform_data/mtd-mxc_nand.h>
 41 
 42 #define DRIVER_NAME "mxc_nand"
 43 
 44 /* Addresses for NFC registers */
 45 #define NFC_V1_V2_BUF_SIZE              (host->regs + 0x00)
 46 #define NFC_V1_V2_BUF_ADDR              (host->regs + 0x04)
 47 #define NFC_V1_V2_FLASH_ADDR            (host->regs + 0x06)
 48 #define NFC_V1_V2_FLASH_CMD             (host->regs + 0x08)
 49 #define NFC_V1_V2_CONFIG                (host->regs + 0x0a)
 50 #define NFC_V1_V2_ECC_STATUS_RESULT     (host->regs + 0x0c)
 51 #define NFC_V1_V2_RSLTMAIN_AREA         (host->regs + 0x0e)
 52 #define NFC_V1_V2_RSLTSPARE_AREA        (host->regs + 0x10)
 53 #define NFC_V1_V2_WRPROT                (host->regs + 0x12)
 54 #define NFC_V1_UNLOCKSTART_BLKADDR      (host->regs + 0x14)
 55 #define NFC_V1_UNLOCKEND_BLKADDR        (host->regs + 0x16)
 56 #define NFC_V21_UNLOCKSTART_BLKADDR0    (host->regs + 0x20)
 57 #define NFC_V21_UNLOCKSTART_BLKADDR1    (host->regs + 0x24)
 58 #define NFC_V21_UNLOCKSTART_BLKADDR2    (host->regs + 0x28)
 59 #define NFC_V21_UNLOCKSTART_BLKADDR3    (host->regs + 0x2c)
 60 #define NFC_V21_UNLOCKEND_BLKADDR0      (host->regs + 0x22)
 61 #define NFC_V21_UNLOCKEND_BLKADDR1      (host->regs + 0x26)
 62 #define NFC_V21_UNLOCKEND_BLKADDR2      (host->regs + 0x2a)
 63 #define NFC_V21_UNLOCKEND_BLKADDR3      (host->regs + 0x2e)
 64 #define NFC_V1_V2_NF_WRPRST             (host->regs + 0x18)
 65 #define NFC_V1_V2_CONFIG1               (host->regs + 0x1a)
 66 #define NFC_V1_V2_CONFIG2               (host->regs + 0x1c)
 67 
 68 #define NFC_V2_CONFIG1_ECC_MODE_4       (1 << 0)
 69 #define NFC_V1_V2_CONFIG1_SP_EN         (1 << 2)
 70 #define NFC_V1_V2_CONFIG1_ECC_EN        (1 << 3)
 71 #define NFC_V1_V2_CONFIG1_INT_MSK       (1 << 4)
 72 #define NFC_V1_V2_CONFIG1_BIG           (1 << 5)
 73 #define NFC_V1_V2_CONFIG1_RST           (1 << 6)
 74 #define NFC_V1_V2_CONFIG1_CE            (1 << 7)
 75 #define NFC_V2_CONFIG1_ONE_CYCLE        (1 << 8)
 76 #define NFC_V2_CONFIG1_PPB(x)           (((x) & 0x3) << 9)
 77 #define NFC_V2_CONFIG1_FP_INT           (1 << 11)
 78 
 79 #define NFC_V1_V2_CONFIG2_INT           (1 << 15)
 80 
 81 /*
 82  * Operation modes for the NFC. Valid for v1, v2 and v3
 83  * type controllers.
 84  */
 85 #define NFC_CMD                         (1 << 0)
 86 #define NFC_ADDR                        (1 << 1)
 87 #define NFC_INPUT                       (1 << 2)
 88 #define NFC_OUTPUT                      (1 << 3)
 89 #define NFC_ID                          (1 << 4)
 90 #define NFC_STATUS                      (1 << 5)
 91 
 92 #define NFC_V3_FLASH_CMD                (host->regs_axi + 0x00)
 93 #define NFC_V3_FLASH_ADDR0              (host->regs_axi + 0x04)
 94 
 95 #define NFC_V3_CONFIG1                  (host->regs_axi + 0x34)
 96 #define NFC_V3_CONFIG1_SP_EN            (1 << 0)
 97 #define NFC_V3_CONFIG1_RBA(x)           (((x) & 0x7 ) << 4)
 98 
 99 #define NFC_V3_ECC_STATUS_RESULT        (host->regs_axi + 0x38)
100 
101 #define NFC_V3_LAUNCH                   (host->regs_axi + 0x40)
102 
103 #define NFC_V3_WRPROT                   (host->regs_ip + 0x0)
104 #define NFC_V3_WRPROT_LOCK_TIGHT        (1 << 0)
105 #define NFC_V3_WRPROT_LOCK              (1 << 1)
106 #define NFC_V3_WRPROT_UNLOCK            (1 << 2)
107 #define NFC_V3_WRPROT_BLS_UNLOCK        (2 << 6)
108 
109 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0   (host->regs_ip + 0x04)
110 
111 #define NFC_V3_CONFIG2                  (host->regs_ip + 0x24)
112 #define NFC_V3_CONFIG2_PS_512                   (0 << 0)
113 #define NFC_V3_CONFIG2_PS_2048                  (1 << 0)
114 #define NFC_V3_CONFIG2_PS_4096                  (2 << 0)
115 #define NFC_V3_CONFIG2_ONE_CYCLE                (1 << 2)
116 #define NFC_V3_CONFIG2_ECC_EN                   (1 << 3)
117 #define NFC_V3_CONFIG2_2CMD_PHASES              (1 << 4)
118 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0          (1 << 5)
119 #define NFC_V3_CONFIG2_ECC_MODE_8               (1 << 6)
120 #define NFC_V3_CONFIG2_PPB(x, shift)            (((x) & 0x3) << shift)
121 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x)       (((x) & 0x3) << 12)
122 #define NFC_V3_CONFIG2_INT_MSK                  (1 << 15)
123 #define NFC_V3_CONFIG2_ST_CMD(x)                (((x) & 0xff) << 24)
124 #define NFC_V3_CONFIG2_SPAS(x)                  (((x) & 0xff) << 16)
125 
126 #define NFC_V3_CONFIG3                          (host->regs_ip + 0x28)
127 #define NFC_V3_CONFIG3_ADD_OP(x)                (((x) & 0x3) << 0)
128 #define NFC_V3_CONFIG3_FW8                      (1 << 3)
129 #define NFC_V3_CONFIG3_SBB(x)                   (((x) & 0x7) << 8)
130 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x)        (((x) & 0x7) << 12)
131 #define NFC_V3_CONFIG3_RBB_MODE                 (1 << 15)
132 #define NFC_V3_CONFIG3_NO_SDMA                  (1 << 20)
133 
134 #define NFC_V3_IPC                      (host->regs_ip + 0x2C)
135 #define NFC_V3_IPC_CREQ                 (1 << 0)
136 #define NFC_V3_IPC_INT                  (1 << 31)
137 
138 #define NFC_V3_DELAY_LINE               (host->regs_ip + 0x34)
139 
140 struct mxc_nand_host;
141 
142 struct mxc_nand_devtype_data {
143         void (*preset)(struct mtd_info *);
144         void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
145         void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
146         void (*send_page)(struct mtd_info *, unsigned int);
147         void (*send_read_id)(struct mxc_nand_host *);
148         uint16_t (*get_dev_status)(struct mxc_nand_host *);
149         int (*check_int)(struct mxc_nand_host *);
150         void (*irq_control)(struct mxc_nand_host *, int);
151         u32 (*get_ecc_status)(struct mxc_nand_host *);
152         struct nand_ecclayout *ecclayout_512, *ecclayout_2k, *ecclayout_4k;
153         void (*select_chip)(struct mtd_info *mtd, int chip);
154         int (*correct_data)(struct mtd_info *mtd, u_char *dat,
155                         u_char *read_ecc, u_char *calc_ecc);
156 
157         /*
158          * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
159          * (CONFIG1:INT_MSK is set). To handle this the driver uses
160          * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
161          */
162         int irqpending_quirk;
163         int needs_ip;
164 
165         size_t regs_offset;
166         size_t spare0_offset;
167         size_t axi_offset;
168 
169         int spare_len;
170         int eccbytes;
171         int eccsize;
172         int ppb_shift;
173 };
174 
175 struct mxc_nand_host {
176         struct mtd_info         mtd;
177         struct nand_chip        nand;
178         struct device           *dev;
179 
180         void __iomem            *spare0;
181         void __iomem            *main_area0;
182 
183         void __iomem            *base;
184         void __iomem            *regs;
185         void __iomem            *regs_axi;
186         void __iomem            *regs_ip;
187         int                     status_request;
188         struct clk              *clk;
189         int                     clk_act;
190         int                     irq;
191         int                     eccsize;
192         int                     active_cs;
193 
194         struct completion       op_completion;
195 
196         uint8_t                 *data_buf;
197         unsigned int            buf_start;
198 
199         const struct mxc_nand_devtype_data *devtype_data;
200         struct mxc_nand_platform_data pdata;
201 };
202 
203 /* OOB placement block for use with hardware ecc generation */
204 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
205         .eccbytes = 5,
206         .eccpos = {6, 7, 8, 9, 10},
207         .oobfree = {{0, 5}, {12, 4}, }
208 };
209 
210 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
211         .eccbytes = 20,
212         .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
213                    38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
214         .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
215 };
216 
217 /* OOB description for 512 byte pages with 16 byte OOB */
218 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
219         .eccbytes = 1 * 9,
220         .eccpos = {
221                  7,  8,  9, 10, 11, 12, 13, 14, 15
222         },
223         .oobfree = {
224                 {.offset = 0, .length = 5}
225         }
226 };
227 
228 /* OOB description for 2048 byte pages with 64 byte OOB */
229 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
230         .eccbytes = 4 * 9,
231         .eccpos = {
232                  7,  8,  9, 10, 11, 12, 13, 14, 15,
233                 23, 24, 25, 26, 27, 28, 29, 30, 31,
234                 39, 40, 41, 42, 43, 44, 45, 46, 47,
235                 55, 56, 57, 58, 59, 60, 61, 62, 63
236         },
237         .oobfree = {
238                 {.offset = 2, .length = 4},
239                 {.offset = 16, .length = 7},
240                 {.offset = 32, .length = 7},
241                 {.offset = 48, .length = 7}
242         }
243 };
244 
245 /* OOB description for 4096 byte pages with 128 byte OOB */
246 static struct nand_ecclayout nandv2_hw_eccoob_4k = {
247         .eccbytes = 8 * 9,
248         .eccpos = {
249                 7,  8,  9, 10, 11, 12, 13, 14, 15,
250                 23, 24, 25, 26, 27, 28, 29, 30, 31,
251                 39, 40, 41, 42, 43, 44, 45, 46, 47,
252                 55, 56, 57, 58, 59, 60, 61, 62, 63,
253                 71, 72, 73, 74, 75, 76, 77, 78, 79,
254                 87, 88, 89, 90, 91, 92, 93, 94, 95,
255                 103, 104, 105, 106, 107, 108, 109, 110, 111,
256                 119, 120, 121, 122, 123, 124, 125, 126, 127,
257         },
258         .oobfree = {
259                 {.offset = 2, .length = 4},
260                 {.offset = 16, .length = 7},
261                 {.offset = 32, .length = 7},
262                 {.offset = 48, .length = 7},
263                 {.offset = 64, .length = 7},
264                 {.offset = 80, .length = 7},
265                 {.offset = 96, .length = 7},
266                 {.offset = 112, .length = 7},
267         }
268 };
269 
270 static const char * const part_probes[] = {
271         "cmdlinepart", "RedBoot", "ofpart", NULL };
272 
273 static void memcpy32_fromio(void *trg, const void __iomem  *src, size_t size)
274 {
275         int i;
276         u32 *t = trg;
277         const __iomem u32 *s = src;
278 
279         for (i = 0; i < (size >> 2); i++)
280                 *t++ = __raw_readl(s++);
281 }
282 
283 static void memcpy32_toio(void __iomem *trg, const void *src, int size)
284 {
285         int i;
286         u32 __iomem *t = trg;
287         const u32 *s = src;
288 
289         for (i = 0; i < (size >> 2); i++)
290                 __raw_writel(*s++, t++);
291 }
292 
293 static int check_int_v3(struct mxc_nand_host *host)
294 {
295         uint32_t tmp;
296 
297         tmp = readl(NFC_V3_IPC);
298         if (!(tmp & NFC_V3_IPC_INT))
299                 return 0;
300 
301         tmp &= ~NFC_V3_IPC_INT;
302         writel(tmp, NFC_V3_IPC);
303 
304         return 1;
305 }
306 
307 static int check_int_v1_v2(struct mxc_nand_host *host)
308 {
309         uint32_t tmp;
310 
311         tmp = readw(NFC_V1_V2_CONFIG2);
312         if (!(tmp & NFC_V1_V2_CONFIG2_INT))
313                 return 0;
314 
315         if (!host->devtype_data->irqpending_quirk)
316                 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
317 
318         return 1;
319 }
320 
321 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
322 {
323         uint16_t tmp;
324 
325         tmp = readw(NFC_V1_V2_CONFIG1);
326 
327         if (activate)
328                 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
329         else
330                 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
331 
332         writew(tmp, NFC_V1_V2_CONFIG1);
333 }
334 
335 static void irq_control_v3(struct mxc_nand_host *host, int activate)
336 {
337         uint32_t tmp;
338 
339         tmp = readl(NFC_V3_CONFIG2);
340 
341         if (activate)
342                 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
343         else
344                 tmp |= NFC_V3_CONFIG2_INT_MSK;
345 
346         writel(tmp, NFC_V3_CONFIG2);
347 }
348 
349 static void irq_control(struct mxc_nand_host *host, int activate)
350 {
351         if (host->devtype_data->irqpending_quirk) {
352                 if (activate)
353                         enable_irq(host->irq);
354                 else
355                         disable_irq_nosync(host->irq);
356         } else {
357                 host->devtype_data->irq_control(host, activate);
358         }
359 }
360 
361 static u32 get_ecc_status_v1(struct mxc_nand_host *host)
362 {
363         return readw(NFC_V1_V2_ECC_STATUS_RESULT);
364 }
365 
366 static u32 get_ecc_status_v2(struct mxc_nand_host *host)
367 {
368         return readl(NFC_V1_V2_ECC_STATUS_RESULT);
369 }
370 
371 static u32 get_ecc_status_v3(struct mxc_nand_host *host)
372 {
373         return readl(NFC_V3_ECC_STATUS_RESULT);
374 }
375 
376 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
377 {
378         struct mxc_nand_host *host = dev_id;
379 
380         if (!host->devtype_data->check_int(host))
381                 return IRQ_NONE;
382 
383         irq_control(host, 0);
384 
385         complete(&host->op_completion);
386 
387         return IRQ_HANDLED;
388 }
389 
390 /* This function polls the NANDFC to wait for the basic operation to
391  * complete by checking the INT bit of config2 register.
392  */
393 static void wait_op_done(struct mxc_nand_host *host, int useirq)
394 {
395         int max_retries = 8000;
396 
397         if (useirq) {
398                 if (!host->devtype_data->check_int(host)) {
399                         reinit_completion(&host->op_completion);
400                         irq_control(host, 1);
401                         wait_for_completion(&host->op_completion);
402                 }
403         } else {
404                 while (max_retries-- > 0) {
405                         if (host->devtype_data->check_int(host))
406                                 break;
407 
408                         udelay(1);
409                 }
410                 if (max_retries < 0)
411                         pr_debug("%s: INT not set\n", __func__);
412         }
413 }
414 
415 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
416 {
417         /* fill command */
418         writel(cmd, NFC_V3_FLASH_CMD);
419 
420         /* send out command */
421         writel(NFC_CMD, NFC_V3_LAUNCH);
422 
423         /* Wait for operation to complete */
424         wait_op_done(host, useirq);
425 }
426 
427 /* This function issues the specified command to the NAND device and
428  * waits for completion. */
429 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
430 {
431         pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq);
432 
433         writew(cmd, NFC_V1_V2_FLASH_CMD);
434         writew(NFC_CMD, NFC_V1_V2_CONFIG2);
435 
436         if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
437                 int max_retries = 100;
438                 /* Reset completion is indicated by NFC_CONFIG2 */
439                 /* being set to 0 */
440                 while (max_retries-- > 0) {
441                         if (readw(NFC_V1_V2_CONFIG2) == 0) {
442                                 break;
443                         }
444                         udelay(1);
445                 }
446                 if (max_retries < 0)
447                         pr_debug("%s: RESET failed\n", __func__);
448         } else {
449                 /* Wait for operation to complete */
450                 wait_op_done(host, useirq);
451         }
452 }
453 
454 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
455 {
456         /* fill address */
457         writel(addr, NFC_V3_FLASH_ADDR0);
458 
459         /* send out address */
460         writel(NFC_ADDR, NFC_V3_LAUNCH);
461 
462         wait_op_done(host, 0);
463 }
464 
465 /* This function sends an address (or partial address) to the
466  * NAND device. The address is used to select the source/destination for
467  * a NAND command. */
468 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
469 {
470         pr_debug("send_addr(host, 0x%x %d)\n", addr, islast);
471 
472         writew(addr, NFC_V1_V2_FLASH_ADDR);
473         writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
474 
475         /* Wait for operation to complete */
476         wait_op_done(host, islast);
477 }
478 
479 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
480 {
481         struct nand_chip *nand_chip = mtd->priv;
482         struct mxc_nand_host *host = nand_chip->priv;
483         uint32_t tmp;
484 
485         tmp = readl(NFC_V3_CONFIG1);
486         tmp &= ~(7 << 4);
487         writel(tmp, NFC_V3_CONFIG1);
488 
489         /* transfer data from NFC ram to nand */
490         writel(ops, NFC_V3_LAUNCH);
491 
492         wait_op_done(host, false);
493 }
494 
495 static void send_page_v2(struct mtd_info *mtd, unsigned int ops)
496 {
497         struct nand_chip *nand_chip = mtd->priv;
498         struct mxc_nand_host *host = nand_chip->priv;
499 
500         /* NANDFC buffer 0 is used for page read/write */
501         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
502 
503         writew(ops, NFC_V1_V2_CONFIG2);
504 
505         /* Wait for operation to complete */
506         wait_op_done(host, true);
507 }
508 
509 static void send_page_v1(struct mtd_info *mtd, unsigned int ops)
510 {
511         struct nand_chip *nand_chip = mtd->priv;
512         struct mxc_nand_host *host = nand_chip->priv;
513         int bufs, i;
514 
515         if (mtd->writesize > 512)
516                 bufs = 4;
517         else
518                 bufs = 1;
519 
520         for (i = 0; i < bufs; i++) {
521 
522                 /* NANDFC buffer 0 is used for page read/write */
523                 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
524 
525                 writew(ops, NFC_V1_V2_CONFIG2);
526 
527                 /* Wait for operation to complete */
528                 wait_op_done(host, true);
529         }
530 }
531 
532 static void send_read_id_v3(struct mxc_nand_host *host)
533 {
534         struct nand_chip *this = &host->nand;
535 
536         /* Read ID into main buffer */
537         writel(NFC_ID, NFC_V3_LAUNCH);
538 
539         wait_op_done(host, true);
540 
541         memcpy32_fromio(host->data_buf, host->main_area0, 16);
542 
543         if (this->options & NAND_BUSWIDTH_16) {
544                 /* compress the ID info */
545                 host->data_buf[1] = host->data_buf[2];
546                 host->data_buf[2] = host->data_buf[4];
547                 host->data_buf[3] = host->data_buf[6];
548                 host->data_buf[4] = host->data_buf[8];
549                 host->data_buf[5] = host->data_buf[10];
550         }
551 }
552 
553 /* Request the NANDFC to perform a read of the NAND device ID. */
554 static void send_read_id_v1_v2(struct mxc_nand_host *host)
555 {
556         struct nand_chip *this = &host->nand;
557 
558         /* NANDFC buffer 0 is used for device ID output */
559         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
560 
561         writew(NFC_ID, NFC_V1_V2_CONFIG2);
562 
563         /* Wait for operation to complete */
564         wait_op_done(host, true);
565 
566         memcpy32_fromio(host->data_buf, host->main_area0, 16);
567 
568         if (this->options & NAND_BUSWIDTH_16) {
569                 /* compress the ID info */
570                 host->data_buf[1] = host->data_buf[2];
571                 host->data_buf[2] = host->data_buf[4];
572                 host->data_buf[3] = host->data_buf[6];
573                 host->data_buf[4] = host->data_buf[8];
574                 host->data_buf[5] = host->data_buf[10];
575         }
576 }
577 
578 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
579 {
580         writew(NFC_STATUS, NFC_V3_LAUNCH);
581         wait_op_done(host, true);
582 
583         return readl(NFC_V3_CONFIG1) >> 16;
584 }
585 
586 /* This function requests the NANDFC to perform a read of the
587  * NAND device status and returns the current status. */
588 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
589 {
590         void __iomem *main_buf = host->main_area0;
591         uint32_t store;
592         uint16_t ret;
593 
594         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
595 
596         /*
597          * The device status is stored in main_area0. To
598          * prevent corruption of the buffer save the value
599          * and restore it afterwards.
600          */
601         store = readl(main_buf);
602 
603         writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
604         wait_op_done(host, true);
605 
606         ret = readw(main_buf);
607 
608         writel(store, main_buf);
609 
610         return ret;
611 }
612 
613 /* This functions is used by upper layer to checks if device is ready */
614 static int mxc_nand_dev_ready(struct mtd_info *mtd)
615 {
616         /*
617          * NFC handles R/B internally. Therefore, this function
618          * always returns status as ready.
619          */
620         return 1;
621 }
622 
623 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
624 {
625         /*
626          * If HW ECC is enabled, we turn it on during init. There is
627          * no need to enable again here.
628          */
629 }
630 
631 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
632                                  u_char *read_ecc, u_char *calc_ecc)
633 {
634         struct nand_chip *nand_chip = mtd->priv;
635         struct mxc_nand_host *host = nand_chip->priv;
636 
637         /*
638          * 1-Bit errors are automatically corrected in HW.  No need for
639          * additional correction.  2-Bit errors cannot be corrected by
640          * HW ECC, so we need to return failure
641          */
642         uint16_t ecc_status = get_ecc_status_v1(host);
643 
644         if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
645                 pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
646                 return -1;
647         }
648 
649         return 0;
650 }
651 
652 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
653                                  u_char *read_ecc, u_char *calc_ecc)
654 {
655         struct nand_chip *nand_chip = mtd->priv;
656         struct mxc_nand_host *host = nand_chip->priv;
657         u32 ecc_stat, err;
658         int no_subpages = 1;
659         int ret = 0;
660         u8 ecc_bit_mask, err_limit;
661 
662         ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
663         err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
664 
665         no_subpages = mtd->writesize >> 9;
666 
667         ecc_stat = host->devtype_data->get_ecc_status(host);
668 
669         do {
670                 err = ecc_stat & ecc_bit_mask;
671                 if (err > err_limit) {
672                         printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
673                         return -1;
674                 } else {
675                         ret += err;
676                 }
677                 ecc_stat >>= 4;
678         } while (--no_subpages);
679 
680         pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
681 
682         return ret;
683 }
684 
685 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
686                                   u_char *ecc_code)
687 {
688         return 0;
689 }
690 
691 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
692 {
693         struct nand_chip *nand_chip = mtd->priv;
694         struct mxc_nand_host *host = nand_chip->priv;
695         uint8_t ret;
696 
697         /* Check for status request */
698         if (host->status_request)
699                 return host->devtype_data->get_dev_status(host) & 0xFF;
700 
701         ret = *(uint8_t *)(host->data_buf + host->buf_start);
702         host->buf_start++;
703 
704         return ret;
705 }
706 
707 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
708 {
709         struct nand_chip *nand_chip = mtd->priv;
710         struct mxc_nand_host *host = nand_chip->priv;
711         uint16_t ret;
712 
713         ret = *(uint16_t *)(host->data_buf + host->buf_start);
714         host->buf_start += 2;
715 
716         return ret;
717 }
718 
719 /* Write data of length len to buffer buf. The data to be
720  * written on NAND Flash is first copied to RAMbuffer. After the Data Input
721  * Operation by the NFC, the data is written to NAND Flash */
722 static void mxc_nand_write_buf(struct mtd_info *mtd,
723                                 const u_char *buf, int len)
724 {
725         struct nand_chip *nand_chip = mtd->priv;
726         struct mxc_nand_host *host = nand_chip->priv;
727         u16 col = host->buf_start;
728         int n = mtd->oobsize + mtd->writesize - col;
729 
730         n = min(n, len);
731 
732         memcpy(host->data_buf + col, buf, n);
733 
734         host->buf_start += n;
735 }
736 
737 /* Read the data buffer from the NAND Flash. To read the data from NAND
738  * Flash first the data output cycle is initiated by the NFC, which copies
739  * the data to RAMbuffer. This data of length len is then copied to buffer buf.
740  */
741 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
742 {
743         struct nand_chip *nand_chip = mtd->priv;
744         struct mxc_nand_host *host = nand_chip->priv;
745         u16 col = host->buf_start;
746         int n = mtd->oobsize + mtd->writesize - col;
747 
748         n = min(n, len);
749 
750         memcpy(buf, host->data_buf + col, n);
751 
752         host->buf_start += n;
753 }
754 
755 /* This function is used by upper layer for select and
756  * deselect of the NAND chip */
757 static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip)
758 {
759         struct nand_chip *nand_chip = mtd->priv;
760         struct mxc_nand_host *host = nand_chip->priv;
761 
762         if (chip == -1) {
763                 /* Disable the NFC clock */
764                 if (host->clk_act) {
765                         clk_disable_unprepare(host->clk);
766                         host->clk_act = 0;
767                 }
768                 return;
769         }
770 
771         if (!host->clk_act) {
772                 /* Enable the NFC clock */
773                 clk_prepare_enable(host->clk);
774                 host->clk_act = 1;
775         }
776 }
777 
778 static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip)
779 {
780         struct nand_chip *nand_chip = mtd->priv;
781         struct mxc_nand_host *host = nand_chip->priv;
782 
783         if (chip == -1) {
784                 /* Disable the NFC clock */
785                 if (host->clk_act) {
786                         clk_disable_unprepare(host->clk);
787                         host->clk_act = 0;
788                 }
789                 return;
790         }
791 
792         if (!host->clk_act) {
793                 /* Enable the NFC clock */
794                 clk_prepare_enable(host->clk);
795                 host->clk_act = 1;
796         }
797 
798         host->active_cs = chip;
799         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
800 }
801 
802 /*
803  * Function to transfer data to/from spare area.
804  */
805 static void copy_spare(struct mtd_info *mtd, bool bfrom)
806 {
807         struct nand_chip *this = mtd->priv;
808         struct mxc_nand_host *host = this->priv;
809         u16 i, j;
810         u16 n = mtd->writesize >> 9;
811         u8 *d = host->data_buf + mtd->writesize;
812         u8 __iomem *s = host->spare0;
813         u16 t = host->devtype_data->spare_len;
814 
815         j = (mtd->oobsize / n >> 1) << 1;
816 
817         if (bfrom) {
818                 for (i = 0; i < n - 1; i++)
819                         memcpy32_fromio(d + i * j, s + i * t, j);
820 
821                 /* the last section */
822                 memcpy32_fromio(d + i * j, s + i * t, mtd->oobsize - i * j);
823         } else {
824                 for (i = 0; i < n - 1; i++)
825                         memcpy32_toio(&s[i * t], &d[i * j], j);
826 
827                 /* the last section */
828                 memcpy32_toio(&s[i * t], &d[i * j], mtd->oobsize - i * j);
829         }
830 }
831 
832 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
833 {
834         struct nand_chip *nand_chip = mtd->priv;
835         struct mxc_nand_host *host = nand_chip->priv;
836 
837         /* Write out column address, if necessary */
838         if (column != -1) {
839                 /*
840                  * MXC NANDFC can only perform full page+spare or
841                  * spare-only read/write.  When the upper layers
842                  * perform a read/write buf operation, the saved column
843                   * address is used to index into the full page.
844                  */
845                 host->devtype_data->send_addr(host, 0, page_addr == -1);
846                 if (mtd->writesize > 512)
847                         /* another col addr cycle for 2k page */
848                         host->devtype_data->send_addr(host, 0, false);
849         }
850 
851         /* Write out page address, if necessary */
852         if (page_addr != -1) {
853                 /* paddr_0 - p_addr_7 */
854                 host->devtype_data->send_addr(host, (page_addr & 0xff), false);
855 
856                 if (mtd->writesize > 512) {
857                         if (mtd->size >= 0x10000000) {
858                                 /* paddr_8 - paddr_15 */
859                                 host->devtype_data->send_addr(host,
860                                                 (page_addr >> 8) & 0xff,
861                                                 false);
862                                 host->devtype_data->send_addr(host,
863                                                 (page_addr >> 16) & 0xff,
864                                                 true);
865                         } else
866                                 /* paddr_8 - paddr_15 */
867                                 host->devtype_data->send_addr(host,
868                                                 (page_addr >> 8) & 0xff, true);
869                 } else {
870                         /* One more address cycle for higher density devices */
871                         if (mtd->size >= 0x4000000) {
872                                 /* paddr_8 - paddr_15 */
873                                 host->devtype_data->send_addr(host,
874                                                 (page_addr >> 8) & 0xff,
875                                                 false);
876                                 host->devtype_data->send_addr(host,
877                                                 (page_addr >> 16) & 0xff,
878                                                 true);
879                         } else
880                                 /* paddr_8 - paddr_15 */
881                                 host->devtype_data->send_addr(host,
882                                                 (page_addr >> 8) & 0xff, true);
883                 }
884         }
885 }
886 
887 /*
888  * v2 and v3 type controllers can do 4bit or 8bit ecc depending
889  * on how much oob the nand chip has. For 8bit ecc we need at least
890  * 26 bytes of oob data per 512 byte block.
891  */
892 static int get_eccsize(struct mtd_info *mtd)
893 {
894         int oobbytes_per_512 = 0;
895 
896         oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
897 
898         if (oobbytes_per_512 < 26)
899                 return 4;
900         else
901                 return 8;
902 }
903 
904 static void preset_v1(struct mtd_info *mtd)
905 {
906         struct nand_chip *nand_chip = mtd->priv;
907         struct mxc_nand_host *host = nand_chip->priv;
908         uint16_t config1 = 0;
909 
910         if (nand_chip->ecc.mode == NAND_ECC_HW)
911                 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
912 
913         if (!host->devtype_data->irqpending_quirk)
914                 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
915 
916         host->eccsize = 1;
917 
918         writew(config1, NFC_V1_V2_CONFIG1);
919         /* preset operation */
920 
921         /* Unlock the internal RAM Buffer */
922         writew(0x2, NFC_V1_V2_CONFIG);
923 
924         /* Blocks to be unlocked */
925         writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
926         writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
927 
928         /* Unlock Block Command for given address range */
929         writew(0x4, NFC_V1_V2_WRPROT);
930 }
931 
932 static void preset_v2(struct mtd_info *mtd)
933 {
934         struct nand_chip *nand_chip = mtd->priv;
935         struct mxc_nand_host *host = nand_chip->priv;
936         uint16_t config1 = 0;
937 
938         if (nand_chip->ecc.mode == NAND_ECC_HW)
939                 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
940 
941         config1 |= NFC_V2_CONFIG1_FP_INT;
942 
943         if (!host->devtype_data->irqpending_quirk)
944                 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
945 
946         if (mtd->writesize) {
947                 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
948 
949                 host->eccsize = get_eccsize(mtd);
950                 if (host->eccsize == 4)
951                         config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
952 
953                 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
954         } else {
955                 host->eccsize = 1;
956         }
957 
958         writew(config1, NFC_V1_V2_CONFIG1);
959         /* preset operation */
960 
961         /* Unlock the internal RAM Buffer */
962         writew(0x2, NFC_V1_V2_CONFIG);
963 
964         /* Blocks to be unlocked */
965         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
966         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
967         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
968         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
969         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
970         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
971         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
972         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
973 
974         /* Unlock Block Command for given address range */
975         writew(0x4, NFC_V1_V2_WRPROT);
976 }
977 
978 static void preset_v3(struct mtd_info *mtd)
979 {
980         struct nand_chip *chip = mtd->priv;
981         struct mxc_nand_host *host = chip->priv;
982         uint32_t config2, config3;
983         int i, addr_phases;
984 
985         writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
986         writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
987 
988         /* Unlock the internal RAM Buffer */
989         writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
990                         NFC_V3_WRPROT);
991 
992         /* Blocks to be unlocked */
993         for (i = 0; i < NAND_MAX_CHIPS; i++)
994                 writel(0x0 |    (0xffff << 16),
995                                 NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
996 
997         writel(0, NFC_V3_IPC);
998 
999         config2 = NFC_V3_CONFIG2_ONE_CYCLE |
1000                 NFC_V3_CONFIG2_2CMD_PHASES |
1001                 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
1002                 NFC_V3_CONFIG2_ST_CMD(0x70) |
1003                 NFC_V3_CONFIG2_INT_MSK |
1004                 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
1005 
1006         if (chip->ecc.mode == NAND_ECC_HW)
1007                 config2 |= NFC_V3_CONFIG2_ECC_EN;
1008 
1009         addr_phases = fls(chip->pagemask) >> 3;
1010 
1011         if (mtd->writesize == 2048) {
1012                 config2 |= NFC_V3_CONFIG2_PS_2048;
1013                 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1014         } else if (mtd->writesize == 4096) {
1015                 config2 |= NFC_V3_CONFIG2_PS_4096;
1016                 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1017         } else {
1018                 config2 |= NFC_V3_CONFIG2_PS_512;
1019                 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
1020         }
1021 
1022         if (mtd->writesize) {
1023                 config2 |= NFC_V3_CONFIG2_PPB(
1024                                 ffs(mtd->erasesize / mtd->writesize) - 6,
1025                                 host->devtype_data->ppb_shift);
1026                 host->eccsize = get_eccsize(mtd);
1027                 if (host->eccsize == 8)
1028                         config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
1029         }
1030 
1031         writel(config2, NFC_V3_CONFIG2);
1032 
1033         config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
1034                         NFC_V3_CONFIG3_NO_SDMA |
1035                         NFC_V3_CONFIG3_RBB_MODE |
1036                         NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1037                         NFC_V3_CONFIG3_ADD_OP(0);
1038 
1039         if (!(chip->options & NAND_BUSWIDTH_16))
1040                 config3 |= NFC_V3_CONFIG3_FW8;
1041 
1042         writel(config3, NFC_V3_CONFIG3);
1043 
1044         writel(0, NFC_V3_DELAY_LINE);
1045 }
1046 
1047 /* Used by the upper layer to write command to NAND Flash for
1048  * different operations to be carried out on NAND Flash */
1049 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
1050                                 int column, int page_addr)
1051 {
1052         struct nand_chip *nand_chip = mtd->priv;
1053         struct mxc_nand_host *host = nand_chip->priv;
1054 
1055         pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1056               command, column, page_addr);
1057 
1058         /* Reset command state information */
1059         host->status_request = false;
1060 
1061         /* Command pre-processing step */
1062         switch (command) {
1063         case NAND_CMD_RESET:
1064                 host->devtype_data->preset(mtd);
1065                 host->devtype_data->send_cmd(host, command, false);
1066                 break;
1067 
1068         case NAND_CMD_STATUS:
1069                 host->buf_start = 0;
1070                 host->status_request = true;
1071 
1072                 host->devtype_data->send_cmd(host, command, true);
1073                 mxc_do_addr_cycle(mtd, column, page_addr);
1074                 break;
1075 
1076         case NAND_CMD_READ0:
1077         case NAND_CMD_READOOB:
1078                 if (command == NAND_CMD_READ0)
1079                         host->buf_start = column;
1080                 else
1081                         host->buf_start = column + mtd->writesize;
1082 
1083                 command = NAND_CMD_READ0; /* only READ0 is valid */
1084 
1085                 host->devtype_data->send_cmd(host, command, false);
1086                 mxc_do_addr_cycle(mtd, column, page_addr);
1087 
1088                 if (mtd->writesize > 512)
1089                         host->devtype_data->send_cmd(host,
1090                                         NAND_CMD_READSTART, true);
1091 
1092                 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1093 
1094                 memcpy32_fromio(host->data_buf, host->main_area0,
1095                                 mtd->writesize);
1096                 copy_spare(mtd, true);
1097                 break;
1098 
1099         case NAND_CMD_SEQIN:
1100                 if (column >= mtd->writesize)
1101                         /* call ourself to read a page */
1102                         mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
1103 
1104                 host->buf_start = column;
1105 
1106                 host->devtype_data->send_cmd(host, command, false);
1107                 mxc_do_addr_cycle(mtd, column, page_addr);
1108                 break;
1109 
1110         case NAND_CMD_PAGEPROG:
1111                 memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
1112                 copy_spare(mtd, false);
1113                 host->devtype_data->send_page(mtd, NFC_INPUT);
1114                 host->devtype_data->send_cmd(host, command, true);
1115                 mxc_do_addr_cycle(mtd, column, page_addr);
1116                 break;
1117 
1118         case NAND_CMD_READID:
1119                 host->devtype_data->send_cmd(host, command, true);
1120                 mxc_do_addr_cycle(mtd, column, page_addr);
1121                 host->devtype_data->send_read_id(host);
1122                 host->buf_start = column;
1123                 break;
1124 
1125         case NAND_CMD_ERASE1:
1126         case NAND_CMD_ERASE2:
1127                 host->devtype_data->send_cmd(host, command, false);
1128                 mxc_do_addr_cycle(mtd, column, page_addr);
1129 
1130                 break;
1131         }
1132 }
1133 
1134 /*
1135  * The generic flash bbt decriptors overlap with our ecc
1136  * hardware, so define some i.MX specific ones.
1137  */
1138 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '' };
1139 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1140 
1141 static struct nand_bbt_descr bbt_main_descr = {
1142         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1143             | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1144         .offs = 0,
1145         .len = 4,
1146         .veroffs = 4,
1147         .maxblocks = 4,
1148         .pattern = bbt_pattern,
1149 };
1150 
1151 static struct nand_bbt_descr bbt_mirror_descr = {
1152         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1153             | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1154         .offs = 0,
1155         .len = 4,
1156         .veroffs = 4,
1157         .maxblocks = 4,
1158         .pattern = mirror_pattern,
1159 };
1160 
1161 /* v1 + irqpending_quirk: i.MX21 */
1162 static const struct mxc_nand_devtype_data imx21_nand_devtype_data = {
1163         .preset = preset_v1,
1164         .send_cmd = send_cmd_v1_v2,
1165         .send_addr = send_addr_v1_v2,
1166         .send_page = send_page_v1,
1167         .send_read_id = send_read_id_v1_v2,
1168         .get_dev_status = get_dev_status_v1_v2,
1169         .check_int = check_int_v1_v2,
1170         .irq_control = irq_control_v1_v2,
1171         .get_ecc_status = get_ecc_status_v1,
1172         .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1173         .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1174         .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
1175         .select_chip = mxc_nand_select_chip_v1_v3,
1176         .correct_data = mxc_nand_correct_data_v1,
1177         .irqpending_quirk = 1,
1178         .needs_ip = 0,
1179         .regs_offset = 0xe00,
1180         .spare0_offset = 0x800,
1181         .spare_len = 16,
1182         .eccbytes = 3,
1183         .eccsize = 1,
1184 };
1185 
1186 /* v1 + !irqpending_quirk: i.MX27, i.MX31 */
1187 static const struct mxc_nand_devtype_data imx27_nand_devtype_data = {
1188         .preset = preset_v1,
1189         .send_cmd = send_cmd_v1_v2,
1190         .send_addr = send_addr_v1_v2,
1191         .send_page = send_page_v1,
1192         .send_read_id = send_read_id_v1_v2,
1193         .get_dev_status = get_dev_status_v1_v2,
1194         .check_int = check_int_v1_v2,
1195         .irq_control = irq_control_v1_v2,
1196         .get_ecc_status = get_ecc_status_v1,
1197         .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1198         .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1199         .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
1200         .select_chip = mxc_nand_select_chip_v1_v3,
1201         .correct_data = mxc_nand_correct_data_v1,
1202         .irqpending_quirk = 0,
1203         .needs_ip = 0,
1204         .regs_offset = 0xe00,
1205         .spare0_offset = 0x800,
1206         .axi_offset = 0,
1207         .spare_len = 16,
1208         .eccbytes = 3,
1209         .eccsize = 1,
1210 };
1211 
1212 /* v21: i.MX25, i.MX35 */
1213 static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
1214         .preset = preset_v2,
1215         .send_cmd = send_cmd_v1_v2,
1216         .send_addr = send_addr_v1_v2,
1217         .send_page = send_page_v2,
1218         .send_read_id = send_read_id_v1_v2,
1219         .get_dev_status = get_dev_status_v1_v2,
1220         .check_int = check_int_v1_v2,
1221         .irq_control = irq_control_v1_v2,
1222         .get_ecc_status = get_ecc_status_v2,
1223         .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1224         .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1225         .ecclayout_4k = &nandv2_hw_eccoob_4k,
1226         .select_chip = mxc_nand_select_chip_v2,
1227         .correct_data = mxc_nand_correct_data_v2_v3,
1228         .irqpending_quirk = 0,
1229         .needs_ip = 0,
1230         .regs_offset = 0x1e00,
1231         .spare0_offset = 0x1000,
1232         .axi_offset = 0,
1233         .spare_len = 64,
1234         .eccbytes = 9,
1235         .eccsize = 0,
1236 };
1237 
1238 /* v3.2a: i.MX51 */
1239 static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
1240         .preset = preset_v3,
1241         .send_cmd = send_cmd_v3,
1242         .send_addr = send_addr_v3,
1243         .send_page = send_page_v3,
1244         .send_read_id = send_read_id_v3,
1245         .get_dev_status = get_dev_status_v3,
1246         .check_int = check_int_v3,
1247         .irq_control = irq_control_v3,
1248         .get_ecc_status = get_ecc_status_v3,
1249         .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1250         .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1251         .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
1252         .select_chip = mxc_nand_select_chip_v1_v3,
1253         .correct_data = mxc_nand_correct_data_v2_v3,
1254         .irqpending_quirk = 0,
1255         .needs_ip = 1,
1256         .regs_offset = 0,
1257         .spare0_offset = 0x1000,
1258         .axi_offset = 0x1e00,
1259         .spare_len = 64,
1260         .eccbytes = 0,
1261         .eccsize = 0,
1262         .ppb_shift = 7,
1263 };
1264 
1265 /* v3.2b: i.MX53 */
1266 static const struct mxc_nand_devtype_data imx53_nand_devtype_data = {
1267         .preset = preset_v3,
1268         .send_cmd = send_cmd_v3,
1269         .send_addr = send_addr_v3,
1270         .send_page = send_page_v3,
1271         .send_read_id = send_read_id_v3,
1272         .get_dev_status = get_dev_status_v3,
1273         .check_int = check_int_v3,
1274         .irq_control = irq_control_v3,
1275         .get_ecc_status = get_ecc_status_v3,
1276         .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1277         .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1278         .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
1279         .select_chip = mxc_nand_select_chip_v1_v3,
1280         .correct_data = mxc_nand_correct_data_v2_v3,
1281         .irqpending_quirk = 0,
1282         .needs_ip = 1,
1283         .regs_offset = 0,
1284         .spare0_offset = 0x1000,
1285         .axi_offset = 0x1e00,
1286         .spare_len = 64,
1287         .eccbytes = 0,
1288         .eccsize = 0,
1289         .ppb_shift = 8,
1290 };
1291 
1292 static inline int is_imx21_nfc(struct mxc_nand_host *host)
1293 {
1294         return host->devtype_data == &imx21_nand_devtype_data;
1295 }
1296 
1297 static inline int is_imx27_nfc(struct mxc_nand_host *host)
1298 {
1299         return host->devtype_data == &imx27_nand_devtype_data;
1300 }
1301 
1302 static inline int is_imx25_nfc(struct mxc_nand_host *host)
1303 {
1304         return host->devtype_data == &imx25_nand_devtype_data;
1305 }
1306 
1307 static inline int is_imx51_nfc(struct mxc_nand_host *host)
1308 {
1309         return host->devtype_data == &imx51_nand_devtype_data;
1310 }
1311 
1312 static inline int is_imx53_nfc(struct mxc_nand_host *host)
1313 {
1314         return host->devtype_data == &imx53_nand_devtype_data;
1315 }
1316 
1317 static struct platform_device_id mxcnd_devtype[] = {
1318         {
1319                 .name = "imx21-nand",
1320                 .driver_data = (kernel_ulong_t) &imx21_nand_devtype_data,
1321         }, {
1322                 .name = "imx27-nand",
1323                 .driver_data = (kernel_ulong_t) &imx27_nand_devtype_data,
1324         }, {
1325                 .name = "imx25-nand",
1326                 .driver_data = (kernel_ulong_t) &imx25_nand_devtype_data,
1327         }, {
1328                 .name = "imx51-nand",
1329                 .driver_data = (kernel_ulong_t) &imx51_nand_devtype_data,
1330         }, {
1331                 .name = "imx53-nand",
1332                 .driver_data = (kernel_ulong_t) &imx53_nand_devtype_data,
1333         }, {
1334                 /* sentinel */
1335         }
1336 };
1337 MODULE_DEVICE_TABLE(platform, mxcnd_devtype);
1338 
1339 #ifdef CONFIG_OF_MTD
1340 static const struct of_device_id mxcnd_dt_ids[] = {
1341         {
1342                 .compatible = "fsl,imx21-nand",
1343                 .data = &imx21_nand_devtype_data,
1344         }, {
1345                 .compatible = "fsl,imx27-nand",
1346                 .data = &imx27_nand_devtype_data,
1347         }, {
1348                 .compatible = "fsl,imx25-nand",
1349                 .data = &imx25_nand_devtype_data,
1350         }, {
1351                 .compatible = "fsl,imx51-nand",
1352                 .data = &imx51_nand_devtype_data,
1353         }, {
1354                 .compatible = "fsl,imx53-nand",
1355                 .data = &imx53_nand_devtype_data,
1356         },
1357         { /* sentinel */ }
1358 };
1359 
1360 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1361 {
1362         struct device_node *np = host->dev->of_node;
1363         struct mxc_nand_platform_data *pdata = &host->pdata;
1364         const struct of_device_id *of_id =
1365                 of_match_device(mxcnd_dt_ids, host->dev);
1366         int buswidth;
1367 
1368         if (!np)
1369                 return 1;
1370 
1371         if (of_get_nand_ecc_mode(np) >= 0)
1372                 pdata->hw_ecc = 1;
1373 
1374         pdata->flash_bbt = of_get_nand_on_flash_bbt(np);
1375 
1376         buswidth = of_get_nand_bus_width(np);
1377         if (buswidth < 0)
1378                 return buswidth;
1379 
1380         pdata->width = buswidth / 8;
1381 
1382         host->devtype_data = of_id->data;
1383 
1384         return 0;
1385 }
1386 #else
1387 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1388 {
1389         return 1;
1390 }
1391 #endif
1392 
1393 static int mxcnd_probe(struct platform_device *pdev)
1394 {
1395         struct nand_chip *this;
1396         struct mtd_info *mtd;
1397         struct mxc_nand_host *host;
1398         struct resource *res;
1399         int err = 0;
1400 
1401         /* Allocate memory for MTD device structure and private data */
1402         host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host),
1403                         GFP_KERNEL);
1404         if (!host)
1405                 return -ENOMEM;
1406 
1407         /* allocate a temporary buffer for the nand_scan_ident() */
1408         host->data_buf = devm_kzalloc(&pdev->dev, PAGE_SIZE, GFP_KERNEL);
1409         if (!host->data_buf)
1410                 return -ENOMEM;
1411 
1412         host->dev = &pdev->dev;
1413         /* structures must be linked */
1414         this = &host->nand;
1415         mtd = &host->mtd;
1416         mtd->priv = this;
1417         mtd->owner = THIS_MODULE;
1418         mtd->dev.parent = &pdev->dev;
1419         mtd->name = DRIVER_NAME;
1420 
1421         /* 50 us command delay time */
1422         this->chip_delay = 5;
1423 
1424         this->priv = host;
1425         this->dev_ready = mxc_nand_dev_ready;
1426         this->cmdfunc = mxc_nand_command;
1427         this->read_byte = mxc_nand_read_byte;
1428         this->read_word = mxc_nand_read_word;
1429         this->write_buf = mxc_nand_write_buf;
1430         this->read_buf = mxc_nand_read_buf;
1431 
1432         host->clk = devm_clk_get(&pdev->dev, NULL);
1433         if (IS_ERR(host->clk))
1434                 return PTR_ERR(host->clk);
1435 
1436         err = mxcnd_probe_dt(host);
1437         if (err > 0) {
1438                 struct mxc_nand_platform_data *pdata =
1439                                         dev_get_platdata(&pdev->dev);
1440                 if (pdata) {
1441                         host->pdata = *pdata;
1442                         host->devtype_data = (struct mxc_nand_devtype_data *)
1443                                                 pdev->id_entry->driver_data;
1444                 } else {
1445                         err = -ENODEV;
1446                 }
1447         }
1448         if (err < 0)
1449                 return err;
1450 
1451         if (host->devtype_data->needs_ip) {
1452                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1453                 host->regs_ip = devm_ioremap_resource(&pdev->dev, res);
1454                 if (IS_ERR(host->regs_ip))
1455                         return PTR_ERR(host->regs_ip);
1456 
1457                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1458         } else {
1459                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1460         }
1461 
1462         host->base = devm_ioremap_resource(&pdev->dev, res);
1463         if (IS_ERR(host->base))
1464                 return PTR_ERR(host->base);
1465 
1466         host->main_area0 = host->base;
1467 
1468         if (host->devtype_data->regs_offset)
1469                 host->regs = host->base + host->devtype_data->regs_offset;
1470         host->spare0 = host->base + host->devtype_data->spare0_offset;
1471         if (host->devtype_data->axi_offset)
1472                 host->regs_axi = host->base + host->devtype_data->axi_offset;
1473 
1474         this->ecc.bytes = host->devtype_data->eccbytes;
1475         host->eccsize = host->devtype_data->eccsize;
1476 
1477         this->select_chip = host->devtype_data->select_chip;
1478         this->ecc.size = 512;
1479         this->ecc.layout = host->devtype_data->ecclayout_512;
1480 
1481         if (host->pdata.hw_ecc) {
1482                 this->ecc.calculate = mxc_nand_calculate_ecc;
1483                 this->ecc.hwctl = mxc_nand_enable_hwecc;
1484                 this->ecc.correct = host->devtype_data->correct_data;
1485                 this->ecc.mode = NAND_ECC_HW;
1486         } else {
1487                 this->ecc.mode = NAND_ECC_SOFT;
1488         }
1489 
1490         /* NAND bus width determines access functions used by upper layer */
1491         if (host->pdata.width == 2)
1492                 this->options |= NAND_BUSWIDTH_16;
1493 
1494         if (host->pdata.flash_bbt) {
1495                 this->bbt_td = &bbt_main_descr;
1496                 this->bbt_md = &bbt_mirror_descr;
1497                 /* update flash based bbt */
1498                 this->bbt_options |= NAND_BBT_USE_FLASH;
1499         }
1500 
1501         init_completion(&host->op_completion);
1502 
1503         host->irq = platform_get_irq(pdev, 0);
1504         if (host->irq < 0)
1505                 return host->irq;
1506 
1507         /*
1508          * Use host->devtype_data->irq_control() here instead of irq_control()
1509          * because we must not disable_irq_nosync without having requested the
1510          * irq.
1511          */
1512         host->devtype_data->irq_control(host, 0);
1513 
1514         err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq,
1515                         0, DRIVER_NAME, host);
1516         if (err)
1517                 return err;
1518 
1519         err = clk_prepare_enable(host->clk);
1520         if (err)
1521                 return err;
1522         host->clk_act = 1;
1523 
1524         /*
1525          * Now that we "own" the interrupt make sure the interrupt mask bit is
1526          * cleared on i.MX21. Otherwise we can't read the interrupt status bit
1527          * on this machine.
1528          */
1529         if (host->devtype_data->irqpending_quirk) {
1530                 disable_irq_nosync(host->irq);
1531                 host->devtype_data->irq_control(host, 1);
1532         }
1533 
1534         /* first scan to find the device and get the page size */
1535         if (nand_scan_ident(mtd, is_imx25_nfc(host) ? 4 : 1, NULL)) {
1536                 err = -ENXIO;
1537                 goto escan;
1538         }
1539 
1540         /* allocate the right size buffer now */
1541         devm_kfree(&pdev->dev, (void *)host->data_buf);
1542         host->data_buf = devm_kzalloc(&pdev->dev, mtd->writesize + mtd->oobsize,
1543                                         GFP_KERNEL);
1544         if (!host->data_buf) {
1545                 err = -ENOMEM;
1546                 goto escan;
1547         }
1548 
1549         /* Call preset again, with correct writesize this time */
1550         host->devtype_data->preset(mtd);
1551 
1552         if (mtd->writesize == 2048)
1553                 this->ecc.layout = host->devtype_data->ecclayout_2k;
1554         else if (mtd->writesize == 4096)
1555                 this->ecc.layout = host->devtype_data->ecclayout_4k;
1556 
1557         if (this->ecc.mode == NAND_ECC_HW) {
1558                 if (is_imx21_nfc(host) || is_imx27_nfc(host))
1559                         this->ecc.strength = 1;
1560                 else
1561                         this->ecc.strength = (host->eccsize == 4) ? 4 : 8;
1562         }
1563 
1564         /* second phase scan */
1565         if (nand_scan_tail(mtd)) {
1566                 err = -ENXIO;
1567                 goto escan;
1568         }
1569 
1570         /* Register the partitions */
1571         mtd_device_parse_register(mtd, part_probes,
1572                         &(struct mtd_part_parser_data){
1573                                 .of_node = pdev->dev.of_node,
1574                         },
1575                         host->pdata.parts,
1576                         host->pdata.nr_parts);
1577 
1578         platform_set_drvdata(pdev, host);
1579 
1580         return 0;
1581 
1582 escan:
1583         if (host->clk_act)
1584                 clk_disable_unprepare(host->clk);
1585 
1586         return err;
1587 }
1588 
1589 static int mxcnd_remove(struct platform_device *pdev)
1590 {
1591         struct mxc_nand_host *host = platform_get_drvdata(pdev);
1592 
1593         nand_release(&host->mtd);
1594         if (host->clk_act)
1595                 clk_disable_unprepare(host->clk);
1596 
1597         return 0;
1598 }
1599 
1600 static struct platform_driver mxcnd_driver = {
1601         .driver = {
1602                    .name = DRIVER_NAME,
1603                    .owner = THIS_MODULE,
1604                    .of_match_table = of_match_ptr(mxcnd_dt_ids),
1605         },
1606         .id_table = mxcnd_devtype,
1607         .probe = mxcnd_probe,
1608         .remove = mxcnd_remove,
1609 };
1610 module_platform_driver(mxcnd_driver);
1611 
1612 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1613 MODULE_DESCRIPTION("MXC NAND MTD driver");
1614 MODULE_LICENSE("GPL");
1615 

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