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Linux/drivers/mtd/nand/lpc32xx_slc.c

  1 /*
  2  * NXP LPC32XX NAND SLC driver
  3  *
  4  * Authors:
  5  *    Kevin Wells <kevin.wells@nxp.com>
  6  *    Roland Stigge <stigge@antcom.de>
  7  *
  8  * Copyright © 2011 NXP Semiconductors
  9  * Copyright © 2012 Roland Stigge
 10  *
 11  * This program is free software; you can redistribute it and/or modify
 12  * it under the terms of the GNU General Public License as published by
 13  * the Free Software Foundation; either version 2 of the License, or
 14  * (at your option) any later version.
 15  *
 16  * This program is distributed in the hope that it will be useful,
 17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 19  * GNU General Public License for more details.
 20  */
 21 
 22 #include <linux/slab.h>
 23 #include <linux/module.h>
 24 #include <linux/platform_device.h>
 25 #include <linux/mtd/mtd.h>
 26 #include <linux/mtd/nand.h>
 27 #include <linux/mtd/partitions.h>
 28 #include <linux/clk.h>
 29 #include <linux/err.h>
 30 #include <linux/delay.h>
 31 #include <linux/io.h>
 32 #include <linux/mm.h>
 33 #include <linux/dma-mapping.h>
 34 #include <linux/dmaengine.h>
 35 #include <linux/mtd/nand_ecc.h>
 36 #include <linux/gpio.h>
 37 #include <linux/of.h>
 38 #include <linux/of_gpio.h>
 39 #include <linux/mtd/lpc32xx_slc.h>
 40 
 41 #define LPC32XX_MODNAME         "lpc32xx-nand"
 42 
 43 /**********************************************************************
 44 * SLC NAND controller register offsets
 45 **********************************************************************/
 46 
 47 #define SLC_DATA(x)             (x + 0x000)
 48 #define SLC_ADDR(x)             (x + 0x004)
 49 #define SLC_CMD(x)              (x + 0x008)
 50 #define SLC_STOP(x)             (x + 0x00C)
 51 #define SLC_CTRL(x)             (x + 0x010)
 52 #define SLC_CFG(x)              (x + 0x014)
 53 #define SLC_STAT(x)             (x + 0x018)
 54 #define SLC_INT_STAT(x)         (x + 0x01C)
 55 #define SLC_IEN(x)              (x + 0x020)
 56 #define SLC_ISR(x)              (x + 0x024)
 57 #define SLC_ICR(x)              (x + 0x028)
 58 #define SLC_TAC(x)              (x + 0x02C)
 59 #define SLC_TC(x)               (x + 0x030)
 60 #define SLC_ECC(x)              (x + 0x034)
 61 #define SLC_DMA_DATA(x)         (x + 0x038)
 62 
 63 /**********************************************************************
 64 * slc_ctrl register definitions
 65 **********************************************************************/
 66 #define SLCCTRL_SW_RESET        (1 << 2) /* Reset the NAND controller bit */
 67 #define SLCCTRL_ECC_CLEAR       (1 << 1) /* Reset ECC bit */
 68 #define SLCCTRL_DMA_START       (1 << 0) /* Start DMA channel bit */
 69 
 70 /**********************************************************************
 71 * slc_cfg register definitions
 72 **********************************************************************/
 73 #define SLCCFG_CE_LOW           (1 << 5) /* Force CE low bit */
 74 #define SLCCFG_DMA_ECC          (1 << 4) /* Enable DMA ECC bit */
 75 #define SLCCFG_ECC_EN           (1 << 3) /* ECC enable bit */
 76 #define SLCCFG_DMA_BURST        (1 << 2) /* DMA burst bit */
 77 #define SLCCFG_DMA_DIR          (1 << 1) /* DMA write(0)/read(1) bit */
 78 #define SLCCFG_WIDTH            (1 << 0) /* External device width, 0=8bit */
 79 
 80 /**********************************************************************
 81 * slc_stat register definitions
 82 **********************************************************************/
 83 #define SLCSTAT_DMA_FIFO        (1 << 2) /* DMA FIFO has data bit */
 84 #define SLCSTAT_SLC_FIFO        (1 << 1) /* SLC FIFO has data bit */
 85 #define SLCSTAT_NAND_READY      (1 << 0) /* NAND device is ready bit */
 86 
 87 /**********************************************************************
 88 * slc_int_stat, slc_ien, slc_isr, and slc_icr register definitions
 89 **********************************************************************/
 90 #define SLCSTAT_INT_TC          (1 << 1) /* Transfer count bit */
 91 #define SLCSTAT_INT_RDY_EN      (1 << 0) /* Ready interrupt bit */
 92 
 93 /**********************************************************************
 94 * slc_tac register definitions
 95 **********************************************************************/
 96 /* Computation of clock cycles on basis of controller and device clock rates */
 97 #define SLCTAC_CLOCKS(c, n, s)  (min_t(u32, DIV_ROUND_UP(c, n) - 1, 0xF) << s)
 98 
 99 /* Clock setting for RDY write sample wait time in 2*n clocks */
100 #define SLCTAC_WDR(n)           (((n) & 0xF) << 28)
101 /* Write pulse width in clock cycles, 1 to 16 clocks */
102 #define SLCTAC_WWIDTH(c, n)     (SLCTAC_CLOCKS(c, n, 24))
103 /* Write hold time of control and data signals, 1 to 16 clocks */
104 #define SLCTAC_WHOLD(c, n)      (SLCTAC_CLOCKS(c, n, 20))
105 /* Write setup time of control and data signals, 1 to 16 clocks */
106 #define SLCTAC_WSETUP(c, n)     (SLCTAC_CLOCKS(c, n, 16))
107 /* Clock setting for RDY read sample wait time in 2*n clocks */
108 #define SLCTAC_RDR(n)           (((n) & 0xF) << 12)
109 /* Read pulse width in clock cycles, 1 to 16 clocks */
110 #define SLCTAC_RWIDTH(c, n)     (SLCTAC_CLOCKS(c, n, 8))
111 /* Read hold time of control and data signals, 1 to 16 clocks */
112 #define SLCTAC_RHOLD(c, n)      (SLCTAC_CLOCKS(c, n, 4))
113 /* Read setup time of control and data signals, 1 to 16 clocks */
114 #define SLCTAC_RSETUP(c, n)     (SLCTAC_CLOCKS(c, n, 0))
115 
116 /**********************************************************************
117 * slc_ecc register definitions
118 **********************************************************************/
119 /* ECC line party fetch macro */
120 #define SLCECC_TO_LINEPAR(n)    (((n) >> 6) & 0x7FFF)
121 #define SLCECC_TO_COLPAR(n)     ((n) & 0x3F)
122 
123 /*
124  * DMA requires storage space for the DMA local buffer and the hardware ECC
125  * storage area. The DMA local buffer is only used if DMA mapping fails
126  * during runtime.
127  */
128 #define LPC32XX_DMA_DATA_SIZE           4096
129 #define LPC32XX_ECC_SAVE_SIZE           ((4096 / 256) * 4)
130 
131 /* Number of bytes used for ECC stored in NAND per 256 bytes */
132 #define LPC32XX_SLC_DEV_ECC_BYTES       3
133 
134 /*
135  * If the NAND base clock frequency can't be fetched, this frequency will be
136  * used instead as the base. This rate is used to setup the timing registers
137  * used for NAND accesses.
138  */
139 #define LPC32XX_DEF_BUS_RATE            133250000
140 
141 /* Milliseconds for DMA FIFO timeout (unlikely anyway) */
142 #define LPC32XX_DMA_TIMEOUT             100
143 
144 /*
145  * NAND ECC Layout for small page NAND devices
146  * Note: For large and huge page devices, the default layouts are used
147  */
148 static int lpc32xx_ooblayout_ecc(struct mtd_info *mtd, int section,
149                                  struct mtd_oob_region *oobregion)
150 {
151         if (section)
152                 return -ERANGE;
153 
154         oobregion->length = 6;
155         oobregion->offset = 10;
156 
157         return 0;
158 }
159 
160 static int lpc32xx_ooblayout_free(struct mtd_info *mtd, int section,
161                                   struct mtd_oob_region *oobregion)
162 {
163         if (section > 1)
164                 return -ERANGE;
165 
166         if (!section) {
167                 oobregion->offset = 0;
168                 oobregion->length = 4;
169         } else {
170                 oobregion->offset = 6;
171                 oobregion->length = 4;
172         }
173 
174         return 0;
175 }
176 
177 static const struct mtd_ooblayout_ops lpc32xx_ooblayout_ops = {
178         .ecc = lpc32xx_ooblayout_ecc,
179         .free = lpc32xx_ooblayout_free,
180 };
181 
182 static u8 bbt_pattern[] = {'B', 'b', 't', '' };
183 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
184 
185 /*
186  * Small page FLASH BBT descriptors, marker at offset 0, version at offset 6
187  * Note: Large page devices used the default layout
188  */
189 static struct nand_bbt_descr bbt_smallpage_main_descr = {
190         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
191                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
192         .offs = 0,
193         .len = 4,
194         .veroffs = 6,
195         .maxblocks = 4,
196         .pattern = bbt_pattern
197 };
198 
199 static struct nand_bbt_descr bbt_smallpage_mirror_descr = {
200         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
201                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
202         .offs = 0,
203         .len = 4,
204         .veroffs = 6,
205         .maxblocks = 4,
206         .pattern = mirror_pattern
207 };
208 
209 /*
210  * NAND platform configuration structure
211  */
212 struct lpc32xx_nand_cfg_slc {
213         uint32_t wdr_clks;
214         uint32_t wwidth;
215         uint32_t whold;
216         uint32_t wsetup;
217         uint32_t rdr_clks;
218         uint32_t rwidth;
219         uint32_t rhold;
220         uint32_t rsetup;
221         int wp_gpio;
222         struct mtd_partition *parts;
223         unsigned num_parts;
224 };
225 
226 struct lpc32xx_nand_host {
227         struct nand_chip        nand_chip;
228         struct lpc32xx_slc_platform_data *pdata;
229         struct clk              *clk;
230         void __iomem            *io_base;
231         struct lpc32xx_nand_cfg_slc *ncfg;
232 
233         struct completion       comp;
234         struct dma_chan         *dma_chan;
235         uint32_t                dma_buf_len;
236         struct dma_slave_config dma_slave_config;
237         struct scatterlist      sgl;
238 
239         /*
240          * DMA and CPU addresses of ECC work area and data buffer
241          */
242         uint32_t                *ecc_buf;
243         uint8_t                 *data_buf;
244         dma_addr_t              io_base_dma;
245 };
246 
247 static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host)
248 {
249         uint32_t clkrate, tmp;
250 
251         /* Reset SLC controller */
252         writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base));
253         udelay(1000);
254 
255         /* Basic setup */
256         writel(0, SLC_CFG(host->io_base));
257         writel(0, SLC_IEN(host->io_base));
258         writel((SLCSTAT_INT_TC | SLCSTAT_INT_RDY_EN),
259                 SLC_ICR(host->io_base));
260 
261         /* Get base clock for SLC block */
262         clkrate = clk_get_rate(host->clk);
263         if (clkrate == 0)
264                 clkrate = LPC32XX_DEF_BUS_RATE;
265 
266         /* Compute clock setup values */
267         tmp = SLCTAC_WDR(host->ncfg->wdr_clks) |
268                 SLCTAC_WWIDTH(clkrate, host->ncfg->wwidth) |
269                 SLCTAC_WHOLD(clkrate, host->ncfg->whold) |
270                 SLCTAC_WSETUP(clkrate, host->ncfg->wsetup) |
271                 SLCTAC_RDR(host->ncfg->rdr_clks) |
272                 SLCTAC_RWIDTH(clkrate, host->ncfg->rwidth) |
273                 SLCTAC_RHOLD(clkrate, host->ncfg->rhold) |
274                 SLCTAC_RSETUP(clkrate, host->ncfg->rsetup);
275         writel(tmp, SLC_TAC(host->io_base));
276 }
277 
278 /*
279  * Hardware specific access to control lines
280  */
281 static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
282         unsigned int ctrl)
283 {
284         uint32_t tmp;
285         struct nand_chip *chip = mtd_to_nand(mtd);
286         struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
287 
288         /* Does CE state need to be changed? */
289         tmp = readl(SLC_CFG(host->io_base));
290         if (ctrl & NAND_NCE)
291                 tmp |= SLCCFG_CE_LOW;
292         else
293                 tmp &= ~SLCCFG_CE_LOW;
294         writel(tmp, SLC_CFG(host->io_base));
295 
296         if (cmd != NAND_CMD_NONE) {
297                 if (ctrl & NAND_CLE)
298                         writel(cmd, SLC_CMD(host->io_base));
299                 else
300                         writel(cmd, SLC_ADDR(host->io_base));
301         }
302 }
303 
304 /*
305  * Read the Device Ready pin
306  */
307 static int lpc32xx_nand_device_ready(struct mtd_info *mtd)
308 {
309         struct nand_chip *chip = mtd_to_nand(mtd);
310         struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
311         int rdy = 0;
312 
313         if ((readl(SLC_STAT(host->io_base)) & SLCSTAT_NAND_READY) != 0)
314                 rdy = 1;
315 
316         return rdy;
317 }
318 
319 /*
320  * Enable NAND write protect
321  */
322 static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host)
323 {
324         if (gpio_is_valid(host->ncfg->wp_gpio))
325                 gpio_set_value(host->ncfg->wp_gpio, 0);
326 }
327 
328 /*
329  * Disable NAND write protect
330  */
331 static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host)
332 {
333         if (gpio_is_valid(host->ncfg->wp_gpio))
334                 gpio_set_value(host->ncfg->wp_gpio, 1);
335 }
336 
337 /*
338  * Prepares SLC for transfers with H/W ECC enabled
339  */
340 static void lpc32xx_nand_ecc_enable(struct mtd_info *mtd, int mode)
341 {
342         /* Hardware ECC is enabled automatically in hardware as needed */
343 }
344 
345 /*
346  * Calculates the ECC for the data
347  */
348 static int lpc32xx_nand_ecc_calculate(struct mtd_info *mtd,
349                                       const unsigned char *buf,
350                                       unsigned char *code)
351 {
352         /*
353          * ECC is calculated automatically in hardware during syndrome read
354          * and write operations, so it doesn't need to be calculated here.
355          */
356         return 0;
357 }
358 
359 /*
360  * Read a single byte from NAND device
361  */
362 static uint8_t lpc32xx_nand_read_byte(struct mtd_info *mtd)
363 {
364         struct nand_chip *chip = mtd_to_nand(mtd);
365         struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
366 
367         return (uint8_t)readl(SLC_DATA(host->io_base));
368 }
369 
370 /*
371  * Simple device read without ECC
372  */
373 static void lpc32xx_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
374 {
375         struct nand_chip *chip = mtd_to_nand(mtd);
376         struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
377 
378         /* Direct device read with no ECC */
379         while (len-- > 0)
380                 *buf++ = (uint8_t)readl(SLC_DATA(host->io_base));
381 }
382 
383 /*
384  * Simple device write without ECC
385  */
386 static void lpc32xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
387 {
388         struct nand_chip *chip = mtd_to_nand(mtd);
389         struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
390 
391         /* Direct device write with no ECC */
392         while (len-- > 0)
393                 writel((uint32_t)*buf++, SLC_DATA(host->io_base));
394 }
395 
396 /*
397  * Read the OOB data from the device without ECC using FIFO method
398  */
399 static int lpc32xx_nand_read_oob_syndrome(struct mtd_info *mtd,
400                                           struct nand_chip *chip, int page)
401 {
402         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
403         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
404 
405         return 0;
406 }
407 
408 /*
409  * Write the OOB data to the device without ECC using FIFO method
410  */
411 static int lpc32xx_nand_write_oob_syndrome(struct mtd_info *mtd,
412         struct nand_chip *chip, int page)
413 {
414         int status;
415 
416         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
417         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
418 
419         /* Send command to program the OOB data */
420         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
421 
422         status = chip->waitfunc(mtd, chip);
423 
424         return status & NAND_STATUS_FAIL ? -EIO : 0;
425 }
426 
427 /*
428  * Fills in the ECC fields in the OOB buffer with the hardware generated ECC
429  */
430 static void lpc32xx_slc_ecc_copy(uint8_t *spare, const uint32_t *ecc, int count)
431 {
432         int i;
433 
434         for (i = 0; i < (count * 3); i += 3) {
435                 uint32_t ce = ecc[i / 3];
436                 ce = ~(ce << 2) & 0xFFFFFF;
437                 spare[i + 2] = (uint8_t)(ce & 0xFF);
438                 ce >>= 8;
439                 spare[i + 1] = (uint8_t)(ce & 0xFF);
440                 ce >>= 8;
441                 spare[i] = (uint8_t)(ce & 0xFF);
442         }
443 }
444 
445 static void lpc32xx_dma_complete_func(void *completion)
446 {
447         complete(completion);
448 }
449 
450 static int lpc32xx_xmit_dma(struct mtd_info *mtd, dma_addr_t dma,
451                             void *mem, int len, enum dma_transfer_direction dir)
452 {
453         struct nand_chip *chip = mtd_to_nand(mtd);
454         struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
455         struct dma_async_tx_descriptor *desc;
456         int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
457         int res;
458 
459         host->dma_slave_config.direction = dir;
460         host->dma_slave_config.src_addr = dma;
461         host->dma_slave_config.dst_addr = dma;
462         host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
463         host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
464         host->dma_slave_config.src_maxburst = 4;
465         host->dma_slave_config.dst_maxburst = 4;
466         /* DMA controller does flow control: */
467         host->dma_slave_config.device_fc = false;
468         if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) {
469                 dev_err(mtd->dev.parent, "Failed to setup DMA slave\n");
470                 return -ENXIO;
471         }
472 
473         sg_init_one(&host->sgl, mem, len);
474 
475         res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1,
476                          DMA_BIDIRECTIONAL);
477         if (res != 1) {
478                 dev_err(mtd->dev.parent, "Failed to map sg list\n");
479                 return -ENXIO;
480         }
481         desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir,
482                                        flags);
483         if (!desc) {
484                 dev_err(mtd->dev.parent, "Failed to prepare slave sg\n");
485                 goto out1;
486         }
487 
488         init_completion(&host->comp);
489         desc->callback = lpc32xx_dma_complete_func;
490         desc->callback_param = &host->comp;
491 
492         dmaengine_submit(desc);
493         dma_async_issue_pending(host->dma_chan);
494 
495         wait_for_completion_timeout(&host->comp, msecs_to_jiffies(1000));
496 
497         dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
498                      DMA_BIDIRECTIONAL);
499 
500         return 0;
501 out1:
502         dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
503                      DMA_BIDIRECTIONAL);
504         return -ENXIO;
505 }
506 
507 /*
508  * DMA read/write transfers with ECC support
509  */
510 static int lpc32xx_xfer(struct mtd_info *mtd, uint8_t *buf, int eccsubpages,
511                         int read)
512 {
513         struct nand_chip *chip = mtd_to_nand(mtd);
514         struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
515         int i, status = 0;
516         unsigned long timeout;
517         int res;
518         enum dma_transfer_direction dir =
519                 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
520         uint8_t *dma_buf;
521         bool dma_mapped;
522 
523         if ((void *)buf <= high_memory) {
524                 dma_buf = buf;
525                 dma_mapped = true;
526         } else {
527                 dma_buf = host->data_buf;
528                 dma_mapped = false;
529                 if (!read)
530                         memcpy(host->data_buf, buf, mtd->writesize);
531         }
532 
533         if (read) {
534                 writel(readl(SLC_CFG(host->io_base)) |
535                        SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC |
536                        SLCCFG_DMA_BURST, SLC_CFG(host->io_base));
537         } else {
538                 writel((readl(SLC_CFG(host->io_base)) |
539                         SLCCFG_ECC_EN | SLCCFG_DMA_ECC | SLCCFG_DMA_BURST) &
540                        ~SLCCFG_DMA_DIR,
541                         SLC_CFG(host->io_base));
542         }
543 
544         /* Clear initial ECC */
545         writel(SLCCTRL_ECC_CLEAR, SLC_CTRL(host->io_base));
546 
547         /* Transfer size is data area only */
548         writel(mtd->writesize, SLC_TC(host->io_base));
549 
550         /* Start transfer in the NAND controller */
551         writel(readl(SLC_CTRL(host->io_base)) | SLCCTRL_DMA_START,
552                SLC_CTRL(host->io_base));
553 
554         for (i = 0; i < chip->ecc.steps; i++) {
555                 /* Data */
556                 res = lpc32xx_xmit_dma(mtd, SLC_DMA_DATA(host->io_base_dma),
557                                        dma_buf + i * chip->ecc.size,
558                                        mtd->writesize / chip->ecc.steps, dir);
559                 if (res)
560                         return res;
561 
562                 /* Always _read_ ECC */
563                 if (i == chip->ecc.steps - 1)
564                         break;
565                 if (!read) /* ECC availability delayed on write */
566                         udelay(10);
567                 res = lpc32xx_xmit_dma(mtd, SLC_ECC(host->io_base_dma),
568                                        &host->ecc_buf[i], 4, DMA_DEV_TO_MEM);
569                 if (res)
570                         return res;
571         }
572 
573         /*
574          * According to NXP, the DMA can be finished here, but the NAND
575          * controller may still have buffered data. After porting to using the
576          * dmaengine DMA driver (amba-pl080), the condition (DMA_FIFO empty)
577          * appears to be always true, according to tests. Keeping the check for
578          * safety reasons for now.
579          */
580         if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) {
581                 dev_warn(mtd->dev.parent, "FIFO not empty!\n");
582                 timeout = jiffies + msecs_to_jiffies(LPC32XX_DMA_TIMEOUT);
583                 while ((readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) &&
584                        time_before(jiffies, timeout))
585                         cpu_relax();
586                 if (!time_before(jiffies, timeout)) {
587                         dev_err(mtd->dev.parent, "FIFO held data too long\n");
588                         status = -EIO;
589                 }
590         }
591 
592         /* Read last calculated ECC value */
593         if (!read)
594                 udelay(10);
595         host->ecc_buf[chip->ecc.steps - 1] =
596                 readl(SLC_ECC(host->io_base));
597 
598         /* Flush DMA */
599         dmaengine_terminate_all(host->dma_chan);
600 
601         if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO ||
602             readl(SLC_TC(host->io_base))) {
603                 /* Something is left in the FIFO, something is wrong */
604                 dev_err(mtd->dev.parent, "DMA FIFO failure\n");
605                 status = -EIO;
606         }
607 
608         /* Stop DMA & HW ECC */
609         writel(readl(SLC_CTRL(host->io_base)) & ~SLCCTRL_DMA_START,
610                SLC_CTRL(host->io_base));
611         writel(readl(SLC_CFG(host->io_base)) &
612                ~(SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC |
613                  SLCCFG_DMA_BURST), SLC_CFG(host->io_base));
614 
615         if (!dma_mapped && read)
616                 memcpy(buf, host->data_buf, mtd->writesize);
617 
618         return status;
619 }
620 
621 /*
622  * Read the data and OOB data from the device, use ECC correction with the
623  * data, disable ECC for the OOB data
624  */
625 static int lpc32xx_nand_read_page_syndrome(struct mtd_info *mtd,
626                                            struct nand_chip *chip, uint8_t *buf,
627                                            int oob_required, int page)
628 {
629         struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
630         struct mtd_oob_region oobregion = { };
631         int stat, i, status, error;
632         uint8_t *oobecc, tmpecc[LPC32XX_ECC_SAVE_SIZE];
633 
634         /* Issue read command */
635         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
636 
637         /* Read data and oob, calculate ECC */
638         status = lpc32xx_xfer(mtd, buf, chip->ecc.steps, 1);
639 
640         /* Get OOB data */
641         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
642 
643         /* Convert to stored ECC format */
644         lpc32xx_slc_ecc_copy(tmpecc, (uint32_t *) host->ecc_buf, chip->ecc.steps);
645 
646         /* Pointer to ECC data retrieved from NAND spare area */
647         error = mtd_ooblayout_ecc(mtd, 0, &oobregion);
648         if (error)
649                 return error;
650 
651         oobecc = chip->oob_poi + oobregion.offset;
652 
653         for (i = 0; i < chip->ecc.steps; i++) {
654                 stat = chip->ecc.correct(mtd, buf, oobecc,
655                                          &tmpecc[i * chip->ecc.bytes]);
656                 if (stat < 0)
657                         mtd->ecc_stats.failed++;
658                 else
659                         mtd->ecc_stats.corrected += stat;
660 
661                 buf += chip->ecc.size;
662                 oobecc += chip->ecc.bytes;
663         }
664 
665         return status;
666 }
667 
668 /*
669  * Read the data and OOB data from the device, no ECC correction with the
670  * data or OOB data
671  */
672 static int lpc32xx_nand_read_page_raw_syndrome(struct mtd_info *mtd,
673                                                struct nand_chip *chip,
674                                                uint8_t *buf, int oob_required,
675                                                int page)
676 {
677         /* Issue read command */
678         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
679 
680         /* Raw reads can just use the FIFO interface */
681         chip->read_buf(mtd, buf, chip->ecc.size * chip->ecc.steps);
682         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
683 
684         return 0;
685 }
686 
687 /*
688  * Write the data and OOB data to the device, use ECC with the data,
689  * disable ECC for the OOB data
690  */
691 static int lpc32xx_nand_write_page_syndrome(struct mtd_info *mtd,
692                                             struct nand_chip *chip,
693                                             const uint8_t *buf,
694                                             int oob_required, int page)
695 {
696         struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
697         struct mtd_oob_region oobregion = { };
698         uint8_t *pb;
699         int error;
700 
701         /* Write data, calculate ECC on outbound data */
702         error = lpc32xx_xfer(mtd, (uint8_t *)buf, chip->ecc.steps, 0);
703         if (error)
704                 return error;
705 
706         /*
707          * The calculated ECC needs some manual work done to it before
708          * committing it to NAND. Process the calculated ECC and place
709          * the resultant values directly into the OOB buffer. */
710         error = mtd_ooblayout_ecc(mtd, 0, &oobregion);
711         if (error)
712                 return error;
713 
714         pb = chip->oob_poi + oobregion.offset;
715         lpc32xx_slc_ecc_copy(pb, (uint32_t *)host->ecc_buf, chip->ecc.steps);
716 
717         /* Write ECC data to device */
718         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
719         return 0;
720 }
721 
722 /*
723  * Write the data and OOB data to the device, no ECC correction with the
724  * data or OOB data
725  */
726 static int lpc32xx_nand_write_page_raw_syndrome(struct mtd_info *mtd,
727                                                 struct nand_chip *chip,
728                                                 const uint8_t *buf,
729                                                 int oob_required, int page)
730 {
731         /* Raw writes can just use the FIFO interface */
732         chip->write_buf(mtd, buf, chip->ecc.size * chip->ecc.steps);
733         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
734         return 0;
735 }
736 
737 static int lpc32xx_nand_dma_setup(struct lpc32xx_nand_host *host)
738 {
739         struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
740         dma_cap_mask_t mask;
741 
742         if (!host->pdata || !host->pdata->dma_filter) {
743                 dev_err(mtd->dev.parent, "no DMA platform data\n");
744                 return -ENOENT;
745         }
746 
747         dma_cap_zero(mask);
748         dma_cap_set(DMA_SLAVE, mask);
749         host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter,
750                                              "nand-slc");
751         if (!host->dma_chan) {
752                 dev_err(mtd->dev.parent, "Failed to request DMA channel\n");
753                 return -EBUSY;
754         }
755 
756         return 0;
757 }
758 
759 static struct lpc32xx_nand_cfg_slc *lpc32xx_parse_dt(struct device *dev)
760 {
761         struct lpc32xx_nand_cfg_slc *ncfg;
762         struct device_node *np = dev->of_node;
763 
764         ncfg = devm_kzalloc(dev, sizeof(*ncfg), GFP_KERNEL);
765         if (!ncfg)
766                 return NULL;
767 
768         of_property_read_u32(np, "nxp,wdr-clks", &ncfg->wdr_clks);
769         of_property_read_u32(np, "nxp,wwidth", &ncfg->wwidth);
770         of_property_read_u32(np, "nxp,whold", &ncfg->whold);
771         of_property_read_u32(np, "nxp,wsetup", &ncfg->wsetup);
772         of_property_read_u32(np, "nxp,rdr-clks", &ncfg->rdr_clks);
773         of_property_read_u32(np, "nxp,rwidth", &ncfg->rwidth);
774         of_property_read_u32(np, "nxp,rhold", &ncfg->rhold);
775         of_property_read_u32(np, "nxp,rsetup", &ncfg->rsetup);
776 
777         if (!ncfg->wdr_clks || !ncfg->wwidth || !ncfg->whold ||
778             !ncfg->wsetup || !ncfg->rdr_clks || !ncfg->rwidth ||
779             !ncfg->rhold || !ncfg->rsetup) {
780                 dev_err(dev, "chip parameters not specified correctly\n");
781                 return NULL;
782         }
783 
784         ncfg->wp_gpio = of_get_named_gpio(np, "gpios", 0);
785 
786         return ncfg;
787 }
788 
789 /*
790  * Probe for NAND controller
791  */
792 static int lpc32xx_nand_probe(struct platform_device *pdev)
793 {
794         struct lpc32xx_nand_host *host;
795         struct mtd_info *mtd;
796         struct nand_chip *chip;
797         struct resource *rc;
798         int res;
799 
800         rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
801         if (rc == NULL) {
802                 dev_err(&pdev->dev, "No memory resource found for device\n");
803                 return -EBUSY;
804         }
805 
806         /* Allocate memory for the device structure (and zero it) */
807         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
808         if (!host)
809                 return -ENOMEM;
810         host->io_base_dma = rc->start;
811 
812         host->io_base = devm_ioremap_resource(&pdev->dev, rc);
813         if (IS_ERR(host->io_base))
814                 return PTR_ERR(host->io_base);
815 
816         if (pdev->dev.of_node)
817                 host->ncfg = lpc32xx_parse_dt(&pdev->dev);
818         if (!host->ncfg) {
819                 dev_err(&pdev->dev,
820                         "Missing or bad NAND config from device tree\n");
821                 return -ENOENT;
822         }
823         if (host->ncfg->wp_gpio == -EPROBE_DEFER)
824                 return -EPROBE_DEFER;
825         if (gpio_is_valid(host->ncfg->wp_gpio) && devm_gpio_request(&pdev->dev,
826                         host->ncfg->wp_gpio, "NAND WP")) {
827                 dev_err(&pdev->dev, "GPIO not available\n");
828                 return -EBUSY;
829         }
830         lpc32xx_wp_disable(host);
831 
832         host->pdata = dev_get_platdata(&pdev->dev);
833 
834         chip = &host->nand_chip;
835         mtd = nand_to_mtd(chip);
836         nand_set_controller_data(chip, host);
837         nand_set_flash_node(chip, pdev->dev.of_node);
838         mtd->owner = THIS_MODULE;
839         mtd->dev.parent = &pdev->dev;
840 
841         /* Get NAND clock */
842         host->clk = devm_clk_get(&pdev->dev, NULL);
843         if (IS_ERR(host->clk)) {
844                 dev_err(&pdev->dev, "Clock failure\n");
845                 res = -ENOENT;
846                 goto err_exit1;
847         }
848         clk_prepare_enable(host->clk);
849 
850         /* Set NAND IO addresses and command/ready functions */
851         chip->IO_ADDR_R = SLC_DATA(host->io_base);
852         chip->IO_ADDR_W = SLC_DATA(host->io_base);
853         chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl;
854         chip->dev_ready = lpc32xx_nand_device_ready;
855         chip->chip_delay = 20; /* 20us command delay time */
856 
857         /* Init NAND controller */
858         lpc32xx_nand_setup(host);
859 
860         platform_set_drvdata(pdev, host);
861 
862         /* NAND callbacks for LPC32xx SLC hardware */
863         chip->ecc.mode = NAND_ECC_HW_SYNDROME;
864         chip->read_byte = lpc32xx_nand_read_byte;
865         chip->read_buf = lpc32xx_nand_read_buf;
866         chip->write_buf = lpc32xx_nand_write_buf;
867         chip->ecc.read_page_raw = lpc32xx_nand_read_page_raw_syndrome;
868         chip->ecc.read_page = lpc32xx_nand_read_page_syndrome;
869         chip->ecc.write_page_raw = lpc32xx_nand_write_page_raw_syndrome;
870         chip->ecc.write_page = lpc32xx_nand_write_page_syndrome;
871         chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome;
872         chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome;
873         chip->ecc.calculate = lpc32xx_nand_ecc_calculate;
874         chip->ecc.correct = nand_correct_data;
875         chip->ecc.strength = 1;
876         chip->ecc.hwctl = lpc32xx_nand_ecc_enable;
877 
878         /*
879          * Allocate a large enough buffer for a single huge page plus
880          * extra space for the spare area and ECC storage area
881          */
882         host->dma_buf_len = LPC32XX_DMA_DATA_SIZE + LPC32XX_ECC_SAVE_SIZE;
883         host->data_buf = devm_kzalloc(&pdev->dev, host->dma_buf_len,
884                                       GFP_KERNEL);
885         if (host->data_buf == NULL) {
886                 res = -ENOMEM;
887                 goto err_exit2;
888         }
889 
890         res = lpc32xx_nand_dma_setup(host);
891         if (res) {
892                 res = -EIO;
893                 goto err_exit2;
894         }
895 
896         /* Find NAND device */
897         if (nand_scan_ident(mtd, 1, NULL)) {
898                 res = -ENXIO;
899                 goto err_exit3;
900         }
901 
902         /* OOB and ECC CPU and DMA work areas */
903         host->ecc_buf = (uint32_t *)(host->data_buf + LPC32XX_DMA_DATA_SIZE);
904 
905         /*
906          * Small page FLASH has a unique OOB layout, but large and huge
907          * page FLASH use the standard layout. Small page FLASH uses a
908          * custom BBT marker layout.
909          */
910         if (mtd->writesize <= 512)
911                 mtd_set_ooblayout(mtd, &lpc32xx_ooblayout_ops);
912 
913         /* These sizes remain the same regardless of page size */
914         chip->ecc.size = 256;
915         chip->ecc.bytes = LPC32XX_SLC_DEV_ECC_BYTES;
916         chip->ecc.prepad = chip->ecc.postpad = 0;
917 
918         /*
919          * Use a custom BBT marker setup for small page FLASH that
920          * won't interfere with the ECC layout. Large and huge page
921          * FLASH use the standard layout.
922          */
923         if ((chip->bbt_options & NAND_BBT_USE_FLASH) &&
924             mtd->writesize <= 512) {
925                 chip->bbt_td = &bbt_smallpage_main_descr;
926                 chip->bbt_md = &bbt_smallpage_mirror_descr;
927         }
928 
929         /*
930          * Fills out all the uninitialized function pointers with the defaults
931          */
932         if (nand_scan_tail(mtd)) {
933                 res = -ENXIO;
934                 goto err_exit3;
935         }
936 
937         mtd->name = "nxp_lpc3220_slc";
938         res = mtd_device_register(mtd, host->ncfg->parts,
939                                   host->ncfg->num_parts);
940         if (!res)
941                 return res;
942 
943         nand_release(mtd);
944 
945 err_exit3:
946         dma_release_channel(host->dma_chan);
947 err_exit2:
948         clk_disable_unprepare(host->clk);
949 err_exit1:
950         lpc32xx_wp_enable(host);
951 
952         return res;
953 }
954 
955 /*
956  * Remove NAND device.
957  */
958 static int lpc32xx_nand_remove(struct platform_device *pdev)
959 {
960         uint32_t tmp;
961         struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
962         struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
963 
964         nand_release(mtd);
965         dma_release_channel(host->dma_chan);
966 
967         /* Force CE high */
968         tmp = readl(SLC_CTRL(host->io_base));
969         tmp &= ~SLCCFG_CE_LOW;
970         writel(tmp, SLC_CTRL(host->io_base));
971 
972         clk_disable_unprepare(host->clk);
973         lpc32xx_wp_enable(host);
974 
975         return 0;
976 }
977 
978 #ifdef CONFIG_PM
979 static int lpc32xx_nand_resume(struct platform_device *pdev)
980 {
981         struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
982 
983         /* Re-enable NAND clock */
984         clk_prepare_enable(host->clk);
985 
986         /* Fresh init of NAND controller */
987         lpc32xx_nand_setup(host);
988 
989         /* Disable write protect */
990         lpc32xx_wp_disable(host);
991 
992         return 0;
993 }
994 
995 static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm)
996 {
997         uint32_t tmp;
998         struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
999 
1000         /* Force CE high */
1001         tmp = readl(SLC_CTRL(host->io_base));
1002         tmp &= ~SLCCFG_CE_LOW;
1003         writel(tmp, SLC_CTRL(host->io_base));
1004 
1005         /* Enable write protect for safety */
1006         lpc32xx_wp_enable(host);
1007 
1008         /* Disable clock */
1009         clk_disable_unprepare(host->clk);
1010 
1011         return 0;
1012 }
1013 
1014 #else
1015 #define lpc32xx_nand_resume NULL
1016 #define lpc32xx_nand_suspend NULL
1017 #endif
1018 
1019 static const struct of_device_id lpc32xx_nand_match[] = {
1020         { .compatible = "nxp,lpc3220-slc" },
1021         { /* sentinel */ },
1022 };
1023 MODULE_DEVICE_TABLE(of, lpc32xx_nand_match);
1024 
1025 static struct platform_driver lpc32xx_nand_driver = {
1026         .probe          = lpc32xx_nand_probe,
1027         .remove         = lpc32xx_nand_remove,
1028         .resume         = lpc32xx_nand_resume,
1029         .suspend        = lpc32xx_nand_suspend,
1030         .driver         = {
1031                 .name   = LPC32XX_MODNAME,
1032                 .of_match_table = lpc32xx_nand_match,
1033         },
1034 };
1035 
1036 module_platform_driver(lpc32xx_nand_driver);
1037 
1038 MODULE_LICENSE("GPL");
1039 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
1040 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
1041 MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX SLC controller");
1042 

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