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Linux/drivers/mtd/nand/gpio.c

  1 /*
  2  * drivers/mtd/nand/gpio.c
  3  *
  4  * Updated, and converted to generic GPIO based driver by Russell King.
  5  *
  6  * Written by Ben Dooks <ben@simtec.co.uk>
  7  *   Based on 2.4 version by Mark Whittaker
  8  *
  9  * © 2004 Simtec Electronics
 10  *
 11  * Device driver for NAND connected via GPIO
 12  *
 13  * This program is free software; you can redistribute it and/or modify
 14  * it under the terms of the GNU General Public License version 2 as
 15  * published by the Free Software Foundation.
 16  *
 17  */
 18 
 19 #include <linux/kernel.h>
 20 #include <linux/err.h>
 21 #include <linux/slab.h>
 22 #include <linux/module.h>
 23 #include <linux/platform_device.h>
 24 #include <linux/gpio.h>
 25 #include <linux/io.h>
 26 #include <linux/mtd/mtd.h>
 27 #include <linux/mtd/nand.h>
 28 #include <linux/mtd/partitions.h>
 29 #include <linux/mtd/nand-gpio.h>
 30 #include <linux/of.h>
 31 #include <linux/of_address.h>
 32 #include <linux/of_gpio.h>
 33 
 34 struct gpiomtd {
 35         void __iomem            *io_sync;
 36         struct mtd_info         mtd_info;
 37         struct nand_chip        nand_chip;
 38         struct gpio_nand_platdata plat;
 39 };
 40 
 41 #define gpio_nand_getpriv(x) container_of(x, struct gpiomtd, mtd_info)
 42 
 43 
 44 #ifdef CONFIG_ARM
 45 /* gpio_nand_dosync()
 46  *
 47  * Make sure the GPIO state changes occur in-order with writes to NAND
 48  * memory region.
 49  * Needed on PXA due to bus-reordering within the SoC itself (see section on
 50  * I/O ordering in PXA manual (section 2.3, p35)
 51  */
 52 static void gpio_nand_dosync(struct gpiomtd *gpiomtd)
 53 {
 54         unsigned long tmp;
 55 
 56         if (gpiomtd->io_sync) {
 57                 /*
 58                  * Linux memory barriers don't cater for what's required here.
 59                  * What's required is what's here - a read from a separate
 60                  * region with a dependency on that read.
 61                  */
 62                 tmp = readl(gpiomtd->io_sync);
 63                 asm volatile("mov %1, %0\n" : "=r" (tmp) : "r" (tmp));
 64         }
 65 }
 66 #else
 67 static inline void gpio_nand_dosync(struct gpiomtd *gpiomtd) {}
 68 #endif
 69 
 70 static void gpio_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 71 {
 72         struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);
 73 
 74         gpio_nand_dosync(gpiomtd);
 75 
 76         if (ctrl & NAND_CTRL_CHANGE) {
 77                 gpio_set_value(gpiomtd->plat.gpio_nce, !(ctrl & NAND_NCE));
 78                 gpio_set_value(gpiomtd->plat.gpio_cle, !!(ctrl & NAND_CLE));
 79                 gpio_set_value(gpiomtd->plat.gpio_ale, !!(ctrl & NAND_ALE));
 80                 gpio_nand_dosync(gpiomtd);
 81         }
 82         if (cmd == NAND_CMD_NONE)
 83                 return;
 84 
 85         writeb(cmd, gpiomtd->nand_chip.IO_ADDR_W);
 86         gpio_nand_dosync(gpiomtd);
 87 }
 88 
 89 static int gpio_nand_devready(struct mtd_info *mtd)
 90 {
 91         struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);
 92 
 93         return gpio_get_value(gpiomtd->plat.gpio_rdy);
 94 }
 95 
 96 #ifdef CONFIG_OF
 97 static const struct of_device_id gpio_nand_id_table[] = {
 98         { .compatible = "gpio-control-nand" },
 99         {}
100 };
101 MODULE_DEVICE_TABLE(of, gpio_nand_id_table);
102 
103 static int gpio_nand_get_config_of(const struct device *dev,
104                                    struct gpio_nand_platdata *plat)
105 {
106         u32 val;
107 
108         if (!dev->of_node)
109                 return -ENODEV;
110 
111         if (!of_property_read_u32(dev->of_node, "bank-width", &val)) {
112                 if (val == 2) {
113                         plat->options |= NAND_BUSWIDTH_16;
114                 } else if (val != 1) {
115                         dev_err(dev, "invalid bank-width %u\n", val);
116                         return -EINVAL;
117                 }
118         }
119 
120         plat->gpio_rdy = of_get_gpio(dev->of_node, 0);
121         plat->gpio_nce = of_get_gpio(dev->of_node, 1);
122         plat->gpio_ale = of_get_gpio(dev->of_node, 2);
123         plat->gpio_cle = of_get_gpio(dev->of_node, 3);
124         plat->gpio_nwp = of_get_gpio(dev->of_node, 4);
125 
126         if (!of_property_read_u32(dev->of_node, "chip-delay", &val))
127                 plat->chip_delay = val;
128 
129         return 0;
130 }
131 
132 static struct resource *gpio_nand_get_io_sync_of(struct platform_device *pdev)
133 {
134         struct resource *r;
135         u64 addr;
136 
137         if (of_property_read_u64(pdev->dev.of_node,
138                                        "gpio-control-nand,io-sync-reg", &addr))
139                 return NULL;
140 
141         r = devm_kzalloc(&pdev->dev, sizeof(*r), GFP_KERNEL);
142         if (!r)
143                 return NULL;
144 
145         r->start = addr;
146         r->end = r->start + 0x3;
147         r->flags = IORESOURCE_MEM;
148 
149         return r;
150 }
151 #else /* CONFIG_OF */
152 static inline int gpio_nand_get_config_of(const struct device *dev,
153                                           struct gpio_nand_platdata *plat)
154 {
155         return -ENOSYS;
156 }
157 
158 static inline struct resource *
159 gpio_nand_get_io_sync_of(struct platform_device *pdev)
160 {
161         return NULL;
162 }
163 #endif /* CONFIG_OF */
164 
165 static inline int gpio_nand_get_config(const struct device *dev,
166                                        struct gpio_nand_platdata *plat)
167 {
168         int ret = gpio_nand_get_config_of(dev, plat);
169 
170         if (!ret)
171                 return ret;
172 
173         if (dev_get_platdata(dev)) {
174                 memcpy(plat, dev_get_platdata(dev), sizeof(*plat));
175                 return 0;
176         }
177 
178         return -EINVAL;
179 }
180 
181 static inline struct resource *
182 gpio_nand_get_io_sync(struct platform_device *pdev)
183 {
184         struct resource *r = gpio_nand_get_io_sync_of(pdev);
185 
186         if (r)
187                 return r;
188 
189         return platform_get_resource(pdev, IORESOURCE_MEM, 1);
190 }
191 
192 static int gpio_nand_remove(struct platform_device *pdev)
193 {
194         struct gpiomtd *gpiomtd = platform_get_drvdata(pdev);
195 
196         nand_release(&gpiomtd->mtd_info);
197 
198         if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
199                 gpio_set_value(gpiomtd->plat.gpio_nwp, 0);
200         gpio_set_value(gpiomtd->plat.gpio_nce, 1);
201 
202         return 0;
203 }
204 
205 static int gpio_nand_probe(struct platform_device *pdev)
206 {
207         struct gpiomtd *gpiomtd;
208         struct nand_chip *chip;
209         struct resource *res;
210         struct mtd_part_parser_data ppdata = {};
211         int ret = 0;
212 
213         if (!pdev->dev.of_node && !dev_get_platdata(&pdev->dev))
214                 return -EINVAL;
215 
216         gpiomtd = devm_kzalloc(&pdev->dev, sizeof(*gpiomtd), GFP_KERNEL);
217         if (!gpiomtd)
218                 return -ENOMEM;
219 
220         chip = &gpiomtd->nand_chip;
221 
222         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
223         chip->IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res);
224         if (IS_ERR(chip->IO_ADDR_R))
225                 return PTR_ERR(chip->IO_ADDR_R);
226 
227         res = gpio_nand_get_io_sync(pdev);
228         if (res) {
229                 gpiomtd->io_sync = devm_ioremap_resource(&pdev->dev, res);
230                 if (IS_ERR(gpiomtd->io_sync))
231                         return PTR_ERR(gpiomtd->io_sync);
232         }
233 
234         ret = gpio_nand_get_config(&pdev->dev, &gpiomtd->plat);
235         if (ret)
236                 return ret;
237 
238         ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_nce, "NAND NCE");
239         if (ret)
240                 return ret;
241         gpio_direction_output(gpiomtd->plat.gpio_nce, 1);
242 
243         if (gpio_is_valid(gpiomtd->plat.gpio_nwp)) {
244                 ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_nwp,
245                                         "NAND NWP");
246                 if (ret)
247                         return ret;
248         }
249 
250         ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_ale, "NAND ALE");
251         if (ret)
252                 return ret;
253         gpio_direction_output(gpiomtd->plat.gpio_ale, 0);
254 
255         ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_cle, "NAND CLE");
256         if (ret)
257                 return ret;
258         gpio_direction_output(gpiomtd->plat.gpio_cle, 0);
259 
260         if (gpio_is_valid(gpiomtd->plat.gpio_rdy)) {
261                 ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_rdy,
262                                         "NAND RDY");
263                 if (ret)
264                         return ret;
265                 gpio_direction_input(gpiomtd->plat.gpio_rdy);
266                 chip->dev_ready = gpio_nand_devready;
267         }
268 
269         chip->IO_ADDR_W         = chip->IO_ADDR_R;
270         chip->ecc.mode          = NAND_ECC_SOFT;
271         chip->options           = gpiomtd->plat.options;
272         chip->chip_delay        = gpiomtd->plat.chip_delay;
273         chip->cmd_ctrl          = gpio_nand_cmd_ctrl;
274 
275         gpiomtd->mtd_info.priv  = chip;
276         gpiomtd->mtd_info.owner = THIS_MODULE;
277 
278         platform_set_drvdata(pdev, gpiomtd);
279 
280         if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
281                 gpio_direction_output(gpiomtd->plat.gpio_nwp, 1);
282 
283         if (nand_scan(&gpiomtd->mtd_info, 1)) {
284                 ret = -ENXIO;
285                 goto err_wp;
286         }
287 
288         if (gpiomtd->plat.adjust_parts)
289                 gpiomtd->plat.adjust_parts(&gpiomtd->plat,
290                                            gpiomtd->mtd_info.size);
291 
292         ppdata.of_node = pdev->dev.of_node;
293         ret = mtd_device_parse_register(&gpiomtd->mtd_info, NULL, &ppdata,
294                                         gpiomtd->plat.parts,
295                                         gpiomtd->plat.num_parts);
296         if (!ret)
297                 return 0;
298 
299 err_wp:
300         if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
301                 gpio_set_value(gpiomtd->plat.gpio_nwp, 0);
302 
303         return ret;
304 }
305 
306 static struct platform_driver gpio_nand_driver = {
307         .probe          = gpio_nand_probe,
308         .remove         = gpio_nand_remove,
309         .driver         = {
310                 .name   = "gpio-nand",
311                 .owner  = THIS_MODULE,
312                 .of_match_table = of_match_ptr(gpio_nand_id_table),
313         },
314 };
315 
316 module_platform_driver(gpio_nand_driver);
317 
318 MODULE_LICENSE("GPL");
319 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
320 MODULE_DESCRIPTION("GPIO NAND Driver");
321 

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