Version:  2.0.40 2.2.26 2.4.37 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6

Linux/drivers/mtd/nand/fsmc_nand.c

  1 /*
  2  * drivers/mtd/nand/fsmc_nand.c
  3  *
  4  * ST Microelectronics
  5  * Flexible Static Memory Controller (FSMC)
  6  * Driver for NAND portions
  7  *
  8  * Copyright © 2010 ST Microelectronics
  9  * Vipin Kumar <vipin.kumar@st.com>
 10  * Ashish Priyadarshi
 11  *
 12  * Based on drivers/mtd/nand/nomadik_nand.c
 13  *
 14  * This file is licensed under the terms of the GNU General Public
 15  * License version 2. This program is licensed "as is" without any
 16  * warranty of any kind, whether express or implied.
 17  */
 18 
 19 #include <linux/clk.h>
 20 #include <linux/completion.h>
 21 #include <linux/dmaengine.h>
 22 #include <linux/dma-direction.h>
 23 #include <linux/dma-mapping.h>
 24 #include <linux/err.h>
 25 #include <linux/init.h>
 26 #include <linux/module.h>
 27 #include <linux/resource.h>
 28 #include <linux/sched.h>
 29 #include <linux/types.h>
 30 #include <linux/mtd/mtd.h>
 31 #include <linux/mtd/nand.h>
 32 #include <linux/mtd/nand_ecc.h>
 33 #include <linux/platform_device.h>
 34 #include <linux/of.h>
 35 #include <linux/mtd/partitions.h>
 36 #include <linux/io.h>
 37 #include <linux/slab.h>
 38 #include <linux/mtd/fsmc.h>
 39 #include <linux/amba/bus.h>
 40 #include <mtd/mtd-abi.h>
 41 
 42 static struct nand_ecclayout fsmc_ecc1_128_layout = {
 43         .eccbytes = 24,
 44         .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
 45                 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
 46         .oobfree = {
 47                 {.offset = 8, .length = 8},
 48                 {.offset = 24, .length = 8},
 49                 {.offset = 40, .length = 8},
 50                 {.offset = 56, .length = 8},
 51                 {.offset = 72, .length = 8},
 52                 {.offset = 88, .length = 8},
 53                 {.offset = 104, .length = 8},
 54                 {.offset = 120, .length = 8}
 55         }
 56 };
 57 
 58 static struct nand_ecclayout fsmc_ecc1_64_layout = {
 59         .eccbytes = 12,
 60         .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52},
 61         .oobfree = {
 62                 {.offset = 8, .length = 8},
 63                 {.offset = 24, .length = 8},
 64                 {.offset = 40, .length = 8},
 65                 {.offset = 56, .length = 8},
 66         }
 67 };
 68 
 69 static struct nand_ecclayout fsmc_ecc1_16_layout = {
 70         .eccbytes = 3,
 71         .eccpos = {2, 3, 4},
 72         .oobfree = {
 73                 {.offset = 8, .length = 8},
 74         }
 75 };
 76 
 77 /*
 78  * ECC4 layout for NAND of pagesize 8192 bytes & OOBsize 256 bytes. 13*16 bytes
 79  * of OB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 46
 80  * bytes are free for use.
 81  */
 82 static struct nand_ecclayout fsmc_ecc4_256_layout = {
 83         .eccbytes = 208,
 84         .eccpos = {  2,   3,   4,   5,   6,   7,   8,
 85                 9,  10,  11,  12,  13,  14,
 86                 18,  19,  20,  21,  22,  23,  24,
 87                 25,  26,  27,  28,  29,  30,
 88                 34,  35,  36,  37,  38,  39,  40,
 89                 41,  42,  43,  44,  45,  46,
 90                 50,  51,  52,  53,  54,  55,  56,
 91                 57,  58,  59,  60,  61,  62,
 92                 66,  67,  68,  69,  70,  71,  72,
 93                 73,  74,  75,  76,  77,  78,
 94                 82,  83,  84,  85,  86,  87,  88,
 95                 89,  90,  91,  92,  93,  94,
 96                 98,  99, 100, 101, 102, 103, 104,
 97                 105, 106, 107, 108, 109, 110,
 98                 114, 115, 116, 117, 118, 119, 120,
 99                 121, 122, 123, 124, 125, 126,
100                 130, 131, 132, 133, 134, 135, 136,
101                 137, 138, 139, 140, 141, 142,
102                 146, 147, 148, 149, 150, 151, 152,
103                 153, 154, 155, 156, 157, 158,
104                 162, 163, 164, 165, 166, 167, 168,
105                 169, 170, 171, 172, 173, 174,
106                 178, 179, 180, 181, 182, 183, 184,
107                 185, 186, 187, 188, 189, 190,
108                 194, 195, 196, 197, 198, 199, 200,
109                 201, 202, 203, 204, 205, 206,
110                 210, 211, 212, 213, 214, 215, 216,
111                 217, 218, 219, 220, 221, 222,
112                 226, 227, 228, 229, 230, 231, 232,
113                 233, 234, 235, 236, 237, 238,
114                 242, 243, 244, 245, 246, 247, 248,
115                 249, 250, 251, 252, 253, 254
116         },
117         .oobfree = {
118                 {.offset = 15, .length = 3},
119                 {.offset = 31, .length = 3},
120                 {.offset = 47, .length = 3},
121                 {.offset = 63, .length = 3},
122                 {.offset = 79, .length = 3},
123                 {.offset = 95, .length = 3},
124                 {.offset = 111, .length = 3},
125                 {.offset = 127, .length = 3},
126                 {.offset = 143, .length = 3},
127                 {.offset = 159, .length = 3},
128                 {.offset = 175, .length = 3},
129                 {.offset = 191, .length = 3},
130                 {.offset = 207, .length = 3},
131                 {.offset = 223, .length = 3},
132                 {.offset = 239, .length = 3},
133                 {.offset = 255, .length = 1}
134         }
135 };
136 
137 /*
138  * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes
139  * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118
140  * bytes are free for use.
141  */
142 static struct nand_ecclayout fsmc_ecc4_224_layout = {
143         .eccbytes = 104,
144         .eccpos = {  2,   3,   4,   5,   6,   7,   8,
145                 9,  10,  11,  12,  13,  14,
146                 18,  19,  20,  21,  22,  23,  24,
147                 25,  26,  27,  28,  29,  30,
148                 34,  35,  36,  37,  38,  39,  40,
149                 41,  42,  43,  44,  45,  46,
150                 50,  51,  52,  53,  54,  55,  56,
151                 57,  58,  59,  60,  61,  62,
152                 66,  67,  68,  69,  70,  71,  72,
153                 73,  74,  75,  76,  77,  78,
154                 82,  83,  84,  85,  86,  87,  88,
155                 89,  90,  91,  92,  93,  94,
156                 98,  99, 100, 101, 102, 103, 104,
157                 105, 106, 107, 108, 109, 110,
158                 114, 115, 116, 117, 118, 119, 120,
159                 121, 122, 123, 124, 125, 126
160         },
161         .oobfree = {
162                 {.offset = 15, .length = 3},
163                 {.offset = 31, .length = 3},
164                 {.offset = 47, .length = 3},
165                 {.offset = 63, .length = 3},
166                 {.offset = 79, .length = 3},
167                 {.offset = 95, .length = 3},
168                 {.offset = 111, .length = 3},
169                 {.offset = 127, .length = 97}
170         }
171 };
172 
173 /*
174  * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 128 bytes. 13*8 bytes
175  * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 22
176  * bytes are free for use.
177  */
178 static struct nand_ecclayout fsmc_ecc4_128_layout = {
179         .eccbytes = 104,
180         .eccpos = {  2,   3,   4,   5,   6,   7,   8,
181                 9,  10,  11,  12,  13,  14,
182                 18,  19,  20,  21,  22,  23,  24,
183                 25,  26,  27,  28,  29,  30,
184                 34,  35,  36,  37,  38,  39,  40,
185                 41,  42,  43,  44,  45,  46,
186                 50,  51,  52,  53,  54,  55,  56,
187                 57,  58,  59,  60,  61,  62,
188                 66,  67,  68,  69,  70,  71,  72,
189                 73,  74,  75,  76,  77,  78,
190                 82,  83,  84,  85,  86,  87,  88,
191                 89,  90,  91,  92,  93,  94,
192                 98,  99, 100, 101, 102, 103, 104,
193                 105, 106, 107, 108, 109, 110,
194                 114, 115, 116, 117, 118, 119, 120,
195                 121, 122, 123, 124, 125, 126
196         },
197         .oobfree = {
198                 {.offset = 15, .length = 3},
199                 {.offset = 31, .length = 3},
200                 {.offset = 47, .length = 3},
201                 {.offset = 63, .length = 3},
202                 {.offset = 79, .length = 3},
203                 {.offset = 95, .length = 3},
204                 {.offset = 111, .length = 3},
205                 {.offset = 127, .length = 1}
206         }
207 };
208 
209 /*
210  * ECC4 layout for NAND of pagesize 2048 bytes & OOBsize 64 bytes. 13*4 bytes of
211  * OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 10
212  * bytes are free for use.
213  */
214 static struct nand_ecclayout fsmc_ecc4_64_layout = {
215         .eccbytes = 52,
216         .eccpos = {  2,   3,   4,   5,   6,   7,   8,
217                 9,  10,  11,  12,  13,  14,
218                 18,  19,  20,  21,  22,  23,  24,
219                 25,  26,  27,  28,  29,  30,
220                 34,  35,  36,  37,  38,  39,  40,
221                 41,  42,  43,  44,  45,  46,
222                 50,  51,  52,  53,  54,  55,  56,
223                 57,  58,  59,  60,  61,  62,
224         },
225         .oobfree = {
226                 {.offset = 15, .length = 3},
227                 {.offset = 31, .length = 3},
228                 {.offset = 47, .length = 3},
229                 {.offset = 63, .length = 1},
230         }
231 };
232 
233 /*
234  * ECC4 layout for NAND of pagesize 512 bytes & OOBsize 16 bytes. 13 bytes of
235  * OOB size is reserved for ECC, Byte no. 4 & 5 reserved for bad block and One
236  * byte is free for use.
237  */
238 static struct nand_ecclayout fsmc_ecc4_16_layout = {
239         .eccbytes = 13,
240         .eccpos = { 0,  1,  2,  3,  6,  7, 8,
241                 9, 10, 11, 12, 13, 14
242         },
243         .oobfree = {
244                 {.offset = 15, .length = 1},
245         }
246 };
247 
248 /*
249  * ECC placement definitions in oobfree type format.
250  * There are 13 bytes of ecc for every 512 byte block and it has to be read
251  * consecutively and immediately after the 512 byte data block for hardware to
252  * generate the error bit offsets in 512 byte data.
253  * Managing the ecc bytes in the following way makes it easier for software to
254  * read ecc bytes consecutive to data bytes. This way is similar to
255  * oobfree structure maintained already in generic nand driver
256  */
257 static struct fsmc_eccplace fsmc_ecc4_lp_place = {
258         .eccplace = {
259                 {.offset = 2, .length = 13},
260                 {.offset = 18, .length = 13},
261                 {.offset = 34, .length = 13},
262                 {.offset = 50, .length = 13},
263                 {.offset = 66, .length = 13},
264                 {.offset = 82, .length = 13},
265                 {.offset = 98, .length = 13},
266                 {.offset = 114, .length = 13}
267         }
268 };
269 
270 static struct fsmc_eccplace fsmc_ecc4_sp_place = {
271         .eccplace = {
272                 {.offset = 0, .length = 4},
273                 {.offset = 6, .length = 9}
274         }
275 };
276 
277 /**
278  * struct fsmc_nand_data - structure for FSMC NAND device state
279  *
280  * @pid:                Part ID on the AMBA PrimeCell format
281  * @mtd:                MTD info for a NAND flash.
282  * @nand:               Chip related info for a NAND flash.
283  * @partitions:         Partition info for a NAND Flash.
284  * @nr_partitions:      Total number of partition of a NAND flash.
285  *
286  * @ecc_place:          ECC placing locations in oobfree type format.
287  * @bank:               Bank number for probed device.
288  * @clk:                Clock structure for FSMC.
289  *
290  * @read_dma_chan:      DMA channel for read access
291  * @write_dma_chan:     DMA channel for write access to NAND
292  * @dma_access_complete: Completion structure
293  *
294  * @data_pa:            NAND Physical port for Data.
295  * @data_va:            NAND port for Data.
296  * @cmd_va:             NAND port for Command.
297  * @addr_va:            NAND port for Address.
298  * @regs_va:            FSMC regs base address.
299  */
300 struct fsmc_nand_data {
301         u32                     pid;
302         struct nand_chip        nand;
303         struct mtd_partition    *partitions;
304         unsigned int            nr_partitions;
305 
306         struct fsmc_eccplace    *ecc_place;
307         unsigned int            bank;
308         struct device           *dev;
309         enum access_mode        mode;
310         struct clk              *clk;
311 
312         /* DMA related objects */
313         struct dma_chan         *read_dma_chan;
314         struct dma_chan         *write_dma_chan;
315         struct completion       dma_access_complete;
316 
317         struct fsmc_nand_timings *dev_timings;
318 
319         dma_addr_t              data_pa;
320         void __iomem            *data_va;
321         void __iomem            *cmd_va;
322         void __iomem            *addr_va;
323         void __iomem            *regs_va;
324 
325         void                    (*select_chip)(uint32_t bank, uint32_t busw);
326 };
327 
328 static inline struct fsmc_nand_data *mtd_to_fsmc(struct mtd_info *mtd)
329 {
330         return container_of(mtd_to_nand(mtd), struct fsmc_nand_data, nand);
331 }
332 
333 /* Assert CS signal based on chipnr */
334 static void fsmc_select_chip(struct mtd_info *mtd, int chipnr)
335 {
336         struct nand_chip *chip = mtd_to_nand(mtd);
337         struct fsmc_nand_data *host;
338 
339         host = mtd_to_fsmc(mtd);
340 
341         switch (chipnr) {
342         case -1:
343                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
344                 break;
345         case 0:
346         case 1:
347         case 2:
348         case 3:
349                 if (host->select_chip)
350                         host->select_chip(chipnr,
351                                         chip->options & NAND_BUSWIDTH_16);
352                 break;
353 
354         default:
355                 dev_err(host->dev, "unsupported chip-select %d\n", chipnr);
356         }
357 }
358 
359 /*
360  * fsmc_cmd_ctrl - For facilitaing Hardware access
361  * This routine allows hardware specific access to control-lines(ALE,CLE)
362  */
363 static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
364 {
365         struct nand_chip *this = mtd_to_nand(mtd);
366         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
367         void __iomem *regs = host->regs_va;
368         unsigned int bank = host->bank;
369 
370         if (ctrl & NAND_CTRL_CHANGE) {
371                 u32 pc;
372 
373                 if (ctrl & NAND_CLE) {
374                         this->IO_ADDR_R = host->cmd_va;
375                         this->IO_ADDR_W = host->cmd_va;
376                 } else if (ctrl & NAND_ALE) {
377                         this->IO_ADDR_R = host->addr_va;
378                         this->IO_ADDR_W = host->addr_va;
379                 } else {
380                         this->IO_ADDR_R = host->data_va;
381                         this->IO_ADDR_W = host->data_va;
382                 }
383 
384                 pc = readl(FSMC_NAND_REG(regs, bank, PC));
385                 if (ctrl & NAND_NCE)
386                         pc |= FSMC_ENABLE;
387                 else
388                         pc &= ~FSMC_ENABLE;
389                 writel_relaxed(pc, FSMC_NAND_REG(regs, bank, PC));
390         }
391 
392         mb();
393 
394         if (cmd != NAND_CMD_NONE)
395                 writeb_relaxed(cmd, this->IO_ADDR_W);
396 }
397 
398 /*
399  * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
400  *
401  * This routine initializes timing parameters related to NAND memory access in
402  * FSMC registers
403  */
404 static void fsmc_nand_setup(void __iomem *regs, uint32_t bank,
405                            uint32_t busw, struct fsmc_nand_timings *timings)
406 {
407         uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
408         uint32_t tclr, tar, thiz, thold, twait, tset;
409         struct fsmc_nand_timings *tims;
410         struct fsmc_nand_timings default_timings = {
411                 .tclr   = FSMC_TCLR_1,
412                 .tar    = FSMC_TAR_1,
413                 .thiz   = FSMC_THIZ_1,
414                 .thold  = FSMC_THOLD_4,
415                 .twait  = FSMC_TWAIT_6,
416                 .tset   = FSMC_TSET_0,
417         };
418 
419         if (timings)
420                 tims = timings;
421         else
422                 tims = &default_timings;
423 
424         tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
425         tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
426         thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
427         thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
428         twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
429         tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
430 
431         if (busw)
432                 writel_relaxed(value | FSMC_DEVWID_16,
433                                 FSMC_NAND_REG(regs, bank, PC));
434         else
435                 writel_relaxed(value | FSMC_DEVWID_8,
436                                 FSMC_NAND_REG(regs, bank, PC));
437 
438         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
439                         FSMC_NAND_REG(regs, bank, PC));
440         writel_relaxed(thiz | thold | twait | tset,
441                         FSMC_NAND_REG(regs, bank, COMM));
442         writel_relaxed(thiz | thold | twait | tset,
443                         FSMC_NAND_REG(regs, bank, ATTRIB));
444 }
445 
446 /*
447  * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
448  */
449 static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
450 {
451         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
452         void __iomem *regs = host->regs_va;
453         uint32_t bank = host->bank;
454 
455         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
456                         FSMC_NAND_REG(regs, bank, PC));
457         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
458                         FSMC_NAND_REG(regs, bank, PC));
459         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
460                         FSMC_NAND_REG(regs, bank, PC));
461 }
462 
463 /*
464  * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
465  * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
466  * max of 8-bits)
467  */
468 static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
469                                 uint8_t *ecc)
470 {
471         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
472         void __iomem *regs = host->regs_va;
473         uint32_t bank = host->bank;
474         uint32_t ecc_tmp;
475         unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
476 
477         do {
478                 if (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
479                         break;
480                 else
481                         cond_resched();
482         } while (!time_after_eq(jiffies, deadline));
483 
484         if (time_after_eq(jiffies, deadline)) {
485                 dev_err(host->dev, "calculate ecc timed out\n");
486                 return -ETIMEDOUT;
487         }
488 
489         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
490         ecc[0] = (uint8_t) (ecc_tmp >> 0);
491         ecc[1] = (uint8_t) (ecc_tmp >> 8);
492         ecc[2] = (uint8_t) (ecc_tmp >> 16);
493         ecc[3] = (uint8_t) (ecc_tmp >> 24);
494 
495         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
496         ecc[4] = (uint8_t) (ecc_tmp >> 0);
497         ecc[5] = (uint8_t) (ecc_tmp >> 8);
498         ecc[6] = (uint8_t) (ecc_tmp >> 16);
499         ecc[7] = (uint8_t) (ecc_tmp >> 24);
500 
501         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
502         ecc[8] = (uint8_t) (ecc_tmp >> 0);
503         ecc[9] = (uint8_t) (ecc_tmp >> 8);
504         ecc[10] = (uint8_t) (ecc_tmp >> 16);
505         ecc[11] = (uint8_t) (ecc_tmp >> 24);
506 
507         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
508         ecc[12] = (uint8_t) (ecc_tmp >> 16);
509 
510         return 0;
511 }
512 
513 /*
514  * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
515  * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
516  * max of 1-bit)
517  */
518 static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
519                                 uint8_t *ecc)
520 {
521         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
522         void __iomem *regs = host->regs_va;
523         uint32_t bank = host->bank;
524         uint32_t ecc_tmp;
525 
526         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
527         ecc[0] = (uint8_t) (ecc_tmp >> 0);
528         ecc[1] = (uint8_t) (ecc_tmp >> 8);
529         ecc[2] = (uint8_t) (ecc_tmp >> 16);
530 
531         return 0;
532 }
533 
534 /* Count the number of 0's in buff upto a max of max_bits */
535 static int count_written_bits(uint8_t *buff, int size, int max_bits)
536 {
537         int k, written_bits = 0;
538 
539         for (k = 0; k < size; k++) {
540                 written_bits += hweight8(~buff[k]);
541                 if (written_bits > max_bits)
542                         break;
543         }
544 
545         return written_bits;
546 }
547 
548 static void dma_complete(void *param)
549 {
550         struct fsmc_nand_data *host = param;
551 
552         complete(&host->dma_access_complete);
553 }
554 
555 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
556                 enum dma_data_direction direction)
557 {
558         struct dma_chan *chan;
559         struct dma_device *dma_dev;
560         struct dma_async_tx_descriptor *tx;
561         dma_addr_t dma_dst, dma_src, dma_addr;
562         dma_cookie_t cookie;
563         unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
564         int ret;
565         unsigned long time_left;
566 
567         if (direction == DMA_TO_DEVICE)
568                 chan = host->write_dma_chan;
569         else if (direction == DMA_FROM_DEVICE)
570                 chan = host->read_dma_chan;
571         else
572                 return -EINVAL;
573 
574         dma_dev = chan->device;
575         dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
576 
577         if (direction == DMA_TO_DEVICE) {
578                 dma_src = dma_addr;
579                 dma_dst = host->data_pa;
580         } else {
581                 dma_src = host->data_pa;
582                 dma_dst = dma_addr;
583         }
584 
585         tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
586                         len, flags);
587         if (!tx) {
588                 dev_err(host->dev, "device_prep_dma_memcpy error\n");
589                 ret = -EIO;
590                 goto unmap_dma;
591         }
592 
593         tx->callback = dma_complete;
594         tx->callback_param = host;
595         cookie = tx->tx_submit(tx);
596 
597         ret = dma_submit_error(cookie);
598         if (ret) {
599                 dev_err(host->dev, "dma_submit_error %d\n", cookie);
600                 goto unmap_dma;
601         }
602 
603         dma_async_issue_pending(chan);
604 
605         time_left =
606         wait_for_completion_timeout(&host->dma_access_complete,
607                                 msecs_to_jiffies(3000));
608         if (time_left == 0) {
609                 dmaengine_terminate_all(chan);
610                 dev_err(host->dev, "wait_for_completion_timeout\n");
611                 ret = -ETIMEDOUT;
612                 goto unmap_dma;
613         }
614 
615         ret = 0;
616 
617 unmap_dma:
618         dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
619 
620         return ret;
621 }
622 
623 /*
624  * fsmc_write_buf - write buffer to chip
625  * @mtd:        MTD device structure
626  * @buf:        data buffer
627  * @len:        number of bytes to write
628  */
629 static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
630 {
631         int i;
632         struct nand_chip *chip = mtd_to_nand(mtd);
633 
634         if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
635                         IS_ALIGNED(len, sizeof(uint32_t))) {
636                 uint32_t *p = (uint32_t *)buf;
637                 len = len >> 2;
638                 for (i = 0; i < len; i++)
639                         writel_relaxed(p[i], chip->IO_ADDR_W);
640         } else {
641                 for (i = 0; i < len; i++)
642                         writeb_relaxed(buf[i], chip->IO_ADDR_W);
643         }
644 }
645 
646 /*
647  * fsmc_read_buf - read chip data into buffer
648  * @mtd:        MTD device structure
649  * @buf:        buffer to store date
650  * @len:        number of bytes to read
651  */
652 static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
653 {
654         int i;
655         struct nand_chip *chip = mtd_to_nand(mtd);
656 
657         if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
658                         IS_ALIGNED(len, sizeof(uint32_t))) {
659                 uint32_t *p = (uint32_t *)buf;
660                 len = len >> 2;
661                 for (i = 0; i < len; i++)
662                         p[i] = readl_relaxed(chip->IO_ADDR_R);
663         } else {
664                 for (i = 0; i < len; i++)
665                         buf[i] = readb_relaxed(chip->IO_ADDR_R);
666         }
667 }
668 
669 /*
670  * fsmc_read_buf_dma - read chip data into buffer
671  * @mtd:        MTD device structure
672  * @buf:        buffer to store date
673  * @len:        number of bytes to read
674  */
675 static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
676 {
677         struct fsmc_nand_data *host  = mtd_to_fsmc(mtd);
678 
679         dma_xfer(host, buf, len, DMA_FROM_DEVICE);
680 }
681 
682 /*
683  * fsmc_write_buf_dma - write buffer to chip
684  * @mtd:        MTD device structure
685  * @buf:        data buffer
686  * @len:        number of bytes to write
687  */
688 static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
689                 int len)
690 {
691         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
692 
693         dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
694 }
695 
696 /*
697  * fsmc_read_page_hwecc
698  * @mtd:        mtd info structure
699  * @chip:       nand chip info structure
700  * @buf:        buffer to store read data
701  * @oob_required:       caller expects OOB data read to chip->oob_poi
702  * @page:       page number to read
703  *
704  * This routine is needed for fsmc version 8 as reading from NAND chip has to be
705  * performed in a strict sequence as follows:
706  * data(512 byte) -> ecc(13 byte)
707  * After this read, fsmc hardware generates and reports error data bits(up to a
708  * max of 8 bits)
709  */
710 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
711                                  uint8_t *buf, int oob_required, int page)
712 {
713         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
714         struct fsmc_eccplace *ecc_place = host->ecc_place;
715         int i, j, s, stat, eccsize = chip->ecc.size;
716         int eccbytes = chip->ecc.bytes;
717         int eccsteps = chip->ecc.steps;
718         uint8_t *p = buf;
719         uint8_t *ecc_calc = chip->buffers->ecccalc;
720         uint8_t *ecc_code = chip->buffers->ecccode;
721         int off, len, group = 0;
722         /*
723          * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
724          * end up reading 14 bytes (7 words) from oob. The local array is
725          * to maintain word alignment
726          */
727         uint16_t ecc_oob[7];
728         uint8_t *oob = (uint8_t *)&ecc_oob[0];
729         unsigned int max_bitflips = 0;
730 
731         for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
732                 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
733                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
734                 chip->read_buf(mtd, p, eccsize);
735 
736                 for (j = 0; j < eccbytes;) {
737                         off = ecc_place->eccplace[group].offset;
738                         len = ecc_place->eccplace[group].length;
739                         group++;
740 
741                         /*
742                          * length is intentionally kept a higher multiple of 2
743                          * to read at least 13 bytes even in case of 16 bit NAND
744                          * devices
745                          */
746                         if (chip->options & NAND_BUSWIDTH_16)
747                                 len = roundup(len, 2);
748 
749                         chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
750                         chip->read_buf(mtd, oob + j, len);
751                         j += len;
752                 }
753 
754                 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
755                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
756 
757                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
758                 if (stat < 0) {
759                         mtd->ecc_stats.failed++;
760                 } else {
761                         mtd->ecc_stats.corrected += stat;
762                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
763                 }
764         }
765 
766         return max_bitflips;
767 }
768 
769 /*
770  * fsmc_bch8_correct_data
771  * @mtd:        mtd info structure
772  * @dat:        buffer of read data
773  * @read_ecc:   ecc read from device spare area
774  * @calc_ecc:   ecc calculated from read data
775  *
776  * calc_ecc is a 104 bit information containing maximum of 8 error
777  * offset informations of 13 bits each in 512 bytes of read data.
778  */
779 static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
780                              uint8_t *read_ecc, uint8_t *calc_ecc)
781 {
782         struct nand_chip *chip = mtd_to_nand(mtd);
783         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
784         void __iomem *regs = host->regs_va;
785         unsigned int bank = host->bank;
786         uint32_t err_idx[8];
787         uint32_t num_err, i;
788         uint32_t ecc1, ecc2, ecc3, ecc4;
789 
790         num_err = (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
791 
792         /* no bit flipping */
793         if (likely(num_err == 0))
794                 return 0;
795 
796         /* too many errors */
797         if (unlikely(num_err > 8)) {
798                 /*
799                  * This is a temporary erase check. A newly erased page read
800                  * would result in an ecc error because the oob data is also
801                  * erased to FF and the calculated ecc for an FF data is not
802                  * FF..FF.
803                  * This is a workaround to skip performing correction in case
804                  * data is FF..FF
805                  *
806                  * Logic:
807                  * For every page, each bit written as 0 is counted until these
808                  * number of bits are greater than 8 (the maximum correction
809                  * capability of FSMC for each 512 + 13 bytes)
810                  */
811 
812                 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
813                 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
814 
815                 if ((bits_ecc + bits_data) <= 8) {
816                         if (bits_data)
817                                 memset(dat, 0xff, chip->ecc.size);
818                         return bits_data;
819                 }
820 
821                 return -EBADMSG;
822         }
823 
824         /*
825          * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
826          * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
827          *
828          * calc_ecc is a 104 bit information containing maximum of 8 error
829          * offset informations of 13 bits each. calc_ecc is copied into a
830          * uint64_t array and error offset indexes are populated in err_idx
831          * array
832          */
833         ecc1 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
834         ecc2 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
835         ecc3 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
836         ecc4 = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
837 
838         err_idx[0] = (ecc1 >> 0) & 0x1FFF;
839         err_idx[1] = (ecc1 >> 13) & 0x1FFF;
840         err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
841         err_idx[3] = (ecc2 >> 7) & 0x1FFF;
842         err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
843         err_idx[5] = (ecc3 >> 1) & 0x1FFF;
844         err_idx[6] = (ecc3 >> 14) & 0x1FFF;
845         err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
846 
847         i = 0;
848         while (num_err--) {
849                 change_bit(0, (unsigned long *)&err_idx[i]);
850                 change_bit(1, (unsigned long *)&err_idx[i]);
851 
852                 if (err_idx[i] < chip->ecc.size * 8) {
853                         change_bit(err_idx[i], (unsigned long *)dat);
854                         i++;
855                 }
856         }
857         return i;
858 }
859 
860 static bool filter(struct dma_chan *chan, void *slave)
861 {
862         chan->private = slave;
863         return true;
864 }
865 
866 #ifdef CONFIG_OF
867 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
868                                      struct device_node *np)
869 {
870         struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
871         u32 val;
872         int ret;
873 
874         /* Set default NAND width to 8 bits */
875         pdata->width = 8;
876         if (!of_property_read_u32(np, "bank-width", &val)) {
877                 if (val == 2) {
878                         pdata->width = 16;
879                 } else if (val != 1) {
880                         dev_err(&pdev->dev, "invalid bank-width %u\n", val);
881                         return -EINVAL;
882                 }
883         }
884         if (of_get_property(np, "nand-skip-bbtscan", NULL))
885                 pdata->options = NAND_SKIP_BBTSCAN;
886 
887         pdata->nand_timings = devm_kzalloc(&pdev->dev,
888                                 sizeof(*pdata->nand_timings), GFP_KERNEL);
889         if (!pdata->nand_timings)
890                 return -ENOMEM;
891         ret = of_property_read_u8_array(np, "timings", (u8 *)pdata->nand_timings,
892                                                 sizeof(*pdata->nand_timings));
893         if (ret) {
894                 dev_info(&pdev->dev, "No timings in dts specified, using default timings!\n");
895                 pdata->nand_timings = NULL;
896         }
897 
898         /* Set default NAND bank to 0 */
899         pdata->bank = 0;
900         if (!of_property_read_u32(np, "bank", &val)) {
901                 if (val > 3) {
902                         dev_err(&pdev->dev, "invalid bank %u\n", val);
903                         return -EINVAL;
904                 }
905                 pdata->bank = val;
906         }
907         return 0;
908 }
909 #else
910 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
911                                      struct device_node *np)
912 {
913         return -ENOSYS;
914 }
915 #endif
916 
917 /*
918  * fsmc_nand_probe - Probe function
919  * @pdev:       platform device structure
920  */
921 static int __init fsmc_nand_probe(struct platform_device *pdev)
922 {
923         struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
924         struct device_node __maybe_unused *np = pdev->dev.of_node;
925         struct fsmc_nand_data *host;
926         struct mtd_info *mtd;
927         struct nand_chip *nand;
928         struct resource *res;
929         dma_cap_mask_t mask;
930         int ret = 0;
931         u32 pid;
932         int i;
933 
934         if (np) {
935                 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
936                 pdev->dev.platform_data = pdata;
937                 ret = fsmc_nand_probe_config_dt(pdev, np);
938                 if (ret) {
939                         dev_err(&pdev->dev, "no platform data\n");
940                         return -ENODEV;
941                 }
942         }
943 
944         if (!pdata) {
945                 dev_err(&pdev->dev, "platform data is NULL\n");
946                 return -EINVAL;
947         }
948 
949         /* Allocate memory for the device structure (and zero it) */
950         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
951         if (!host)
952                 return -ENOMEM;
953 
954         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
955         host->data_va = devm_ioremap_resource(&pdev->dev, res);
956         if (IS_ERR(host->data_va))
957                 return PTR_ERR(host->data_va);
958 
959         host->data_pa = (dma_addr_t)res->start;
960 
961         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
962         host->addr_va = devm_ioremap_resource(&pdev->dev, res);
963         if (IS_ERR(host->addr_va))
964                 return PTR_ERR(host->addr_va);
965 
966         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
967         host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
968         if (IS_ERR(host->cmd_va))
969                 return PTR_ERR(host->cmd_va);
970 
971         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
972         host->regs_va = devm_ioremap_resource(&pdev->dev, res);
973         if (IS_ERR(host->regs_va))
974                 return PTR_ERR(host->regs_va);
975 
976         host->clk = clk_get(&pdev->dev, NULL);
977         if (IS_ERR(host->clk)) {
978                 dev_err(&pdev->dev, "failed to fetch block clock\n");
979                 return PTR_ERR(host->clk);
980         }
981 
982         ret = clk_prepare_enable(host->clk);
983         if (ret)
984                 goto err_clk_prepare_enable;
985 
986         /*
987          * This device ID is actually a common AMBA ID as used on the
988          * AMBA PrimeCell bus. However it is not a PrimeCell.
989          */
990         for (pid = 0, i = 0; i < 4; i++)
991                 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
992         host->pid = pid;
993         dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
994                  "revision %02x, config %02x\n",
995                  AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
996                  AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
997 
998         host->bank = pdata->bank;
999         host->select_chip = pdata->select_bank;
1000         host->partitions = pdata->partitions;
1001         host->nr_partitions = pdata->nr_partitions;
1002         host->dev = &pdev->dev;
1003         host->dev_timings = pdata->nand_timings;
1004         host->mode = pdata->mode;
1005 
1006         if (host->mode == USE_DMA_ACCESS)
1007                 init_completion(&host->dma_access_complete);
1008 
1009         /* Link all private pointers */
1010         mtd = nand_to_mtd(&host->nand);
1011         nand = &host->nand;
1012         nand_set_controller_data(nand, host);
1013         nand_set_flash_node(nand, np);
1014 
1015         mtd->dev.parent = &pdev->dev;
1016         nand->IO_ADDR_R = host->data_va;
1017         nand->IO_ADDR_W = host->data_va;
1018         nand->cmd_ctrl = fsmc_cmd_ctrl;
1019         nand->chip_delay = 30;
1020 
1021         /*
1022          * Setup default ECC mode. nand_dt_init() called from nand_scan_ident()
1023          * can overwrite this value if the DT provides a different value.
1024          */
1025         nand->ecc.mode = NAND_ECC_HW;
1026         nand->ecc.hwctl = fsmc_enable_hwecc;
1027         nand->ecc.size = 512;
1028         nand->options = pdata->options;
1029         nand->select_chip = fsmc_select_chip;
1030         nand->badblockbits = 7;
1031         nand_set_flash_node(nand, np);
1032 
1033         if (pdata->width == FSMC_NAND_BW16)
1034                 nand->options |= NAND_BUSWIDTH_16;
1035 
1036         switch (host->mode) {
1037         case USE_DMA_ACCESS:
1038                 dma_cap_zero(mask);
1039                 dma_cap_set(DMA_MEMCPY, mask);
1040                 host->read_dma_chan = dma_request_channel(mask, filter,
1041                                 pdata->read_dma_priv);
1042                 if (!host->read_dma_chan) {
1043                         dev_err(&pdev->dev, "Unable to get read dma channel\n");
1044                         goto err_req_read_chnl;
1045                 }
1046                 host->write_dma_chan = dma_request_channel(mask, filter,
1047                                 pdata->write_dma_priv);
1048                 if (!host->write_dma_chan) {
1049                         dev_err(&pdev->dev, "Unable to get write dma channel\n");
1050                         goto err_req_write_chnl;
1051                 }
1052                 nand->read_buf = fsmc_read_buf_dma;
1053                 nand->write_buf = fsmc_write_buf_dma;
1054                 break;
1055 
1056         default:
1057         case USE_WORD_ACCESS:
1058                 nand->read_buf = fsmc_read_buf;
1059                 nand->write_buf = fsmc_write_buf;
1060                 break;
1061         }
1062 
1063         fsmc_nand_setup(host->regs_va, host->bank,
1064                         nand->options & NAND_BUSWIDTH_16,
1065                         host->dev_timings);
1066 
1067         if (AMBA_REV_BITS(host->pid) >= 8) {
1068                 nand->ecc.read_page = fsmc_read_page_hwecc;
1069                 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
1070                 nand->ecc.correct = fsmc_bch8_correct_data;
1071                 nand->ecc.bytes = 13;
1072                 nand->ecc.strength = 8;
1073         }
1074 
1075         /*
1076          * Scan to find existence of the device
1077          */
1078         if (nand_scan_ident(mtd, 1, NULL)) {
1079                 ret = -ENXIO;
1080                 dev_err(&pdev->dev, "No NAND Device found!\n");
1081                 goto err_scan_ident;
1082         }
1083 
1084         if (AMBA_REV_BITS(host->pid) >= 8) {
1085                 switch (mtd->oobsize) {
1086                 case 16:
1087                         nand->ecc.layout = &fsmc_ecc4_16_layout;
1088                         host->ecc_place = &fsmc_ecc4_sp_place;
1089                         break;
1090                 case 64:
1091                         nand->ecc.layout = &fsmc_ecc4_64_layout;
1092                         host->ecc_place = &fsmc_ecc4_lp_place;
1093                         break;
1094                 case 128:
1095                         nand->ecc.layout = &fsmc_ecc4_128_layout;
1096                         host->ecc_place = &fsmc_ecc4_lp_place;
1097                         break;
1098                 case 224:
1099                         nand->ecc.layout = &fsmc_ecc4_224_layout;
1100                         host->ecc_place = &fsmc_ecc4_lp_place;
1101                         break;
1102                 case 256:
1103                         nand->ecc.layout = &fsmc_ecc4_256_layout;
1104                         host->ecc_place = &fsmc_ecc4_lp_place;
1105                         break;
1106                 default:
1107                         dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
1108                                  mtd->oobsize);
1109                         ret = -EINVAL;
1110                         goto err_probe;
1111                 }
1112         } else {
1113                 switch (nand->ecc.mode) {
1114                 case NAND_ECC_HW:
1115                         dev_info(&pdev->dev, "Using 1-bit HW ECC scheme\n");
1116                         nand->ecc.calculate = fsmc_read_hwecc_ecc1;
1117                         nand->ecc.correct = nand_correct_data;
1118                         nand->ecc.bytes = 3;
1119                         nand->ecc.strength = 1;
1120                         break;
1121 
1122                 case NAND_ECC_SOFT_BCH:
1123                         dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
1124                         break;
1125 
1126                 default:
1127                         dev_err(&pdev->dev, "Unsupported ECC mode!\n");
1128                         goto err_probe;
1129                 }
1130 
1131                 /*
1132                  * Don't set layout for BCH4 SW ECC. This will be
1133                  * generated later in nand_bch_init() later.
1134                  */
1135                 if (nand->ecc.mode != NAND_ECC_SOFT_BCH) {
1136                         switch (mtd->oobsize) {
1137                         case 16:
1138                                 nand->ecc.layout = &fsmc_ecc1_16_layout;
1139                                 break;
1140                         case 64:
1141                                 nand->ecc.layout = &fsmc_ecc1_64_layout;
1142                                 break;
1143                         case 128:
1144                                 nand->ecc.layout = &fsmc_ecc1_128_layout;
1145                                 break;
1146                         default:
1147                                 dev_warn(&pdev->dev,
1148                                          "No oob scheme defined for oobsize %d\n",
1149                                          mtd->oobsize);
1150                                 ret = -EINVAL;
1151                                 goto err_probe;
1152                         }
1153                 }
1154         }
1155 
1156         /* Second stage of scan to fill MTD data-structures */
1157         if (nand_scan_tail(mtd)) {
1158                 ret = -ENXIO;
1159                 goto err_probe;
1160         }
1161 
1162         /*
1163          * The partition information can is accessed by (in the same precedence)
1164          *
1165          * command line through Bootloader,
1166          * platform data,
1167          * default partition information present in driver.
1168          */
1169         /*
1170          * Check for partition info passed
1171          */
1172         mtd->name = "nand";
1173         ret = mtd_device_register(mtd, host->partitions, host->nr_partitions);
1174         if (ret)
1175                 goto err_probe;
1176 
1177         platform_set_drvdata(pdev, host);
1178         dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1179         return 0;
1180 
1181 err_probe:
1182 err_scan_ident:
1183         if (host->mode == USE_DMA_ACCESS)
1184                 dma_release_channel(host->write_dma_chan);
1185 err_req_write_chnl:
1186         if (host->mode == USE_DMA_ACCESS)
1187                 dma_release_channel(host->read_dma_chan);
1188 err_req_read_chnl:
1189         clk_disable_unprepare(host->clk);
1190 err_clk_prepare_enable:
1191         clk_put(host->clk);
1192         return ret;
1193 }
1194 
1195 /*
1196  * Clean up routine
1197  */
1198 static int fsmc_nand_remove(struct platform_device *pdev)
1199 {
1200         struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1201 
1202         if (host) {
1203                 nand_release(nand_to_mtd(&host->nand));
1204 
1205                 if (host->mode == USE_DMA_ACCESS) {
1206                         dma_release_channel(host->write_dma_chan);
1207                         dma_release_channel(host->read_dma_chan);
1208                 }
1209                 clk_disable_unprepare(host->clk);
1210                 clk_put(host->clk);
1211         }
1212 
1213         return 0;
1214 }
1215 
1216 #ifdef CONFIG_PM_SLEEP
1217 static int fsmc_nand_suspend(struct device *dev)
1218 {
1219         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1220         if (host)
1221                 clk_disable_unprepare(host->clk);
1222         return 0;
1223 }
1224 
1225 static int fsmc_nand_resume(struct device *dev)
1226 {
1227         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1228         if (host) {
1229                 clk_prepare_enable(host->clk);
1230                 fsmc_nand_setup(host->regs_va, host->bank,
1231                                 host->nand.options & NAND_BUSWIDTH_16,
1232                                 host->dev_timings);
1233         }
1234         return 0;
1235 }
1236 #endif
1237 
1238 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1239 
1240 #ifdef CONFIG_OF
1241 static const struct of_device_id fsmc_nand_id_table[] = {
1242         { .compatible = "st,spear600-fsmc-nand" },
1243         { .compatible = "stericsson,fsmc-nand" },
1244         {}
1245 };
1246 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1247 #endif
1248 
1249 static struct platform_driver fsmc_nand_driver = {
1250         .remove = fsmc_nand_remove,
1251         .driver = {
1252                 .name = "fsmc-nand",
1253                 .of_match_table = of_match_ptr(fsmc_nand_id_table),
1254                 .pm = &fsmc_nand_pm_ops,
1255         },
1256 };
1257 
1258 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
1259 
1260 MODULE_LICENSE("GPL");
1261 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1262 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");
1263 

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