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Linux/drivers/mtd/nand/fsl_elbc_nand.c

  1 /* Freescale Enhanced Local Bus Controller NAND driver
  2  *
  3  * Copyright © 2006-2007, 2010 Freescale Semiconductor
  4  *
  5  * Authors: Nick Spence <nick.spence@freescale.com>,
  6  *          Scott Wood <scottwood@freescale.com>
  7  *          Jack Lan <jack.lan@freescale.com>
  8  *          Roy Zang <tie-fei.zang@freescale.com>
  9  *
 10  * This program is free software; you can redistribute it and/or modify
 11  * it under the terms of the GNU General Public License as published by
 12  * the Free Software Foundation; either version 2 of the License, or
 13  * (at your option) any later version.
 14  *
 15  * This program is distributed in the hope that it will be useful,
 16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 18  * GNU General Public License for more details.
 19  *
 20  * You should have received a copy of the GNU General Public License
 21  * along with this program; if not, write to the Free Software
 22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 23  */
 24 
 25 #include <linux/module.h>
 26 #include <linux/types.h>
 27 #include <linux/kernel.h>
 28 #include <linux/string.h>
 29 #include <linux/ioport.h>
 30 #include <linux/of_address.h>
 31 #include <linux/of_platform.h>
 32 #include <linux/platform_device.h>
 33 #include <linux/slab.h>
 34 #include <linux/interrupt.h>
 35 
 36 #include <linux/mtd/mtd.h>
 37 #include <linux/mtd/nand.h>
 38 #include <linux/mtd/nand_ecc.h>
 39 #include <linux/mtd/partitions.h>
 40 
 41 #include <asm/io.h>
 42 #include <asm/fsl_lbc.h>
 43 
 44 #define MAX_BANKS 8
 45 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
 46 #define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
 47 
 48 /* mtd information per set */
 49 
 50 struct fsl_elbc_mtd {
 51         struct nand_chip chip;
 52         struct fsl_lbc_ctrl *ctrl;
 53 
 54         struct device *dev;
 55         int bank;               /* Chip select bank number           */
 56         u8 __iomem *vbase;      /* Chip select base virtual address  */
 57         int page_size;          /* NAND page size (0=512, 1=2048)    */
 58         unsigned int fmr;       /* FCM Flash Mode Register value     */
 59 };
 60 
 61 /* Freescale eLBC FCM controller information */
 62 
 63 struct fsl_elbc_fcm_ctrl {
 64         struct nand_hw_control controller;
 65         struct fsl_elbc_mtd *chips[MAX_BANKS];
 66 
 67         u8 __iomem *addr;        /* Address of assigned FCM buffer        */
 68         unsigned int page;       /* Last page written to / read from      */
 69         unsigned int read_bytes; /* Number of bytes read during command   */
 70         unsigned int column;     /* Saved column from SEQIN               */
 71         unsigned int index;      /* Pointer to next byte to 'read'        */
 72         unsigned int status;     /* status read from LTESR after last op  */
 73         unsigned int mdr;        /* UPM/FCM Data Register value           */
 74         unsigned int use_mdr;    /* Non zero if the MDR is to be set      */
 75         unsigned int oob;        /* Non zero if operating on OOB data     */
 76         unsigned int counter;    /* counter for the initializations       */
 77         unsigned int max_bitflips;  /* Saved during READ0 cmd             */
 78 };
 79 
 80 /* These map to the positions used by the FCM hardware ECC generator */
 81 
 82 /* Small Page FLASH with FMR[ECCM] = 0 */
 83 static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
 84         .eccbytes = 3,
 85         .eccpos = {6, 7, 8},
 86         .oobfree = { {0, 5}, {9, 7} },
 87 };
 88 
 89 /* Small Page FLASH with FMR[ECCM] = 1 */
 90 static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
 91         .eccbytes = 3,
 92         .eccpos = {8, 9, 10},
 93         .oobfree = { {0, 5}, {6, 2}, {11, 5} },
 94 };
 95 
 96 /* Large Page FLASH with FMR[ECCM] = 0 */
 97 static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
 98         .eccbytes = 12,
 99         .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
100         .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
101 };
102 
103 /* Large Page FLASH with FMR[ECCM] = 1 */
104 static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
105         .eccbytes = 12,
106         .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
107         .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
108 };
109 
110 /*
111  * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
112  * interfere with ECC positions, that's why we implement our own descriptors.
113  * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
114  */
115 static u8 bbt_pattern[] = {'B', 'b', 't', '' };
116 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
117 
118 static struct nand_bbt_descr bbt_main_descr = {
119         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
120                    NAND_BBT_2BIT | NAND_BBT_VERSION,
121         .offs = 11,
122         .len = 4,
123         .veroffs = 15,
124         .maxblocks = 4,
125         .pattern = bbt_pattern,
126 };
127 
128 static struct nand_bbt_descr bbt_mirror_descr = {
129         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
130                    NAND_BBT_2BIT | NAND_BBT_VERSION,
131         .offs = 11,
132         .len = 4,
133         .veroffs = 15,
134         .maxblocks = 4,
135         .pattern = mirror_pattern,
136 };
137 
138 /*=================================*/
139 
140 /*
141  * Set up the FCM hardware block and page address fields, and the fcm
142  * structure addr field to point to the correct FCM buffer in memory
143  */
144 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
145 {
146         struct nand_chip *chip = mtd_to_nand(mtd);
147         struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
148         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
149         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
150         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
151         int buf_num;
152 
153         elbc_fcm_ctrl->page = page_addr;
154 
155         if (priv->page_size) {
156                 /*
157                  * large page size chip : FPAR[PI] save the lowest 6 bits,
158                  *                        FBAR[BLK] save the other bits.
159                  */
160                 out_be32(&lbc->fbar, page_addr >> 6);
161                 out_be32(&lbc->fpar,
162                          ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
163                          (oob ? FPAR_LP_MS : 0) | column);
164                 buf_num = (page_addr & 1) << 2;
165         } else {
166                 /*
167                  * small page size chip : FPAR[PI] save the lowest 5 bits,
168                  *                        FBAR[BLK] save the other bits.
169                  */
170                 out_be32(&lbc->fbar, page_addr >> 5);
171                 out_be32(&lbc->fpar,
172                          ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
173                          (oob ? FPAR_SP_MS : 0) | column);
174                 buf_num = page_addr & 7;
175         }
176 
177         elbc_fcm_ctrl->addr = priv->vbase + buf_num * 1024;
178         elbc_fcm_ctrl->index = column;
179 
180         /* for OOB data point to the second half of the buffer */
181         if (oob)
182                 elbc_fcm_ctrl->index += priv->page_size ? 2048 : 512;
183 
184         dev_vdbg(priv->dev, "set_addr: bank=%d, "
185                             "elbc_fcm_ctrl->addr=0x%p (0x%p), "
186                             "index %x, pes %d ps %d\n",
187                  buf_num, elbc_fcm_ctrl->addr, priv->vbase,
188                  elbc_fcm_ctrl->index,
189                  chip->phys_erase_shift, chip->page_shift);
190 }
191 
192 /*
193  * execute FCM command and wait for it to complete
194  */
195 static int fsl_elbc_run_command(struct mtd_info *mtd)
196 {
197         struct nand_chip *chip = mtd_to_nand(mtd);
198         struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
199         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
200         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
201         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
202 
203         /* Setup the FMR[OP] to execute without write protection */
204         out_be32(&lbc->fmr, priv->fmr | 3);
205         if (elbc_fcm_ctrl->use_mdr)
206                 out_be32(&lbc->mdr, elbc_fcm_ctrl->mdr);
207 
208         dev_vdbg(priv->dev,
209                  "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
210                  in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
211         dev_vdbg(priv->dev,
212                  "fsl_elbc_run_command: fbar=%08x fpar=%08x "
213                  "fbcr=%08x bank=%d\n",
214                  in_be32(&lbc->fbar), in_be32(&lbc->fpar),
215                  in_be32(&lbc->fbcr), priv->bank);
216 
217         ctrl->irq_status = 0;
218         /* execute special operation */
219         out_be32(&lbc->lsor, priv->bank);
220 
221         /* wait for FCM complete flag or timeout */
222         wait_event_timeout(ctrl->irq_wait, ctrl->irq_status,
223                            FCM_TIMEOUT_MSECS * HZ/1000);
224         elbc_fcm_ctrl->status = ctrl->irq_status;
225         /* store mdr value in case it was needed */
226         if (elbc_fcm_ctrl->use_mdr)
227                 elbc_fcm_ctrl->mdr = in_be32(&lbc->mdr);
228 
229         elbc_fcm_ctrl->use_mdr = 0;
230 
231         if (elbc_fcm_ctrl->status != LTESR_CC) {
232                 dev_info(priv->dev,
233                          "command failed: fir %x fcr %x status %x mdr %x\n",
234                          in_be32(&lbc->fir), in_be32(&lbc->fcr),
235                          elbc_fcm_ctrl->status, elbc_fcm_ctrl->mdr);
236                 return -EIO;
237         }
238 
239         if (chip->ecc.mode != NAND_ECC_HW)
240                 return 0;
241 
242         elbc_fcm_ctrl->max_bitflips = 0;
243 
244         if (elbc_fcm_ctrl->read_bytes == mtd->writesize + mtd->oobsize) {
245                 uint32_t lteccr = in_be32(&lbc->lteccr);
246                 /*
247                  * if command was a full page read and the ELBC
248                  * has the LTECCR register, then bits 12-15 (ppc order) of
249                  * LTECCR indicates which 512 byte sub-pages had fixed errors.
250                  * bits 28-31 are uncorrectable errors, marked elsewhere.
251                  * for small page nand only 1 bit is used.
252                  * if the ELBC doesn't have the lteccr register it reads 0
253                  * FIXME: 4 bits can be corrected on NANDs with 2k pages, so
254                  * count the number of sub-pages with bitflips and update
255                  * ecc_stats.corrected accordingly.
256                  */
257                 if (lteccr & 0x000F000F)
258                         out_be32(&lbc->lteccr, 0x000F000F); /* clear lteccr */
259                 if (lteccr & 0x000F0000) {
260                         mtd->ecc_stats.corrected++;
261                         elbc_fcm_ctrl->max_bitflips = 1;
262                 }
263         }
264 
265         return 0;
266 }
267 
268 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
269 {
270         struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
271         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
272         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
273 
274         if (priv->page_size) {
275                 out_be32(&lbc->fir,
276                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
277                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
278                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
279                          (FIR_OP_CM1 << FIR_OP3_SHIFT) |
280                          (FIR_OP_RBW << FIR_OP4_SHIFT));
281 
282                 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
283                                     (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
284         } else {
285                 out_be32(&lbc->fir,
286                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
287                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
288                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
289                          (FIR_OP_RBW << FIR_OP3_SHIFT));
290 
291                 if (oob)
292                         out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT);
293                 else
294                         out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
295         }
296 }
297 
298 /* cmdfunc send commands to the FCM */
299 static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
300                              int column, int page_addr)
301 {
302         struct nand_chip *chip = mtd_to_nand(mtd);
303         struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
304         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
305         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
306         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
307 
308         elbc_fcm_ctrl->use_mdr = 0;
309 
310         /* clear the read buffer */
311         elbc_fcm_ctrl->read_bytes = 0;
312         if (command != NAND_CMD_PAGEPROG)
313                 elbc_fcm_ctrl->index = 0;
314 
315         switch (command) {
316         /* READ0 and READ1 read the entire buffer to use hardware ECC. */
317         case NAND_CMD_READ1:
318                 column += 256;
319 
320         /* fall-through */
321         case NAND_CMD_READ0:
322                 dev_dbg(priv->dev,
323                         "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
324                         " 0x%x, column: 0x%x.\n", page_addr, column);
325 
326 
327                 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
328                 set_addr(mtd, 0, page_addr, 0);
329 
330                 elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
331                 elbc_fcm_ctrl->index += column;
332 
333                 fsl_elbc_do_read(chip, 0);
334                 fsl_elbc_run_command(mtd);
335                 return;
336 
337         /* READOOB reads only the OOB because no ECC is performed. */
338         case NAND_CMD_READOOB:
339                 dev_vdbg(priv->dev,
340                          "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
341                          " 0x%x, column: 0x%x.\n", page_addr, column);
342 
343                 out_be32(&lbc->fbcr, mtd->oobsize - column);
344                 set_addr(mtd, column, page_addr, 1);
345 
346                 elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
347 
348                 fsl_elbc_do_read(chip, 1);
349                 fsl_elbc_run_command(mtd);
350                 return;
351 
352         case NAND_CMD_READID:
353         case NAND_CMD_PARAM:
354                 dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD %x\n", command);
355 
356                 out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) |
357                                     (FIR_OP_UA  << FIR_OP1_SHIFT) |
358                                     (FIR_OP_RBW << FIR_OP2_SHIFT));
359                 out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT);
360                 /*
361                  * although currently it's 8 bytes for READID, we always read
362                  * the maximum 256 bytes(for PARAM)
363                  */
364                 out_be32(&lbc->fbcr, 256);
365                 elbc_fcm_ctrl->read_bytes = 256;
366                 elbc_fcm_ctrl->use_mdr = 1;
367                 elbc_fcm_ctrl->mdr = column;
368                 set_addr(mtd, 0, 0, 0);
369                 fsl_elbc_run_command(mtd);
370                 return;
371 
372         /* ERASE1 stores the block and page address */
373         case NAND_CMD_ERASE1:
374                 dev_vdbg(priv->dev,
375                          "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
376                          "page_addr: 0x%x.\n", page_addr);
377                 set_addr(mtd, 0, page_addr, 0);
378                 return;
379 
380         /* ERASE2 uses the block and page address from ERASE1 */
381         case NAND_CMD_ERASE2:
382                 dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
383 
384                 out_be32(&lbc->fir,
385                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
386                          (FIR_OP_PA  << FIR_OP1_SHIFT) |
387                          (FIR_OP_CM2 << FIR_OP2_SHIFT) |
388                          (FIR_OP_CW1 << FIR_OP3_SHIFT) |
389                          (FIR_OP_RS  << FIR_OP4_SHIFT));
390 
391                 out_be32(&lbc->fcr,
392                          (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
393                          (NAND_CMD_STATUS << FCR_CMD1_SHIFT) |
394                          (NAND_CMD_ERASE2 << FCR_CMD2_SHIFT));
395 
396                 out_be32(&lbc->fbcr, 0);
397                 elbc_fcm_ctrl->read_bytes = 0;
398                 elbc_fcm_ctrl->use_mdr = 1;
399 
400                 fsl_elbc_run_command(mtd);
401                 return;
402 
403         /* SEQIN sets up the addr buffer and all registers except the length */
404         case NAND_CMD_SEQIN: {
405                 __be32 fcr;
406                 dev_vdbg(priv->dev,
407                          "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
408                          "page_addr: 0x%x, column: 0x%x.\n",
409                          page_addr, column);
410 
411                 elbc_fcm_ctrl->column = column;
412                 elbc_fcm_ctrl->use_mdr = 1;
413 
414                 if (column >= mtd->writesize) {
415                         /* OOB area */
416                         column -= mtd->writesize;
417                         elbc_fcm_ctrl->oob = 1;
418                 } else {
419                         WARN_ON(column != 0);
420                         elbc_fcm_ctrl->oob = 0;
421                 }
422 
423                 fcr = (NAND_CMD_STATUS   << FCR_CMD1_SHIFT) |
424                       (NAND_CMD_SEQIN    << FCR_CMD2_SHIFT) |
425                       (NAND_CMD_PAGEPROG << FCR_CMD3_SHIFT);
426 
427                 if (priv->page_size) {
428                         out_be32(&lbc->fir,
429                                  (FIR_OP_CM2 << FIR_OP0_SHIFT) |
430                                  (FIR_OP_CA  << FIR_OP1_SHIFT) |
431                                  (FIR_OP_PA  << FIR_OP2_SHIFT) |
432                                  (FIR_OP_WB  << FIR_OP3_SHIFT) |
433                                  (FIR_OP_CM3 << FIR_OP4_SHIFT) |
434                                  (FIR_OP_CW1 << FIR_OP5_SHIFT) |
435                                  (FIR_OP_RS  << FIR_OP6_SHIFT));
436                 } else {
437                         out_be32(&lbc->fir,
438                                  (FIR_OP_CM0 << FIR_OP0_SHIFT) |
439                                  (FIR_OP_CM2 << FIR_OP1_SHIFT) |
440                                  (FIR_OP_CA  << FIR_OP2_SHIFT) |
441                                  (FIR_OP_PA  << FIR_OP3_SHIFT) |
442                                  (FIR_OP_WB  << FIR_OP4_SHIFT) |
443                                  (FIR_OP_CM3 << FIR_OP5_SHIFT) |
444                                  (FIR_OP_CW1 << FIR_OP6_SHIFT) |
445                                  (FIR_OP_RS  << FIR_OP7_SHIFT));
446 
447                         if (elbc_fcm_ctrl->oob)
448                                 /* OOB area --> READOOB */
449                                 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
450                         else
451                                 /* First 256 bytes --> READ0 */
452                                 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
453                 }
454 
455                 out_be32(&lbc->fcr, fcr);
456                 set_addr(mtd, column, page_addr, elbc_fcm_ctrl->oob);
457                 return;
458         }
459 
460         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
461         case NAND_CMD_PAGEPROG: {
462                 dev_vdbg(priv->dev,
463                          "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
464                          "writing %d bytes.\n", elbc_fcm_ctrl->index);
465 
466                 /* if the write did not start at 0 or is not a full page
467                  * then set the exact length, otherwise use a full page
468                  * write so the HW generates the ECC.
469                  */
470                 if (elbc_fcm_ctrl->oob || elbc_fcm_ctrl->column != 0 ||
471                     elbc_fcm_ctrl->index != mtd->writesize + mtd->oobsize)
472                         out_be32(&lbc->fbcr,
473                                 elbc_fcm_ctrl->index - elbc_fcm_ctrl->column);
474                 else
475                         out_be32(&lbc->fbcr, 0);
476 
477                 fsl_elbc_run_command(mtd);
478                 return;
479         }
480 
481         /* CMD_STATUS must read the status byte while CEB is active */
482         /* Note - it does not wait for the ready line */
483         case NAND_CMD_STATUS:
484                 out_be32(&lbc->fir,
485                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
486                          (FIR_OP_RBW << FIR_OP1_SHIFT));
487                 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
488                 out_be32(&lbc->fbcr, 1);
489                 set_addr(mtd, 0, 0, 0);
490                 elbc_fcm_ctrl->read_bytes = 1;
491 
492                 fsl_elbc_run_command(mtd);
493 
494                 /* The chip always seems to report that it is
495                  * write-protected, even when it is not.
496                  */
497                 setbits8(elbc_fcm_ctrl->addr, NAND_STATUS_WP);
498                 return;
499 
500         /* RESET without waiting for the ready line */
501         case NAND_CMD_RESET:
502                 dev_dbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
503                 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
504                 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
505                 fsl_elbc_run_command(mtd);
506                 return;
507 
508         default:
509                 dev_err(priv->dev,
510                         "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
511                         command);
512         }
513 }
514 
515 static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
516 {
517         /* The hardware does not seem to support multiple
518          * chips per bank.
519          */
520 }
521 
522 /*
523  * Write buf to the FCM Controller Data Buffer
524  */
525 static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
526 {
527         struct nand_chip *chip = mtd_to_nand(mtd);
528         struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
529         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
530         unsigned int bufsize = mtd->writesize + mtd->oobsize;
531 
532         if (len <= 0) {
533                 dev_err(priv->dev, "write_buf of %d bytes", len);
534                 elbc_fcm_ctrl->status = 0;
535                 return;
536         }
537 
538         if ((unsigned int)len > bufsize - elbc_fcm_ctrl->index) {
539                 dev_err(priv->dev,
540                         "write_buf beyond end of buffer "
541                         "(%d requested, %u available)\n",
542                         len, bufsize - elbc_fcm_ctrl->index);
543                 len = bufsize - elbc_fcm_ctrl->index;
544         }
545 
546         memcpy_toio(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], buf, len);
547         /*
548          * This is workaround for the weird elbc hangs during nand write,
549          * Scott Wood says: "...perhaps difference in how long it takes a
550          * write to make it through the localbus compared to a write to IMMR
551          * is causing problems, and sync isn't helping for some reason."
552          * Reading back the last byte helps though.
553          */
554         in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index] + len - 1);
555 
556         elbc_fcm_ctrl->index += len;
557 }
558 
559 /*
560  * read a byte from either the FCM hardware buffer if it has any data left
561  * otherwise issue a command to read a single byte.
562  */
563 static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
564 {
565         struct nand_chip *chip = mtd_to_nand(mtd);
566         struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
567         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
568 
569         /* If there are still bytes in the FCM, then use the next byte. */
570         if (elbc_fcm_ctrl->index < elbc_fcm_ctrl->read_bytes)
571                 return in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index++]);
572 
573         dev_err(priv->dev, "read_byte beyond end of buffer\n");
574         return ERR_BYTE;
575 }
576 
577 /*
578  * Read from the FCM Controller Data Buffer
579  */
580 static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
581 {
582         struct nand_chip *chip = mtd_to_nand(mtd);
583         struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
584         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
585         int avail;
586 
587         if (len < 0)
588                 return;
589 
590         avail = min((unsigned int)len,
591                         elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index);
592         memcpy_fromio(buf, &elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], avail);
593         elbc_fcm_ctrl->index += avail;
594 
595         if (len > avail)
596                 dev_err(priv->dev,
597                         "read_buf beyond end of buffer "
598                         "(%d requested, %d available)\n",
599                         len, avail);
600 }
601 
602 /* This function is called after Program and Erase Operations to
603  * check for success or failure.
604  */
605 static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
606 {
607         struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
608         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
609 
610         if (elbc_fcm_ctrl->status != LTESR_CC)
611                 return NAND_STATUS_FAIL;
612 
613         /* The chip always seems to report that it is
614          * write-protected, even when it is not.
615          */
616         return (elbc_fcm_ctrl->mdr & 0xff) | NAND_STATUS_WP;
617 }
618 
619 static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
620 {
621         struct nand_chip *chip = mtd_to_nand(mtd);
622         struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
623         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
624         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
625         unsigned int al;
626 
627         /* calculate FMR Address Length field */
628         al = 0;
629         if (chip->pagemask & 0xffff0000)
630                 al++;
631         if (chip->pagemask & 0xff000000)
632                 al++;
633 
634         priv->fmr |= al << FMR_AL_SHIFT;
635 
636         dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n",
637                 chip->numchips);
638         dev_dbg(priv->dev, "fsl_elbc_init: nand->chipsize = %lld\n",
639                 chip->chipsize);
640         dev_dbg(priv->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
641                 chip->pagemask);
642         dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_delay = %d\n",
643                 chip->chip_delay);
644         dev_dbg(priv->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
645                 chip->badblockpos);
646         dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
647                 chip->chip_shift);
648         dev_dbg(priv->dev, "fsl_elbc_init: nand->page_shift = %d\n",
649                 chip->page_shift);
650         dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
651                 chip->phys_erase_shift);
652         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
653                 chip->ecc.mode);
654         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
655                 chip->ecc.steps);
656         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
657                 chip->ecc.bytes);
658         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.total = %d\n",
659                 chip->ecc.total);
660         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.layout = %p\n",
661                 chip->ecc.layout);
662         dev_dbg(priv->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
663         dev_dbg(priv->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size);
664         dev_dbg(priv->dev, "fsl_elbc_init: mtd->erasesize = %d\n",
665                 mtd->erasesize);
666         dev_dbg(priv->dev, "fsl_elbc_init: mtd->writesize = %d\n",
667                 mtd->writesize);
668         dev_dbg(priv->dev, "fsl_elbc_init: mtd->oobsize = %d\n",
669                 mtd->oobsize);
670 
671         /* adjust Option Register and ECC to match Flash page size */
672         if (mtd->writesize == 512) {
673                 priv->page_size = 0;
674                 clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
675         } else if (mtd->writesize == 2048) {
676                 priv->page_size = 1;
677                 setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
678                 /* adjust ecc setup if needed */
679                 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
680                     BR_DECC_CHK_GEN) {
681                         chip->ecc.size = 512;
682                         chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
683                                            &fsl_elbc_oob_lp_eccm1 :
684                                            &fsl_elbc_oob_lp_eccm0;
685                 }
686         } else {
687                 dev_err(priv->dev,
688                         "fsl_elbc_init: page size %d is not supported\n",
689                         mtd->writesize);
690                 return -1;
691         }
692 
693         return 0;
694 }
695 
696 static int fsl_elbc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
697                               uint8_t *buf, int oob_required, int page)
698 {
699         struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
700         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
701         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
702 
703         fsl_elbc_read_buf(mtd, buf, mtd->writesize);
704         if (oob_required)
705                 fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
706 
707         if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
708                 mtd->ecc_stats.failed++;
709 
710         return elbc_fcm_ctrl->max_bitflips;
711 }
712 
713 /* ECC will be calculated automatically, and errors will be detected in
714  * waitfunc.
715  */
716 static int fsl_elbc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
717                                 const uint8_t *buf, int oob_required, int page)
718 {
719         fsl_elbc_write_buf(mtd, buf, mtd->writesize);
720         fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
721 
722         return 0;
723 }
724 
725 /* ECC will be calculated automatically, and errors will be detected in
726  * waitfunc.
727  */
728 static int fsl_elbc_write_subpage(struct mtd_info *mtd, struct nand_chip *chip,
729                                 uint32_t offset, uint32_t data_len,
730                                 const uint8_t *buf, int oob_required, int page)
731 {
732         fsl_elbc_write_buf(mtd, buf, mtd->writesize);
733         fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
734 
735         return 0;
736 }
737 
738 static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
739 {
740         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
741         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
742         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
743         struct nand_chip *chip = &priv->chip;
744         struct mtd_info *mtd = nand_to_mtd(chip);
745 
746         dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
747 
748         /* Fill in fsl_elbc_mtd structure */
749         mtd->dev.parent = priv->dev;
750         nand_set_flash_node(chip, priv->dev->of_node);
751 
752         /* set timeout to maximum */
753         priv->fmr = 15 << FMR_CWTO_SHIFT;
754         if (in_be32(&lbc->bank[priv->bank].or) & OR_FCM_PGS)
755                 priv->fmr |= FMR_ECCM;
756 
757         /* fill in nand_chip structure */
758         /* set up function call table */
759         chip->read_byte = fsl_elbc_read_byte;
760         chip->write_buf = fsl_elbc_write_buf;
761         chip->read_buf = fsl_elbc_read_buf;
762         chip->select_chip = fsl_elbc_select_chip;
763         chip->cmdfunc = fsl_elbc_cmdfunc;
764         chip->waitfunc = fsl_elbc_wait;
765 
766         chip->bbt_td = &bbt_main_descr;
767         chip->bbt_md = &bbt_mirror_descr;
768 
769         /* set up nand options */
770         chip->bbt_options = NAND_BBT_USE_FLASH;
771 
772         chip->controller = &elbc_fcm_ctrl->controller;
773         nand_set_controller_data(chip, priv);
774 
775         chip->ecc.read_page = fsl_elbc_read_page;
776         chip->ecc.write_page = fsl_elbc_write_page;
777         chip->ecc.write_subpage = fsl_elbc_write_subpage;
778 
779         /* If CS Base Register selects full hardware ECC then use it */
780         if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
781             BR_DECC_CHK_GEN) {
782                 chip->ecc.mode = NAND_ECC_HW;
783                 /* put in small page settings and adjust later if needed */
784                 chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
785                                 &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0;
786                 chip->ecc.size = 512;
787                 chip->ecc.bytes = 3;
788                 chip->ecc.strength = 1;
789         } else {
790                 /* otherwise fall back to default software ECC */
791                 chip->ecc.mode = NAND_ECC_SOFT;
792         }
793 
794         return 0;
795 }
796 
797 static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
798 {
799         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
800         struct mtd_info *mtd = nand_to_mtd(&priv->chip);
801 
802         nand_release(mtd);
803 
804         kfree(mtd->name);
805 
806         if (priv->vbase)
807                 iounmap(priv->vbase);
808 
809         elbc_fcm_ctrl->chips[priv->bank] = NULL;
810         kfree(priv);
811         return 0;
812 }
813 
814 static DEFINE_MUTEX(fsl_elbc_nand_mutex);
815 
816 static int fsl_elbc_nand_probe(struct platform_device *pdev)
817 {
818         struct fsl_lbc_regs __iomem *lbc;
819         struct fsl_elbc_mtd *priv;
820         struct resource res;
821         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl;
822         static const char *part_probe_types[]
823                 = { "cmdlinepart", "RedBoot", "ofpart", NULL };
824         int ret;
825         int bank;
826         struct device *dev;
827         struct device_node *node = pdev->dev.of_node;
828         struct mtd_info *mtd;
829 
830         if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
831                 return -ENODEV;
832         lbc = fsl_lbc_ctrl_dev->regs;
833         dev = fsl_lbc_ctrl_dev->dev;
834 
835         /* get, allocate and map the memory resource */
836         ret = of_address_to_resource(node, 0, &res);
837         if (ret) {
838                 dev_err(dev, "failed to get resource\n");
839                 return ret;
840         }
841 
842         /* find which chip select it is connected to */
843         for (bank = 0; bank < MAX_BANKS; bank++)
844                 if ((in_be32(&lbc->bank[bank].br) & BR_V) &&
845                     (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM &&
846                     (in_be32(&lbc->bank[bank].br) &
847                      in_be32(&lbc->bank[bank].or) & BR_BA)
848                      == fsl_lbc_addr(res.start))
849                         break;
850 
851         if (bank >= MAX_BANKS) {
852                 dev_err(dev, "address did not match any chip selects\n");
853                 return -ENODEV;
854         }
855 
856         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
857         if (!priv)
858                 return -ENOMEM;
859 
860         mutex_lock(&fsl_elbc_nand_mutex);
861         if (!fsl_lbc_ctrl_dev->nand) {
862                 elbc_fcm_ctrl = kzalloc(sizeof(*elbc_fcm_ctrl), GFP_KERNEL);
863                 if (!elbc_fcm_ctrl) {
864                         mutex_unlock(&fsl_elbc_nand_mutex);
865                         ret = -ENOMEM;
866                         goto err;
867                 }
868                 elbc_fcm_ctrl->counter++;
869 
870                 spin_lock_init(&elbc_fcm_ctrl->controller.lock);
871                 init_waitqueue_head(&elbc_fcm_ctrl->controller.wq);
872                 fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl;
873         } else {
874                 elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
875         }
876         mutex_unlock(&fsl_elbc_nand_mutex);
877 
878         elbc_fcm_ctrl->chips[bank] = priv;
879         priv->bank = bank;
880         priv->ctrl = fsl_lbc_ctrl_dev;
881         priv->dev = &pdev->dev;
882         dev_set_drvdata(priv->dev, priv);
883 
884         priv->vbase = ioremap(res.start, resource_size(&res));
885         if (!priv->vbase) {
886                 dev_err(dev, "failed to map chip region\n");
887                 ret = -ENOMEM;
888                 goto err;
889         }
890 
891         mtd = nand_to_mtd(&priv->chip);
892         mtd->name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start);
893         if (!nand_to_mtd(&priv->chip)->name) {
894                 ret = -ENOMEM;
895                 goto err;
896         }
897 
898         ret = fsl_elbc_chip_init(priv);
899         if (ret)
900                 goto err;
901 
902         ret = nand_scan_ident(mtd, 1, NULL);
903         if (ret)
904                 goto err;
905 
906         ret = fsl_elbc_chip_init_tail(mtd);
907         if (ret)
908                 goto err;
909 
910         ret = nand_scan_tail(mtd);
911         if (ret)
912                 goto err;
913 
914         /* First look for RedBoot table or partitions on the command
915          * line, these take precedence over device tree information */
916         mtd_device_parse_register(mtd, part_probe_types, NULL,
917                                   NULL, 0);
918 
919         printk(KERN_INFO "eLBC NAND device at 0x%llx, bank %d\n",
920                (unsigned long long)res.start, priv->bank);
921         return 0;
922 
923 err:
924         fsl_elbc_chip_remove(priv);
925         return ret;
926 }
927 
928 static int fsl_elbc_nand_remove(struct platform_device *pdev)
929 {
930         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
931         struct fsl_elbc_mtd *priv = dev_get_drvdata(&pdev->dev);
932 
933         fsl_elbc_chip_remove(priv);
934 
935         mutex_lock(&fsl_elbc_nand_mutex);
936         elbc_fcm_ctrl->counter--;
937         if (!elbc_fcm_ctrl->counter) {
938                 fsl_lbc_ctrl_dev->nand = NULL;
939                 kfree(elbc_fcm_ctrl);
940         }
941         mutex_unlock(&fsl_elbc_nand_mutex);
942 
943         return 0;
944 
945 }
946 
947 static const struct of_device_id fsl_elbc_nand_match[] = {
948         { .compatible = "fsl,elbc-fcm-nand", },
949         {}
950 };
951 MODULE_DEVICE_TABLE(of, fsl_elbc_nand_match);
952 
953 static struct platform_driver fsl_elbc_nand_driver = {
954         .driver = {
955                 .name = "fsl,elbc-fcm-nand",
956                 .of_match_table = fsl_elbc_nand_match,
957         },
958         .probe = fsl_elbc_nand_probe,
959         .remove = fsl_elbc_nand_remove,
960 };
961 
962 module_platform_driver(fsl_elbc_nand_driver);
963 
964 MODULE_LICENSE("GPL");
965 MODULE_AUTHOR("Freescale");
966 MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver");
967 

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