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Linux/drivers/mtd/nand/denali.c

  1 /*
  2  * NAND Flash Controller Device Driver
  3  * Copyright © 2009-2010, Intel Corporation and its suppliers.
  4  *
  5  * This program is free software; you can redistribute it and/or modify it
  6  * under the terms and conditions of the GNU General Public License,
  7  * version 2, as published by the Free Software Foundation.
  8  *
  9  * This program is distributed in the hope it will be useful, but WITHOUT
 10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 12  * more details.
 13  *
 14  * You should have received a copy of the GNU General Public License along with
 15  * this program; if not, write to the Free Software Foundation, Inc.,
 16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 17  *
 18  */
 19 #include <linux/interrupt.h>
 20 #include <linux/delay.h>
 21 #include <linux/dma-mapping.h>
 22 #include <linux/wait.h>
 23 #include <linux/mutex.h>
 24 #include <linux/slab.h>
 25 #include <linux/mtd/mtd.h>
 26 #include <linux/module.h>
 27 
 28 #include "denali.h"
 29 
 30 MODULE_LICENSE("GPL");
 31 
 32 /*
 33  * We define a module parameter that allows the user to override
 34  * the hardware and decide what timing mode should be used.
 35  */
 36 #define NAND_DEFAULT_TIMINGS    -1
 37 
 38 static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
 39 module_param(onfi_timing_mode, int, S_IRUGO);
 40 MODULE_PARM_DESC(onfi_timing_mode,
 41            "Overrides default ONFI setting. -1 indicates use default timings");
 42 
 43 #define DENALI_NAND_NAME    "denali-nand"
 44 
 45 /*
 46  * We define a macro here that combines all interrupts this driver uses into
 47  * a single constant value, for convenience.
 48  */
 49 #define DENALI_IRQ_ALL  (INTR_STATUS__DMA_CMD_COMP | \
 50                         INTR_STATUS__ECC_TRANSACTION_DONE | \
 51                         INTR_STATUS__ECC_ERR | \
 52                         INTR_STATUS__PROGRAM_FAIL | \
 53                         INTR_STATUS__LOAD_COMP | \
 54                         INTR_STATUS__PROGRAM_COMP | \
 55                         INTR_STATUS__TIME_OUT | \
 56                         INTR_STATUS__ERASE_FAIL | \
 57                         INTR_STATUS__RST_COMP | \
 58                         INTR_STATUS__ERASE_COMP)
 59 
 60 /*
 61  * indicates whether or not the internal value for the flash bank is
 62  * valid or not
 63  */
 64 #define CHIP_SELECT_INVALID     -1
 65 
 66 #define SUPPORT_8BITECC         1
 67 
 68 /*
 69  * This macro divides two integers and rounds fractional values up
 70  * to the nearest integer value.
 71  */
 72 #define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
 73 
 74 /*
 75  * this macro allows us to convert from an MTD structure to our own
 76  * device context (denali) structure.
 77  */
 78 static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
 79 {
 80         return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);
 81 }
 82 
 83 /*
 84  * These constants are defined by the driver to enable common driver
 85  * configuration options.
 86  */
 87 #define SPARE_ACCESS            0x41
 88 #define MAIN_ACCESS             0x42
 89 #define MAIN_SPARE_ACCESS       0x43
 90 #define PIPELINE_ACCESS         0x2000
 91 
 92 #define DENALI_READ     0
 93 #define DENALI_WRITE    0x100
 94 
 95 /* types of device accesses. We can issue commands and get status */
 96 #define COMMAND_CYCLE   0
 97 #define ADDR_CYCLE      1
 98 #define STATUS_CYCLE    2
 99 
100 /*
101  * this is a helper macro that allows us to
102  * format the bank into the proper bits for the controller
103  */
104 #define BANK(x) ((x) << 24)
105 
106 /* forward declarations */
107 static void clear_interrupts(struct denali_nand_info *denali);
108 static uint32_t wait_for_irq(struct denali_nand_info *denali,
109                                                         uint32_t irq_mask);
110 static void denali_irq_enable(struct denali_nand_info *denali,
111                                                         uint32_t int_mask);
112 static uint32_t read_interrupt_status(struct denali_nand_info *denali);
113 
114 /*
115  * Certain operations for the denali NAND controller use an indexed mode to
116  * read/write data. The operation is performed by writing the address value
117  * of the command to the device memory followed by the data. This function
118  * abstracts this common operation.
119  */
120 static void index_addr(struct denali_nand_info *denali,
121                                 uint32_t address, uint32_t data)
122 {
123         iowrite32(address, denali->flash_mem);
124         iowrite32(data, denali->flash_mem + 0x10);
125 }
126 
127 /* Perform an indexed read of the device */
128 static void index_addr_read_data(struct denali_nand_info *denali,
129                                  uint32_t address, uint32_t *pdata)
130 {
131         iowrite32(address, denali->flash_mem);
132         *pdata = ioread32(denali->flash_mem + 0x10);
133 }
134 
135 /*
136  * We need to buffer some data for some of the NAND core routines.
137  * The operations manage buffering that data.
138  */
139 static void reset_buf(struct denali_nand_info *denali)
140 {
141         denali->buf.head = denali->buf.tail = 0;
142 }
143 
144 static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)
145 {
146         denali->buf.buf[denali->buf.tail++] = byte;
147 }
148 
149 /* reads the status of the device */
150 static void read_status(struct denali_nand_info *denali)
151 {
152         uint32_t cmd;
153 
154         /* initialize the data buffer to store status */
155         reset_buf(denali);
156 
157         cmd = ioread32(denali->flash_reg + WRITE_PROTECT);
158         if (cmd)
159                 write_byte_to_buf(denali, NAND_STATUS_WP);
160         else
161                 write_byte_to_buf(denali, 0);
162 }
163 
164 /* resets a specific device connected to the core */
165 static void reset_bank(struct denali_nand_info *denali)
166 {
167         uint32_t irq_status;
168         uint32_t irq_mask = INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT;
169 
170         clear_interrupts(denali);
171 
172         iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET);
173 
174         irq_status = wait_for_irq(denali, irq_mask);
175 
176         if (irq_status & INTR_STATUS__TIME_OUT)
177                 dev_err(denali->dev, "reset bank failed.\n");
178 }
179 
180 /* Reset the flash controller */
181 static uint16_t denali_nand_reset(struct denali_nand_info *denali)
182 {
183         int i;
184 
185         dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
186                 __FILE__, __LINE__, __func__);
187 
188         for (i = 0; i < denali->max_banks; i++)
189                 iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
190                 denali->flash_reg + INTR_STATUS(i));
191 
192         for (i = 0; i < denali->max_banks; i++) {
193                 iowrite32(1 << i, denali->flash_reg + DEVICE_RESET);
194                 while (!(ioread32(denali->flash_reg + INTR_STATUS(i)) &
195                         (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT)))
196                         cpu_relax();
197                 if (ioread32(denali->flash_reg + INTR_STATUS(i)) &
198                         INTR_STATUS__TIME_OUT)
199                         dev_dbg(denali->dev,
200                         "NAND Reset operation timed out on bank %d\n", i);
201         }
202 
203         for (i = 0; i < denali->max_banks; i++)
204                 iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
205                           denali->flash_reg + INTR_STATUS(i));
206 
207         return PASS;
208 }
209 
210 /*
211  * this routine calculates the ONFI timing values for a given mode and
212  * programs the clocking register accordingly. The mode is determined by
213  * the get_onfi_nand_para routine.
214  */
215 static void nand_onfi_timing_set(struct denali_nand_info *denali,
216                                                                 uint16_t mode)
217 {
218         uint16_t Trea[6] = {40, 30, 25, 20, 20, 16};
219         uint16_t Trp[6] = {50, 25, 17, 15, 12, 10};
220         uint16_t Treh[6] = {30, 15, 15, 10, 10, 7};
221         uint16_t Trc[6] = {100, 50, 35, 30, 25, 20};
222         uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15};
223         uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5};
224         uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25};
225         uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70};
226         uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100};
227         uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100};
228         uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60};
229         uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15};
230 
231         uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid;
232         uint16_t dv_window = 0;
233         uint16_t en_lo, en_hi;
234         uint16_t acc_clks;
235         uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
236 
237         dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
238                 __FILE__, __LINE__, __func__);
239 
240         en_lo = CEIL_DIV(Trp[mode], CLK_X);
241         en_hi = CEIL_DIV(Treh[mode], CLK_X);
242 #if ONFI_BLOOM_TIME
243         if ((en_hi * CLK_X) < (Treh[mode] + 2))
244                 en_hi++;
245 #endif
246 
247         if ((en_lo + en_hi) * CLK_X < Trc[mode])
248                 en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X);
249 
250         if ((en_lo + en_hi) < CLK_MULTI)
251                 en_lo += CLK_MULTI - en_lo - en_hi;
252 
253         while (dv_window < 8) {
254                 data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode];
255 
256                 data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode];
257 
258                 data_invalid = data_invalid_rhoh < data_invalid_rloh ?
259                                         data_invalid_rhoh : data_invalid_rloh;
260 
261                 dv_window = data_invalid - Trea[mode];
262 
263                 if (dv_window < 8)
264                         en_lo++;
265         }
266 
267         acc_clks = CEIL_DIV(Trea[mode], CLK_X);
268 
269         while (acc_clks * CLK_X - Trea[mode] < 3)
270                 acc_clks++;
271 
272         if (data_invalid - acc_clks * CLK_X < 2)
273                 dev_warn(denali->dev, "%s, Line %d: Warning!\n",
274                          __FILE__, __LINE__);
275 
276         addr_2_data = CEIL_DIV(Tadl[mode], CLK_X);
277         re_2_we = CEIL_DIV(Trhw[mode], CLK_X);
278         re_2_re = CEIL_DIV(Trhz[mode], CLK_X);
279         we_2_re = CEIL_DIV(Twhr[mode], CLK_X);
280         cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X);
281         if (cs_cnt == 0)
282                 cs_cnt = 1;
283 
284         if (Tcea[mode]) {
285                 while (cs_cnt * CLK_X + Trea[mode] < Tcea[mode])
286                         cs_cnt++;
287         }
288 
289 #if MODE5_WORKAROUND
290         if (mode == 5)
291                 acc_clks = 5;
292 #endif
293 
294         /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */
295         if (ioread32(denali->flash_reg + MANUFACTURER_ID) == 0 &&
296                 ioread32(denali->flash_reg + DEVICE_ID) == 0x88)
297                 acc_clks = 6;
298 
299         iowrite32(acc_clks, denali->flash_reg + ACC_CLKS);
300         iowrite32(re_2_we, denali->flash_reg + RE_2_WE);
301         iowrite32(re_2_re, denali->flash_reg + RE_2_RE);
302         iowrite32(we_2_re, denali->flash_reg + WE_2_RE);
303         iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA);
304         iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
305         iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
306         iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
307 }
308 
309 /* queries the NAND device to see what ONFI modes it supports. */
310 static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
311 {
312         int i;
313 
314         /*
315          * we needn't to do a reset here because driver has already
316          * reset all the banks before
317          */
318         if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
319                 ONFI_TIMING_MODE__VALUE))
320                 return FAIL;
321 
322         for (i = 5; i > 0; i--) {
323                 if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
324                         (0x01 << i))
325                         break;
326         }
327 
328         nand_onfi_timing_set(denali, i);
329 
330         /*
331          * By now, all the ONFI devices we know support the page cache
332          * rw feature. So here we enable the pipeline_rw_ahead feature
333          */
334         /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */
335         /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE);  */
336 
337         return PASS;
338 }
339 
340 static void get_samsung_nand_para(struct denali_nand_info *denali,
341                                                         uint8_t device_id)
342 {
343         if (device_id == 0xd3) { /* Samsung K9WAG08U1A */
344                 /* Set timing register values according to datasheet */
345                 iowrite32(5, denali->flash_reg + ACC_CLKS);
346                 iowrite32(20, denali->flash_reg + RE_2_WE);
347                 iowrite32(12, denali->flash_reg + WE_2_RE);
348                 iowrite32(14, denali->flash_reg + ADDR_2_DATA);
349                 iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT);
350                 iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT);
351                 iowrite32(2, denali->flash_reg + CS_SETUP_CNT);
352         }
353 }
354 
355 static void get_toshiba_nand_para(struct denali_nand_info *denali)
356 {
357         uint32_t tmp;
358 
359         /*
360          * Workaround to fix a controller bug which reports a wrong
361          * spare area size for some kind of Toshiba NAND device
362          */
363         if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
364                 (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
365                 iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
366                 tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) *
367                         ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
368                 iowrite32(tmp,
369                                 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
370 #if SUPPORT_15BITECC
371                 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
372 #elif SUPPORT_8BITECC
373                 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
374 #endif
375         }
376 }
377 
378 static void get_hynix_nand_para(struct denali_nand_info *denali,
379                                                         uint8_t device_id)
380 {
381         uint32_t main_size, spare_size;
382 
383         switch (device_id) {
384         case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
385         case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
386                 iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK);
387                 iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
388                 iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
389                 main_size = 4096 *
390                         ioread32(denali->flash_reg + DEVICES_CONNECTED);
391                 spare_size = 224 *
392                         ioread32(denali->flash_reg + DEVICES_CONNECTED);
393                 iowrite32(main_size,
394                                 denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
395                 iowrite32(spare_size,
396                                 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
397                 iowrite32(0, denali->flash_reg + DEVICE_WIDTH);
398 #if SUPPORT_15BITECC
399                 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
400 #elif SUPPORT_8BITECC
401                 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
402 #endif
403                 break;
404         default:
405                 dev_warn(denali->dev,
406                          "Spectra: Unknown Hynix NAND (Device ID: 0x%x).\n"
407                          "Will use default parameter values instead.\n",
408                          device_id);
409         }
410 }
411 
412 /*
413  * determines how many NAND chips are connected to the controller. Note for
414  * Intel CE4100 devices we don't support more than one device.
415  */
416 static void find_valid_banks(struct denali_nand_info *denali)
417 {
418         uint32_t id[denali->max_banks];
419         int i;
420 
421         denali->total_used_banks = 1;
422         for (i = 0; i < denali->max_banks; i++) {
423                 index_addr(denali, MODE_11 | (i << 24) | 0, 0x90);
424                 index_addr(denali, MODE_11 | (i << 24) | 1, 0);
425                 index_addr_read_data(denali, MODE_11 | (i << 24) | 2, &id[i]);
426 
427                 dev_dbg(denali->dev,
428                         "Return 1st ID for bank[%d]: %x\n", i, id[i]);
429 
430                 if (i == 0) {
431                         if (!(id[i] & 0x0ff))
432                                 break; /* WTF? */
433                 } else {
434                         if ((id[i] & 0x0ff) == (id[0] & 0x0ff))
435                                 denali->total_used_banks++;
436                         else
437                                 break;
438                 }
439         }
440 
441         if (denali->platform == INTEL_CE4100) {
442                 /*
443                  * Platform limitations of the CE4100 device limit
444                  * users to a single chip solution for NAND.
445                  * Multichip support is not enabled.
446                  */
447                 if (denali->total_used_banks != 1) {
448                         dev_err(denali->dev,
449                                 "Sorry, Intel CE4100 only supports a single NAND device.\n");
450                         BUG();
451                 }
452         }
453         dev_dbg(denali->dev,
454                 "denali->total_used_banks: %d\n", denali->total_used_banks);
455 }
456 
457 /*
458  * Use the configuration feature register to determine the maximum number of
459  * banks that the hardware supports.
460  */
461 static void detect_max_banks(struct denali_nand_info *denali)
462 {
463         uint32_t features = ioread32(denali->flash_reg + FEATURES);
464         /*
465          * Read the revision register, so we can calculate the max_banks
466          * properly: the encoding changed from rev 5.0 to 5.1
467          */
468         u32 revision = MAKE_COMPARABLE_REVISION(
469                                 ioread32(denali->flash_reg + REVISION));
470 
471         if (revision < REVISION_5_1)
472                 denali->max_banks = 2 << (features & FEATURES__N_BANKS);
473         else
474                 denali->max_banks = 1 << (features & FEATURES__N_BANKS);
475 }
476 
477 static void detect_partition_feature(struct denali_nand_info *denali)
478 {
479         /*
480          * For MRST platform, denali->fwblks represent the
481          * number of blocks firmware is taken,
482          * FW is in protect partition and MTD driver has no
483          * permission to access it. So let driver know how many
484          * blocks it can't touch.
485          */
486         if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
487                 if ((ioread32(denali->flash_reg + PERM_SRC_ID(1)) &
488                         PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) {
489                         denali->fwblks =
490                             ((ioread32(denali->flash_reg + MIN_MAX_BANK(1)) &
491                               MIN_MAX_BANK__MIN_VALUE) *
492                              denali->blksperchip)
493                             +
494                             (ioread32(denali->flash_reg + MIN_BLK_ADDR(1)) &
495                             MIN_BLK_ADDR__VALUE);
496                 } else {
497                         denali->fwblks = SPECTRA_START_BLOCK;
498                 }
499         } else {
500                 denali->fwblks = SPECTRA_START_BLOCK;
501         }
502 }
503 
504 static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
505 {
506         uint16_t status = PASS;
507         uint32_t id_bytes[8], addr;
508         uint8_t maf_id, device_id;
509         int i;
510 
511         dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
512                         __FILE__, __LINE__, __func__);
513 
514         /*
515          * Use read id method to get device ID and other params.
516          * For some NAND chips, controller can't report the correct
517          * device ID by reading from DEVICE_ID register
518          */
519         addr = MODE_11 | BANK(denali->flash_bank);
520         index_addr(denali, addr | 0, 0x90);
521         index_addr(denali, addr | 1, 0);
522         for (i = 0; i < 8; i++)
523                 index_addr_read_data(denali, addr | 2, &id_bytes[i]);
524         maf_id = id_bytes[0];
525         device_id = id_bytes[1];
526 
527         if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
528                 ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */
529                 if (FAIL == get_onfi_nand_para(denali))
530                         return FAIL;
531         } else if (maf_id == 0xEC) { /* Samsung NAND */
532                 get_samsung_nand_para(denali, device_id);
533         } else if (maf_id == 0x98) { /* Toshiba NAND */
534                 get_toshiba_nand_para(denali);
535         } else if (maf_id == 0xAD) { /* Hynix NAND */
536                 get_hynix_nand_para(denali, device_id);
537         }
538 
539         dev_info(denali->dev,
540                         "Dump timing register values:\n"
541                         "acc_clks: %d, re_2_we: %d, re_2_re: %d\n"
542                         "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n"
543                         "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
544                         ioread32(denali->flash_reg + ACC_CLKS),
545                         ioread32(denali->flash_reg + RE_2_WE),
546                         ioread32(denali->flash_reg + RE_2_RE),
547                         ioread32(denali->flash_reg + WE_2_RE),
548                         ioread32(denali->flash_reg + ADDR_2_DATA),
549                         ioread32(denali->flash_reg + RDWR_EN_LO_CNT),
550                         ioread32(denali->flash_reg + RDWR_EN_HI_CNT),
551                         ioread32(denali->flash_reg + CS_SETUP_CNT));
552 
553         find_valid_banks(denali);
554 
555         detect_partition_feature(denali);
556 
557         /*
558          * If the user specified to override the default timings
559          * with a specific ONFI mode, we apply those changes here.
560          */
561         if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
562                 nand_onfi_timing_set(denali, onfi_timing_mode);
563 
564         return status;
565 }
566 
567 static void denali_set_intr_modes(struct denali_nand_info *denali,
568                                         uint16_t INT_ENABLE)
569 {
570         dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
571                 __FILE__, __LINE__, __func__);
572 
573         if (INT_ENABLE)
574                 iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE);
575         else
576                 iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE);
577 }
578 
579 /*
580  * validation function to verify that the controlling software is making
581  * a valid request
582  */
583 static inline bool is_flash_bank_valid(int flash_bank)
584 {
585         return flash_bank >= 0 && flash_bank < 4;
586 }
587 
588 static void denali_irq_init(struct denali_nand_info *denali)
589 {
590         uint32_t int_mask;
591         int i;
592 
593         /* Disable global interrupts */
594         denali_set_intr_modes(denali, false);
595 
596         int_mask = DENALI_IRQ_ALL;
597 
598         /* Clear all status bits */
599         for (i = 0; i < denali->max_banks; ++i)
600                 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i));
601 
602         denali_irq_enable(denali, int_mask);
603 }
604 
605 static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali)
606 {
607         denali_set_intr_modes(denali, false);
608         free_irq(irqnum, denali);
609 }
610 
611 static void denali_irq_enable(struct denali_nand_info *denali,
612                                                         uint32_t int_mask)
613 {
614         int i;
615 
616         for (i = 0; i < denali->max_banks; ++i)
617                 iowrite32(int_mask, denali->flash_reg + INTR_EN(i));
618 }
619 
620 /*
621  * This function only returns when an interrupt that this driver cares about
622  * occurs. This is to reduce the overhead of servicing interrupts
623  */
624 static inline uint32_t denali_irq_detected(struct denali_nand_info *denali)
625 {
626         return read_interrupt_status(denali) & DENALI_IRQ_ALL;
627 }
628 
629 /* Interrupts are cleared by writing a 1 to the appropriate status bit */
630 static inline void clear_interrupt(struct denali_nand_info *denali,
631                                                         uint32_t irq_mask)
632 {
633         uint32_t intr_status_reg;
634 
635         intr_status_reg = INTR_STATUS(denali->flash_bank);
636 
637         iowrite32(irq_mask, denali->flash_reg + intr_status_reg);
638 }
639 
640 static void clear_interrupts(struct denali_nand_info *denali)
641 {
642         uint32_t status;
643 
644         spin_lock_irq(&denali->irq_lock);
645 
646         status = read_interrupt_status(denali);
647         clear_interrupt(denali, status);
648 
649         denali->irq_status = 0x0;
650         spin_unlock_irq(&denali->irq_lock);
651 }
652 
653 static uint32_t read_interrupt_status(struct denali_nand_info *denali)
654 {
655         uint32_t intr_status_reg;
656 
657         intr_status_reg = INTR_STATUS(denali->flash_bank);
658 
659         return ioread32(denali->flash_reg + intr_status_reg);
660 }
661 
662 /*
663  * This is the interrupt service routine. It handles all interrupts
664  * sent to this device. Note that on CE4100, this is a shared interrupt.
665  */
666 static irqreturn_t denali_isr(int irq, void *dev_id)
667 {
668         struct denali_nand_info *denali = dev_id;
669         uint32_t irq_status;
670         irqreturn_t result = IRQ_NONE;
671 
672         spin_lock(&denali->irq_lock);
673 
674         /* check to see if a valid NAND chip has been selected. */
675         if (is_flash_bank_valid(denali->flash_bank)) {
676                 /*
677                  * check to see if controller generated the interrupt,
678                  * since this is a shared interrupt
679                  */
680                 irq_status = denali_irq_detected(denali);
681                 if (irq_status != 0) {
682                         /* handle interrupt */
683                         /* first acknowledge it */
684                         clear_interrupt(denali, irq_status);
685                         /*
686                          * store the status in the device context for someone
687                          * to read
688                          */
689                         denali->irq_status |= irq_status;
690                         /* notify anyone who cares that it happened */
691                         complete(&denali->complete);
692                         /* tell the OS that we've handled this */
693                         result = IRQ_HANDLED;
694                 }
695         }
696         spin_unlock(&denali->irq_lock);
697         return result;
698 }
699 #define BANK(x) ((x) << 24)
700 
701 static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
702 {
703         unsigned long comp_res;
704         uint32_t intr_status;
705         unsigned long timeout = msecs_to_jiffies(1000);
706 
707         do {
708                 comp_res =
709                         wait_for_completion_timeout(&denali->complete, timeout);
710                 spin_lock_irq(&denali->irq_lock);
711                 intr_status = denali->irq_status;
712 
713                 if (intr_status & irq_mask) {
714                         denali->irq_status &= ~irq_mask;
715                         spin_unlock_irq(&denali->irq_lock);
716                         /* our interrupt was detected */
717                         break;
718                 }
719 
720                 /*
721                  * these are not the interrupts you are looking for -
722                  * need to wait again
723                  */
724                 spin_unlock_irq(&denali->irq_lock);
725         } while (comp_res != 0);
726 
727         if (comp_res == 0) {
728                 /* timeout */
729                 pr_err("timeout occurred, status = 0x%x, mask = 0x%x\n",
730                                 intr_status, irq_mask);
731 
732                 intr_status = 0;
733         }
734         return intr_status;
735 }
736 
737 /*
738  * This helper function setups the registers for ECC and whether or not
739  * the spare area will be transferred.
740  */
741 static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
742                                 bool transfer_spare)
743 {
744         int ecc_en_flag, transfer_spare_flag;
745 
746         /* set ECC, transfer spare bits if needed */
747         ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;
748         transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;
749 
750         /* Enable spare area/ECC per user's request. */
751         iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
752         iowrite32(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG);
753 }
754 
755 /*
756  * sends a pipeline command operation to the controller. See the Denali NAND
757  * controller's user guide for more information (section 4.2.3.6).
758  */
759 static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
760                                     bool ecc_en, bool transfer_spare,
761                                     int access_type, int op)
762 {
763         int status = PASS;
764         uint32_t page_count = 1;
765         uint32_t addr, cmd, irq_status, irq_mask;
766 
767         if (op == DENALI_READ)
768                 irq_mask = INTR_STATUS__LOAD_COMP;
769         else if (op == DENALI_WRITE)
770                 irq_mask = 0;
771         else
772                 BUG();
773 
774         setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
775 
776         clear_interrupts(denali);
777 
778         addr = BANK(denali->flash_bank) | denali->page;
779 
780         if (op == DENALI_WRITE && access_type != SPARE_ACCESS) {
781                 cmd = MODE_01 | addr;
782                 iowrite32(cmd, denali->flash_mem);
783         } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) {
784                 /* read spare area */
785                 cmd = MODE_10 | addr;
786                 index_addr(denali, cmd, access_type);
787 
788                 cmd = MODE_01 | addr;
789                 iowrite32(cmd, denali->flash_mem);
790         } else if (op == DENALI_READ) {
791                 /* setup page read request for access type */
792                 cmd = MODE_10 | addr;
793                 index_addr(denali, cmd, access_type);
794 
795                 /*
796                  * page 33 of the NAND controller spec indicates we should not
797                  * use the pipeline commands in Spare area only mode.
798                  * So we don't.
799                  */
800                 if (access_type == SPARE_ACCESS) {
801                         cmd = MODE_01 | addr;
802                         iowrite32(cmd, denali->flash_mem);
803                 } else {
804                         index_addr(denali, cmd,
805                                         PIPELINE_ACCESS | op | page_count);
806 
807                         /*
808                          * wait for command to be accepted
809                          * can always use status0 bit as the
810                          * mask is identical for each bank.
811                          */
812                         irq_status = wait_for_irq(denali, irq_mask);
813 
814                         if (irq_status == 0) {
815                                 dev_err(denali->dev,
816                                         "cmd, page, addr on timeout (0x%x, 0x%x, 0x%x)\n",
817                                         cmd, denali->page, addr);
818                                 status = FAIL;
819                         } else {
820                                 cmd = MODE_01 | addr;
821                                 iowrite32(cmd, denali->flash_mem);
822                         }
823                 }
824         }
825         return status;
826 }
827 
828 /* helper function that simply writes a buffer to the flash */
829 static int write_data_to_flash_mem(struct denali_nand_info *denali,
830                                    const uint8_t *buf, int len)
831 {
832         uint32_t *buf32;
833         int i;
834 
835         /*
836          * verify that the len is a multiple of 4.
837          * see comment in read_data_from_flash_mem()
838          */
839         BUG_ON((len % 4) != 0);
840 
841         /* write the data to the flash memory */
842         buf32 = (uint32_t *)buf;
843         for (i = 0; i < len / 4; i++)
844                 iowrite32(*buf32++, denali->flash_mem + 0x10);
845         return i * 4; /* intent is to return the number of bytes read */
846 }
847 
848 /* helper function that simply reads a buffer from the flash */
849 static int read_data_from_flash_mem(struct denali_nand_info *denali,
850                                     uint8_t *buf, int len)
851 {
852         uint32_t *buf32;
853         int i;
854 
855         /*
856          * we assume that len will be a multiple of 4, if not it would be nice
857          * to know about it ASAP rather than have random failures...
858          * This assumption is based on the fact that this function is designed
859          * to be used to read flash pages, which are typically multiples of 4.
860          */
861         BUG_ON((len % 4) != 0);
862 
863         /* transfer the data from the flash */
864         buf32 = (uint32_t *)buf;
865         for (i = 0; i < len / 4; i++)
866                 *buf32++ = ioread32(denali->flash_mem + 0x10);
867         return i * 4; /* intent is to return the number of bytes read */
868 }
869 
870 /* writes OOB data to the device */
871 static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
872 {
873         struct denali_nand_info *denali = mtd_to_denali(mtd);
874         uint32_t irq_status;
875         uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP |
876                                                 INTR_STATUS__PROGRAM_FAIL;
877         int status = 0;
878 
879         denali->page = page;
880 
881         if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS,
882                                                         DENALI_WRITE) == PASS) {
883                 write_data_to_flash_mem(denali, buf, mtd->oobsize);
884 
885                 /* wait for operation to complete */
886                 irq_status = wait_for_irq(denali, irq_mask);
887 
888                 if (irq_status == 0) {
889                         dev_err(denali->dev, "OOB write failed\n");
890                         status = -EIO;
891                 }
892         } else {
893                 dev_err(denali->dev, "unable to send pipeline command\n");
894                 status = -EIO;
895         }
896         return status;
897 }
898 
899 /* reads OOB data from the device */
900 static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
901 {
902         struct denali_nand_info *denali = mtd_to_denali(mtd);
903         uint32_t irq_mask = INTR_STATUS__LOAD_COMP;
904         uint32_t irq_status, addr, cmd;
905 
906         denali->page = page;
907 
908         if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
909                                                         DENALI_READ) == PASS) {
910                 read_data_from_flash_mem(denali, buf, mtd->oobsize);
911 
912                 /*
913                  * wait for command to be accepted
914                  * can always use status0 bit as the
915                  * mask is identical for each bank.
916                  */
917                 irq_status = wait_for_irq(denali, irq_mask);
918 
919                 if (irq_status == 0)
920                         dev_err(denali->dev, "page on OOB timeout %d\n",
921                                         denali->page);
922 
923                 /*
924                  * We set the device back to MAIN_ACCESS here as I observed
925                  * instability with the controller if you do a block erase
926                  * and the last transaction was a SPARE_ACCESS. Block erase
927                  * is reliable (according to the MTD test infrastructure)
928                  * if you are in MAIN_ACCESS.
929                  */
930                 addr = BANK(denali->flash_bank) | denali->page;
931                 cmd = MODE_10 | addr;
932                 index_addr(denali, cmd, MAIN_ACCESS);
933         }
934 }
935 
936 /*
937  * this function examines buffers to see if they contain data that
938  * indicate that the buffer is part of an erased region of flash.
939  */
940 static bool is_erased(uint8_t *buf, int len)
941 {
942         int i;
943 
944         for (i = 0; i < len; i++)
945                 if (buf[i] != 0xFF)
946                         return false;
947         return true;
948 }
949 #define ECC_SECTOR_SIZE 512
950 
951 #define ECC_SECTOR(x)   (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12)
952 #define ECC_BYTE(x)     (((x) & ECC_ERROR_ADDRESS__OFFSET))
953 #define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK)
954 #define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO__ERROR_TYPE))
955 #define ECC_ERR_DEVICE(x)       (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8)
956 #define ECC_LAST_ERR(x)         ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO)
957 
958 static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
959                        uint32_t irq_status, unsigned int *max_bitflips)
960 {
961         bool check_erased_page = false;
962         unsigned int bitflips = 0;
963 
964         if (irq_status & INTR_STATUS__ECC_ERR) {
965                 /* read the ECC errors. we'll ignore them for now */
966                 uint32_t err_address, err_correction_info, err_byte,
967                          err_sector, err_device, err_correction_value;
968                 denali_set_intr_modes(denali, false);
969 
970                 do {
971                         err_address = ioread32(denali->flash_reg +
972                                                 ECC_ERROR_ADDRESS);
973                         err_sector = ECC_SECTOR(err_address);
974                         err_byte = ECC_BYTE(err_address);
975 
976                         err_correction_info = ioread32(denali->flash_reg +
977                                                 ERR_CORRECTION_INFO);
978                         err_correction_value =
979                                 ECC_CORRECTION_VALUE(err_correction_info);
980                         err_device = ECC_ERR_DEVICE(err_correction_info);
981 
982                         if (ECC_ERROR_CORRECTABLE(err_correction_info)) {
983                                 /*
984                                  * If err_byte is larger than ECC_SECTOR_SIZE,
985                                  * means error happened in OOB, so we ignore
986                                  * it. It's no need for us to correct it
987                                  * err_device is represented the NAND error
988                                  * bits are happened in if there are more
989                                  * than one NAND connected.
990                                  */
991                                 if (err_byte < ECC_SECTOR_SIZE) {
992                                         struct mtd_info *mtd =
993                                                 nand_to_mtd(&denali->nand);
994                                         int offset;
995 
996                                         offset = (err_sector *
997                                                         ECC_SECTOR_SIZE +
998                                                         err_byte) *
999                                                         denali->devnum +
1000                                                         err_device;
1001                                         /* correct the ECC error */
1002                                         buf[offset] ^= err_correction_value;
1003                                         mtd->ecc_stats.corrected++;
1004                                         bitflips++;
1005                                 }
1006                         } else {
1007                                 /*
1008                                  * if the error is not correctable, need to
1009                                  * look at the page to see if it is an erased
1010                                  * page. if so, then it's not a real ECC error
1011                                  */
1012                                 check_erased_page = true;
1013                         }
1014                 } while (!ECC_LAST_ERR(err_correction_info));
1015                 /*
1016                  * Once handle all ecc errors, controller will triger
1017                  * a ECC_TRANSACTION_DONE interrupt, so here just wait
1018                  * for a while for this interrupt
1019                  */
1020                 while (!(read_interrupt_status(denali) &
1021                                 INTR_STATUS__ECC_TRANSACTION_DONE))
1022                         cpu_relax();
1023                 clear_interrupts(denali);
1024                 denali_set_intr_modes(denali, true);
1025         }
1026         *max_bitflips = bitflips;
1027         return check_erased_page;
1028 }
1029 
1030 /* programs the controller to either enable/disable DMA transfers */
1031 static void denali_enable_dma(struct denali_nand_info *denali, bool en)
1032 {
1033         iowrite32(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE);
1034         ioread32(denali->flash_reg + DMA_ENABLE);
1035 }
1036 
1037 /* setups the HW to perform the data DMA */
1038 static void denali_setup_dma(struct denali_nand_info *denali, int op)
1039 {
1040         uint32_t mode;
1041         const int page_count = 1;
1042         uint32_t addr = denali->buf.dma_buf;
1043 
1044         mode = MODE_10 | BANK(denali->flash_bank);
1045 
1046         /* DMA is a four step process */
1047 
1048         /* 1. setup transfer type and # of pages */
1049         index_addr(denali, mode | denali->page, 0x2000 | op | page_count);
1050 
1051         /* 2. set memory high address bits 23:8 */
1052         index_addr(denali, mode | ((addr >> 16) << 8), 0x2200);
1053 
1054         /* 3. set memory low address bits 23:8 */
1055         index_addr(denali, mode | ((addr & 0xffff) << 8), 0x2300);
1056 
1057         /* 4. interrupt when complete, burst len = 64 bytes */
1058         index_addr(denali, mode | 0x14000, 0x2400);
1059 }
1060 
1061 /*
1062  * writes a page. user specifies type, and this function handles the
1063  * configuration details.
1064  */
1065 static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
1066                         const uint8_t *buf, bool raw_xfer)
1067 {
1068         struct denali_nand_info *denali = mtd_to_denali(mtd);
1069         dma_addr_t addr = denali->buf.dma_buf;
1070         size_t size = mtd->writesize + mtd->oobsize;
1071         uint32_t irq_status;
1072         uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP |
1073                                                 INTR_STATUS__PROGRAM_FAIL;
1074 
1075         /*
1076          * if it is a raw xfer, we want to disable ecc and send the spare area.
1077          * !raw_xfer - enable ecc
1078          * raw_xfer - transfer spare
1079          */
1080         setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer);
1081 
1082         /* copy buffer into DMA buffer */
1083         memcpy(denali->buf.buf, buf, mtd->writesize);
1084 
1085         if (raw_xfer) {
1086                 /* transfer the data to the spare area */
1087                 memcpy(denali->buf.buf + mtd->writesize,
1088                         chip->oob_poi,
1089                         mtd->oobsize);
1090         }
1091 
1092         dma_sync_single_for_device(denali->dev, addr, size, DMA_TO_DEVICE);
1093 
1094         clear_interrupts(denali);
1095         denali_enable_dma(denali, true);
1096 
1097         denali_setup_dma(denali, DENALI_WRITE);
1098 
1099         /* wait for operation to complete */
1100         irq_status = wait_for_irq(denali, irq_mask);
1101 
1102         if (irq_status == 0) {
1103                 dev_err(denali->dev, "timeout on write_page (type = %d)\n",
1104                         raw_xfer);
1105                 denali->status = NAND_STATUS_FAIL;
1106         }
1107 
1108         denali_enable_dma(denali, false);
1109         dma_sync_single_for_cpu(denali->dev, addr, size, DMA_TO_DEVICE);
1110 
1111         return 0;
1112 }
1113 
1114 /* NAND core entry points */
1115 
1116 /*
1117  * this is the callback that the NAND core calls to write a page. Since
1118  * writing a page with ECC or without is similar, all the work is done
1119  * by write_page above.
1120  */
1121 static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1122                                 const uint8_t *buf, int oob_required, int page)
1123 {
1124         /*
1125          * for regular page writes, we let HW handle all the ECC
1126          * data written to the device.
1127          */
1128         return write_page(mtd, chip, buf, false);
1129 }
1130 
1131 /*
1132  * This is the callback that the NAND core calls to write a page without ECC.
1133  * raw access is similar to ECC page writes, so all the work is done in the
1134  * write_page() function above.
1135  */
1136 static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1137                                  const uint8_t *buf, int oob_required,
1138                                  int page)
1139 {
1140         /*
1141          * for raw page writes, we want to disable ECC and simply write
1142          * whatever data is in the buffer.
1143          */
1144         return write_page(mtd, chip, buf, true);
1145 }
1146 
1147 static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1148                             int page)
1149 {
1150         return write_oob_data(mtd, chip->oob_poi, page);
1151 }
1152 
1153 static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1154                            int page)
1155 {
1156         read_oob_data(mtd, chip->oob_poi, page);
1157 
1158         return 0;
1159 }
1160 
1161 static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1162                             uint8_t *buf, int oob_required, int page)
1163 {
1164         unsigned int max_bitflips;
1165         struct denali_nand_info *denali = mtd_to_denali(mtd);
1166 
1167         dma_addr_t addr = denali->buf.dma_buf;
1168         size_t size = mtd->writesize + mtd->oobsize;
1169 
1170         uint32_t irq_status;
1171         uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE |
1172                             INTR_STATUS__ECC_ERR;
1173         bool check_erased_page = false;
1174 
1175         if (page != denali->page) {
1176                 dev_err(denali->dev,
1177                         "IN %s: page %d is not equal to denali->page %d",
1178                         __func__, page, denali->page);
1179                 BUG();
1180         }
1181 
1182         setup_ecc_for_xfer(denali, true, false);
1183 
1184         denali_enable_dma(denali, true);
1185         dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
1186 
1187         clear_interrupts(denali);
1188         denali_setup_dma(denali, DENALI_READ);
1189 
1190         /* wait for operation to complete */
1191         irq_status = wait_for_irq(denali, irq_mask);
1192 
1193         dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE);
1194 
1195         memcpy(buf, denali->buf.buf, mtd->writesize);
1196 
1197         check_erased_page = handle_ecc(denali, buf, irq_status, &max_bitflips);
1198         denali_enable_dma(denali, false);
1199 
1200         if (check_erased_page) {
1201                 read_oob_data(mtd, chip->oob_poi, denali->page);
1202 
1203                 /* check ECC failures that may have occurred on erased pages */
1204                 if (check_erased_page) {
1205                         if (!is_erased(buf, mtd->writesize))
1206                                 mtd->ecc_stats.failed++;
1207                         if (!is_erased(buf, mtd->oobsize))
1208                                 mtd->ecc_stats.failed++;
1209                 }
1210         }
1211         return max_bitflips;
1212 }
1213 
1214 static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1215                                 uint8_t *buf, int oob_required, int page)
1216 {
1217         struct denali_nand_info *denali = mtd_to_denali(mtd);
1218         dma_addr_t addr = denali->buf.dma_buf;
1219         size_t size = mtd->writesize + mtd->oobsize;
1220         uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP;
1221 
1222         if (page != denali->page) {
1223                 dev_err(denali->dev,
1224                         "IN %s: page %d is not equal to denali->page %d",
1225                         __func__, page, denali->page);
1226                 BUG();
1227         }
1228 
1229         setup_ecc_for_xfer(denali, false, true);
1230         denali_enable_dma(denali, true);
1231 
1232         dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
1233 
1234         clear_interrupts(denali);
1235         denali_setup_dma(denali, DENALI_READ);
1236 
1237         /* wait for operation to complete */
1238         wait_for_irq(denali, irq_mask);
1239 
1240         dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE);
1241 
1242         denali_enable_dma(denali, false);
1243 
1244         memcpy(buf, denali->buf.buf, mtd->writesize);
1245         memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize);
1246 
1247         return 0;
1248 }
1249 
1250 static uint8_t denali_read_byte(struct mtd_info *mtd)
1251 {
1252         struct denali_nand_info *denali = mtd_to_denali(mtd);
1253         uint8_t result = 0xff;
1254 
1255         if (denali->buf.head < denali->buf.tail)
1256                 result = denali->buf.buf[denali->buf.head++];
1257 
1258         return result;
1259 }
1260 
1261 static void denali_select_chip(struct mtd_info *mtd, int chip)
1262 {
1263         struct denali_nand_info *denali = mtd_to_denali(mtd);
1264 
1265         spin_lock_irq(&denali->irq_lock);
1266         denali->flash_bank = chip;
1267         spin_unlock_irq(&denali->irq_lock);
1268 }
1269 
1270 static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
1271 {
1272         struct denali_nand_info *denali = mtd_to_denali(mtd);
1273         int status = denali->status;
1274 
1275         denali->status = 0;
1276 
1277         return status;
1278 }
1279 
1280 static int denali_erase(struct mtd_info *mtd, int page)
1281 {
1282         struct denali_nand_info *denali = mtd_to_denali(mtd);
1283 
1284         uint32_t cmd, irq_status;
1285 
1286         clear_interrupts(denali);
1287 
1288         /* setup page read request for access type */
1289         cmd = MODE_10 | BANK(denali->flash_bank) | page;
1290         index_addr(denali, cmd, 0x1);
1291 
1292         /* wait for erase to complete or failure to occur */
1293         irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP |
1294                                         INTR_STATUS__ERASE_FAIL);
1295 
1296         return irq_status & INTR_STATUS__ERASE_FAIL ? NAND_STATUS_FAIL : PASS;
1297 }
1298 
1299 static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
1300                            int page)
1301 {
1302         struct denali_nand_info *denali = mtd_to_denali(mtd);
1303         uint32_t addr, id;
1304         int i;
1305 
1306         switch (cmd) {
1307         case NAND_CMD_PAGEPROG:
1308                 break;
1309         case NAND_CMD_STATUS:
1310                 read_status(denali);
1311                 break;
1312         case NAND_CMD_READID:
1313         case NAND_CMD_PARAM:
1314                 reset_buf(denali);
1315                 /*
1316                  * sometimes ManufactureId read from register is not right
1317                  * e.g. some of Micron MT29F32G08QAA MLC NAND chips
1318                  * So here we send READID cmd to NAND insteand
1319                  */
1320                 addr = MODE_11 | BANK(denali->flash_bank);
1321                 index_addr(denali, addr | 0, 0x90);
1322                 index_addr(denali, addr | 1, col);
1323                 for (i = 0; i < 8; i++) {
1324                         index_addr_read_data(denali, addr | 2, &id);
1325                         write_byte_to_buf(denali, id);
1326                 }
1327                 break;
1328         case NAND_CMD_READ0:
1329         case NAND_CMD_SEQIN:
1330                 denali->page = page;
1331                 break;
1332         case NAND_CMD_RESET:
1333                 reset_bank(denali);
1334                 break;
1335         case NAND_CMD_READOOB:
1336                 /* TODO: Read OOB data */
1337                 break;
1338         default:
1339                 pr_err(": unsupported command received 0x%x\n", cmd);
1340                 break;
1341         }
1342 }
1343 /* end NAND core entry points */
1344 
1345 /* Initialization code to bring the device up to a known good state */
1346 static void denali_hw_init(struct denali_nand_info *denali)
1347 {
1348         /*
1349          * tell driver how many bit controller will skip before
1350          * writing ECC code in OOB, this register may be already
1351          * set by firmware. So we read this value out.
1352          * if this value is 0, just let it be.
1353          */
1354         denali->bbtskipbytes = ioread32(denali->flash_reg +
1355                                                 SPARE_AREA_SKIP_BYTES);
1356         detect_max_banks(denali);
1357         denali_nand_reset(denali);
1358         iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED);
1359         iowrite32(CHIP_EN_DONT_CARE__FLAG,
1360                         denali->flash_reg + CHIP_ENABLE_DONT_CARE);
1361 
1362         iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
1363 
1364         /* Should set value for these registers when init */
1365         iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
1366         iowrite32(1, denali->flash_reg + ECC_ENABLE);
1367         denali_nand_timing_set(denali);
1368         denali_irq_init(denali);
1369 }
1370 
1371 /*
1372  * Althogh controller spec said SLC ECC is forceb to be 4bit,
1373  * but denali controller in MRST only support 15bit and 8bit ECC
1374  * correction
1375  */
1376 #define ECC_8BITS       14
1377 static struct nand_ecclayout nand_8bit_oob = {
1378         .eccbytes = 14,
1379 };
1380 
1381 #define ECC_15BITS      26
1382 static struct nand_ecclayout nand_15bit_oob = {
1383         .eccbytes = 26,
1384 };
1385 
1386 static uint8_t bbt_pattern[] = {'B', 'b', 't', '' };
1387 static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
1388 
1389 static struct nand_bbt_descr bbt_main_descr = {
1390         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1391                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1392         .offs = 8,
1393         .len = 4,
1394         .veroffs = 12,
1395         .maxblocks = 4,
1396         .pattern = bbt_pattern,
1397 };
1398 
1399 static struct nand_bbt_descr bbt_mirror_descr = {
1400         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1401                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1402         .offs = 8,
1403         .len = 4,
1404         .veroffs = 12,
1405         .maxblocks = 4,
1406         .pattern = mirror_pattern,
1407 };
1408 
1409 /* initialize driver data structures */
1410 static void denali_drv_init(struct denali_nand_info *denali)
1411 {
1412         denali->idx = 0;
1413 
1414         /* setup interrupt handler */
1415         /*
1416          * the completion object will be used to notify
1417          * the callee that the interrupt is done
1418          */
1419         init_completion(&denali->complete);
1420 
1421         /*
1422          * the spinlock will be used to synchronize the ISR with any
1423          * element that might be access shared data (interrupt status)
1424          */
1425         spin_lock_init(&denali->irq_lock);
1426 
1427         /* indicate that MTD has not selected a valid bank yet */
1428         denali->flash_bank = CHIP_SELECT_INVALID;
1429 
1430         /* initialize our irq_status variable to indicate no interrupts */
1431         denali->irq_status = 0;
1432 }
1433 
1434 int denali_init(struct denali_nand_info *denali)
1435 {
1436         struct mtd_info *mtd = nand_to_mtd(&denali->nand);
1437         int ret;
1438 
1439         if (denali->platform == INTEL_CE4100) {
1440                 /*
1441                  * Due to a silicon limitation, we can only support
1442                  * ONFI timing mode 1 and below.
1443                  */
1444                 if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
1445                         pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n");
1446                         return -EINVAL;
1447                 }
1448         }
1449 
1450         /* allocate a temporary buffer for nand_scan_ident() */
1451         denali->buf.buf = devm_kzalloc(denali->dev, PAGE_SIZE,
1452                                         GFP_DMA | GFP_KERNEL);
1453         if (!denali->buf.buf)
1454                 return -ENOMEM;
1455 
1456         mtd->dev.parent = denali->dev;
1457         denali_hw_init(denali);
1458         denali_drv_init(denali);
1459 
1460         /*
1461          * denali_isr register is done after all the hardware
1462          * initilization is finished
1463          */
1464         if (request_irq(denali->irq, denali_isr, IRQF_SHARED,
1465                         DENALI_NAND_NAME, denali)) {
1466                 pr_err("Spectra: Unable to allocate IRQ\n");
1467                 return -ENODEV;
1468         }
1469 
1470         /* now that our ISR is registered, we can enable interrupts */
1471         denali_set_intr_modes(denali, true);
1472         mtd->name = "denali-nand";
1473 
1474         /* register the driver with the NAND core subsystem */
1475         denali->nand.select_chip = denali_select_chip;
1476         denali->nand.cmdfunc = denali_cmdfunc;
1477         denali->nand.read_byte = denali_read_byte;
1478         denali->nand.waitfunc = denali_waitfunc;
1479 
1480         /*
1481          * scan for NAND devices attached to the controller
1482          * this is the first stage in a two step process to register
1483          * with the nand subsystem
1484          */
1485         if (nand_scan_ident(mtd, denali->max_banks, NULL)) {
1486                 ret = -ENXIO;
1487                 goto failed_req_irq;
1488         }
1489 
1490         /* allocate the right size buffer now */
1491         devm_kfree(denali->dev, denali->buf.buf);
1492         denali->buf.buf = devm_kzalloc(denali->dev,
1493                              mtd->writesize + mtd->oobsize,
1494                              GFP_KERNEL);
1495         if (!denali->buf.buf) {
1496                 ret = -ENOMEM;
1497                 goto failed_req_irq;
1498         }
1499 
1500         /* Is 32-bit DMA supported? */
1501         ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32));
1502         if (ret) {
1503                 pr_err("Spectra: no usable DMA configuration\n");
1504                 goto failed_req_irq;
1505         }
1506 
1507         denali->buf.dma_buf = dma_map_single(denali->dev, denali->buf.buf,
1508                              mtd->writesize + mtd->oobsize,
1509                              DMA_BIDIRECTIONAL);
1510         if (dma_mapping_error(denali->dev, denali->buf.dma_buf)) {
1511                 dev_err(denali->dev, "Spectra: failed to map DMA buffer\n");
1512                 ret = -EIO;
1513                 goto failed_req_irq;
1514         }
1515 
1516         /*
1517          * support for multi nand
1518          * MTD known nothing about multi nand, so we should tell it
1519          * the real pagesize and anything necessery
1520          */
1521         denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED);
1522         denali->nand.chipsize <<= (denali->devnum - 1);
1523         denali->nand.page_shift += (denali->devnum - 1);
1524         denali->nand.pagemask = (denali->nand.chipsize >>
1525                                                 denali->nand.page_shift) - 1;
1526         denali->nand.bbt_erase_shift += (denali->devnum - 1);
1527         denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift;
1528         denali->nand.chip_shift += (denali->devnum - 1);
1529         mtd->writesize <<= (denali->devnum - 1);
1530         mtd->oobsize <<= (denali->devnum - 1);
1531         mtd->erasesize <<= (denali->devnum - 1);
1532         mtd->size = denali->nand.numchips * denali->nand.chipsize;
1533         denali->bbtskipbytes *= denali->devnum;
1534 
1535         /*
1536          * second stage of the NAND scan
1537          * this stage requires information regarding ECC and
1538          * bad block management.
1539          */
1540 
1541         /* Bad block management */
1542         denali->nand.bbt_td = &bbt_main_descr;
1543         denali->nand.bbt_md = &bbt_mirror_descr;
1544 
1545         /* skip the scan for now until we have OOB read and write support */
1546         denali->nand.bbt_options |= NAND_BBT_USE_FLASH;
1547         denali->nand.options |= NAND_SKIP_BBTSCAN;
1548         denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
1549 
1550         /* no subpage writes on denali */
1551         denali->nand.options |= NAND_NO_SUBPAGE_WRITE;
1552 
1553         /*
1554          * Denali Controller only support 15bit and 8bit ECC in MRST,
1555          * so just let controller do 15bit ECC for MLC and 8bit ECC for
1556          * SLC if possible.
1557          * */
1558         if (!nand_is_slc(&denali->nand) &&
1559                         (mtd->oobsize > (denali->bbtskipbytes +
1560                         ECC_15BITS * (mtd->writesize /
1561                         ECC_SECTOR_SIZE)))) {
1562                 /* if MLC OOB size is large enough, use 15bit ECC*/
1563                 denali->nand.ecc.strength = 15;
1564                 denali->nand.ecc.layout = &nand_15bit_oob;
1565                 denali->nand.ecc.bytes = ECC_15BITS;
1566                 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
1567         } else if (mtd->oobsize < (denali->bbtskipbytes +
1568                         ECC_8BITS * (mtd->writesize /
1569                         ECC_SECTOR_SIZE))) {
1570                 pr_err("Your NAND chip OOB is not large enough to contain 8bit ECC correction codes");
1571                 goto failed_req_irq;
1572         } else {
1573                 denali->nand.ecc.strength = 8;
1574                 denali->nand.ecc.layout = &nand_8bit_oob;
1575                 denali->nand.ecc.bytes = ECC_8BITS;
1576                 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
1577         }
1578 
1579         denali->nand.ecc.bytes *= denali->devnum;
1580         denali->nand.ecc.strength *= denali->devnum;
1581         denali->nand.ecc.layout->eccbytes *=
1582                 mtd->writesize / ECC_SECTOR_SIZE;
1583         denali->nand.ecc.layout->oobfree[0].offset =
1584                 denali->bbtskipbytes + denali->nand.ecc.layout->eccbytes;
1585         denali->nand.ecc.layout->oobfree[0].length =
1586                 mtd->oobsize - denali->nand.ecc.layout->eccbytes -
1587                 denali->bbtskipbytes;
1588 
1589         /*
1590          * Let driver know the total blocks number and how many blocks
1591          * contained by each nand chip. blksperchip will help driver to
1592          * know how many blocks is taken by FW.
1593          */
1594         denali->totalblks = mtd->size >> denali->nand.phys_erase_shift;
1595         denali->blksperchip = denali->totalblks / denali->nand.numchips;
1596 
1597         /* override the default read operations */
1598         denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum;
1599         denali->nand.ecc.read_page = denali_read_page;
1600         denali->nand.ecc.read_page_raw = denali_read_page_raw;
1601         denali->nand.ecc.write_page = denali_write_page;
1602         denali->nand.ecc.write_page_raw = denali_write_page_raw;
1603         denali->nand.ecc.read_oob = denali_read_oob;
1604         denali->nand.ecc.write_oob = denali_write_oob;
1605         denali->nand.erase = denali_erase;
1606 
1607         if (nand_scan_tail(mtd)) {
1608                 ret = -ENXIO;
1609                 goto failed_req_irq;
1610         }
1611 
1612         ret = mtd_device_register(mtd, NULL, 0);
1613         if (ret) {
1614                 dev_err(denali->dev, "Spectra: Failed to register MTD: %d\n",
1615                                 ret);
1616                 goto failed_req_irq;
1617         }
1618         return 0;
1619 
1620 failed_req_irq:
1621         denali_irq_cleanup(denali->irq, denali);
1622 
1623         return ret;
1624 }
1625 EXPORT_SYMBOL(denali_init);
1626 
1627 /* driver exit point */
1628 void denali_remove(struct denali_nand_info *denali)
1629 {
1630         struct mtd_info *mtd = nand_to_mtd(&denali->nand);
1631         /*
1632          * Pre-compute DMA buffer size to avoid any problems in case
1633          * nand_release() ever changes in a way that mtd->writesize and
1634          * mtd->oobsize are not reliable after this call.
1635          */
1636         int bufsize = mtd->writesize + mtd->oobsize;
1637 
1638         nand_release(mtd);
1639         denali_irq_cleanup(denali->irq, denali);
1640         dma_unmap_single(denali->dev, denali->buf.dma_buf, bufsize,
1641                          DMA_BIDIRECTIONAL);
1642 }
1643 EXPORT_SYMBOL(denali_remove);
1644 

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