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Linux/drivers/mtd/nand/denali.c

  1 /*
  2  * NAND Flash Controller Device Driver
  3  * Copyright © 2009-2010, Intel Corporation and its suppliers.
  4  *
  5  * This program is free software; you can redistribute it and/or modify it
  6  * under the terms and conditions of the GNU General Public License,
  7  * version 2, as published by the Free Software Foundation.
  8  *
  9  * This program is distributed in the hope it will be useful, but WITHOUT
 10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 12  * more details.
 13  *
 14  * You should have received a copy of the GNU General Public License along with
 15  * this program; if not, write to the Free Software Foundation, Inc.,
 16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 17  *
 18  */
 19 #include <linux/interrupt.h>
 20 #include <linux/delay.h>
 21 #include <linux/dma-mapping.h>
 22 #include <linux/wait.h>
 23 #include <linux/mutex.h>
 24 #include <linux/mtd/mtd.h>
 25 #include <linux/module.h>
 26 
 27 #include "denali.h"
 28 
 29 MODULE_LICENSE("GPL");
 30 
 31 /*
 32  * We define a module parameter that allows the user to override
 33  * the hardware and decide what timing mode should be used.
 34  */
 35 #define NAND_DEFAULT_TIMINGS    -1
 36 
 37 static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
 38 module_param(onfi_timing_mode, int, S_IRUGO);
 39 MODULE_PARM_DESC(onfi_timing_mode,
 40            "Overrides default ONFI setting. -1 indicates use default timings");
 41 
 42 #define DENALI_NAND_NAME    "denali-nand"
 43 
 44 /*
 45  * We define a macro here that combines all interrupts this driver uses into
 46  * a single constant value, for convenience.
 47  */
 48 #define DENALI_IRQ_ALL  (INTR_STATUS__DMA_CMD_COMP | \
 49                         INTR_STATUS__ECC_TRANSACTION_DONE | \
 50                         INTR_STATUS__ECC_ERR | \
 51                         INTR_STATUS__PROGRAM_FAIL | \
 52                         INTR_STATUS__LOAD_COMP | \
 53                         INTR_STATUS__PROGRAM_COMP | \
 54                         INTR_STATUS__TIME_OUT | \
 55                         INTR_STATUS__ERASE_FAIL | \
 56                         INTR_STATUS__RST_COMP | \
 57                         INTR_STATUS__ERASE_COMP)
 58 
 59 /*
 60  * indicates whether or not the internal value for the flash bank is
 61  * valid or not
 62  */
 63 #define CHIP_SELECT_INVALID     -1
 64 
 65 #define SUPPORT_8BITECC         1
 66 
 67 /*
 68  * This macro divides two integers and rounds fractional values up
 69  * to the nearest integer value.
 70  */
 71 #define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
 72 
 73 /*
 74  * this macro allows us to convert from an MTD structure to our own
 75  * device context (denali) structure.
 76  */
 77 static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
 78 {
 79         return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);
 80 }
 81 
 82 /*
 83  * These constants are defined by the driver to enable common driver
 84  * configuration options.
 85  */
 86 #define SPARE_ACCESS            0x41
 87 #define MAIN_ACCESS             0x42
 88 #define MAIN_SPARE_ACCESS       0x43
 89 #define PIPELINE_ACCESS         0x2000
 90 
 91 #define DENALI_READ     0
 92 #define DENALI_WRITE    0x100
 93 
 94 /* types of device accesses. We can issue commands and get status */
 95 #define COMMAND_CYCLE   0
 96 #define ADDR_CYCLE      1
 97 #define STATUS_CYCLE    2
 98 
 99 /*
100  * this is a helper macro that allows us to
101  * format the bank into the proper bits for the controller
102  */
103 #define BANK(x) ((x) << 24)
104 
105 /* forward declarations */
106 static void clear_interrupts(struct denali_nand_info *denali);
107 static uint32_t wait_for_irq(struct denali_nand_info *denali,
108                                                         uint32_t irq_mask);
109 static void denali_irq_enable(struct denali_nand_info *denali,
110                                                         uint32_t int_mask);
111 static uint32_t read_interrupt_status(struct denali_nand_info *denali);
112 
113 /*
114  * Certain operations for the denali NAND controller use an indexed mode to
115  * read/write data. The operation is performed by writing the address value
116  * of the command to the device memory followed by the data. This function
117  * abstracts this common operation.
118  */
119 static void index_addr(struct denali_nand_info *denali,
120                                 uint32_t address, uint32_t data)
121 {
122         iowrite32(address, denali->flash_mem);
123         iowrite32(data, denali->flash_mem + 0x10);
124 }
125 
126 /* Perform an indexed read of the device */
127 static void index_addr_read_data(struct denali_nand_info *denali,
128                                  uint32_t address, uint32_t *pdata)
129 {
130         iowrite32(address, denali->flash_mem);
131         *pdata = ioread32(denali->flash_mem + 0x10);
132 }
133 
134 /*
135  * We need to buffer some data for some of the NAND core routines.
136  * The operations manage buffering that data.
137  */
138 static void reset_buf(struct denali_nand_info *denali)
139 {
140         denali->buf.head = denali->buf.tail = 0;
141 }
142 
143 static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)
144 {
145         denali->buf.buf[denali->buf.tail++] = byte;
146 }
147 
148 /* reads the status of the device */
149 static void read_status(struct denali_nand_info *denali)
150 {
151         uint32_t cmd;
152 
153         /* initialize the data buffer to store status */
154         reset_buf(denali);
155 
156         cmd = ioread32(denali->flash_reg + WRITE_PROTECT);
157         if (cmd)
158                 write_byte_to_buf(denali, NAND_STATUS_WP);
159         else
160                 write_byte_to_buf(denali, 0);
161 }
162 
163 /* resets a specific device connected to the core */
164 static void reset_bank(struct denali_nand_info *denali)
165 {
166         uint32_t irq_status;
167         uint32_t irq_mask = INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT;
168 
169         clear_interrupts(denali);
170 
171         iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET);
172 
173         irq_status = wait_for_irq(denali, irq_mask);
174 
175         if (irq_status & INTR_STATUS__TIME_OUT)
176                 dev_err(denali->dev, "reset bank failed.\n");
177 }
178 
179 /* Reset the flash controller */
180 static uint16_t denali_nand_reset(struct denali_nand_info *denali)
181 {
182         int i;
183 
184         for (i = 0; i < denali->max_banks; i++)
185                 iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
186                 denali->flash_reg + INTR_STATUS(i));
187 
188         for (i = 0; i < denali->max_banks; i++) {
189                 iowrite32(1 << i, denali->flash_reg + DEVICE_RESET);
190                 while (!(ioread32(denali->flash_reg + INTR_STATUS(i)) &
191                         (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT)))
192                         cpu_relax();
193                 if (ioread32(denali->flash_reg + INTR_STATUS(i)) &
194                         INTR_STATUS__TIME_OUT)
195                         dev_dbg(denali->dev,
196                         "NAND Reset operation timed out on bank %d\n", i);
197         }
198 
199         for (i = 0; i < denali->max_banks; i++)
200                 iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
201                           denali->flash_reg + INTR_STATUS(i));
202 
203         return PASS;
204 }
205 
206 /*
207  * this routine calculates the ONFI timing values for a given mode and
208  * programs the clocking register accordingly. The mode is determined by
209  * the get_onfi_nand_para routine.
210  */
211 static void nand_onfi_timing_set(struct denali_nand_info *denali,
212                                                                 uint16_t mode)
213 {
214         uint16_t Trea[6] = {40, 30, 25, 20, 20, 16};
215         uint16_t Trp[6] = {50, 25, 17, 15, 12, 10};
216         uint16_t Treh[6] = {30, 15, 15, 10, 10, 7};
217         uint16_t Trc[6] = {100, 50, 35, 30, 25, 20};
218         uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15};
219         uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5};
220         uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25};
221         uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70};
222         uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100};
223         uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100};
224         uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60};
225         uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15};
226 
227         uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid;
228         uint16_t dv_window = 0;
229         uint16_t en_lo, en_hi;
230         uint16_t acc_clks;
231         uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
232 
233         en_lo = CEIL_DIV(Trp[mode], CLK_X);
234         en_hi = CEIL_DIV(Treh[mode], CLK_X);
235 #if ONFI_BLOOM_TIME
236         if ((en_hi * CLK_X) < (Treh[mode] + 2))
237                 en_hi++;
238 #endif
239 
240         if ((en_lo + en_hi) * CLK_X < Trc[mode])
241                 en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X);
242 
243         if ((en_lo + en_hi) < CLK_MULTI)
244                 en_lo += CLK_MULTI - en_lo - en_hi;
245 
246         while (dv_window < 8) {
247                 data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode];
248 
249                 data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode];
250 
251                 data_invalid = data_invalid_rhoh < data_invalid_rloh ?
252                                         data_invalid_rhoh : data_invalid_rloh;
253 
254                 dv_window = data_invalid - Trea[mode];
255 
256                 if (dv_window < 8)
257                         en_lo++;
258         }
259 
260         acc_clks = CEIL_DIV(Trea[mode], CLK_X);
261 
262         while (acc_clks * CLK_X - Trea[mode] < 3)
263                 acc_clks++;
264 
265         if (data_invalid - acc_clks * CLK_X < 2)
266                 dev_warn(denali->dev, "%s, Line %d: Warning!\n",
267                          __FILE__, __LINE__);
268 
269         addr_2_data = CEIL_DIV(Tadl[mode], CLK_X);
270         re_2_we = CEIL_DIV(Trhw[mode], CLK_X);
271         re_2_re = CEIL_DIV(Trhz[mode], CLK_X);
272         we_2_re = CEIL_DIV(Twhr[mode], CLK_X);
273         cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X);
274         if (cs_cnt == 0)
275                 cs_cnt = 1;
276 
277         if (Tcea[mode]) {
278                 while (cs_cnt * CLK_X + Trea[mode] < Tcea[mode])
279                         cs_cnt++;
280         }
281 
282 #if MODE5_WORKAROUND
283         if (mode == 5)
284                 acc_clks = 5;
285 #endif
286 
287         /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */
288         if (ioread32(denali->flash_reg + MANUFACTURER_ID) == 0 &&
289                 ioread32(denali->flash_reg + DEVICE_ID) == 0x88)
290                 acc_clks = 6;
291 
292         iowrite32(acc_clks, denali->flash_reg + ACC_CLKS);
293         iowrite32(re_2_we, denali->flash_reg + RE_2_WE);
294         iowrite32(re_2_re, denali->flash_reg + RE_2_RE);
295         iowrite32(we_2_re, denali->flash_reg + WE_2_RE);
296         iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA);
297         iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
298         iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
299         iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
300 }
301 
302 /* queries the NAND device to see what ONFI modes it supports. */
303 static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
304 {
305         int i;
306 
307         /*
308          * we needn't to do a reset here because driver has already
309          * reset all the banks before
310          */
311         if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
312                 ONFI_TIMING_MODE__VALUE))
313                 return FAIL;
314 
315         for (i = 5; i > 0; i--) {
316                 if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
317                         (0x01 << i))
318                         break;
319         }
320 
321         nand_onfi_timing_set(denali, i);
322 
323         /*
324          * By now, all the ONFI devices we know support the page cache
325          * rw feature. So here we enable the pipeline_rw_ahead feature
326          */
327         /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */
328         /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE);  */
329 
330         return PASS;
331 }
332 
333 static void get_samsung_nand_para(struct denali_nand_info *denali,
334                                                         uint8_t device_id)
335 {
336         if (device_id == 0xd3) { /* Samsung K9WAG08U1A */
337                 /* Set timing register values according to datasheet */
338                 iowrite32(5, denali->flash_reg + ACC_CLKS);
339                 iowrite32(20, denali->flash_reg + RE_2_WE);
340                 iowrite32(12, denali->flash_reg + WE_2_RE);
341                 iowrite32(14, denali->flash_reg + ADDR_2_DATA);
342                 iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT);
343                 iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT);
344                 iowrite32(2, denali->flash_reg + CS_SETUP_CNT);
345         }
346 }
347 
348 static void get_toshiba_nand_para(struct denali_nand_info *denali)
349 {
350         uint32_t tmp;
351 
352         /*
353          * Workaround to fix a controller bug which reports a wrong
354          * spare area size for some kind of Toshiba NAND device
355          */
356         if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
357                 (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
358                 iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
359                 tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) *
360                         ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
361                 iowrite32(tmp,
362                                 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
363 #if SUPPORT_15BITECC
364                 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
365 #elif SUPPORT_8BITECC
366                 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
367 #endif
368         }
369 }
370 
371 static void get_hynix_nand_para(struct denali_nand_info *denali,
372                                                         uint8_t device_id)
373 {
374         uint32_t main_size, spare_size;
375 
376         switch (device_id) {
377         case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
378         case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
379                 iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK);
380                 iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
381                 iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
382                 main_size = 4096 *
383                         ioread32(denali->flash_reg + DEVICES_CONNECTED);
384                 spare_size = 224 *
385                         ioread32(denali->flash_reg + DEVICES_CONNECTED);
386                 iowrite32(main_size,
387                                 denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
388                 iowrite32(spare_size,
389                                 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
390                 iowrite32(0, denali->flash_reg + DEVICE_WIDTH);
391 #if SUPPORT_15BITECC
392                 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
393 #elif SUPPORT_8BITECC
394                 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
395 #endif
396                 break;
397         default:
398                 dev_warn(denali->dev,
399                          "Unknown Hynix NAND (Device ID: 0x%x).\n"
400                          "Will use default parameter values instead.\n",
401                          device_id);
402         }
403 }
404 
405 /*
406  * determines how many NAND chips are connected to the controller. Note for
407  * Intel CE4100 devices we don't support more than one device.
408  */
409 static void find_valid_banks(struct denali_nand_info *denali)
410 {
411         uint32_t id[denali->max_banks];
412         int i;
413 
414         denali->total_used_banks = 1;
415         for (i = 0; i < denali->max_banks; i++) {
416                 index_addr(denali, MODE_11 | (i << 24) | 0, 0x90);
417                 index_addr(denali, MODE_11 | (i << 24) | 1, 0);
418                 index_addr_read_data(denali, MODE_11 | (i << 24) | 2, &id[i]);
419 
420                 dev_dbg(denali->dev,
421                         "Return 1st ID for bank[%d]: %x\n", i, id[i]);
422 
423                 if (i == 0) {
424                         if (!(id[i] & 0x0ff))
425                                 break; /* WTF? */
426                 } else {
427                         if ((id[i] & 0x0ff) == (id[0] & 0x0ff))
428                                 denali->total_used_banks++;
429                         else
430                                 break;
431                 }
432         }
433 
434         if (denali->platform == INTEL_CE4100) {
435                 /*
436                  * Platform limitations of the CE4100 device limit
437                  * users to a single chip solution for NAND.
438                  * Multichip support is not enabled.
439                  */
440                 if (denali->total_used_banks != 1) {
441                         dev_err(denali->dev,
442                                 "Sorry, Intel CE4100 only supports a single NAND device.\n");
443                         BUG();
444                 }
445         }
446         dev_dbg(denali->dev,
447                 "denali->total_used_banks: %d\n", denali->total_used_banks);
448 }
449 
450 /*
451  * Use the configuration feature register to determine the maximum number of
452  * banks that the hardware supports.
453  */
454 static void detect_max_banks(struct denali_nand_info *denali)
455 {
456         uint32_t features = ioread32(denali->flash_reg + FEATURES);
457         /*
458          * Read the revision register, so we can calculate the max_banks
459          * properly: the encoding changed from rev 5.0 to 5.1
460          */
461         u32 revision = MAKE_COMPARABLE_REVISION(
462                                 ioread32(denali->flash_reg + REVISION));
463 
464         if (revision < REVISION_5_1)
465                 denali->max_banks = 2 << (features & FEATURES__N_BANKS);
466         else
467                 denali->max_banks = 1 << (features & FEATURES__N_BANKS);
468 }
469 
470 static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
471 {
472         uint16_t status = PASS;
473         uint32_t id_bytes[8], addr;
474         uint8_t maf_id, device_id;
475         int i;
476 
477         /*
478          * Use read id method to get device ID and other params.
479          * For some NAND chips, controller can't report the correct
480          * device ID by reading from DEVICE_ID register
481          */
482         addr = MODE_11 | BANK(denali->flash_bank);
483         index_addr(denali, addr | 0, 0x90);
484         index_addr(denali, addr | 1, 0);
485         for (i = 0; i < 8; i++)
486                 index_addr_read_data(denali, addr | 2, &id_bytes[i]);
487         maf_id = id_bytes[0];
488         device_id = id_bytes[1];
489 
490         if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
491                 ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */
492                 if (FAIL == get_onfi_nand_para(denali))
493                         return FAIL;
494         } else if (maf_id == 0xEC) { /* Samsung NAND */
495                 get_samsung_nand_para(denali, device_id);
496         } else if (maf_id == 0x98) { /* Toshiba NAND */
497                 get_toshiba_nand_para(denali);
498         } else if (maf_id == 0xAD) { /* Hynix NAND */
499                 get_hynix_nand_para(denali, device_id);
500         }
501 
502         dev_info(denali->dev,
503                         "Dump timing register values:\n"
504                         "acc_clks: %d, re_2_we: %d, re_2_re: %d\n"
505                         "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n"
506                         "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
507                         ioread32(denali->flash_reg + ACC_CLKS),
508                         ioread32(denali->flash_reg + RE_2_WE),
509                         ioread32(denali->flash_reg + RE_2_RE),
510                         ioread32(denali->flash_reg + WE_2_RE),
511                         ioread32(denali->flash_reg + ADDR_2_DATA),
512                         ioread32(denali->flash_reg + RDWR_EN_LO_CNT),
513                         ioread32(denali->flash_reg + RDWR_EN_HI_CNT),
514                         ioread32(denali->flash_reg + CS_SETUP_CNT));
515 
516         find_valid_banks(denali);
517 
518         /*
519          * If the user specified to override the default timings
520          * with a specific ONFI mode, we apply those changes here.
521          */
522         if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
523                 nand_onfi_timing_set(denali, onfi_timing_mode);
524 
525         return status;
526 }
527 
528 static void denali_set_intr_modes(struct denali_nand_info *denali,
529                                         uint16_t INT_ENABLE)
530 {
531         if (INT_ENABLE)
532                 iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE);
533         else
534                 iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE);
535 }
536 
537 /*
538  * validation function to verify that the controlling software is making
539  * a valid request
540  */
541 static inline bool is_flash_bank_valid(int flash_bank)
542 {
543         return flash_bank >= 0 && flash_bank < 4;
544 }
545 
546 static void denali_irq_init(struct denali_nand_info *denali)
547 {
548         uint32_t int_mask;
549         int i;
550 
551         /* Disable global interrupts */
552         denali_set_intr_modes(denali, false);
553 
554         int_mask = DENALI_IRQ_ALL;
555 
556         /* Clear all status bits */
557         for (i = 0; i < denali->max_banks; ++i)
558                 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i));
559 
560         denali_irq_enable(denali, int_mask);
561 }
562 
563 static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali)
564 {
565         denali_set_intr_modes(denali, false);
566 }
567 
568 static void denali_irq_enable(struct denali_nand_info *denali,
569                                                         uint32_t int_mask)
570 {
571         int i;
572 
573         for (i = 0; i < denali->max_banks; ++i)
574                 iowrite32(int_mask, denali->flash_reg + INTR_EN(i));
575 }
576 
577 /*
578  * This function only returns when an interrupt that this driver cares about
579  * occurs. This is to reduce the overhead of servicing interrupts
580  */
581 static inline uint32_t denali_irq_detected(struct denali_nand_info *denali)
582 {
583         return read_interrupt_status(denali) & DENALI_IRQ_ALL;
584 }
585 
586 /* Interrupts are cleared by writing a 1 to the appropriate status bit */
587 static inline void clear_interrupt(struct denali_nand_info *denali,
588                                                         uint32_t irq_mask)
589 {
590         uint32_t intr_status_reg;
591 
592         intr_status_reg = INTR_STATUS(denali->flash_bank);
593 
594         iowrite32(irq_mask, denali->flash_reg + intr_status_reg);
595 }
596 
597 static void clear_interrupts(struct denali_nand_info *denali)
598 {
599         uint32_t status;
600 
601         spin_lock_irq(&denali->irq_lock);
602 
603         status = read_interrupt_status(denali);
604         clear_interrupt(denali, status);
605 
606         denali->irq_status = 0x0;
607         spin_unlock_irq(&denali->irq_lock);
608 }
609 
610 static uint32_t read_interrupt_status(struct denali_nand_info *denali)
611 {
612         uint32_t intr_status_reg;
613 
614         intr_status_reg = INTR_STATUS(denali->flash_bank);
615 
616         return ioread32(denali->flash_reg + intr_status_reg);
617 }
618 
619 /*
620  * This is the interrupt service routine. It handles all interrupts
621  * sent to this device. Note that on CE4100, this is a shared interrupt.
622  */
623 static irqreturn_t denali_isr(int irq, void *dev_id)
624 {
625         struct denali_nand_info *denali = dev_id;
626         uint32_t irq_status;
627         irqreturn_t result = IRQ_NONE;
628 
629         spin_lock(&denali->irq_lock);
630 
631         /* check to see if a valid NAND chip has been selected. */
632         if (is_flash_bank_valid(denali->flash_bank)) {
633                 /*
634                  * check to see if controller generated the interrupt,
635                  * since this is a shared interrupt
636                  */
637                 irq_status = denali_irq_detected(denali);
638                 if (irq_status != 0) {
639                         /* handle interrupt */
640                         /* first acknowledge it */
641                         clear_interrupt(denali, irq_status);
642                         /*
643                          * store the status in the device context for someone
644                          * to read
645                          */
646                         denali->irq_status |= irq_status;
647                         /* notify anyone who cares that it happened */
648                         complete(&denali->complete);
649                         /* tell the OS that we've handled this */
650                         result = IRQ_HANDLED;
651                 }
652         }
653         spin_unlock(&denali->irq_lock);
654         return result;
655 }
656 #define BANK(x) ((x) << 24)
657 
658 static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
659 {
660         unsigned long comp_res;
661         uint32_t intr_status;
662         unsigned long timeout = msecs_to_jiffies(1000);
663 
664         do {
665                 comp_res =
666                         wait_for_completion_timeout(&denali->complete, timeout);
667                 spin_lock_irq(&denali->irq_lock);
668                 intr_status = denali->irq_status;
669 
670                 if (intr_status & irq_mask) {
671                         denali->irq_status &= ~irq_mask;
672                         spin_unlock_irq(&denali->irq_lock);
673                         /* our interrupt was detected */
674                         break;
675                 }
676 
677                 /*
678                  * these are not the interrupts you are looking for -
679                  * need to wait again
680                  */
681                 spin_unlock_irq(&denali->irq_lock);
682         } while (comp_res != 0);
683 
684         if (comp_res == 0) {
685                 /* timeout */
686                 pr_err("timeout occurred, status = 0x%x, mask = 0x%x\n",
687                                 intr_status, irq_mask);
688 
689                 intr_status = 0;
690         }
691         return intr_status;
692 }
693 
694 /*
695  * This helper function setups the registers for ECC and whether or not
696  * the spare area will be transferred.
697  */
698 static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
699                                 bool transfer_spare)
700 {
701         int ecc_en_flag, transfer_spare_flag;
702 
703         /* set ECC, transfer spare bits if needed */
704         ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;
705         transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;
706 
707         /* Enable spare area/ECC per user's request. */
708         iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
709         iowrite32(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG);
710 }
711 
712 /*
713  * sends a pipeline command operation to the controller. See the Denali NAND
714  * controller's user guide for more information (section 4.2.3.6).
715  */
716 static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
717                                     bool ecc_en, bool transfer_spare,
718                                     int access_type, int op)
719 {
720         int status = PASS;
721         uint32_t page_count = 1;
722         uint32_t addr, cmd, irq_status, irq_mask;
723 
724         if (op == DENALI_READ)
725                 irq_mask = INTR_STATUS__LOAD_COMP;
726         else if (op == DENALI_WRITE)
727                 irq_mask = 0;
728         else
729                 BUG();
730 
731         setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
732 
733         clear_interrupts(denali);
734 
735         addr = BANK(denali->flash_bank) | denali->page;
736 
737         if (op == DENALI_WRITE && access_type != SPARE_ACCESS) {
738                 cmd = MODE_01 | addr;
739                 iowrite32(cmd, denali->flash_mem);
740         } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) {
741                 /* read spare area */
742                 cmd = MODE_10 | addr;
743                 index_addr(denali, cmd, access_type);
744 
745                 cmd = MODE_01 | addr;
746                 iowrite32(cmd, denali->flash_mem);
747         } else if (op == DENALI_READ) {
748                 /* setup page read request for access type */
749                 cmd = MODE_10 | addr;
750                 index_addr(denali, cmd, access_type);
751 
752                 /*
753                  * page 33 of the NAND controller spec indicates we should not
754                  * use the pipeline commands in Spare area only mode.
755                  * So we don't.
756                  */
757                 if (access_type == SPARE_ACCESS) {
758                         cmd = MODE_01 | addr;
759                         iowrite32(cmd, denali->flash_mem);
760                 } else {
761                         index_addr(denali, cmd,
762                                         PIPELINE_ACCESS | op | page_count);
763 
764                         /*
765                          * wait for command to be accepted
766                          * can always use status0 bit as the
767                          * mask is identical for each bank.
768                          */
769                         irq_status = wait_for_irq(denali, irq_mask);
770 
771                         if (irq_status == 0) {
772                                 dev_err(denali->dev,
773                                         "cmd, page, addr on timeout (0x%x, 0x%x, 0x%x)\n",
774                                         cmd, denali->page, addr);
775                                 status = FAIL;
776                         } else {
777                                 cmd = MODE_01 | addr;
778                                 iowrite32(cmd, denali->flash_mem);
779                         }
780                 }
781         }
782         return status;
783 }
784 
785 /* helper function that simply writes a buffer to the flash */
786 static int write_data_to_flash_mem(struct denali_nand_info *denali,
787                                    const uint8_t *buf, int len)
788 {
789         uint32_t *buf32;
790         int i;
791 
792         /*
793          * verify that the len is a multiple of 4.
794          * see comment in read_data_from_flash_mem()
795          */
796         BUG_ON((len % 4) != 0);
797 
798         /* write the data to the flash memory */
799         buf32 = (uint32_t *)buf;
800         for (i = 0; i < len / 4; i++)
801                 iowrite32(*buf32++, denali->flash_mem + 0x10);
802         return i * 4; /* intent is to return the number of bytes read */
803 }
804 
805 /* helper function that simply reads a buffer from the flash */
806 static int read_data_from_flash_mem(struct denali_nand_info *denali,
807                                     uint8_t *buf, int len)
808 {
809         uint32_t *buf32;
810         int i;
811 
812         /*
813          * we assume that len will be a multiple of 4, if not it would be nice
814          * to know about it ASAP rather than have random failures...
815          * This assumption is based on the fact that this function is designed
816          * to be used to read flash pages, which are typically multiples of 4.
817          */
818         BUG_ON((len % 4) != 0);
819 
820         /* transfer the data from the flash */
821         buf32 = (uint32_t *)buf;
822         for (i = 0; i < len / 4; i++)
823                 *buf32++ = ioread32(denali->flash_mem + 0x10);
824         return i * 4; /* intent is to return the number of bytes read */
825 }
826 
827 /* writes OOB data to the device */
828 static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
829 {
830         struct denali_nand_info *denali = mtd_to_denali(mtd);
831         uint32_t irq_status;
832         uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP |
833                                                 INTR_STATUS__PROGRAM_FAIL;
834         int status = 0;
835 
836         denali->page = page;
837 
838         if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS,
839                                                         DENALI_WRITE) == PASS) {
840                 write_data_to_flash_mem(denali, buf, mtd->oobsize);
841 
842                 /* wait for operation to complete */
843                 irq_status = wait_for_irq(denali, irq_mask);
844 
845                 if (irq_status == 0) {
846                         dev_err(denali->dev, "OOB write failed\n");
847                         status = -EIO;
848                 }
849         } else {
850                 dev_err(denali->dev, "unable to send pipeline command\n");
851                 status = -EIO;
852         }
853         return status;
854 }
855 
856 /* reads OOB data from the device */
857 static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
858 {
859         struct denali_nand_info *denali = mtd_to_denali(mtd);
860         uint32_t irq_mask = INTR_STATUS__LOAD_COMP;
861         uint32_t irq_status, addr, cmd;
862 
863         denali->page = page;
864 
865         if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
866                                                         DENALI_READ) == PASS) {
867                 read_data_from_flash_mem(denali, buf, mtd->oobsize);
868 
869                 /*
870                  * wait for command to be accepted
871                  * can always use status0 bit as the
872                  * mask is identical for each bank.
873                  */
874                 irq_status = wait_for_irq(denali, irq_mask);
875 
876                 if (irq_status == 0)
877                         dev_err(denali->dev, "page on OOB timeout %d\n",
878                                         denali->page);
879 
880                 /*
881                  * We set the device back to MAIN_ACCESS here as I observed
882                  * instability with the controller if you do a block erase
883                  * and the last transaction was a SPARE_ACCESS. Block erase
884                  * is reliable (according to the MTD test infrastructure)
885                  * if you are in MAIN_ACCESS.
886                  */
887                 addr = BANK(denali->flash_bank) | denali->page;
888                 cmd = MODE_10 | addr;
889                 index_addr(denali, cmd, MAIN_ACCESS);
890         }
891 }
892 
893 /*
894  * this function examines buffers to see if they contain data that
895  * indicate that the buffer is part of an erased region of flash.
896  */
897 static bool is_erased(uint8_t *buf, int len)
898 {
899         int i;
900 
901         for (i = 0; i < len; i++)
902                 if (buf[i] != 0xFF)
903                         return false;
904         return true;
905 }
906 #define ECC_SECTOR_SIZE 512
907 
908 #define ECC_SECTOR(x)   (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12)
909 #define ECC_BYTE(x)     (((x) & ECC_ERROR_ADDRESS__OFFSET))
910 #define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK)
911 #define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO__ERROR_TYPE))
912 #define ECC_ERR_DEVICE(x)       (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8)
913 #define ECC_LAST_ERR(x)         ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO)
914 
915 static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
916                        uint32_t irq_status, unsigned int *max_bitflips)
917 {
918         bool check_erased_page = false;
919         unsigned int bitflips = 0;
920 
921         if (irq_status & INTR_STATUS__ECC_ERR) {
922                 /* read the ECC errors. we'll ignore them for now */
923                 uint32_t err_address, err_correction_info, err_byte,
924                          err_sector, err_device, err_correction_value;
925                 denali_set_intr_modes(denali, false);
926 
927                 do {
928                         err_address = ioread32(denali->flash_reg +
929                                                 ECC_ERROR_ADDRESS);
930                         err_sector = ECC_SECTOR(err_address);
931                         err_byte = ECC_BYTE(err_address);
932 
933                         err_correction_info = ioread32(denali->flash_reg +
934                                                 ERR_CORRECTION_INFO);
935                         err_correction_value =
936                                 ECC_CORRECTION_VALUE(err_correction_info);
937                         err_device = ECC_ERR_DEVICE(err_correction_info);
938 
939                         if (ECC_ERROR_CORRECTABLE(err_correction_info)) {
940                                 /*
941                                  * If err_byte is larger than ECC_SECTOR_SIZE,
942                                  * means error happened in OOB, so we ignore
943                                  * it. It's no need for us to correct it
944                                  * err_device is represented the NAND error
945                                  * bits are happened in if there are more
946                                  * than one NAND connected.
947                                  */
948                                 if (err_byte < ECC_SECTOR_SIZE) {
949                                         struct mtd_info *mtd =
950                                                 nand_to_mtd(&denali->nand);
951                                         int offset;
952 
953                                         offset = (err_sector *
954                                                         ECC_SECTOR_SIZE +
955                                                         err_byte) *
956                                                         denali->devnum +
957                                                         err_device;
958                                         /* correct the ECC error */
959                                         buf[offset] ^= err_correction_value;
960                                         mtd->ecc_stats.corrected++;
961                                         bitflips++;
962                                 }
963                         } else {
964                                 /*
965                                  * if the error is not correctable, need to
966                                  * look at the page to see if it is an erased
967                                  * page. if so, then it's not a real ECC error
968                                  */
969                                 check_erased_page = true;
970                         }
971                 } while (!ECC_LAST_ERR(err_correction_info));
972                 /*
973                  * Once handle all ecc errors, controller will triger
974                  * a ECC_TRANSACTION_DONE interrupt, so here just wait
975                  * for a while for this interrupt
976                  */
977                 while (!(read_interrupt_status(denali) &
978                                 INTR_STATUS__ECC_TRANSACTION_DONE))
979                         cpu_relax();
980                 clear_interrupts(denali);
981                 denali_set_intr_modes(denali, true);
982         }
983         *max_bitflips = bitflips;
984         return check_erased_page;
985 }
986 
987 /* programs the controller to either enable/disable DMA transfers */
988 static void denali_enable_dma(struct denali_nand_info *denali, bool en)
989 {
990         iowrite32(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE);
991         ioread32(denali->flash_reg + DMA_ENABLE);
992 }
993 
994 /* setups the HW to perform the data DMA */
995 static void denali_setup_dma(struct denali_nand_info *denali, int op)
996 {
997         uint32_t mode;
998         const int page_count = 1;
999         uint32_t addr = denali->buf.dma_buf;
1000 
1001         mode = MODE_10 | BANK(denali->flash_bank);
1002 
1003         /* DMA is a four step process */
1004 
1005         /* 1. setup transfer type and # of pages */
1006         index_addr(denali, mode | denali->page, 0x2000 | op | page_count);
1007 
1008         /* 2. set memory high address bits 23:8 */
1009         index_addr(denali, mode | ((addr >> 16) << 8), 0x2200);
1010 
1011         /* 3. set memory low address bits 23:8 */
1012         index_addr(denali, mode | ((addr & 0xffff) << 8), 0x2300);
1013 
1014         /* 4. interrupt when complete, burst len = 64 bytes */
1015         index_addr(denali, mode | 0x14000, 0x2400);
1016 }
1017 
1018 /*
1019  * writes a page. user specifies type, and this function handles the
1020  * configuration details.
1021  */
1022 static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
1023                         const uint8_t *buf, bool raw_xfer)
1024 {
1025         struct denali_nand_info *denali = mtd_to_denali(mtd);
1026         dma_addr_t addr = denali->buf.dma_buf;
1027         size_t size = mtd->writesize + mtd->oobsize;
1028         uint32_t irq_status;
1029         uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP |
1030                                                 INTR_STATUS__PROGRAM_FAIL;
1031 
1032         /*
1033          * if it is a raw xfer, we want to disable ecc and send the spare area.
1034          * !raw_xfer - enable ecc
1035          * raw_xfer - transfer spare
1036          */
1037         setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer);
1038 
1039         /* copy buffer into DMA buffer */
1040         memcpy(denali->buf.buf, buf, mtd->writesize);
1041 
1042         if (raw_xfer) {
1043                 /* transfer the data to the spare area */
1044                 memcpy(denali->buf.buf + mtd->writesize,
1045                         chip->oob_poi,
1046                         mtd->oobsize);
1047         }
1048 
1049         dma_sync_single_for_device(denali->dev, addr, size, DMA_TO_DEVICE);
1050 
1051         clear_interrupts(denali);
1052         denali_enable_dma(denali, true);
1053 
1054         denali_setup_dma(denali, DENALI_WRITE);
1055 
1056         /* wait for operation to complete */
1057         irq_status = wait_for_irq(denali, irq_mask);
1058 
1059         if (irq_status == 0) {
1060                 dev_err(denali->dev, "timeout on write_page (type = %d)\n",
1061                         raw_xfer);
1062                 denali->status = NAND_STATUS_FAIL;
1063         }
1064 
1065         denali_enable_dma(denali, false);
1066         dma_sync_single_for_cpu(denali->dev, addr, size, DMA_TO_DEVICE);
1067 
1068         return 0;
1069 }
1070 
1071 /* NAND core entry points */
1072 
1073 /*
1074  * this is the callback that the NAND core calls to write a page. Since
1075  * writing a page with ECC or without is similar, all the work is done
1076  * by write_page above.
1077  */
1078 static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1079                                 const uint8_t *buf, int oob_required, int page)
1080 {
1081         /*
1082          * for regular page writes, we let HW handle all the ECC
1083          * data written to the device.
1084          */
1085         return write_page(mtd, chip, buf, false);
1086 }
1087 
1088 /*
1089  * This is the callback that the NAND core calls to write a page without ECC.
1090  * raw access is similar to ECC page writes, so all the work is done in the
1091  * write_page() function above.
1092  */
1093 static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1094                                  const uint8_t *buf, int oob_required,
1095                                  int page)
1096 {
1097         /*
1098          * for raw page writes, we want to disable ECC and simply write
1099          * whatever data is in the buffer.
1100          */
1101         return write_page(mtd, chip, buf, true);
1102 }
1103 
1104 static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1105                             int page)
1106 {
1107         return write_oob_data(mtd, chip->oob_poi, page);
1108 }
1109 
1110 static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1111                            int page)
1112 {
1113         read_oob_data(mtd, chip->oob_poi, page);
1114 
1115         return 0;
1116 }
1117 
1118 static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1119                             uint8_t *buf, int oob_required, int page)
1120 {
1121         unsigned int max_bitflips;
1122         struct denali_nand_info *denali = mtd_to_denali(mtd);
1123 
1124         dma_addr_t addr = denali->buf.dma_buf;
1125         size_t size = mtd->writesize + mtd->oobsize;
1126 
1127         uint32_t irq_status;
1128         uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE |
1129                             INTR_STATUS__ECC_ERR;
1130         bool check_erased_page = false;
1131 
1132         if (page != denali->page) {
1133                 dev_err(denali->dev,
1134                         "IN %s: page %d is not equal to denali->page %d",
1135                         __func__, page, denali->page);
1136                 BUG();
1137         }
1138 
1139         setup_ecc_for_xfer(denali, true, false);
1140 
1141         denali_enable_dma(denali, true);
1142         dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
1143 
1144         clear_interrupts(denali);
1145         denali_setup_dma(denali, DENALI_READ);
1146 
1147         /* wait for operation to complete */
1148         irq_status = wait_for_irq(denali, irq_mask);
1149 
1150         dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE);
1151 
1152         memcpy(buf, denali->buf.buf, mtd->writesize);
1153 
1154         check_erased_page = handle_ecc(denali, buf, irq_status, &max_bitflips);
1155         denali_enable_dma(denali, false);
1156 
1157         if (check_erased_page) {
1158                 read_oob_data(mtd, chip->oob_poi, denali->page);
1159 
1160                 /* check ECC failures that may have occurred on erased pages */
1161                 if (check_erased_page) {
1162                         if (!is_erased(buf, mtd->writesize))
1163                                 mtd->ecc_stats.failed++;
1164                         if (!is_erased(buf, mtd->oobsize))
1165                                 mtd->ecc_stats.failed++;
1166                 }
1167         }
1168         return max_bitflips;
1169 }
1170 
1171 static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1172                                 uint8_t *buf, int oob_required, int page)
1173 {
1174         struct denali_nand_info *denali = mtd_to_denali(mtd);
1175         dma_addr_t addr = denali->buf.dma_buf;
1176         size_t size = mtd->writesize + mtd->oobsize;
1177         uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP;
1178 
1179         if (page != denali->page) {
1180                 dev_err(denali->dev,
1181                         "IN %s: page %d is not equal to denali->page %d",
1182                         __func__, page, denali->page);
1183                 BUG();
1184         }
1185 
1186         setup_ecc_for_xfer(denali, false, true);
1187         denali_enable_dma(denali, true);
1188 
1189         dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
1190 
1191         clear_interrupts(denali);
1192         denali_setup_dma(denali, DENALI_READ);
1193 
1194         /* wait for operation to complete */
1195         wait_for_irq(denali, irq_mask);
1196 
1197         dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE);
1198 
1199         denali_enable_dma(denali, false);
1200 
1201         memcpy(buf, denali->buf.buf, mtd->writesize);
1202         memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize);
1203 
1204         return 0;
1205 }
1206 
1207 static uint8_t denali_read_byte(struct mtd_info *mtd)
1208 {
1209         struct denali_nand_info *denali = mtd_to_denali(mtd);
1210         uint8_t result = 0xff;
1211 
1212         if (denali->buf.head < denali->buf.tail)
1213                 result = denali->buf.buf[denali->buf.head++];
1214 
1215         return result;
1216 }
1217 
1218 static void denali_select_chip(struct mtd_info *mtd, int chip)
1219 {
1220         struct denali_nand_info *denali = mtd_to_denali(mtd);
1221 
1222         spin_lock_irq(&denali->irq_lock);
1223         denali->flash_bank = chip;
1224         spin_unlock_irq(&denali->irq_lock);
1225 }
1226 
1227 static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
1228 {
1229         struct denali_nand_info *denali = mtd_to_denali(mtd);
1230         int status = denali->status;
1231 
1232         denali->status = 0;
1233 
1234         return status;
1235 }
1236 
1237 static int denali_erase(struct mtd_info *mtd, int page)
1238 {
1239         struct denali_nand_info *denali = mtd_to_denali(mtd);
1240 
1241         uint32_t cmd, irq_status;
1242 
1243         clear_interrupts(denali);
1244 
1245         /* setup page read request for access type */
1246         cmd = MODE_10 | BANK(denali->flash_bank) | page;
1247         index_addr(denali, cmd, 0x1);
1248 
1249         /* wait for erase to complete or failure to occur */
1250         irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP |
1251                                         INTR_STATUS__ERASE_FAIL);
1252 
1253         return irq_status & INTR_STATUS__ERASE_FAIL ? NAND_STATUS_FAIL : PASS;
1254 }
1255 
1256 static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
1257                            int page)
1258 {
1259         struct denali_nand_info *denali = mtd_to_denali(mtd);
1260         uint32_t addr, id;
1261         int i;
1262 
1263         switch (cmd) {
1264         case NAND_CMD_PAGEPROG:
1265                 break;
1266         case NAND_CMD_STATUS:
1267                 read_status(denali);
1268                 break;
1269         case NAND_CMD_READID:
1270         case NAND_CMD_PARAM:
1271                 reset_buf(denali);
1272                 /*
1273                  * sometimes ManufactureId read from register is not right
1274                  * e.g. some of Micron MT29F32G08QAA MLC NAND chips
1275                  * So here we send READID cmd to NAND insteand
1276                  */
1277                 addr = MODE_11 | BANK(denali->flash_bank);
1278                 index_addr(denali, addr | 0, 0x90);
1279                 index_addr(denali, addr | 1, col);
1280                 for (i = 0; i < 8; i++) {
1281                         index_addr_read_data(denali, addr | 2, &id);
1282                         write_byte_to_buf(denali, id);
1283                 }
1284                 break;
1285         case NAND_CMD_READ0:
1286         case NAND_CMD_SEQIN:
1287                 denali->page = page;
1288                 break;
1289         case NAND_CMD_RESET:
1290                 reset_bank(denali);
1291                 break;
1292         case NAND_CMD_READOOB:
1293                 /* TODO: Read OOB data */
1294                 break;
1295         default:
1296                 pr_err(": unsupported command received 0x%x\n", cmd);
1297                 break;
1298         }
1299 }
1300 /* end NAND core entry points */
1301 
1302 /* Initialization code to bring the device up to a known good state */
1303 static void denali_hw_init(struct denali_nand_info *denali)
1304 {
1305         /*
1306          * tell driver how many bit controller will skip before
1307          * writing ECC code in OOB, this register may be already
1308          * set by firmware. So we read this value out.
1309          * if this value is 0, just let it be.
1310          */
1311         denali->bbtskipbytes = ioread32(denali->flash_reg +
1312                                                 SPARE_AREA_SKIP_BYTES);
1313         detect_max_banks(denali);
1314         denali_nand_reset(denali);
1315         iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED);
1316         iowrite32(CHIP_EN_DONT_CARE__FLAG,
1317                         denali->flash_reg + CHIP_ENABLE_DONT_CARE);
1318 
1319         iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
1320 
1321         /* Should set value for these registers when init */
1322         iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
1323         iowrite32(1, denali->flash_reg + ECC_ENABLE);
1324         denali_nand_timing_set(denali);
1325         denali_irq_init(denali);
1326 }
1327 
1328 /*
1329  * Althogh controller spec said SLC ECC is forceb to be 4bit,
1330  * but denali controller in MRST only support 15bit and 8bit ECC
1331  * correction
1332  */
1333 #define ECC_8BITS       14
1334 #define ECC_15BITS      26
1335 
1336 static int denali_ooblayout_ecc(struct mtd_info *mtd, int section,
1337                                 struct mtd_oob_region *oobregion)
1338 {
1339         struct denali_nand_info *denali = mtd_to_denali(mtd);
1340         struct nand_chip *chip = mtd_to_nand(mtd);
1341 
1342         if (section)
1343                 return -ERANGE;
1344 
1345         oobregion->offset = denali->bbtskipbytes;
1346         oobregion->length = chip->ecc.total;
1347 
1348         return 0;
1349 }
1350 
1351 static int denali_ooblayout_free(struct mtd_info *mtd, int section,
1352                                  struct mtd_oob_region *oobregion)
1353 {
1354         struct denali_nand_info *denali = mtd_to_denali(mtd);
1355         struct nand_chip *chip = mtd_to_nand(mtd);
1356 
1357         if (section)
1358                 return -ERANGE;
1359 
1360         oobregion->offset = chip->ecc.total + denali->bbtskipbytes;
1361         oobregion->length = mtd->oobsize - oobregion->offset;
1362 
1363         return 0;
1364 }
1365 
1366 static const struct mtd_ooblayout_ops denali_ooblayout_ops = {
1367         .ecc = denali_ooblayout_ecc,
1368         .free = denali_ooblayout_free,
1369 };
1370 
1371 static uint8_t bbt_pattern[] = {'B', 'b', 't', '' };
1372 static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
1373 
1374 static struct nand_bbt_descr bbt_main_descr = {
1375         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1376                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1377         .offs = 8,
1378         .len = 4,
1379         .veroffs = 12,
1380         .maxblocks = 4,
1381         .pattern = bbt_pattern,
1382 };
1383 
1384 static struct nand_bbt_descr bbt_mirror_descr = {
1385         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1386                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1387         .offs = 8,
1388         .len = 4,
1389         .veroffs = 12,
1390         .maxblocks = 4,
1391         .pattern = mirror_pattern,
1392 };
1393 
1394 /* initialize driver data structures */
1395 static void denali_drv_init(struct denali_nand_info *denali)
1396 {
1397         /*
1398          * the completion object will be used to notify
1399          * the callee that the interrupt is done
1400          */
1401         init_completion(&denali->complete);
1402 
1403         /*
1404          * the spinlock will be used to synchronize the ISR with any
1405          * element that might be access shared data (interrupt status)
1406          */
1407         spin_lock_init(&denali->irq_lock);
1408 
1409         /* indicate that MTD has not selected a valid bank yet */
1410         denali->flash_bank = CHIP_SELECT_INVALID;
1411 
1412         /* initialize our irq_status variable to indicate no interrupts */
1413         denali->irq_status = 0;
1414 }
1415 
1416 int denali_init(struct denali_nand_info *denali)
1417 {
1418         struct mtd_info *mtd = nand_to_mtd(&denali->nand);
1419         int ret;
1420 
1421         if (denali->platform == INTEL_CE4100) {
1422                 /*
1423                  * Due to a silicon limitation, we can only support
1424                  * ONFI timing mode 1 and below.
1425                  */
1426                 if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
1427                         pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n");
1428                         return -EINVAL;
1429                 }
1430         }
1431 
1432         /* allocate a temporary buffer for nand_scan_ident() */
1433         denali->buf.buf = devm_kzalloc(denali->dev, PAGE_SIZE,
1434                                         GFP_DMA | GFP_KERNEL);
1435         if (!denali->buf.buf)
1436                 return -ENOMEM;
1437 
1438         mtd->dev.parent = denali->dev;
1439         denali_hw_init(denali);
1440         denali_drv_init(denali);
1441 
1442         /* Request IRQ after all the hardware initialization is finished */
1443         ret = devm_request_irq(denali->dev, denali->irq, denali_isr,
1444                                IRQF_SHARED, DENALI_NAND_NAME, denali);
1445         if (ret) {
1446                 dev_err(denali->dev, "Unable to request IRQ\n");
1447                 return ret;
1448         }
1449 
1450         /* now that our ISR is registered, we can enable interrupts */
1451         denali_set_intr_modes(denali, true);
1452         mtd->name = "denali-nand";
1453 
1454         /* register the driver with the NAND core subsystem */
1455         denali->nand.select_chip = denali_select_chip;
1456         denali->nand.cmdfunc = denali_cmdfunc;
1457         denali->nand.read_byte = denali_read_byte;
1458         denali->nand.waitfunc = denali_waitfunc;
1459 
1460         /*
1461          * scan for NAND devices attached to the controller
1462          * this is the first stage in a two step process to register
1463          * with the nand subsystem
1464          */
1465         ret = nand_scan_ident(mtd, denali->max_banks, NULL);
1466         if (ret)
1467                 goto failed_req_irq;
1468 
1469         /* allocate the right size buffer now */
1470         devm_kfree(denali->dev, denali->buf.buf);
1471         denali->buf.buf = devm_kzalloc(denali->dev,
1472                              mtd->writesize + mtd->oobsize,
1473                              GFP_KERNEL);
1474         if (!denali->buf.buf) {
1475                 ret = -ENOMEM;
1476                 goto failed_req_irq;
1477         }
1478 
1479         /* Is 32-bit DMA supported? */
1480         ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32));
1481         if (ret) {
1482                 dev_err(denali->dev, "No usable DMA configuration\n");
1483                 goto failed_req_irq;
1484         }
1485 
1486         denali->buf.dma_buf = dma_map_single(denali->dev, denali->buf.buf,
1487                              mtd->writesize + mtd->oobsize,
1488                              DMA_BIDIRECTIONAL);
1489         if (dma_mapping_error(denali->dev, denali->buf.dma_buf)) {
1490                 dev_err(denali->dev, "Failed to map DMA buffer\n");
1491                 ret = -EIO;
1492                 goto failed_req_irq;
1493         }
1494 
1495         /*
1496          * support for multi nand
1497          * MTD known nothing about multi nand, so we should tell it
1498          * the real pagesize and anything necessery
1499          */
1500         denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED);
1501         denali->nand.chipsize <<= denali->devnum - 1;
1502         denali->nand.page_shift += denali->devnum - 1;
1503         denali->nand.pagemask = (denali->nand.chipsize >>
1504                                                 denali->nand.page_shift) - 1;
1505         denali->nand.bbt_erase_shift += denali->devnum - 1;
1506         denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift;
1507         denali->nand.chip_shift += denali->devnum - 1;
1508         mtd->writesize <<= denali->devnum - 1;
1509         mtd->oobsize <<= denali->devnum - 1;
1510         mtd->erasesize <<= denali->devnum - 1;
1511         mtd->size = denali->nand.numchips * denali->nand.chipsize;
1512         denali->bbtskipbytes *= denali->devnum;
1513 
1514         /*
1515          * second stage of the NAND scan
1516          * this stage requires information regarding ECC and
1517          * bad block management.
1518          */
1519 
1520         /* Bad block management */
1521         denali->nand.bbt_td = &bbt_main_descr;
1522         denali->nand.bbt_md = &bbt_mirror_descr;
1523 
1524         /* skip the scan for now until we have OOB read and write support */
1525         denali->nand.bbt_options |= NAND_BBT_USE_FLASH;
1526         denali->nand.options |= NAND_SKIP_BBTSCAN;
1527         denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
1528 
1529         /* no subpage writes on denali */
1530         denali->nand.options |= NAND_NO_SUBPAGE_WRITE;
1531 
1532         /*
1533          * Denali Controller only support 15bit and 8bit ECC in MRST,
1534          * so just let controller do 15bit ECC for MLC and 8bit ECC for
1535          * SLC if possible.
1536          * */
1537         if (!nand_is_slc(&denali->nand) &&
1538                         (mtd->oobsize > (denali->bbtskipbytes +
1539                         ECC_15BITS * (mtd->writesize /
1540                         ECC_SECTOR_SIZE)))) {
1541                 /* if MLC OOB size is large enough, use 15bit ECC*/
1542                 denali->nand.ecc.strength = 15;
1543                 denali->nand.ecc.bytes = ECC_15BITS;
1544                 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
1545         } else if (mtd->oobsize < (denali->bbtskipbytes +
1546                         ECC_8BITS * (mtd->writesize /
1547                         ECC_SECTOR_SIZE))) {
1548                 pr_err("Your NAND chip OOB is not large enough to contain 8bit ECC correction codes");
1549                 goto failed_req_irq;
1550         } else {
1551                 denali->nand.ecc.strength = 8;
1552                 denali->nand.ecc.bytes = ECC_8BITS;
1553                 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
1554         }
1555 
1556         mtd_set_ooblayout(mtd, &denali_ooblayout_ops);
1557         denali->nand.ecc.bytes *= denali->devnum;
1558         denali->nand.ecc.strength *= denali->devnum;
1559 
1560         /* override the default read operations */
1561         denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum;
1562         denali->nand.ecc.read_page = denali_read_page;
1563         denali->nand.ecc.read_page_raw = denali_read_page_raw;
1564         denali->nand.ecc.write_page = denali_write_page;
1565         denali->nand.ecc.write_page_raw = denali_write_page_raw;
1566         denali->nand.ecc.read_oob = denali_read_oob;
1567         denali->nand.ecc.write_oob = denali_write_oob;
1568         denali->nand.erase = denali_erase;
1569 
1570         ret = nand_scan_tail(mtd);
1571         if (ret)
1572                 goto failed_req_irq;
1573 
1574         ret = mtd_device_register(mtd, NULL, 0);
1575         if (ret) {
1576                 dev_err(denali->dev, "Failed to register MTD: %d\n", ret);
1577                 goto failed_req_irq;
1578         }
1579         return 0;
1580 
1581 failed_req_irq:
1582         denali_irq_cleanup(denali->irq, denali);
1583 
1584         return ret;
1585 }
1586 EXPORT_SYMBOL(denali_init);
1587 
1588 /* driver exit point */
1589 void denali_remove(struct denali_nand_info *denali)
1590 {
1591         struct mtd_info *mtd = nand_to_mtd(&denali->nand);
1592         /*
1593          * Pre-compute DMA buffer size to avoid any problems in case
1594          * nand_release() ever changes in a way that mtd->writesize and
1595          * mtd->oobsize are not reliable after this call.
1596          */
1597         int bufsize = mtd->writesize + mtd->oobsize;
1598 
1599         nand_release(mtd);
1600         denali_irq_cleanup(denali->irq, denali);
1601         dma_unmap_single(denali->dev, denali->buf.dma_buf, bufsize,
1602                          DMA_BIDIRECTIONAL);
1603 }
1604 EXPORT_SYMBOL(denali_remove);
1605 

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