Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5

Linux/drivers/mtd/nand/davinci_nand.c

  1 /*
  2  * davinci_nand.c - NAND Flash Driver for DaVinci family chips
  3  *
  4  * Copyright © 2006 Texas Instruments.
  5  *
  6  * Port to 2.6.23 Copyright © 2008 by:
  7  *   Sander Huijsen <Shuijsen@optelecom-nkf.com>
  8  *   Troy Kisky <troy.kisky@boundarydevices.com>
  9  *   Dirk Behme <Dirk.Behme@gmail.com>
 10  *
 11  * This program is free software; you can redistribute it and/or modify
 12  * it under the terms of the GNU General Public License as published by
 13  * the Free Software Foundation; either version 2 of the License, or
 14  * (at your option) any later version.
 15  *
 16  * This program is distributed in the hope that it will be useful,
 17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 19  * GNU General Public License for more details.
 20  *
 21  * You should have received a copy of the GNU General Public License
 22  * along with this program; if not, write to the Free Software
 23  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 24  */
 25 
 26 #include <linux/kernel.h>
 27 #include <linux/module.h>
 28 #include <linux/platform_device.h>
 29 #include <linux/err.h>
 30 #include <linux/clk.h>
 31 #include <linux/io.h>
 32 #include <linux/mtd/nand.h>
 33 #include <linux/mtd/partitions.h>
 34 #include <linux/slab.h>
 35 #include <linux/of_device.h>
 36 #include <linux/of.h>
 37 #include <linux/of_mtd.h>
 38 
 39 #include <linux/platform_data/mtd-davinci.h>
 40 #include <linux/platform_data/mtd-davinci-aemif.h>
 41 
 42 /*
 43  * This is a device driver for the NAND flash controller found on the
 44  * various DaVinci family chips.  It handles up to four SoC chipselects,
 45  * and some flavors of secondary chipselect (e.g. based on A12) as used
 46  * with multichip packages.
 47  *
 48  * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
 49  * available on chips like the DM355 and OMAP-L137 and needed with the
 50  * more error-prone MLC NAND chips.
 51  *
 52  * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
 53  * outputs in a "wire-AND" configuration, with no per-chip signals.
 54  */
 55 struct davinci_nand_info {
 56         struct nand_chip        chip;
 57         struct nand_ecclayout   ecclayout;
 58 
 59         struct device           *dev;
 60         struct clk              *clk;
 61 
 62         bool                    is_readmode;
 63 
 64         void __iomem            *base;
 65         void __iomem            *vaddr;
 66 
 67         uint32_t                ioaddr;
 68         uint32_t                current_cs;
 69 
 70         uint32_t                mask_chipsel;
 71         uint32_t                mask_ale;
 72         uint32_t                mask_cle;
 73 
 74         uint32_t                core_chipsel;
 75 
 76         struct davinci_aemif_timing     *timing;
 77 };
 78 
 79 static DEFINE_SPINLOCK(davinci_nand_lock);
 80 static bool ecc4_busy;
 81 
 82 static inline struct davinci_nand_info *to_davinci_nand(struct mtd_info *mtd)
 83 {
 84         return container_of(mtd_to_nand(mtd), struct davinci_nand_info, chip);
 85 }
 86 
 87 static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info,
 88                 int offset)
 89 {
 90         return __raw_readl(info->base + offset);
 91 }
 92 
 93 static inline void davinci_nand_writel(struct davinci_nand_info *info,
 94                 int offset, unsigned long value)
 95 {
 96         __raw_writel(value, info->base + offset);
 97 }
 98 
 99 /*----------------------------------------------------------------------*/
100 
101 /*
102  * Access to hardware control lines:  ALE, CLE, secondary chipselect.
103  */
104 
105 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
106                                    unsigned int ctrl)
107 {
108         struct davinci_nand_info        *info = to_davinci_nand(mtd);
109         uint32_t                        addr = info->current_cs;
110         struct nand_chip                *nand = mtd_to_nand(mtd);
111 
112         /* Did the control lines change? */
113         if (ctrl & NAND_CTRL_CHANGE) {
114                 if ((ctrl & NAND_CTRL_CLE) == NAND_CTRL_CLE)
115                         addr |= info->mask_cle;
116                 else if ((ctrl & NAND_CTRL_ALE) == NAND_CTRL_ALE)
117                         addr |= info->mask_ale;
118 
119                 nand->IO_ADDR_W = (void __iomem __force *)addr;
120         }
121 
122         if (cmd != NAND_CMD_NONE)
123                 iowrite8(cmd, nand->IO_ADDR_W);
124 }
125 
126 static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
127 {
128         struct davinci_nand_info        *info = to_davinci_nand(mtd);
129         uint32_t                        addr = info->ioaddr;
130 
131         /* maybe kick in a second chipselect */
132         if (chip > 0)
133                 addr |= info->mask_chipsel;
134         info->current_cs = addr;
135 
136         info->chip.IO_ADDR_W = (void __iomem __force *)addr;
137         info->chip.IO_ADDR_R = info->chip.IO_ADDR_W;
138 }
139 
140 /*----------------------------------------------------------------------*/
141 
142 /*
143  * 1-bit hardware ECC ... context maintained for each core chipselect
144  */
145 
146 static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd)
147 {
148         struct davinci_nand_info *info = to_davinci_nand(mtd);
149 
150         return davinci_nand_readl(info, NANDF1ECC_OFFSET
151                         + 4 * info->core_chipsel);
152 }
153 
154 static void nand_davinci_hwctl_1bit(struct mtd_info *mtd, int mode)
155 {
156         struct davinci_nand_info *info;
157         uint32_t nandcfr;
158         unsigned long flags;
159 
160         info = to_davinci_nand(mtd);
161 
162         /* Reset ECC hardware */
163         nand_davinci_readecc_1bit(mtd);
164 
165         spin_lock_irqsave(&davinci_nand_lock, flags);
166 
167         /* Restart ECC hardware */
168         nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET);
169         nandcfr |= BIT(8 + info->core_chipsel);
170         davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr);
171 
172         spin_unlock_irqrestore(&davinci_nand_lock, flags);
173 }
174 
175 /*
176  * Read hardware ECC value and pack into three bytes
177  */
178 static int nand_davinci_calculate_1bit(struct mtd_info *mtd,
179                                       const u_char *dat, u_char *ecc_code)
180 {
181         unsigned int ecc_val = nand_davinci_readecc_1bit(mtd);
182         unsigned int ecc24 = (ecc_val & 0x0fff) | ((ecc_val & 0x0fff0000) >> 4);
183 
184         /* invert so that erased block ecc is correct */
185         ecc24 = ~ecc24;
186         ecc_code[0] = (u_char)(ecc24);
187         ecc_code[1] = (u_char)(ecc24 >> 8);
188         ecc_code[2] = (u_char)(ecc24 >> 16);
189 
190         return 0;
191 }
192 
193 static int nand_davinci_correct_1bit(struct mtd_info *mtd, u_char *dat,
194                                      u_char *read_ecc, u_char *calc_ecc)
195 {
196         struct nand_chip *chip = mtd_to_nand(mtd);
197         uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) |
198                                           (read_ecc[2] << 16);
199         uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) |
200                                           (calc_ecc[2] << 16);
201         uint32_t diff = eccCalc ^ eccNand;
202 
203         if (diff) {
204                 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
205                         /* Correctable error */
206                         if ((diff >> (12 + 3)) < chip->ecc.size) {
207                                 dat[diff >> (12 + 3)] ^= BIT((diff >> 12) & 7);
208                                 return 1;
209                         } else {
210                                 return -EBADMSG;
211                         }
212                 } else if (!(diff & (diff - 1))) {
213                         /* Single bit ECC error in the ECC itself,
214                          * nothing to fix */
215                         return 1;
216                 } else {
217                         /* Uncorrectable error */
218                         return -EBADMSG;
219                 }
220 
221         }
222         return 0;
223 }
224 
225 /*----------------------------------------------------------------------*/
226 
227 /*
228  * 4-bit hardware ECC ... context maintained over entire AEMIF
229  *
230  * This is a syndrome engine, but we avoid NAND_ECC_HW_SYNDROME
231  * since that forces use of a problematic "infix OOB" layout.
232  * Among other things, it trashes manufacturer bad block markers.
233  * Also, and specific to this hardware, it ECC-protects the "prepad"
234  * in the OOB ... while having ECC protection for parts of OOB would
235  * seem useful, the current MTD stack sometimes wants to update the
236  * OOB without recomputing ECC.
237  */
238 
239 static void nand_davinci_hwctl_4bit(struct mtd_info *mtd, int mode)
240 {
241         struct davinci_nand_info *info = to_davinci_nand(mtd);
242         unsigned long flags;
243         u32 val;
244 
245         spin_lock_irqsave(&davinci_nand_lock, flags);
246 
247         /* Start 4-bit ECC calculation for read/write */
248         val = davinci_nand_readl(info, NANDFCR_OFFSET);
249         val &= ~(0x03 << 4);
250         val |= (info->core_chipsel << 4) | BIT(12);
251         davinci_nand_writel(info, NANDFCR_OFFSET, val);
252 
253         info->is_readmode = (mode == NAND_ECC_READ);
254 
255         spin_unlock_irqrestore(&davinci_nand_lock, flags);
256 }
257 
258 /* Read raw ECC code after writing to NAND. */
259 static void
260 nand_davinci_readecc_4bit(struct davinci_nand_info *info, u32 code[4])
261 {
262         const u32 mask = 0x03ff03ff;
263 
264         code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask;
265         code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask;
266         code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask;
267         code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask;
268 }
269 
270 /* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */
271 static int nand_davinci_calculate_4bit(struct mtd_info *mtd,
272                 const u_char *dat, u_char *ecc_code)
273 {
274         struct davinci_nand_info *info = to_davinci_nand(mtd);
275         u32 raw_ecc[4], *p;
276         unsigned i;
277 
278         /* After a read, terminate ECC calculation by a dummy read
279          * of some 4-bit ECC register.  ECC covers everything that
280          * was read; correct() just uses the hardware state, so
281          * ecc_code is not needed.
282          */
283         if (info->is_readmode) {
284                 davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
285                 return 0;
286         }
287 
288         /* Pack eight raw 10-bit ecc values into ten bytes, making
289          * two passes which each convert four values (in upper and
290          * lower halves of two 32-bit words) into five bytes.  The
291          * ROM boot loader uses this same packing scheme.
292          */
293         nand_davinci_readecc_4bit(info, raw_ecc);
294         for (i = 0, p = raw_ecc; i < 2; i++, p += 2) {
295                 *ecc_code++ =   p[0]        & 0xff;
296                 *ecc_code++ = ((p[0] >>  8) & 0x03) | ((p[0] >> 14) & 0xfc);
297                 *ecc_code++ = ((p[0] >> 22) & 0x0f) | ((p[1] <<  4) & 0xf0);
298                 *ecc_code++ = ((p[1] >>  4) & 0x3f) | ((p[1] >> 10) & 0xc0);
299                 *ecc_code++ =  (p[1] >> 18) & 0xff;
300         }
301 
302         return 0;
303 }
304 
305 /* Correct up to 4 bits in data we just read, using state left in the
306  * hardware plus the ecc_code computed when it was first written.
307  */
308 static int nand_davinci_correct_4bit(struct mtd_info *mtd,
309                 u_char *data, u_char *ecc_code, u_char *null)
310 {
311         int i;
312         struct davinci_nand_info *info = to_davinci_nand(mtd);
313         unsigned short ecc10[8];
314         unsigned short *ecc16;
315         u32 syndrome[4];
316         u32 ecc_state;
317         unsigned num_errors, corrected;
318         unsigned long timeo;
319 
320         /* Unpack ten bytes into eight 10 bit values.  We know we're
321          * little-endian, and use type punning for less shifting/masking.
322          */
323         if (WARN_ON(0x01 & (unsigned) ecc_code))
324                 return -EINVAL;
325         ecc16 = (unsigned short *)ecc_code;
326 
327         ecc10[0] =  (ecc16[0] >>  0) & 0x3ff;
328         ecc10[1] = ((ecc16[0] >> 10) & 0x3f) | ((ecc16[1] << 6) & 0x3c0);
329         ecc10[2] =  (ecc16[1] >>  4) & 0x3ff;
330         ecc10[3] = ((ecc16[1] >> 14) & 0x3)  | ((ecc16[2] << 2) & 0x3fc);
331         ecc10[4] =  (ecc16[2] >>  8)         | ((ecc16[3] << 8) & 0x300);
332         ecc10[5] =  (ecc16[3] >>  2) & 0x3ff;
333         ecc10[6] = ((ecc16[3] >> 12) & 0xf)  | ((ecc16[4] << 4) & 0x3f0);
334         ecc10[7] =  (ecc16[4] >>  6) & 0x3ff;
335 
336         /* Tell ECC controller about the expected ECC codes. */
337         for (i = 7; i >= 0; i--)
338                 davinci_nand_writel(info, NAND_4BIT_ECC_LOAD_OFFSET, ecc10[i]);
339 
340         /* Allow time for syndrome calculation ... then read it.
341          * A syndrome of all zeroes 0 means no detected errors.
342          */
343         davinci_nand_readl(info, NANDFSR_OFFSET);
344         nand_davinci_readecc_4bit(info, syndrome);
345         if (!(syndrome[0] | syndrome[1] | syndrome[2] | syndrome[3]))
346                 return 0;
347 
348         /*
349          * Clear any previous address calculation by doing a dummy read of an
350          * error address register.
351          */
352         davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET);
353 
354         /* Start address calculation, and wait for it to complete.
355          * We _could_ start reading more data while this is working,
356          * to speed up the overall page read.
357          */
358         davinci_nand_writel(info, NANDFCR_OFFSET,
359                         davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13));
360 
361         /*
362          * ECC_STATE field reads 0x3 (Error correction complete) immediately
363          * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately
364          * begin trying to poll for the state, you may fall right out of your
365          * loop without any of the correction calculations having taken place.
366          * The recommendation from the hardware team is to initially delay as
367          * long as ECC_STATE reads less than 4. After that, ECC HW has entered
368          * correction state.
369          */
370         timeo = jiffies + usecs_to_jiffies(100);
371         do {
372                 ecc_state = (davinci_nand_readl(info,
373                                 NANDFSR_OFFSET) >> 8) & 0x0f;
374                 cpu_relax();
375         } while ((ecc_state < 4) && time_before(jiffies, timeo));
376 
377         for (;;) {
378                 u32     fsr = davinci_nand_readl(info, NANDFSR_OFFSET);
379 
380                 switch ((fsr >> 8) & 0x0f) {
381                 case 0:         /* no error, should not happen */
382                         davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
383                         return 0;
384                 case 1:         /* five or more errors detected */
385                         davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
386                         return -EBADMSG;
387                 case 2:         /* error addresses computed */
388                 case 3:
389                         num_errors = 1 + ((fsr >> 16) & 0x03);
390                         goto correct;
391                 default:        /* still working on it */
392                         cpu_relax();
393                         continue;
394                 }
395         }
396 
397 correct:
398         /* correct each error */
399         for (i = 0, corrected = 0; i < num_errors; i++) {
400                 int error_address, error_value;
401 
402                 if (i > 1) {
403                         error_address = davinci_nand_readl(info,
404                                                 NAND_ERR_ADD2_OFFSET);
405                         error_value = davinci_nand_readl(info,
406                                                 NAND_ERR_ERRVAL2_OFFSET);
407                 } else {
408                         error_address = davinci_nand_readl(info,
409                                                 NAND_ERR_ADD1_OFFSET);
410                         error_value = davinci_nand_readl(info,
411                                                 NAND_ERR_ERRVAL1_OFFSET);
412                 }
413 
414                 if (i & 1) {
415                         error_address >>= 16;
416                         error_value >>= 16;
417                 }
418                 error_address &= 0x3ff;
419                 error_address = (512 + 7) - error_address;
420 
421                 if (error_address < 512) {
422                         data[error_address] ^= error_value;
423                         corrected++;
424                 }
425         }
426 
427         return corrected;
428 }
429 
430 /*----------------------------------------------------------------------*/
431 
432 /*
433  * NOTE:  NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's
434  * how these chips are normally wired.  This translates to both 8 and 16
435  * bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4).
436  *
437  * For now we assume that configuration, or any other one which ignores
438  * the two LSBs for NAND access ... so we can issue 32-bit reads/writes
439  * and have that transparently morphed into multiple NAND operations.
440  */
441 static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
442 {
443         struct nand_chip *chip = mtd_to_nand(mtd);
444 
445         if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
446                 ioread32_rep(chip->IO_ADDR_R, buf, len >> 2);
447         else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
448                 ioread16_rep(chip->IO_ADDR_R, buf, len >> 1);
449         else
450                 ioread8_rep(chip->IO_ADDR_R, buf, len);
451 }
452 
453 static void nand_davinci_write_buf(struct mtd_info *mtd,
454                 const uint8_t *buf, int len)
455 {
456         struct nand_chip *chip = mtd_to_nand(mtd);
457 
458         if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
459                 iowrite32_rep(chip->IO_ADDR_R, buf, len >> 2);
460         else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
461                 iowrite16_rep(chip->IO_ADDR_R, buf, len >> 1);
462         else
463                 iowrite8_rep(chip->IO_ADDR_R, buf, len);
464 }
465 
466 /*
467  * Check hardware register for wait status. Returns 1 if device is ready,
468  * 0 if it is still busy.
469  */
470 static int nand_davinci_dev_ready(struct mtd_info *mtd)
471 {
472         struct davinci_nand_info *info = to_davinci_nand(mtd);
473 
474         return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0);
475 }
476 
477 /*----------------------------------------------------------------------*/
478 
479 /* An ECC layout for using 4-bit ECC with small-page flash, storing
480  * ten ECC bytes plus the manufacturer's bad block marker byte, and
481  * and not overlapping the default BBT markers.
482  */
483 static struct nand_ecclayout hwecc4_small = {
484         .eccbytes = 10,
485         .eccpos = { 0, 1, 2, 3, 4,
486                 /* offset 5 holds the badblock marker */
487                 6, 7,
488                 13, 14, 15, },
489         .oobfree = {
490                 {.offset = 8, .length = 5, },
491                 {.offset = 16, },
492         },
493 };
494 
495 /* An ECC layout for using 4-bit ECC with large-page (2048bytes) flash,
496  * storing ten ECC bytes plus the manufacturer's bad block marker byte,
497  * and not overlapping the default BBT markers.
498  */
499 static struct nand_ecclayout hwecc4_2048 = {
500         .eccbytes = 40,
501         .eccpos = {
502                 /* at the end of spare sector */
503                 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
504                 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
505                 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
506                 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
507                 },
508         .oobfree = {
509                 /* 2 bytes at offset 0 hold manufacturer badblock markers */
510                 {.offset = 2, .length = 22, },
511                 /* 5 bytes at offset 8 hold BBT markers */
512                 /* 8 bytes at offset 16 hold JFFS2 clean markers */
513         },
514 };
515 
516 /*
517  * An ECC layout for using 4-bit ECC with large-page (4096bytes) flash,
518  * storing ten ECC bytes plus the manufacturer's bad block marker byte,
519  * and not overlapping the default BBT markers.
520  */
521 static struct nand_ecclayout hwecc4_4096 = {
522         .eccbytes = 80,
523         .eccpos = {
524                 /* at the end of spare sector */
525                 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
526                 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
527                 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
528                 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
529                 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
530                 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
531                 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
532                 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
533         },
534         .oobfree = {
535                 /* 2 bytes at offset 0 hold manufacturer badblock markers */
536                 {.offset = 2, .length = 46, },
537                 /* 5 bytes at offset 8 hold BBT markers */
538                 /* 8 bytes at offset 16 hold JFFS2 clean markers */
539         },
540 };
541 
542 #if defined(CONFIG_OF)
543 static const struct of_device_id davinci_nand_of_match[] = {
544         {.compatible = "ti,davinci-nand", },
545         {.compatible = "ti,keystone-nand", },
546         {},
547 };
548 MODULE_DEVICE_TABLE(of, davinci_nand_of_match);
549 
550 static struct davinci_nand_pdata
551         *nand_davinci_get_pdata(struct platform_device *pdev)
552 {
553         if (!dev_get_platdata(&pdev->dev) && pdev->dev.of_node) {
554                 struct davinci_nand_pdata *pdata;
555                 const char *mode;
556                 u32 prop;
557 
558                 pdata =  devm_kzalloc(&pdev->dev,
559                                 sizeof(struct davinci_nand_pdata),
560                                 GFP_KERNEL);
561                 pdev->dev.platform_data = pdata;
562                 if (!pdata)
563                         return ERR_PTR(-ENOMEM);
564                 if (!of_property_read_u32(pdev->dev.of_node,
565                         "ti,davinci-chipselect", &prop))
566                         pdev->id = prop;
567                 else
568                         return ERR_PTR(-EINVAL);
569 
570                 if (!of_property_read_u32(pdev->dev.of_node,
571                         "ti,davinci-mask-ale", &prop))
572                         pdata->mask_ale = prop;
573                 if (!of_property_read_u32(pdev->dev.of_node,
574                         "ti,davinci-mask-cle", &prop))
575                         pdata->mask_cle = prop;
576                 if (!of_property_read_u32(pdev->dev.of_node,
577                         "ti,davinci-mask-chipsel", &prop))
578                         pdata->mask_chipsel = prop;
579                 if (!of_property_read_string(pdev->dev.of_node,
580                         "nand-ecc-mode", &mode) ||
581                     !of_property_read_string(pdev->dev.of_node,
582                         "ti,davinci-ecc-mode", &mode)) {
583                         if (!strncmp("none", mode, 4))
584                                 pdata->ecc_mode = NAND_ECC_NONE;
585                         if (!strncmp("soft", mode, 4))
586                                 pdata->ecc_mode = NAND_ECC_SOFT;
587                         if (!strncmp("hw", mode, 2))
588                                 pdata->ecc_mode = NAND_ECC_HW;
589                 }
590                 if (!of_property_read_u32(pdev->dev.of_node,
591                         "ti,davinci-ecc-bits", &prop))
592                         pdata->ecc_bits = prop;
593 
594                 prop = of_get_nand_bus_width(pdev->dev.of_node);
595                 if (0 < prop || !of_property_read_u32(pdev->dev.of_node,
596                         "ti,davinci-nand-buswidth", &prop))
597                         if (prop == 16)
598                                 pdata->options |= NAND_BUSWIDTH_16;
599                 if (of_property_read_bool(pdev->dev.of_node,
600                         "nand-on-flash-bbt") ||
601                     of_property_read_bool(pdev->dev.of_node,
602                         "ti,davinci-nand-use-bbt"))
603                         pdata->bbt_options = NAND_BBT_USE_FLASH;
604 
605                 if (of_device_is_compatible(pdev->dev.of_node,
606                                             "ti,keystone-nand")) {
607                         pdata->options |= NAND_NO_SUBPAGE_WRITE;
608                 }
609         }
610 
611         return dev_get_platdata(&pdev->dev);
612 }
613 #else
614 static struct davinci_nand_pdata
615         *nand_davinci_get_pdata(struct platform_device *pdev)
616 {
617         return dev_get_platdata(&pdev->dev);
618 }
619 #endif
620 
621 static int nand_davinci_probe(struct platform_device *pdev)
622 {
623         struct davinci_nand_pdata       *pdata;
624         struct davinci_nand_info        *info;
625         struct resource                 *res1;
626         struct resource                 *res2;
627         void __iomem                    *vaddr;
628         void __iomem                    *base;
629         int                             ret;
630         uint32_t                        val;
631         nand_ecc_modes_t                ecc_mode;
632         struct mtd_info                 *mtd;
633 
634         pdata = nand_davinci_get_pdata(pdev);
635         if (IS_ERR(pdata))
636                 return PTR_ERR(pdata);
637 
638         /* insist on board-specific configuration */
639         if (!pdata)
640                 return -ENODEV;
641 
642         /* which external chipselect will we be managing? */
643         if (pdev->id < 0 || pdev->id > 3)
644                 return -ENODEV;
645 
646         info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
647         if (!info)
648                 return -ENOMEM;
649 
650         platform_set_drvdata(pdev, info);
651 
652         res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
653         res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
654         if (!res1 || !res2) {
655                 dev_err(&pdev->dev, "resource missing\n");
656                 return -EINVAL;
657         }
658 
659         vaddr = devm_ioremap_resource(&pdev->dev, res1);
660         if (IS_ERR(vaddr))
661                 return PTR_ERR(vaddr);
662 
663         /*
664          * This registers range is used to setup NAND settings. In case with
665          * TI AEMIF driver, the same memory address range is requested already
666          * by AEMIF, so we cannot request it twice, just ioremap.
667          * The AEMIF and NAND drivers not use the same registers in this range.
668          */
669         base = devm_ioremap(&pdev->dev, res2->start, resource_size(res2));
670         if (!base) {
671                 dev_err(&pdev->dev, "ioremap failed for resource %pR\n", res2);
672                 return -EADDRNOTAVAIL;
673         }
674 
675         info->dev               = &pdev->dev;
676         info->base              = base;
677         info->vaddr             = vaddr;
678 
679         mtd                     = nand_to_mtd(&info->chip);
680         mtd->dev.parent         = &pdev->dev;
681         nand_set_flash_node(&info->chip, pdev->dev.of_node);
682 
683         info->chip.IO_ADDR_R    = vaddr;
684         info->chip.IO_ADDR_W    = vaddr;
685         info->chip.chip_delay   = 0;
686         info->chip.select_chip  = nand_davinci_select_chip;
687 
688         /* options such as NAND_BBT_USE_FLASH */
689         info->chip.bbt_options  = pdata->bbt_options;
690         /* options such as 16-bit widths */
691         info->chip.options      = pdata->options;
692         info->chip.bbt_td       = pdata->bbt_td;
693         info->chip.bbt_md       = pdata->bbt_md;
694         info->timing            = pdata->timing;
695 
696         info->ioaddr            = (uint32_t __force) vaddr;
697 
698         info->current_cs        = info->ioaddr;
699         info->core_chipsel      = pdev->id;
700         info->mask_chipsel      = pdata->mask_chipsel;
701 
702         /* use nandboot-capable ALE/CLE masks by default */
703         info->mask_ale          = pdata->mask_ale ? : MASK_ALE;
704         info->mask_cle          = pdata->mask_cle ? : MASK_CLE;
705 
706         /* Set address of hardware control function */
707         info->chip.cmd_ctrl     = nand_davinci_hwcontrol;
708         info->chip.dev_ready    = nand_davinci_dev_ready;
709 
710         /* Speed up buffer I/O */
711         info->chip.read_buf     = nand_davinci_read_buf;
712         info->chip.write_buf    = nand_davinci_write_buf;
713 
714         /* Use board-specific ECC config */
715         ecc_mode                = pdata->ecc_mode;
716 
717         ret = -EINVAL;
718         switch (ecc_mode) {
719         case NAND_ECC_NONE:
720         case NAND_ECC_SOFT:
721                 pdata->ecc_bits = 0;
722                 break;
723         case NAND_ECC_HW:
724                 if (pdata->ecc_bits == 4) {
725                         /* No sanity checks:  CPUs must support this,
726                          * and the chips may not use NAND_BUSWIDTH_16.
727                          */
728 
729                         /* No sharing 4-bit hardware between chipselects yet */
730                         spin_lock_irq(&davinci_nand_lock);
731                         if (ecc4_busy)
732                                 ret = -EBUSY;
733                         else
734                                 ecc4_busy = true;
735                         spin_unlock_irq(&davinci_nand_lock);
736 
737                         if (ret == -EBUSY)
738                                 return ret;
739 
740                         info->chip.ecc.calculate = nand_davinci_calculate_4bit;
741                         info->chip.ecc.correct = nand_davinci_correct_4bit;
742                         info->chip.ecc.hwctl = nand_davinci_hwctl_4bit;
743                         info->chip.ecc.bytes = 10;
744                         info->chip.ecc.options = NAND_ECC_GENERIC_ERASED_CHECK;
745                 } else {
746                         info->chip.ecc.calculate = nand_davinci_calculate_1bit;
747                         info->chip.ecc.correct = nand_davinci_correct_1bit;
748                         info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
749                         info->chip.ecc.bytes = 3;
750                 }
751                 info->chip.ecc.size = 512;
752                 info->chip.ecc.strength = pdata->ecc_bits;
753                 break;
754         default:
755                 return -EINVAL;
756         }
757         info->chip.ecc.mode = ecc_mode;
758 
759         info->clk = devm_clk_get(&pdev->dev, "aemif");
760         if (IS_ERR(info->clk)) {
761                 ret = PTR_ERR(info->clk);
762                 dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret);
763                 return ret;
764         }
765 
766         ret = clk_prepare_enable(info->clk);
767         if (ret < 0) {
768                 dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n",
769                         ret);
770                 goto err_clk_enable;
771         }
772 
773         spin_lock_irq(&davinci_nand_lock);
774 
775         /* put CSxNAND into NAND mode */
776         val = davinci_nand_readl(info, NANDFCR_OFFSET);
777         val |= BIT(info->core_chipsel);
778         davinci_nand_writel(info, NANDFCR_OFFSET, val);
779 
780         spin_unlock_irq(&davinci_nand_lock);
781 
782         /* Scan to find existence of the device(s) */
783         ret = nand_scan_ident(mtd, pdata->mask_chipsel ? 2 : 1, NULL);
784         if (ret < 0) {
785                 dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
786                 goto err;
787         }
788 
789         /* Update ECC layout if needed ... for 1-bit HW ECC, the default
790          * is OK, but it allocates 6 bytes when only 3 are needed (for
791          * each 512 bytes).  For the 4-bit HW ECC, that default is not
792          * usable:  10 bytes are needed, not 6.
793          */
794         if (pdata->ecc_bits == 4) {
795                 int     chunks = mtd->writesize / 512;
796 
797                 if (!chunks || mtd->oobsize < 16) {
798                         dev_dbg(&pdev->dev, "too small\n");
799                         ret = -EINVAL;
800                         goto err;
801                 }
802 
803                 /* For small page chips, preserve the manufacturer's
804                  * badblock marking data ... and make sure a flash BBT
805                  * table marker fits in the free bytes.
806                  */
807                 if (chunks == 1) {
808                         info->ecclayout = hwecc4_small;
809                         info->ecclayout.oobfree[1].length = mtd->oobsize - 16;
810                         goto syndrome_done;
811                 }
812                 if (chunks == 4) {
813                         info->ecclayout = hwecc4_2048;
814                         info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST;
815                         goto syndrome_done;
816                 }
817                 if (chunks == 8) {
818                         info->ecclayout = hwecc4_4096;
819                         info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST;
820                         goto syndrome_done;
821                 }
822 
823                 ret = -EIO;
824                 goto err;
825 
826 syndrome_done:
827                 info->chip.ecc.layout = &info->ecclayout;
828         }
829 
830         ret = nand_scan_tail(mtd);
831         if (ret < 0)
832                 goto err;
833 
834         if (pdata->parts)
835                 ret = mtd_device_parse_register(mtd, NULL, NULL,
836                                         pdata->parts, pdata->nr_parts);
837         else
838                 ret = mtd_device_register(mtd, NULL, 0);
839         if (ret < 0)
840                 goto err;
841 
842         val = davinci_nand_readl(info, NRCSR_OFFSET);
843         dev_info(&pdev->dev, "controller rev. %d.%d\n",
844                (val >> 8) & 0xff, val & 0xff);
845 
846         return 0;
847 
848 err:
849         clk_disable_unprepare(info->clk);
850 
851 err_clk_enable:
852         spin_lock_irq(&davinci_nand_lock);
853         if (ecc_mode == NAND_ECC_HW_SYNDROME)
854                 ecc4_busy = false;
855         spin_unlock_irq(&davinci_nand_lock);
856         return ret;
857 }
858 
859 static int nand_davinci_remove(struct platform_device *pdev)
860 {
861         struct davinci_nand_info *info = platform_get_drvdata(pdev);
862 
863         spin_lock_irq(&davinci_nand_lock);
864         if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME)
865                 ecc4_busy = false;
866         spin_unlock_irq(&davinci_nand_lock);
867 
868         nand_release(nand_to_mtd(&info->chip));
869 
870         clk_disable_unprepare(info->clk);
871 
872         return 0;
873 }
874 
875 static struct platform_driver nand_davinci_driver = {
876         .probe          = nand_davinci_probe,
877         .remove         = nand_davinci_remove,
878         .driver         = {
879                 .name   = "davinci_nand",
880                 .of_match_table = of_match_ptr(davinci_nand_of_match),
881         },
882 };
883 MODULE_ALIAS("platform:davinci_nand");
884 
885 module_platform_driver(nand_davinci_driver);
886 
887 MODULE_LICENSE("GPL");
888 MODULE_AUTHOR("Texas Instruments");
889 MODULE_DESCRIPTION("Davinci NAND flash driver");
890 
891 

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