Version:  2.6.34 2.6.35 2.6.36 2.6.37 2.6.38 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14

Linux/drivers/mtd/nand/davinci_nand.c

  1 /*
  2  * davinci_nand.c - NAND Flash Driver for DaVinci family chips
  3  *
  4  * Copyright © 2006 Texas Instruments.
  5  *
  6  * Port to 2.6.23 Copyright © 2008 by:
  7  *   Sander Huijsen <Shuijsen@optelecom-nkf.com>
  8  *   Troy Kisky <troy.kisky@boundarydevices.com>
  9  *   Dirk Behme <Dirk.Behme@gmail.com>
 10  *
 11  * This program is free software; you can redistribute it and/or modify
 12  * it under the terms of the GNU General Public License as published by
 13  * the Free Software Foundation; either version 2 of the License, or
 14  * (at your option) any later version.
 15  *
 16  * This program is distributed in the hope that it will be useful,
 17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 19  * GNU General Public License for more details.
 20  *
 21  * You should have received a copy of the GNU General Public License
 22  * along with this program; if not, write to the Free Software
 23  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 24  */
 25 
 26 #include <linux/kernel.h>
 27 #include <linux/init.h>
 28 #include <linux/module.h>
 29 #include <linux/platform_device.h>
 30 #include <linux/err.h>
 31 #include <linux/clk.h>
 32 #include <linux/io.h>
 33 #include <linux/mtd/nand.h>
 34 #include <linux/mtd/partitions.h>
 35 #include <linux/slab.h>
 36 #include <linux/of_device.h>
 37 #include <linux/of.h>
 38 #include <linux/of_mtd.h>
 39 
 40 #include <linux/platform_data/mtd-davinci.h>
 41 #include <linux/platform_data/mtd-davinci-aemif.h>
 42 
 43 /*
 44  * This is a device driver for the NAND flash controller found on the
 45  * various DaVinci family chips.  It handles up to four SoC chipselects,
 46  * and some flavors of secondary chipselect (e.g. based on A12) as used
 47  * with multichip packages.
 48  *
 49  * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
 50  * available on chips like the DM355 and OMAP-L137 and needed with the
 51  * more error-prone MLC NAND chips.
 52  *
 53  * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
 54  * outputs in a "wire-AND" configuration, with no per-chip signals.
 55  */
 56 struct davinci_nand_info {
 57         struct mtd_info         mtd;
 58         struct nand_chip        chip;
 59         struct nand_ecclayout   ecclayout;
 60 
 61         struct device           *dev;
 62         struct clk              *clk;
 63 
 64         bool                    is_readmode;
 65 
 66         void __iomem            *base;
 67         void __iomem            *vaddr;
 68 
 69         uint32_t                ioaddr;
 70         uint32_t                current_cs;
 71 
 72         uint32_t                mask_chipsel;
 73         uint32_t                mask_ale;
 74         uint32_t                mask_cle;
 75 
 76         uint32_t                core_chipsel;
 77 
 78         struct davinci_aemif_timing     *timing;
 79 };
 80 
 81 static DEFINE_SPINLOCK(davinci_nand_lock);
 82 static bool ecc4_busy;
 83 
 84 #define to_davinci_nand(m) container_of(m, struct davinci_nand_info, mtd)
 85 
 86 
 87 static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info,
 88                 int offset)
 89 {
 90         return __raw_readl(info->base + offset);
 91 }
 92 
 93 static inline void davinci_nand_writel(struct davinci_nand_info *info,
 94                 int offset, unsigned long value)
 95 {
 96         __raw_writel(value, info->base + offset);
 97 }
 98 
 99 /*----------------------------------------------------------------------*/
100 
101 /*
102  * Access to hardware control lines:  ALE, CLE, secondary chipselect.
103  */
104 
105 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
106                                    unsigned int ctrl)
107 {
108         struct davinci_nand_info        *info = to_davinci_nand(mtd);
109         uint32_t                        addr = info->current_cs;
110         struct nand_chip                *nand = mtd->priv;
111 
112         /* Did the control lines change? */
113         if (ctrl & NAND_CTRL_CHANGE) {
114                 if ((ctrl & NAND_CTRL_CLE) == NAND_CTRL_CLE)
115                         addr |= info->mask_cle;
116                 else if ((ctrl & NAND_CTRL_ALE) == NAND_CTRL_ALE)
117                         addr |= info->mask_ale;
118 
119                 nand->IO_ADDR_W = (void __iomem __force *)addr;
120         }
121 
122         if (cmd != NAND_CMD_NONE)
123                 iowrite8(cmd, nand->IO_ADDR_W);
124 }
125 
126 static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
127 {
128         struct davinci_nand_info        *info = to_davinci_nand(mtd);
129         uint32_t                        addr = info->ioaddr;
130 
131         /* maybe kick in a second chipselect */
132         if (chip > 0)
133                 addr |= info->mask_chipsel;
134         info->current_cs = addr;
135 
136         info->chip.IO_ADDR_W = (void __iomem __force *)addr;
137         info->chip.IO_ADDR_R = info->chip.IO_ADDR_W;
138 }
139 
140 /*----------------------------------------------------------------------*/
141 
142 /*
143  * 1-bit hardware ECC ... context maintained for each core chipselect
144  */
145 
146 static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd)
147 {
148         struct davinci_nand_info *info = to_davinci_nand(mtd);
149 
150         return davinci_nand_readl(info, NANDF1ECC_OFFSET
151                         + 4 * info->core_chipsel);
152 }
153 
154 static void nand_davinci_hwctl_1bit(struct mtd_info *mtd, int mode)
155 {
156         struct davinci_nand_info *info;
157         uint32_t nandcfr;
158         unsigned long flags;
159 
160         info = to_davinci_nand(mtd);
161 
162         /* Reset ECC hardware */
163         nand_davinci_readecc_1bit(mtd);
164 
165         spin_lock_irqsave(&davinci_nand_lock, flags);
166 
167         /* Restart ECC hardware */
168         nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET);
169         nandcfr |= BIT(8 + info->core_chipsel);
170         davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr);
171 
172         spin_unlock_irqrestore(&davinci_nand_lock, flags);
173 }
174 
175 /*
176  * Read hardware ECC value and pack into three bytes
177  */
178 static int nand_davinci_calculate_1bit(struct mtd_info *mtd,
179                                       const u_char *dat, u_char *ecc_code)
180 {
181         unsigned int ecc_val = nand_davinci_readecc_1bit(mtd);
182         unsigned int ecc24 = (ecc_val & 0x0fff) | ((ecc_val & 0x0fff0000) >> 4);
183 
184         /* invert so that erased block ecc is correct */
185         ecc24 = ~ecc24;
186         ecc_code[0] = (u_char)(ecc24);
187         ecc_code[1] = (u_char)(ecc24 >> 8);
188         ecc_code[2] = (u_char)(ecc24 >> 16);
189 
190         return 0;
191 }
192 
193 static int nand_davinci_correct_1bit(struct mtd_info *mtd, u_char *dat,
194                                      u_char *read_ecc, u_char *calc_ecc)
195 {
196         struct nand_chip *chip = mtd->priv;
197         uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) |
198                                           (read_ecc[2] << 16);
199         uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) |
200                                           (calc_ecc[2] << 16);
201         uint32_t diff = eccCalc ^ eccNand;
202 
203         if (diff) {
204                 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
205                         /* Correctable error */
206                         if ((diff >> (12 + 3)) < chip->ecc.size) {
207                                 dat[diff >> (12 + 3)] ^= BIT((diff >> 12) & 7);
208                                 return 1;
209                         } else {
210                                 return -1;
211                         }
212                 } else if (!(diff & (diff - 1))) {
213                         /* Single bit ECC error in the ECC itself,
214                          * nothing to fix */
215                         return 1;
216                 } else {
217                         /* Uncorrectable error */
218                         return -1;
219                 }
220 
221         }
222         return 0;
223 }
224 
225 /*----------------------------------------------------------------------*/
226 
227 /*
228  * 4-bit hardware ECC ... context maintained over entire AEMIF
229  *
230  * This is a syndrome engine, but we avoid NAND_ECC_HW_SYNDROME
231  * since that forces use of a problematic "infix OOB" layout.
232  * Among other things, it trashes manufacturer bad block markers.
233  * Also, and specific to this hardware, it ECC-protects the "prepad"
234  * in the OOB ... while having ECC protection for parts of OOB would
235  * seem useful, the current MTD stack sometimes wants to update the
236  * OOB without recomputing ECC.
237  */
238 
239 static void nand_davinci_hwctl_4bit(struct mtd_info *mtd, int mode)
240 {
241         struct davinci_nand_info *info = to_davinci_nand(mtd);
242         unsigned long flags;
243         u32 val;
244 
245         spin_lock_irqsave(&davinci_nand_lock, flags);
246 
247         /* Start 4-bit ECC calculation for read/write */
248         val = davinci_nand_readl(info, NANDFCR_OFFSET);
249         val &= ~(0x03 << 4);
250         val |= (info->core_chipsel << 4) | BIT(12);
251         davinci_nand_writel(info, NANDFCR_OFFSET, val);
252 
253         info->is_readmode = (mode == NAND_ECC_READ);
254 
255         spin_unlock_irqrestore(&davinci_nand_lock, flags);
256 }
257 
258 /* Read raw ECC code after writing to NAND. */
259 static void
260 nand_davinci_readecc_4bit(struct davinci_nand_info *info, u32 code[4])
261 {
262         const u32 mask = 0x03ff03ff;
263 
264         code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask;
265         code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask;
266         code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask;
267         code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask;
268 }
269 
270 /* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */
271 static int nand_davinci_calculate_4bit(struct mtd_info *mtd,
272                 const u_char *dat, u_char *ecc_code)
273 {
274         struct davinci_nand_info *info = to_davinci_nand(mtd);
275         u32 raw_ecc[4], *p;
276         unsigned i;
277 
278         /* After a read, terminate ECC calculation by a dummy read
279          * of some 4-bit ECC register.  ECC covers everything that
280          * was read; correct() just uses the hardware state, so
281          * ecc_code is not needed.
282          */
283         if (info->is_readmode) {
284                 davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
285                 return 0;
286         }
287 
288         /* Pack eight raw 10-bit ecc values into ten bytes, making
289          * two passes which each convert four values (in upper and
290          * lower halves of two 32-bit words) into five bytes.  The
291          * ROM boot loader uses this same packing scheme.
292          */
293         nand_davinci_readecc_4bit(info, raw_ecc);
294         for (i = 0, p = raw_ecc; i < 2; i++, p += 2) {
295                 *ecc_code++ =   p[0]        & 0xff;
296                 *ecc_code++ = ((p[0] >>  8) & 0x03) | ((p[0] >> 14) & 0xfc);
297                 *ecc_code++ = ((p[0] >> 22) & 0x0f) | ((p[1] <<  4) & 0xf0);
298                 *ecc_code++ = ((p[1] >>  4) & 0x3f) | ((p[1] >> 10) & 0xc0);
299                 *ecc_code++ =  (p[1] >> 18) & 0xff;
300         }
301 
302         return 0;
303 }
304 
305 /* Correct up to 4 bits in data we just read, using state left in the
306  * hardware plus the ecc_code computed when it was first written.
307  */
308 static int nand_davinci_correct_4bit(struct mtd_info *mtd,
309                 u_char *data, u_char *ecc_code, u_char *null)
310 {
311         int i;
312         struct davinci_nand_info *info = to_davinci_nand(mtd);
313         unsigned short ecc10[8];
314         unsigned short *ecc16;
315         u32 syndrome[4];
316         u32 ecc_state;
317         unsigned num_errors, corrected;
318         unsigned long timeo;
319 
320         /* All bytes 0xff?  It's an erased page; ignore its ECC. */
321         for (i = 0; i < 10; i++) {
322                 if (ecc_code[i] != 0xff)
323                         goto compare;
324         }
325         return 0;
326 
327 compare:
328         /* Unpack ten bytes into eight 10 bit values.  We know we're
329          * little-endian, and use type punning for less shifting/masking.
330          */
331         if (WARN_ON(0x01 & (unsigned) ecc_code))
332                 return -EINVAL;
333         ecc16 = (unsigned short *)ecc_code;
334 
335         ecc10[0] =  (ecc16[0] >>  0) & 0x3ff;
336         ecc10[1] = ((ecc16[0] >> 10) & 0x3f) | ((ecc16[1] << 6) & 0x3c0);
337         ecc10[2] =  (ecc16[1] >>  4) & 0x3ff;
338         ecc10[3] = ((ecc16[1] >> 14) & 0x3)  | ((ecc16[2] << 2) & 0x3fc);
339         ecc10[4] =  (ecc16[2] >>  8)         | ((ecc16[3] << 8) & 0x300);
340         ecc10[5] =  (ecc16[3] >>  2) & 0x3ff;
341         ecc10[6] = ((ecc16[3] >> 12) & 0xf)  | ((ecc16[4] << 4) & 0x3f0);
342         ecc10[7] =  (ecc16[4] >>  6) & 0x3ff;
343 
344         /* Tell ECC controller about the expected ECC codes. */
345         for (i = 7; i >= 0; i--)
346                 davinci_nand_writel(info, NAND_4BIT_ECC_LOAD_OFFSET, ecc10[i]);
347 
348         /* Allow time for syndrome calculation ... then read it.
349          * A syndrome of all zeroes 0 means no detected errors.
350          */
351         davinci_nand_readl(info, NANDFSR_OFFSET);
352         nand_davinci_readecc_4bit(info, syndrome);
353         if (!(syndrome[0] | syndrome[1] | syndrome[2] | syndrome[3]))
354                 return 0;
355 
356         /*
357          * Clear any previous address calculation by doing a dummy read of an
358          * error address register.
359          */
360         davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET);
361 
362         /* Start address calculation, and wait for it to complete.
363          * We _could_ start reading more data while this is working,
364          * to speed up the overall page read.
365          */
366         davinci_nand_writel(info, NANDFCR_OFFSET,
367                         davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13));
368 
369         /*
370          * ECC_STATE field reads 0x3 (Error correction complete) immediately
371          * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately
372          * begin trying to poll for the state, you may fall right out of your
373          * loop without any of the correction calculations having taken place.
374          * The recommendation from the hardware team is to initially delay as
375          * long as ECC_STATE reads less than 4. After that, ECC HW has entered
376          * correction state.
377          */
378         timeo = jiffies + usecs_to_jiffies(100);
379         do {
380                 ecc_state = (davinci_nand_readl(info,
381                                 NANDFSR_OFFSET) >> 8) & 0x0f;
382                 cpu_relax();
383         } while ((ecc_state < 4) && time_before(jiffies, timeo));
384 
385         for (;;) {
386                 u32     fsr = davinci_nand_readl(info, NANDFSR_OFFSET);
387 
388                 switch ((fsr >> 8) & 0x0f) {
389                 case 0:         /* no error, should not happen */
390                         davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
391                         return 0;
392                 case 1:         /* five or more errors detected */
393                         davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
394                         return -EIO;
395                 case 2:         /* error addresses computed */
396                 case 3:
397                         num_errors = 1 + ((fsr >> 16) & 0x03);
398                         goto correct;
399                 default:        /* still working on it */
400                         cpu_relax();
401                         continue;
402                 }
403         }
404 
405 correct:
406         /* correct each error */
407         for (i = 0, corrected = 0; i < num_errors; i++) {
408                 int error_address, error_value;
409 
410                 if (i > 1) {
411                         error_address = davinci_nand_readl(info,
412                                                 NAND_ERR_ADD2_OFFSET);
413                         error_value = davinci_nand_readl(info,
414                                                 NAND_ERR_ERRVAL2_OFFSET);
415                 } else {
416                         error_address = davinci_nand_readl(info,
417                                                 NAND_ERR_ADD1_OFFSET);
418                         error_value = davinci_nand_readl(info,
419                                                 NAND_ERR_ERRVAL1_OFFSET);
420                 }
421 
422                 if (i & 1) {
423                         error_address >>= 16;
424                         error_value >>= 16;
425                 }
426                 error_address &= 0x3ff;
427                 error_address = (512 + 7) - error_address;
428 
429                 if (error_address < 512) {
430                         data[error_address] ^= error_value;
431                         corrected++;
432                 }
433         }
434 
435         return corrected;
436 }
437 
438 /*----------------------------------------------------------------------*/
439 
440 /*
441  * NOTE:  NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's
442  * how these chips are normally wired.  This translates to both 8 and 16
443  * bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4).
444  *
445  * For now we assume that configuration, or any other one which ignores
446  * the two LSBs for NAND access ... so we can issue 32-bit reads/writes
447  * and have that transparently morphed into multiple NAND operations.
448  */
449 static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
450 {
451         struct nand_chip *chip = mtd->priv;
452 
453         if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
454                 ioread32_rep(chip->IO_ADDR_R, buf, len >> 2);
455         else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
456                 ioread16_rep(chip->IO_ADDR_R, buf, len >> 1);
457         else
458                 ioread8_rep(chip->IO_ADDR_R, buf, len);
459 }
460 
461 static void nand_davinci_write_buf(struct mtd_info *mtd,
462                 const uint8_t *buf, int len)
463 {
464         struct nand_chip *chip = mtd->priv;
465 
466         if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
467                 iowrite32_rep(chip->IO_ADDR_R, buf, len >> 2);
468         else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
469                 iowrite16_rep(chip->IO_ADDR_R, buf, len >> 1);
470         else
471                 iowrite8_rep(chip->IO_ADDR_R, buf, len);
472 }
473 
474 /*
475  * Check hardware register for wait status. Returns 1 if device is ready,
476  * 0 if it is still busy.
477  */
478 static int nand_davinci_dev_ready(struct mtd_info *mtd)
479 {
480         struct davinci_nand_info *info = to_davinci_nand(mtd);
481 
482         return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0);
483 }
484 
485 /*----------------------------------------------------------------------*/
486 
487 /* An ECC layout for using 4-bit ECC with small-page flash, storing
488  * ten ECC bytes plus the manufacturer's bad block marker byte, and
489  * and not overlapping the default BBT markers.
490  */
491 static struct nand_ecclayout hwecc4_small = {
492         .eccbytes = 10,
493         .eccpos = { 0, 1, 2, 3, 4,
494                 /* offset 5 holds the badblock marker */
495                 6, 7,
496                 13, 14, 15, },
497         .oobfree = {
498                 {.offset = 8, .length = 5, },
499                 {.offset = 16, },
500         },
501 };
502 
503 /* An ECC layout for using 4-bit ECC with large-page (2048bytes) flash,
504  * storing ten ECC bytes plus the manufacturer's bad block marker byte,
505  * and not overlapping the default BBT markers.
506  */
507 static struct nand_ecclayout hwecc4_2048 = {
508         .eccbytes = 40,
509         .eccpos = {
510                 /* at the end of spare sector */
511                 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
512                 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
513                 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
514                 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
515                 },
516         .oobfree = {
517                 /* 2 bytes at offset 0 hold manufacturer badblock markers */
518                 {.offset = 2, .length = 22, },
519                 /* 5 bytes at offset 8 hold BBT markers */
520                 /* 8 bytes at offset 16 hold JFFS2 clean markers */
521         },
522 };
523 
524 #if defined(CONFIG_OF)
525 static const struct of_device_id davinci_nand_of_match[] = {
526         {.compatible = "ti,davinci-nand", },
527         {},
528 };
529 MODULE_DEVICE_TABLE(of, davinci_nand_of_match);
530 
531 static struct davinci_nand_pdata
532         *nand_davinci_get_pdata(struct platform_device *pdev)
533 {
534         if (!dev_get_platdata(&pdev->dev) && pdev->dev.of_node) {
535                 struct davinci_nand_pdata *pdata;
536                 const char *mode;
537                 u32 prop;
538 
539                 pdata =  devm_kzalloc(&pdev->dev,
540                                 sizeof(struct davinci_nand_pdata),
541                                 GFP_KERNEL);
542                 pdev->dev.platform_data = pdata;
543                 if (!pdata)
544                         return ERR_PTR(-ENOMEM);
545                 if (!of_property_read_u32(pdev->dev.of_node,
546                         "ti,davinci-chipselect", &prop))
547                         pdev->id = prop;
548                 else
549                         return ERR_PTR(-EINVAL);
550 
551                 if (!of_property_read_u32(pdev->dev.of_node,
552                         "ti,davinci-mask-ale", &prop))
553                         pdata->mask_ale = prop;
554                 if (!of_property_read_u32(pdev->dev.of_node,
555                         "ti,davinci-mask-cle", &prop))
556                         pdata->mask_cle = prop;
557                 if (!of_property_read_u32(pdev->dev.of_node,
558                         "ti,davinci-mask-chipsel", &prop))
559                         pdata->mask_chipsel = prop;
560                 if (!of_property_read_string(pdev->dev.of_node,
561                         "nand-ecc-mode", &mode) ||
562                     !of_property_read_string(pdev->dev.of_node,
563                         "ti,davinci-ecc-mode", &mode)) {
564                         if (!strncmp("none", mode, 4))
565                                 pdata->ecc_mode = NAND_ECC_NONE;
566                         if (!strncmp("soft", mode, 4))
567                                 pdata->ecc_mode = NAND_ECC_SOFT;
568                         if (!strncmp("hw", mode, 2))
569                                 pdata->ecc_mode = NAND_ECC_HW;
570                 }
571                 if (!of_property_read_u32(pdev->dev.of_node,
572                         "ti,davinci-ecc-bits", &prop))
573                         pdata->ecc_bits = prop;
574 
575                 prop = of_get_nand_bus_width(pdev->dev.of_node);
576                 if (0 < prop || !of_property_read_u32(pdev->dev.of_node,
577                         "ti,davinci-nand-buswidth", &prop))
578                         if (prop == 16)
579                                 pdata->options |= NAND_BUSWIDTH_16;
580                 if (of_property_read_bool(pdev->dev.of_node,
581                         "nand-on-flash-bbt") ||
582                     of_property_read_bool(pdev->dev.of_node,
583                         "ti,davinci-nand-use-bbt"))
584                         pdata->bbt_options = NAND_BBT_USE_FLASH;
585         }
586 
587         return dev_get_platdata(&pdev->dev);
588 }
589 #else
590 static struct davinci_nand_pdata
591         *nand_davinci_get_pdata(struct platform_device *pdev)
592 {
593         return dev_get_platdata(&pdev->dev);
594 }
595 #endif
596 
597 static int nand_davinci_probe(struct platform_device *pdev)
598 {
599         struct davinci_nand_pdata       *pdata;
600         struct davinci_nand_info        *info;
601         struct resource                 *res1;
602         struct resource                 *res2;
603         void __iomem                    *vaddr;
604         void __iomem                    *base;
605         int                             ret;
606         uint32_t                        val;
607         nand_ecc_modes_t                ecc_mode;
608 
609         pdata = nand_davinci_get_pdata(pdev);
610         if (IS_ERR(pdata))
611                 return PTR_ERR(pdata);
612 
613         /* insist on board-specific configuration */
614         if (!pdata)
615                 return -ENODEV;
616 
617         /* which external chipselect will we be managing? */
618         if (pdev->id < 0 || pdev->id > 3)
619                 return -ENODEV;
620 
621         info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
622         if (!info)
623                 return -ENOMEM;
624 
625         platform_set_drvdata(pdev, info);
626 
627         res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
628         res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
629         if (!res1 || !res2) {
630                 dev_err(&pdev->dev, "resource missing\n");
631                 return -EINVAL;
632         }
633 
634         vaddr = devm_ioremap_resource(&pdev->dev, res1);
635         if (IS_ERR(vaddr))
636                 return PTR_ERR(vaddr);
637 
638         /*
639          * This registers range is used to setup NAND settings. In case with
640          * TI AEMIF driver, the same memory address range is requested already
641          * by AEMIF, so we cannot request it twice, just ioremap.
642          * The AEMIF and NAND drivers not use the same registers in this range.
643          */
644         base = devm_ioremap(&pdev->dev, res2->start, resource_size(res2));
645         if (!base) {
646                 dev_err(&pdev->dev, "ioremap failed for resource %pR\n", res2);
647                 return -EADDRNOTAVAIL;
648         }
649 
650         info->dev               = &pdev->dev;
651         info->base              = base;
652         info->vaddr             = vaddr;
653 
654         info->mtd.priv          = &info->chip;
655         info->mtd.name          = dev_name(&pdev->dev);
656         info->mtd.owner         = THIS_MODULE;
657 
658         info->mtd.dev.parent    = &pdev->dev;
659 
660         info->chip.IO_ADDR_R    = vaddr;
661         info->chip.IO_ADDR_W    = vaddr;
662         info->chip.chip_delay   = 0;
663         info->chip.select_chip  = nand_davinci_select_chip;
664 
665         /* options such as NAND_BBT_USE_FLASH */
666         info->chip.bbt_options  = pdata->bbt_options;
667         /* options such as 16-bit widths */
668         info->chip.options      = pdata->options;
669         info->chip.bbt_td       = pdata->bbt_td;
670         info->chip.bbt_md       = pdata->bbt_md;
671         info->timing            = pdata->timing;
672 
673         info->ioaddr            = (uint32_t __force) vaddr;
674 
675         info->current_cs        = info->ioaddr;
676         info->core_chipsel      = pdev->id;
677         info->mask_chipsel      = pdata->mask_chipsel;
678 
679         /* use nandboot-capable ALE/CLE masks by default */
680         info->mask_ale          = pdata->mask_ale ? : MASK_ALE;
681         info->mask_cle          = pdata->mask_cle ? : MASK_CLE;
682 
683         /* Set address of hardware control function */
684         info->chip.cmd_ctrl     = nand_davinci_hwcontrol;
685         info->chip.dev_ready    = nand_davinci_dev_ready;
686 
687         /* Speed up buffer I/O */
688         info->chip.read_buf     = nand_davinci_read_buf;
689         info->chip.write_buf    = nand_davinci_write_buf;
690 
691         /* Use board-specific ECC config */
692         ecc_mode                = pdata->ecc_mode;
693 
694         ret = -EINVAL;
695         switch (ecc_mode) {
696         case NAND_ECC_NONE:
697         case NAND_ECC_SOFT:
698                 pdata->ecc_bits = 0;
699                 break;
700         case NAND_ECC_HW:
701                 if (pdata->ecc_bits == 4) {
702                         /* No sanity checks:  CPUs must support this,
703                          * and the chips may not use NAND_BUSWIDTH_16.
704                          */
705 
706                         /* No sharing 4-bit hardware between chipselects yet */
707                         spin_lock_irq(&davinci_nand_lock);
708                         if (ecc4_busy)
709                                 ret = -EBUSY;
710                         else
711                                 ecc4_busy = true;
712                         spin_unlock_irq(&davinci_nand_lock);
713 
714                         if (ret == -EBUSY)
715                                 return ret;
716 
717                         info->chip.ecc.calculate = nand_davinci_calculate_4bit;
718                         info->chip.ecc.correct = nand_davinci_correct_4bit;
719                         info->chip.ecc.hwctl = nand_davinci_hwctl_4bit;
720                         info->chip.ecc.bytes = 10;
721                 } else {
722                         info->chip.ecc.calculate = nand_davinci_calculate_1bit;
723                         info->chip.ecc.correct = nand_davinci_correct_1bit;
724                         info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
725                         info->chip.ecc.bytes = 3;
726                 }
727                 info->chip.ecc.size = 512;
728                 info->chip.ecc.strength = pdata->ecc_bits;
729                 break;
730         default:
731                 return -EINVAL;
732         }
733         info->chip.ecc.mode = ecc_mode;
734 
735         info->clk = devm_clk_get(&pdev->dev, "aemif");
736         if (IS_ERR(info->clk)) {
737                 ret = PTR_ERR(info->clk);
738                 dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret);
739                 return ret;
740         }
741 
742         ret = clk_prepare_enable(info->clk);
743         if (ret < 0) {
744                 dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n",
745                         ret);
746                 goto err_clk_enable;
747         }
748 
749         /*
750          * Setup Async configuration register in case we did not boot from
751          * NAND and so bootloader did not bother to set it up.
752          */
753         val = davinci_nand_readl(info, A1CR_OFFSET + info->core_chipsel * 4);
754 
755         /* Extended Wait is not valid and Select Strobe mode is not used */
756         val &= ~(ACR_ASIZE_MASK | ACR_EW_MASK | ACR_SS_MASK);
757         if (info->chip.options & NAND_BUSWIDTH_16)
758                 val |= 0x1;
759 
760         davinci_nand_writel(info, A1CR_OFFSET + info->core_chipsel * 4, val);
761 
762         ret = 0;
763         if (info->timing)
764                 ret = davinci_aemif_setup_timing(info->timing, info->base,
765                                                         info->core_chipsel);
766         if (ret < 0) {
767                 dev_dbg(&pdev->dev, "NAND timing values setup fail\n");
768                 goto err;
769         }
770 
771         spin_lock_irq(&davinci_nand_lock);
772 
773         /* put CSxNAND into NAND mode */
774         val = davinci_nand_readl(info, NANDFCR_OFFSET);
775         val |= BIT(info->core_chipsel);
776         davinci_nand_writel(info, NANDFCR_OFFSET, val);
777 
778         spin_unlock_irq(&davinci_nand_lock);
779 
780         /* Scan to find existence of the device(s) */
781         ret = nand_scan_ident(&info->mtd, pdata->mask_chipsel ? 2 : 1, NULL);
782         if (ret < 0) {
783                 dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
784                 goto err;
785         }
786 
787         /* Update ECC layout if needed ... for 1-bit HW ECC, the default
788          * is OK, but it allocates 6 bytes when only 3 are needed (for
789          * each 512 bytes).  For the 4-bit HW ECC, that default is not
790          * usable:  10 bytes are needed, not 6.
791          */
792         if (pdata->ecc_bits == 4) {
793                 int     chunks = info->mtd.writesize / 512;
794 
795                 if (!chunks || info->mtd.oobsize < 16) {
796                         dev_dbg(&pdev->dev, "too small\n");
797                         ret = -EINVAL;
798                         goto err;
799                 }
800 
801                 /* For small page chips, preserve the manufacturer's
802                  * badblock marking data ... and make sure a flash BBT
803                  * table marker fits in the free bytes.
804                  */
805                 if (chunks == 1) {
806                         info->ecclayout = hwecc4_small;
807                         info->ecclayout.oobfree[1].length =
808                                 info->mtd.oobsize - 16;
809                         goto syndrome_done;
810                 }
811                 if (chunks == 4) {
812                         info->ecclayout = hwecc4_2048;
813                         info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST;
814                         goto syndrome_done;
815                 }
816 
817                 /* 4KiB page chips are not yet supported. The eccpos from
818                  * nand_ecclayout cannot hold 80 bytes and change to eccpos[]
819                  * breaks userspace ioctl interface with mtd-utils. Once we
820                  * resolve this issue, NAND_ECC_HW_OOB_FIRST mode can be used
821                  * for the 4KiB page chips.
822                  *
823                  * TODO: Note that nand_ecclayout has now been expanded and can
824                  *  hold plenty of OOB entries.
825                  */
826                 dev_warn(&pdev->dev, "no 4-bit ECC support yet "
827                                 "for 4KiB-page NAND\n");
828                 ret = -EIO;
829                 goto err;
830 
831 syndrome_done:
832                 info->chip.ecc.layout = &info->ecclayout;
833         }
834 
835         ret = nand_scan_tail(&info->mtd);
836         if (ret < 0)
837                 goto err;
838 
839         if (pdata->parts)
840                 ret = mtd_device_parse_register(&info->mtd, NULL, NULL,
841                                         pdata->parts, pdata->nr_parts);
842         else {
843                 struct mtd_part_parser_data     ppdata;
844 
845                 ppdata.of_node = pdev->dev.of_node;
846                 ret = mtd_device_parse_register(&info->mtd, NULL, &ppdata,
847                                                 NULL, 0);
848         }
849         if (ret < 0)
850                 goto err;
851 
852         val = davinci_nand_readl(info, NRCSR_OFFSET);
853         dev_info(&pdev->dev, "controller rev. %d.%d\n",
854                (val >> 8) & 0xff, val & 0xff);
855 
856         return 0;
857 
858 err:
859         clk_disable_unprepare(info->clk);
860 
861 err_clk_enable:
862         spin_lock_irq(&davinci_nand_lock);
863         if (ecc_mode == NAND_ECC_HW_SYNDROME)
864                 ecc4_busy = false;
865         spin_unlock_irq(&davinci_nand_lock);
866         return ret;
867 }
868 
869 static int nand_davinci_remove(struct platform_device *pdev)
870 {
871         struct davinci_nand_info *info = platform_get_drvdata(pdev);
872 
873         spin_lock_irq(&davinci_nand_lock);
874         if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME)
875                 ecc4_busy = false;
876         spin_unlock_irq(&davinci_nand_lock);
877 
878         nand_release(&info->mtd);
879 
880         clk_disable_unprepare(info->clk);
881 
882         return 0;
883 }
884 
885 static struct platform_driver nand_davinci_driver = {
886         .probe          = nand_davinci_probe,
887         .remove         = nand_davinci_remove,
888         .driver         = {
889                 .name   = "davinci_nand",
890                 .owner  = THIS_MODULE,
891                 .of_match_table = of_match_ptr(davinci_nand_of_match),
892         },
893 };
894 MODULE_ALIAS("platform:davinci_nand");
895 
896 module_platform_driver(nand_davinci_driver);
897 
898 MODULE_LICENSE("GPL");
899 MODULE_AUTHOR("Texas Instruments");
900 MODULE_DESCRIPTION("Davinci NAND flash driver");
901 
902 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us