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Linux/drivers/mtd/nand/bf5xx_nand.c

  1 /* linux/drivers/mtd/nand/bf5xx_nand.c
  2  *
  3  * Copyright 2006-2008 Analog Devices Inc.
  4  *      http://blackfin.uclinux.org/
  5  *      Bryan Wu <bryan.wu@analog.com>
  6  *
  7  * Blackfin BF5xx on-chip NAND flash controller driver
  8  *
  9  * Derived from drivers/mtd/nand/s3c2410.c
 10  * Copyright (c) 2007 Ben Dooks <ben@simtec.co.uk>
 11  *
 12  * Derived from drivers/mtd/nand/cafe.c
 13  * Copyright © 2006 Red Hat, Inc.
 14  * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
 15  *
 16  * Changelog:
 17  *      12-Jun-2007  Bryan Wu:  Initial version
 18  *      18-Jul-2007  Bryan Wu:
 19  *              - ECC_HW and ECC_SW supported
 20  *              - DMA supported in ECC_HW
 21  *              - YAFFS tested as rootfs in both ECC_HW and ECC_SW
 22  *
 23  * This program is free software; you can redistribute it and/or modify
 24  * it under the terms of the GNU General Public License as published by
 25  * the Free Software Foundation; either version 2 of the License, or
 26  * (at your option) any later version.
 27  *
 28  * This program is distributed in the hope that it will be useful,
 29  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 30  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 31  * GNU General Public License for more details.
 32  *
 33  * You should have received a copy of the GNU General Public License
 34  * along with this program; if not, write to the Free Software
 35  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 36 */
 37 
 38 #include <linux/module.h>
 39 #include <linux/types.h>
 40 #include <linux/kernel.h>
 41 #include <linux/string.h>
 42 #include <linux/ioport.h>
 43 #include <linux/platform_device.h>
 44 #include <linux/delay.h>
 45 #include <linux/dma-mapping.h>
 46 #include <linux/err.h>
 47 #include <linux/slab.h>
 48 #include <linux/io.h>
 49 #include <linux/bitops.h>
 50 
 51 #include <linux/mtd/mtd.h>
 52 #include <linux/mtd/nand.h>
 53 #include <linux/mtd/nand_ecc.h>
 54 #include <linux/mtd/partitions.h>
 55 
 56 #include <asm/blackfin.h>
 57 #include <asm/dma.h>
 58 #include <asm/cacheflush.h>
 59 #include <asm/nand.h>
 60 #include <asm/portmux.h>
 61 
 62 #define DRV_NAME        "bf5xx-nand"
 63 #define DRV_VERSION     "1.2"
 64 #define DRV_AUTHOR      "Bryan Wu <bryan.wu@analog.com>"
 65 #define DRV_DESC        "BF5xx on-chip NAND FLash Controller Driver"
 66 
 67 /* NFC_STAT Masks */
 68 #define NBUSY       0x01  /* Not Busy */
 69 #define WB_FULL     0x02  /* Write Buffer Full */
 70 #define PG_WR_STAT  0x04  /* Page Write Pending */
 71 #define PG_RD_STAT  0x08  /* Page Read Pending */
 72 #define WB_EMPTY    0x10  /* Write Buffer Empty */
 73 
 74 /* NFC_IRQSTAT Masks */
 75 #define NBUSYIRQ    0x01  /* Not Busy IRQ */
 76 #define WB_OVF      0x02  /* Write Buffer Overflow */
 77 #define WB_EDGE     0x04  /* Write Buffer Edge Detect */
 78 #define RD_RDY      0x08  /* Read Data Ready */
 79 #define WR_DONE     0x10  /* Page Write Done */
 80 
 81 /* NFC_RST Masks */
 82 #define ECC_RST     0x01  /* ECC (and NFC counters) Reset */
 83 
 84 /* NFC_PGCTL Masks */
 85 #define PG_RD_START 0x01  /* Page Read Start */
 86 #define PG_WR_START 0x02  /* Page Write Start */
 87 
 88 #ifdef CONFIG_MTD_NAND_BF5XX_HWECC
 89 static int hardware_ecc = 1;
 90 #else
 91 static int hardware_ecc;
 92 #endif
 93 
 94 static const unsigned short bfin_nfc_pin_req[] =
 95         {P_NAND_CE,
 96          P_NAND_RB,
 97          P_NAND_D0,
 98          P_NAND_D1,
 99          P_NAND_D2,
100          P_NAND_D3,
101          P_NAND_D4,
102          P_NAND_D5,
103          P_NAND_D6,
104          P_NAND_D7,
105          P_NAND_WE,
106          P_NAND_RE,
107          P_NAND_CLE,
108          P_NAND_ALE,
109          0};
110 
111 #ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC
112 static struct nand_ecclayout bootrom_ecclayout = {
113         .eccbytes = 24,
114         .eccpos = {
115                 0x8 * 0, 0x8 * 0 + 1, 0x8 * 0 + 2,
116                 0x8 * 1, 0x8 * 1 + 1, 0x8 * 1 + 2,
117                 0x8 * 2, 0x8 * 2 + 1, 0x8 * 2 + 2,
118                 0x8 * 3, 0x8 * 3 + 1, 0x8 * 3 + 2,
119                 0x8 * 4, 0x8 * 4 + 1, 0x8 * 4 + 2,
120                 0x8 * 5, 0x8 * 5 + 1, 0x8 * 5 + 2,
121                 0x8 * 6, 0x8 * 6 + 1, 0x8 * 6 + 2,
122                 0x8 * 7, 0x8 * 7 + 1, 0x8 * 7 + 2
123         },
124         .oobfree = {
125                 { 0x8 * 0 + 3, 5 },
126                 { 0x8 * 1 + 3, 5 },
127                 { 0x8 * 2 + 3, 5 },
128                 { 0x8 * 3 + 3, 5 },
129                 { 0x8 * 4 + 3, 5 },
130                 { 0x8 * 5 + 3, 5 },
131                 { 0x8 * 6 + 3, 5 },
132                 { 0x8 * 7 + 3, 5 },
133         }
134 };
135 #endif
136 
137 /*
138  * Data structures for bf5xx nand flash controller driver
139  */
140 
141 /* bf5xx nand info */
142 struct bf5xx_nand_info {
143         /* mtd info */
144         struct nand_hw_control          controller;
145         struct mtd_info                 mtd;
146         struct nand_chip                chip;
147 
148         /* platform info */
149         struct bf5xx_nand_platform      *platform;
150 
151         /* device info */
152         struct device                   *device;
153 
154         /* DMA stuff */
155         struct completion               dma_completion;
156 };
157 
158 /*
159  * Conversion functions
160  */
161 static struct bf5xx_nand_info *mtd_to_nand_info(struct mtd_info *mtd)
162 {
163         return container_of(mtd, struct bf5xx_nand_info, mtd);
164 }
165 
166 static struct bf5xx_nand_info *to_nand_info(struct platform_device *pdev)
167 {
168         return platform_get_drvdata(pdev);
169 }
170 
171 static struct bf5xx_nand_platform *to_nand_plat(struct platform_device *pdev)
172 {
173         return dev_get_platdata(&pdev->dev);
174 }
175 
176 /*
177  * struct nand_chip interface function pointers
178  */
179 
180 /*
181  * bf5xx_nand_hwcontrol
182  *
183  * Issue command and address cycles to the chip
184  */
185 static void bf5xx_nand_hwcontrol(struct mtd_info *mtd, int cmd,
186                                    unsigned int ctrl)
187 {
188         if (cmd == NAND_CMD_NONE)
189                 return;
190 
191         while (bfin_read_NFC_STAT() & WB_FULL)
192                 cpu_relax();
193 
194         if (ctrl & NAND_CLE)
195                 bfin_write_NFC_CMD(cmd);
196         else if (ctrl & NAND_ALE)
197                 bfin_write_NFC_ADDR(cmd);
198         SSYNC();
199 }
200 
201 /*
202  * bf5xx_nand_devready()
203  *
204  * returns 0 if the nand is busy, 1 if it is ready
205  */
206 static int bf5xx_nand_devready(struct mtd_info *mtd)
207 {
208         unsigned short val = bfin_read_NFC_STAT();
209 
210         if ((val & NBUSY) == NBUSY)
211                 return 1;
212         else
213                 return 0;
214 }
215 
216 /*
217  * ECC functions
218  * These allow the bf5xx to use the controller's ECC
219  * generator block to ECC the data as it passes through
220  */
221 
222 /*
223  * ECC error correction function
224  */
225 static int bf5xx_nand_correct_data_256(struct mtd_info *mtd, u_char *dat,
226                                         u_char *read_ecc, u_char *calc_ecc)
227 {
228         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
229         u32 syndrome[5];
230         u32 calced, stored;
231         int i;
232         unsigned short failing_bit, failing_byte;
233         u_char data;
234 
235         calced = calc_ecc[0] | (calc_ecc[1] << 8) | (calc_ecc[2] << 16);
236         stored = read_ecc[0] | (read_ecc[1] << 8) | (read_ecc[2] << 16);
237 
238         syndrome[0] = (calced ^ stored);
239 
240         /*
241          * syndrome 0: all zero
242          * No error in data
243          * No action
244          */
245         if (!syndrome[0] || !calced || !stored)
246                 return 0;
247 
248         /*
249          * sysdrome 0: only one bit is one
250          * ECC data was incorrect
251          * No action
252          */
253         if (hweight32(syndrome[0]) == 1) {
254                 dev_err(info->device, "ECC data was incorrect!\n");
255                 return 1;
256         }
257 
258         syndrome[1] = (calced & 0x7FF) ^ (stored & 0x7FF);
259         syndrome[2] = (calced & 0x7FF) ^ ((calced >> 11) & 0x7FF);
260         syndrome[3] = (stored & 0x7FF) ^ ((stored >> 11) & 0x7FF);
261         syndrome[4] = syndrome[2] ^ syndrome[3];
262 
263         for (i = 0; i < 5; i++)
264                 dev_info(info->device, "syndrome[%d] 0x%08x\n", i, syndrome[i]);
265 
266         dev_info(info->device,
267                 "calced[0x%08x], stored[0x%08x]\n",
268                 calced, stored);
269 
270         /*
271          * sysdrome 0: exactly 11 bits are one, each parity
272          * and parity' pair is 1 & 0 or 0 & 1.
273          * 1-bit correctable error
274          * Correct the error
275          */
276         if (hweight32(syndrome[0]) == 11 && syndrome[4] == 0x7FF) {
277                 dev_info(info->device,
278                         "1-bit correctable error, correct it.\n");
279                 dev_info(info->device,
280                         "syndrome[1] 0x%08x\n", syndrome[1]);
281 
282                 failing_bit = syndrome[1] & 0x7;
283                 failing_byte = syndrome[1] >> 0x3;
284                 data = *(dat + failing_byte);
285                 data = data ^ (0x1 << failing_bit);
286                 *(dat + failing_byte) = data;
287 
288                 return 0;
289         }
290 
291         /*
292          * sysdrome 0: random data
293          * More than 1-bit error, non-correctable error
294          * Discard data, mark bad block
295          */
296         dev_err(info->device,
297                 "More than 1-bit error, non-correctable error.\n");
298         dev_err(info->device,
299                 "Please discard data, mark bad block\n");
300 
301         return 1;
302 }
303 
304 static int bf5xx_nand_correct_data(struct mtd_info *mtd, u_char *dat,
305                                         u_char *read_ecc, u_char *calc_ecc)
306 {
307         struct nand_chip *chip = mtd->priv;
308         int ret;
309 
310         ret = bf5xx_nand_correct_data_256(mtd, dat, read_ecc, calc_ecc);
311 
312         /* If ecc size is 512, correct second 256 bytes */
313         if (chip->ecc.size == 512) {
314                 dat += 256;
315                 read_ecc += 3;
316                 calc_ecc += 3;
317                 ret |= bf5xx_nand_correct_data_256(mtd, dat, read_ecc, calc_ecc);
318         }
319 
320         return ret;
321 }
322 
323 static void bf5xx_nand_enable_hwecc(struct mtd_info *mtd, int mode)
324 {
325         return;
326 }
327 
328 static int bf5xx_nand_calculate_ecc(struct mtd_info *mtd,
329                 const u_char *dat, u_char *ecc_code)
330 {
331         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
332         struct nand_chip *chip = mtd->priv;
333         u16 ecc0, ecc1;
334         u32 code[2];
335         u8 *p;
336 
337         /* first 3 bytes ECC code for 256 page size */
338         ecc0 = bfin_read_NFC_ECC0();
339         ecc1 = bfin_read_NFC_ECC1();
340 
341         code[0] = (ecc0 & 0x7ff) | ((ecc1 & 0x7ff) << 11);
342 
343         dev_dbg(info->device, "returning ecc 0x%08x\n", code[0]);
344 
345         p = (u8 *) code;
346         memcpy(ecc_code, p, 3);
347 
348         /* second 3 bytes ECC code for 512 ecc size */
349         if (chip->ecc.size == 512) {
350                 ecc0 = bfin_read_NFC_ECC2();
351                 ecc1 = bfin_read_NFC_ECC3();
352                 code[1] = (ecc0 & 0x7ff) | ((ecc1 & 0x7ff) << 11);
353 
354                 /* second 3 bytes in ecc_code for second 256
355                  * bytes of 512 page size
356                  */
357                 p = (u8 *) (code + 1);
358                 memcpy((ecc_code + 3), p, 3);
359                 dev_dbg(info->device, "returning ecc 0x%08x\n", code[1]);
360         }
361 
362         return 0;
363 }
364 
365 /*
366  * PIO mode for buffer writing and reading
367  */
368 static void bf5xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
369 {
370         int i;
371         unsigned short val;
372 
373         /*
374          * Data reads are requested by first writing to NFC_DATA_RD
375          * and then reading back from NFC_READ.
376          */
377         for (i = 0; i < len; i++) {
378                 while (bfin_read_NFC_STAT() & WB_FULL)
379                         cpu_relax();
380 
381                 /* Contents do not matter */
382                 bfin_write_NFC_DATA_RD(0x0000);
383                 SSYNC();
384 
385                 while ((bfin_read_NFC_IRQSTAT() & RD_RDY) != RD_RDY)
386                         cpu_relax();
387 
388                 buf[i] = bfin_read_NFC_READ();
389 
390                 val = bfin_read_NFC_IRQSTAT();
391                 val |= RD_RDY;
392                 bfin_write_NFC_IRQSTAT(val);
393                 SSYNC();
394         }
395 }
396 
397 static uint8_t bf5xx_nand_read_byte(struct mtd_info *mtd)
398 {
399         uint8_t val;
400 
401         bf5xx_nand_read_buf(mtd, &val, 1);
402 
403         return val;
404 }
405 
406 static void bf5xx_nand_write_buf(struct mtd_info *mtd,
407                                 const uint8_t *buf, int len)
408 {
409         int i;
410 
411         for (i = 0; i < len; i++) {
412                 while (bfin_read_NFC_STAT() & WB_FULL)
413                         cpu_relax();
414 
415                 bfin_write_NFC_DATA_WR(buf[i]);
416                 SSYNC();
417         }
418 }
419 
420 static void bf5xx_nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
421 {
422         int i;
423         u16 *p = (u16 *) buf;
424         len >>= 1;
425 
426         /*
427          * Data reads are requested by first writing to NFC_DATA_RD
428          * and then reading back from NFC_READ.
429          */
430         bfin_write_NFC_DATA_RD(0x5555);
431 
432         SSYNC();
433 
434         for (i = 0; i < len; i++)
435                 p[i] = bfin_read_NFC_READ();
436 }
437 
438 static void bf5xx_nand_write_buf16(struct mtd_info *mtd,
439                                 const uint8_t *buf, int len)
440 {
441         int i;
442         u16 *p = (u16 *) buf;
443         len >>= 1;
444 
445         for (i = 0; i < len; i++)
446                 bfin_write_NFC_DATA_WR(p[i]);
447 
448         SSYNC();
449 }
450 
451 /*
452  * DMA functions for buffer writing and reading
453  */
454 static irqreturn_t bf5xx_nand_dma_irq(int irq, void *dev_id)
455 {
456         struct bf5xx_nand_info *info = dev_id;
457 
458         clear_dma_irqstat(CH_NFC);
459         disable_dma(CH_NFC);
460         complete(&info->dma_completion);
461 
462         return IRQ_HANDLED;
463 }
464 
465 static void bf5xx_nand_dma_rw(struct mtd_info *mtd,
466                                 uint8_t *buf, int is_read)
467 {
468         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
469         struct nand_chip *chip = mtd->priv;
470         unsigned short val;
471 
472         dev_dbg(info->device, " mtd->%p, buf->%p, is_read %d\n",
473                         mtd, buf, is_read);
474 
475         /*
476          * Before starting a dma transfer, be sure to invalidate/flush
477          * the cache over the address range of your DMA buffer to
478          * prevent cache coherency problems. Otherwise very subtle bugs
479          * can be introduced to your driver.
480          */
481         if (is_read)
482                 invalidate_dcache_range((unsigned int)buf,
483                                 (unsigned int)(buf + chip->ecc.size));
484         else
485                 flush_dcache_range((unsigned int)buf,
486                                 (unsigned int)(buf + chip->ecc.size));
487 
488         /*
489          * This register must be written before each page is
490          * transferred to generate the correct ECC register
491          * values.
492          */
493         bfin_write_NFC_RST(ECC_RST);
494         SSYNC();
495         while (bfin_read_NFC_RST() & ECC_RST)
496                 cpu_relax();
497 
498         disable_dma(CH_NFC);
499         clear_dma_irqstat(CH_NFC);
500 
501         /* setup DMA register with Blackfin DMA API */
502         set_dma_config(CH_NFC, 0x0);
503         set_dma_start_addr(CH_NFC, (unsigned long) buf);
504 
505         /* The DMAs have different size on BF52x and BF54x */
506 #ifdef CONFIG_BF52x
507         set_dma_x_count(CH_NFC, (chip->ecc.size >> 1));
508         set_dma_x_modify(CH_NFC, 2);
509         val = DI_EN | WDSIZE_16;
510 #endif
511 
512 #ifdef CONFIG_BF54x
513         set_dma_x_count(CH_NFC, (chip->ecc.size >> 2));
514         set_dma_x_modify(CH_NFC, 4);
515         val = DI_EN | WDSIZE_32;
516 #endif
517         /* setup write or read operation */
518         if (is_read)
519                 val |= WNR;
520         set_dma_config(CH_NFC, val);
521         enable_dma(CH_NFC);
522 
523         /* Start PAGE read/write operation */
524         if (is_read)
525                 bfin_write_NFC_PGCTL(PG_RD_START);
526         else
527                 bfin_write_NFC_PGCTL(PG_WR_START);
528         wait_for_completion(&info->dma_completion);
529 }
530 
531 static void bf5xx_nand_dma_read_buf(struct mtd_info *mtd,
532                                         uint8_t *buf, int len)
533 {
534         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
535         struct nand_chip *chip = mtd->priv;
536 
537         dev_dbg(info->device, "mtd->%p, buf->%p, int %d\n", mtd, buf, len);
538 
539         if (len == chip->ecc.size)
540                 bf5xx_nand_dma_rw(mtd, buf, 1);
541         else
542                 bf5xx_nand_read_buf(mtd, buf, len);
543 }
544 
545 static void bf5xx_nand_dma_write_buf(struct mtd_info *mtd,
546                                 const uint8_t *buf, int len)
547 {
548         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
549         struct nand_chip *chip = mtd->priv;
550 
551         dev_dbg(info->device, "mtd->%p, buf->%p, len %d\n", mtd, buf, len);
552 
553         if (len == chip->ecc.size)
554                 bf5xx_nand_dma_rw(mtd, (uint8_t *)buf, 0);
555         else
556                 bf5xx_nand_write_buf(mtd, buf, len);
557 }
558 
559 static int bf5xx_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
560                 uint8_t *buf, int oob_required, int page)
561 {
562         bf5xx_nand_read_buf(mtd, buf, mtd->writesize);
563         bf5xx_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize);
564 
565         return 0;
566 }
567 
568 static int bf5xx_nand_write_page_raw(struct mtd_info *mtd,
569                 struct nand_chip *chip, const uint8_t *buf, int oob_required)
570 {
571         bf5xx_nand_write_buf(mtd, buf, mtd->writesize);
572         bf5xx_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
573 
574         return 0;
575 }
576 
577 /*
578  * System initialization functions
579  */
580 static int bf5xx_nand_dma_init(struct bf5xx_nand_info *info)
581 {
582         int ret;
583 
584         /* Do not use dma */
585         if (!hardware_ecc)
586                 return 0;
587 
588         init_completion(&info->dma_completion);
589 
590         /* Request NFC DMA channel */
591         ret = request_dma(CH_NFC, "BF5XX NFC driver");
592         if (ret < 0) {
593                 dev_err(info->device, " unable to get DMA channel\n");
594                 return ret;
595         }
596 
597 #ifdef CONFIG_BF54x
598         /* Setup DMAC1 channel mux for NFC which shared with SDH */
599         bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() & ~1);
600         SSYNC();
601 #endif
602 
603         set_dma_callback(CH_NFC, bf5xx_nand_dma_irq, info);
604 
605         /* Turn off the DMA channel first */
606         disable_dma(CH_NFC);
607         return 0;
608 }
609 
610 static void bf5xx_nand_dma_remove(struct bf5xx_nand_info *info)
611 {
612         /* Free NFC DMA channel */
613         if (hardware_ecc)
614                 free_dma(CH_NFC);
615 }
616 
617 /*
618  * BF5XX NFC hardware initialization
619  *  - pin mux setup
620  *  - clear interrupt status
621  */
622 static int bf5xx_nand_hw_init(struct bf5xx_nand_info *info)
623 {
624         int err = 0;
625         unsigned short val;
626         struct bf5xx_nand_platform *plat = info->platform;
627 
628         /* setup NFC_CTL register */
629         dev_info(info->device,
630                 "data_width=%d, wr_dly=%d, rd_dly=%d\n",
631                 (plat->data_width ? 16 : 8),
632                 plat->wr_dly, plat->rd_dly);
633 
634         val = (1 << NFC_PG_SIZE_OFFSET) |
635                 (plat->data_width << NFC_NWIDTH_OFFSET) |
636                 (plat->rd_dly << NFC_RDDLY_OFFSET) |
637                 (plat->wr_dly << NFC_WRDLY_OFFSET);
638         dev_dbg(info->device, "NFC_CTL is 0x%04x\n", val);
639 
640         bfin_write_NFC_CTL(val);
641         SSYNC();
642 
643         /* clear interrupt status */
644         bfin_write_NFC_IRQMASK(0x0);
645         SSYNC();
646         val = bfin_read_NFC_IRQSTAT();
647         bfin_write_NFC_IRQSTAT(val);
648         SSYNC();
649 
650         /* DMA initialization  */
651         if (bf5xx_nand_dma_init(info))
652                 err = -ENXIO;
653 
654         return err;
655 }
656 
657 /*
658  * Device management interface
659  */
660 static int bf5xx_nand_add_partition(struct bf5xx_nand_info *info)
661 {
662         struct mtd_info *mtd = &info->mtd;
663         struct mtd_partition *parts = info->platform->partitions;
664         int nr = info->platform->nr_partitions;
665 
666         return mtd_device_register(mtd, parts, nr);
667 }
668 
669 static int bf5xx_nand_remove(struct platform_device *pdev)
670 {
671         struct bf5xx_nand_info *info = to_nand_info(pdev);
672 
673         /* first thing we need to do is release all our mtds
674          * and their partitions, then go through freeing the
675          * resources used
676          */
677         nand_release(&info->mtd);
678 
679         peripheral_free_list(bfin_nfc_pin_req);
680         bf5xx_nand_dma_remove(info);
681 
682         return 0;
683 }
684 
685 static int bf5xx_nand_scan(struct mtd_info *mtd)
686 {
687         struct nand_chip *chip = mtd->priv;
688         int ret;
689 
690         ret = nand_scan_ident(mtd, 1, NULL);
691         if (ret)
692                 return ret;
693 
694         if (hardware_ecc) {
695                 /*
696                  * for nand with page size > 512B, think it as several sections with 512B
697                  */
698                 if (likely(mtd->writesize >= 512)) {
699                         chip->ecc.size = 512;
700                         chip->ecc.bytes = 6;
701                         chip->ecc.strength = 2;
702                 } else {
703                         chip->ecc.size = 256;
704                         chip->ecc.bytes = 3;
705                         chip->ecc.strength = 1;
706                         bfin_write_NFC_CTL(bfin_read_NFC_CTL() & ~(1 << NFC_PG_SIZE_OFFSET));
707                         SSYNC();
708                 }
709         }
710 
711         return  nand_scan_tail(mtd);
712 }
713 
714 /*
715  * bf5xx_nand_probe
716  *
717  * called by device layer when it finds a device matching
718  * one our driver can handled. This code checks to see if
719  * it can allocate all necessary resources then calls the
720  * nand layer to look for devices
721  */
722 static int bf5xx_nand_probe(struct platform_device *pdev)
723 {
724         struct bf5xx_nand_platform *plat = to_nand_plat(pdev);
725         struct bf5xx_nand_info *info = NULL;
726         struct nand_chip *chip = NULL;
727         struct mtd_info *mtd = NULL;
728         int err = 0;
729 
730         dev_dbg(&pdev->dev, "(%p)\n", pdev);
731 
732         if (!plat) {
733                 dev_err(&pdev->dev, "no platform specific information\n");
734                 return -EINVAL;
735         }
736 
737         if (peripheral_request_list(bfin_nfc_pin_req, DRV_NAME)) {
738                 dev_err(&pdev->dev, "requesting Peripherals failed\n");
739                 return -EFAULT;
740         }
741 
742         info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
743         if (info == NULL) {
744                 err = -ENOMEM;
745                 goto out_err;
746         }
747 
748         platform_set_drvdata(pdev, info);
749 
750         spin_lock_init(&info->controller.lock);
751         init_waitqueue_head(&info->controller.wq);
752 
753         info->device     = &pdev->dev;
754         info->platform   = plat;
755 
756         /* initialise chip data struct */
757         chip = &info->chip;
758 
759         if (plat->data_width)
760                 chip->options |= NAND_BUSWIDTH_16;
761 
762         chip->options |= NAND_CACHEPRG | NAND_SKIP_BBTSCAN;
763 
764         chip->read_buf = (plat->data_width) ?
765                 bf5xx_nand_read_buf16 : bf5xx_nand_read_buf;
766         chip->write_buf = (plat->data_width) ?
767                 bf5xx_nand_write_buf16 : bf5xx_nand_write_buf;
768 
769         chip->read_byte    = bf5xx_nand_read_byte;
770 
771         chip->cmd_ctrl     = bf5xx_nand_hwcontrol;
772         chip->dev_ready    = bf5xx_nand_devready;
773 
774         chip->priv         = &info->mtd;
775         chip->controller   = &info->controller;
776 
777         chip->IO_ADDR_R    = (void __iomem *) NFC_READ;
778         chip->IO_ADDR_W    = (void __iomem *) NFC_DATA_WR;
779 
780         chip->chip_delay   = 0;
781 
782         /* initialise mtd info data struct */
783         mtd             = &info->mtd;
784         mtd->priv       = chip;
785         mtd->owner      = THIS_MODULE;
786 
787         /* initialise the hardware */
788         err = bf5xx_nand_hw_init(info);
789         if (err)
790                 goto out_err;
791 
792         /* setup hardware ECC data struct */
793         if (hardware_ecc) {
794 #ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC
795                 chip->ecc.layout = &bootrom_ecclayout;
796 #endif
797                 chip->read_buf      = bf5xx_nand_dma_read_buf;
798                 chip->write_buf     = bf5xx_nand_dma_write_buf;
799                 chip->ecc.calculate = bf5xx_nand_calculate_ecc;
800                 chip->ecc.correct   = bf5xx_nand_correct_data;
801                 chip->ecc.mode      = NAND_ECC_HW;
802                 chip->ecc.hwctl     = bf5xx_nand_enable_hwecc;
803                 chip->ecc.read_page_raw = bf5xx_nand_read_page_raw;
804                 chip->ecc.write_page_raw = bf5xx_nand_write_page_raw;
805         } else {
806                 chip->ecc.mode      = NAND_ECC_SOFT;
807         }
808 
809         /* scan hardware nand chip and setup mtd info data struct */
810         if (bf5xx_nand_scan(mtd)) {
811                 err = -ENXIO;
812                 goto out_err_nand_scan;
813         }
814 
815 #ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC
816         chip->badblockpos = 63;
817 #endif
818 
819         /* add NAND partition */
820         bf5xx_nand_add_partition(info);
821 
822         dev_dbg(&pdev->dev, "initialised ok\n");
823         return 0;
824 
825 out_err_nand_scan:
826         bf5xx_nand_dma_remove(info);
827 out_err:
828         peripheral_free_list(bfin_nfc_pin_req);
829 
830         return err;
831 }
832 
833 /* driver device registration */
834 static struct platform_driver bf5xx_nand_driver = {
835         .probe          = bf5xx_nand_probe,
836         .remove         = bf5xx_nand_remove,
837         .driver         = {
838                 .name   = DRV_NAME,
839                 .owner  = THIS_MODULE,
840         },
841 };
842 
843 module_platform_driver(bf5xx_nand_driver);
844 
845 MODULE_LICENSE("GPL");
846 MODULE_AUTHOR(DRV_AUTHOR);
847 MODULE_DESCRIPTION(DRV_DESC);
848 MODULE_ALIAS("platform:" DRV_NAME);
849 

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