Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/drivers/mtd/nand/atmel_nand.c

  1 /*
  2  *  Copyright © 2003 Rick Bronson
  3  *
  4  *  Derived from drivers/mtd/nand/autcpu12.c
  5  *       Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
  6  *
  7  *  Derived from drivers/mtd/spia.c
  8  *       Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
  9  *
 10  *
 11  *  Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
 12  *     Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
 13  *
 14  *     Derived from Das U-Boot source code
 15  *              (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
 16  *     © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
 17  *
 18  *  Add Programmable Multibit ECC support for various AT91 SoC
 19  *     © Copyright 2012 ATMEL, Hong Xu
 20  *
 21  *  Add Nand Flash Controller support for SAMA5 SoC
 22  *     © Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
 23  *
 24  * This program is free software; you can redistribute it and/or modify
 25  * it under the terms of the GNU General Public License version 2 as
 26  * published by the Free Software Foundation.
 27  *
 28  */
 29 
 30 #include <linux/clk.h>
 31 #include <linux/dma-mapping.h>
 32 #include <linux/slab.h>
 33 #include <linux/module.h>
 34 #include <linux/moduleparam.h>
 35 #include <linux/platform_device.h>
 36 #include <linux/of.h>
 37 #include <linux/of_device.h>
 38 #include <linux/of_gpio.h>
 39 #include <linux/of_mtd.h>
 40 #include <linux/mtd/mtd.h>
 41 #include <linux/mtd/nand.h>
 42 #include <linux/mtd/partitions.h>
 43 
 44 #include <linux/delay.h>
 45 #include <linux/dmaengine.h>
 46 #include <linux/gpio.h>
 47 #include <linux/interrupt.h>
 48 #include <linux/io.h>
 49 #include <linux/platform_data/atmel.h>
 50 
 51 static int use_dma = 1;
 52 module_param(use_dma, int, 0);
 53 
 54 static int on_flash_bbt = 0;
 55 module_param(on_flash_bbt, int, 0);
 56 
 57 /* Register access macros */
 58 #define ecc_readl(add, reg)                             \
 59         __raw_readl(add + ATMEL_ECC_##reg)
 60 #define ecc_writel(add, reg, value)                     \
 61         __raw_writel((value), add + ATMEL_ECC_##reg)
 62 
 63 #include "atmel_nand_ecc.h"     /* Hardware ECC registers */
 64 #include "atmel_nand_nfc.h"     /* Nand Flash Controller definition */
 65 
 66 /* oob layout for large page size
 67  * bad block info is on bytes 0 and 1
 68  * the bytes have to be consecutives to avoid
 69  * several NAND_CMD_RNDOUT during read
 70  */
 71 static struct nand_ecclayout atmel_oobinfo_large = {
 72         .eccbytes = 4,
 73         .eccpos = {60, 61, 62, 63},
 74         .oobfree = {
 75                 {2, 58}
 76         },
 77 };
 78 
 79 /* oob layout for small page size
 80  * bad block info is on bytes 4 and 5
 81  * the bytes have to be consecutives to avoid
 82  * several NAND_CMD_RNDOUT during read
 83  */
 84 static struct nand_ecclayout atmel_oobinfo_small = {
 85         .eccbytes = 4,
 86         .eccpos = {0, 1, 2, 3},
 87         .oobfree = {
 88                 {6, 10}
 89         },
 90 };
 91 
 92 struct atmel_nfc {
 93         void __iomem            *base_cmd_regs;
 94         void __iomem            *hsmc_regs;
 95         void __iomem            *sram_bank0;
 96         dma_addr_t              sram_bank0_phys;
 97         bool                    use_nfc_sram;
 98         bool                    write_by_sram;
 99 
100         struct clk              *clk;
101 
102         bool                    is_initialized;
103         struct completion       comp_ready;
104         struct completion       comp_cmd_done;
105         struct completion       comp_xfer_done;
106 
107         /* Point to the sram bank which include readed data via NFC */
108         void __iomem            *data_in_sram;
109         bool                    will_write_sram;
110 };
111 static struct atmel_nfc nand_nfc;
112 
113 struct atmel_nand_host {
114         struct nand_chip        nand_chip;
115         struct mtd_info         mtd;
116         void __iomem            *io_base;
117         dma_addr_t              io_phys;
118         struct atmel_nand_data  board;
119         struct device           *dev;
120         void __iomem            *ecc;
121 
122         struct completion       comp;
123         struct dma_chan         *dma_chan;
124 
125         struct atmel_nfc        *nfc;
126 
127         bool                    has_pmecc;
128         u8                      pmecc_corr_cap;
129         u16                     pmecc_sector_size;
130         u32                     pmecc_lookup_table_offset;
131         u32                     pmecc_lookup_table_offset_512;
132         u32                     pmecc_lookup_table_offset_1024;
133 
134         int                     pmecc_degree;   /* Degree of remainders */
135         int                     pmecc_cw_len;   /* Length of codeword */
136 
137         void __iomem            *pmerrloc_base;
138         void __iomem            *pmecc_rom_base;
139 
140         /* lookup table for alpha_to and index_of */
141         void __iomem            *pmecc_alpha_to;
142         void __iomem            *pmecc_index_of;
143 
144         /* data for pmecc computation */
145         int16_t                 *pmecc_partial_syn;
146         int16_t                 *pmecc_si;
147         int16_t                 *pmecc_smu;     /* Sigma table */
148         int16_t                 *pmecc_lmu;     /* polynomal order */
149         int                     *pmecc_mu;
150         int                     *pmecc_dmu;
151         int                     *pmecc_delta;
152 };
153 
154 static struct nand_ecclayout atmel_pmecc_oobinfo;
155 
156 /*
157  * Enable NAND.
158  */
159 static void atmel_nand_enable(struct atmel_nand_host *host)
160 {
161         if (gpio_is_valid(host->board.enable_pin))
162                 gpio_set_value(host->board.enable_pin, 0);
163 }
164 
165 /*
166  * Disable NAND.
167  */
168 static void atmel_nand_disable(struct atmel_nand_host *host)
169 {
170         if (gpio_is_valid(host->board.enable_pin))
171                 gpio_set_value(host->board.enable_pin, 1);
172 }
173 
174 /*
175  * Hardware specific access to control-lines
176  */
177 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
178 {
179         struct nand_chip *nand_chip = mtd->priv;
180         struct atmel_nand_host *host = nand_chip->priv;
181 
182         if (ctrl & NAND_CTRL_CHANGE) {
183                 if (ctrl & NAND_NCE)
184                         atmel_nand_enable(host);
185                 else
186                         atmel_nand_disable(host);
187         }
188         if (cmd == NAND_CMD_NONE)
189                 return;
190 
191         if (ctrl & NAND_CLE)
192                 writeb(cmd, host->io_base + (1 << host->board.cle));
193         else
194                 writeb(cmd, host->io_base + (1 << host->board.ale));
195 }
196 
197 /*
198  * Read the Device Ready pin.
199  */
200 static int atmel_nand_device_ready(struct mtd_info *mtd)
201 {
202         struct nand_chip *nand_chip = mtd->priv;
203         struct atmel_nand_host *host = nand_chip->priv;
204 
205         return gpio_get_value(host->board.rdy_pin) ^
206                 !!host->board.rdy_pin_active_low;
207 }
208 
209 /* Set up for hardware ready pin and enable pin. */
210 static int atmel_nand_set_enable_ready_pins(struct mtd_info *mtd)
211 {
212         struct nand_chip *chip = mtd->priv;
213         struct atmel_nand_host *host = chip->priv;
214         int res = 0;
215 
216         if (gpio_is_valid(host->board.rdy_pin)) {
217                 res = devm_gpio_request(host->dev,
218                                 host->board.rdy_pin, "nand_rdy");
219                 if (res < 0) {
220                         dev_err(host->dev,
221                                 "can't request rdy gpio %d\n",
222                                 host->board.rdy_pin);
223                         return res;
224                 }
225 
226                 res = gpio_direction_input(host->board.rdy_pin);
227                 if (res < 0) {
228                         dev_err(host->dev,
229                                 "can't request input direction rdy gpio %d\n",
230                                 host->board.rdy_pin);
231                         return res;
232                 }
233 
234                 chip->dev_ready = atmel_nand_device_ready;
235         }
236 
237         if (gpio_is_valid(host->board.enable_pin)) {
238                 res = devm_gpio_request(host->dev,
239                                 host->board.enable_pin, "nand_enable");
240                 if (res < 0) {
241                         dev_err(host->dev,
242                                 "can't request enable gpio %d\n",
243                                 host->board.enable_pin);
244                         return res;
245                 }
246 
247                 res = gpio_direction_output(host->board.enable_pin, 1);
248                 if (res < 0) {
249                         dev_err(host->dev,
250                                 "can't request output direction enable gpio %d\n",
251                                 host->board.enable_pin);
252                         return res;
253                 }
254         }
255 
256         return res;
257 }
258 
259 static void memcpy32_fromio(void *trg, const void __iomem  *src, size_t size)
260 {
261         int i;
262         u32 *t = trg;
263         const __iomem u32 *s = src;
264 
265         for (i = 0; i < (size >> 2); i++)
266                 *t++ = readl_relaxed(s++);
267 }
268 
269 static void memcpy32_toio(void __iomem *trg, const void *src, int size)
270 {
271         int i;
272         u32 __iomem *t = trg;
273         const u32 *s = src;
274 
275         for (i = 0; i < (size >> 2); i++)
276                 writel_relaxed(*s++, t++);
277 }
278 
279 /*
280  * Minimal-overhead PIO for data access.
281  */
282 static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
283 {
284         struct nand_chip        *nand_chip = mtd->priv;
285         struct atmel_nand_host *host = nand_chip->priv;
286 
287         if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
288                 memcpy32_fromio(buf, host->nfc->data_in_sram, len);
289                 host->nfc->data_in_sram += len;
290         } else {
291                 __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
292         }
293 }
294 
295 static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
296 {
297         struct nand_chip        *nand_chip = mtd->priv;
298         struct atmel_nand_host *host = nand_chip->priv;
299 
300         if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
301                 memcpy32_fromio(buf, host->nfc->data_in_sram, len);
302                 host->nfc->data_in_sram += len;
303         } else {
304                 __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
305         }
306 }
307 
308 static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
309 {
310         struct nand_chip        *nand_chip = mtd->priv;
311 
312         __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
313 }
314 
315 static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
316 {
317         struct nand_chip        *nand_chip = mtd->priv;
318 
319         __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
320 }
321 
322 static void dma_complete_func(void *completion)
323 {
324         complete(completion);
325 }
326 
327 static int nfc_set_sram_bank(struct atmel_nand_host *host, unsigned int bank)
328 {
329         /* NFC only has two banks. Must be 0 or 1 */
330         if (bank > 1)
331                 return -EINVAL;
332 
333         if (bank) {
334                 /* Only for a 2k-page or lower flash, NFC can handle 2 banks */
335                 if (host->mtd.writesize > 2048)
336                         return -EINVAL;
337                 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK1);
338         } else {
339                 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK0);
340         }
341 
342         return 0;
343 }
344 
345 static uint nfc_get_sram_off(struct atmel_nand_host *host)
346 {
347         if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
348                 return NFC_SRAM_BANK1_OFFSET;
349         else
350                 return 0;
351 }
352 
353 static dma_addr_t nfc_sram_phys(struct atmel_nand_host *host)
354 {
355         if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
356                 return host->nfc->sram_bank0_phys + NFC_SRAM_BANK1_OFFSET;
357         else
358                 return host->nfc->sram_bank0_phys;
359 }
360 
361 static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
362                                int is_read)
363 {
364         struct dma_device *dma_dev;
365         enum dma_ctrl_flags flags;
366         dma_addr_t dma_src_addr, dma_dst_addr, phys_addr;
367         struct dma_async_tx_descriptor *tx = NULL;
368         dma_cookie_t cookie;
369         struct nand_chip *chip = mtd->priv;
370         struct atmel_nand_host *host = chip->priv;
371         void *p = buf;
372         int err = -EIO;
373         enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
374         struct atmel_nfc *nfc = host->nfc;
375 
376         if (buf >= high_memory)
377                 goto err_buf;
378 
379         dma_dev = host->dma_chan->device;
380 
381         flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
382 
383         phys_addr = dma_map_single(dma_dev->dev, p, len, dir);
384         if (dma_mapping_error(dma_dev->dev, phys_addr)) {
385                 dev_err(host->dev, "Failed to dma_map_single\n");
386                 goto err_buf;
387         }
388 
389         if (is_read) {
390                 if (nfc && nfc->data_in_sram)
391                         dma_src_addr = nfc_sram_phys(host) + (nfc->data_in_sram
392                                 - (nfc->sram_bank0 + nfc_get_sram_off(host)));
393                 else
394                         dma_src_addr = host->io_phys;
395 
396                 dma_dst_addr = phys_addr;
397         } else {
398                 dma_src_addr = phys_addr;
399 
400                 if (nfc && nfc->write_by_sram)
401                         dma_dst_addr = nfc_sram_phys(host);
402                 else
403                         dma_dst_addr = host->io_phys;
404         }
405 
406         tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr,
407                                              dma_src_addr, len, flags);
408         if (!tx) {
409                 dev_err(host->dev, "Failed to prepare DMA memcpy\n");
410                 goto err_dma;
411         }
412 
413         init_completion(&host->comp);
414         tx->callback = dma_complete_func;
415         tx->callback_param = &host->comp;
416 
417         cookie = tx->tx_submit(tx);
418         if (dma_submit_error(cookie)) {
419                 dev_err(host->dev, "Failed to do DMA tx_submit\n");
420                 goto err_dma;
421         }
422 
423         dma_async_issue_pending(host->dma_chan);
424         wait_for_completion(&host->comp);
425 
426         if (is_read && nfc && nfc->data_in_sram)
427                 /* After read data from SRAM, need to increase the position */
428                 nfc->data_in_sram += len;
429 
430         err = 0;
431 
432 err_dma:
433         dma_unmap_single(dma_dev->dev, phys_addr, len, dir);
434 err_buf:
435         if (err != 0)
436                 dev_dbg(host->dev, "Fall back to CPU I/O\n");
437         return err;
438 }
439 
440 static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
441 {
442         struct nand_chip *chip = mtd->priv;
443         struct atmel_nand_host *host = chip->priv;
444 
445         if (use_dma && len > mtd->oobsize)
446                 /* only use DMA for bigger than oob size: better performances */
447                 if (atmel_nand_dma_op(mtd, buf, len, 1) == 0)
448                         return;
449 
450         if (host->board.bus_width_16)
451                 atmel_read_buf16(mtd, buf, len);
452         else
453                 atmel_read_buf8(mtd, buf, len);
454 }
455 
456 static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
457 {
458         struct nand_chip *chip = mtd->priv;
459         struct atmel_nand_host *host = chip->priv;
460 
461         if (use_dma && len > mtd->oobsize)
462                 /* only use DMA for bigger than oob size: better performances */
463                 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0)
464                         return;
465 
466         if (host->board.bus_width_16)
467                 atmel_write_buf16(mtd, buf, len);
468         else
469                 atmel_write_buf8(mtd, buf, len);
470 }
471 
472 /*
473  * Return number of ecc bytes per sector according to sector size and
474  * correction capability
475  *
476  * Following table shows what at91 PMECC supported:
477  * Correction Capability        Sector_512_bytes        Sector_1024_bytes
478  * =====================        ================        =================
479  *                2-bits                 4-bytes                  4-bytes
480  *                4-bits                 7-bytes                  7-bytes
481  *                8-bits                13-bytes                 14-bytes
482  *               12-bits                20-bytes                 21-bytes
483  *               24-bits                39-bytes                 42-bytes
484  */
485 static int pmecc_get_ecc_bytes(int cap, int sector_size)
486 {
487         int m = 12 + sector_size / 512;
488         return (m * cap + 7) / 8;
489 }
490 
491 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
492                                     int oobsize, int ecc_len)
493 {
494         int i;
495 
496         layout->eccbytes = ecc_len;
497 
498         /* ECC will occupy the last ecc_len bytes continuously */
499         for (i = 0; i < ecc_len; i++)
500                 layout->eccpos[i] = oobsize - ecc_len + i;
501 
502         layout->oobfree[0].offset = 2;
503         layout->oobfree[0].length =
504                 oobsize - ecc_len - layout->oobfree[0].offset;
505 }
506 
507 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
508 {
509         int table_size;
510 
511         table_size = host->pmecc_sector_size == 512 ?
512                 PMECC_LOOKUP_TABLE_SIZE_512 : PMECC_LOOKUP_TABLE_SIZE_1024;
513 
514         return host->pmecc_rom_base + host->pmecc_lookup_table_offset +
515                         table_size * sizeof(int16_t);
516 }
517 
518 static int pmecc_data_alloc(struct atmel_nand_host *host)
519 {
520         const int cap = host->pmecc_corr_cap;
521         int size;
522 
523         size = (2 * cap + 1) * sizeof(int16_t);
524         host->pmecc_partial_syn = devm_kzalloc(host->dev, size, GFP_KERNEL);
525         host->pmecc_si = devm_kzalloc(host->dev, size, GFP_KERNEL);
526         host->pmecc_lmu = devm_kzalloc(host->dev,
527                         (cap + 1) * sizeof(int16_t), GFP_KERNEL);
528         host->pmecc_smu = devm_kzalloc(host->dev,
529                         (cap + 2) * size, GFP_KERNEL);
530 
531         size = (cap + 1) * sizeof(int);
532         host->pmecc_mu = devm_kzalloc(host->dev, size, GFP_KERNEL);
533         host->pmecc_dmu = devm_kzalloc(host->dev, size, GFP_KERNEL);
534         host->pmecc_delta = devm_kzalloc(host->dev, size, GFP_KERNEL);
535 
536         if (!host->pmecc_partial_syn ||
537                 !host->pmecc_si ||
538                 !host->pmecc_lmu ||
539                 !host->pmecc_smu ||
540                 !host->pmecc_mu ||
541                 !host->pmecc_dmu ||
542                 !host->pmecc_delta)
543                 return -ENOMEM;
544 
545         return 0;
546 }
547 
548 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
549 {
550         struct nand_chip *nand_chip = mtd->priv;
551         struct atmel_nand_host *host = nand_chip->priv;
552         int i;
553         uint32_t value;
554 
555         /* Fill odd syndromes */
556         for (i = 0; i < host->pmecc_corr_cap; i++) {
557                 value = pmecc_readl_rem_relaxed(host->ecc, sector, i / 2);
558                 if (i & 1)
559                         value >>= 16;
560                 value &= 0xffff;
561                 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
562         }
563 }
564 
565 static void pmecc_substitute(struct mtd_info *mtd)
566 {
567         struct nand_chip *nand_chip = mtd->priv;
568         struct atmel_nand_host *host = nand_chip->priv;
569         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
570         int16_t __iomem *index_of = host->pmecc_index_of;
571         int16_t *partial_syn = host->pmecc_partial_syn;
572         const int cap = host->pmecc_corr_cap;
573         int16_t *si;
574         int i, j;
575 
576         /* si[] is a table that holds the current syndrome value,
577          * an element of that table belongs to the field
578          */
579         si = host->pmecc_si;
580 
581         memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
582 
583         /* Computation 2t syndromes based on S(x) */
584         /* Odd syndromes */
585         for (i = 1; i < 2 * cap; i += 2) {
586                 for (j = 0; j < host->pmecc_degree; j++) {
587                         if (partial_syn[i] & ((unsigned short)0x1 << j))
588                                 si[i] = readw_relaxed(alpha_to + i * j) ^ si[i];
589                 }
590         }
591         /* Even syndrome = (Odd syndrome) ** 2 */
592         for (i = 2, j = 1; j <= cap; i = ++j << 1) {
593                 if (si[j] == 0) {
594                         si[i] = 0;
595                 } else {
596                         int16_t tmp;
597 
598                         tmp = readw_relaxed(index_of + si[j]);
599                         tmp = (tmp * 2) % host->pmecc_cw_len;
600                         si[i] = readw_relaxed(alpha_to + tmp);
601                 }
602         }
603 
604         return;
605 }
606 
607 static void pmecc_get_sigma(struct mtd_info *mtd)
608 {
609         struct nand_chip *nand_chip = mtd->priv;
610         struct atmel_nand_host *host = nand_chip->priv;
611 
612         int16_t *lmu = host->pmecc_lmu;
613         int16_t *si = host->pmecc_si;
614         int *mu = host->pmecc_mu;
615         int *dmu = host->pmecc_dmu;     /* Discrepancy */
616         int *delta = host->pmecc_delta; /* Delta order */
617         int cw_len = host->pmecc_cw_len;
618         const int16_t cap = host->pmecc_corr_cap;
619         const int num = 2 * cap + 1;
620         int16_t __iomem *index_of = host->pmecc_index_of;
621         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
622         int i, j, k;
623         uint32_t dmu_0_count, tmp;
624         int16_t *smu = host->pmecc_smu;
625 
626         /* index of largest delta */
627         int ro;
628         int largest;
629         int diff;
630 
631         dmu_0_count = 0;
632 
633         /* First Row */
634 
635         /* Mu */
636         mu[0] = -1;
637 
638         memset(smu, 0, sizeof(int16_t) * num);
639         smu[0] = 1;
640 
641         /* discrepancy set to 1 */
642         dmu[0] = 1;
643         /* polynom order set to 0 */
644         lmu[0] = 0;
645         delta[0] = (mu[0] * 2 - lmu[0]) >> 1;
646 
647         /* Second Row */
648 
649         /* Mu */
650         mu[1] = 0;
651         /* Sigma(x) set to 1 */
652         memset(&smu[num], 0, sizeof(int16_t) * num);
653         smu[num] = 1;
654 
655         /* discrepancy set to S1 */
656         dmu[1] = si[1];
657 
658         /* polynom order set to 0 */
659         lmu[1] = 0;
660 
661         delta[1] = (mu[1] * 2 - lmu[1]) >> 1;
662 
663         /* Init the Sigma(x) last row */
664         memset(&smu[(cap + 1) * num], 0, sizeof(int16_t) * num);
665 
666         for (i = 1; i <= cap; i++) {
667                 mu[i + 1] = i << 1;
668                 /* Begin Computing Sigma (Mu+1) and L(mu) */
669                 /* check if discrepancy is set to 0 */
670                 if (dmu[i] == 0) {
671                         dmu_0_count++;
672 
673                         tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
674                         if ((cap - (lmu[i] >> 1) - 1) & 0x1)
675                                 tmp += 2;
676                         else
677                                 tmp += 1;
678 
679                         if (dmu_0_count == tmp) {
680                                 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
681                                         smu[(cap + 1) * num + j] =
682                                                         smu[i * num + j];
683 
684                                 lmu[cap + 1] = lmu[i];
685                                 return;
686                         }
687 
688                         /* copy polynom */
689                         for (j = 0; j <= lmu[i] >> 1; j++)
690                                 smu[(i + 1) * num + j] = smu[i * num + j];
691 
692                         /* copy previous polynom order to the next */
693                         lmu[i + 1] = lmu[i];
694                 } else {
695                         ro = 0;
696                         largest = -1;
697                         /* find largest delta with dmu != 0 */
698                         for (j = 0; j < i; j++) {
699                                 if ((dmu[j]) && (delta[j] > largest)) {
700                                         largest = delta[j];
701                                         ro = j;
702                                 }
703                         }
704 
705                         /* compute difference */
706                         diff = (mu[i] - mu[ro]);
707 
708                         /* Compute degree of the new smu polynomial */
709                         if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
710                                 lmu[i + 1] = lmu[i];
711                         else
712                                 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
713 
714                         /* Init smu[i+1] with 0 */
715                         for (k = 0; k < num; k++)
716                                 smu[(i + 1) * num + k] = 0;
717 
718                         /* Compute smu[i+1] */
719                         for (k = 0; k <= lmu[ro] >> 1; k++) {
720                                 int16_t a, b, c;
721 
722                                 if (!(smu[ro * num + k] && dmu[i]))
723                                         continue;
724                                 a = readw_relaxed(index_of + dmu[i]);
725                                 b = readw_relaxed(index_of + dmu[ro]);
726                                 c = readw_relaxed(index_of + smu[ro * num + k]);
727                                 tmp = a + (cw_len - b) + c;
728                                 a = readw_relaxed(alpha_to + tmp % cw_len);
729                                 smu[(i + 1) * num + (k + diff)] = a;
730                         }
731 
732                         for (k = 0; k <= lmu[i] >> 1; k++)
733                                 smu[(i + 1) * num + k] ^= smu[i * num + k];
734                 }
735 
736                 /* End Computing Sigma (Mu+1) and L(mu) */
737                 /* In either case compute delta */
738                 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
739 
740                 /* Do not compute discrepancy for the last iteration */
741                 if (i >= cap)
742                         continue;
743 
744                 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
745                         tmp = 2 * (i - 1);
746                         if (k == 0) {
747                                 dmu[i + 1] = si[tmp + 3];
748                         } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
749                                 int16_t a, b, c;
750                                 a = readw_relaxed(index_of +
751                                                 smu[(i + 1) * num + k]);
752                                 b = si[2 * (i - 1) + 3 - k];
753                                 c = readw_relaxed(index_of + b);
754                                 tmp = a + c;
755                                 tmp %= cw_len;
756                                 dmu[i + 1] = readw_relaxed(alpha_to + tmp) ^
757                                         dmu[i + 1];
758                         }
759                 }
760         }
761 
762         return;
763 }
764 
765 static int pmecc_err_location(struct mtd_info *mtd)
766 {
767         struct nand_chip *nand_chip = mtd->priv;
768         struct atmel_nand_host *host = nand_chip->priv;
769         unsigned long end_time;
770         const int cap = host->pmecc_corr_cap;
771         const int num = 2 * cap + 1;
772         int sector_size = host->pmecc_sector_size;
773         int err_nbr = 0;        /* number of error */
774         int roots_nbr;          /* number of roots */
775         int i;
776         uint32_t val;
777         int16_t *smu = host->pmecc_smu;
778 
779         pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE);
780 
781         for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
782                 pmerrloc_writel_sigma_relaxed(host->pmerrloc_base, i,
783                                       smu[(cap + 1) * num + i]);
784                 err_nbr++;
785         }
786 
787         val = (err_nbr - 1) << 16;
788         if (sector_size == 1024)
789                 val |= 1;
790 
791         pmerrloc_writel(host->pmerrloc_base, ELCFG, val);
792         pmerrloc_writel(host->pmerrloc_base, ELEN,
793                         sector_size * 8 + host->pmecc_degree * cap);
794 
795         end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
796         while (!(pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
797                  & PMERRLOC_CALC_DONE)) {
798                 if (unlikely(time_after(jiffies, end_time))) {
799                         dev_err(host->dev, "PMECC: Timeout to calculate error location.\n");
800                         return -1;
801                 }
802                 cpu_relax();
803         }
804 
805         roots_nbr = (pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
806                 & PMERRLOC_ERR_NUM_MASK) >> 8;
807         /* Number of roots == degree of smu hence <= cap */
808         if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
809                 return err_nbr - 1;
810 
811         /* Number of roots does not match the degree of smu
812          * unable to correct error */
813         return -1;
814 }
815 
816 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
817                 int sector_num, int extra_bytes, int err_nbr)
818 {
819         struct nand_chip *nand_chip = mtd->priv;
820         struct atmel_nand_host *host = nand_chip->priv;
821         int i = 0;
822         int byte_pos, bit_pos, sector_size, pos;
823         uint32_t tmp;
824         uint8_t err_byte;
825 
826         sector_size = host->pmecc_sector_size;
827 
828         while (err_nbr) {
829                 tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1;
830                 byte_pos = tmp / 8;
831                 bit_pos  = tmp % 8;
832 
833                 if (byte_pos >= (sector_size + extra_bytes))
834                         BUG();  /* should never happen */
835 
836                 if (byte_pos < sector_size) {
837                         err_byte = *(buf + byte_pos);
838                         *(buf + byte_pos) ^= (1 << bit_pos);
839 
840                         pos = sector_num * host->pmecc_sector_size + byte_pos;
841                         dev_info(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
842                                 pos, bit_pos, err_byte, *(buf + byte_pos));
843                 } else {
844                         /* Bit flip in OOB area */
845                         tmp = sector_num * nand_chip->ecc.bytes
846                                         + (byte_pos - sector_size);
847                         err_byte = ecc[tmp];
848                         ecc[tmp] ^= (1 << bit_pos);
849 
850                         pos = tmp + nand_chip->ecc.layout->eccpos[0];
851                         dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
852                                 pos, bit_pos, err_byte, ecc[tmp]);
853                 }
854 
855                 i++;
856                 err_nbr--;
857         }
858 
859         return;
860 }
861 
862 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
863         u8 *ecc)
864 {
865         struct nand_chip *nand_chip = mtd->priv;
866         struct atmel_nand_host *host = nand_chip->priv;
867         int i, err_nbr;
868         uint8_t *buf_pos;
869         int total_err = 0;
870 
871         for (i = 0; i < nand_chip->ecc.total; i++)
872                 if (ecc[i] != 0xff)
873                         goto normal_check;
874         /* Erased page, return OK */
875         return 0;
876 
877 normal_check:
878         for (i = 0; i < nand_chip->ecc.steps; i++) {
879                 err_nbr = 0;
880                 if (pmecc_stat & 0x1) {
881                         buf_pos = buf + i * host->pmecc_sector_size;
882 
883                         pmecc_gen_syndrome(mtd, i);
884                         pmecc_substitute(mtd);
885                         pmecc_get_sigma(mtd);
886 
887                         err_nbr = pmecc_err_location(mtd);
888                         if (err_nbr == -1) {
889                                 dev_err(host->dev, "PMECC: Too many errors\n");
890                                 mtd->ecc_stats.failed++;
891                                 return -EIO;
892                         } else {
893                                 pmecc_correct_data(mtd, buf_pos, ecc, i,
894                                         nand_chip->ecc.bytes, err_nbr);
895                                 mtd->ecc_stats.corrected += err_nbr;
896                                 total_err += err_nbr;
897                         }
898                 }
899                 pmecc_stat >>= 1;
900         }
901 
902         return total_err;
903 }
904 
905 static void pmecc_enable(struct atmel_nand_host *host, int ecc_op)
906 {
907         u32 val;
908 
909         if (ecc_op != NAND_ECC_READ && ecc_op != NAND_ECC_WRITE) {
910                 dev_err(host->dev, "atmel_nand: wrong pmecc operation type!");
911                 return;
912         }
913 
914         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
915         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
916         val = pmecc_readl_relaxed(host->ecc, CFG);
917 
918         if (ecc_op == NAND_ECC_READ)
919                 pmecc_writel(host->ecc, CFG, (val & ~PMECC_CFG_WRITE_OP)
920                         | PMECC_CFG_AUTO_ENABLE);
921         else
922                 pmecc_writel(host->ecc, CFG, (val | PMECC_CFG_WRITE_OP)
923                         & ~PMECC_CFG_AUTO_ENABLE);
924 
925         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
926         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
927 }
928 
929 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
930         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
931 {
932         struct atmel_nand_host *host = chip->priv;
933         int eccsize = chip->ecc.size * chip->ecc.steps;
934         uint8_t *oob = chip->oob_poi;
935         uint32_t *eccpos = chip->ecc.layout->eccpos;
936         uint32_t stat;
937         unsigned long end_time;
938         int bitflips = 0;
939 
940         if (!host->nfc || !host->nfc->use_nfc_sram)
941                 pmecc_enable(host, NAND_ECC_READ);
942 
943         chip->read_buf(mtd, buf, eccsize);
944         chip->read_buf(mtd, oob, mtd->oobsize);
945 
946         end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
947         while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
948                 if (unlikely(time_after(jiffies, end_time))) {
949                         dev_err(host->dev, "PMECC: Timeout to get error status.\n");
950                         return -EIO;
951                 }
952                 cpu_relax();
953         }
954 
955         stat = pmecc_readl_relaxed(host->ecc, ISR);
956         if (stat != 0) {
957                 bitflips = pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]);
958                 if (bitflips < 0)
959                         /* uncorrectable errors */
960                         return 0;
961         }
962 
963         return bitflips;
964 }
965 
966 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
967                 struct nand_chip *chip, const uint8_t *buf, int oob_required)
968 {
969         struct atmel_nand_host *host = chip->priv;
970         uint32_t *eccpos = chip->ecc.layout->eccpos;
971         int i, j;
972         unsigned long end_time;
973 
974         if (!host->nfc || !host->nfc->write_by_sram) {
975                 pmecc_enable(host, NAND_ECC_WRITE);
976                 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
977         }
978 
979         end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
980         while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
981                 if (unlikely(time_after(jiffies, end_time))) {
982                         dev_err(host->dev, "PMECC: Timeout to get ECC value.\n");
983                         return -EIO;
984                 }
985                 cpu_relax();
986         }
987 
988         for (i = 0; i < chip->ecc.steps; i++) {
989                 for (j = 0; j < chip->ecc.bytes; j++) {
990                         int pos;
991 
992                         pos = i * chip->ecc.bytes + j;
993                         chip->oob_poi[eccpos[pos]] =
994                                 pmecc_readb_ecc_relaxed(host->ecc, i, j);
995                 }
996         }
997         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
998 
999         return 0;
1000 }
1001 
1002 static void atmel_pmecc_core_init(struct mtd_info *mtd)
1003 {
1004         struct nand_chip *nand_chip = mtd->priv;
1005         struct atmel_nand_host *host = nand_chip->priv;
1006         uint32_t val = 0;
1007         struct nand_ecclayout *ecc_layout;
1008 
1009         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
1010         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
1011 
1012         switch (host->pmecc_corr_cap) {
1013         case 2:
1014                 val = PMECC_CFG_BCH_ERR2;
1015                 break;
1016         case 4:
1017                 val = PMECC_CFG_BCH_ERR4;
1018                 break;
1019         case 8:
1020                 val = PMECC_CFG_BCH_ERR8;
1021                 break;
1022         case 12:
1023                 val = PMECC_CFG_BCH_ERR12;
1024                 break;
1025         case 24:
1026                 val = PMECC_CFG_BCH_ERR24;
1027                 break;
1028         }
1029 
1030         if (host->pmecc_sector_size == 512)
1031                 val |= PMECC_CFG_SECTOR512;
1032         else if (host->pmecc_sector_size == 1024)
1033                 val |= PMECC_CFG_SECTOR1024;
1034 
1035         switch (nand_chip->ecc.steps) {
1036         case 1:
1037                 val |= PMECC_CFG_PAGE_1SECTOR;
1038                 break;
1039         case 2:
1040                 val |= PMECC_CFG_PAGE_2SECTORS;
1041                 break;
1042         case 4:
1043                 val |= PMECC_CFG_PAGE_4SECTORS;
1044                 break;
1045         case 8:
1046                 val |= PMECC_CFG_PAGE_8SECTORS;
1047                 break;
1048         }
1049 
1050         val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
1051                 | PMECC_CFG_AUTO_DISABLE);
1052         pmecc_writel(host->ecc, CFG, val);
1053 
1054         ecc_layout = nand_chip->ecc.layout;
1055         pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1);
1056         pmecc_writel(host->ecc, SADDR, ecc_layout->eccpos[0]);
1057         pmecc_writel(host->ecc, EADDR,
1058                         ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
1059         /* See datasheet about PMECC Clock Control Register */
1060         pmecc_writel(host->ecc, CLK, 2);
1061         pmecc_writel(host->ecc, IDR, 0xff);
1062         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
1063 }
1064 
1065 /*
1066  * Get minimum ecc requirements from NAND.
1067  * If pmecc-cap, pmecc-sector-size in DTS are not specified, this function
1068  * will set them according to minimum ecc requirement. Otherwise, use the
1069  * value in DTS file.
1070  * return 0 if success. otherwise return error code.
1071  */
1072 static int pmecc_choose_ecc(struct atmel_nand_host *host,
1073                 int *cap, int *sector_size)
1074 {
1075         /* Get minimum ECC requirements */
1076         if (host->nand_chip.ecc_strength_ds) {
1077                 *cap = host->nand_chip.ecc_strength_ds;
1078                 *sector_size = host->nand_chip.ecc_step_ds;
1079                 dev_info(host->dev, "minimum ECC: %d bits in %d bytes\n",
1080                                 *cap, *sector_size);
1081         } else {
1082                 *cap = 2;
1083                 *sector_size = 512;
1084                 dev_info(host->dev, "can't detect min. ECC, assume 2 bits in 512 bytes\n");
1085         }
1086 
1087         /* If device tree doesn't specify, use NAND's minimum ECC parameters */
1088         if (host->pmecc_corr_cap == 0) {
1089                 /* use the most fitable ecc bits (the near bigger one ) */
1090                 if (*cap <= 2)
1091                         host->pmecc_corr_cap = 2;
1092                 else if (*cap <= 4)
1093                         host->pmecc_corr_cap = 4;
1094                 else if (*cap <= 8)
1095                         host->pmecc_corr_cap = 8;
1096                 else if (*cap <= 12)
1097                         host->pmecc_corr_cap = 12;
1098                 else if (*cap <= 24)
1099                         host->pmecc_corr_cap = 24;
1100                 else
1101                         return -EINVAL;
1102         }
1103         if (host->pmecc_sector_size == 0) {
1104                 /* use the most fitable sector size (the near smaller one ) */
1105                 if (*sector_size >= 1024)
1106                         host->pmecc_sector_size = 1024;
1107                 else if (*sector_size >= 512)
1108                         host->pmecc_sector_size = 512;
1109                 else
1110                         return -EINVAL;
1111         }
1112         return 0;
1113 }
1114 
1115 static int atmel_pmecc_nand_init_params(struct platform_device *pdev,
1116                                          struct atmel_nand_host *host)
1117 {
1118         struct mtd_info *mtd = &host->mtd;
1119         struct nand_chip *nand_chip = &host->nand_chip;
1120         struct resource *regs, *regs_pmerr, *regs_rom;
1121         int cap, sector_size, err_no;
1122 
1123         err_no = pmecc_choose_ecc(host, &cap, &sector_size);
1124         if (err_no) {
1125                 dev_err(host->dev, "The NAND flash's ECC requirement are not support!");
1126                 return err_no;
1127         }
1128 
1129         if (cap > host->pmecc_corr_cap ||
1130                         sector_size != host->pmecc_sector_size)
1131                 dev_info(host->dev, "WARNING: Be Caution! Using different PMECC parameters from Nand ONFI ECC reqirement.\n");
1132 
1133         cap = host->pmecc_corr_cap;
1134         sector_size = host->pmecc_sector_size;
1135         host->pmecc_lookup_table_offset = (sector_size == 512) ?
1136                         host->pmecc_lookup_table_offset_512 :
1137                         host->pmecc_lookup_table_offset_1024;
1138 
1139         dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n",
1140                  cap, sector_size);
1141 
1142         regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1143         if (!regs) {
1144                 dev_warn(host->dev,
1145                         "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
1146                 nand_chip->ecc.mode = NAND_ECC_SOFT;
1147                 return 0;
1148         }
1149 
1150         host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1151         if (IS_ERR(host->ecc)) {
1152                 err_no = PTR_ERR(host->ecc);
1153                 goto err;
1154         }
1155 
1156         regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1157         host->pmerrloc_base = devm_ioremap_resource(&pdev->dev, regs_pmerr);
1158         if (IS_ERR(host->pmerrloc_base)) {
1159                 err_no = PTR_ERR(host->pmerrloc_base);
1160                 goto err;
1161         }
1162 
1163         regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1164         host->pmecc_rom_base = devm_ioremap_resource(&pdev->dev, regs_rom);
1165         if (IS_ERR(host->pmecc_rom_base)) {
1166                 err_no = PTR_ERR(host->pmecc_rom_base);
1167                 goto err;
1168         }
1169 
1170         nand_chip->ecc.size = sector_size;
1171 
1172         /* set ECC page size and oob layout */
1173         switch (mtd->writesize) {
1174         case 512:
1175         case 1024:
1176         case 2048:
1177         case 4096:
1178         case 8192:
1179                 if (sector_size > mtd->writesize) {
1180                         dev_err(host->dev, "pmecc sector size is bigger than the page size!\n");
1181                         err_no = -EINVAL;
1182                         goto err;
1183                 }
1184 
1185                 host->pmecc_degree = (sector_size == 512) ?
1186                         PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
1187                 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
1188                 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
1189                 host->pmecc_index_of = host->pmecc_rom_base +
1190                         host->pmecc_lookup_table_offset;
1191 
1192                 nand_chip->ecc.strength = cap;
1193                 nand_chip->ecc.bytes = pmecc_get_ecc_bytes(cap, sector_size);
1194                 nand_chip->ecc.steps = mtd->writesize / sector_size;
1195                 nand_chip->ecc.total = nand_chip->ecc.bytes *
1196                         nand_chip->ecc.steps;
1197                 if (nand_chip->ecc.total > mtd->oobsize - 2) {
1198                         dev_err(host->dev, "No room for ECC bytes\n");
1199                         err_no = -EINVAL;
1200                         goto err;
1201                 }
1202                 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
1203                                         mtd->oobsize,
1204                                         nand_chip->ecc.total);
1205 
1206                 nand_chip->ecc.layout = &atmel_pmecc_oobinfo;
1207                 break;
1208         default:
1209                 dev_warn(host->dev,
1210                         "Unsupported page size for PMECC, use Software ECC\n");
1211                 /* page size not handled by HW ECC */
1212                 /* switching back to soft ECC */
1213                 nand_chip->ecc.mode = NAND_ECC_SOFT;
1214                 return 0;
1215         }
1216 
1217         /* Allocate data for PMECC computation */
1218         err_no = pmecc_data_alloc(host);
1219         if (err_no) {
1220                 dev_err(host->dev,
1221                                 "Cannot allocate memory for PMECC computation!\n");
1222                 goto err;
1223         }
1224 
1225         nand_chip->options |= NAND_NO_SUBPAGE_WRITE;
1226         nand_chip->ecc.read_page = atmel_nand_pmecc_read_page;
1227         nand_chip->ecc.write_page = atmel_nand_pmecc_write_page;
1228 
1229         atmel_pmecc_core_init(mtd);
1230 
1231         return 0;
1232 
1233 err:
1234         return err_no;
1235 }
1236 
1237 /*
1238  * Calculate HW ECC
1239  *
1240  * function called after a write
1241  *
1242  * mtd:        MTD block structure
1243  * dat:        raw data (unused)
1244  * ecc_code:   buffer for ECC
1245  */
1246 static int atmel_nand_calculate(struct mtd_info *mtd,
1247                 const u_char *dat, unsigned char *ecc_code)
1248 {
1249         struct nand_chip *nand_chip = mtd->priv;
1250         struct atmel_nand_host *host = nand_chip->priv;
1251         unsigned int ecc_value;
1252 
1253         /* get the first 2 ECC bytes */
1254         ecc_value = ecc_readl(host->ecc, PR);
1255 
1256         ecc_code[0] = ecc_value & 0xFF;
1257         ecc_code[1] = (ecc_value >> 8) & 0xFF;
1258 
1259         /* get the last 2 ECC bytes */
1260         ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
1261 
1262         ecc_code[2] = ecc_value & 0xFF;
1263         ecc_code[3] = (ecc_value >> 8) & 0xFF;
1264 
1265         return 0;
1266 }
1267 
1268 /*
1269  * HW ECC read page function
1270  *
1271  * mtd:        mtd info structure
1272  * chip:       nand chip info structure
1273  * buf:        buffer to store read data
1274  * oob_required:    caller expects OOB data read to chip->oob_poi
1275  */
1276 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1277                                 uint8_t *buf, int oob_required, int page)
1278 {
1279         int eccsize = chip->ecc.size;
1280         int eccbytes = chip->ecc.bytes;
1281         uint32_t *eccpos = chip->ecc.layout->eccpos;
1282         uint8_t *p = buf;
1283         uint8_t *oob = chip->oob_poi;
1284         uint8_t *ecc_pos;
1285         int stat;
1286         unsigned int max_bitflips = 0;
1287 
1288         /*
1289          * Errata: ALE is incorrectly wired up to the ECC controller
1290          * on the AP7000, so it will include the address cycles in the
1291          * ECC calculation.
1292          *
1293          * Workaround: Reset the parity registers before reading the
1294          * actual data.
1295          */
1296         struct atmel_nand_host *host = chip->priv;
1297         if (host->board.need_reset_workaround)
1298                 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1299 
1300         /* read the page */
1301         chip->read_buf(mtd, p, eccsize);
1302 
1303         /* move to ECC position if needed */
1304         if (eccpos[0] != 0) {
1305                 /* This only works on large pages
1306                  * because the ECC controller waits for
1307                  * NAND_CMD_RNDOUTSTART after the
1308                  * NAND_CMD_RNDOUT.
1309                  * anyway, for small pages, the eccpos[0] == 0
1310                  */
1311                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1312                                 mtd->writesize + eccpos[0], -1);
1313         }
1314 
1315         /* the ECC controller needs to read the ECC just after the data */
1316         ecc_pos = oob + eccpos[0];
1317         chip->read_buf(mtd, ecc_pos, eccbytes);
1318 
1319         /* check if there's an error */
1320         stat = chip->ecc.correct(mtd, p, oob, NULL);
1321 
1322         if (stat < 0) {
1323                 mtd->ecc_stats.failed++;
1324         } else {
1325                 mtd->ecc_stats.corrected += stat;
1326                 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1327         }
1328 
1329         /* get back to oob start (end of page) */
1330         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1331 
1332         /* read the oob */
1333         chip->read_buf(mtd, oob, mtd->oobsize);
1334 
1335         return max_bitflips;
1336 }
1337 
1338 /*
1339  * HW ECC Correction
1340  *
1341  * function called after a read
1342  *
1343  * mtd:        MTD block structure
1344  * dat:        raw data read from the chip
1345  * read_ecc:   ECC from the chip (unused)
1346  * isnull:     unused
1347  *
1348  * Detect and correct a 1 bit error for a page
1349  */
1350 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1351                 u_char *read_ecc, u_char *isnull)
1352 {
1353         struct nand_chip *nand_chip = mtd->priv;
1354         struct atmel_nand_host *host = nand_chip->priv;
1355         unsigned int ecc_status;
1356         unsigned int ecc_word, ecc_bit;
1357 
1358         /* get the status from the Status Register */
1359         ecc_status = ecc_readl(host->ecc, SR);
1360 
1361         /* if there's no error */
1362         if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1363                 return 0;
1364 
1365         /* get error bit offset (4 bits) */
1366         ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
1367         /* get word address (12 bits) */
1368         ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
1369         ecc_word >>= 4;
1370 
1371         /* if there are multiple errors */
1372         if (ecc_status & ATMEL_ECC_MULERR) {
1373                 /* check if it is a freshly erased block
1374                  * (filled with 0xff) */
1375                 if ((ecc_bit == ATMEL_ECC_BITADDR)
1376                                 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1377                         /* the block has just been erased, return OK */
1378                         return 0;
1379                 }
1380                 /* it doesn't seems to be a freshly
1381                  * erased block.
1382                  * We can't correct so many errors */
1383                 dev_dbg(host->dev, "atmel_nand : multiple errors detected."
1384                                 " Unable to correct.\n");
1385                 return -EIO;
1386         }
1387 
1388         /* if there's a single bit error : we can correct it */
1389         if (ecc_status & ATMEL_ECC_ECCERR) {
1390                 /* there's nothing much to do here.
1391                  * the bit error is on the ECC itself.
1392                  */
1393                 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
1394                                 " Nothing to correct\n");
1395                 return 0;
1396         }
1397 
1398         dev_dbg(host->dev, "atmel_nand : one bit error on data."
1399                         " (word offset in the page :"
1400                         " 0x%x bit offset : 0x%x)\n",
1401                         ecc_word, ecc_bit);
1402         /* correct the error */
1403         if (nand_chip->options & NAND_BUSWIDTH_16) {
1404                 /* 16 bits words */
1405                 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1406         } else {
1407                 /* 8 bits words */
1408                 dat[ecc_word] ^= (1 << ecc_bit);
1409         }
1410         dev_dbg(host->dev, "atmel_nand : error corrected\n");
1411         return 1;
1412 }
1413 
1414 /*
1415  * Enable HW ECC : unused on most chips
1416  */
1417 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1418 {
1419         struct nand_chip *nand_chip = mtd->priv;
1420         struct atmel_nand_host *host = nand_chip->priv;
1421 
1422         if (host->board.need_reset_workaround)
1423                 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1424 }
1425 
1426 static int atmel_of_init_port(struct atmel_nand_host *host,
1427                               struct device_node *np)
1428 {
1429         u32 val;
1430         u32 offset[2];
1431         int ecc_mode;
1432         struct atmel_nand_data *board = &host->board;
1433         enum of_gpio_flags flags = 0;
1434 
1435         if (of_property_read_u32(np, "atmel,nand-addr-offset", &val) == 0) {
1436                 if (val >= 32) {
1437                         dev_err(host->dev, "invalid addr-offset %u\n", val);
1438                         return -EINVAL;
1439                 }
1440                 board->ale = val;
1441         }
1442 
1443         if (of_property_read_u32(np, "atmel,nand-cmd-offset", &val) == 0) {
1444                 if (val >= 32) {
1445                         dev_err(host->dev, "invalid cmd-offset %u\n", val);
1446                         return -EINVAL;
1447                 }
1448                 board->cle = val;
1449         }
1450 
1451         ecc_mode = of_get_nand_ecc_mode(np);
1452 
1453         board->ecc_mode = ecc_mode < 0 ? NAND_ECC_SOFT : ecc_mode;
1454 
1455         board->on_flash_bbt = of_get_nand_on_flash_bbt(np);
1456 
1457         board->has_dma = of_property_read_bool(np, "atmel,nand-has-dma");
1458 
1459         if (of_get_nand_bus_width(np) == 16)
1460                 board->bus_width_16 = 1;
1461 
1462         board->rdy_pin = of_get_gpio_flags(np, 0, &flags);
1463         board->rdy_pin_active_low = (flags == OF_GPIO_ACTIVE_LOW);
1464 
1465         board->enable_pin = of_get_gpio(np, 1);
1466         board->det_pin = of_get_gpio(np, 2);
1467 
1468         host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
1469 
1470         /* load the nfc driver if there is */
1471         of_platform_populate(np, NULL, NULL, host->dev);
1472 
1473         if (!(board->ecc_mode == NAND_ECC_HW) || !host->has_pmecc)
1474                 return 0;       /* Not using PMECC */
1475 
1476         /* use PMECC, get correction capability, sector size and lookup
1477          * table offset.
1478          * If correction bits and sector size are not specified, then find
1479          * them from NAND ONFI parameters.
1480          */
1481         if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
1482                 if ((val != 2) && (val != 4) && (val != 8) && (val != 12) &&
1483                                 (val != 24)) {
1484                         dev_err(host->dev,
1485                                 "Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n",
1486                                 val);
1487                         return -EINVAL;
1488                 }
1489                 host->pmecc_corr_cap = (u8)val;
1490         }
1491 
1492         if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) {
1493                 if ((val != 512) && (val != 1024)) {
1494                         dev_err(host->dev,
1495                                 "Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n",
1496                                 val);
1497                         return -EINVAL;
1498                 }
1499                 host->pmecc_sector_size = (u16)val;
1500         }
1501 
1502         if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset",
1503                         offset, 2) != 0) {
1504                 dev_err(host->dev, "Cannot get PMECC lookup table offset\n");
1505                 return -EINVAL;
1506         }
1507         if (!offset[0] && !offset[1]) {
1508                 dev_err(host->dev, "Invalid PMECC lookup table offset\n");
1509                 return -EINVAL;
1510         }
1511         host->pmecc_lookup_table_offset_512 = offset[0];
1512         host->pmecc_lookup_table_offset_1024 = offset[1];
1513 
1514         return 0;
1515 }
1516 
1517 static int atmel_hw_nand_init_params(struct platform_device *pdev,
1518                                          struct atmel_nand_host *host)
1519 {
1520         struct mtd_info *mtd = &host->mtd;
1521         struct nand_chip *nand_chip = &host->nand_chip;
1522         struct resource         *regs;
1523 
1524         regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1525         if (!regs) {
1526                 dev_err(host->dev,
1527                         "Can't get I/O resource regs, use software ECC\n");
1528                 nand_chip->ecc.mode = NAND_ECC_SOFT;
1529                 return 0;
1530         }
1531 
1532         host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1533         if (IS_ERR(host->ecc))
1534                 return PTR_ERR(host->ecc);
1535 
1536         /* ECC is calculated for the whole page (1 step) */
1537         nand_chip->ecc.size = mtd->writesize;
1538 
1539         /* set ECC page size and oob layout */
1540         switch (mtd->writesize) {
1541         case 512:
1542                 nand_chip->ecc.layout = &atmel_oobinfo_small;
1543                 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
1544                 break;
1545         case 1024:
1546                 nand_chip->ecc.layout = &atmel_oobinfo_large;
1547                 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
1548                 break;
1549         case 2048:
1550                 nand_chip->ecc.layout = &atmel_oobinfo_large;
1551                 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
1552                 break;
1553         case 4096:
1554                 nand_chip->ecc.layout = &atmel_oobinfo_large;
1555                 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
1556                 break;
1557         default:
1558                 /* page size not handled by HW ECC */
1559                 /* switching back to soft ECC */
1560                 nand_chip->ecc.mode = NAND_ECC_SOFT;
1561                 return 0;
1562         }
1563 
1564         /* set up for HW ECC */
1565         nand_chip->ecc.calculate = atmel_nand_calculate;
1566         nand_chip->ecc.correct = atmel_nand_correct;
1567         nand_chip->ecc.hwctl = atmel_nand_hwctl;
1568         nand_chip->ecc.read_page = atmel_nand_read_page;
1569         nand_chip->ecc.bytes = 4;
1570         nand_chip->ecc.strength = 1;
1571 
1572         return 0;
1573 }
1574 
1575 static inline u32 nfc_read_status(struct atmel_nand_host *host)
1576 {
1577         u32 err_flags = NFC_SR_DTOE | NFC_SR_UNDEF | NFC_SR_AWB | NFC_SR_ASE;
1578         u32 nfc_status = nfc_readl(host->nfc->hsmc_regs, SR);
1579 
1580         if (unlikely(nfc_status & err_flags)) {
1581                 if (nfc_status & NFC_SR_DTOE)
1582                         dev_err(host->dev, "NFC: Waiting Nand R/B Timeout Error\n");
1583                 else if (nfc_status & NFC_SR_UNDEF)
1584                         dev_err(host->dev, "NFC: Access Undefined Area Error\n");
1585                 else if (nfc_status & NFC_SR_AWB)
1586                         dev_err(host->dev, "NFC: Access memory While NFC is busy\n");
1587                 else if (nfc_status & NFC_SR_ASE)
1588                         dev_err(host->dev, "NFC: Access memory Size Error\n");
1589         }
1590 
1591         return nfc_status;
1592 }
1593 
1594 /* SMC interrupt service routine */
1595 static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
1596 {
1597         struct atmel_nand_host *host = dev_id;
1598         u32 status, mask, pending;
1599         irqreturn_t ret = IRQ_NONE;
1600 
1601         status = nfc_read_status(host);
1602         mask = nfc_readl(host->nfc->hsmc_regs, IMR);
1603         pending = status & mask;
1604 
1605         if (pending & NFC_SR_XFR_DONE) {
1606                 complete(&host->nfc->comp_xfer_done);
1607                 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_XFR_DONE);
1608                 ret = IRQ_HANDLED;
1609         }
1610         if (pending & NFC_SR_RB_EDGE) {
1611                 complete(&host->nfc->comp_ready);
1612                 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_RB_EDGE);
1613                 ret = IRQ_HANDLED;
1614         }
1615         if (pending & NFC_SR_CMD_DONE) {
1616                 complete(&host->nfc->comp_cmd_done);
1617                 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_CMD_DONE);
1618                 ret = IRQ_HANDLED;
1619         }
1620 
1621         return ret;
1622 }
1623 
1624 /* NFC(Nand Flash Controller) related functions */
1625 static void nfc_prepare_interrupt(struct atmel_nand_host *host, u32 flag)
1626 {
1627         if (flag & NFC_SR_XFR_DONE)
1628                 init_completion(&host->nfc->comp_xfer_done);
1629 
1630         if (flag & NFC_SR_RB_EDGE)
1631                 init_completion(&host->nfc->comp_ready);
1632 
1633         if (flag & NFC_SR_CMD_DONE)
1634                 init_completion(&host->nfc->comp_cmd_done);
1635 
1636         /* Enable interrupt that need to wait for */
1637         nfc_writel(host->nfc->hsmc_regs, IER, flag);
1638 }
1639 
1640 static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag)
1641 {
1642         int i, index = 0;
1643         struct completion *comp[3];     /* Support 3 interrupt completion */
1644 
1645         if (flag & NFC_SR_XFR_DONE)
1646                 comp[index++] = &host->nfc->comp_xfer_done;
1647 
1648         if (flag & NFC_SR_RB_EDGE)
1649                 comp[index++] = &host->nfc->comp_ready;
1650 
1651         if (flag & NFC_SR_CMD_DONE)
1652                 comp[index++] = &host->nfc->comp_cmd_done;
1653 
1654         if (index == 0) {
1655                 dev_err(host->dev, "Unkown interrupt flag: 0x%08x\n", flag);
1656                 return -EINVAL;
1657         }
1658 
1659         for (i = 0; i < index; i++) {
1660                 if (wait_for_completion_timeout(comp[i],
1661                                 msecs_to_jiffies(NFC_TIME_OUT_MS)))
1662                         continue;       /* wait for next completion */
1663                 else
1664                         goto err_timeout;
1665         }
1666 
1667         return 0;
1668 
1669 err_timeout:
1670         dev_err(host->dev, "Time out to wait for interrupt: 0x%08x\n", flag);
1671         /* Disable the interrupt as it is not handled by interrupt handler */
1672         nfc_writel(host->nfc->hsmc_regs, IDR, flag);
1673         return -ETIMEDOUT;
1674 }
1675 
1676 static int nfc_send_command(struct atmel_nand_host *host,
1677         unsigned int cmd, unsigned int addr, unsigned char cycle0)
1678 {
1679         unsigned long timeout;
1680         u32 flag = NFC_SR_CMD_DONE;
1681         flag |= cmd & NFCADDR_CMD_DATAEN ? NFC_SR_XFR_DONE : 0;
1682 
1683         dev_dbg(host->dev,
1684                 "nfc_cmd: 0x%08x, addr1234: 0x%08x, cycle0: 0x%02x\n",
1685                 cmd, addr, cycle0);
1686 
1687         timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1688         while (nfc_cmd_readl(NFCADDR_CMD_NFCBUSY, host->nfc->base_cmd_regs)
1689                         & NFCADDR_CMD_NFCBUSY) {
1690                 if (time_after(jiffies, timeout)) {
1691                         dev_err(host->dev,
1692                                 "Time out to wait CMD_NFCBUSY ready!\n");
1693                         return -ETIMEDOUT;
1694                 }
1695         }
1696 
1697         nfc_prepare_interrupt(host, flag);
1698         nfc_writel(host->nfc->hsmc_regs, CYCLE0, cycle0);
1699         nfc_cmd_addr1234_writel(cmd, addr, host->nfc->base_cmd_regs);
1700         return nfc_wait_interrupt(host, flag);
1701 }
1702 
1703 static int nfc_device_ready(struct mtd_info *mtd)
1704 {
1705         u32 status, mask;
1706         struct nand_chip *nand_chip = mtd->priv;
1707         struct atmel_nand_host *host = nand_chip->priv;
1708 
1709         status = nfc_read_status(host);
1710         mask = nfc_readl(host->nfc->hsmc_regs, IMR);
1711 
1712         /* The mask should be 0. If not we may lost interrupts */
1713         if (unlikely(mask & status))
1714                 dev_err(host->dev, "Lost the interrupt flags: 0x%08x\n",
1715                                 mask & status);
1716 
1717         return status & NFC_SR_RB_EDGE;
1718 }
1719 
1720 static void nfc_select_chip(struct mtd_info *mtd, int chip)
1721 {
1722         struct nand_chip *nand_chip = mtd->priv;
1723         struct atmel_nand_host *host = nand_chip->priv;
1724 
1725         if (chip == -1)
1726                 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_DISABLE);
1727         else
1728                 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_ENABLE);
1729 }
1730 
1731 static int nfc_make_addr(struct mtd_info *mtd, int command, int column,
1732                 int page_addr, unsigned int *addr1234, unsigned int *cycle0)
1733 {
1734         struct nand_chip *chip = mtd->priv;
1735 
1736         int acycle = 0;
1737         unsigned char addr_bytes[8];
1738         int index = 0, bit_shift;
1739 
1740         BUG_ON(addr1234 == NULL || cycle0 == NULL);
1741 
1742         *cycle0 = 0;
1743         *addr1234 = 0;
1744 
1745         if (column != -1) {
1746                 if (chip->options & NAND_BUSWIDTH_16 &&
1747                                 !nand_opcode_8bits(command))
1748                         column >>= 1;
1749                 addr_bytes[acycle++] = column & 0xff;
1750                 if (mtd->writesize > 512)
1751                         addr_bytes[acycle++] = (column >> 8) & 0xff;
1752         }
1753 
1754         if (page_addr != -1) {
1755                 addr_bytes[acycle++] = page_addr & 0xff;
1756                 addr_bytes[acycle++] = (page_addr >> 8) & 0xff;
1757                 if (chip->chipsize > (128 << 20))
1758                         addr_bytes[acycle++] = (page_addr >> 16) & 0xff;
1759         }
1760 
1761         if (acycle > 4)
1762                 *cycle0 = addr_bytes[index++];
1763 
1764         for (bit_shift = 0; index < acycle; bit_shift += 8)
1765                 *addr1234 += addr_bytes[index++] << bit_shift;
1766 
1767         /* return acycle in cmd register */
1768         return acycle << NFCADDR_CMD_ACYCLE_BIT_POS;
1769 }
1770 
1771 static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
1772                                 int column, int page_addr)
1773 {
1774         struct nand_chip *chip = mtd->priv;
1775         struct atmel_nand_host *host = chip->priv;
1776         unsigned long timeout;
1777         unsigned int nfc_addr_cmd = 0;
1778 
1779         unsigned int cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1780 
1781         /* Set default settings: no cmd2, no addr cycle. read from nand */
1782         unsigned int cmd2 = 0;
1783         unsigned int vcmd2 = 0;
1784         int acycle = NFCADDR_CMD_ACYCLE_NONE;
1785         int csid = NFCADDR_CMD_CSID_3;
1786         int dataen = NFCADDR_CMD_DATADIS;
1787         int nfcwr = NFCADDR_CMD_NFCRD;
1788         unsigned int addr1234 = 0;
1789         unsigned int cycle0 = 0;
1790         bool do_addr = true;
1791         host->nfc->data_in_sram = NULL;
1792 
1793         dev_dbg(host->dev, "%s: cmd = 0x%02x, col = 0x%08x, page = 0x%08x\n",
1794              __func__, command, column, page_addr);
1795 
1796         switch (command) {
1797         case NAND_CMD_RESET:
1798                 nfc_addr_cmd = cmd1 | acycle | csid | dataen | nfcwr;
1799                 nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1800                 udelay(chip->chip_delay);
1801 
1802                 nfc_nand_command(mtd, NAND_CMD_STATUS, -1, -1);
1803                 timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1804                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) {
1805                         if (time_after(jiffies, timeout)) {
1806                                 dev_err(host->dev,
1807                                         "Time out to wait status ready!\n");
1808                                 break;
1809                         }
1810                 }
1811                 return;
1812         case NAND_CMD_STATUS:
1813                 do_addr = false;
1814                 break;
1815         case NAND_CMD_PARAM:
1816         case NAND_CMD_READID:
1817                 do_addr = false;
1818                 acycle = NFCADDR_CMD_ACYCLE_1;
1819                 if (column != -1)
1820                         addr1234 = column;
1821                 break;
1822         case NAND_CMD_RNDOUT:
1823                 cmd2 = NAND_CMD_RNDOUTSTART << NFCADDR_CMD_CMD2_BIT_POS;
1824                 vcmd2 = NFCADDR_CMD_VCMD2;
1825                 break;
1826         case NAND_CMD_READ0:
1827         case NAND_CMD_READOOB:
1828                 if (command == NAND_CMD_READOOB) {
1829                         column += mtd->writesize;
1830                         command = NAND_CMD_READ0; /* only READ0 is valid */
1831                         cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1832                 }
1833                 if (host->nfc->use_nfc_sram) {
1834                         /* Enable Data transfer to sram */
1835                         dataen = NFCADDR_CMD_DATAEN;
1836 
1837                         /* Need enable PMECC now, since NFC will transfer
1838                          * data in bus after sending nfc read command.
1839                          */
1840                         if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
1841                                 pmecc_enable(host, NAND_ECC_READ);
1842                 }
1843 
1844                 cmd2 = NAND_CMD_READSTART << NFCADDR_CMD_CMD2_BIT_POS;
1845                 vcmd2 = NFCADDR_CMD_VCMD2;
1846                 break;
1847         /* For prgramming command, the cmd need set to write enable */
1848         case NAND_CMD_PAGEPROG:
1849         case NAND_CMD_SEQIN:
1850         case NAND_CMD_RNDIN:
1851                 nfcwr = NFCADDR_CMD_NFCWR;
1852                 if (host->nfc->will_write_sram && command == NAND_CMD_SEQIN)
1853                         dataen = NFCADDR_CMD_DATAEN;
1854                 break;
1855         default:
1856                 break;
1857         }
1858 
1859         if (do_addr)
1860                 acycle = nfc_make_addr(mtd, command, column, page_addr,
1861                                 &addr1234, &cycle0);
1862 
1863         nfc_addr_cmd = cmd1 | cmd2 | vcmd2 | acycle | csid | dataen | nfcwr;
1864         nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1865 
1866         /*
1867          * Program and erase have their own busy handlers status, sequential
1868          * in, and deplete1 need no delay.
1869          */
1870         switch (command) {
1871         case NAND_CMD_CACHEDPROG:
1872         case NAND_CMD_PAGEPROG:
1873         case NAND_CMD_ERASE1:
1874         case NAND_CMD_ERASE2:
1875         case NAND_CMD_RNDIN:
1876         case NAND_CMD_STATUS:
1877         case NAND_CMD_RNDOUT:
1878         case NAND_CMD_SEQIN:
1879         case NAND_CMD_READID:
1880                 return;
1881 
1882         case NAND_CMD_READ0:
1883                 if (dataen == NFCADDR_CMD_DATAEN) {
1884                         host->nfc->data_in_sram = host->nfc->sram_bank0 +
1885                                 nfc_get_sram_off(host);
1886                         return;
1887                 }
1888                 /* fall through */
1889         default:
1890                 nfc_prepare_interrupt(host, NFC_SR_RB_EDGE);
1891                 nfc_wait_interrupt(host, NFC_SR_RB_EDGE);
1892         }
1893 }
1894 
1895 static int nfc_sram_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1896                         uint32_t offset, int data_len, const uint8_t *buf,
1897                         int oob_required, int page, int cached, int raw)
1898 {
1899         int cfg, len;
1900         int status = 0;
1901         struct atmel_nand_host *host = chip->priv;
1902         void __iomem *sram = host->nfc->sram_bank0 + nfc_get_sram_off(host);
1903 
1904         /* Subpage write is not supported */
1905         if (offset || (data_len < mtd->writesize))
1906                 return -EINVAL;
1907 
1908         len = mtd->writesize;
1909         /* Copy page data to sram that will write to nand via NFC */
1910         if (use_dma) {
1911                 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) != 0)
1912                         /* Fall back to use cpu copy */
1913                         memcpy32_toio(sram, buf, len);
1914         } else {
1915                 memcpy32_toio(sram, buf, len);
1916         }
1917 
1918         cfg = nfc_readl(host->nfc->hsmc_regs, CFG);
1919         if (unlikely(raw) && oob_required) {
1920                 memcpy32_toio(sram + len, chip->oob_poi, mtd->oobsize);
1921                 len += mtd->oobsize;
1922                 nfc_writel(host->nfc->hsmc_regs, CFG, cfg | NFC_CFG_WSPARE);
1923         } else {
1924                 nfc_writel(host->nfc->hsmc_regs, CFG, cfg & ~NFC_CFG_WSPARE);
1925         }
1926 
1927         if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
1928                 /*
1929                  * When use NFC sram, need set up PMECC before send
1930                  * NAND_CMD_SEQIN command. Since when the nand command
1931                  * is sent, nfc will do transfer from sram and nand.
1932                  */
1933                 pmecc_enable(host, NAND_ECC_WRITE);
1934 
1935         host->nfc->will_write_sram = true;
1936         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1937         host->nfc->will_write_sram = false;
1938 
1939         if (likely(!raw))
1940                 /* Need to write ecc into oob */
1941                 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
1942 
1943         if (status < 0)
1944                 return status;
1945 
1946         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1947         status = chip->waitfunc(mtd, chip);
1948 
1949         if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1950                 status = chip->errstat(mtd, chip, FL_WRITING, status, page);
1951 
1952         if (status & NAND_STATUS_FAIL)
1953                 return -EIO;
1954 
1955         return 0;
1956 }
1957 
1958 static int nfc_sram_init(struct mtd_info *mtd)
1959 {
1960         struct nand_chip *chip = mtd->priv;
1961         struct atmel_nand_host *host = chip->priv;
1962         int res = 0;
1963 
1964         /* Initialize the NFC CFG register */
1965         unsigned int cfg_nfc = 0;
1966 
1967         /* set page size and oob layout */
1968         switch (mtd->writesize) {
1969         case 512:
1970                 cfg_nfc = NFC_CFG_PAGESIZE_512;
1971                 break;
1972         case 1024:
1973                 cfg_nfc = NFC_CFG_PAGESIZE_1024;
1974                 break;
1975         case 2048:
1976                 cfg_nfc = NFC_CFG_PAGESIZE_2048;
1977                 break;
1978         case 4096:
1979                 cfg_nfc = NFC_CFG_PAGESIZE_4096;
1980                 break;
1981         case 8192:
1982                 cfg_nfc = NFC_CFG_PAGESIZE_8192;
1983                 break;
1984         default:
1985                 dev_err(host->dev, "Unsupported page size for NFC.\n");
1986                 res = -ENXIO;
1987                 return res;
1988         }
1989 
1990         /* oob bytes size = (NFCSPARESIZE + 1) * 4
1991          * Max support spare size is 512 bytes. */
1992         cfg_nfc |= (((mtd->oobsize / 4) - 1) << NFC_CFG_NFC_SPARESIZE_BIT_POS
1993                 & NFC_CFG_NFC_SPARESIZE);
1994         /* default set a max timeout */
1995         cfg_nfc |= NFC_CFG_RSPARE |
1996                         NFC_CFG_NFC_DTOCYC | NFC_CFG_NFC_DTOMUL;
1997 
1998         nfc_writel(host->nfc->hsmc_regs, CFG, cfg_nfc);
1999 
2000         host->nfc->will_write_sram = false;
2001         nfc_set_sram_bank(host, 0);
2002 
2003         /* Use Write page with NFC SRAM only for PMECC or ECC NONE. */
2004         if (host->nfc->write_by_sram) {
2005                 if ((chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) ||
2006                                 chip->ecc.mode == NAND_ECC_NONE)
2007                         chip->write_page = nfc_sram_write_page;
2008                 else
2009                         host->nfc->write_by_sram = false;
2010         }
2011 
2012         dev_info(host->dev, "Using NFC Sram read %s\n",
2013                         host->nfc->write_by_sram ? "and write" : "");
2014         return 0;
2015 }
2016 
2017 static struct platform_driver atmel_nand_nfc_driver;
2018 /*
2019  * Probe for the NAND device.
2020  */
2021 static int atmel_nand_probe(struct platform_device *pdev)
2022 {
2023         struct atmel_nand_host *host;
2024         struct mtd_info *mtd;
2025         struct nand_chip *nand_chip;
2026         struct resource *mem;
2027         struct mtd_part_parser_data ppdata = {};
2028         int res, irq;
2029 
2030         /* Allocate memory for the device structure (and zero it) */
2031         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
2032         if (!host)
2033                 return -ENOMEM;
2034 
2035         res = platform_driver_register(&atmel_nand_nfc_driver);
2036         if (res)
2037                 dev_err(&pdev->dev, "atmel_nand: can't register NFC driver\n");
2038 
2039         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2040         host->io_base = devm_ioremap_resource(&pdev->dev, mem);
2041         if (IS_ERR(host->io_base)) {
2042                 res = PTR_ERR(host->io_base);
2043                 goto err_nand_ioremap;
2044         }
2045         host->io_phys = (dma_addr_t)mem->start;
2046 
2047         mtd = &host->mtd;
2048         nand_chip = &host->nand_chip;
2049         host->dev = &pdev->dev;
2050         if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
2051                 /* Only when CONFIG_OF is enabled of_node can be parsed */
2052                 res = atmel_of_init_port(host, pdev->dev.of_node);
2053                 if (res)
2054                         goto err_nand_ioremap;
2055         } else {
2056                 memcpy(&host->board, dev_get_platdata(&pdev->dev),
2057                        sizeof(struct atmel_nand_data));
2058         }
2059 
2060         nand_chip->priv = host;         /* link the private data structures */
2061         mtd->priv = nand_chip;
2062         mtd->owner = THIS_MODULE;
2063 
2064         /* Set address of NAND IO lines */
2065         nand_chip->IO_ADDR_R = host->io_base;
2066         nand_chip->IO_ADDR_W = host->io_base;
2067 
2068         if (nand_nfc.is_initialized) {
2069                 /* NFC driver is probed and initialized */
2070                 host->nfc = &nand_nfc;
2071 
2072                 nand_chip->select_chip = nfc_select_chip;
2073                 nand_chip->dev_ready = nfc_device_ready;
2074                 nand_chip->cmdfunc = nfc_nand_command;
2075 
2076                 /* Initialize the interrupt for NFC */
2077                 irq = platform_get_irq(pdev, 0);
2078                 if (irq < 0) {
2079                         dev_err(host->dev, "Cannot get HSMC irq!\n");
2080                         res = irq;
2081                         goto err_nand_ioremap;
2082                 }
2083 
2084                 res = devm_request_irq(&pdev->dev, irq, hsmc_interrupt,
2085                                 0, "hsmc", host);
2086                 if (res) {
2087                         dev_err(&pdev->dev, "Unable to request HSMC irq %d\n",
2088                                 irq);
2089                         goto err_nand_ioremap;
2090                 }
2091         } else {
2092                 res = atmel_nand_set_enable_ready_pins(mtd);
2093                 if (res)
2094                         goto err_nand_ioremap;
2095 
2096                 nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
2097         }
2098 
2099         nand_chip->ecc.mode = host->board.ecc_mode;
2100         nand_chip->chip_delay = 40;             /* 40us command delay time */
2101 
2102         if (host->board.bus_width_16)   /* 16-bit bus width */
2103                 nand_chip->options |= NAND_BUSWIDTH_16;
2104 
2105         nand_chip->read_buf = atmel_read_buf;
2106         nand_chip->write_buf = atmel_write_buf;
2107 
2108         platform_set_drvdata(pdev, host);
2109         atmel_nand_enable(host);
2110 
2111         if (gpio_is_valid(host->board.det_pin)) {
2112                 res = devm_gpio_request(&pdev->dev,
2113                                 host->board.det_pin, "nand_det");
2114                 if (res < 0) {
2115                         dev_err(&pdev->dev,
2116                                 "can't request det gpio %d\n",
2117                                 host->board.det_pin);
2118                         goto err_no_card;
2119                 }
2120 
2121                 res = gpio_direction_input(host->board.det_pin);
2122                 if (res < 0) {
2123                         dev_err(&pdev->dev,
2124                                 "can't request input direction det gpio %d\n",
2125                                 host->board.det_pin);
2126                         goto err_no_card;
2127                 }
2128 
2129                 if (gpio_get_value(host->board.det_pin)) {
2130                         dev_info(&pdev->dev, "No SmartMedia card inserted.\n");
2131                         res = -ENXIO;
2132                         goto err_no_card;
2133                 }
2134         }
2135 
2136         if (host->board.on_flash_bbt || on_flash_bbt) {
2137                 dev_info(&pdev->dev, "Use On Flash BBT\n");
2138                 nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
2139         }
2140 
2141         if (!host->board.has_dma)
2142                 use_dma = 0;
2143 
2144         if (use_dma) {
2145                 dma_cap_mask_t mask;
2146 
2147                 dma_cap_zero(mask);
2148                 dma_cap_set(DMA_MEMCPY, mask);
2149                 host->dma_chan = dma_request_channel(mask, NULL, NULL);
2150                 if (!host->dma_chan) {
2151                         dev_err(host->dev, "Failed to request DMA channel\n");
2152                         use_dma = 0;
2153                 }
2154         }
2155         if (use_dma)
2156                 dev_info(host->dev, "Using %s for DMA transfers.\n",
2157                                         dma_chan_name(host->dma_chan));
2158         else
2159                 dev_info(host->dev, "No DMA support for NAND access.\n");
2160 
2161         /* first scan to find the device and get the page size */
2162         if (nand_scan_ident(mtd, 1, NULL)) {
2163                 res = -ENXIO;
2164                 goto err_scan_ident;
2165         }
2166 
2167         if (nand_chip->ecc.mode == NAND_ECC_HW) {
2168                 if (host->has_pmecc)
2169                         res = atmel_pmecc_nand_init_params(pdev, host);
2170                 else
2171                         res = atmel_hw_nand_init_params(pdev, host);
2172 
2173                 if (res != 0)
2174                         goto err_hw_ecc;
2175         }
2176 
2177         /* initialize the nfc configuration register */
2178         if (host->nfc && host->nfc->use_nfc_sram) {
2179                 res = nfc_sram_init(mtd);
2180                 if (res) {
2181                         host->nfc->use_nfc_sram = false;
2182                         dev_err(host->dev, "Disable use nfc sram for data transfer.\n");
2183                 }
2184         }
2185 
2186         /* second phase scan */
2187         if (nand_scan_tail(mtd)) {
2188                 res = -ENXIO;
2189                 goto err_scan_tail;
2190         }
2191 
2192         mtd->name = "atmel_nand";
2193         ppdata.of_node = pdev->dev.of_node;
2194         res = mtd_device_parse_register(mtd, NULL, &ppdata,
2195                         host->board.parts, host->board.num_parts);
2196         if (!res)
2197                 return res;
2198 
2199 err_scan_tail:
2200         if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW)
2201                 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
2202 err_hw_ecc:
2203 err_scan_ident:
2204 err_no_card:
2205         atmel_nand_disable(host);
2206         if (host->dma_chan)
2207                 dma_release_channel(host->dma_chan);
2208 err_nand_ioremap:
2209         return res;
2210 }
2211 
2212 /*
2213  * Remove a NAND device.
2214  */
2215 static int atmel_nand_remove(struct platform_device *pdev)
2216 {
2217         struct atmel_nand_host *host = platform_get_drvdata(pdev);
2218         struct mtd_info *mtd = &host->mtd;
2219 
2220         nand_release(mtd);
2221 
2222         atmel_nand_disable(host);
2223 
2224         if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
2225                 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
2226                 pmerrloc_writel(host->pmerrloc_base, ELDIS,
2227                                 PMERRLOC_DISABLE);
2228         }
2229 
2230         if (host->dma_chan)
2231                 dma_release_channel(host->dma_chan);
2232 
2233         platform_driver_unregister(&atmel_nand_nfc_driver);
2234 
2235         return 0;
2236 }
2237 
2238 static const struct of_device_id atmel_nand_dt_ids[] = {
2239         { .compatible = "atmel,at91rm9200-nand" },
2240         { /* sentinel */ }
2241 };
2242 
2243 MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids);
2244 
2245 static int atmel_nand_nfc_probe(struct platform_device *pdev)
2246 {
2247         struct atmel_nfc *nfc = &nand_nfc;
2248         struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram;
2249         int ret;
2250 
2251         nfc_cmd_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2252         nfc->base_cmd_regs = devm_ioremap_resource(&pdev->dev, nfc_cmd_regs);
2253         if (IS_ERR(nfc->base_cmd_regs))
2254                 return PTR_ERR(nfc->base_cmd_regs);
2255 
2256         nfc_hsmc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2257         nfc->hsmc_regs = devm_ioremap_resource(&pdev->dev, nfc_hsmc_regs);
2258         if (IS_ERR(nfc->hsmc_regs))
2259                 return PTR_ERR(nfc->hsmc_regs);
2260 
2261         nfc_sram = platform_get_resource(pdev, IORESOURCE_MEM, 2);
2262         if (nfc_sram) {
2263                 nfc->sram_bank0 = devm_ioremap_resource(&pdev->dev, nfc_sram);
2264                 if (IS_ERR(nfc->sram_bank0)) {
2265                         dev_warn(&pdev->dev, "Fail to ioremap the NFC sram with error: %ld. So disable NFC sram.\n",
2266                                         PTR_ERR(nfc->sram_bank0));
2267                 } else {
2268                         nfc->use_nfc_sram = true;
2269                         nfc->sram_bank0_phys = (dma_addr_t)nfc_sram->start;
2270 
2271                         if (pdev->dev.of_node)
2272                                 nfc->write_by_sram = of_property_read_bool(
2273                                                 pdev->dev.of_node,
2274                                                 "atmel,write-by-sram");
2275                 }
2276         }
2277 
2278         nfc_writel(nfc->hsmc_regs, IDR, 0xffffffff);
2279         nfc_readl(nfc->hsmc_regs, SR);  /* clear the NFC_SR */
2280 
2281         nfc->clk = devm_clk_get(&pdev->dev, NULL);
2282         if (!IS_ERR(nfc->clk)) {
2283                 ret = clk_prepare_enable(nfc->clk);
2284                 if (ret)
2285                         return ret;
2286         } else {
2287                 dev_warn(&pdev->dev, "NFC clock missing, update your Device Tree");
2288         }
2289 
2290         nfc->is_initialized = true;
2291         dev_info(&pdev->dev, "NFC is probed.\n");
2292 
2293         return 0;
2294 }
2295 
2296 static int atmel_nand_nfc_remove(struct platform_device *pdev)
2297 {
2298         struct atmel_nfc *nfc = &nand_nfc;
2299 
2300         if (!IS_ERR(nfc->clk))
2301                 clk_disable_unprepare(nfc->clk);
2302 
2303         return 0;
2304 }
2305 
2306 static const struct of_device_id atmel_nand_nfc_match[] = {
2307         { .compatible = "atmel,sama5d3-nfc" },
2308         { /* sentinel */ }
2309 };
2310 MODULE_DEVICE_TABLE(of, atmel_nand_nfc_match);
2311 
2312 static struct platform_driver atmel_nand_nfc_driver = {
2313         .driver = {
2314                 .name = "atmel_nand_nfc",
2315                 .owner = THIS_MODULE,
2316                 .of_match_table = of_match_ptr(atmel_nand_nfc_match),
2317         },
2318         .probe = atmel_nand_nfc_probe,
2319         .remove = atmel_nand_nfc_remove,
2320 };
2321 
2322 static struct platform_driver atmel_nand_driver = {
2323         .probe          = atmel_nand_probe,
2324         .remove         = atmel_nand_remove,
2325         .driver         = {
2326                 .name   = "atmel_nand",
2327                 .owner  = THIS_MODULE,
2328                 .of_match_table = of_match_ptr(atmel_nand_dt_ids),
2329         },
2330 };
2331 
2332 module_platform_driver(atmel_nand_driver);
2333 
2334 MODULE_LICENSE("GPL");
2335 MODULE_AUTHOR("Rick Bronson");
2336 MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
2337 MODULE_ALIAS("platform:atmel_nand");
2338 

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