Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/mtd/nand/atmel_nand.c

  1 /*
  2  *  Copyright © 2003 Rick Bronson
  3  *
  4  *  Derived from drivers/mtd/nand/autcpu12.c
  5  *       Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
  6  *
  7  *  Derived from drivers/mtd/spia.c
  8  *       Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
  9  *
 10  *
 11  *  Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
 12  *     Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
 13  *
 14  *     Derived from Das U-Boot source code
 15  *              (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
 16  *     © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
 17  *
 18  *  Add Programmable Multibit ECC support for various AT91 SoC
 19  *     © Copyright 2012 ATMEL, Hong Xu
 20  *
 21  *  Add Nand Flash Controller support for SAMA5 SoC
 22  *     © Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
 23  *
 24  * This program is free software; you can redistribute it and/or modify
 25  * it under the terms of the GNU General Public License version 2 as
 26  * published by the Free Software Foundation.
 27  *
 28  */
 29 
 30 #include <linux/dma-mapping.h>
 31 #include <linux/slab.h>
 32 #include <linux/module.h>
 33 #include <linux/moduleparam.h>
 34 #include <linux/platform_device.h>
 35 #include <linux/of.h>
 36 #include <linux/of_device.h>
 37 #include <linux/of_gpio.h>
 38 #include <linux/of_mtd.h>
 39 #include <linux/mtd/mtd.h>
 40 #include <linux/mtd/nand.h>
 41 #include <linux/mtd/partitions.h>
 42 
 43 #include <linux/delay.h>
 44 #include <linux/dmaengine.h>
 45 #include <linux/gpio.h>
 46 #include <linux/interrupt.h>
 47 #include <linux/io.h>
 48 #include <linux/platform_data/atmel.h>
 49 
 50 static int use_dma = 1;
 51 module_param(use_dma, int, 0);
 52 
 53 static int on_flash_bbt = 0;
 54 module_param(on_flash_bbt, int, 0);
 55 
 56 /* Register access macros */
 57 #define ecc_readl(add, reg)                             \
 58         __raw_readl(add + ATMEL_ECC_##reg)
 59 #define ecc_writel(add, reg, value)                     \
 60         __raw_writel((value), add + ATMEL_ECC_##reg)
 61 
 62 #include "atmel_nand_ecc.h"     /* Hardware ECC registers */
 63 #include "atmel_nand_nfc.h"     /* Nand Flash Controller definition */
 64 
 65 /* oob layout for large page size
 66  * bad block info is on bytes 0 and 1
 67  * the bytes have to be consecutives to avoid
 68  * several NAND_CMD_RNDOUT during read
 69  */
 70 static struct nand_ecclayout atmel_oobinfo_large = {
 71         .eccbytes = 4,
 72         .eccpos = {60, 61, 62, 63},
 73         .oobfree = {
 74                 {2, 58}
 75         },
 76 };
 77 
 78 /* oob layout for small page size
 79  * bad block info is on bytes 4 and 5
 80  * the bytes have to be consecutives to avoid
 81  * several NAND_CMD_RNDOUT during read
 82  */
 83 static struct nand_ecclayout atmel_oobinfo_small = {
 84         .eccbytes = 4,
 85         .eccpos = {0, 1, 2, 3},
 86         .oobfree = {
 87                 {6, 10}
 88         },
 89 };
 90 
 91 struct atmel_nfc {
 92         void __iomem            *base_cmd_regs;
 93         void __iomem            *hsmc_regs;
 94         void __iomem            *sram_bank0;
 95         dma_addr_t              sram_bank0_phys;
 96         bool                    use_nfc_sram;
 97         bool                    write_by_sram;
 98 
 99         bool                    is_initialized;
100         struct completion       comp_nfc;
101 
102         /* Point to the sram bank which include readed data via NFC */
103         void __iomem            *data_in_sram;
104         bool                    will_write_sram;
105 };
106 static struct atmel_nfc nand_nfc;
107 
108 struct atmel_nand_host {
109         struct nand_chip        nand_chip;
110         struct mtd_info         mtd;
111         void __iomem            *io_base;
112         dma_addr_t              io_phys;
113         struct atmel_nand_data  board;
114         struct device           *dev;
115         void __iomem            *ecc;
116 
117         struct completion       comp;
118         struct dma_chan         *dma_chan;
119 
120         struct atmel_nfc        *nfc;
121 
122         bool                    has_pmecc;
123         u8                      pmecc_corr_cap;
124         u16                     pmecc_sector_size;
125         u32                     pmecc_lookup_table_offset;
126         u32                     pmecc_lookup_table_offset_512;
127         u32                     pmecc_lookup_table_offset_1024;
128 
129         int                     pmecc_bytes_per_sector;
130         int                     pmecc_sector_number;
131         int                     pmecc_degree;   /* Degree of remainders */
132         int                     pmecc_cw_len;   /* Length of codeword */
133 
134         void __iomem            *pmerrloc_base;
135         void __iomem            *pmecc_rom_base;
136 
137         /* lookup table for alpha_to and index_of */
138         void __iomem            *pmecc_alpha_to;
139         void __iomem            *pmecc_index_of;
140 
141         /* data for pmecc computation */
142         int16_t                 *pmecc_partial_syn;
143         int16_t                 *pmecc_si;
144         int16_t                 *pmecc_smu;     /* Sigma table */
145         int16_t                 *pmecc_lmu;     /* polynomal order */
146         int                     *pmecc_mu;
147         int                     *pmecc_dmu;
148         int                     *pmecc_delta;
149 };
150 
151 static struct nand_ecclayout atmel_pmecc_oobinfo;
152 
153 /*
154  * Enable NAND.
155  */
156 static void atmel_nand_enable(struct atmel_nand_host *host)
157 {
158         if (gpio_is_valid(host->board.enable_pin))
159                 gpio_set_value(host->board.enable_pin, 0);
160 }
161 
162 /*
163  * Disable NAND.
164  */
165 static void atmel_nand_disable(struct atmel_nand_host *host)
166 {
167         if (gpio_is_valid(host->board.enable_pin))
168                 gpio_set_value(host->board.enable_pin, 1);
169 }
170 
171 /*
172  * Hardware specific access to control-lines
173  */
174 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
175 {
176         struct nand_chip *nand_chip = mtd->priv;
177         struct atmel_nand_host *host = nand_chip->priv;
178 
179         if (ctrl & NAND_CTRL_CHANGE) {
180                 if (ctrl & NAND_NCE)
181                         atmel_nand_enable(host);
182                 else
183                         atmel_nand_disable(host);
184         }
185         if (cmd == NAND_CMD_NONE)
186                 return;
187 
188         if (ctrl & NAND_CLE)
189                 writeb(cmd, host->io_base + (1 << host->board.cle));
190         else
191                 writeb(cmd, host->io_base + (1 << host->board.ale));
192 }
193 
194 /*
195  * Read the Device Ready pin.
196  */
197 static int atmel_nand_device_ready(struct mtd_info *mtd)
198 {
199         struct nand_chip *nand_chip = mtd->priv;
200         struct atmel_nand_host *host = nand_chip->priv;
201 
202         return gpio_get_value(host->board.rdy_pin) ^
203                 !!host->board.rdy_pin_active_low;
204 }
205 
206 /* Set up for hardware ready pin and enable pin. */
207 static int atmel_nand_set_enable_ready_pins(struct mtd_info *mtd)
208 {
209         struct nand_chip *chip = mtd->priv;
210         struct atmel_nand_host *host = chip->priv;
211         int res = 0;
212 
213         if (gpio_is_valid(host->board.rdy_pin)) {
214                 res = devm_gpio_request(host->dev,
215                                 host->board.rdy_pin, "nand_rdy");
216                 if (res < 0) {
217                         dev_err(host->dev,
218                                 "can't request rdy gpio %d\n",
219                                 host->board.rdy_pin);
220                         return res;
221                 }
222 
223                 res = gpio_direction_input(host->board.rdy_pin);
224                 if (res < 0) {
225                         dev_err(host->dev,
226                                 "can't request input direction rdy gpio %d\n",
227                                 host->board.rdy_pin);
228                         return res;
229                 }
230 
231                 chip->dev_ready = atmel_nand_device_ready;
232         }
233 
234         if (gpio_is_valid(host->board.enable_pin)) {
235                 res = devm_gpio_request(host->dev,
236                                 host->board.enable_pin, "nand_enable");
237                 if (res < 0) {
238                         dev_err(host->dev,
239                                 "can't request enable gpio %d\n",
240                                 host->board.enable_pin);
241                         return res;
242                 }
243 
244                 res = gpio_direction_output(host->board.enable_pin, 1);
245                 if (res < 0) {
246                         dev_err(host->dev,
247                                 "can't request output direction enable gpio %d\n",
248                                 host->board.enable_pin);
249                         return res;
250                 }
251         }
252 
253         return res;
254 }
255 
256 static void memcpy32_fromio(void *trg, const void __iomem  *src, size_t size)
257 {
258         int i;
259         u32 *t = trg;
260         const __iomem u32 *s = src;
261 
262         for (i = 0; i < (size >> 2); i++)
263                 *t++ = readl_relaxed(s++);
264 }
265 
266 static void memcpy32_toio(void __iomem *trg, const void *src, int size)
267 {
268         int i;
269         u32 __iomem *t = trg;
270         const u32 *s = src;
271 
272         for (i = 0; i < (size >> 2); i++)
273                 writel_relaxed(*s++, t++);
274 }
275 
276 /*
277  * Minimal-overhead PIO for data access.
278  */
279 static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
280 {
281         struct nand_chip        *nand_chip = mtd->priv;
282         struct atmel_nand_host *host = nand_chip->priv;
283 
284         if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
285                 memcpy32_fromio(buf, host->nfc->data_in_sram, len);
286                 host->nfc->data_in_sram += len;
287         } else {
288                 __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
289         }
290 }
291 
292 static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
293 {
294         struct nand_chip        *nand_chip = mtd->priv;
295         struct atmel_nand_host *host = nand_chip->priv;
296 
297         if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
298                 memcpy32_fromio(buf, host->nfc->data_in_sram, len);
299                 host->nfc->data_in_sram += len;
300         } else {
301                 __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
302         }
303 }
304 
305 static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
306 {
307         struct nand_chip        *nand_chip = mtd->priv;
308 
309         __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
310 }
311 
312 static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
313 {
314         struct nand_chip        *nand_chip = mtd->priv;
315 
316         __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
317 }
318 
319 static void dma_complete_func(void *completion)
320 {
321         complete(completion);
322 }
323 
324 static int nfc_set_sram_bank(struct atmel_nand_host *host, unsigned int bank)
325 {
326         /* NFC only has two banks. Must be 0 or 1 */
327         if (bank > 1)
328                 return -EINVAL;
329 
330         if (bank) {
331                 /* Only for a 2k-page or lower flash, NFC can handle 2 banks */
332                 if (host->mtd.writesize > 2048)
333                         return -EINVAL;
334                 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK1);
335         } else {
336                 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK0);
337         }
338 
339         return 0;
340 }
341 
342 static uint nfc_get_sram_off(struct atmel_nand_host *host)
343 {
344         if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
345                 return NFC_SRAM_BANK1_OFFSET;
346         else
347                 return 0;
348 }
349 
350 static dma_addr_t nfc_sram_phys(struct atmel_nand_host *host)
351 {
352         if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
353                 return host->nfc->sram_bank0_phys + NFC_SRAM_BANK1_OFFSET;
354         else
355                 return host->nfc->sram_bank0_phys;
356 }
357 
358 static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
359                                int is_read)
360 {
361         struct dma_device *dma_dev;
362         enum dma_ctrl_flags flags;
363         dma_addr_t dma_src_addr, dma_dst_addr, phys_addr;
364         struct dma_async_tx_descriptor *tx = NULL;
365         dma_cookie_t cookie;
366         struct nand_chip *chip = mtd->priv;
367         struct atmel_nand_host *host = chip->priv;
368         void *p = buf;
369         int err = -EIO;
370         enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
371         struct atmel_nfc *nfc = host->nfc;
372 
373         if (buf >= high_memory)
374                 goto err_buf;
375 
376         dma_dev = host->dma_chan->device;
377 
378         flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
379 
380         phys_addr = dma_map_single(dma_dev->dev, p, len, dir);
381         if (dma_mapping_error(dma_dev->dev, phys_addr)) {
382                 dev_err(host->dev, "Failed to dma_map_single\n");
383                 goto err_buf;
384         }
385 
386         if (is_read) {
387                 if (nfc && nfc->data_in_sram)
388                         dma_src_addr = nfc_sram_phys(host) + (nfc->data_in_sram
389                                 - (nfc->sram_bank0 + nfc_get_sram_off(host)));
390                 else
391                         dma_src_addr = host->io_phys;
392 
393                 dma_dst_addr = phys_addr;
394         } else {
395                 dma_src_addr = phys_addr;
396 
397                 if (nfc && nfc->write_by_sram)
398                         dma_dst_addr = nfc_sram_phys(host);
399                 else
400                         dma_dst_addr = host->io_phys;
401         }
402 
403         tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr,
404                                              dma_src_addr, len, flags);
405         if (!tx) {
406                 dev_err(host->dev, "Failed to prepare DMA memcpy\n");
407                 goto err_dma;
408         }
409 
410         init_completion(&host->comp);
411         tx->callback = dma_complete_func;
412         tx->callback_param = &host->comp;
413 
414         cookie = tx->tx_submit(tx);
415         if (dma_submit_error(cookie)) {
416                 dev_err(host->dev, "Failed to do DMA tx_submit\n");
417                 goto err_dma;
418         }
419 
420         dma_async_issue_pending(host->dma_chan);
421         wait_for_completion(&host->comp);
422 
423         if (is_read && nfc && nfc->data_in_sram)
424                 /* After read data from SRAM, need to increase the position */
425                 nfc->data_in_sram += len;
426 
427         err = 0;
428 
429 err_dma:
430         dma_unmap_single(dma_dev->dev, phys_addr, len, dir);
431 err_buf:
432         if (err != 0)
433                 dev_dbg(host->dev, "Fall back to CPU I/O\n");
434         return err;
435 }
436 
437 static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
438 {
439         struct nand_chip *chip = mtd->priv;
440         struct atmel_nand_host *host = chip->priv;
441 
442         if (use_dma && len > mtd->oobsize)
443                 /* only use DMA for bigger than oob size: better performances */
444                 if (atmel_nand_dma_op(mtd, buf, len, 1) == 0)
445                         return;
446 
447         if (host->board.bus_width_16)
448                 atmel_read_buf16(mtd, buf, len);
449         else
450                 atmel_read_buf8(mtd, buf, len);
451 }
452 
453 static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
454 {
455         struct nand_chip *chip = mtd->priv;
456         struct atmel_nand_host *host = chip->priv;
457 
458         if (use_dma && len > mtd->oobsize)
459                 /* only use DMA for bigger than oob size: better performances */
460                 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0)
461                         return;
462 
463         if (host->board.bus_width_16)
464                 atmel_write_buf16(mtd, buf, len);
465         else
466                 atmel_write_buf8(mtd, buf, len);
467 }
468 
469 /*
470  * Return number of ecc bytes per sector according to sector size and
471  * correction capability
472  *
473  * Following table shows what at91 PMECC supported:
474  * Correction Capability        Sector_512_bytes        Sector_1024_bytes
475  * =====================        ================        =================
476  *                2-bits                 4-bytes                  4-bytes
477  *                4-bits                 7-bytes                  7-bytes
478  *                8-bits                13-bytes                 14-bytes
479  *               12-bits                20-bytes                 21-bytes
480  *               24-bits                39-bytes                 42-bytes
481  */
482 static int pmecc_get_ecc_bytes(int cap, int sector_size)
483 {
484         int m = 12 + sector_size / 512;
485         return (m * cap + 7) / 8;
486 }
487 
488 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
489                                     int oobsize, int ecc_len)
490 {
491         int i;
492 
493         layout->eccbytes = ecc_len;
494 
495         /* ECC will occupy the last ecc_len bytes continuously */
496         for (i = 0; i < ecc_len; i++)
497                 layout->eccpos[i] = oobsize - ecc_len + i;
498 
499         layout->oobfree[0].offset = 2;
500         layout->oobfree[0].length =
501                 oobsize - ecc_len - layout->oobfree[0].offset;
502 }
503 
504 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
505 {
506         int table_size;
507 
508         table_size = host->pmecc_sector_size == 512 ?
509                 PMECC_LOOKUP_TABLE_SIZE_512 : PMECC_LOOKUP_TABLE_SIZE_1024;
510 
511         return host->pmecc_rom_base + host->pmecc_lookup_table_offset +
512                         table_size * sizeof(int16_t);
513 }
514 
515 static int pmecc_data_alloc(struct atmel_nand_host *host)
516 {
517         const int cap = host->pmecc_corr_cap;
518         int size;
519 
520         size = (2 * cap + 1) * sizeof(int16_t);
521         host->pmecc_partial_syn = devm_kzalloc(host->dev, size, GFP_KERNEL);
522         host->pmecc_si = devm_kzalloc(host->dev, size, GFP_KERNEL);
523         host->pmecc_lmu = devm_kzalloc(host->dev,
524                         (cap + 1) * sizeof(int16_t), GFP_KERNEL);
525         host->pmecc_smu = devm_kzalloc(host->dev,
526                         (cap + 2) * size, GFP_KERNEL);
527 
528         size = (cap + 1) * sizeof(int);
529         host->pmecc_mu = devm_kzalloc(host->dev, size, GFP_KERNEL);
530         host->pmecc_dmu = devm_kzalloc(host->dev, size, GFP_KERNEL);
531         host->pmecc_delta = devm_kzalloc(host->dev, size, GFP_KERNEL);
532 
533         if (!host->pmecc_partial_syn ||
534                 !host->pmecc_si ||
535                 !host->pmecc_lmu ||
536                 !host->pmecc_smu ||
537                 !host->pmecc_mu ||
538                 !host->pmecc_dmu ||
539                 !host->pmecc_delta)
540                 return -ENOMEM;
541 
542         return 0;
543 }
544 
545 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
546 {
547         struct nand_chip *nand_chip = mtd->priv;
548         struct atmel_nand_host *host = nand_chip->priv;
549         int i;
550         uint32_t value;
551 
552         /* Fill odd syndromes */
553         for (i = 0; i < host->pmecc_corr_cap; i++) {
554                 value = pmecc_readl_rem_relaxed(host->ecc, sector, i / 2);
555                 if (i & 1)
556                         value >>= 16;
557                 value &= 0xffff;
558                 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
559         }
560 }
561 
562 static void pmecc_substitute(struct mtd_info *mtd)
563 {
564         struct nand_chip *nand_chip = mtd->priv;
565         struct atmel_nand_host *host = nand_chip->priv;
566         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
567         int16_t __iomem *index_of = host->pmecc_index_of;
568         int16_t *partial_syn = host->pmecc_partial_syn;
569         const int cap = host->pmecc_corr_cap;
570         int16_t *si;
571         int i, j;
572 
573         /* si[] is a table that holds the current syndrome value,
574          * an element of that table belongs to the field
575          */
576         si = host->pmecc_si;
577 
578         memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
579 
580         /* Computation 2t syndromes based on S(x) */
581         /* Odd syndromes */
582         for (i = 1; i < 2 * cap; i += 2) {
583                 for (j = 0; j < host->pmecc_degree; j++) {
584                         if (partial_syn[i] & ((unsigned short)0x1 << j))
585                                 si[i] = readw_relaxed(alpha_to + i * j) ^ si[i];
586                 }
587         }
588         /* Even syndrome = (Odd syndrome) ** 2 */
589         for (i = 2, j = 1; j <= cap; i = ++j << 1) {
590                 if (si[j] == 0) {
591                         si[i] = 0;
592                 } else {
593                         int16_t tmp;
594 
595                         tmp = readw_relaxed(index_of + si[j]);
596                         tmp = (tmp * 2) % host->pmecc_cw_len;
597                         si[i] = readw_relaxed(alpha_to + tmp);
598                 }
599         }
600 
601         return;
602 }
603 
604 static void pmecc_get_sigma(struct mtd_info *mtd)
605 {
606         struct nand_chip *nand_chip = mtd->priv;
607         struct atmel_nand_host *host = nand_chip->priv;
608 
609         int16_t *lmu = host->pmecc_lmu;
610         int16_t *si = host->pmecc_si;
611         int *mu = host->pmecc_mu;
612         int *dmu = host->pmecc_dmu;     /* Discrepancy */
613         int *delta = host->pmecc_delta; /* Delta order */
614         int cw_len = host->pmecc_cw_len;
615         const int16_t cap = host->pmecc_corr_cap;
616         const int num = 2 * cap + 1;
617         int16_t __iomem *index_of = host->pmecc_index_of;
618         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
619         int i, j, k;
620         uint32_t dmu_0_count, tmp;
621         int16_t *smu = host->pmecc_smu;
622 
623         /* index of largest delta */
624         int ro;
625         int largest;
626         int diff;
627 
628         dmu_0_count = 0;
629 
630         /* First Row */
631 
632         /* Mu */
633         mu[0] = -1;
634 
635         memset(smu, 0, sizeof(int16_t) * num);
636         smu[0] = 1;
637 
638         /* discrepancy set to 1 */
639         dmu[0] = 1;
640         /* polynom order set to 0 */
641         lmu[0] = 0;
642         delta[0] = (mu[0] * 2 - lmu[0]) >> 1;
643 
644         /* Second Row */
645 
646         /* Mu */
647         mu[1] = 0;
648         /* Sigma(x) set to 1 */
649         memset(&smu[num], 0, sizeof(int16_t) * num);
650         smu[num] = 1;
651 
652         /* discrepancy set to S1 */
653         dmu[1] = si[1];
654 
655         /* polynom order set to 0 */
656         lmu[1] = 0;
657 
658         delta[1] = (mu[1] * 2 - lmu[1]) >> 1;
659 
660         /* Init the Sigma(x) last row */
661         memset(&smu[(cap + 1) * num], 0, sizeof(int16_t) * num);
662 
663         for (i = 1; i <= cap; i++) {
664                 mu[i + 1] = i << 1;
665                 /* Begin Computing Sigma (Mu+1) and L(mu) */
666                 /* check if discrepancy is set to 0 */
667                 if (dmu[i] == 0) {
668                         dmu_0_count++;
669 
670                         tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
671                         if ((cap - (lmu[i] >> 1) - 1) & 0x1)
672                                 tmp += 2;
673                         else
674                                 tmp += 1;
675 
676                         if (dmu_0_count == tmp) {
677                                 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
678                                         smu[(cap + 1) * num + j] =
679                                                         smu[i * num + j];
680 
681                                 lmu[cap + 1] = lmu[i];
682                                 return;
683                         }
684 
685                         /* copy polynom */
686                         for (j = 0; j <= lmu[i] >> 1; j++)
687                                 smu[(i + 1) * num + j] = smu[i * num + j];
688 
689                         /* copy previous polynom order to the next */
690                         lmu[i + 1] = lmu[i];
691                 } else {
692                         ro = 0;
693                         largest = -1;
694                         /* find largest delta with dmu != 0 */
695                         for (j = 0; j < i; j++) {
696                                 if ((dmu[j]) && (delta[j] > largest)) {
697                                         largest = delta[j];
698                                         ro = j;
699                                 }
700                         }
701 
702                         /* compute difference */
703                         diff = (mu[i] - mu[ro]);
704 
705                         /* Compute degree of the new smu polynomial */
706                         if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
707                                 lmu[i + 1] = lmu[i];
708                         else
709                                 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
710 
711                         /* Init smu[i+1] with 0 */
712                         for (k = 0; k < num; k++)
713                                 smu[(i + 1) * num + k] = 0;
714 
715                         /* Compute smu[i+1] */
716                         for (k = 0; k <= lmu[ro] >> 1; k++) {
717                                 int16_t a, b, c;
718 
719                                 if (!(smu[ro * num + k] && dmu[i]))
720                                         continue;
721                                 a = readw_relaxed(index_of + dmu[i]);
722                                 b = readw_relaxed(index_of + dmu[ro]);
723                                 c = readw_relaxed(index_of + smu[ro * num + k]);
724                                 tmp = a + (cw_len - b) + c;
725                                 a = readw_relaxed(alpha_to + tmp % cw_len);
726                                 smu[(i + 1) * num + (k + diff)] = a;
727                         }
728 
729                         for (k = 0; k <= lmu[i] >> 1; k++)
730                                 smu[(i + 1) * num + k] ^= smu[i * num + k];
731                 }
732 
733                 /* End Computing Sigma (Mu+1) and L(mu) */
734                 /* In either case compute delta */
735                 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
736 
737                 /* Do not compute discrepancy for the last iteration */
738                 if (i >= cap)
739                         continue;
740 
741                 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
742                         tmp = 2 * (i - 1);
743                         if (k == 0) {
744                                 dmu[i + 1] = si[tmp + 3];
745                         } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
746                                 int16_t a, b, c;
747                                 a = readw_relaxed(index_of +
748                                                 smu[(i + 1) * num + k]);
749                                 b = si[2 * (i - 1) + 3 - k];
750                                 c = readw_relaxed(index_of + b);
751                                 tmp = a + c;
752                                 tmp %= cw_len;
753                                 dmu[i + 1] = readw_relaxed(alpha_to + tmp) ^
754                                         dmu[i + 1];
755                         }
756                 }
757         }
758 
759         return;
760 }
761 
762 static int pmecc_err_location(struct mtd_info *mtd)
763 {
764         struct nand_chip *nand_chip = mtd->priv;
765         struct atmel_nand_host *host = nand_chip->priv;
766         unsigned long end_time;
767         const int cap = host->pmecc_corr_cap;
768         const int num = 2 * cap + 1;
769         int sector_size = host->pmecc_sector_size;
770         int err_nbr = 0;        /* number of error */
771         int roots_nbr;          /* number of roots */
772         int i;
773         uint32_t val;
774         int16_t *smu = host->pmecc_smu;
775 
776         pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE);
777 
778         for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
779                 pmerrloc_writel_sigma_relaxed(host->pmerrloc_base, i,
780                                       smu[(cap + 1) * num + i]);
781                 err_nbr++;
782         }
783 
784         val = (err_nbr - 1) << 16;
785         if (sector_size == 1024)
786                 val |= 1;
787 
788         pmerrloc_writel(host->pmerrloc_base, ELCFG, val);
789         pmerrloc_writel(host->pmerrloc_base, ELEN,
790                         sector_size * 8 + host->pmecc_degree * cap);
791 
792         end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
793         while (!(pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
794                  & PMERRLOC_CALC_DONE)) {
795                 if (unlikely(time_after(jiffies, end_time))) {
796                         dev_err(host->dev, "PMECC: Timeout to calculate error location.\n");
797                         return -1;
798                 }
799                 cpu_relax();
800         }
801 
802         roots_nbr = (pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
803                 & PMERRLOC_ERR_NUM_MASK) >> 8;
804         /* Number of roots == degree of smu hence <= cap */
805         if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
806                 return err_nbr - 1;
807 
808         /* Number of roots does not match the degree of smu
809          * unable to correct error */
810         return -1;
811 }
812 
813 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
814                 int sector_num, int extra_bytes, int err_nbr)
815 {
816         struct nand_chip *nand_chip = mtd->priv;
817         struct atmel_nand_host *host = nand_chip->priv;
818         int i = 0;
819         int byte_pos, bit_pos, sector_size, pos;
820         uint32_t tmp;
821         uint8_t err_byte;
822 
823         sector_size = host->pmecc_sector_size;
824 
825         while (err_nbr) {
826                 tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1;
827                 byte_pos = tmp / 8;
828                 bit_pos  = tmp % 8;
829 
830                 if (byte_pos >= (sector_size + extra_bytes))
831                         BUG();  /* should never happen */
832 
833                 if (byte_pos < sector_size) {
834                         err_byte = *(buf + byte_pos);
835                         *(buf + byte_pos) ^= (1 << bit_pos);
836 
837                         pos = sector_num * host->pmecc_sector_size + byte_pos;
838                         dev_info(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
839                                 pos, bit_pos, err_byte, *(buf + byte_pos));
840                 } else {
841                         /* Bit flip in OOB area */
842                         tmp = sector_num * host->pmecc_bytes_per_sector
843                                         + (byte_pos - sector_size);
844                         err_byte = ecc[tmp];
845                         ecc[tmp] ^= (1 << bit_pos);
846 
847                         pos = tmp + nand_chip->ecc.layout->eccpos[0];
848                         dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
849                                 pos, bit_pos, err_byte, ecc[tmp]);
850                 }
851 
852                 i++;
853                 err_nbr--;
854         }
855 
856         return;
857 }
858 
859 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
860         u8 *ecc)
861 {
862         struct nand_chip *nand_chip = mtd->priv;
863         struct atmel_nand_host *host = nand_chip->priv;
864         int i, err_nbr, eccbytes;
865         uint8_t *buf_pos;
866         int total_err = 0;
867 
868         eccbytes = nand_chip->ecc.bytes;
869         for (i = 0; i < eccbytes; i++)
870                 if (ecc[i] != 0xff)
871                         goto normal_check;
872         /* Erased page, return OK */
873         return 0;
874 
875 normal_check:
876         for (i = 0; i < host->pmecc_sector_number; i++) {
877                 err_nbr = 0;
878                 if (pmecc_stat & 0x1) {
879                         buf_pos = buf + i * host->pmecc_sector_size;
880 
881                         pmecc_gen_syndrome(mtd, i);
882                         pmecc_substitute(mtd);
883                         pmecc_get_sigma(mtd);
884 
885                         err_nbr = pmecc_err_location(mtd);
886                         if (err_nbr == -1) {
887                                 dev_err(host->dev, "PMECC: Too many errors\n");
888                                 mtd->ecc_stats.failed++;
889                                 return -EIO;
890                         } else {
891                                 pmecc_correct_data(mtd, buf_pos, ecc, i,
892                                         host->pmecc_bytes_per_sector, err_nbr);
893                                 mtd->ecc_stats.corrected += err_nbr;
894                                 total_err += err_nbr;
895                         }
896                 }
897                 pmecc_stat >>= 1;
898         }
899 
900         return total_err;
901 }
902 
903 static void pmecc_enable(struct atmel_nand_host *host, int ecc_op)
904 {
905         u32 val;
906 
907         if (ecc_op != NAND_ECC_READ && ecc_op != NAND_ECC_WRITE) {
908                 dev_err(host->dev, "atmel_nand: wrong pmecc operation type!");
909                 return;
910         }
911 
912         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
913         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
914         val = pmecc_readl_relaxed(host->ecc, CFG);
915 
916         if (ecc_op == NAND_ECC_READ)
917                 pmecc_writel(host->ecc, CFG, (val & ~PMECC_CFG_WRITE_OP)
918                         | PMECC_CFG_AUTO_ENABLE);
919         else
920                 pmecc_writel(host->ecc, CFG, (val | PMECC_CFG_WRITE_OP)
921                         & ~PMECC_CFG_AUTO_ENABLE);
922 
923         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
924         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
925 }
926 
927 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
928         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
929 {
930         struct atmel_nand_host *host = chip->priv;
931         int eccsize = chip->ecc.size;
932         uint8_t *oob = chip->oob_poi;
933         uint32_t *eccpos = chip->ecc.layout->eccpos;
934         uint32_t stat;
935         unsigned long end_time;
936         int bitflips = 0;
937 
938         if (!host->nfc || !host->nfc->use_nfc_sram)
939                 pmecc_enable(host, NAND_ECC_READ);
940 
941         chip->read_buf(mtd, buf, eccsize);
942         chip->read_buf(mtd, oob, mtd->oobsize);
943 
944         end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
945         while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
946                 if (unlikely(time_after(jiffies, end_time))) {
947                         dev_err(host->dev, "PMECC: Timeout to get error status.\n");
948                         return -EIO;
949                 }
950                 cpu_relax();
951         }
952 
953         stat = pmecc_readl_relaxed(host->ecc, ISR);
954         if (stat != 0) {
955                 bitflips = pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]);
956                 if (bitflips < 0)
957                         /* uncorrectable errors */
958                         return 0;
959         }
960 
961         return bitflips;
962 }
963 
964 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
965                 struct nand_chip *chip, const uint8_t *buf, int oob_required)
966 {
967         struct atmel_nand_host *host = chip->priv;
968         uint32_t *eccpos = chip->ecc.layout->eccpos;
969         int i, j;
970         unsigned long end_time;
971 
972         if (!host->nfc || !host->nfc->write_by_sram) {
973                 pmecc_enable(host, NAND_ECC_WRITE);
974                 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
975         }
976 
977         end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
978         while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
979                 if (unlikely(time_after(jiffies, end_time))) {
980                         dev_err(host->dev, "PMECC: Timeout to get ECC value.\n");
981                         return -EIO;
982                 }
983                 cpu_relax();
984         }
985 
986         for (i = 0; i < host->pmecc_sector_number; i++) {
987                 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
988                         int pos;
989 
990                         pos = i * host->pmecc_bytes_per_sector + j;
991                         chip->oob_poi[eccpos[pos]] =
992                                 pmecc_readb_ecc_relaxed(host->ecc, i, j);
993                 }
994         }
995         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
996 
997         return 0;
998 }
999 
1000 static void atmel_pmecc_core_init(struct mtd_info *mtd)
1001 {
1002         struct nand_chip *nand_chip = mtd->priv;
1003         struct atmel_nand_host *host = nand_chip->priv;
1004         uint32_t val = 0;
1005         struct nand_ecclayout *ecc_layout;
1006 
1007         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
1008         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
1009 
1010         switch (host->pmecc_corr_cap) {
1011         case 2:
1012                 val = PMECC_CFG_BCH_ERR2;
1013                 break;
1014         case 4:
1015                 val = PMECC_CFG_BCH_ERR4;
1016                 break;
1017         case 8:
1018                 val = PMECC_CFG_BCH_ERR8;
1019                 break;
1020         case 12:
1021                 val = PMECC_CFG_BCH_ERR12;
1022                 break;
1023         case 24:
1024                 val = PMECC_CFG_BCH_ERR24;
1025                 break;
1026         }
1027 
1028         if (host->pmecc_sector_size == 512)
1029                 val |= PMECC_CFG_SECTOR512;
1030         else if (host->pmecc_sector_size == 1024)
1031                 val |= PMECC_CFG_SECTOR1024;
1032 
1033         switch (host->pmecc_sector_number) {
1034         case 1:
1035                 val |= PMECC_CFG_PAGE_1SECTOR;
1036                 break;
1037         case 2:
1038                 val |= PMECC_CFG_PAGE_2SECTORS;
1039                 break;
1040         case 4:
1041                 val |= PMECC_CFG_PAGE_4SECTORS;
1042                 break;
1043         case 8:
1044                 val |= PMECC_CFG_PAGE_8SECTORS;
1045                 break;
1046         }
1047 
1048         val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
1049                 | PMECC_CFG_AUTO_DISABLE);
1050         pmecc_writel(host->ecc, CFG, val);
1051 
1052         ecc_layout = nand_chip->ecc.layout;
1053         pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1);
1054         pmecc_writel(host->ecc, SADDR, ecc_layout->eccpos[0]);
1055         pmecc_writel(host->ecc, EADDR,
1056                         ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
1057         /* See datasheet about PMECC Clock Control Register */
1058         pmecc_writel(host->ecc, CLK, 2);
1059         pmecc_writel(host->ecc, IDR, 0xff);
1060         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
1061 }
1062 
1063 /*
1064  * Get minimum ecc requirements from NAND.
1065  * If pmecc-cap, pmecc-sector-size in DTS are not specified, this function
1066  * will set them according to minimum ecc requirement. Otherwise, use the
1067  * value in DTS file.
1068  * return 0 if success. otherwise return error code.
1069  */
1070 static int pmecc_choose_ecc(struct atmel_nand_host *host,
1071                 int *cap, int *sector_size)
1072 {
1073         /* Get minimum ECC requirements */
1074         if (host->nand_chip.ecc_strength_ds) {
1075                 *cap = host->nand_chip.ecc_strength_ds;
1076                 *sector_size = host->nand_chip.ecc_step_ds;
1077                 dev_info(host->dev, "minimum ECC: %d bits in %d bytes\n",
1078                                 *cap, *sector_size);
1079         } else {
1080                 *cap = 2;
1081                 *sector_size = 512;
1082                 dev_info(host->dev, "can't detect min. ECC, assume 2 bits in 512 bytes\n");
1083         }
1084 
1085         /* If device tree doesn't specify, use NAND's minimum ECC parameters */
1086         if (host->pmecc_corr_cap == 0) {
1087                 /* use the most fitable ecc bits (the near bigger one ) */
1088                 if (*cap <= 2)
1089                         host->pmecc_corr_cap = 2;
1090                 else if (*cap <= 4)
1091                         host->pmecc_corr_cap = 4;
1092                 else if (*cap <= 8)
1093                         host->pmecc_corr_cap = 8;
1094                 else if (*cap <= 12)
1095                         host->pmecc_corr_cap = 12;
1096                 else if (*cap <= 24)
1097                         host->pmecc_corr_cap = 24;
1098                 else
1099                         return -EINVAL;
1100         }
1101         if (host->pmecc_sector_size == 0) {
1102                 /* use the most fitable sector size (the near smaller one ) */
1103                 if (*sector_size >= 1024)
1104                         host->pmecc_sector_size = 1024;
1105                 else if (*sector_size >= 512)
1106                         host->pmecc_sector_size = 512;
1107                 else
1108                         return -EINVAL;
1109         }
1110         return 0;
1111 }
1112 
1113 static int atmel_pmecc_nand_init_params(struct platform_device *pdev,
1114                                          struct atmel_nand_host *host)
1115 {
1116         struct mtd_info *mtd = &host->mtd;
1117         struct nand_chip *nand_chip = &host->nand_chip;
1118         struct resource *regs, *regs_pmerr, *regs_rom;
1119         int cap, sector_size, err_no;
1120 
1121         err_no = pmecc_choose_ecc(host, &cap, &sector_size);
1122         if (err_no) {
1123                 dev_err(host->dev, "The NAND flash's ECC requirement are not support!");
1124                 return err_no;
1125         }
1126 
1127         if (cap > host->pmecc_corr_cap ||
1128                         sector_size != host->pmecc_sector_size)
1129                 dev_info(host->dev, "WARNING: Be Caution! Using different PMECC parameters from Nand ONFI ECC reqirement.\n");
1130 
1131         cap = host->pmecc_corr_cap;
1132         sector_size = host->pmecc_sector_size;
1133         host->pmecc_lookup_table_offset = (sector_size == 512) ?
1134                         host->pmecc_lookup_table_offset_512 :
1135                         host->pmecc_lookup_table_offset_1024;
1136 
1137         dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n",
1138                  cap, sector_size);
1139 
1140         regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1141         if (!regs) {
1142                 dev_warn(host->dev,
1143                         "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
1144                 nand_chip->ecc.mode = NAND_ECC_SOFT;
1145                 return 0;
1146         }
1147 
1148         host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1149         if (IS_ERR(host->ecc)) {
1150                 dev_err(host->dev, "ioremap failed\n");
1151                 err_no = PTR_ERR(host->ecc);
1152                 goto err;
1153         }
1154 
1155         regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1156         host->pmerrloc_base = devm_ioremap_resource(&pdev->dev, regs_pmerr);
1157         if (IS_ERR(host->pmerrloc_base)) {
1158                 dev_err(host->dev,
1159                         "Can not get I/O resource for PMECC ERRLOC controller!\n");
1160                 err_no = PTR_ERR(host->pmerrloc_base);
1161                 goto err;
1162         }
1163 
1164         regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1165         host->pmecc_rom_base = devm_ioremap_resource(&pdev->dev, regs_rom);
1166         if (IS_ERR(host->pmecc_rom_base)) {
1167                 dev_err(host->dev, "Can not get I/O resource for ROM!\n");
1168                 err_no = PTR_ERR(host->pmecc_rom_base);
1169                 goto err;
1170         }
1171 
1172         /* ECC is calculated for the whole page (1 step) */
1173         nand_chip->ecc.size = mtd->writesize;
1174 
1175         /* set ECC page size and oob layout */
1176         switch (mtd->writesize) {
1177         case 2048:
1178                 host->pmecc_degree = (sector_size == 512) ?
1179                         PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
1180                 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
1181                 host->pmecc_sector_number = mtd->writesize / sector_size;
1182                 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
1183                         cap, sector_size);
1184                 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
1185                 host->pmecc_index_of = host->pmecc_rom_base +
1186                         host->pmecc_lookup_table_offset;
1187 
1188                 nand_chip->ecc.steps = 1;
1189                 nand_chip->ecc.strength = cap;
1190                 nand_chip->ecc.bytes = host->pmecc_bytes_per_sector *
1191                                        host->pmecc_sector_number;
1192                 if (nand_chip->ecc.bytes > mtd->oobsize - 2) {
1193                         dev_err(host->dev, "No room for ECC bytes\n");
1194                         err_no = -EINVAL;
1195                         goto err;
1196                 }
1197                 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
1198                                         mtd->oobsize,
1199                                         nand_chip->ecc.bytes);
1200                 nand_chip->ecc.layout = &atmel_pmecc_oobinfo;
1201                 break;
1202         case 512:
1203         case 1024:
1204         case 4096:
1205                 /* TODO */
1206                 dev_warn(host->dev,
1207                         "Unsupported page size for PMECC, use Software ECC\n");
1208         default:
1209                 /* page size not handled by HW ECC */
1210                 /* switching back to soft ECC */
1211                 nand_chip->ecc.mode = NAND_ECC_SOFT;
1212                 return 0;
1213         }
1214 
1215         /* Allocate data for PMECC computation */
1216         err_no = pmecc_data_alloc(host);
1217         if (err_no) {
1218                 dev_err(host->dev,
1219                                 "Cannot allocate memory for PMECC computation!\n");
1220                 goto err;
1221         }
1222 
1223         nand_chip->options |= NAND_NO_SUBPAGE_WRITE;
1224         nand_chip->ecc.read_page = atmel_nand_pmecc_read_page;
1225         nand_chip->ecc.write_page = atmel_nand_pmecc_write_page;
1226 
1227         atmel_pmecc_core_init(mtd);
1228 
1229         return 0;
1230 
1231 err:
1232         return err_no;
1233 }
1234 
1235 /*
1236  * Calculate HW ECC
1237  *
1238  * function called after a write
1239  *
1240  * mtd:        MTD block structure
1241  * dat:        raw data (unused)
1242  * ecc_code:   buffer for ECC
1243  */
1244 static int atmel_nand_calculate(struct mtd_info *mtd,
1245                 const u_char *dat, unsigned char *ecc_code)
1246 {
1247         struct nand_chip *nand_chip = mtd->priv;
1248         struct atmel_nand_host *host = nand_chip->priv;
1249         unsigned int ecc_value;
1250 
1251         /* get the first 2 ECC bytes */
1252         ecc_value = ecc_readl(host->ecc, PR);
1253 
1254         ecc_code[0] = ecc_value & 0xFF;
1255         ecc_code[1] = (ecc_value >> 8) & 0xFF;
1256 
1257         /* get the last 2 ECC bytes */
1258         ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
1259 
1260         ecc_code[2] = ecc_value & 0xFF;
1261         ecc_code[3] = (ecc_value >> 8) & 0xFF;
1262 
1263         return 0;
1264 }
1265 
1266 /*
1267  * HW ECC read page function
1268  *
1269  * mtd:        mtd info structure
1270  * chip:       nand chip info structure
1271  * buf:        buffer to store read data
1272  * oob_required:    caller expects OOB data read to chip->oob_poi
1273  */
1274 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1275                                 uint8_t *buf, int oob_required, int page)
1276 {
1277         int eccsize = chip->ecc.size;
1278         int eccbytes = chip->ecc.bytes;
1279         uint32_t *eccpos = chip->ecc.layout->eccpos;
1280         uint8_t *p = buf;
1281         uint8_t *oob = chip->oob_poi;
1282         uint8_t *ecc_pos;
1283         int stat;
1284         unsigned int max_bitflips = 0;
1285 
1286         /*
1287          * Errata: ALE is incorrectly wired up to the ECC controller
1288          * on the AP7000, so it will include the address cycles in the
1289          * ECC calculation.
1290          *
1291          * Workaround: Reset the parity registers before reading the
1292          * actual data.
1293          */
1294         struct atmel_nand_host *host = chip->priv;
1295         if (host->board.need_reset_workaround)
1296                 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1297 
1298         /* read the page */
1299         chip->read_buf(mtd, p, eccsize);
1300 
1301         /* move to ECC position if needed */
1302         if (eccpos[0] != 0) {
1303                 /* This only works on large pages
1304                  * because the ECC controller waits for
1305                  * NAND_CMD_RNDOUTSTART after the
1306                  * NAND_CMD_RNDOUT.
1307                  * anyway, for small pages, the eccpos[0] == 0
1308                  */
1309                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1310                                 mtd->writesize + eccpos[0], -1);
1311         }
1312 
1313         /* the ECC controller needs to read the ECC just after the data */
1314         ecc_pos = oob + eccpos[0];
1315         chip->read_buf(mtd, ecc_pos, eccbytes);
1316 
1317         /* check if there's an error */
1318         stat = chip->ecc.correct(mtd, p, oob, NULL);
1319 
1320         if (stat < 0) {
1321                 mtd->ecc_stats.failed++;
1322         } else {
1323                 mtd->ecc_stats.corrected += stat;
1324                 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1325         }
1326 
1327         /* get back to oob start (end of page) */
1328         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1329 
1330         /* read the oob */
1331         chip->read_buf(mtd, oob, mtd->oobsize);
1332 
1333         return max_bitflips;
1334 }
1335 
1336 /*
1337  * HW ECC Correction
1338  *
1339  * function called after a read
1340  *
1341  * mtd:        MTD block structure
1342  * dat:        raw data read from the chip
1343  * read_ecc:   ECC from the chip (unused)
1344  * isnull:     unused
1345  *
1346  * Detect and correct a 1 bit error for a page
1347  */
1348 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1349                 u_char *read_ecc, u_char *isnull)
1350 {
1351         struct nand_chip *nand_chip = mtd->priv;
1352         struct atmel_nand_host *host = nand_chip->priv;
1353         unsigned int ecc_status;
1354         unsigned int ecc_word, ecc_bit;
1355 
1356         /* get the status from the Status Register */
1357         ecc_status = ecc_readl(host->ecc, SR);
1358 
1359         /* if there's no error */
1360         if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1361                 return 0;
1362 
1363         /* get error bit offset (4 bits) */
1364         ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
1365         /* get word address (12 bits) */
1366         ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
1367         ecc_word >>= 4;
1368 
1369         /* if there are multiple errors */
1370         if (ecc_status & ATMEL_ECC_MULERR) {
1371                 /* check if it is a freshly erased block
1372                  * (filled with 0xff) */
1373                 if ((ecc_bit == ATMEL_ECC_BITADDR)
1374                                 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1375                         /* the block has just been erased, return OK */
1376                         return 0;
1377                 }
1378                 /* it doesn't seems to be a freshly
1379                  * erased block.
1380                  * We can't correct so many errors */
1381                 dev_dbg(host->dev, "atmel_nand : multiple errors detected."
1382                                 " Unable to correct.\n");
1383                 return -EIO;
1384         }
1385 
1386         /* if there's a single bit error : we can correct it */
1387         if (ecc_status & ATMEL_ECC_ECCERR) {
1388                 /* there's nothing much to do here.
1389                  * the bit error is on the ECC itself.
1390                  */
1391                 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
1392                                 " Nothing to correct\n");
1393                 return 0;
1394         }
1395 
1396         dev_dbg(host->dev, "atmel_nand : one bit error on data."
1397                         " (word offset in the page :"
1398                         " 0x%x bit offset : 0x%x)\n",
1399                         ecc_word, ecc_bit);
1400         /* correct the error */
1401         if (nand_chip->options & NAND_BUSWIDTH_16) {
1402                 /* 16 bits words */
1403                 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1404         } else {
1405                 /* 8 bits words */
1406                 dat[ecc_word] ^= (1 << ecc_bit);
1407         }
1408         dev_dbg(host->dev, "atmel_nand : error corrected\n");
1409         return 1;
1410 }
1411 
1412 /*
1413  * Enable HW ECC : unused on most chips
1414  */
1415 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1416 {
1417         struct nand_chip *nand_chip = mtd->priv;
1418         struct atmel_nand_host *host = nand_chip->priv;
1419 
1420         if (host->board.need_reset_workaround)
1421                 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1422 }
1423 
1424 static int atmel_of_init_port(struct atmel_nand_host *host,
1425                               struct device_node *np)
1426 {
1427         u32 val;
1428         u32 offset[2];
1429         int ecc_mode;
1430         struct atmel_nand_data *board = &host->board;
1431         enum of_gpio_flags flags = 0;
1432 
1433         if (of_property_read_u32(np, "atmel,nand-addr-offset", &val) == 0) {
1434                 if (val >= 32) {
1435                         dev_err(host->dev, "invalid addr-offset %u\n", val);
1436                         return -EINVAL;
1437                 }
1438                 board->ale = val;
1439         }
1440 
1441         if (of_property_read_u32(np, "atmel,nand-cmd-offset", &val) == 0) {
1442                 if (val >= 32) {
1443                         dev_err(host->dev, "invalid cmd-offset %u\n", val);
1444                         return -EINVAL;
1445                 }
1446                 board->cle = val;
1447         }
1448 
1449         ecc_mode = of_get_nand_ecc_mode(np);
1450 
1451         board->ecc_mode = ecc_mode < 0 ? NAND_ECC_SOFT : ecc_mode;
1452 
1453         board->on_flash_bbt = of_get_nand_on_flash_bbt(np);
1454 
1455         board->has_dma = of_property_read_bool(np, "atmel,nand-has-dma");
1456 
1457         if (of_get_nand_bus_width(np) == 16)
1458                 board->bus_width_16 = 1;
1459 
1460         board->rdy_pin = of_get_gpio_flags(np, 0, &flags);
1461         board->rdy_pin_active_low = (flags == OF_GPIO_ACTIVE_LOW);
1462 
1463         board->enable_pin = of_get_gpio(np, 1);
1464         board->det_pin = of_get_gpio(np, 2);
1465 
1466         host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
1467 
1468         /* load the nfc driver if there is */
1469         of_platform_populate(np, NULL, NULL, host->dev);
1470 
1471         if (!(board->ecc_mode == NAND_ECC_HW) || !host->has_pmecc)
1472                 return 0;       /* Not using PMECC */
1473 
1474         /* use PMECC, get correction capability, sector size and lookup
1475          * table offset.
1476          * If correction bits and sector size are not specified, then find
1477          * them from NAND ONFI parameters.
1478          */
1479         if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
1480                 if ((val != 2) && (val != 4) && (val != 8) && (val != 12) &&
1481                                 (val != 24)) {
1482                         dev_err(host->dev,
1483                                 "Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n",
1484                                 val);
1485                         return -EINVAL;
1486                 }
1487                 host->pmecc_corr_cap = (u8)val;
1488         }
1489 
1490         if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) {
1491                 if ((val != 512) && (val != 1024)) {
1492                         dev_err(host->dev,
1493                                 "Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n",
1494                                 val);
1495                         return -EINVAL;
1496                 }
1497                 host->pmecc_sector_size = (u16)val;
1498         }
1499 
1500         if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset",
1501                         offset, 2) != 0) {
1502                 dev_err(host->dev, "Cannot get PMECC lookup table offset\n");
1503                 return -EINVAL;
1504         }
1505         if (!offset[0] && !offset[1]) {
1506                 dev_err(host->dev, "Invalid PMECC lookup table offset\n");
1507                 return -EINVAL;
1508         }
1509         host->pmecc_lookup_table_offset_512 = offset[0];
1510         host->pmecc_lookup_table_offset_1024 = offset[1];
1511 
1512         return 0;
1513 }
1514 
1515 static int atmel_hw_nand_init_params(struct platform_device *pdev,
1516                                          struct atmel_nand_host *host)
1517 {
1518         struct mtd_info *mtd = &host->mtd;
1519         struct nand_chip *nand_chip = &host->nand_chip;
1520         struct resource         *regs;
1521 
1522         regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1523         if (!regs) {
1524                 dev_err(host->dev,
1525                         "Can't get I/O resource regs, use software ECC\n");
1526                 nand_chip->ecc.mode = NAND_ECC_SOFT;
1527                 return 0;
1528         }
1529 
1530         host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1531         if (IS_ERR(host->ecc)) {
1532                 dev_err(host->dev, "ioremap failed\n");
1533                 return PTR_ERR(host->ecc);
1534         }
1535 
1536         /* ECC is calculated for the whole page (1 step) */
1537         nand_chip->ecc.size = mtd->writesize;
1538 
1539         /* set ECC page size and oob layout */
1540         switch (mtd->writesize) {
1541         case 512:
1542                 nand_chip->ecc.layout = &atmel_oobinfo_small;
1543                 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
1544                 break;
1545         case 1024:
1546                 nand_chip->ecc.layout = &atmel_oobinfo_large;
1547                 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
1548                 break;
1549         case 2048:
1550                 nand_chip->ecc.layout = &atmel_oobinfo_large;
1551                 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
1552                 break;
1553         case 4096:
1554                 nand_chip->ecc.layout = &atmel_oobinfo_large;
1555                 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
1556                 break;
1557         default:
1558                 /* page size not handled by HW ECC */
1559                 /* switching back to soft ECC */
1560                 nand_chip->ecc.mode = NAND_ECC_SOFT;
1561                 return 0;
1562         }
1563 
1564         /* set up for HW ECC */
1565         nand_chip->ecc.calculate = atmel_nand_calculate;
1566         nand_chip->ecc.correct = atmel_nand_correct;
1567         nand_chip->ecc.hwctl = atmel_nand_hwctl;
1568         nand_chip->ecc.read_page = atmel_nand_read_page;
1569         nand_chip->ecc.bytes = 4;
1570         nand_chip->ecc.strength = 1;
1571 
1572         return 0;
1573 }
1574 
1575 /* SMC interrupt service routine */
1576 static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
1577 {
1578         struct atmel_nand_host *host = dev_id;
1579         u32 status, mask, pending;
1580         irqreturn_t ret = IRQ_HANDLED;
1581 
1582         status = nfc_readl(host->nfc->hsmc_regs, SR);
1583         mask = nfc_readl(host->nfc->hsmc_regs, IMR);
1584         pending = status & mask;
1585 
1586         if (pending & NFC_SR_XFR_DONE) {
1587                 complete(&host->nfc->comp_nfc);
1588                 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_XFR_DONE);
1589         } else if (pending & NFC_SR_RB_EDGE) {
1590                 complete(&host->nfc->comp_nfc);
1591                 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_RB_EDGE);
1592         } else if (pending & NFC_SR_CMD_DONE) {
1593                 complete(&host->nfc->comp_nfc);
1594                 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_CMD_DONE);
1595         } else {
1596                 ret = IRQ_NONE;
1597         }
1598 
1599         return ret;
1600 }
1601 
1602 /* NFC(Nand Flash Controller) related functions */
1603 static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag)
1604 {
1605         unsigned long timeout;
1606         init_completion(&host->nfc->comp_nfc);
1607 
1608         /* Enable interrupt that need to wait for */
1609         nfc_writel(host->nfc->hsmc_regs, IER, flag);
1610 
1611         timeout = wait_for_completion_timeout(&host->nfc->comp_nfc,
1612                         msecs_to_jiffies(NFC_TIME_OUT_MS));
1613         if (timeout)
1614                 return 0;
1615 
1616         /* Time out to wait for the interrupt */
1617         dev_err(host->dev, "Time out to wait for interrupt: 0x%08x\n", flag);
1618         return -ETIMEDOUT;
1619 }
1620 
1621 static int nfc_send_command(struct atmel_nand_host *host,
1622         unsigned int cmd, unsigned int addr, unsigned char cycle0)
1623 {
1624         unsigned long timeout;
1625         dev_dbg(host->dev,
1626                 "nfc_cmd: 0x%08x, addr1234: 0x%08x, cycle0: 0x%02x\n",
1627                 cmd, addr, cycle0);
1628 
1629         timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1630         while (nfc_cmd_readl(NFCADDR_CMD_NFCBUSY, host->nfc->base_cmd_regs)
1631                         & NFCADDR_CMD_NFCBUSY) {
1632                 if (time_after(jiffies, timeout)) {
1633                         dev_err(host->dev,
1634                                 "Time out to wait CMD_NFCBUSY ready!\n");
1635                         return -ETIMEDOUT;
1636                 }
1637         }
1638         nfc_writel(host->nfc->hsmc_regs, CYCLE0, cycle0);
1639         nfc_cmd_addr1234_writel(cmd, addr, host->nfc->base_cmd_regs);
1640         return nfc_wait_interrupt(host, NFC_SR_CMD_DONE);
1641 }
1642 
1643 static int nfc_device_ready(struct mtd_info *mtd)
1644 {
1645         struct nand_chip *nand_chip = mtd->priv;
1646         struct atmel_nand_host *host = nand_chip->priv;
1647         if (!nfc_wait_interrupt(host, NFC_SR_RB_EDGE))
1648                 return 1;
1649         return 0;
1650 }
1651 
1652 static void nfc_select_chip(struct mtd_info *mtd, int chip)
1653 {
1654         struct nand_chip *nand_chip = mtd->priv;
1655         struct atmel_nand_host *host = nand_chip->priv;
1656 
1657         if (chip == -1)
1658                 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_DISABLE);
1659         else
1660                 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_ENABLE);
1661 }
1662 
1663 static int nfc_make_addr(struct mtd_info *mtd, int command, int column,
1664                 int page_addr, unsigned int *addr1234, unsigned int *cycle0)
1665 {
1666         struct nand_chip *chip = mtd->priv;
1667 
1668         int acycle = 0;
1669         unsigned char addr_bytes[8];
1670         int index = 0, bit_shift;
1671 
1672         BUG_ON(addr1234 == NULL || cycle0 == NULL);
1673 
1674         *cycle0 = 0;
1675         *addr1234 = 0;
1676 
1677         if (column != -1) {
1678                 if (chip->options & NAND_BUSWIDTH_16 &&
1679                                 !nand_opcode_8bits(command))
1680                         column >>= 1;
1681                 addr_bytes[acycle++] = column & 0xff;
1682                 if (mtd->writesize > 512)
1683                         addr_bytes[acycle++] = (column >> 8) & 0xff;
1684         }
1685 
1686         if (page_addr != -1) {
1687                 addr_bytes[acycle++] = page_addr & 0xff;
1688                 addr_bytes[acycle++] = (page_addr >> 8) & 0xff;
1689                 if (chip->chipsize > (128 << 20))
1690                         addr_bytes[acycle++] = (page_addr >> 16) & 0xff;
1691         }
1692 
1693         if (acycle > 4)
1694                 *cycle0 = addr_bytes[index++];
1695 
1696         for (bit_shift = 0; index < acycle; bit_shift += 8)
1697                 *addr1234 += addr_bytes[index++] << bit_shift;
1698 
1699         /* return acycle in cmd register */
1700         return acycle << NFCADDR_CMD_ACYCLE_BIT_POS;
1701 }
1702 
1703 static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
1704                                 int column, int page_addr)
1705 {
1706         struct nand_chip *chip = mtd->priv;
1707         struct atmel_nand_host *host = chip->priv;
1708         unsigned long timeout;
1709         unsigned int nfc_addr_cmd = 0;
1710 
1711         unsigned int cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1712 
1713         /* Set default settings: no cmd2, no addr cycle. read from nand */
1714         unsigned int cmd2 = 0;
1715         unsigned int vcmd2 = 0;
1716         int acycle = NFCADDR_CMD_ACYCLE_NONE;
1717         int csid = NFCADDR_CMD_CSID_3;
1718         int dataen = NFCADDR_CMD_DATADIS;
1719         int nfcwr = NFCADDR_CMD_NFCRD;
1720         unsigned int addr1234 = 0;
1721         unsigned int cycle0 = 0;
1722         bool do_addr = true;
1723         host->nfc->data_in_sram = NULL;
1724 
1725         dev_dbg(host->dev, "%s: cmd = 0x%02x, col = 0x%08x, page = 0x%08x\n",
1726              __func__, command, column, page_addr);
1727 
1728         switch (command) {
1729         case NAND_CMD_RESET:
1730                 nfc_addr_cmd = cmd1 | acycle | csid | dataen | nfcwr;
1731                 nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1732                 udelay(chip->chip_delay);
1733 
1734                 nfc_nand_command(mtd, NAND_CMD_STATUS, -1, -1);
1735                 timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1736                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) {
1737                         if (time_after(jiffies, timeout)) {
1738                                 dev_err(host->dev,
1739                                         "Time out to wait status ready!\n");
1740                                 break;
1741                         }
1742                 }
1743                 return;
1744         case NAND_CMD_STATUS:
1745                 do_addr = false;
1746                 break;
1747         case NAND_CMD_PARAM:
1748         case NAND_CMD_READID:
1749                 do_addr = false;
1750                 acycle = NFCADDR_CMD_ACYCLE_1;
1751                 if (column != -1)
1752                         addr1234 = column;
1753                 break;
1754         case NAND_CMD_RNDOUT:
1755                 cmd2 = NAND_CMD_RNDOUTSTART << NFCADDR_CMD_CMD2_BIT_POS;
1756                 vcmd2 = NFCADDR_CMD_VCMD2;
1757                 break;
1758         case NAND_CMD_READ0:
1759         case NAND_CMD_READOOB:
1760                 if (command == NAND_CMD_READOOB) {
1761                         column += mtd->writesize;
1762                         command = NAND_CMD_READ0; /* only READ0 is valid */
1763                         cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1764                 }
1765                 if (host->nfc->use_nfc_sram) {
1766                         /* Enable Data transfer to sram */
1767                         dataen = NFCADDR_CMD_DATAEN;
1768 
1769                         /* Need enable PMECC now, since NFC will transfer
1770                          * data in bus after sending nfc read command.
1771                          */
1772                         if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
1773                                 pmecc_enable(host, NAND_ECC_READ);
1774                 }
1775 
1776                 cmd2 = NAND_CMD_READSTART << NFCADDR_CMD_CMD2_BIT_POS;
1777                 vcmd2 = NFCADDR_CMD_VCMD2;
1778                 break;
1779         /* For prgramming command, the cmd need set to write enable */
1780         case NAND_CMD_PAGEPROG:
1781         case NAND_CMD_SEQIN:
1782         case NAND_CMD_RNDIN:
1783                 nfcwr = NFCADDR_CMD_NFCWR;
1784                 if (host->nfc->will_write_sram && command == NAND_CMD_SEQIN)
1785                         dataen = NFCADDR_CMD_DATAEN;
1786                 break;
1787         default:
1788                 break;
1789         }
1790 
1791         if (do_addr)
1792                 acycle = nfc_make_addr(mtd, command, column, page_addr,
1793                                 &addr1234, &cycle0);
1794 
1795         nfc_addr_cmd = cmd1 | cmd2 | vcmd2 | acycle | csid | dataen | nfcwr;
1796         nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1797 
1798         if (dataen == NFCADDR_CMD_DATAEN)
1799                 if (nfc_wait_interrupt(host, NFC_SR_XFR_DONE))
1800                         dev_err(host->dev, "something wrong, No XFR_DONE interrupt comes.\n");
1801 
1802         /*
1803          * Program and erase have their own busy handlers status, sequential
1804          * in, and deplete1 need no delay.
1805          */
1806         switch (command) {
1807         case NAND_CMD_CACHEDPROG:
1808         case NAND_CMD_PAGEPROG:
1809         case NAND_CMD_ERASE1:
1810         case NAND_CMD_ERASE2:
1811         case NAND_CMD_RNDIN:
1812         case NAND_CMD_STATUS:
1813         case NAND_CMD_RNDOUT:
1814         case NAND_CMD_SEQIN:
1815         case NAND_CMD_READID:
1816                 return;
1817 
1818         case NAND_CMD_READ0:
1819                 if (dataen == NFCADDR_CMD_DATAEN) {
1820                         host->nfc->data_in_sram = host->nfc->sram_bank0 +
1821                                 nfc_get_sram_off(host);
1822                         return;
1823                 }
1824                 /* fall through */
1825         default:
1826                 nfc_wait_interrupt(host, NFC_SR_RB_EDGE);
1827         }
1828 }
1829 
1830 static int nfc_sram_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1831                         uint32_t offset, int data_len, const uint8_t *buf,
1832                         int oob_required, int page, int cached, int raw)
1833 {
1834         int cfg, len;
1835         int status = 0;
1836         struct atmel_nand_host *host = chip->priv;
1837         void __iomem *sram = host->nfc->sram_bank0 + nfc_get_sram_off(host);
1838 
1839         /* Subpage write is not supported */
1840         if (offset || (data_len < mtd->writesize))
1841                 return -EINVAL;
1842 
1843         cfg = nfc_readl(host->nfc->hsmc_regs, CFG);
1844         len = mtd->writesize;
1845 
1846         if (unlikely(raw)) {
1847                 len += mtd->oobsize;
1848                 nfc_writel(host->nfc->hsmc_regs, CFG, cfg | NFC_CFG_WSPARE);
1849         } else
1850                 nfc_writel(host->nfc->hsmc_regs, CFG, cfg & ~NFC_CFG_WSPARE);
1851 
1852         /* Copy page data to sram that will write to nand via NFC */
1853         if (use_dma) {
1854                 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) != 0)
1855                         /* Fall back to use cpu copy */
1856                         memcpy32_toio(sram, buf, len);
1857         } else {
1858                 memcpy32_toio(sram, buf, len);
1859         }
1860 
1861         if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
1862                 /*
1863                  * When use NFC sram, need set up PMECC before send
1864                  * NAND_CMD_SEQIN command. Since when the nand command
1865                  * is sent, nfc will do transfer from sram and nand.
1866                  */
1867                 pmecc_enable(host, NAND_ECC_WRITE);
1868 
1869         host->nfc->will_write_sram = true;
1870         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1871         host->nfc->will_write_sram = false;
1872 
1873         if (likely(!raw))
1874                 /* Need to write ecc into oob */
1875                 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
1876 
1877         if (status < 0)
1878                 return status;
1879 
1880         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1881         status = chip->waitfunc(mtd, chip);
1882 
1883         if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1884                 status = chip->errstat(mtd, chip, FL_WRITING, status, page);
1885 
1886         if (status & NAND_STATUS_FAIL)
1887                 return -EIO;
1888 
1889         return 0;
1890 }
1891 
1892 static int nfc_sram_init(struct mtd_info *mtd)
1893 {
1894         struct nand_chip *chip = mtd->priv;
1895         struct atmel_nand_host *host = chip->priv;
1896         int res = 0;
1897 
1898         /* Initialize the NFC CFG register */
1899         unsigned int cfg_nfc = 0;
1900 
1901         /* set page size and oob layout */
1902         switch (mtd->writesize) {
1903         case 512:
1904                 cfg_nfc = NFC_CFG_PAGESIZE_512;
1905                 break;
1906         case 1024:
1907                 cfg_nfc = NFC_CFG_PAGESIZE_1024;
1908                 break;
1909         case 2048:
1910                 cfg_nfc = NFC_CFG_PAGESIZE_2048;
1911                 break;
1912         case 4096:
1913                 cfg_nfc = NFC_CFG_PAGESIZE_4096;
1914                 break;
1915         case 8192:
1916                 cfg_nfc = NFC_CFG_PAGESIZE_8192;
1917                 break;
1918         default:
1919                 dev_err(host->dev, "Unsupported page size for NFC.\n");
1920                 res = -ENXIO;
1921                 return res;
1922         }
1923 
1924         /* oob bytes size = (NFCSPARESIZE + 1) * 4
1925          * Max support spare size is 512 bytes. */
1926         cfg_nfc |= (((mtd->oobsize / 4) - 1) << NFC_CFG_NFC_SPARESIZE_BIT_POS
1927                 & NFC_CFG_NFC_SPARESIZE);
1928         /* default set a max timeout */
1929         cfg_nfc |= NFC_CFG_RSPARE |
1930                         NFC_CFG_NFC_DTOCYC | NFC_CFG_NFC_DTOMUL;
1931 
1932         nfc_writel(host->nfc->hsmc_regs, CFG, cfg_nfc);
1933 
1934         host->nfc->will_write_sram = false;
1935         nfc_set_sram_bank(host, 0);
1936 
1937         /* Use Write page with NFC SRAM only for PMECC or ECC NONE. */
1938         if (host->nfc->write_by_sram) {
1939                 if ((chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) ||
1940                                 chip->ecc.mode == NAND_ECC_NONE)
1941                         chip->write_page = nfc_sram_write_page;
1942                 else
1943                         host->nfc->write_by_sram = false;
1944         }
1945 
1946         dev_info(host->dev, "Using NFC Sram read %s\n",
1947                         host->nfc->write_by_sram ? "and write" : "");
1948         return 0;
1949 }
1950 
1951 static struct platform_driver atmel_nand_nfc_driver;
1952 /*
1953  * Probe for the NAND device.
1954  */
1955 static int atmel_nand_probe(struct platform_device *pdev)
1956 {
1957         struct atmel_nand_host *host;
1958         struct mtd_info *mtd;
1959         struct nand_chip *nand_chip;
1960         struct resource *mem;
1961         struct mtd_part_parser_data ppdata = {};
1962         int res, irq;
1963 
1964         /* Allocate memory for the device structure (and zero it) */
1965         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
1966         if (!host)
1967                 return -ENOMEM;
1968 
1969         res = platform_driver_register(&atmel_nand_nfc_driver);
1970         if (res)
1971                 dev_err(&pdev->dev, "atmel_nand: can't register NFC driver\n");
1972 
1973         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1974         host->io_base = devm_ioremap_resource(&pdev->dev, mem);
1975         if (IS_ERR(host->io_base)) {
1976                 dev_err(&pdev->dev, "atmel_nand: ioremap resource failed\n");
1977                 res = PTR_ERR(host->io_base);
1978                 goto err_nand_ioremap;
1979         }
1980         host->io_phys = (dma_addr_t)mem->start;
1981 
1982         mtd = &host->mtd;
1983         nand_chip = &host->nand_chip;
1984         host->dev = &pdev->dev;
1985         if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
1986                 /* Only when CONFIG_OF is enabled of_node can be parsed */
1987                 res = atmel_of_init_port(host, pdev->dev.of_node);
1988                 if (res)
1989                         goto err_nand_ioremap;
1990         } else {
1991                 memcpy(&host->board, dev_get_platdata(&pdev->dev),
1992                        sizeof(struct atmel_nand_data));
1993         }
1994 
1995         nand_chip->priv = host;         /* link the private data structures */
1996         mtd->priv = nand_chip;
1997         mtd->owner = THIS_MODULE;
1998 
1999         /* Set address of NAND IO lines */
2000         nand_chip->IO_ADDR_R = host->io_base;
2001         nand_chip->IO_ADDR_W = host->io_base;
2002 
2003         if (nand_nfc.is_initialized) {
2004                 /* NFC driver is probed and initialized */
2005                 host->nfc = &nand_nfc;
2006 
2007                 nand_chip->select_chip = nfc_select_chip;
2008                 nand_chip->dev_ready = nfc_device_ready;
2009                 nand_chip->cmdfunc = nfc_nand_command;
2010 
2011                 /* Initialize the interrupt for NFC */
2012                 irq = platform_get_irq(pdev, 0);
2013                 if (irq < 0) {
2014                         dev_err(host->dev, "Cannot get HSMC irq!\n");
2015                         res = irq;
2016                         goto err_nand_ioremap;
2017                 }
2018 
2019                 res = devm_request_irq(&pdev->dev, irq, hsmc_interrupt,
2020                                 0, "hsmc", host);
2021                 if (res) {
2022                         dev_err(&pdev->dev, "Unable to request HSMC irq %d\n",
2023                                 irq);
2024                         goto err_nand_ioremap;
2025                 }
2026         } else {
2027                 res = atmel_nand_set_enable_ready_pins(mtd);
2028                 if (res)
2029                         goto err_nand_ioremap;
2030 
2031                 nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
2032         }
2033 
2034         nand_chip->ecc.mode = host->board.ecc_mode;
2035         nand_chip->chip_delay = 20;             /* 20us command delay time */
2036 
2037         if (host->board.bus_width_16)   /* 16-bit bus width */
2038                 nand_chip->options |= NAND_BUSWIDTH_16;
2039 
2040         nand_chip->read_buf = atmel_read_buf;
2041         nand_chip->write_buf = atmel_write_buf;
2042 
2043         platform_set_drvdata(pdev, host);
2044         atmel_nand_enable(host);
2045 
2046         if (gpio_is_valid(host->board.det_pin)) {
2047                 res = devm_gpio_request(&pdev->dev,
2048                                 host->board.det_pin, "nand_det");
2049                 if (res < 0) {
2050                         dev_err(&pdev->dev,
2051                                 "can't request det gpio %d\n",
2052                                 host->board.det_pin);
2053                         goto err_no_card;
2054                 }
2055 
2056                 res = gpio_direction_input(host->board.det_pin);
2057                 if (res < 0) {
2058                         dev_err(&pdev->dev,
2059                                 "can't request input direction det gpio %d\n",
2060                                 host->board.det_pin);
2061                         goto err_no_card;
2062                 }
2063 
2064                 if (gpio_get_value(host->board.det_pin)) {
2065                         dev_info(&pdev->dev, "No SmartMedia card inserted.\n");
2066                         res = -ENXIO;
2067                         goto err_no_card;
2068                 }
2069         }
2070 
2071         if (host->board.on_flash_bbt || on_flash_bbt) {
2072                 dev_info(&pdev->dev, "Use On Flash BBT\n");
2073                 nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
2074         }
2075 
2076         if (!host->board.has_dma)
2077                 use_dma = 0;
2078 
2079         if (use_dma) {
2080                 dma_cap_mask_t mask;
2081 
2082                 dma_cap_zero(mask);
2083                 dma_cap_set(DMA_MEMCPY, mask);
2084                 host->dma_chan = dma_request_channel(mask, NULL, NULL);
2085                 if (!host->dma_chan) {
2086                         dev_err(host->dev, "Failed to request DMA channel\n");
2087                         use_dma = 0;
2088                 }
2089         }
2090         if (use_dma)
2091                 dev_info(host->dev, "Using %s for DMA transfers.\n",
2092                                         dma_chan_name(host->dma_chan));
2093         else
2094                 dev_info(host->dev, "No DMA support for NAND access.\n");
2095 
2096         /* first scan to find the device and get the page size */
2097         if (nand_scan_ident(mtd, 1, NULL)) {
2098                 res = -ENXIO;
2099                 goto err_scan_ident;
2100         }
2101 
2102         if (nand_chip->ecc.mode == NAND_ECC_HW) {
2103                 if (host->has_pmecc)
2104                         res = atmel_pmecc_nand_init_params(pdev, host);
2105                 else
2106                         res = atmel_hw_nand_init_params(pdev, host);
2107 
2108                 if (res != 0)
2109                         goto err_hw_ecc;
2110         }
2111 
2112         /* initialize the nfc configuration register */
2113         if (host->nfc && host->nfc->use_nfc_sram) {
2114                 res = nfc_sram_init(mtd);
2115                 if (res) {
2116                         host->nfc->use_nfc_sram = false;
2117                         dev_err(host->dev, "Disable use nfc sram for data transfer.\n");
2118                 }
2119         }
2120 
2121         /* second phase scan */
2122         if (nand_scan_tail(mtd)) {
2123                 res = -ENXIO;
2124                 goto err_scan_tail;
2125         }
2126 
2127         mtd->name = "atmel_nand";
2128         ppdata.of_node = pdev->dev.of_node;
2129         res = mtd_device_parse_register(mtd, NULL, &ppdata,
2130                         host->board.parts, host->board.num_parts);
2131         if (!res)
2132                 return res;
2133 
2134 err_scan_tail:
2135         if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW)
2136                 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
2137 err_hw_ecc:
2138 err_scan_ident:
2139 err_no_card:
2140         atmel_nand_disable(host);
2141         if (host->dma_chan)
2142                 dma_release_channel(host->dma_chan);
2143 err_nand_ioremap:
2144         return res;
2145 }
2146 
2147 /*
2148  * Remove a NAND device.
2149  */
2150 static int atmel_nand_remove(struct platform_device *pdev)
2151 {
2152         struct atmel_nand_host *host = platform_get_drvdata(pdev);
2153         struct mtd_info *mtd = &host->mtd;
2154 
2155         nand_release(mtd);
2156 
2157         atmel_nand_disable(host);
2158 
2159         if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
2160                 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
2161                 pmerrloc_writel(host->pmerrloc_base, ELDIS,
2162                                 PMERRLOC_DISABLE);
2163         }
2164 
2165         if (host->dma_chan)
2166                 dma_release_channel(host->dma_chan);
2167 
2168         platform_driver_unregister(&atmel_nand_nfc_driver);
2169 
2170         return 0;
2171 }
2172 
2173 static const struct of_device_id atmel_nand_dt_ids[] = {
2174         { .compatible = "atmel,at91rm9200-nand" },
2175         { /* sentinel */ }
2176 };
2177 
2178 MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids);
2179 
2180 static int atmel_nand_nfc_probe(struct platform_device *pdev)
2181 {
2182         struct atmel_nfc *nfc = &nand_nfc;
2183         struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram;
2184 
2185         nfc_cmd_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2186         nfc->base_cmd_regs = devm_ioremap_resource(&pdev->dev, nfc_cmd_regs);
2187         if (IS_ERR(nfc->base_cmd_regs))
2188                 return PTR_ERR(nfc->base_cmd_regs);
2189 
2190         nfc_hsmc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2191         nfc->hsmc_regs = devm_ioremap_resource(&pdev->dev, nfc_hsmc_regs);
2192         if (IS_ERR(nfc->hsmc_regs))
2193                 return PTR_ERR(nfc->hsmc_regs);
2194 
2195         nfc_sram = platform_get_resource(pdev, IORESOURCE_MEM, 2);
2196         if (nfc_sram) {
2197                 nfc->sram_bank0 = devm_ioremap_resource(&pdev->dev, nfc_sram);
2198                 if (IS_ERR(nfc->sram_bank0)) {
2199                         dev_warn(&pdev->dev, "Fail to ioremap the NFC sram with error: %ld. So disable NFC sram.\n",
2200                                         PTR_ERR(nfc->sram_bank0));
2201                 } else {
2202                         nfc->use_nfc_sram = true;
2203                         nfc->sram_bank0_phys = (dma_addr_t)nfc_sram->start;
2204 
2205                         if (pdev->dev.of_node)
2206                                 nfc->write_by_sram = of_property_read_bool(
2207                                                 pdev->dev.of_node,
2208                                                 "atmel,write-by-sram");
2209                 }
2210         }
2211 
2212         nfc->is_initialized = true;
2213         dev_info(&pdev->dev, "NFC is probed.\n");
2214         return 0;
2215 }
2216 
2217 static const struct of_device_id atmel_nand_nfc_match[] = {
2218         { .compatible = "atmel,sama5d3-nfc" },
2219         { /* sentinel */ }
2220 };
2221 MODULE_DEVICE_TABLE(of, atmel_nand_nfc_match);
2222 
2223 static struct platform_driver atmel_nand_nfc_driver = {
2224         .driver = {
2225                 .name = "atmel_nand_nfc",
2226                 .owner = THIS_MODULE,
2227                 .of_match_table = of_match_ptr(atmel_nand_nfc_match),
2228         },
2229         .probe = atmel_nand_nfc_probe,
2230 };
2231 
2232 static struct platform_driver atmel_nand_driver = {
2233         .probe          = atmel_nand_probe,
2234         .remove         = atmel_nand_remove,
2235         .driver         = {
2236                 .name   = "atmel_nand",
2237                 .owner  = THIS_MODULE,
2238                 .of_match_table = of_match_ptr(atmel_nand_dt_ids),
2239         },
2240 };
2241 
2242 module_platform_driver(atmel_nand_driver);
2243 
2244 MODULE_LICENSE("GPL");
2245 MODULE_AUTHOR("Rick Bronson");
2246 MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
2247 MODULE_ALIAS("platform:atmel_nand");
2248 

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