Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4

Linux/drivers/mtd/nand/atmel_nand.c

  1 /*
  2  *  Copyright © 2003 Rick Bronson
  3  *
  4  *  Derived from drivers/mtd/nand/autcpu12.c
  5  *       Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
  6  *
  7  *  Derived from drivers/mtd/spia.c
  8  *       Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
  9  *
 10  *
 11  *  Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
 12  *     Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
 13  *
 14  *     Derived from Das U-Boot source code
 15  *              (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
 16  *     © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
 17  *
 18  *  Add Programmable Multibit ECC support for various AT91 SoC
 19  *     © Copyright 2012 ATMEL, Hong Xu
 20  *
 21  *  Add Nand Flash Controller support for SAMA5 SoC
 22  *     © Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
 23  *
 24  * This program is free software; you can redistribute it and/or modify
 25  * it under the terms of the GNU General Public License version 2 as
 26  * published by the Free Software Foundation.
 27  *
 28  */
 29 
 30 #include <linux/clk.h>
 31 #include <linux/dma-mapping.h>
 32 #include <linux/slab.h>
 33 #include <linux/module.h>
 34 #include <linux/moduleparam.h>
 35 #include <linux/platform_device.h>
 36 #include <linux/of.h>
 37 #include <linux/of_device.h>
 38 #include <linux/of_gpio.h>
 39 #include <linux/of_mtd.h>
 40 #include <linux/mtd/mtd.h>
 41 #include <linux/mtd/nand.h>
 42 #include <linux/mtd/partitions.h>
 43 
 44 #include <linux/delay.h>
 45 #include <linux/dmaengine.h>
 46 #include <linux/gpio.h>
 47 #include <linux/interrupt.h>
 48 #include <linux/io.h>
 49 #include <linux/platform_data/atmel.h>
 50 
 51 static int use_dma = 1;
 52 module_param(use_dma, int, 0);
 53 
 54 static int on_flash_bbt = 0;
 55 module_param(on_flash_bbt, int, 0);
 56 
 57 /* Register access macros */
 58 #define ecc_readl(add, reg)                             \
 59         __raw_readl(add + ATMEL_ECC_##reg)
 60 #define ecc_writel(add, reg, value)                     \
 61         __raw_writel((value), add + ATMEL_ECC_##reg)
 62 
 63 #include "atmel_nand_ecc.h"     /* Hardware ECC registers */
 64 #include "atmel_nand_nfc.h"     /* Nand Flash Controller definition */
 65 
 66 struct atmel_nand_caps {
 67         bool pmecc_correct_erase_page;
 68 };
 69 
 70 /* oob layout for large page size
 71  * bad block info is on bytes 0 and 1
 72  * the bytes have to be consecutives to avoid
 73  * several NAND_CMD_RNDOUT during read
 74  */
 75 static struct nand_ecclayout atmel_oobinfo_large = {
 76         .eccbytes = 4,
 77         .eccpos = {60, 61, 62, 63},
 78         .oobfree = {
 79                 {2, 58}
 80         },
 81 };
 82 
 83 /* oob layout for small page size
 84  * bad block info is on bytes 4 and 5
 85  * the bytes have to be consecutives to avoid
 86  * several NAND_CMD_RNDOUT during read
 87  */
 88 static struct nand_ecclayout atmel_oobinfo_small = {
 89         .eccbytes = 4,
 90         .eccpos = {0, 1, 2, 3},
 91         .oobfree = {
 92                 {6, 10}
 93         },
 94 };
 95 
 96 struct atmel_nfc {
 97         void __iomem            *base_cmd_regs;
 98         void __iomem            *hsmc_regs;
 99         void                    *sram_bank0;
100         dma_addr_t              sram_bank0_phys;
101         bool                    use_nfc_sram;
102         bool                    write_by_sram;
103 
104         struct clk              *clk;
105 
106         bool                    is_initialized;
107         struct completion       comp_ready;
108         struct completion       comp_cmd_done;
109         struct completion       comp_xfer_done;
110 
111         /* Point to the sram bank which include readed data via NFC */
112         void                    *data_in_sram;
113         bool                    will_write_sram;
114 };
115 static struct atmel_nfc nand_nfc;
116 
117 struct atmel_nand_host {
118         struct nand_chip        nand_chip;
119         struct mtd_info         mtd;
120         void __iomem            *io_base;
121         dma_addr_t              io_phys;
122         struct atmel_nand_data  board;
123         struct device           *dev;
124         void __iomem            *ecc;
125 
126         struct completion       comp;
127         struct dma_chan         *dma_chan;
128 
129         struct atmel_nfc        *nfc;
130 
131         struct atmel_nand_caps  *caps;
132         bool                    has_pmecc;
133         u8                      pmecc_corr_cap;
134         u16                     pmecc_sector_size;
135         bool                    has_no_lookup_table;
136         u32                     pmecc_lookup_table_offset;
137         u32                     pmecc_lookup_table_offset_512;
138         u32                     pmecc_lookup_table_offset_1024;
139 
140         int                     pmecc_degree;   /* Degree of remainders */
141         int                     pmecc_cw_len;   /* Length of codeword */
142 
143         void __iomem            *pmerrloc_base;
144         void __iomem            *pmecc_rom_base;
145 
146         /* lookup table for alpha_to and index_of */
147         void __iomem            *pmecc_alpha_to;
148         void __iomem            *pmecc_index_of;
149 
150         /* data for pmecc computation */
151         int16_t                 *pmecc_partial_syn;
152         int16_t                 *pmecc_si;
153         int16_t                 *pmecc_smu;     /* Sigma table */
154         int16_t                 *pmecc_lmu;     /* polynomal order */
155         int                     *pmecc_mu;
156         int                     *pmecc_dmu;
157         int                     *pmecc_delta;
158 };
159 
160 static struct nand_ecclayout atmel_pmecc_oobinfo;
161 
162 /*
163  * Enable NAND.
164  */
165 static void atmel_nand_enable(struct atmel_nand_host *host)
166 {
167         if (gpio_is_valid(host->board.enable_pin))
168                 gpio_set_value(host->board.enable_pin, 0);
169 }
170 
171 /*
172  * Disable NAND.
173  */
174 static void atmel_nand_disable(struct atmel_nand_host *host)
175 {
176         if (gpio_is_valid(host->board.enable_pin))
177                 gpio_set_value(host->board.enable_pin, 1);
178 }
179 
180 /*
181  * Hardware specific access to control-lines
182  */
183 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
184 {
185         struct nand_chip *nand_chip = mtd->priv;
186         struct atmel_nand_host *host = nand_chip->priv;
187 
188         if (ctrl & NAND_CTRL_CHANGE) {
189                 if (ctrl & NAND_NCE)
190                         atmel_nand_enable(host);
191                 else
192                         atmel_nand_disable(host);
193         }
194         if (cmd == NAND_CMD_NONE)
195                 return;
196 
197         if (ctrl & NAND_CLE)
198                 writeb(cmd, host->io_base + (1 << host->board.cle));
199         else
200                 writeb(cmd, host->io_base + (1 << host->board.ale));
201 }
202 
203 /*
204  * Read the Device Ready pin.
205  */
206 static int atmel_nand_device_ready(struct mtd_info *mtd)
207 {
208         struct nand_chip *nand_chip = mtd->priv;
209         struct atmel_nand_host *host = nand_chip->priv;
210 
211         return gpio_get_value(host->board.rdy_pin) ^
212                 !!host->board.rdy_pin_active_low;
213 }
214 
215 /* Set up for hardware ready pin and enable pin. */
216 static int atmel_nand_set_enable_ready_pins(struct mtd_info *mtd)
217 {
218         struct nand_chip *chip = mtd->priv;
219         struct atmel_nand_host *host = chip->priv;
220         int res = 0;
221 
222         if (gpio_is_valid(host->board.rdy_pin)) {
223                 res = devm_gpio_request(host->dev,
224                                 host->board.rdy_pin, "nand_rdy");
225                 if (res < 0) {
226                         dev_err(host->dev,
227                                 "can't request rdy gpio %d\n",
228                                 host->board.rdy_pin);
229                         return res;
230                 }
231 
232                 res = gpio_direction_input(host->board.rdy_pin);
233                 if (res < 0) {
234                         dev_err(host->dev,
235                                 "can't request input direction rdy gpio %d\n",
236                                 host->board.rdy_pin);
237                         return res;
238                 }
239 
240                 chip->dev_ready = atmel_nand_device_ready;
241         }
242 
243         if (gpio_is_valid(host->board.enable_pin)) {
244                 res = devm_gpio_request(host->dev,
245                                 host->board.enable_pin, "nand_enable");
246                 if (res < 0) {
247                         dev_err(host->dev,
248                                 "can't request enable gpio %d\n",
249                                 host->board.enable_pin);
250                         return res;
251                 }
252 
253                 res = gpio_direction_output(host->board.enable_pin, 1);
254                 if (res < 0) {
255                         dev_err(host->dev,
256                                 "can't request output direction enable gpio %d\n",
257                                 host->board.enable_pin);
258                         return res;
259                 }
260         }
261 
262         return res;
263 }
264 
265 /*
266  * Minimal-overhead PIO for data access.
267  */
268 static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
269 {
270         struct nand_chip        *nand_chip = mtd->priv;
271         struct atmel_nand_host *host = nand_chip->priv;
272 
273         if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
274                 memcpy(buf, host->nfc->data_in_sram, len);
275                 host->nfc->data_in_sram += len;
276         } else {
277                 __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
278         }
279 }
280 
281 static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
282 {
283         struct nand_chip        *nand_chip = mtd->priv;
284         struct atmel_nand_host *host = nand_chip->priv;
285 
286         if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
287                 memcpy(buf, host->nfc->data_in_sram, len);
288                 host->nfc->data_in_sram += len;
289         } else {
290                 __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
291         }
292 }
293 
294 static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
295 {
296         struct nand_chip        *nand_chip = mtd->priv;
297 
298         __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
299 }
300 
301 static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
302 {
303         struct nand_chip        *nand_chip = mtd->priv;
304 
305         __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
306 }
307 
308 static void dma_complete_func(void *completion)
309 {
310         complete(completion);
311 }
312 
313 static int nfc_set_sram_bank(struct atmel_nand_host *host, unsigned int bank)
314 {
315         /* NFC only has two banks. Must be 0 or 1 */
316         if (bank > 1)
317                 return -EINVAL;
318 
319         if (bank) {
320                 /* Only for a 2k-page or lower flash, NFC can handle 2 banks */
321                 if (host->mtd.writesize > 2048)
322                         return -EINVAL;
323                 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK1);
324         } else {
325                 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK0);
326         }
327 
328         return 0;
329 }
330 
331 static uint nfc_get_sram_off(struct atmel_nand_host *host)
332 {
333         if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
334                 return NFC_SRAM_BANK1_OFFSET;
335         else
336                 return 0;
337 }
338 
339 static dma_addr_t nfc_sram_phys(struct atmel_nand_host *host)
340 {
341         if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
342                 return host->nfc->sram_bank0_phys + NFC_SRAM_BANK1_OFFSET;
343         else
344                 return host->nfc->sram_bank0_phys;
345 }
346 
347 static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
348                                int is_read)
349 {
350         struct dma_device *dma_dev;
351         enum dma_ctrl_flags flags;
352         dma_addr_t dma_src_addr, dma_dst_addr, phys_addr;
353         struct dma_async_tx_descriptor *tx = NULL;
354         dma_cookie_t cookie;
355         struct nand_chip *chip = mtd->priv;
356         struct atmel_nand_host *host = chip->priv;
357         void *p = buf;
358         int err = -EIO;
359         enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
360         struct atmel_nfc *nfc = host->nfc;
361 
362         if (buf >= high_memory)
363                 goto err_buf;
364 
365         dma_dev = host->dma_chan->device;
366 
367         flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
368 
369         phys_addr = dma_map_single(dma_dev->dev, p, len, dir);
370         if (dma_mapping_error(dma_dev->dev, phys_addr)) {
371                 dev_err(host->dev, "Failed to dma_map_single\n");
372                 goto err_buf;
373         }
374 
375         if (is_read) {
376                 if (nfc && nfc->data_in_sram)
377                         dma_src_addr = nfc_sram_phys(host) + (nfc->data_in_sram
378                                 - (nfc->sram_bank0 + nfc_get_sram_off(host)));
379                 else
380                         dma_src_addr = host->io_phys;
381 
382                 dma_dst_addr = phys_addr;
383         } else {
384                 dma_src_addr = phys_addr;
385 
386                 if (nfc && nfc->write_by_sram)
387                         dma_dst_addr = nfc_sram_phys(host);
388                 else
389                         dma_dst_addr = host->io_phys;
390         }
391 
392         tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr,
393                                              dma_src_addr, len, flags);
394         if (!tx) {
395                 dev_err(host->dev, "Failed to prepare DMA memcpy\n");
396                 goto err_dma;
397         }
398 
399         init_completion(&host->comp);
400         tx->callback = dma_complete_func;
401         tx->callback_param = &host->comp;
402 
403         cookie = tx->tx_submit(tx);
404         if (dma_submit_error(cookie)) {
405                 dev_err(host->dev, "Failed to do DMA tx_submit\n");
406                 goto err_dma;
407         }
408 
409         dma_async_issue_pending(host->dma_chan);
410         wait_for_completion(&host->comp);
411 
412         if (is_read && nfc && nfc->data_in_sram)
413                 /* After read data from SRAM, need to increase the position */
414                 nfc->data_in_sram += len;
415 
416         err = 0;
417 
418 err_dma:
419         dma_unmap_single(dma_dev->dev, phys_addr, len, dir);
420 err_buf:
421         if (err != 0)
422                 dev_dbg(host->dev, "Fall back to CPU I/O\n");
423         return err;
424 }
425 
426 static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
427 {
428         struct nand_chip *chip = mtd->priv;
429         struct atmel_nand_host *host = chip->priv;
430 
431         if (use_dma && len > mtd->oobsize)
432                 /* only use DMA for bigger than oob size: better performances */
433                 if (atmel_nand_dma_op(mtd, buf, len, 1) == 0)
434                         return;
435 
436         if (host->board.bus_width_16)
437                 atmel_read_buf16(mtd, buf, len);
438         else
439                 atmel_read_buf8(mtd, buf, len);
440 }
441 
442 static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
443 {
444         struct nand_chip *chip = mtd->priv;
445         struct atmel_nand_host *host = chip->priv;
446 
447         if (use_dma && len > mtd->oobsize)
448                 /* only use DMA for bigger than oob size: better performances */
449                 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0)
450                         return;
451 
452         if (host->board.bus_width_16)
453                 atmel_write_buf16(mtd, buf, len);
454         else
455                 atmel_write_buf8(mtd, buf, len);
456 }
457 
458 /*
459  * Return number of ecc bytes per sector according to sector size and
460  * correction capability
461  *
462  * Following table shows what at91 PMECC supported:
463  * Correction Capability        Sector_512_bytes        Sector_1024_bytes
464  * =====================        ================        =================
465  *                2-bits                 4-bytes                  4-bytes
466  *                4-bits                 7-bytes                  7-bytes
467  *                8-bits                13-bytes                 14-bytes
468  *               12-bits                20-bytes                 21-bytes
469  *               24-bits                39-bytes                 42-bytes
470  */
471 static int pmecc_get_ecc_bytes(int cap, int sector_size)
472 {
473         int m = 12 + sector_size / 512;
474         return (m * cap + 7) / 8;
475 }
476 
477 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
478                                     int oobsize, int ecc_len)
479 {
480         int i;
481 
482         layout->eccbytes = ecc_len;
483 
484         /* ECC will occupy the last ecc_len bytes continuously */
485         for (i = 0; i < ecc_len; i++)
486                 layout->eccpos[i] = oobsize - ecc_len + i;
487 
488         layout->oobfree[0].offset = PMECC_OOB_RESERVED_BYTES;
489         layout->oobfree[0].length =
490                 oobsize - ecc_len - layout->oobfree[0].offset;
491 }
492 
493 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
494 {
495         int table_size;
496 
497         table_size = host->pmecc_sector_size == 512 ?
498                 PMECC_LOOKUP_TABLE_SIZE_512 : PMECC_LOOKUP_TABLE_SIZE_1024;
499 
500         return host->pmecc_rom_base + host->pmecc_lookup_table_offset +
501                         table_size * sizeof(int16_t);
502 }
503 
504 static int pmecc_data_alloc(struct atmel_nand_host *host)
505 {
506         const int cap = host->pmecc_corr_cap;
507         int size;
508 
509         size = (2 * cap + 1) * sizeof(int16_t);
510         host->pmecc_partial_syn = devm_kzalloc(host->dev, size, GFP_KERNEL);
511         host->pmecc_si = devm_kzalloc(host->dev, size, GFP_KERNEL);
512         host->pmecc_lmu = devm_kzalloc(host->dev,
513                         (cap + 1) * sizeof(int16_t), GFP_KERNEL);
514         host->pmecc_smu = devm_kzalloc(host->dev,
515                         (cap + 2) * size, GFP_KERNEL);
516 
517         size = (cap + 1) * sizeof(int);
518         host->pmecc_mu = devm_kzalloc(host->dev, size, GFP_KERNEL);
519         host->pmecc_dmu = devm_kzalloc(host->dev, size, GFP_KERNEL);
520         host->pmecc_delta = devm_kzalloc(host->dev, size, GFP_KERNEL);
521 
522         if (!host->pmecc_partial_syn ||
523                 !host->pmecc_si ||
524                 !host->pmecc_lmu ||
525                 !host->pmecc_smu ||
526                 !host->pmecc_mu ||
527                 !host->pmecc_dmu ||
528                 !host->pmecc_delta)
529                 return -ENOMEM;
530 
531         return 0;
532 }
533 
534 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
535 {
536         struct nand_chip *nand_chip = mtd->priv;
537         struct atmel_nand_host *host = nand_chip->priv;
538         int i;
539         uint32_t value;
540 
541         /* Fill odd syndromes */
542         for (i = 0; i < host->pmecc_corr_cap; i++) {
543                 value = pmecc_readl_rem_relaxed(host->ecc, sector, i / 2);
544                 if (i & 1)
545                         value >>= 16;
546                 value &= 0xffff;
547                 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
548         }
549 }
550 
551 static void pmecc_substitute(struct mtd_info *mtd)
552 {
553         struct nand_chip *nand_chip = mtd->priv;
554         struct atmel_nand_host *host = nand_chip->priv;
555         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
556         int16_t __iomem *index_of = host->pmecc_index_of;
557         int16_t *partial_syn = host->pmecc_partial_syn;
558         const int cap = host->pmecc_corr_cap;
559         int16_t *si;
560         int i, j;
561 
562         /* si[] is a table that holds the current syndrome value,
563          * an element of that table belongs to the field
564          */
565         si = host->pmecc_si;
566 
567         memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
568 
569         /* Computation 2t syndromes based on S(x) */
570         /* Odd syndromes */
571         for (i = 1; i < 2 * cap; i += 2) {
572                 for (j = 0; j < host->pmecc_degree; j++) {
573                         if (partial_syn[i] & ((unsigned short)0x1 << j))
574                                 si[i] = readw_relaxed(alpha_to + i * j) ^ si[i];
575                 }
576         }
577         /* Even syndrome = (Odd syndrome) ** 2 */
578         for (i = 2, j = 1; j <= cap; i = ++j << 1) {
579                 if (si[j] == 0) {
580                         si[i] = 0;
581                 } else {
582                         int16_t tmp;
583 
584                         tmp = readw_relaxed(index_of + si[j]);
585                         tmp = (tmp * 2) % host->pmecc_cw_len;
586                         si[i] = readw_relaxed(alpha_to + tmp);
587                 }
588         }
589 
590         return;
591 }
592 
593 static void pmecc_get_sigma(struct mtd_info *mtd)
594 {
595         struct nand_chip *nand_chip = mtd->priv;
596         struct atmel_nand_host *host = nand_chip->priv;
597 
598         int16_t *lmu = host->pmecc_lmu;
599         int16_t *si = host->pmecc_si;
600         int *mu = host->pmecc_mu;
601         int *dmu = host->pmecc_dmu;     /* Discrepancy */
602         int *delta = host->pmecc_delta; /* Delta order */
603         int cw_len = host->pmecc_cw_len;
604         const int16_t cap = host->pmecc_corr_cap;
605         const int num = 2 * cap + 1;
606         int16_t __iomem *index_of = host->pmecc_index_of;
607         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
608         int i, j, k;
609         uint32_t dmu_0_count, tmp;
610         int16_t *smu = host->pmecc_smu;
611 
612         /* index of largest delta */
613         int ro;
614         int largest;
615         int diff;
616 
617         dmu_0_count = 0;
618 
619         /* First Row */
620 
621         /* Mu */
622         mu[0] = -1;
623 
624         memset(smu, 0, sizeof(int16_t) * num);
625         smu[0] = 1;
626 
627         /* discrepancy set to 1 */
628         dmu[0] = 1;
629         /* polynom order set to 0 */
630         lmu[0] = 0;
631         delta[0] = (mu[0] * 2 - lmu[0]) >> 1;
632 
633         /* Second Row */
634 
635         /* Mu */
636         mu[1] = 0;
637         /* Sigma(x) set to 1 */
638         memset(&smu[num], 0, sizeof(int16_t) * num);
639         smu[num] = 1;
640 
641         /* discrepancy set to S1 */
642         dmu[1] = si[1];
643 
644         /* polynom order set to 0 */
645         lmu[1] = 0;
646 
647         delta[1] = (mu[1] * 2 - lmu[1]) >> 1;
648 
649         /* Init the Sigma(x) last row */
650         memset(&smu[(cap + 1) * num], 0, sizeof(int16_t) * num);
651 
652         for (i = 1; i <= cap; i++) {
653                 mu[i + 1] = i << 1;
654                 /* Begin Computing Sigma (Mu+1) and L(mu) */
655                 /* check if discrepancy is set to 0 */
656                 if (dmu[i] == 0) {
657                         dmu_0_count++;
658 
659                         tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
660                         if ((cap - (lmu[i] >> 1) - 1) & 0x1)
661                                 tmp += 2;
662                         else
663                                 tmp += 1;
664 
665                         if (dmu_0_count == tmp) {
666                                 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
667                                         smu[(cap + 1) * num + j] =
668                                                         smu[i * num + j];
669 
670                                 lmu[cap + 1] = lmu[i];
671                                 return;
672                         }
673 
674                         /* copy polynom */
675                         for (j = 0; j <= lmu[i] >> 1; j++)
676                                 smu[(i + 1) * num + j] = smu[i * num + j];
677 
678                         /* copy previous polynom order to the next */
679                         lmu[i + 1] = lmu[i];
680                 } else {
681                         ro = 0;
682                         largest = -1;
683                         /* find largest delta with dmu != 0 */
684                         for (j = 0; j < i; j++) {
685                                 if ((dmu[j]) && (delta[j] > largest)) {
686                                         largest = delta[j];
687                                         ro = j;
688                                 }
689                         }
690 
691                         /* compute difference */
692                         diff = (mu[i] - mu[ro]);
693 
694                         /* Compute degree of the new smu polynomial */
695                         if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
696                                 lmu[i + 1] = lmu[i];
697                         else
698                                 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
699 
700                         /* Init smu[i+1] with 0 */
701                         for (k = 0; k < num; k++)
702                                 smu[(i + 1) * num + k] = 0;
703 
704                         /* Compute smu[i+1] */
705                         for (k = 0; k <= lmu[ro] >> 1; k++) {
706                                 int16_t a, b, c;
707 
708                                 if (!(smu[ro * num + k] && dmu[i]))
709                                         continue;
710                                 a = readw_relaxed(index_of + dmu[i]);
711                                 b = readw_relaxed(index_of + dmu[ro]);
712                                 c = readw_relaxed(index_of + smu[ro * num + k]);
713                                 tmp = a + (cw_len - b) + c;
714                                 a = readw_relaxed(alpha_to + tmp % cw_len);
715                                 smu[(i + 1) * num + (k + diff)] = a;
716                         }
717 
718                         for (k = 0; k <= lmu[i] >> 1; k++)
719                                 smu[(i + 1) * num + k] ^= smu[i * num + k];
720                 }
721 
722                 /* End Computing Sigma (Mu+1) and L(mu) */
723                 /* In either case compute delta */
724                 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
725 
726                 /* Do not compute discrepancy for the last iteration */
727                 if (i >= cap)
728                         continue;
729 
730                 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
731                         tmp = 2 * (i - 1);
732                         if (k == 0) {
733                                 dmu[i + 1] = si[tmp + 3];
734                         } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
735                                 int16_t a, b, c;
736                                 a = readw_relaxed(index_of +
737                                                 smu[(i + 1) * num + k]);
738                                 b = si[2 * (i - 1) + 3 - k];
739                                 c = readw_relaxed(index_of + b);
740                                 tmp = a + c;
741                                 tmp %= cw_len;
742                                 dmu[i + 1] = readw_relaxed(alpha_to + tmp) ^
743                                         dmu[i + 1];
744                         }
745                 }
746         }
747 
748         return;
749 }
750 
751 static int pmecc_err_location(struct mtd_info *mtd)
752 {
753         struct nand_chip *nand_chip = mtd->priv;
754         struct atmel_nand_host *host = nand_chip->priv;
755         unsigned long end_time;
756         const int cap = host->pmecc_corr_cap;
757         const int num = 2 * cap + 1;
758         int sector_size = host->pmecc_sector_size;
759         int err_nbr = 0;        /* number of error */
760         int roots_nbr;          /* number of roots */
761         int i;
762         uint32_t val;
763         int16_t *smu = host->pmecc_smu;
764 
765         pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE);
766 
767         for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
768                 pmerrloc_writel_sigma_relaxed(host->pmerrloc_base, i,
769                                       smu[(cap + 1) * num + i]);
770                 err_nbr++;
771         }
772 
773         val = (err_nbr - 1) << 16;
774         if (sector_size == 1024)
775                 val |= 1;
776 
777         pmerrloc_writel(host->pmerrloc_base, ELCFG, val);
778         pmerrloc_writel(host->pmerrloc_base, ELEN,
779                         sector_size * 8 + host->pmecc_degree * cap);
780 
781         end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
782         while (!(pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
783                  & PMERRLOC_CALC_DONE)) {
784                 if (unlikely(time_after(jiffies, end_time))) {
785                         dev_err(host->dev, "PMECC: Timeout to calculate error location.\n");
786                         return -1;
787                 }
788                 cpu_relax();
789         }
790 
791         roots_nbr = (pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
792                 & PMERRLOC_ERR_NUM_MASK) >> 8;
793         /* Number of roots == degree of smu hence <= cap */
794         if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
795                 return err_nbr - 1;
796 
797         /* Number of roots does not match the degree of smu
798          * unable to correct error */
799         return -1;
800 }
801 
802 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
803                 int sector_num, int extra_bytes, int err_nbr)
804 {
805         struct nand_chip *nand_chip = mtd->priv;
806         struct atmel_nand_host *host = nand_chip->priv;
807         int i = 0;
808         int byte_pos, bit_pos, sector_size, pos;
809         uint32_t tmp;
810         uint8_t err_byte;
811 
812         sector_size = host->pmecc_sector_size;
813 
814         while (err_nbr) {
815                 tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1;
816                 byte_pos = tmp / 8;
817                 bit_pos  = tmp % 8;
818 
819                 if (byte_pos >= (sector_size + extra_bytes))
820                         BUG();  /* should never happen */
821 
822                 if (byte_pos < sector_size) {
823                         err_byte = *(buf + byte_pos);
824                         *(buf + byte_pos) ^= (1 << bit_pos);
825 
826                         pos = sector_num * host->pmecc_sector_size + byte_pos;
827                         dev_info(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
828                                 pos, bit_pos, err_byte, *(buf + byte_pos));
829                 } else {
830                         /* Bit flip in OOB area */
831                         tmp = sector_num * nand_chip->ecc.bytes
832                                         + (byte_pos - sector_size);
833                         err_byte = ecc[tmp];
834                         ecc[tmp] ^= (1 << bit_pos);
835 
836                         pos = tmp + nand_chip->ecc.layout->eccpos[0];
837                         dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
838                                 pos, bit_pos, err_byte, ecc[tmp]);
839                 }
840 
841                 i++;
842                 err_nbr--;
843         }
844 
845         return;
846 }
847 
848 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
849         u8 *ecc)
850 {
851         struct nand_chip *nand_chip = mtd->priv;
852         struct atmel_nand_host *host = nand_chip->priv;
853         int i, err_nbr;
854         uint8_t *buf_pos;
855         int max_bitflips = 0;
856 
857         /* If can correct bitfilps from erased page, do the normal check */
858         if (host->caps->pmecc_correct_erase_page)
859                 goto normal_check;
860 
861         for (i = 0; i < nand_chip->ecc.total; i++)
862                 if (ecc[i] != 0xff)
863                         goto normal_check;
864         /* Erased page, return OK */
865         return 0;
866 
867 normal_check:
868         for (i = 0; i < nand_chip->ecc.steps; i++) {
869                 err_nbr = 0;
870                 if (pmecc_stat & 0x1) {
871                         buf_pos = buf + i * host->pmecc_sector_size;
872 
873                         pmecc_gen_syndrome(mtd, i);
874                         pmecc_substitute(mtd);
875                         pmecc_get_sigma(mtd);
876 
877                         err_nbr = pmecc_err_location(mtd);
878                         if (err_nbr == -1) {
879                                 dev_err(host->dev, "PMECC: Too many errors\n");
880                                 mtd->ecc_stats.failed++;
881                                 return -EIO;
882                         } else {
883                                 pmecc_correct_data(mtd, buf_pos, ecc, i,
884                                         nand_chip->ecc.bytes, err_nbr);
885                                 mtd->ecc_stats.corrected += err_nbr;
886                                 max_bitflips = max_t(int, max_bitflips, err_nbr);
887                         }
888                 }
889                 pmecc_stat >>= 1;
890         }
891 
892         return max_bitflips;
893 }
894 
895 static void pmecc_enable(struct atmel_nand_host *host, int ecc_op)
896 {
897         u32 val;
898 
899         if (ecc_op != NAND_ECC_READ && ecc_op != NAND_ECC_WRITE) {
900                 dev_err(host->dev, "atmel_nand: wrong pmecc operation type!");
901                 return;
902         }
903 
904         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
905         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
906         val = pmecc_readl_relaxed(host->ecc, CFG);
907 
908         if (ecc_op == NAND_ECC_READ)
909                 pmecc_writel(host->ecc, CFG, (val & ~PMECC_CFG_WRITE_OP)
910                         | PMECC_CFG_AUTO_ENABLE);
911         else
912                 pmecc_writel(host->ecc, CFG, (val | PMECC_CFG_WRITE_OP)
913                         & ~PMECC_CFG_AUTO_ENABLE);
914 
915         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
916         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
917 }
918 
919 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
920         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
921 {
922         struct atmel_nand_host *host = chip->priv;
923         int eccsize = chip->ecc.size * chip->ecc.steps;
924         uint8_t *oob = chip->oob_poi;
925         uint32_t *eccpos = chip->ecc.layout->eccpos;
926         uint32_t stat;
927         unsigned long end_time;
928         int bitflips = 0;
929 
930         if (!host->nfc || !host->nfc->use_nfc_sram)
931                 pmecc_enable(host, NAND_ECC_READ);
932 
933         chip->read_buf(mtd, buf, eccsize);
934         chip->read_buf(mtd, oob, mtd->oobsize);
935 
936         end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
937         while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
938                 if (unlikely(time_after(jiffies, end_time))) {
939                         dev_err(host->dev, "PMECC: Timeout to get error status.\n");
940                         return -EIO;
941                 }
942                 cpu_relax();
943         }
944 
945         stat = pmecc_readl_relaxed(host->ecc, ISR);
946         if (stat != 0) {
947                 bitflips = pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]);
948                 if (bitflips < 0)
949                         /* uncorrectable errors */
950                         return 0;
951         }
952 
953         return bitflips;
954 }
955 
956 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
957                 struct nand_chip *chip, const uint8_t *buf, int oob_required,
958                 int page)
959 {
960         struct atmel_nand_host *host = chip->priv;
961         uint32_t *eccpos = chip->ecc.layout->eccpos;
962         int i, j;
963         unsigned long end_time;
964 
965         if (!host->nfc || !host->nfc->write_by_sram) {
966                 pmecc_enable(host, NAND_ECC_WRITE);
967                 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
968         }
969 
970         end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
971         while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
972                 if (unlikely(time_after(jiffies, end_time))) {
973                         dev_err(host->dev, "PMECC: Timeout to get ECC value.\n");
974                         return -EIO;
975                 }
976                 cpu_relax();
977         }
978 
979         for (i = 0; i < chip->ecc.steps; i++) {
980                 for (j = 0; j < chip->ecc.bytes; j++) {
981                         int pos;
982 
983                         pos = i * chip->ecc.bytes + j;
984                         chip->oob_poi[eccpos[pos]] =
985                                 pmecc_readb_ecc_relaxed(host->ecc, i, j);
986                 }
987         }
988         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
989 
990         return 0;
991 }
992 
993 static void atmel_pmecc_core_init(struct mtd_info *mtd)
994 {
995         struct nand_chip *nand_chip = mtd->priv;
996         struct atmel_nand_host *host = nand_chip->priv;
997         uint32_t val = 0;
998         struct nand_ecclayout *ecc_layout;
999 
1000         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
1001         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
1002 
1003         switch (host->pmecc_corr_cap) {
1004         case 2:
1005                 val = PMECC_CFG_BCH_ERR2;
1006                 break;
1007         case 4:
1008                 val = PMECC_CFG_BCH_ERR4;
1009                 break;
1010         case 8:
1011                 val = PMECC_CFG_BCH_ERR8;
1012                 break;
1013         case 12:
1014                 val = PMECC_CFG_BCH_ERR12;
1015                 break;
1016         case 24:
1017                 val = PMECC_CFG_BCH_ERR24;
1018                 break;
1019         }
1020 
1021         if (host->pmecc_sector_size == 512)
1022                 val |= PMECC_CFG_SECTOR512;
1023         else if (host->pmecc_sector_size == 1024)
1024                 val |= PMECC_CFG_SECTOR1024;
1025 
1026         switch (nand_chip->ecc.steps) {
1027         case 1:
1028                 val |= PMECC_CFG_PAGE_1SECTOR;
1029                 break;
1030         case 2:
1031                 val |= PMECC_CFG_PAGE_2SECTORS;
1032                 break;
1033         case 4:
1034                 val |= PMECC_CFG_PAGE_4SECTORS;
1035                 break;
1036         case 8:
1037                 val |= PMECC_CFG_PAGE_8SECTORS;
1038                 break;
1039         }
1040 
1041         val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
1042                 | PMECC_CFG_AUTO_DISABLE);
1043         pmecc_writel(host->ecc, CFG, val);
1044 
1045         ecc_layout = nand_chip->ecc.layout;
1046         pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1);
1047         pmecc_writel(host->ecc, SADDR, ecc_layout->eccpos[0]);
1048         pmecc_writel(host->ecc, EADDR,
1049                         ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
1050         /* See datasheet about PMECC Clock Control Register */
1051         pmecc_writel(host->ecc, CLK, 2);
1052         pmecc_writel(host->ecc, IDR, 0xff);
1053         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
1054 }
1055 
1056 /*
1057  * Get minimum ecc requirements from NAND.
1058  * If pmecc-cap, pmecc-sector-size in DTS are not specified, this function
1059  * will set them according to minimum ecc requirement. Otherwise, use the
1060  * value in DTS file.
1061  * return 0 if success. otherwise return error code.
1062  */
1063 static int pmecc_choose_ecc(struct atmel_nand_host *host,
1064                 int *cap, int *sector_size)
1065 {
1066         /* Get minimum ECC requirements */
1067         if (host->nand_chip.ecc_strength_ds) {
1068                 *cap = host->nand_chip.ecc_strength_ds;
1069                 *sector_size = host->nand_chip.ecc_step_ds;
1070                 dev_info(host->dev, "minimum ECC: %d bits in %d bytes\n",
1071                                 *cap, *sector_size);
1072         } else {
1073                 *cap = 2;
1074                 *sector_size = 512;
1075                 dev_info(host->dev, "can't detect min. ECC, assume 2 bits in 512 bytes\n");
1076         }
1077 
1078         /* If device tree doesn't specify, use NAND's minimum ECC parameters */
1079         if (host->pmecc_corr_cap == 0) {
1080                 /* use the most fitable ecc bits (the near bigger one ) */
1081                 if (*cap <= 2)
1082                         host->pmecc_corr_cap = 2;
1083                 else if (*cap <= 4)
1084                         host->pmecc_corr_cap = 4;
1085                 else if (*cap <= 8)
1086                         host->pmecc_corr_cap = 8;
1087                 else if (*cap <= 12)
1088                         host->pmecc_corr_cap = 12;
1089                 else if (*cap <= 24)
1090                         host->pmecc_corr_cap = 24;
1091                 else
1092                         return -EINVAL;
1093         }
1094         if (host->pmecc_sector_size == 0) {
1095                 /* use the most fitable sector size (the near smaller one ) */
1096                 if (*sector_size >= 1024)
1097                         host->pmecc_sector_size = 1024;
1098                 else if (*sector_size >= 512)
1099                         host->pmecc_sector_size = 512;
1100                 else
1101                         return -EINVAL;
1102         }
1103         return 0;
1104 }
1105 
1106 static inline int deg(unsigned int poly)
1107 {
1108         /* polynomial degree is the most-significant bit index */
1109         return fls(poly) - 1;
1110 }
1111 
1112 static int build_gf_tables(int mm, unsigned int poly,
1113                 int16_t *index_of, int16_t *alpha_to)
1114 {
1115         unsigned int i, x = 1;
1116         const unsigned int k = 1 << deg(poly);
1117         unsigned int nn = (1 << mm) - 1;
1118 
1119         /* primitive polynomial must be of degree m */
1120         if (k != (1u << mm))
1121                 return -EINVAL;
1122 
1123         for (i = 0; i < nn; i++) {
1124                 alpha_to[i] = x;
1125                 index_of[x] = i;
1126                 if (i && (x == 1))
1127                         /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
1128                         return -EINVAL;
1129                 x <<= 1;
1130                 if (x & k)
1131                         x ^= poly;
1132         }
1133         alpha_to[nn] = 1;
1134         index_of[0] = 0;
1135 
1136         return 0;
1137 }
1138 
1139 static uint16_t *create_lookup_table(struct device *dev, int sector_size)
1140 {
1141         int degree = (sector_size == 512) ?
1142                         PMECC_GF_DIMENSION_13 :
1143                         PMECC_GF_DIMENSION_14;
1144         unsigned int poly = (sector_size == 512) ?
1145                         PMECC_GF_13_PRIMITIVE_POLY :
1146                         PMECC_GF_14_PRIMITIVE_POLY;
1147         int table_size = (sector_size == 512) ?
1148                         PMECC_LOOKUP_TABLE_SIZE_512 :
1149                         PMECC_LOOKUP_TABLE_SIZE_1024;
1150 
1151         int16_t *addr = devm_kzalloc(dev, 2 * table_size * sizeof(uint16_t),
1152                         GFP_KERNEL);
1153         if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
1154                 return NULL;
1155 
1156         return addr;
1157 }
1158 
1159 static int atmel_pmecc_nand_init_params(struct platform_device *pdev,
1160                                          struct atmel_nand_host *host)
1161 {
1162         struct mtd_info *mtd = &host->mtd;
1163         struct nand_chip *nand_chip = &host->nand_chip;
1164         struct resource *regs, *regs_pmerr, *regs_rom;
1165         uint16_t *galois_table;
1166         int cap, sector_size, err_no;
1167 
1168         err_no = pmecc_choose_ecc(host, &cap, &sector_size);
1169         if (err_no) {
1170                 dev_err(host->dev, "The NAND flash's ECC requirement are not support!");
1171                 return err_no;
1172         }
1173 
1174         if (cap > host->pmecc_corr_cap ||
1175                         sector_size != host->pmecc_sector_size)
1176                 dev_info(host->dev, "WARNING: Be Caution! Using different PMECC parameters from Nand ONFI ECC reqirement.\n");
1177 
1178         cap = host->pmecc_corr_cap;
1179         sector_size = host->pmecc_sector_size;
1180         host->pmecc_lookup_table_offset = (sector_size == 512) ?
1181                         host->pmecc_lookup_table_offset_512 :
1182                         host->pmecc_lookup_table_offset_1024;
1183 
1184         dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n",
1185                  cap, sector_size);
1186 
1187         regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1188         if (!regs) {
1189                 dev_warn(host->dev,
1190                         "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
1191                 nand_chip->ecc.mode = NAND_ECC_SOFT;
1192                 return 0;
1193         }
1194 
1195         host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1196         if (IS_ERR(host->ecc)) {
1197                 err_no = PTR_ERR(host->ecc);
1198                 goto err;
1199         }
1200 
1201         regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1202         host->pmerrloc_base = devm_ioremap_resource(&pdev->dev, regs_pmerr);
1203         if (IS_ERR(host->pmerrloc_base)) {
1204                 err_no = PTR_ERR(host->pmerrloc_base);
1205                 goto err;
1206         }
1207 
1208         if (!host->has_no_lookup_table) {
1209                 regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1210                 host->pmecc_rom_base = devm_ioremap_resource(&pdev->dev,
1211                                                                 regs_rom);
1212                 if (IS_ERR(host->pmecc_rom_base)) {
1213                         dev_err(host->dev, "Can not get I/O resource for ROM, will build a lookup table in runtime!\n");
1214                         host->has_no_lookup_table = true;
1215                 }
1216         }
1217 
1218         if (host->has_no_lookup_table) {
1219                 /* Build the look-up table in runtime */
1220                 galois_table = create_lookup_table(host->dev, sector_size);
1221                 if (!galois_table) {
1222                         dev_err(host->dev, "Failed to build a lookup table in runtime!\n");
1223                         err_no = -EINVAL;
1224                         goto err;
1225                 }
1226 
1227                 host->pmecc_rom_base = (void __iomem *)galois_table;
1228                 host->pmecc_lookup_table_offset = 0;
1229         }
1230 
1231         nand_chip->ecc.size = sector_size;
1232 
1233         /* set ECC page size and oob layout */
1234         switch (mtd->writesize) {
1235         case 512:
1236         case 1024:
1237         case 2048:
1238         case 4096:
1239         case 8192:
1240                 if (sector_size > mtd->writesize) {
1241                         dev_err(host->dev, "pmecc sector size is bigger than the page size!\n");
1242                         err_no = -EINVAL;
1243                         goto err;
1244                 }
1245 
1246                 host->pmecc_degree = (sector_size == 512) ?
1247                         PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
1248                 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
1249                 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
1250                 host->pmecc_index_of = host->pmecc_rom_base +
1251                         host->pmecc_lookup_table_offset;
1252 
1253                 nand_chip->ecc.strength = cap;
1254                 nand_chip->ecc.bytes = pmecc_get_ecc_bytes(cap, sector_size);
1255                 nand_chip->ecc.steps = mtd->writesize / sector_size;
1256                 nand_chip->ecc.total = nand_chip->ecc.bytes *
1257                         nand_chip->ecc.steps;
1258                 if (nand_chip->ecc.total >
1259                                 mtd->oobsize - PMECC_OOB_RESERVED_BYTES) {
1260                         dev_err(host->dev, "No room for ECC bytes\n");
1261                         err_no = -EINVAL;
1262                         goto err;
1263                 }
1264                 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
1265                                         mtd->oobsize,
1266                                         nand_chip->ecc.total);
1267 
1268                 nand_chip->ecc.layout = &atmel_pmecc_oobinfo;
1269                 break;
1270         default:
1271                 dev_warn(host->dev,
1272                         "Unsupported page size for PMECC, use Software ECC\n");
1273                 /* page size not handled by HW ECC */
1274                 /* switching back to soft ECC */
1275                 nand_chip->ecc.mode = NAND_ECC_SOFT;
1276                 return 0;
1277         }
1278 
1279         /* Allocate data for PMECC computation */
1280         err_no = pmecc_data_alloc(host);
1281         if (err_no) {
1282                 dev_err(host->dev,
1283                                 "Cannot allocate memory for PMECC computation!\n");
1284                 goto err;
1285         }
1286 
1287         nand_chip->options |= NAND_NO_SUBPAGE_WRITE;
1288         nand_chip->ecc.read_page = atmel_nand_pmecc_read_page;
1289         nand_chip->ecc.write_page = atmel_nand_pmecc_write_page;
1290 
1291         atmel_pmecc_core_init(mtd);
1292 
1293         return 0;
1294 
1295 err:
1296         return err_no;
1297 }
1298 
1299 /*
1300  * Calculate HW ECC
1301  *
1302  * function called after a write
1303  *
1304  * mtd:        MTD block structure
1305  * dat:        raw data (unused)
1306  * ecc_code:   buffer for ECC
1307  */
1308 static int atmel_nand_calculate(struct mtd_info *mtd,
1309                 const u_char *dat, unsigned char *ecc_code)
1310 {
1311         struct nand_chip *nand_chip = mtd->priv;
1312         struct atmel_nand_host *host = nand_chip->priv;
1313         unsigned int ecc_value;
1314 
1315         /* get the first 2 ECC bytes */
1316         ecc_value = ecc_readl(host->ecc, PR);
1317 
1318         ecc_code[0] = ecc_value & 0xFF;
1319         ecc_code[1] = (ecc_value >> 8) & 0xFF;
1320 
1321         /* get the last 2 ECC bytes */
1322         ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
1323 
1324         ecc_code[2] = ecc_value & 0xFF;
1325         ecc_code[3] = (ecc_value >> 8) & 0xFF;
1326 
1327         return 0;
1328 }
1329 
1330 /*
1331  * HW ECC read page function
1332  *
1333  * mtd:        mtd info structure
1334  * chip:       nand chip info structure
1335  * buf:        buffer to store read data
1336  * oob_required:    caller expects OOB data read to chip->oob_poi
1337  */
1338 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1339                                 uint8_t *buf, int oob_required, int page)
1340 {
1341         int eccsize = chip->ecc.size;
1342         int eccbytes = chip->ecc.bytes;
1343         uint32_t *eccpos = chip->ecc.layout->eccpos;
1344         uint8_t *p = buf;
1345         uint8_t *oob = chip->oob_poi;
1346         uint8_t *ecc_pos;
1347         int stat;
1348         unsigned int max_bitflips = 0;
1349 
1350         /*
1351          * Errata: ALE is incorrectly wired up to the ECC controller
1352          * on the AP7000, so it will include the address cycles in the
1353          * ECC calculation.
1354          *
1355          * Workaround: Reset the parity registers before reading the
1356          * actual data.
1357          */
1358         struct atmel_nand_host *host = chip->priv;
1359         if (host->board.need_reset_workaround)
1360                 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1361 
1362         /* read the page */
1363         chip->read_buf(mtd, p, eccsize);
1364 
1365         /* move to ECC position if needed */
1366         if (eccpos[0] != 0) {
1367                 /* This only works on large pages
1368                  * because the ECC controller waits for
1369                  * NAND_CMD_RNDOUTSTART after the
1370                  * NAND_CMD_RNDOUT.
1371                  * anyway, for small pages, the eccpos[0] == 0
1372                  */
1373                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1374                                 mtd->writesize + eccpos[0], -1);
1375         }
1376 
1377         /* the ECC controller needs to read the ECC just after the data */
1378         ecc_pos = oob + eccpos[0];
1379         chip->read_buf(mtd, ecc_pos, eccbytes);
1380 
1381         /* check if there's an error */
1382         stat = chip->ecc.correct(mtd, p, oob, NULL);
1383 
1384         if (stat < 0) {
1385                 mtd->ecc_stats.failed++;
1386         } else {
1387                 mtd->ecc_stats.corrected += stat;
1388                 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1389         }
1390 
1391         /* get back to oob start (end of page) */
1392         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1393 
1394         /* read the oob */
1395         chip->read_buf(mtd, oob, mtd->oobsize);
1396 
1397         return max_bitflips;
1398 }
1399 
1400 /*
1401  * HW ECC Correction
1402  *
1403  * function called after a read
1404  *
1405  * mtd:        MTD block structure
1406  * dat:        raw data read from the chip
1407  * read_ecc:   ECC from the chip (unused)
1408  * isnull:     unused
1409  *
1410  * Detect and correct a 1 bit error for a page
1411  */
1412 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1413                 u_char *read_ecc, u_char *isnull)
1414 {
1415         struct nand_chip *nand_chip = mtd->priv;
1416         struct atmel_nand_host *host = nand_chip->priv;
1417         unsigned int ecc_status;
1418         unsigned int ecc_word, ecc_bit;
1419 
1420         /* get the status from the Status Register */
1421         ecc_status = ecc_readl(host->ecc, SR);
1422 
1423         /* if there's no error */
1424         if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1425                 return 0;
1426 
1427         /* get error bit offset (4 bits) */
1428         ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
1429         /* get word address (12 bits) */
1430         ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
1431         ecc_word >>= 4;
1432 
1433         /* if there are multiple errors */
1434         if (ecc_status & ATMEL_ECC_MULERR) {
1435                 /* check if it is a freshly erased block
1436                  * (filled with 0xff) */
1437                 if ((ecc_bit == ATMEL_ECC_BITADDR)
1438                                 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1439                         /* the block has just been erased, return OK */
1440                         return 0;
1441                 }
1442                 /* it doesn't seems to be a freshly
1443                  * erased block.
1444                  * We can't correct so many errors */
1445                 dev_dbg(host->dev, "atmel_nand : multiple errors detected."
1446                                 " Unable to correct.\n");
1447                 return -EIO;
1448         }
1449 
1450         /* if there's a single bit error : we can correct it */
1451         if (ecc_status & ATMEL_ECC_ECCERR) {
1452                 /* there's nothing much to do here.
1453                  * the bit error is on the ECC itself.
1454                  */
1455                 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
1456                                 " Nothing to correct\n");
1457                 return 0;
1458         }
1459 
1460         dev_dbg(host->dev, "atmel_nand : one bit error on data."
1461                         " (word offset in the page :"
1462                         " 0x%x bit offset : 0x%x)\n",
1463                         ecc_word, ecc_bit);
1464         /* correct the error */
1465         if (nand_chip->options & NAND_BUSWIDTH_16) {
1466                 /* 16 bits words */
1467                 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1468         } else {
1469                 /* 8 bits words */
1470                 dat[ecc_word] ^= (1 << ecc_bit);
1471         }
1472         dev_dbg(host->dev, "atmel_nand : error corrected\n");
1473         return 1;
1474 }
1475 
1476 /*
1477  * Enable HW ECC : unused on most chips
1478  */
1479 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1480 {
1481         struct nand_chip *nand_chip = mtd->priv;
1482         struct atmel_nand_host *host = nand_chip->priv;
1483 
1484         if (host->board.need_reset_workaround)
1485                 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1486 }
1487 
1488 static const struct of_device_id atmel_nand_dt_ids[];
1489 
1490 static int atmel_of_init_port(struct atmel_nand_host *host,
1491                               struct device_node *np)
1492 {
1493         u32 val;
1494         u32 offset[2];
1495         int ecc_mode;
1496         struct atmel_nand_data *board = &host->board;
1497         enum of_gpio_flags flags = 0;
1498 
1499         host->caps = (struct atmel_nand_caps *)
1500                 of_match_device(atmel_nand_dt_ids, host->dev)->data;
1501 
1502         if (of_property_read_u32(np, "atmel,nand-addr-offset", &val) == 0) {
1503                 if (val >= 32) {
1504                         dev_err(host->dev, "invalid addr-offset %u\n", val);
1505                         return -EINVAL;
1506                 }
1507                 board->ale = val;
1508         }
1509 
1510         if (of_property_read_u32(np, "atmel,nand-cmd-offset", &val) == 0) {
1511                 if (val >= 32) {
1512                         dev_err(host->dev, "invalid cmd-offset %u\n", val);
1513                         return -EINVAL;
1514                 }
1515                 board->cle = val;
1516         }
1517 
1518         ecc_mode = of_get_nand_ecc_mode(np);
1519 
1520         board->ecc_mode = ecc_mode < 0 ? NAND_ECC_SOFT : ecc_mode;
1521 
1522         board->on_flash_bbt = of_get_nand_on_flash_bbt(np);
1523 
1524         board->has_dma = of_property_read_bool(np, "atmel,nand-has-dma");
1525 
1526         if (of_get_nand_bus_width(np) == 16)
1527                 board->bus_width_16 = 1;
1528 
1529         board->rdy_pin = of_get_gpio_flags(np, 0, &flags);
1530         board->rdy_pin_active_low = (flags == OF_GPIO_ACTIVE_LOW);
1531 
1532         board->enable_pin = of_get_gpio(np, 1);
1533         board->det_pin = of_get_gpio(np, 2);
1534 
1535         host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
1536 
1537         /* load the nfc driver if there is */
1538         of_platform_populate(np, NULL, NULL, host->dev);
1539 
1540         if (!(board->ecc_mode == NAND_ECC_HW) || !host->has_pmecc)
1541                 return 0;       /* Not using PMECC */
1542 
1543         /* use PMECC, get correction capability, sector size and lookup
1544          * table offset.
1545          * If correction bits and sector size are not specified, then find
1546          * them from NAND ONFI parameters.
1547          */
1548         if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
1549                 if ((val != 2) && (val != 4) && (val != 8) && (val != 12) &&
1550                                 (val != 24)) {
1551                         dev_err(host->dev,
1552                                 "Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n",
1553                                 val);
1554                         return -EINVAL;
1555                 }
1556                 host->pmecc_corr_cap = (u8)val;
1557         }
1558 
1559         if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) {
1560                 if ((val != 512) && (val != 1024)) {
1561                         dev_err(host->dev,
1562                                 "Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n",
1563                                 val);
1564                         return -EINVAL;
1565                 }
1566                 host->pmecc_sector_size = (u16)val;
1567         }
1568 
1569         if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset",
1570                         offset, 2) != 0) {
1571                 dev_err(host->dev, "Cannot get PMECC lookup table offset, will build a lookup table in runtime.\n");
1572                 host->has_no_lookup_table = true;
1573                 /* Will build a lookup table and initialize the offset later */
1574                 return 0;
1575         }
1576         if (!offset[0] && !offset[1]) {
1577                 dev_err(host->dev, "Invalid PMECC lookup table offset\n");
1578                 return -EINVAL;
1579         }
1580         host->pmecc_lookup_table_offset_512 = offset[0];
1581         host->pmecc_lookup_table_offset_1024 = offset[1];
1582 
1583         return 0;
1584 }
1585 
1586 static int atmel_hw_nand_init_params(struct platform_device *pdev,
1587                                          struct atmel_nand_host *host)
1588 {
1589         struct mtd_info *mtd = &host->mtd;
1590         struct nand_chip *nand_chip = &host->nand_chip;
1591         struct resource         *regs;
1592 
1593         regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1594         if (!regs) {
1595                 dev_err(host->dev,
1596                         "Can't get I/O resource regs, use software ECC\n");
1597                 nand_chip->ecc.mode = NAND_ECC_SOFT;
1598                 return 0;
1599         }
1600 
1601         host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1602         if (IS_ERR(host->ecc))
1603                 return PTR_ERR(host->ecc);
1604 
1605         /* ECC is calculated for the whole page (1 step) */
1606         nand_chip->ecc.size = mtd->writesize;
1607 
1608         /* set ECC page size and oob layout */
1609         switch (mtd->writesize) {
1610         case 512:
1611                 nand_chip->ecc.layout = &atmel_oobinfo_small;
1612                 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
1613                 break;
1614         case 1024:
1615                 nand_chip->ecc.layout = &atmel_oobinfo_large;
1616                 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
1617                 break;
1618         case 2048:
1619                 nand_chip->ecc.layout = &atmel_oobinfo_large;
1620                 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
1621                 break;
1622         case 4096:
1623                 nand_chip->ecc.layout = &atmel_oobinfo_large;
1624                 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
1625                 break;
1626         default:
1627                 /* page size not handled by HW ECC */
1628                 /* switching back to soft ECC */
1629                 nand_chip->ecc.mode = NAND_ECC_SOFT;
1630                 return 0;
1631         }
1632 
1633         /* set up for HW ECC */
1634         nand_chip->ecc.calculate = atmel_nand_calculate;
1635         nand_chip->ecc.correct = atmel_nand_correct;
1636         nand_chip->ecc.hwctl = atmel_nand_hwctl;
1637         nand_chip->ecc.read_page = atmel_nand_read_page;
1638         nand_chip->ecc.bytes = 4;
1639         nand_chip->ecc.strength = 1;
1640 
1641         return 0;
1642 }
1643 
1644 static inline u32 nfc_read_status(struct atmel_nand_host *host)
1645 {
1646         u32 err_flags = NFC_SR_DTOE | NFC_SR_UNDEF | NFC_SR_AWB | NFC_SR_ASE;
1647         u32 nfc_status = nfc_readl(host->nfc->hsmc_regs, SR);
1648 
1649         if (unlikely(nfc_status & err_flags)) {
1650                 if (nfc_status & NFC_SR_DTOE)
1651                         dev_err(host->dev, "NFC: Waiting Nand R/B Timeout Error\n");
1652                 else if (nfc_status & NFC_SR_UNDEF)
1653                         dev_err(host->dev, "NFC: Access Undefined Area Error\n");
1654                 else if (nfc_status & NFC_SR_AWB)
1655                         dev_err(host->dev, "NFC: Access memory While NFC is busy\n");
1656                 else if (nfc_status & NFC_SR_ASE)
1657                         dev_err(host->dev, "NFC: Access memory Size Error\n");
1658         }
1659 
1660         return nfc_status;
1661 }
1662 
1663 /* SMC interrupt service routine */
1664 static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
1665 {
1666         struct atmel_nand_host *host = dev_id;
1667         u32 status, mask, pending;
1668         irqreturn_t ret = IRQ_NONE;
1669 
1670         status = nfc_read_status(host);
1671         mask = nfc_readl(host->nfc->hsmc_regs, IMR);
1672         pending = status & mask;
1673 
1674         if (pending & NFC_SR_XFR_DONE) {
1675                 complete(&host->nfc->comp_xfer_done);
1676                 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_XFR_DONE);
1677                 ret = IRQ_HANDLED;
1678         }
1679         if (pending & NFC_SR_RB_EDGE) {
1680                 complete(&host->nfc->comp_ready);
1681                 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_RB_EDGE);
1682                 ret = IRQ_HANDLED;
1683         }
1684         if (pending & NFC_SR_CMD_DONE) {
1685                 complete(&host->nfc->comp_cmd_done);
1686                 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_CMD_DONE);
1687                 ret = IRQ_HANDLED;
1688         }
1689 
1690         return ret;
1691 }
1692 
1693 /* NFC(Nand Flash Controller) related functions */
1694 static void nfc_prepare_interrupt(struct atmel_nand_host *host, u32 flag)
1695 {
1696         if (flag & NFC_SR_XFR_DONE)
1697                 init_completion(&host->nfc->comp_xfer_done);
1698 
1699         if (flag & NFC_SR_RB_EDGE)
1700                 init_completion(&host->nfc->comp_ready);
1701 
1702         if (flag & NFC_SR_CMD_DONE)
1703                 init_completion(&host->nfc->comp_cmd_done);
1704 
1705         /* Enable interrupt that need to wait for */
1706         nfc_writel(host->nfc->hsmc_regs, IER, flag);
1707 }
1708 
1709 static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag)
1710 {
1711         int i, index = 0;
1712         struct completion *comp[3];     /* Support 3 interrupt completion */
1713 
1714         if (flag & NFC_SR_XFR_DONE)
1715                 comp[index++] = &host->nfc->comp_xfer_done;
1716 
1717         if (flag & NFC_SR_RB_EDGE)
1718                 comp[index++] = &host->nfc->comp_ready;
1719 
1720         if (flag & NFC_SR_CMD_DONE)
1721                 comp[index++] = &host->nfc->comp_cmd_done;
1722 
1723         if (index == 0) {
1724                 dev_err(host->dev, "Unknown interrupt flag: 0x%08x\n", flag);
1725                 return -EINVAL;
1726         }
1727 
1728         for (i = 0; i < index; i++) {
1729                 if (wait_for_completion_timeout(comp[i],
1730                                 msecs_to_jiffies(NFC_TIME_OUT_MS)))
1731                         continue;       /* wait for next completion */
1732                 else
1733                         goto err_timeout;
1734         }
1735 
1736         return 0;
1737 
1738 err_timeout:
1739         dev_err(host->dev, "Time out to wait for interrupt: 0x%08x\n", flag);
1740         /* Disable the interrupt as it is not handled by interrupt handler */
1741         nfc_writel(host->nfc->hsmc_regs, IDR, flag);
1742         return -ETIMEDOUT;
1743 }
1744 
1745 static int nfc_send_command(struct atmel_nand_host *host,
1746         unsigned int cmd, unsigned int addr, unsigned char cycle0)
1747 {
1748         unsigned long timeout;
1749         u32 flag = NFC_SR_CMD_DONE;
1750         flag |= cmd & NFCADDR_CMD_DATAEN ? NFC_SR_XFR_DONE : 0;
1751 
1752         dev_dbg(host->dev,
1753                 "nfc_cmd: 0x%08x, addr1234: 0x%08x, cycle0: 0x%02x\n",
1754                 cmd, addr, cycle0);
1755 
1756         timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1757         while (nfc_readl(host->nfc->hsmc_regs, SR) & NFC_SR_BUSY) {
1758                 if (time_after(jiffies, timeout)) {
1759                         dev_err(host->dev,
1760                                 "Time out to wait for NFC ready!\n");
1761                         return -ETIMEDOUT;
1762                 }
1763         }
1764 
1765         nfc_prepare_interrupt(host, flag);
1766         nfc_writel(host->nfc->hsmc_regs, CYCLE0, cycle0);
1767         nfc_cmd_addr1234_writel(cmd, addr, host->nfc->base_cmd_regs);
1768         return nfc_wait_interrupt(host, flag);
1769 }
1770 
1771 static int nfc_device_ready(struct mtd_info *mtd)
1772 {
1773         u32 status, mask;
1774         struct nand_chip *nand_chip = mtd->priv;
1775         struct atmel_nand_host *host = nand_chip->priv;
1776 
1777         status = nfc_read_status(host);
1778         mask = nfc_readl(host->nfc->hsmc_regs, IMR);
1779 
1780         /* The mask should be 0. If not we may lost interrupts */
1781         if (unlikely(mask & status))
1782                 dev_err(host->dev, "Lost the interrupt flags: 0x%08x\n",
1783                                 mask & status);
1784 
1785         return status & NFC_SR_RB_EDGE;
1786 }
1787 
1788 static void nfc_select_chip(struct mtd_info *mtd, int chip)
1789 {
1790         struct nand_chip *nand_chip = mtd->priv;
1791         struct atmel_nand_host *host = nand_chip->priv;
1792 
1793         if (chip == -1)
1794                 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_DISABLE);
1795         else
1796                 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_ENABLE);
1797 }
1798 
1799 static int nfc_make_addr(struct mtd_info *mtd, int command, int column,
1800                 int page_addr, unsigned int *addr1234, unsigned int *cycle0)
1801 {
1802         struct nand_chip *chip = mtd->priv;
1803 
1804         int acycle = 0;
1805         unsigned char addr_bytes[8];
1806         int index = 0, bit_shift;
1807 
1808         BUG_ON(addr1234 == NULL || cycle0 == NULL);
1809 
1810         *cycle0 = 0;
1811         *addr1234 = 0;
1812 
1813         if (column != -1) {
1814                 if (chip->options & NAND_BUSWIDTH_16 &&
1815                                 !nand_opcode_8bits(command))
1816                         column >>= 1;
1817                 addr_bytes[acycle++] = column & 0xff;
1818                 if (mtd->writesize > 512)
1819                         addr_bytes[acycle++] = (column >> 8) & 0xff;
1820         }
1821 
1822         if (page_addr != -1) {
1823                 addr_bytes[acycle++] = page_addr & 0xff;
1824                 addr_bytes[acycle++] = (page_addr >> 8) & 0xff;
1825                 if (chip->chipsize > (128 << 20))
1826                         addr_bytes[acycle++] = (page_addr >> 16) & 0xff;
1827         }
1828 
1829         if (acycle > 4)
1830                 *cycle0 = addr_bytes[index++];
1831 
1832         for (bit_shift = 0; index < acycle; bit_shift += 8)
1833                 *addr1234 += addr_bytes[index++] << bit_shift;
1834 
1835         /* return acycle in cmd register */
1836         return acycle << NFCADDR_CMD_ACYCLE_BIT_POS;
1837 }
1838 
1839 static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
1840                                 int column, int page_addr)
1841 {
1842         struct nand_chip *chip = mtd->priv;
1843         struct atmel_nand_host *host = chip->priv;
1844         unsigned long timeout;
1845         unsigned int nfc_addr_cmd = 0;
1846 
1847         unsigned int cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1848 
1849         /* Set default settings: no cmd2, no addr cycle. read from nand */
1850         unsigned int cmd2 = 0;
1851         unsigned int vcmd2 = 0;
1852         int acycle = NFCADDR_CMD_ACYCLE_NONE;
1853         int csid = NFCADDR_CMD_CSID_3;
1854         int dataen = NFCADDR_CMD_DATADIS;
1855         int nfcwr = NFCADDR_CMD_NFCRD;
1856         unsigned int addr1234 = 0;
1857         unsigned int cycle0 = 0;
1858         bool do_addr = true;
1859         host->nfc->data_in_sram = NULL;
1860 
1861         dev_dbg(host->dev, "%s: cmd = 0x%02x, col = 0x%08x, page = 0x%08x\n",
1862              __func__, command, column, page_addr);
1863 
1864         switch (command) {
1865         case NAND_CMD_RESET:
1866                 nfc_addr_cmd = cmd1 | acycle | csid | dataen | nfcwr;
1867                 nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1868                 udelay(chip->chip_delay);
1869 
1870                 nfc_nand_command(mtd, NAND_CMD_STATUS, -1, -1);
1871                 timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1872                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) {
1873                         if (time_after(jiffies, timeout)) {
1874                                 dev_err(host->dev,
1875                                         "Time out to wait status ready!\n");
1876                                 break;
1877                         }
1878                 }
1879                 return;
1880         case NAND_CMD_STATUS:
1881                 do_addr = false;
1882                 break;
1883         case NAND_CMD_PARAM:
1884         case NAND_CMD_READID:
1885                 do_addr = false;
1886                 acycle = NFCADDR_CMD_ACYCLE_1;
1887                 if (column != -1)
1888                         addr1234 = column;
1889                 break;
1890         case NAND_CMD_RNDOUT:
1891                 cmd2 = NAND_CMD_RNDOUTSTART << NFCADDR_CMD_CMD2_BIT_POS;
1892                 vcmd2 = NFCADDR_CMD_VCMD2;
1893                 break;
1894         case NAND_CMD_READ0:
1895         case NAND_CMD_READOOB:
1896                 if (command == NAND_CMD_READOOB) {
1897                         column += mtd->writesize;
1898                         command = NAND_CMD_READ0; /* only READ0 is valid */
1899                         cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1900                 }
1901                 if (host->nfc->use_nfc_sram) {
1902                         /* Enable Data transfer to sram */
1903                         dataen = NFCADDR_CMD_DATAEN;
1904 
1905                         /* Need enable PMECC now, since NFC will transfer
1906                          * data in bus after sending nfc read command.
1907                          */
1908                         if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
1909                                 pmecc_enable(host, NAND_ECC_READ);
1910                 }
1911 
1912                 cmd2 = NAND_CMD_READSTART << NFCADDR_CMD_CMD2_BIT_POS;
1913                 vcmd2 = NFCADDR_CMD_VCMD2;
1914                 break;
1915         /* For prgramming command, the cmd need set to write enable */
1916         case NAND_CMD_PAGEPROG:
1917         case NAND_CMD_SEQIN:
1918         case NAND_CMD_RNDIN:
1919                 nfcwr = NFCADDR_CMD_NFCWR;
1920                 if (host->nfc->will_write_sram && command == NAND_CMD_SEQIN)
1921                         dataen = NFCADDR_CMD_DATAEN;
1922                 break;
1923         default:
1924                 break;
1925         }
1926 
1927         if (do_addr)
1928                 acycle = nfc_make_addr(mtd, command, column, page_addr,
1929                                 &addr1234, &cycle0);
1930 
1931         nfc_addr_cmd = cmd1 | cmd2 | vcmd2 | acycle | csid | dataen | nfcwr;
1932         nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1933 
1934         /*
1935          * Program and erase have their own busy handlers status, sequential
1936          * in, and deplete1 need no delay.
1937          */
1938         switch (command) {
1939         case NAND_CMD_CACHEDPROG:
1940         case NAND_CMD_PAGEPROG:
1941         case NAND_CMD_ERASE1:
1942         case NAND_CMD_ERASE2:
1943         case NAND_CMD_RNDIN:
1944         case NAND_CMD_STATUS:
1945         case NAND_CMD_RNDOUT:
1946         case NAND_CMD_SEQIN:
1947         case NAND_CMD_READID:
1948                 return;
1949 
1950         case NAND_CMD_READ0:
1951                 if (dataen == NFCADDR_CMD_DATAEN) {
1952                         host->nfc->data_in_sram = host->nfc->sram_bank0 +
1953                                 nfc_get_sram_off(host);
1954                         return;
1955                 }
1956                 /* fall through */
1957         default:
1958                 nfc_prepare_interrupt(host, NFC_SR_RB_EDGE);
1959                 nfc_wait_interrupt(host, NFC_SR_RB_EDGE);
1960         }
1961 }
1962 
1963 static int nfc_sram_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1964                         uint32_t offset, int data_len, const uint8_t *buf,
1965                         int oob_required, int page, int cached, int raw)
1966 {
1967         int cfg, len;
1968         int status = 0;
1969         struct atmel_nand_host *host = chip->priv;
1970         void *sram = host->nfc->sram_bank0 + nfc_get_sram_off(host);
1971 
1972         /* Subpage write is not supported */
1973         if (offset || (data_len < mtd->writesize))
1974                 return -EINVAL;
1975 
1976         len = mtd->writesize;
1977         /* Copy page data to sram that will write to nand via NFC */
1978         if (use_dma) {
1979                 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) != 0)
1980                         /* Fall back to use cpu copy */
1981                         memcpy(sram, buf, len);
1982         } else {
1983                 memcpy(sram, buf, len);
1984         }
1985 
1986         cfg = nfc_readl(host->nfc->hsmc_regs, CFG);
1987         if (unlikely(raw) && oob_required) {
1988                 memcpy(sram + len, chip->oob_poi, mtd->oobsize);
1989                 len += mtd->oobsize;
1990                 nfc_writel(host->nfc->hsmc_regs, CFG, cfg | NFC_CFG_WSPARE);
1991         } else {
1992                 nfc_writel(host->nfc->hsmc_regs, CFG, cfg & ~NFC_CFG_WSPARE);
1993         }
1994 
1995         if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
1996                 /*
1997                  * When use NFC sram, need set up PMECC before send
1998                  * NAND_CMD_SEQIN command. Since when the nand command
1999                  * is sent, nfc will do transfer from sram and nand.
2000                  */
2001                 pmecc_enable(host, NAND_ECC_WRITE);
2002 
2003         host->nfc->will_write_sram = true;
2004         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2005         host->nfc->will_write_sram = false;
2006 
2007         if (likely(!raw))
2008                 /* Need to write ecc into oob */
2009                 status = chip->ecc.write_page(mtd, chip, buf, oob_required,
2010                                               page);
2011 
2012         if (status < 0)
2013                 return status;
2014 
2015         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2016         status = chip->waitfunc(mtd, chip);
2017 
2018         if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2019                 status = chip->errstat(mtd, chip, FL_WRITING, status, page);
2020 
2021         if (status & NAND_STATUS_FAIL)
2022                 return -EIO;
2023 
2024         return 0;
2025 }
2026 
2027 static int nfc_sram_init(struct mtd_info *mtd)
2028 {
2029         struct nand_chip *chip = mtd->priv;
2030         struct atmel_nand_host *host = chip->priv;
2031         int res = 0;
2032 
2033         /* Initialize the NFC CFG register */
2034         unsigned int cfg_nfc = 0;
2035 
2036         /* set page size and oob layout */
2037         switch (mtd->writesize) {
2038         case 512:
2039                 cfg_nfc = NFC_CFG_PAGESIZE_512;
2040                 break;
2041         case 1024:
2042                 cfg_nfc = NFC_CFG_PAGESIZE_1024;
2043                 break;
2044         case 2048:
2045                 cfg_nfc = NFC_CFG_PAGESIZE_2048;
2046                 break;
2047         case 4096:
2048                 cfg_nfc = NFC_CFG_PAGESIZE_4096;
2049                 break;
2050         case 8192:
2051                 cfg_nfc = NFC_CFG_PAGESIZE_8192;
2052                 break;
2053         default:
2054                 dev_err(host->dev, "Unsupported page size for NFC.\n");
2055                 res = -ENXIO;
2056                 return res;
2057         }
2058 
2059         /* oob bytes size = (NFCSPARESIZE + 1) * 4
2060          * Max support spare size is 512 bytes. */
2061         cfg_nfc |= (((mtd->oobsize / 4) - 1) << NFC_CFG_NFC_SPARESIZE_BIT_POS
2062                 & NFC_CFG_NFC_SPARESIZE);
2063         /* default set a max timeout */
2064         cfg_nfc |= NFC_CFG_RSPARE |
2065                         NFC_CFG_NFC_DTOCYC | NFC_CFG_NFC_DTOMUL;
2066 
2067         nfc_writel(host->nfc->hsmc_regs, CFG, cfg_nfc);
2068 
2069         host->nfc->will_write_sram = false;
2070         nfc_set_sram_bank(host, 0);
2071 
2072         /* Use Write page with NFC SRAM only for PMECC or ECC NONE. */
2073         if (host->nfc->write_by_sram) {
2074                 if ((chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) ||
2075                                 chip->ecc.mode == NAND_ECC_NONE)
2076                         chip->write_page = nfc_sram_write_page;
2077                 else
2078                         host->nfc->write_by_sram = false;
2079         }
2080 
2081         dev_info(host->dev, "Using NFC Sram read %s\n",
2082                         host->nfc->write_by_sram ? "and write" : "");
2083         return 0;
2084 }
2085 
2086 static struct platform_driver atmel_nand_nfc_driver;
2087 /*
2088  * Probe for the NAND device.
2089  */
2090 static int atmel_nand_probe(struct platform_device *pdev)
2091 {
2092         struct atmel_nand_host *host;
2093         struct mtd_info *mtd;
2094         struct nand_chip *nand_chip;
2095         struct resource *mem;
2096         struct mtd_part_parser_data ppdata = {};
2097         int res, irq;
2098 
2099         /* Allocate memory for the device structure (and zero it) */
2100         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
2101         if (!host)
2102                 return -ENOMEM;
2103 
2104         res = platform_driver_register(&atmel_nand_nfc_driver);
2105         if (res)
2106                 dev_err(&pdev->dev, "atmel_nand: can't register NFC driver\n");
2107 
2108         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2109         host->io_base = devm_ioremap_resource(&pdev->dev, mem);
2110         if (IS_ERR(host->io_base)) {
2111                 res = PTR_ERR(host->io_base);
2112                 goto err_nand_ioremap;
2113         }
2114         host->io_phys = (dma_addr_t)mem->start;
2115 
2116         mtd = &host->mtd;
2117         nand_chip = &host->nand_chip;
2118         host->dev = &pdev->dev;
2119         if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
2120                 /* Only when CONFIG_OF is enabled of_node can be parsed */
2121                 res = atmel_of_init_port(host, pdev->dev.of_node);
2122                 if (res)
2123                         goto err_nand_ioremap;
2124         } else {
2125                 memcpy(&host->board, dev_get_platdata(&pdev->dev),
2126                        sizeof(struct atmel_nand_data));
2127         }
2128 
2129         nand_chip->priv = host;         /* link the private data structures */
2130         mtd->priv = nand_chip;
2131         mtd->dev.parent = &pdev->dev;
2132 
2133         /* Set address of NAND IO lines */
2134         nand_chip->IO_ADDR_R = host->io_base;
2135         nand_chip->IO_ADDR_W = host->io_base;
2136 
2137         if (nand_nfc.is_initialized) {
2138                 /* NFC driver is probed and initialized */
2139                 host->nfc = &nand_nfc;
2140 
2141                 nand_chip->select_chip = nfc_select_chip;
2142                 nand_chip->dev_ready = nfc_device_ready;
2143                 nand_chip->cmdfunc = nfc_nand_command;
2144 
2145                 /* Initialize the interrupt for NFC */
2146                 irq = platform_get_irq(pdev, 0);
2147                 if (irq < 0) {
2148                         dev_err(host->dev, "Cannot get HSMC irq!\n");
2149                         res = irq;
2150                         goto err_nand_ioremap;
2151                 }
2152 
2153                 res = devm_request_irq(&pdev->dev, irq, hsmc_interrupt,
2154                                 0, "hsmc", host);
2155                 if (res) {
2156                         dev_err(&pdev->dev, "Unable to request HSMC irq %d\n",
2157                                 irq);
2158                         goto err_nand_ioremap;
2159                 }
2160         } else {
2161                 res = atmel_nand_set_enable_ready_pins(mtd);
2162                 if (res)
2163                         goto err_nand_ioremap;
2164 
2165                 nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
2166         }
2167 
2168         nand_chip->ecc.mode = host->board.ecc_mode;
2169         nand_chip->chip_delay = 40;             /* 40us command delay time */
2170 
2171         if (host->board.bus_width_16)   /* 16-bit bus width */
2172                 nand_chip->options |= NAND_BUSWIDTH_16;
2173 
2174         nand_chip->read_buf = atmel_read_buf;
2175         nand_chip->write_buf = atmel_write_buf;
2176 
2177         platform_set_drvdata(pdev, host);
2178         atmel_nand_enable(host);
2179 
2180         if (gpio_is_valid(host->board.det_pin)) {
2181                 res = devm_gpio_request(&pdev->dev,
2182                                 host->board.det_pin, "nand_det");
2183                 if (res < 0) {
2184                         dev_err(&pdev->dev,
2185                                 "can't request det gpio %d\n",
2186                                 host->board.det_pin);
2187                         goto err_no_card;
2188                 }
2189 
2190                 res = gpio_direction_input(host->board.det_pin);
2191                 if (res < 0) {
2192                         dev_err(&pdev->dev,
2193                                 "can't request input direction det gpio %d\n",
2194                                 host->board.det_pin);
2195                         goto err_no_card;
2196                 }
2197 
2198                 if (gpio_get_value(host->board.det_pin)) {
2199                         dev_info(&pdev->dev, "No SmartMedia card inserted.\n");
2200                         res = -ENXIO;
2201                         goto err_no_card;
2202                 }
2203         }
2204 
2205         if (host->board.on_flash_bbt || on_flash_bbt) {
2206                 dev_info(&pdev->dev, "Use On Flash BBT\n");
2207                 nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
2208         }
2209 
2210         if (!host->board.has_dma)
2211                 use_dma = 0;
2212 
2213         if (use_dma) {
2214                 dma_cap_mask_t mask;
2215 
2216                 dma_cap_zero(mask);
2217                 dma_cap_set(DMA_MEMCPY, mask);
2218                 host->dma_chan = dma_request_channel(mask, NULL, NULL);
2219                 if (!host->dma_chan) {
2220                         dev_err(host->dev, "Failed to request DMA channel\n");
2221                         use_dma = 0;
2222                 }
2223         }
2224         if (use_dma)
2225                 dev_info(host->dev, "Using %s for DMA transfers.\n",
2226                                         dma_chan_name(host->dma_chan));
2227         else
2228                 dev_info(host->dev, "No DMA support for NAND access.\n");
2229 
2230         /* first scan to find the device and get the page size */
2231         if (nand_scan_ident(mtd, 1, NULL)) {
2232                 res = -ENXIO;
2233                 goto err_scan_ident;
2234         }
2235 
2236         if (nand_chip->ecc.mode == NAND_ECC_HW) {
2237                 if (host->has_pmecc)
2238                         res = atmel_pmecc_nand_init_params(pdev, host);
2239                 else
2240                         res = atmel_hw_nand_init_params(pdev, host);
2241 
2242                 if (res != 0)
2243                         goto err_hw_ecc;
2244         }
2245 
2246         /* initialize the nfc configuration register */
2247         if (host->nfc && host->nfc->use_nfc_sram) {
2248                 res = nfc_sram_init(mtd);
2249                 if (res) {
2250                         host->nfc->use_nfc_sram = false;
2251                         dev_err(host->dev, "Disable use nfc sram for data transfer.\n");
2252                 }
2253         }
2254 
2255         /* second phase scan */
2256         if (nand_scan_tail(mtd)) {
2257                 res = -ENXIO;
2258                 goto err_scan_tail;
2259         }
2260 
2261         mtd->name = "atmel_nand";
2262         ppdata.of_node = pdev->dev.of_node;
2263         res = mtd_device_parse_register(mtd, NULL, &ppdata,
2264                         host->board.parts, host->board.num_parts);
2265         if (!res)
2266                 return res;
2267 
2268 err_scan_tail:
2269         if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW)
2270                 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
2271 err_hw_ecc:
2272 err_scan_ident:
2273 err_no_card:
2274         atmel_nand_disable(host);
2275         if (host->dma_chan)
2276                 dma_release_channel(host->dma_chan);
2277 err_nand_ioremap:
2278         return res;
2279 }
2280 
2281 /*
2282  * Remove a NAND device.
2283  */
2284 static int atmel_nand_remove(struct platform_device *pdev)
2285 {
2286         struct atmel_nand_host *host = platform_get_drvdata(pdev);
2287         struct mtd_info *mtd = &host->mtd;
2288 
2289         nand_release(mtd);
2290 
2291         atmel_nand_disable(host);
2292 
2293         if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
2294                 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
2295                 pmerrloc_writel(host->pmerrloc_base, ELDIS,
2296                                 PMERRLOC_DISABLE);
2297         }
2298 
2299         if (host->dma_chan)
2300                 dma_release_channel(host->dma_chan);
2301 
2302         platform_driver_unregister(&atmel_nand_nfc_driver);
2303 
2304         return 0;
2305 }
2306 
2307 static struct atmel_nand_caps at91rm9200_caps = {
2308         .pmecc_correct_erase_page = false,
2309 };
2310 
2311 static struct atmel_nand_caps sama5d4_caps = {
2312         .pmecc_correct_erase_page = true,
2313 };
2314 
2315 static const struct of_device_id atmel_nand_dt_ids[] = {
2316         { .compatible = "atmel,at91rm9200-nand", .data = &at91rm9200_caps },
2317         { .compatible = "atmel,sama5d4-nand", .data = &sama5d4_caps },
2318         { /* sentinel */ }
2319 };
2320 
2321 MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids);
2322 
2323 static int atmel_nand_nfc_probe(struct platform_device *pdev)
2324 {
2325         struct atmel_nfc *nfc = &nand_nfc;
2326         struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram;
2327         int ret;
2328 
2329         nfc_cmd_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2330         nfc->base_cmd_regs = devm_ioremap_resource(&pdev->dev, nfc_cmd_regs);
2331         if (IS_ERR(nfc->base_cmd_regs))
2332                 return PTR_ERR(nfc->base_cmd_regs);
2333 
2334         nfc_hsmc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2335         nfc->hsmc_regs = devm_ioremap_resource(&pdev->dev, nfc_hsmc_regs);
2336         if (IS_ERR(nfc->hsmc_regs))
2337                 return PTR_ERR(nfc->hsmc_regs);
2338 
2339         nfc_sram = platform_get_resource(pdev, IORESOURCE_MEM, 2);
2340         if (nfc_sram) {
2341                 nfc->sram_bank0 = (void * __force)
2342                                 devm_ioremap_resource(&pdev->dev, nfc_sram);
2343                 if (IS_ERR(nfc->sram_bank0)) {
2344                         dev_warn(&pdev->dev, "Fail to ioremap the NFC sram with error: %ld. So disable NFC sram.\n",
2345                                         PTR_ERR(nfc->sram_bank0));
2346                 } else {
2347                         nfc->use_nfc_sram = true;
2348                         nfc->sram_bank0_phys = (dma_addr_t)nfc_sram->start;
2349 
2350                         if (pdev->dev.of_node)
2351                                 nfc->write_by_sram = of_property_read_bool(
2352                                                 pdev->dev.of_node,
2353                                                 "atmel,write-by-sram");
2354                 }
2355         }
2356 
2357         nfc_writel(nfc->hsmc_regs, IDR, 0xffffffff);
2358         nfc_readl(nfc->hsmc_regs, SR);  /* clear the NFC_SR */
2359 
2360         nfc->clk = devm_clk_get(&pdev->dev, NULL);
2361         if (!IS_ERR(nfc->clk)) {
2362                 ret = clk_prepare_enable(nfc->clk);
2363                 if (ret)
2364                         return ret;
2365         } else {
2366                 dev_warn(&pdev->dev, "NFC clock missing, update your Device Tree");
2367         }
2368 
2369         nfc->is_initialized = true;
2370         dev_info(&pdev->dev, "NFC is probed.\n");
2371 
2372         return 0;
2373 }
2374 
2375 static int atmel_nand_nfc_remove(struct platform_device *pdev)
2376 {
2377         struct atmel_nfc *nfc = &nand_nfc;
2378 
2379         if (!IS_ERR(nfc->clk))
2380                 clk_disable_unprepare(nfc->clk);
2381 
2382         return 0;
2383 }
2384 
2385 static const struct of_device_id atmel_nand_nfc_match[] = {
2386         { .compatible = "atmel,sama5d3-nfc" },
2387         { /* sentinel */ }
2388 };
2389 MODULE_DEVICE_TABLE(of, atmel_nand_nfc_match);
2390 
2391 static struct platform_driver atmel_nand_nfc_driver = {
2392         .driver = {
2393                 .name = "atmel_nand_nfc",
2394                 .of_match_table = of_match_ptr(atmel_nand_nfc_match),
2395         },
2396         .probe = atmel_nand_nfc_probe,
2397         .remove = atmel_nand_nfc_remove,
2398 };
2399 
2400 static struct platform_driver atmel_nand_driver = {
2401         .probe          = atmel_nand_probe,
2402         .remove         = atmel_nand_remove,
2403         .driver         = {
2404                 .name   = "atmel_nand",
2405                 .of_match_table = of_match_ptr(atmel_nand_dt_ids),
2406         },
2407 };
2408 
2409 module_platform_driver(atmel_nand_driver);
2410 
2411 MODULE_LICENSE("GPL");
2412 MODULE_AUTHOR("Rick Bronson");
2413 MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
2414 MODULE_ALIAS("platform:atmel_nand");
2415 

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