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Linux/drivers/mtd/maps/scb2_flash.c

  1 /*
  2  * MTD map driver for BIOS Flash on Intel SCB2 boards
  3  * Copyright (C) 2002 Sun Microsystems, Inc.
  4  * Tim Hockin <thockin@sun.com>
  5  *
  6  * A few notes on this MTD map:
  7  *
  8  * This was developed with a small number of SCB2 boards to test on.
  9  * Hopefully, Intel has not introducted too many unaccounted variables in the
 10  * making of this board.
 11  *
 12  * The BIOS marks its own memory region as 'reserved' in the e820 map.  We
 13  * try to request it here, but if it fails, we carry on anyway.
 14  *
 15  * This is how the chip is attached, so said the schematic:
 16  * * a 4 MiB (32 Mib) 16 bit chip
 17  * * a 1 MiB memory region
 18  * * A20 and A21 pulled up
 19  * * D8-D15 ignored
 20  * What this means is that, while we are addressing bytes linearly, we are
 21  * really addressing words, and discarding the other byte.  This means that
 22  * the chip MUST BE at least 2 MiB.  This also means that every block is
 23  * actually half as big as the chip reports.  It also means that accesses of
 24  * logical address 0 hit higher-address sections of the chip, not physical 0.
 25  * One can only hope that these 4MiB x16 chips were a lot cheaper than 1MiB x8
 26  * chips.
 27  *
 28  * This driver assumes the chip is not write-protected by an external signal.
 29  * As of the this writing, that is true, but may change, just to spite me.
 30  *
 31  * The actual BIOS layout has been mostly reverse engineered.  Intel BIOS
 32  * updates for this board include 10 related (*.bio - &.bi9) binary files and
 33  * another separate (*.bbo) binary file.  The 10 files are 64k of data + a
 34  * small header.  If the headers are stripped off, the 10 64k files can be
 35  * concatenated into a 640k image.  This is your BIOS image, proper.  The
 36  * separate .bbo file also has a small header.  It is the 'Boot Block'
 37  * recovery BIOS.  Once the header is stripped, no further prep is needed.
 38  * As best I can tell, the BIOS is arranged as such:
 39  * offset 0x00000 to 0x4ffff (320k):  unknown - SCSI BIOS, etc?
 40  * offset 0x50000 to 0xeffff (640k):  BIOS proper
 41  * offset 0xf0000 ty 0xfffff (64k):   Boot Block region
 42  *
 43  * Intel's BIOS update program flashes the BIOS and Boot Block in separate
 44  * steps.  Probably a wise thing to do.
 45  */
 46 
 47 #include <linux/module.h>
 48 #include <linux/types.h>
 49 #include <linux/kernel.h>
 50 #include <asm/io.h>
 51 #include <linux/mtd/mtd.h>
 52 #include <linux/mtd/map.h>
 53 #include <linux/mtd/cfi.h>
 54 #include <linux/pci.h>
 55 #include <linux/pci_ids.h>
 56 
 57 #define MODNAME         "scb2_flash"
 58 #define SCB2_ADDR       0xfff00000
 59 #define SCB2_WINDOW     0x00100000
 60 
 61 
 62 static void __iomem *scb2_ioaddr;
 63 static struct mtd_info *scb2_mtd;
 64 static struct map_info scb2_map = {
 65         .name =      "SCB2 BIOS Flash",
 66         .size =      0,
 67         .bankwidth =  1,
 68 };
 69 static int region_fail;
 70 
 71 static int scb2_fixup_mtd(struct mtd_info *mtd)
 72 {
 73         int i;
 74         int done = 0;
 75         struct map_info *map = mtd->priv;
 76         struct cfi_private *cfi = map->fldrv_priv;
 77 
 78         /* barf if this doesn't look right */
 79         if (cfi->cfiq->InterfaceDesc != CFI_INTERFACE_X16_ASYNC) {
 80                 printk(KERN_ERR MODNAME ": unsupported InterfaceDesc: %#x\n",
 81                     cfi->cfiq->InterfaceDesc);
 82                 return -1;
 83         }
 84 
 85         /* I wasn't here. I didn't see. dwmw2. */
 86 
 87         /* the chip is sometimes bigger than the map - what a waste */
 88         mtd->size = map->size;
 89 
 90         /*
 91          * We only REALLY get half the chip, due to the way it is
 92          * wired up - D8-D15 are tossed away.  We read linear bytes,
 93          * but in reality we are getting 1/2 of each 16-bit read,
 94          * which LOOKS linear to us.  Because CFI code accounts for
 95          * things like lock/unlock/erase by eraseregions, we need to
 96          * fudge them to reflect this.  Erases go like this:
 97          *   * send an erase to an address
 98          *   * the chip samples the address and erases the block
 99          *   * add the block erasesize to the address and repeat
100          *   -- the problem is that addresses are 16-bit addressable
101          *   -- we end up erasing every-other block
102          */
103         mtd->erasesize /= 2;
104         for (i = 0; i < mtd->numeraseregions; i++) {
105                 struct mtd_erase_region_info *region = &mtd->eraseregions[i];
106                 region->erasesize /= 2;
107         }
108 
109         /*
110          * If the chip is bigger than the map, it is wired with the high
111          * address lines pulled up.  This makes us access the top portion of
112          * the chip, so all our erase-region info is wrong.  Start cutting from
113          * the bottom.
114          */
115         for (i = 0; !done && i < mtd->numeraseregions; i++) {
116                 struct mtd_erase_region_info *region = &mtd->eraseregions[i];
117 
118                 if (region->numblocks * region->erasesize > mtd->size) {
119                         region->numblocks = ((unsigned long)mtd->size /
120                                                 region->erasesize);
121                         done = 1;
122                 } else {
123                         region->numblocks = 0;
124                 }
125                 region->offset = 0;
126         }
127 
128         return 0;
129 }
130 
131 /* CSB5's 'Function Control Register' has bits for decoding @ >= 0xffc00000 */
132 #define CSB5_FCR        0x41
133 #define CSB5_FCR_DECODE_ALL 0x0e
134 static int scb2_flash_probe(struct pci_dev *dev,
135                             const struct pci_device_id *ent)
136 {
137         u8 reg;
138 
139         /* enable decoding of the flash region in the south bridge */
140         pci_read_config_byte(dev, CSB5_FCR, &reg);
141         pci_write_config_byte(dev, CSB5_FCR, reg | CSB5_FCR_DECODE_ALL);
142 
143         if (!request_mem_region(SCB2_ADDR, SCB2_WINDOW, scb2_map.name)) {
144                 /*
145                  * The BIOS seems to mark the flash region as 'reserved'
146                  * in the e820 map.  Warn and go about our business.
147                  */
148                 printk(KERN_WARNING MODNAME
149                     ": warning - can't reserve rom window, continuing\n");
150                 region_fail = 1;
151         }
152 
153         /* remap the IO window (w/o caching) */
154         scb2_ioaddr = ioremap_nocache(SCB2_ADDR, SCB2_WINDOW);
155         if (!scb2_ioaddr) {
156                 printk(KERN_ERR MODNAME ": Failed to ioremap window!\n");
157                 if (!region_fail)
158                         release_mem_region(SCB2_ADDR, SCB2_WINDOW);
159                 return -ENOMEM;
160         }
161 
162         scb2_map.phys = SCB2_ADDR;
163         scb2_map.virt = scb2_ioaddr;
164         scb2_map.size = SCB2_WINDOW;
165 
166         simple_map_init(&scb2_map);
167 
168         /* try to find a chip */
169         scb2_mtd = do_map_probe("cfi_probe", &scb2_map);
170 
171         if (!scb2_mtd) {
172                 printk(KERN_ERR MODNAME ": flash probe failed!\n");
173                 iounmap(scb2_ioaddr);
174                 if (!region_fail)
175                         release_mem_region(SCB2_ADDR, SCB2_WINDOW);
176                 return -ENODEV;
177         }
178 
179         scb2_mtd->owner = THIS_MODULE;
180         if (scb2_fixup_mtd(scb2_mtd) < 0) {
181                 mtd_device_unregister(scb2_mtd);
182                 map_destroy(scb2_mtd);
183                 iounmap(scb2_ioaddr);
184                 if (!region_fail)
185                         release_mem_region(SCB2_ADDR, SCB2_WINDOW);
186                 return -ENODEV;
187         }
188 
189         printk(KERN_NOTICE MODNAME ": chip size 0x%llx at offset 0x%llx\n",
190                (unsigned long long)scb2_mtd->size,
191                (unsigned long long)(SCB2_WINDOW - scb2_mtd->size));
192 
193         mtd_device_register(scb2_mtd, NULL, 0);
194 
195         return 0;
196 }
197 
198 static void scb2_flash_remove(struct pci_dev *dev)
199 {
200         if (!scb2_mtd)
201                 return;
202 
203         /* disable flash writes */
204         mtd_lock(scb2_mtd, 0, scb2_mtd->size);
205 
206         mtd_device_unregister(scb2_mtd);
207         map_destroy(scb2_mtd);
208 
209         iounmap(scb2_ioaddr);
210         scb2_ioaddr = NULL;
211 
212         if (!region_fail)
213                 release_mem_region(SCB2_ADDR, SCB2_WINDOW);
214 }
215 
216 static struct pci_device_id scb2_flash_pci_ids[] = {
217         {
218           .vendor = PCI_VENDOR_ID_SERVERWORKS,
219           .device = PCI_DEVICE_ID_SERVERWORKS_CSB5,
220           .subvendor = PCI_ANY_ID,
221           .subdevice = PCI_ANY_ID
222         },
223         { 0, }
224 };
225 
226 static struct pci_driver scb2_flash_driver = {
227         .name =     "Intel SCB2 BIOS Flash",
228         .id_table = scb2_flash_pci_ids,
229         .probe =    scb2_flash_probe,
230         .remove =   scb2_flash_remove,
231 };
232 
233 module_pci_driver(scb2_flash_driver);
234 
235 MODULE_LICENSE("GPL");
236 MODULE_AUTHOR("Tim Hockin <thockin@sun.com>");
237 MODULE_DESCRIPTION("MTD map driver for Intel SCB2 BIOS Flash");
238 MODULE_DEVICE_TABLE(pci, scb2_flash_pci_ids);
239 

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