Version:  2.0.40 2.2.26 2.4.37 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15

Linux/drivers/mtd/devices/spear_smi.c

  1 /*
  2  * SMI (Serial Memory Controller) device driver for Serial NOR Flash on
  3  * SPEAr platform
  4  * The serial nor interface is largely based on drivers/mtd/m25p80.c,
  5  * however the SPI interface has been replaced by SMI.
  6  *
  7  * Copyright © 2010 STMicroelectronics.
  8  * Ashish Priyadarshi
  9  * Shiraz Hashim <shiraz.linux.kernel@gmail.com>
 10  *
 11  * This file is licensed under the terms of the GNU General Public
 12  * License version 2. This program is licensed "as is" without any
 13  * warranty of any kind, whether express or implied.
 14  */
 15 
 16 #include <linux/clk.h>
 17 #include <linux/delay.h>
 18 #include <linux/device.h>
 19 #include <linux/err.h>
 20 #include <linux/errno.h>
 21 #include <linux/interrupt.h>
 22 #include <linux/io.h>
 23 #include <linux/ioport.h>
 24 #include <linux/jiffies.h>
 25 #include <linux/kernel.h>
 26 #include <linux/module.h>
 27 #include <linux/param.h>
 28 #include <linux/platform_device.h>
 29 #include <linux/pm.h>
 30 #include <linux/mtd/mtd.h>
 31 #include <linux/mtd/partitions.h>
 32 #include <linux/mtd/spear_smi.h>
 33 #include <linux/mutex.h>
 34 #include <linux/sched.h>
 35 #include <linux/slab.h>
 36 #include <linux/wait.h>
 37 #include <linux/of.h>
 38 #include <linux/of_address.h>
 39 
 40 /* SMI clock rate */
 41 #define SMI_MAX_CLOCK_FREQ      50000000 /* 50 MHz */
 42 
 43 /* MAX time out to safely come out of a erase or write busy conditions */
 44 #define SMI_PROBE_TIMEOUT       (HZ / 10)
 45 #define SMI_MAX_TIME_OUT        (3 * HZ)
 46 
 47 /* timeout for command completion */
 48 #define SMI_CMD_TIMEOUT         (HZ / 10)
 49 
 50 /* registers of smi */
 51 #define SMI_CR1         0x0     /* SMI control register 1 */
 52 #define SMI_CR2         0x4     /* SMI control register 2 */
 53 #define SMI_SR          0x8     /* SMI status register */
 54 #define SMI_TR          0xC     /* SMI transmit register */
 55 #define SMI_RR          0x10    /* SMI receive register */
 56 
 57 /* defines for control_reg 1 */
 58 #define BANK_EN         (0xF << 0)      /* enables all banks */
 59 #define DSEL_TIME       (0x6 << 4)      /* Deselect time 6 + 1 SMI_CK periods */
 60 #define SW_MODE         (0x1 << 28)     /* enables SW Mode */
 61 #define WB_MODE         (0x1 << 29)     /* Write Burst Mode */
 62 #define FAST_MODE       (0x1 << 15)     /* Fast Mode */
 63 #define HOLD1           (0x1 << 16)     /* Clock Hold period selection */
 64 
 65 /* defines for control_reg 2 */
 66 #define SEND            (0x1 << 7)      /* Send data */
 67 #define TFIE            (0x1 << 8)      /* Transmission Flag Interrupt Enable */
 68 #define WCIE            (0x1 << 9)      /* Write Complete Interrupt Enable */
 69 #define RD_STATUS_REG   (0x1 << 10)     /* reads status reg */
 70 #define WE              (0x1 << 11)     /* Write Enable */
 71 
 72 #define TX_LEN_SHIFT    0
 73 #define RX_LEN_SHIFT    4
 74 #define BANK_SHIFT      12
 75 
 76 /* defines for status register */
 77 #define SR_WIP          0x1     /* Write in progress */
 78 #define SR_WEL          0x2     /* Write enable latch */
 79 #define SR_BP0          0x4     /* Block protect 0 */
 80 #define SR_BP1          0x8     /* Block protect 1 */
 81 #define SR_BP2          0x10    /* Block protect 2 */
 82 #define SR_SRWD         0x80    /* SR write protect */
 83 #define TFF             0x100   /* Transfer Finished Flag */
 84 #define WCF             0x200   /* Transfer Finished Flag */
 85 #define ERF1            0x400   /* Forbidden Write Request */
 86 #define ERF2            0x800   /* Forbidden Access */
 87 
 88 #define WM_SHIFT        12
 89 
 90 /* flash opcodes */
 91 #define OPCODE_RDID     0x9f    /* Read JEDEC ID */
 92 
 93 /* Flash Device Ids maintenance section */
 94 
 95 /* data structure to maintain flash ids from different vendors */
 96 struct flash_device {
 97         char *name;
 98         u8 erase_cmd;
 99         u32 device_id;
100         u32 pagesize;
101         unsigned long sectorsize;
102         unsigned long size_in_bytes;
103 };
104 
105 #define FLASH_ID(n, es, id, psize, ssize, size) \
106 {                               \
107         .name = n,              \
108         .erase_cmd = es,        \
109         .device_id = id,        \
110         .pagesize = psize,      \
111         .sectorsize = ssize,    \
112         .size_in_bytes = size   \
113 }
114 
115 static struct flash_device flash_devices[] = {
116         FLASH_ID("st m25p16"     , 0xd8, 0x00152020, 0x100, 0x10000, 0x200000),
117         FLASH_ID("st m25p32"     , 0xd8, 0x00162020, 0x100, 0x10000, 0x400000),
118         FLASH_ID("st m25p64"     , 0xd8, 0x00172020, 0x100, 0x10000, 0x800000),
119         FLASH_ID("st m25p128"    , 0xd8, 0x00182020, 0x100, 0x40000, 0x1000000),
120         FLASH_ID("st m25p05"     , 0xd8, 0x00102020, 0x80 , 0x8000 , 0x10000),
121         FLASH_ID("st m25p10"     , 0xd8, 0x00112020, 0x80 , 0x8000 , 0x20000),
122         FLASH_ID("st m25p20"     , 0xd8, 0x00122020, 0x100, 0x10000, 0x40000),
123         FLASH_ID("st m25p40"     , 0xd8, 0x00132020, 0x100, 0x10000, 0x80000),
124         FLASH_ID("st m25p80"     , 0xd8, 0x00142020, 0x100, 0x10000, 0x100000),
125         FLASH_ID("st m45pe10"    , 0xd8, 0x00114020, 0x100, 0x10000, 0x20000),
126         FLASH_ID("st m45pe20"    , 0xd8, 0x00124020, 0x100, 0x10000, 0x40000),
127         FLASH_ID("st m45pe40"    , 0xd8, 0x00134020, 0x100, 0x10000, 0x80000),
128         FLASH_ID("st m45pe80"    , 0xd8, 0x00144020, 0x100, 0x10000, 0x100000),
129         FLASH_ID("sp s25fl004"   , 0xd8, 0x00120201, 0x100, 0x10000, 0x80000),
130         FLASH_ID("sp s25fl008"   , 0xd8, 0x00130201, 0x100, 0x10000, 0x100000),
131         FLASH_ID("sp s25fl016"   , 0xd8, 0x00140201, 0x100, 0x10000, 0x200000),
132         FLASH_ID("sp s25fl032"   , 0xd8, 0x00150201, 0x100, 0x10000, 0x400000),
133         FLASH_ID("sp s25fl064"   , 0xd8, 0x00160201, 0x100, 0x10000, 0x800000),
134         FLASH_ID("atmel 25f512"  , 0x52, 0x0065001F, 0x80 , 0x8000 , 0x10000),
135         FLASH_ID("atmel 25f1024" , 0x52, 0x0060001F, 0x100, 0x8000 , 0x20000),
136         FLASH_ID("atmel 25f2048" , 0x52, 0x0063001F, 0x100, 0x10000, 0x40000),
137         FLASH_ID("atmel 25f4096" , 0x52, 0x0064001F, 0x100, 0x10000, 0x80000),
138         FLASH_ID("atmel 25fs040" , 0xd7, 0x0004661F, 0x100, 0x10000, 0x80000),
139         FLASH_ID("mac 25l512"    , 0xd8, 0x001020C2, 0x010, 0x10000, 0x10000),
140         FLASH_ID("mac 25l1005"   , 0xd8, 0x001120C2, 0x010, 0x10000, 0x20000),
141         FLASH_ID("mac 25l2005"   , 0xd8, 0x001220C2, 0x010, 0x10000, 0x40000),
142         FLASH_ID("mac 25l4005"   , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000),
143         FLASH_ID("mac 25l4005a"  , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000),
144         FLASH_ID("mac 25l8005"   , 0xd8, 0x001420C2, 0x010, 0x10000, 0x100000),
145         FLASH_ID("mac 25l1605"   , 0xd8, 0x001520C2, 0x100, 0x10000, 0x200000),
146         FLASH_ID("mac 25l1605a"  , 0xd8, 0x001520C2, 0x010, 0x10000, 0x200000),
147         FLASH_ID("mac 25l3205"   , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000),
148         FLASH_ID("mac 25l3205a"  , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000),
149         FLASH_ID("mac 25l6405"   , 0xd8, 0x001720C2, 0x100, 0x10000, 0x800000),
150 };
151 
152 /* Define spear specific structures */
153 
154 struct spear_snor_flash;
155 
156 /**
157  * struct spear_smi - Structure for SMI Device
158  *
159  * @clk: functional clock
160  * @status: current status register of SMI.
161  * @clk_rate: functional clock rate of SMI (default: SMI_MAX_CLOCK_FREQ)
162  * @lock: lock to prevent parallel access of SMI.
163  * @io_base: base address for registers of SMI.
164  * @pdev: platform device
165  * @cmd_complete: queue to wait for command completion of NOR-flash.
166  * @num_flashes: number of flashes actually present on board.
167  * @flash: separate structure for each Serial NOR-flash attached to SMI.
168  */
169 struct spear_smi {
170         struct clk *clk;
171         u32 status;
172         unsigned long clk_rate;
173         struct mutex lock;
174         void __iomem *io_base;
175         struct platform_device *pdev;
176         wait_queue_head_t cmd_complete;
177         u32 num_flashes;
178         struct spear_snor_flash *flash[MAX_NUM_FLASH_CHIP];
179 };
180 
181 /**
182  * struct spear_snor_flash - Structure for Serial NOR Flash
183  *
184  * @bank: Bank number(0, 1, 2, 3) for each NOR-flash.
185  * @dev_id: Device ID of NOR-flash.
186  * @lock: lock to manage flash read, write and erase operations
187  * @mtd: MTD info for each NOR-flash.
188  * @num_parts: Total number of partition in each bank of NOR-flash.
189  * @parts: Partition info for each bank of NOR-flash.
190  * @page_size: Page size of NOR-flash.
191  * @base_addr: Base address of NOR-flash.
192  * @erase_cmd: erase command may vary on different flash types
193  * @fast_mode: flash supports read in fast mode
194  */
195 struct spear_snor_flash {
196         u32 bank;
197         u32 dev_id;
198         struct mutex lock;
199         struct mtd_info mtd;
200         u32 num_parts;
201         struct mtd_partition *parts;
202         u32 page_size;
203         void __iomem *base_addr;
204         u8 erase_cmd;
205         u8 fast_mode;
206 };
207 
208 static inline struct spear_snor_flash *get_flash_data(struct mtd_info *mtd)
209 {
210         return container_of(mtd, struct spear_snor_flash, mtd);
211 }
212 
213 /**
214  * spear_smi_read_sr - Read status register of flash through SMI
215  * @dev: structure of SMI information.
216  * @bank: bank to which flash is connected
217  *
218  * This routine will return the status register of the flash chip present at the
219  * given bank.
220  */
221 static int spear_smi_read_sr(struct spear_smi *dev, u32 bank)
222 {
223         int ret;
224         u32 ctrlreg1;
225 
226         mutex_lock(&dev->lock);
227         dev->status = 0; /* Will be set in interrupt handler */
228 
229         ctrlreg1 = readl(dev->io_base + SMI_CR1);
230         /* program smi in hw mode */
231         writel(ctrlreg1 & ~(SW_MODE | WB_MODE), dev->io_base + SMI_CR1);
232 
233         /* performing a rsr instruction in hw mode */
234         writel((bank << BANK_SHIFT) | RD_STATUS_REG | TFIE,
235                         dev->io_base + SMI_CR2);
236 
237         /* wait for tff */
238         ret = wait_event_interruptible_timeout(dev->cmd_complete,
239                         dev->status & TFF, SMI_CMD_TIMEOUT);
240 
241         /* copy dev->status (lower 16 bits) in order to release lock */
242         if (ret > 0)
243                 ret = dev->status & 0xffff;
244         else if (ret == 0)
245                 ret = -ETIMEDOUT;
246 
247         /* restore the ctrl regs state */
248         writel(ctrlreg1, dev->io_base + SMI_CR1);
249         writel(0, dev->io_base + SMI_CR2);
250         mutex_unlock(&dev->lock);
251 
252         return ret;
253 }
254 
255 /**
256  * spear_smi_wait_till_ready - wait till flash is ready
257  * @dev: structure of SMI information.
258  * @bank: flash corresponding to this bank
259  * @timeout: timeout for busy wait condition
260  *
261  * This routine checks for WIP (write in progress) bit in Status register
262  * If successful the routine returns 0 else -EBUSY
263  */
264 static int spear_smi_wait_till_ready(struct spear_smi *dev, u32 bank,
265                 unsigned long timeout)
266 {
267         unsigned long finish;
268         int status;
269 
270         finish = jiffies + timeout;
271         do {
272                 status = spear_smi_read_sr(dev, bank);
273                 if (status < 0) {
274                         if (status == -ETIMEDOUT)
275                                 continue; /* try till finish */
276                         return status;
277                 } else if (!(status & SR_WIP)) {
278                         return 0;
279                 }
280 
281                 cond_resched();
282         } while (!time_after_eq(jiffies, finish));
283 
284         dev_err(&dev->pdev->dev, "smi controller is busy, timeout\n");
285         return -EBUSY;
286 }
287 
288 /**
289  * spear_smi_int_handler - SMI Interrupt Handler.
290  * @irq: irq number
291  * @dev_id: structure of SMI device, embedded in dev_id.
292  *
293  * The handler clears all interrupt conditions and records the status in
294  * dev->status which is used by the driver later.
295  */
296 static irqreturn_t spear_smi_int_handler(int irq, void *dev_id)
297 {
298         u32 status = 0;
299         struct spear_smi *dev = dev_id;
300 
301         status = readl(dev->io_base + SMI_SR);
302 
303         if (unlikely(!status))
304                 return IRQ_NONE;
305 
306         /* clear all interrupt conditions */
307         writel(0, dev->io_base + SMI_SR);
308 
309         /* copy the status register in dev->status */
310         dev->status |= status;
311 
312         /* send the completion */
313         wake_up_interruptible(&dev->cmd_complete);
314 
315         return IRQ_HANDLED;
316 }
317 
318 /**
319  * spear_smi_hw_init - initializes the smi controller.
320  * @dev: structure of smi device
321  *
322  * this routine initializes the smi controller wit the default values
323  */
324 static void spear_smi_hw_init(struct spear_smi *dev)
325 {
326         unsigned long rate = 0;
327         u32 prescale = 0;
328         u32 val;
329 
330         rate = clk_get_rate(dev->clk);
331 
332         /* functional clock of smi */
333         prescale = DIV_ROUND_UP(rate, dev->clk_rate);
334 
335         /*
336          * setting the standard values, fast mode, prescaler for
337          * SMI_MAX_CLOCK_FREQ (50MHz) operation and bank enable
338          */
339         val = HOLD1 | BANK_EN | DSEL_TIME | (prescale << 8);
340 
341         mutex_lock(&dev->lock);
342         /* clear all interrupt conditions */
343         writel(0, dev->io_base + SMI_SR);
344 
345         writel(val, dev->io_base + SMI_CR1);
346         mutex_unlock(&dev->lock);
347 }
348 
349 /**
350  * get_flash_index - match chip id from a flash list.
351  * @flash_id: a valid nor flash chip id obtained from board.
352  *
353  * try to validate the chip id by matching from a list, if not found then simply
354  * returns negative. In case of success returns index in to the flash devices
355  * array.
356  */
357 static int get_flash_index(u32 flash_id)
358 {
359         int index;
360 
361         /* Matches chip-id to entire list of 'serial-nor flash' ids */
362         for (index = 0; index < ARRAY_SIZE(flash_devices); index++) {
363                 if (flash_devices[index].device_id == flash_id)
364                         return index;
365         }
366 
367         /* Memory chip is not listed and not supported */
368         return -ENODEV;
369 }
370 
371 /**
372  * spear_smi_write_enable - Enable the flash to do write operation
373  * @dev: structure of SMI device
374  * @bank: enable write for flash connected to this bank
375  *
376  * Set write enable latch with Write Enable command.
377  * Returns 0 on success.
378  */
379 static int spear_smi_write_enable(struct spear_smi *dev, u32 bank)
380 {
381         int ret;
382         u32 ctrlreg1;
383 
384         mutex_lock(&dev->lock);
385         dev->status = 0; /* Will be set in interrupt handler */
386 
387         ctrlreg1 = readl(dev->io_base + SMI_CR1);
388         /* program smi in h/w mode */
389         writel(ctrlreg1 & ~SW_MODE, dev->io_base + SMI_CR1);
390 
391         /* give the flash, write enable command */
392         writel((bank << BANK_SHIFT) | WE | TFIE, dev->io_base + SMI_CR2);
393 
394         ret = wait_event_interruptible_timeout(dev->cmd_complete,
395                         dev->status & TFF, SMI_CMD_TIMEOUT);
396 
397         /* restore the ctrl regs state */
398         writel(ctrlreg1, dev->io_base + SMI_CR1);
399         writel(0, dev->io_base + SMI_CR2);
400 
401         if (ret == 0) {
402                 ret = -EIO;
403                 dev_err(&dev->pdev->dev,
404                         "smi controller failed on write enable\n");
405         } else if (ret > 0) {
406                 /* check whether write mode status is set for required bank */
407                 if (dev->status & (1 << (bank + WM_SHIFT)))
408                         ret = 0;
409                 else {
410                         dev_err(&dev->pdev->dev, "couldn't enable write\n");
411                         ret = -EIO;
412                 }
413         }
414 
415         mutex_unlock(&dev->lock);
416         return ret;
417 }
418 
419 static inline u32
420 get_sector_erase_cmd(struct spear_snor_flash *flash, u32 offset)
421 {
422         u32 cmd;
423         u8 *x = (u8 *)&cmd;
424 
425         x[0] = flash->erase_cmd;
426         x[1] = offset >> 16;
427         x[2] = offset >> 8;
428         x[3] = offset;
429 
430         return cmd;
431 }
432 
433 /**
434  * spear_smi_erase_sector - erase one sector of flash
435  * @dev: structure of SMI information
436  * @command: erase command to be send
437  * @bank: bank to which this command needs to be send
438  * @bytes: size of command
439  *
440  * Erase one sector of flash memory at offset ``offset'' which is any
441  * address within the sector which should be erased.
442  * Returns 0 if successful, non-zero otherwise.
443  */
444 static int spear_smi_erase_sector(struct spear_smi *dev,
445                 u32 bank, u32 command, u32 bytes)
446 {
447         u32 ctrlreg1 = 0;
448         int ret;
449 
450         ret = spear_smi_wait_till_ready(dev, bank, SMI_MAX_TIME_OUT);
451         if (ret)
452                 return ret;
453 
454         ret = spear_smi_write_enable(dev, bank);
455         if (ret)
456                 return ret;
457 
458         mutex_lock(&dev->lock);
459 
460         ctrlreg1 = readl(dev->io_base + SMI_CR1);
461         writel((ctrlreg1 | SW_MODE) & ~WB_MODE, dev->io_base + SMI_CR1);
462 
463         /* send command in sw mode */
464         writel(command, dev->io_base + SMI_TR);
465 
466         writel((bank << BANK_SHIFT) | SEND | TFIE | (bytes << TX_LEN_SHIFT),
467                         dev->io_base + SMI_CR2);
468 
469         ret = wait_event_interruptible_timeout(dev->cmd_complete,
470                         dev->status & TFF, SMI_CMD_TIMEOUT);
471 
472         if (ret == 0) {
473                 ret = -EIO;
474                 dev_err(&dev->pdev->dev, "sector erase failed\n");
475         } else if (ret > 0)
476                 ret = 0; /* success */
477 
478         /* restore ctrl regs */
479         writel(ctrlreg1, dev->io_base + SMI_CR1);
480         writel(0, dev->io_base + SMI_CR2);
481 
482         mutex_unlock(&dev->lock);
483         return ret;
484 }
485 
486 /**
487  * spear_mtd_erase - perform flash erase operation as requested by user
488  * @mtd: Provides the memory characteristics
489  * @e_info: Provides the erase information
490  *
491  * Erase an address range on the flash chip. The address range may extend
492  * one or more erase sectors. Return an error is there is a problem erasing.
493  */
494 static int spear_mtd_erase(struct mtd_info *mtd, struct erase_info *e_info)
495 {
496         struct spear_snor_flash *flash = get_flash_data(mtd);
497         struct spear_smi *dev = mtd->priv;
498         u32 addr, command, bank;
499         int len, ret;
500 
501         if (!flash || !dev)
502                 return -ENODEV;
503 
504         bank = flash->bank;
505         if (bank > dev->num_flashes - 1) {
506                 dev_err(&dev->pdev->dev, "Invalid Bank Num");
507                 return -EINVAL;
508         }
509 
510         addr = e_info->addr;
511         len = e_info->len;
512 
513         mutex_lock(&flash->lock);
514 
515         /* now erase sectors in loop */
516         while (len) {
517                 command = get_sector_erase_cmd(flash, addr);
518                 /* preparing the command for flash */
519                 ret = spear_smi_erase_sector(dev, bank, command, 4);
520                 if (ret) {
521                         e_info->state = MTD_ERASE_FAILED;
522                         mutex_unlock(&flash->lock);
523                         return ret;
524                 }
525                 addr += mtd->erasesize;
526                 len -= mtd->erasesize;
527         }
528 
529         mutex_unlock(&flash->lock);
530         e_info->state = MTD_ERASE_DONE;
531         mtd_erase_callback(e_info);
532 
533         return 0;
534 }
535 
536 /**
537  * spear_mtd_read - performs flash read operation as requested by the user
538  * @mtd: MTD information of the memory bank
539  * @from: Address from which to start read
540  * @len: Number of bytes to be read
541  * @retlen: Fills the Number of bytes actually read
542  * @buf: Fills this after reading
543  *
544  * Read an address range from the flash chip. The address range
545  * may be any size provided it is within the physical boundaries.
546  * Returns 0 on success, non zero otherwise
547  */
548 static int spear_mtd_read(struct mtd_info *mtd, loff_t from, size_t len,
549                 size_t *retlen, u8 *buf)
550 {
551         struct spear_snor_flash *flash = get_flash_data(mtd);
552         struct spear_smi *dev = mtd->priv;
553         void __iomem *src;
554         u32 ctrlreg1, val;
555         int ret;
556 
557         if (!flash || !dev)
558                 return -ENODEV;
559 
560         if (flash->bank > dev->num_flashes - 1) {
561                 dev_err(&dev->pdev->dev, "Invalid Bank Num");
562                 return -EINVAL;
563         }
564 
565         /* select address as per bank number */
566         src = flash->base_addr + from;
567 
568         mutex_lock(&flash->lock);
569 
570         /* wait till previous write/erase is done. */
571         ret = spear_smi_wait_till_ready(dev, flash->bank, SMI_MAX_TIME_OUT);
572         if (ret) {
573                 mutex_unlock(&flash->lock);
574                 return ret;
575         }
576 
577         mutex_lock(&dev->lock);
578         /* put smi in hw mode not wbt mode */
579         ctrlreg1 = val = readl(dev->io_base + SMI_CR1);
580         val &= ~(SW_MODE | WB_MODE);
581         if (flash->fast_mode)
582                 val |= FAST_MODE;
583 
584         writel(val, dev->io_base + SMI_CR1);
585 
586         memcpy_fromio(buf, src, len);
587 
588         /* restore ctrl reg1 */
589         writel(ctrlreg1, dev->io_base + SMI_CR1);
590         mutex_unlock(&dev->lock);
591 
592         *retlen = len;
593         mutex_unlock(&flash->lock);
594 
595         return 0;
596 }
597 
598 static inline int spear_smi_cpy_toio(struct spear_smi *dev, u32 bank,
599                 void __iomem *dest, const void *src, size_t len)
600 {
601         int ret;
602         u32 ctrlreg1;
603 
604         /* wait until finished previous write command. */
605         ret = spear_smi_wait_till_ready(dev, bank, SMI_MAX_TIME_OUT);
606         if (ret)
607                 return ret;
608 
609         /* put smi in write enable */
610         ret = spear_smi_write_enable(dev, bank);
611         if (ret)
612                 return ret;
613 
614         /* put smi in hw, write burst mode */
615         mutex_lock(&dev->lock);
616 
617         ctrlreg1 = readl(dev->io_base + SMI_CR1);
618         writel((ctrlreg1 | WB_MODE) & ~SW_MODE, dev->io_base + SMI_CR1);
619 
620         memcpy_toio(dest, src, len);
621 
622         writel(ctrlreg1, dev->io_base + SMI_CR1);
623 
624         mutex_unlock(&dev->lock);
625         return 0;
626 }
627 
628 /**
629  * spear_mtd_write - performs write operation as requested by the user.
630  * @mtd: MTD information of the memory bank.
631  * @to: Address to write.
632  * @len: Number of bytes to be written.
633  * @retlen: Number of bytes actually wrote.
634  * @buf: Buffer from which the data to be taken.
635  *
636  * Write an address range to the flash chip. Data must be written in
637  * flash_page_size chunks. The address range may be any size provided
638  * it is within the physical boundaries.
639  * Returns 0 on success, non zero otherwise
640  */
641 static int spear_mtd_write(struct mtd_info *mtd, loff_t to, size_t len,
642                 size_t *retlen, const u8 *buf)
643 {
644         struct spear_snor_flash *flash = get_flash_data(mtd);
645         struct spear_smi *dev = mtd->priv;
646         void __iomem *dest;
647         u32 page_offset, page_size;
648         int ret;
649 
650         if (!flash || !dev)
651                 return -ENODEV;
652 
653         if (flash->bank > dev->num_flashes - 1) {
654                 dev_err(&dev->pdev->dev, "Invalid Bank Num");
655                 return -EINVAL;
656         }
657 
658         /* select address as per bank number */
659         dest = flash->base_addr + to;
660         mutex_lock(&flash->lock);
661 
662         page_offset = (u32)to % flash->page_size;
663 
664         /* do if all the bytes fit onto one page */
665         if (page_offset + len <= flash->page_size) {
666                 ret = spear_smi_cpy_toio(dev, flash->bank, dest, buf, len);
667                 if (!ret)
668                         *retlen += len;
669         } else {
670                 u32 i;
671 
672                 /* the size of data remaining on the first page */
673                 page_size = flash->page_size - page_offset;
674 
675                 ret = spear_smi_cpy_toio(dev, flash->bank, dest, buf,
676                                 page_size);
677                 if (ret)
678                         goto err_write;
679                 else
680                         *retlen += page_size;
681 
682                 /* write everything in pagesize chunks */
683                 for (i = page_size; i < len; i += page_size) {
684                         page_size = len - i;
685                         if (page_size > flash->page_size)
686                                 page_size = flash->page_size;
687 
688                         ret = spear_smi_cpy_toio(dev, flash->bank, dest + i,
689                                         buf + i, page_size);
690                         if (ret)
691                                 break;
692                         else
693                                 *retlen += page_size;
694                 }
695         }
696 
697 err_write:
698         mutex_unlock(&flash->lock);
699 
700         return ret;
701 }
702 
703 /**
704  * spear_smi_probe_flash - Detects the NOR Flash chip.
705  * @dev: structure of SMI information.
706  * @bank: bank on which flash must be probed
707  *
708  * This routine will check whether there exists a flash chip on a given memory
709  * bank ID.
710  * Return index of the probed flash in flash devices structure
711  */
712 static int spear_smi_probe_flash(struct spear_smi *dev, u32 bank)
713 {
714         int ret;
715         u32 val = 0;
716 
717         ret = spear_smi_wait_till_ready(dev, bank, SMI_PROBE_TIMEOUT);
718         if (ret)
719                 return ret;
720 
721         mutex_lock(&dev->lock);
722 
723         dev->status = 0; /* Will be set in interrupt handler */
724         /* put smi in sw mode */
725         val = readl(dev->io_base + SMI_CR1);
726         writel(val | SW_MODE, dev->io_base + SMI_CR1);
727 
728         /* send readid command in sw mode */
729         writel(OPCODE_RDID, dev->io_base + SMI_TR);
730 
731         val = (bank << BANK_SHIFT) | SEND | (1 << TX_LEN_SHIFT) |
732                 (3 << RX_LEN_SHIFT) | TFIE;
733         writel(val, dev->io_base + SMI_CR2);
734 
735         /* wait for TFF */
736         ret = wait_event_interruptible_timeout(dev->cmd_complete,
737                         dev->status & TFF, SMI_CMD_TIMEOUT);
738         if (ret <= 0) {
739                 ret = -ENODEV;
740                 goto err_probe;
741         }
742 
743         /* get memory chip id */
744         val = readl(dev->io_base + SMI_RR);
745         val &= 0x00ffffff;
746         ret = get_flash_index(val);
747 
748 err_probe:
749         /* clear sw mode */
750         val = readl(dev->io_base + SMI_CR1);
751         writel(val & ~SW_MODE, dev->io_base + SMI_CR1);
752 
753         mutex_unlock(&dev->lock);
754         return ret;
755 }
756 
757 
758 #ifdef CONFIG_OF
759 static int spear_smi_probe_config_dt(struct platform_device *pdev,
760                                      struct device_node *np)
761 {
762         struct spear_smi_plat_data *pdata = dev_get_platdata(&pdev->dev);
763         struct device_node *pp = NULL;
764         const __be32 *addr;
765         u32 val;
766         int len;
767         int i = 0;
768 
769         if (!np)
770                 return -ENODEV;
771 
772         of_property_read_u32(np, "clock-rate", &val);
773         pdata->clk_rate = val;
774 
775         pdata->board_flash_info = devm_kzalloc(&pdev->dev,
776                                                sizeof(*pdata->board_flash_info),
777                                                GFP_KERNEL);
778 
779         /* Fill structs for each subnode (flash device) */
780         while ((pp = of_get_next_child(np, pp))) {
781                 struct spear_smi_flash_info *flash_info;
782 
783                 flash_info = &pdata->board_flash_info[i];
784                 pdata->np[i] = pp;
785 
786                 /* Read base-addr and size from DT */
787                 addr = of_get_property(pp, "reg", &len);
788                 pdata->board_flash_info->mem_base = be32_to_cpup(&addr[0]);
789                 pdata->board_flash_info->size = be32_to_cpup(&addr[1]);
790 
791                 if (of_get_property(pp, "st,smi-fast-mode", NULL))
792                         pdata->board_flash_info->fast_mode = 1;
793 
794                 i++;
795         }
796 
797         pdata->num_flashes = i;
798 
799         return 0;
800 }
801 #else
802 static int spear_smi_probe_config_dt(struct platform_device *pdev,
803                                      struct device_node *np)
804 {
805         return -ENOSYS;
806 }
807 #endif
808 
809 static int spear_smi_setup_banks(struct platform_device *pdev,
810                                  u32 bank, struct device_node *np)
811 {
812         struct spear_smi *dev = platform_get_drvdata(pdev);
813         struct mtd_part_parser_data ppdata = {};
814         struct spear_smi_flash_info *flash_info;
815         struct spear_smi_plat_data *pdata;
816         struct spear_snor_flash *flash;
817         struct mtd_partition *parts = NULL;
818         int count = 0;
819         int flash_index;
820         int ret = 0;
821 
822         pdata = dev_get_platdata(&pdev->dev);
823         if (bank > pdata->num_flashes - 1)
824                 return -EINVAL;
825 
826         flash_info = &pdata->board_flash_info[bank];
827         if (!flash_info)
828                 return -ENODEV;
829 
830         flash = devm_kzalloc(&pdev->dev, sizeof(*flash), GFP_ATOMIC);
831         if (!flash)
832                 return -ENOMEM;
833         flash->bank = bank;
834         flash->fast_mode = flash_info->fast_mode ? 1 : 0;
835         mutex_init(&flash->lock);
836 
837         /* verify whether nor flash is really present on board */
838         flash_index = spear_smi_probe_flash(dev, bank);
839         if (flash_index < 0) {
840                 dev_info(&dev->pdev->dev, "smi-nor%d not found\n", bank);
841                 return flash_index;
842         }
843         /* map the memory for nor flash chip */
844         flash->base_addr = devm_ioremap(&pdev->dev, flash_info->mem_base,
845                                         flash_info->size);
846         if (!flash->base_addr)
847                 return -EIO;
848 
849         dev->flash[bank] = flash;
850         flash->mtd.priv = dev;
851 
852         if (flash_info->name)
853                 flash->mtd.name = flash_info->name;
854         else
855                 flash->mtd.name = flash_devices[flash_index].name;
856 
857         flash->mtd.type = MTD_NORFLASH;
858         flash->mtd.writesize = 1;
859         flash->mtd.flags = MTD_CAP_NORFLASH;
860         flash->mtd.size = flash_info->size;
861         flash->mtd.erasesize = flash_devices[flash_index].sectorsize;
862         flash->page_size = flash_devices[flash_index].pagesize;
863         flash->mtd.writebufsize = flash->page_size;
864         flash->erase_cmd = flash_devices[flash_index].erase_cmd;
865         flash->mtd._erase = spear_mtd_erase;
866         flash->mtd._read = spear_mtd_read;
867         flash->mtd._write = spear_mtd_write;
868         flash->dev_id = flash_devices[flash_index].device_id;
869 
870         dev_info(&dev->pdev->dev, "mtd .name=%s .size=%llx(%lluM)\n",
871                         flash->mtd.name, flash->mtd.size,
872                         flash->mtd.size / (1024 * 1024));
873 
874         dev_info(&dev->pdev->dev, ".erasesize = 0x%x(%uK)\n",
875                         flash->mtd.erasesize, flash->mtd.erasesize / 1024);
876 
877 #ifndef CONFIG_OF
878         if (flash_info->partitions) {
879                 parts = flash_info->partitions;
880                 count = flash_info->nr_partitions;
881         }
882 #endif
883         ppdata.of_node = np;
884 
885         ret = mtd_device_parse_register(&flash->mtd, NULL, &ppdata, parts,
886                                         count);
887         if (ret) {
888                 dev_err(&dev->pdev->dev, "Err MTD partition=%d\n", ret);
889                 return ret;
890         }
891 
892         return 0;
893 }
894 
895 /**
896  * spear_smi_probe - Entry routine
897  * @pdev: platform device structure
898  *
899  * This is the first routine which gets invoked during booting and does all
900  * initialization/allocation work. The routine looks for available memory banks,
901  * and do proper init for any found one.
902  * Returns 0 on success, non zero otherwise
903  */
904 static int spear_smi_probe(struct platform_device *pdev)
905 {
906         struct device_node *np = pdev->dev.of_node;
907         struct spear_smi_plat_data *pdata = NULL;
908         struct spear_smi *dev;
909         struct resource *smi_base;
910         int irq, ret = 0;
911         int i;
912 
913         if (np) {
914                 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
915                 if (!pdata) {
916                         ret = -ENOMEM;
917                         goto err;
918                 }
919                 pdev->dev.platform_data = pdata;
920                 ret = spear_smi_probe_config_dt(pdev, np);
921                 if (ret) {
922                         ret = -ENODEV;
923                         dev_err(&pdev->dev, "no platform data\n");
924                         goto err;
925                 }
926         } else {
927                 pdata = dev_get_platdata(&pdev->dev);
928                 if (!pdata) {
929                         ret = -ENODEV;
930                         dev_err(&pdev->dev, "no platform data\n");
931                         goto err;
932                 }
933         }
934 
935         irq = platform_get_irq(pdev, 0);
936         if (irq < 0) {
937                 ret = -ENODEV;
938                 dev_err(&pdev->dev, "invalid smi irq\n");
939                 goto err;
940         }
941 
942         dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_ATOMIC);
943         if (!dev) {
944                 ret = -ENOMEM;
945                 goto err;
946         }
947 
948         smi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
949 
950         dev->io_base = devm_ioremap_resource(&pdev->dev, smi_base);
951         if (IS_ERR(dev->io_base)) {
952                 ret = PTR_ERR(dev->io_base);
953                 goto err;
954         }
955 
956         dev->pdev = pdev;
957         dev->clk_rate = pdata->clk_rate;
958 
959         if (dev->clk_rate > SMI_MAX_CLOCK_FREQ)
960                 dev->clk_rate = SMI_MAX_CLOCK_FREQ;
961 
962         dev->num_flashes = pdata->num_flashes;
963 
964         if (dev->num_flashes > MAX_NUM_FLASH_CHIP) {
965                 dev_err(&pdev->dev, "exceeding max number of flashes\n");
966                 dev->num_flashes = MAX_NUM_FLASH_CHIP;
967         }
968 
969         dev->clk = devm_clk_get(&pdev->dev, NULL);
970         if (IS_ERR(dev->clk)) {
971                 ret = PTR_ERR(dev->clk);
972                 goto err;
973         }
974 
975         ret = clk_prepare_enable(dev->clk);
976         if (ret)
977                 goto err;
978 
979         ret = devm_request_irq(&pdev->dev, irq, spear_smi_int_handler, 0,
980                                pdev->name, dev);
981         if (ret) {
982                 dev_err(&dev->pdev->dev, "SMI IRQ allocation failed\n");
983                 goto err_irq;
984         }
985 
986         mutex_init(&dev->lock);
987         init_waitqueue_head(&dev->cmd_complete);
988         spear_smi_hw_init(dev);
989         platform_set_drvdata(pdev, dev);
990 
991         /* loop for each serial nor-flash which is connected to smi */
992         for (i = 0; i < dev->num_flashes; i++) {
993                 ret = spear_smi_setup_banks(pdev, i, pdata->np[i]);
994                 if (ret) {
995                         dev_err(&dev->pdev->dev, "bank setup failed\n");
996                         goto err_irq;
997                 }
998         }
999 
1000         return 0;
1001 
1002 err_irq:
1003         clk_disable_unprepare(dev->clk);
1004 err:
1005         return ret;
1006 }
1007 
1008 /**
1009  * spear_smi_remove - Exit routine
1010  * @pdev: platform device structure
1011  *
1012  * free all allocations and delete the partitions.
1013  */
1014 static int spear_smi_remove(struct platform_device *pdev)
1015 {
1016         struct spear_smi *dev;
1017         struct spear_snor_flash *flash;
1018         int ret, i;
1019 
1020         dev = platform_get_drvdata(pdev);
1021         if (!dev) {
1022                 dev_err(&pdev->dev, "dev is null\n");
1023                 return -ENODEV;
1024         }
1025 
1026         /* clean up for all nor flash */
1027         for (i = 0; i < dev->num_flashes; i++) {
1028                 flash = dev->flash[i];
1029                 if (!flash)
1030                         continue;
1031 
1032                 /* clean up mtd stuff */
1033                 ret = mtd_device_unregister(&flash->mtd);
1034                 if (ret)
1035                         dev_err(&pdev->dev, "error removing mtd\n");
1036         }
1037 
1038         clk_disable_unprepare(dev->clk);
1039 
1040         return 0;
1041 }
1042 
1043 #ifdef CONFIG_PM_SLEEP
1044 static int spear_smi_suspend(struct device *dev)
1045 {
1046         struct spear_smi *sdev = dev_get_drvdata(dev);
1047 
1048         if (sdev && sdev->clk)
1049                 clk_disable_unprepare(sdev->clk);
1050 
1051         return 0;
1052 }
1053 
1054 static int spear_smi_resume(struct device *dev)
1055 {
1056         struct spear_smi *sdev = dev_get_drvdata(dev);
1057         int ret = -EPERM;
1058 
1059         if (sdev && sdev->clk)
1060                 ret = clk_prepare_enable(sdev->clk);
1061 
1062         if (!ret)
1063                 spear_smi_hw_init(sdev);
1064         return ret;
1065 }
1066 #endif
1067 
1068 static SIMPLE_DEV_PM_OPS(spear_smi_pm_ops, spear_smi_suspend, spear_smi_resume);
1069 
1070 #ifdef CONFIG_OF
1071 static const struct of_device_id spear_smi_id_table[] = {
1072         { .compatible = "st,spear600-smi" },
1073         {}
1074 };
1075 MODULE_DEVICE_TABLE(of, spear_smi_id_table);
1076 #endif
1077 
1078 static struct platform_driver spear_smi_driver = {
1079         .driver = {
1080                 .name = "smi",
1081                 .bus = &platform_bus_type,
1082                 .owner = THIS_MODULE,
1083                 .of_match_table = of_match_ptr(spear_smi_id_table),
1084                 .pm = &spear_smi_pm_ops,
1085         },
1086         .probe = spear_smi_probe,
1087         .remove = spear_smi_remove,
1088 };
1089 module_platform_driver(spear_smi_driver);
1090 
1091 MODULE_LICENSE("GPL");
1092 MODULE_AUTHOR("Ashish Priyadarshi, Shiraz Hashim <shiraz.linux.kernel@gmail.com>");
1093 MODULE_DESCRIPTION("MTD SMI driver for serial nor flash chips");
1094 

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