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Linux/drivers/mmc/host/sh_mobile_sdhi.c

  1 /*
  2  * SuperH Mobile SDHI
  3  *
  4  * Copyright (C) 2016 Sang Engineering, Wolfram Sang
  5  * Copyright (C) 2015-16 Renesas Electronics Corporation
  6  * Copyright (C) 2009 Magnus Damm
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License version 2 as
 10  * published by the Free Software Foundation.
 11  *
 12  * Based on "Compaq ASIC3 support":
 13  *
 14  * Copyright 2001 Compaq Computer Corporation.
 15  * Copyright 2004-2005 Phil Blundell
 16  * Copyright 2007-2008 OpenedHand Ltd.
 17  *
 18  * Authors: Phil Blundell <pb@handhelds.org>,
 19  *          Samuel Ortiz <sameo@openedhand.com>
 20  *
 21  */
 22 
 23 #include <linux/kernel.h>
 24 #include <linux/clk.h>
 25 #include <linux/slab.h>
 26 #include <linux/mod_devicetable.h>
 27 #include <linux/module.h>
 28 #include <linux/of_device.h>
 29 #include <linux/platform_device.h>
 30 #include <linux/mmc/host.h>
 31 #include <linux/mfd/tmio.h>
 32 #include <linux/sh_dma.h>
 33 #include <linux/delay.h>
 34 #include <linux/pinctrl/consumer.h>
 35 #include <linux/pinctrl/pinctrl-state.h>
 36 #include <linux/regulator/consumer.h>
 37 
 38 #include "tmio_mmc.h"
 39 
 40 #define EXT_ACC           0xe4
 41 
 42 #define SDHI_VER_GEN2_SDR50     0x490c
 43 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */
 44 #define SDHI_VER_GEN2_SDR104    0xcb0d
 45 #define SDHI_VER_GEN3_SD        0xcc10
 46 #define SDHI_VER_GEN3_SDMMC     0xcd10
 47 
 48 #define host_to_priv(host) container_of((host)->pdata, struct sh_mobile_sdhi, mmc_data)
 49 
 50 struct sh_mobile_sdhi_scc {
 51         unsigned long clk_rate; /* clock rate for SDR104 */
 52         u32 tap;                /* sampling clock position for SDR104 */
 53 };
 54 
 55 struct sh_mobile_sdhi_of_data {
 56         unsigned long tmio_flags;
 57         u32           tmio_ocr_mask;
 58         unsigned long capabilities;
 59         unsigned long capabilities2;
 60         enum dma_slave_buswidth dma_buswidth;
 61         dma_addr_t dma_rx_offset;
 62         unsigned bus_shift;
 63         int scc_offset;
 64         struct sh_mobile_sdhi_scc *taps;
 65         int taps_num;
 66 };
 67 
 68 static const struct sh_mobile_sdhi_of_data of_default_cfg = {
 69         .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
 70 };
 71 
 72 static const struct sh_mobile_sdhi_of_data of_rz_compatible = {
 73         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_32BIT_DATA_PORT,
 74         .tmio_ocr_mask  = MMC_VDD_32_33,
 75         .capabilities   = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
 76 };
 77 
 78 static const struct sh_mobile_sdhi_of_data of_rcar_gen1_compatible = {
 79         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE |
 80                           TMIO_MMC_CLK_ACTUAL,
 81         .capabilities   = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
 82 };
 83 
 84 /* Definitions for sampling clocks */
 85 static struct sh_mobile_sdhi_scc rcar_gen2_scc_taps[] = {
 86         {
 87                 .clk_rate = 156000000,
 88                 .tap = 0x00000703,
 89         },
 90         {
 91                 .clk_rate = 0,
 92                 .tap = 0x00000300,
 93         },
 94 };
 95 
 96 static const struct sh_mobile_sdhi_of_data of_rcar_gen2_compatible = {
 97         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE |
 98                           TMIO_MMC_CLK_ACTUAL | TMIO_MMC_MIN_RCAR2,
 99         .capabilities   = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
100         .dma_buswidth   = DMA_SLAVE_BUSWIDTH_4_BYTES,
101         .dma_rx_offset  = 0x2000,
102         .scc_offset     = 0x0300,
103         .taps           = rcar_gen2_scc_taps,
104         .taps_num       = ARRAY_SIZE(rcar_gen2_scc_taps),
105 };
106 
107 /* Definitions for sampling clocks */
108 static struct sh_mobile_sdhi_scc rcar_gen3_scc_taps[] = {
109         {
110                 .clk_rate = 0,
111                 .tap = 0x00000300,
112         },
113 };
114 
115 static const struct sh_mobile_sdhi_of_data of_rcar_gen3_compatible = {
116         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE |
117                           TMIO_MMC_CLK_ACTUAL | TMIO_MMC_MIN_RCAR2,
118         .capabilities   = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
119         .bus_shift      = 2,
120         .scc_offset     = 0x1000,
121         .taps           = rcar_gen3_scc_taps,
122         .taps_num       = ARRAY_SIZE(rcar_gen3_scc_taps),
123 };
124 
125 static const struct of_device_id sh_mobile_sdhi_of_match[] = {
126         { .compatible = "renesas,sdhi-shmobile" },
127         { .compatible = "renesas,sdhi-sh73a0", .data = &of_default_cfg, },
128         { .compatible = "renesas,sdhi-r8a73a4", .data = &of_default_cfg, },
129         { .compatible = "renesas,sdhi-r8a7740", .data = &of_default_cfg, },
130         { .compatible = "renesas,sdhi-r7s72100", .data = &of_rz_compatible, },
131         { .compatible = "renesas,sdhi-r8a7778", .data = &of_rcar_gen1_compatible, },
132         { .compatible = "renesas,sdhi-r8a7779", .data = &of_rcar_gen1_compatible, },
133         { .compatible = "renesas,sdhi-r8a7790", .data = &of_rcar_gen2_compatible, },
134         { .compatible = "renesas,sdhi-r8a7791", .data = &of_rcar_gen2_compatible, },
135         { .compatible = "renesas,sdhi-r8a7792", .data = &of_rcar_gen2_compatible, },
136         { .compatible = "renesas,sdhi-r8a7793", .data = &of_rcar_gen2_compatible, },
137         { .compatible = "renesas,sdhi-r8a7794", .data = &of_rcar_gen2_compatible, },
138         { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
139         { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
140         {},
141 };
142 MODULE_DEVICE_TABLE(of, sh_mobile_sdhi_of_match);
143 
144 struct sh_mobile_sdhi {
145         struct clk *clk;
146         struct tmio_mmc_data mmc_data;
147         struct tmio_mmc_dma dma_priv;
148         struct pinctrl *pinctrl;
149         struct pinctrl_state *pins_default, *pins_uhs;
150         void __iomem *scc_ctl;
151 };
152 
153 static void sh_mobile_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
154 {
155         u32 val;
156 
157         /*
158          * see also
159          *      sh_mobile_sdhi_of_data :: dma_buswidth
160          */
161         switch (sd_ctrl_read16(host, CTL_VERSION)) {
162         case SDHI_VER_GEN2_SDR50:
163                 val = (width == 32) ? 0x0001 : 0x0000;
164                 break;
165         case SDHI_VER_GEN2_SDR104:
166                 val = (width == 32) ? 0x0000 : 0x0001;
167                 break;
168         case SDHI_VER_GEN3_SD:
169         case SDHI_VER_GEN3_SDMMC:
170                 if (width == 64)
171                         val = 0x0000;
172                 else if (width == 32)
173                         val = 0x0101;
174                 else
175                         val = 0x0001;
176                 break;
177         default:
178                 /* nothing to do */
179                 return;
180         }
181 
182         sd_ctrl_write16(host, EXT_ACC, val);
183 }
184 
185 static int sh_mobile_sdhi_clk_enable(struct tmio_mmc_host *host)
186 {
187         struct mmc_host *mmc = host->mmc;
188         struct sh_mobile_sdhi *priv = host_to_priv(host);
189         int ret = clk_prepare_enable(priv->clk);
190         if (ret < 0)
191                 return ret;
192 
193         /*
194          * The clock driver may not know what maximum frequency
195          * actually works, so it should be set with the max-frequency
196          * property which will already have been read to f_max.  If it
197          * was missing, assume the current frequency is the maximum.
198          */
199         if (!mmc->f_max)
200                 mmc->f_max = clk_get_rate(priv->clk);
201 
202         /*
203          * Minimum frequency is the minimum input clock frequency
204          * divided by our maximum divider.
205          */
206         mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
207 
208         /* enable 16bit data access on SDBUF as default */
209         sh_mobile_sdhi_sdbuf_width(host, 16);
210 
211         return 0;
212 }
213 
214 static unsigned int sh_mobile_sdhi_clk_update(struct tmio_mmc_host *host,
215                                               unsigned int new_clock)
216 {
217         struct sh_mobile_sdhi *priv = host_to_priv(host);
218         unsigned int freq, diff, best_freq = 0, diff_min = ~0;
219         int i, ret;
220 
221         /* tested only on RCar Gen2+ currently; may work for others */
222         if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
223                 return clk_get_rate(priv->clk);
224 
225         /*
226          * We want the bus clock to be as close as possible to, but no
227          * greater than, new_clock.  As we can divide by 1 << i for
228          * any i in [0, 9] we want the input clock to be as close as
229          * possible, but no greater than, new_clock << i.
230          */
231         for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
232                 freq = clk_round_rate(priv->clk, new_clock << i);
233                 if (freq > (new_clock << i)) {
234                         /* Too fast; look for a slightly slower option */
235                         freq = clk_round_rate(priv->clk,
236                                               (new_clock << i) / 4 * 3);
237                         if (freq > (new_clock << i))
238                                 continue;
239                 }
240 
241                 diff = new_clock - (freq >> i);
242                 if (diff <= diff_min) {
243                         best_freq = freq;
244                         diff_min = diff;
245                 }
246         }
247 
248         ret = clk_set_rate(priv->clk, best_freq);
249 
250         return ret == 0 ? best_freq : clk_get_rate(priv->clk);
251 }
252 
253 static void sh_mobile_sdhi_clk_disable(struct tmio_mmc_host *host)
254 {
255         struct sh_mobile_sdhi *priv = host_to_priv(host);
256 
257         clk_disable_unprepare(priv->clk);
258 }
259 
260 static int sh_mobile_sdhi_card_busy(struct mmc_host *mmc)
261 {
262         struct tmio_mmc_host *host = mmc_priv(mmc);
263 
264         return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & TMIO_STAT_DAT0);
265 }
266 
267 static int sh_mobile_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
268                                                       struct mmc_ios *ios)
269 {
270         struct tmio_mmc_host *host = mmc_priv(mmc);
271         struct sh_mobile_sdhi *priv = host_to_priv(host);
272         struct pinctrl_state *pin_state;
273         int ret;
274 
275         switch (ios->signal_voltage) {
276         case MMC_SIGNAL_VOLTAGE_330:
277                 pin_state = priv->pins_default;
278                 break;
279         case MMC_SIGNAL_VOLTAGE_180:
280                 pin_state = priv->pins_uhs;
281                 break;
282         default:
283                 return -EINVAL;
284         }
285 
286         /*
287          * If anything is missing, assume signal voltage is fixed at
288          * 3.3V and succeed/fail accordingly.
289          */
290         if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
291                 return ios->signal_voltage ==
292                         MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
293 
294         ret = mmc_regulator_set_vqmmc(host->mmc, ios);
295         if (ret)
296                 return ret;
297 
298         return pinctrl_select_state(priv->pinctrl, pin_state);
299 }
300 
301 /* SCC registers */
302 #define SH_MOBILE_SDHI_SCC_DTCNTL       0x000
303 #define SH_MOBILE_SDHI_SCC_TAPSET       0x002
304 #define SH_MOBILE_SDHI_SCC_DT2FF        0x004
305 #define SH_MOBILE_SDHI_SCC_CKSEL        0x006
306 #define SH_MOBILE_SDHI_SCC_RVSCNTL      0x008
307 #define SH_MOBILE_SDHI_SCC_RVSREQ       0x00A
308 
309 /* Definitions for values the SH_MOBILE_SDHI_SCC_DTCNTL register */
310 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN         BIT(0)
311 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT  16
312 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK   0xff
313 
314 /* Definitions for values the SH_MOBILE_SDHI_SCC_CKSEL register */
315 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL          BIT(0)
316 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSCNTL register */
317 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN        BIT(0)
318 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSREQ register */
319 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR        BIT(2)
320 
321 static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
322                                 struct sh_mobile_sdhi *priv, int addr)
323 {
324         return readl(priv->scc_ctl + (addr << host->bus_shift));
325 }
326 
327 static inline void sd_scc_write32(struct tmio_mmc_host *host,
328                                   struct sh_mobile_sdhi *priv,
329                                   int addr, u32 val)
330 {
331         writel(val, priv->scc_ctl + (addr << host->bus_shift));
332 }
333 
334 static unsigned int sh_mobile_sdhi_init_tuning(struct tmio_mmc_host *host)
335 {
336         struct sh_mobile_sdhi *priv;
337 
338         if (!(host->mmc->caps & MMC_CAP_UHS_SDR104))
339                 return 0;
340 
341         priv = host_to_priv(host);
342 
343         /* set sampling clock selection range */
344         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
345                        0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
346 
347         /* Initialize SCC */
348         sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
349 
350         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
351                        SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
352                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL));
353 
354         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
355                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
356 
357         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
358                        SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
359                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
360 
361         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
362                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
363 
364         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
365                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
366                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
367 
368         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, host->scc_tappos);
369 
370         /* Read TAPNUM */
371         return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
372                 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
373                 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
374 }
375 
376 static void sh_mobile_sdhi_prepare_tuning(struct tmio_mmc_host *host,
377                                          unsigned long tap)
378 {
379         struct sh_mobile_sdhi *priv = host_to_priv(host);
380 
381         /* Set sampling clock position */
382         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap);
383 }
384 
385 #define SH_MOBILE_SDHI_MAX_TAP 3
386 
387 static int sh_mobile_sdhi_select_tuning(struct tmio_mmc_host *host)
388 {
389         struct sh_mobile_sdhi *priv = host_to_priv(host);
390         unsigned long tap_cnt;  /* counter of tuning success */
391         unsigned long tap_set;  /* tap position */
392         unsigned long tap_start;/* start position of tuning success */
393         unsigned long tap_end;  /* end position of tuning success */
394         unsigned long ntap;     /* temporary counter of tuning success */
395         unsigned long i;
396 
397         /* Clear SCC_RVSREQ */
398         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
399 
400         /*
401          * Find the longest consecutive run of successful probes.  If that
402          * is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the
403          * center index as the tap.
404          */
405         tap_cnt = 0;
406         ntap = 0;
407         tap_start = 0;
408         tap_end = 0;
409         for (i = 0; i < host->tap_num * 2; i++) {
410                 if (test_bit(i, host->taps))
411                         ntap++;
412                 else {
413                         if (ntap > tap_cnt) {
414                                 tap_start = i - ntap;
415                                 tap_end = i - 1;
416                                 tap_cnt = ntap;
417                         }
418                         ntap = 0;
419                 }
420         }
421 
422         if (ntap > tap_cnt) {
423                 tap_start = i - ntap;
424                 tap_end = i - 1;
425                 tap_cnt = ntap;
426         }
427 
428         if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP)
429                 tap_set = (tap_start + tap_end) / 2 % host->tap_num;
430         else
431                 return -EIO;
432 
433         /* Set SCC */
434         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap_set);
435 
436         /* Enable auto re-tuning */
437         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
438                        SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
439                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
440 
441         return 0;
442 }
443 
444 
445 static bool sh_mobile_sdhi_check_scc_error(struct tmio_mmc_host *host)
446 {
447         struct sh_mobile_sdhi *priv;
448 
449         if (!(host->mmc->caps & MMC_CAP_UHS_SDR104))
450                 return 0;
451 
452         priv = host_to_priv(host);
453 
454         /* Check SCC error */
455         if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
456             SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &&
457             sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
458             SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
459                 /* Clear SCC error */
460                 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
461                 return true;
462         }
463 
464         return false;
465 }
466 
467 static void sh_mobile_sdhi_hw_reset(struct tmio_mmc_host *host)
468 {
469         struct sh_mobile_sdhi *priv;
470 
471         if (!(host->mmc->caps & MMC_CAP_UHS_SDR104))
472                 return;
473 
474         priv = host_to_priv(host);
475 
476         /* Reset SCC */
477         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
478                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
479 
480         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
481                        ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
482                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
483 
484         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
485                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
486 
487         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
488                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
489                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
490 
491         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
492                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
493                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
494 }
495 
496 static int sh_mobile_sdhi_wait_idle(struct tmio_mmc_host *host)
497 {
498         int timeout = 1000;
499 
500         while (--timeout && !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
501                               & TMIO_STAT_SCLKDIVEN))
502                 udelay(1);
503 
504         if (!timeout) {
505                 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
506                 return -EBUSY;
507         }
508 
509         return 0;
510 }
511 
512 static int sh_mobile_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
513 {
514         switch (addr)
515         {
516         case CTL_SD_CMD:
517         case CTL_STOP_INTERNAL_ACTION:
518         case CTL_XFER_BLK_COUNT:
519         case CTL_SD_CARD_CLK_CTL:
520         case CTL_SD_XFER_LEN:
521         case CTL_SD_MEM_CARD_OPT:
522         case CTL_TRANSACTION_CTL:
523         case CTL_DMA_ENABLE:
524         case EXT_ACC:
525                 return sh_mobile_sdhi_wait_idle(host);
526         }
527 
528         return 0;
529 }
530 
531 static int sh_mobile_sdhi_multi_io_quirk(struct mmc_card *card,
532                                          unsigned int direction, int blk_size)
533 {
534         /*
535          * In Renesas controllers, when performing a
536          * multiple block read of one or two blocks,
537          * depending on the timing with which the
538          * response register is read, the response
539          * value may not be read properly.
540          * Use single block read for this HW bug
541          */
542         if ((direction == MMC_DATA_READ) &&
543             blk_size == 2)
544                 return 1;
545 
546         return blk_size;
547 }
548 
549 static void sh_mobile_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
550 {
551         sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? 2 : 0);
552 
553         /* enable 32bit access if DMA mode if possibile */
554         sh_mobile_sdhi_sdbuf_width(host, enable ? 32 : 16);
555 }
556 
557 static int sh_mobile_sdhi_probe(struct platform_device *pdev)
558 {
559         const struct of_device_id *of_id =
560                 of_match_device(sh_mobile_sdhi_of_match, &pdev->dev);
561         struct sh_mobile_sdhi *priv;
562         struct tmio_mmc_data *mmc_data;
563         struct tmio_mmc_data *mmd = pdev->dev.platform_data;
564         struct tmio_mmc_host *host;
565         struct resource *res;
566         int irq, ret, i;
567         struct tmio_mmc_dma *dma_priv;
568 
569         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
570         if (!res)
571                 return -EINVAL;
572 
573         priv = devm_kzalloc(&pdev->dev, sizeof(struct sh_mobile_sdhi), GFP_KERNEL);
574         if (!priv)
575                 return -ENOMEM;
576 
577         mmc_data = &priv->mmc_data;
578         dma_priv = &priv->dma_priv;
579 
580         priv->clk = devm_clk_get(&pdev->dev, NULL);
581         if (IS_ERR(priv->clk)) {
582                 ret = PTR_ERR(priv->clk);
583                 dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
584                 goto eprobe;
585         }
586 
587         priv->pinctrl = devm_pinctrl_get(&pdev->dev);
588         if (!IS_ERR(priv->pinctrl)) {
589                 priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
590                                                 PINCTRL_STATE_DEFAULT);
591                 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
592                                                 "state_uhs");
593         }
594 
595         host = tmio_mmc_host_alloc(pdev);
596         if (!host) {
597                 ret = -ENOMEM;
598                 goto eprobe;
599         }
600 
601         if (of_id && of_id->data) {
602                 const struct sh_mobile_sdhi_of_data *of_data = of_id->data;
603 
604                 mmc_data->flags |= of_data->tmio_flags;
605                 mmc_data->ocr_mask = of_data->tmio_ocr_mask;
606                 mmc_data->capabilities |= of_data->capabilities;
607                 mmc_data->capabilities2 |= of_data->capabilities2;
608                 mmc_data->dma_rx_offset = of_data->dma_rx_offset;
609                 dma_priv->dma_buswidth = of_data->dma_buswidth;
610                 host->bus_shift = of_data->bus_shift;
611         }
612 
613         host->dma               = dma_priv;
614         host->write16_hook      = sh_mobile_sdhi_write16_hook;
615         host->clk_enable        = sh_mobile_sdhi_clk_enable;
616         host->clk_update        = sh_mobile_sdhi_clk_update;
617         host->clk_disable       = sh_mobile_sdhi_clk_disable;
618         host->multi_io_quirk    = sh_mobile_sdhi_multi_io_quirk;
619 
620         /* SDR speeds are only available on Gen2+ */
621         if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
622                 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
623                 host->card_busy = sh_mobile_sdhi_card_busy;
624                 host->start_signal_voltage_switch =
625                         sh_mobile_sdhi_start_signal_voltage_switch;
626                 host->init_tuning       = sh_mobile_sdhi_init_tuning;
627                 host->prepare_tuning    = sh_mobile_sdhi_prepare_tuning;
628                 host->select_tuning     = sh_mobile_sdhi_select_tuning;
629                 host->check_scc_error   = sh_mobile_sdhi_check_scc_error;
630                 host->hw_reset          = sh_mobile_sdhi_hw_reset;
631         }
632 
633         /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
634         if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
635                 host->bus_shift = 1;
636 
637         if (mmd)
638                 *mmc_data = *mmd;
639 
640         dma_priv->filter = shdma_chan_filter;
641         dma_priv->enable = sh_mobile_sdhi_enable_dma;
642 
643         mmc_data->alignment_shift = 1; /* 2-byte alignment */
644         mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
645 
646         /*
647          * All SDHI blocks support 2-byte and larger block sizes in 4-bit
648          * bus width mode.
649          */
650         mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
651 
652         /*
653          * All SDHI blocks support SDIO IRQ signalling.
654          */
655         mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
656 
657         /*
658          * All SDHI have CMD12 controll bit
659          */
660         mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
661 
662         /*
663          * All SDHI need SDIO_INFO1 reserved bit
664          */
665         mmc_data->flags |= TMIO_MMC_SDIO_STATUS_QUIRK;
666 
667         ret = tmio_mmc_host_probe(host, mmc_data);
668         if (ret < 0)
669                 goto efree;
670 
671         if (host->mmc->caps & MMC_CAP_UHS_SDR104) {
672                 host->mmc->caps |= MMC_CAP_HW_RESET;
673 
674                 if (of_id && of_id->data) {
675                         const struct sh_mobile_sdhi_of_data *of_data;
676                         const struct sh_mobile_sdhi_scc *taps;
677                         bool hit = false;
678 
679                         of_data = of_id->data;
680                         taps = of_data->taps;
681 
682                         for (i = 0; i < of_data->taps_num; i++) {
683                                 if (taps[i].clk_rate == 0 ||
684                                     taps[i].clk_rate == host->mmc->f_max) {
685                                         host->scc_tappos = taps->tap;
686                                         hit = true;
687                                         break;
688                                 }
689                         }
690 
691                         if (!hit)
692                                 dev_warn(&host->pdev->dev, "Unknown clock rate for SDR104\n");
693 
694                         priv->scc_ctl = host->ctl + of_data->scc_offset;
695                 }
696         }
697 
698         i = 0;
699         while (1) {
700                 irq = platform_get_irq(pdev, i);
701                 if (irq < 0)
702                         break;
703                 i++;
704                 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
705                                   dev_name(&pdev->dev), host);
706                 if (ret)
707                         goto eirq;
708         }
709 
710         /* There must be at least one IRQ source */
711         if (!i) {
712                 ret = irq;
713                 goto eirq;
714         }
715 
716         dev_info(&pdev->dev, "%s base at 0x%08lx max clock rate %u MHz\n",
717                  mmc_hostname(host->mmc), (unsigned long)
718                  (platform_get_resource(pdev, IORESOURCE_MEM, 0)->start),
719                  host->mmc->f_max / 1000000);
720 
721         return ret;
722 
723 eirq:
724         tmio_mmc_host_remove(host);
725 efree:
726         tmio_mmc_host_free(host);
727 eprobe:
728         return ret;
729 }
730 
731 static int sh_mobile_sdhi_remove(struct platform_device *pdev)
732 {
733         struct mmc_host *mmc = platform_get_drvdata(pdev);
734         struct tmio_mmc_host *host = mmc_priv(mmc);
735 
736         tmio_mmc_host_remove(host);
737 
738         return 0;
739 }
740 
741 static const struct dev_pm_ops tmio_mmc_dev_pm_ops = {
742         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
743                         pm_runtime_force_resume)
744         SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
745                         tmio_mmc_host_runtime_resume,
746                         NULL)
747 };
748 
749 static struct platform_driver sh_mobile_sdhi_driver = {
750         .driver         = {
751                 .name   = "sh_mobile_sdhi",
752                 .pm     = &tmio_mmc_dev_pm_ops,
753                 .of_match_table = sh_mobile_sdhi_of_match,
754         },
755         .probe          = sh_mobile_sdhi_probe,
756         .remove         = sh_mobile_sdhi_remove,
757 };
758 
759 module_platform_driver(sh_mobile_sdhi_driver);
760 
761 MODULE_DESCRIPTION("SuperH Mobile SDHI driver");
762 MODULE_AUTHOR("Magnus Damm");
763 MODULE_LICENSE("GPL v2");
764 MODULE_ALIAS("platform:sh_mobile_sdhi");
765 

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