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Linux/drivers/mmc/host/sh_mmcif.c

  1 /*
  2  * MMCIF eMMC driver.
  3  *
  4  * Copyright (C) 2010 Renesas Solutions Corp.
  5  * Yusuke Goda <yusuke.goda.sx@renesas.com>
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License as published by
  9  * the Free Software Foundation; either version 2 of the License.
 10  *
 11  *
 12  * TODO
 13  *  1. DMA
 14  *  2. Power management
 15  *  3. Handle MMC errors better
 16  *
 17  */
 18 
 19 /*
 20  * The MMCIF driver is now processing MMC requests asynchronously, according
 21  * to the Linux MMC API requirement.
 22  *
 23  * The MMCIF driver processes MMC requests in up to 3 stages: command, optional
 24  * data, and optional stop. To achieve asynchronous processing each of these
 25  * stages is split into two halves: a top and a bottom half. The top half
 26  * initialises the hardware, installs a timeout handler to handle completion
 27  * timeouts, and returns. In case of the command stage this immediately returns
 28  * control to the caller, leaving all further processing to run asynchronously.
 29  * All further request processing is performed by the bottom halves.
 30  *
 31  * The bottom half further consists of a "hard" IRQ handler, an IRQ handler
 32  * thread, a DMA completion callback, if DMA is used, a timeout work, and
 33  * request- and stage-specific handler methods.
 34  *
 35  * Each bottom half run begins with either a hardware interrupt, a DMA callback
 36  * invocation, or a timeout work run. In case of an error or a successful
 37  * processing completion, the MMC core is informed and the request processing is
 38  * finished. In case processing has to continue, i.e., if data has to be read
 39  * from or written to the card, or if a stop command has to be sent, the next
 40  * top half is called, which performs the necessary hardware handling and
 41  * reschedules the timeout work. This returns the driver state machine into the
 42  * bottom half waiting state.
 43  */
 44 
 45 #include <linux/bitops.h>
 46 #include <linux/clk.h>
 47 #include <linux/completion.h>
 48 #include <linux/delay.h>
 49 #include <linux/dma-mapping.h>
 50 #include <linux/dmaengine.h>
 51 #include <linux/mmc/card.h>
 52 #include <linux/mmc/core.h>
 53 #include <linux/mmc/host.h>
 54 #include <linux/mmc/mmc.h>
 55 #include <linux/mmc/sdio.h>
 56 #include <linux/mmc/sh_mmcif.h>
 57 #include <linux/mmc/slot-gpio.h>
 58 #include <linux/mod_devicetable.h>
 59 #include <linux/mutex.h>
 60 #include <linux/of_device.h>
 61 #include <linux/pagemap.h>
 62 #include <linux/platform_device.h>
 63 #include <linux/pm_qos.h>
 64 #include <linux/pm_runtime.h>
 65 #include <linux/sh_dma.h>
 66 #include <linux/spinlock.h>
 67 #include <linux/module.h>
 68 
 69 #define DRIVER_NAME     "sh_mmcif"
 70 #define DRIVER_VERSION  "2010-04-28"
 71 
 72 /* CE_CMD_SET */
 73 #define CMD_MASK                0x3f000000
 74 #define CMD_SET_RTYP_NO         ((0 << 23) | (0 << 22))
 75 #define CMD_SET_RTYP_6B         ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
 76 #define CMD_SET_RTYP_17B        ((1 << 23) | (0 << 22)) /* R2 */
 77 #define CMD_SET_RBSY            (1 << 21) /* R1b */
 78 #define CMD_SET_CCSEN           (1 << 20)
 79 #define CMD_SET_WDAT            (1 << 19) /* 1: on data, 0: no data */
 80 #define CMD_SET_DWEN            (1 << 18) /* 1: write, 0: read */
 81 #define CMD_SET_CMLTE           (1 << 17) /* 1: multi block trans, 0: single */
 82 #define CMD_SET_CMD12EN         (1 << 16) /* 1: CMD12 auto issue */
 83 #define CMD_SET_RIDXC_INDEX     ((0 << 15) | (0 << 14)) /* index check */
 84 #define CMD_SET_RIDXC_BITS      ((0 << 15) | (1 << 14)) /* check bits check */
 85 #define CMD_SET_RIDXC_NO        ((1 << 15) | (0 << 14)) /* no check */
 86 #define CMD_SET_CRC7C           ((0 << 13) | (0 << 12)) /* CRC7 check*/
 87 #define CMD_SET_CRC7C_BITS      ((0 << 13) | (1 << 12)) /* check bits check*/
 88 #define CMD_SET_CRC7C_INTERNAL  ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
 89 #define CMD_SET_CRC16C          (1 << 10) /* 0: CRC16 check*/
 90 #define CMD_SET_CRCSTE          (1 << 8) /* 1: not receive CRC status */
 91 #define CMD_SET_TBIT            (1 << 7) /* 1: tran mission bit "Low" */
 92 #define CMD_SET_OPDM            (1 << 6) /* 1: open/drain */
 93 #define CMD_SET_CCSH            (1 << 5)
 94 #define CMD_SET_DARS            (1 << 2) /* Dual Data Rate */
 95 #define CMD_SET_DATW_1          ((0 << 1) | (0 << 0)) /* 1bit */
 96 #define CMD_SET_DATW_4          ((0 << 1) | (1 << 0)) /* 4bit */
 97 #define CMD_SET_DATW_8          ((1 << 1) | (0 << 0)) /* 8bit */
 98 
 99 /* CE_CMD_CTRL */
100 #define CMD_CTRL_BREAK          (1 << 0)
101 
102 /* CE_BLOCK_SET */
103 #define BLOCK_SIZE_MASK         0x0000ffff
104 
105 /* CE_INT */
106 #define INT_CCSDE               (1 << 29)
107 #define INT_CMD12DRE            (1 << 26)
108 #define INT_CMD12RBE            (1 << 25)
109 #define INT_CMD12CRE            (1 << 24)
110 #define INT_DTRANE              (1 << 23)
111 #define INT_BUFRE               (1 << 22)
112 #define INT_BUFWEN              (1 << 21)
113 #define INT_BUFREN              (1 << 20)
114 #define INT_CCSRCV              (1 << 19)
115 #define INT_RBSYE               (1 << 17)
116 #define INT_CRSPE               (1 << 16)
117 #define INT_CMDVIO              (1 << 15)
118 #define INT_BUFVIO              (1 << 14)
119 #define INT_WDATERR             (1 << 11)
120 #define INT_RDATERR             (1 << 10)
121 #define INT_RIDXERR             (1 << 9)
122 #define INT_RSPERR              (1 << 8)
123 #define INT_CCSTO               (1 << 5)
124 #define INT_CRCSTO              (1 << 4)
125 #define INT_WDATTO              (1 << 3)
126 #define INT_RDATTO              (1 << 2)
127 #define INT_RBSYTO              (1 << 1)
128 #define INT_RSPTO               (1 << 0)
129 #define INT_ERR_STS             (INT_CMDVIO | INT_BUFVIO | INT_WDATERR |  \
130                                  INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
131                                  INT_CCSTO | INT_CRCSTO | INT_WDATTO |    \
132                                  INT_RDATTO | INT_RBSYTO | INT_RSPTO)
133 
134 #define INT_ALL                 (INT_RBSYE | INT_CRSPE | INT_BUFREN |    \
135                                  INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \
136                                  INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE)
137 
138 #define INT_CCS                 (INT_CCSTO | INT_CCSRCV | INT_CCSDE)
139 
140 /* CE_INT_MASK */
141 #define MASK_ALL                0x00000000
142 #define MASK_MCCSDE             (1 << 29)
143 #define MASK_MCMD12DRE          (1 << 26)
144 #define MASK_MCMD12RBE          (1 << 25)
145 #define MASK_MCMD12CRE          (1 << 24)
146 #define MASK_MDTRANE            (1 << 23)
147 #define MASK_MBUFRE             (1 << 22)
148 #define MASK_MBUFWEN            (1 << 21)
149 #define MASK_MBUFREN            (1 << 20)
150 #define MASK_MCCSRCV            (1 << 19)
151 #define MASK_MRBSYE             (1 << 17)
152 #define MASK_MCRSPE             (1 << 16)
153 #define MASK_MCMDVIO            (1 << 15)
154 #define MASK_MBUFVIO            (1 << 14)
155 #define MASK_MWDATERR           (1 << 11)
156 #define MASK_MRDATERR           (1 << 10)
157 #define MASK_MRIDXERR           (1 << 9)
158 #define MASK_MRSPERR            (1 << 8)
159 #define MASK_MCCSTO             (1 << 5)
160 #define MASK_MCRCSTO            (1 << 4)
161 #define MASK_MWDATTO            (1 << 3)
162 #define MASK_MRDATTO            (1 << 2)
163 #define MASK_MRBSYTO            (1 << 1)
164 #define MASK_MRSPTO             (1 << 0)
165 
166 #define MASK_START_CMD          (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \
167                                  MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \
168                                  MASK_MCRCSTO | MASK_MWDATTO | \
169                                  MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO)
170 
171 #define MASK_CLEAN              (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE |      \
172                                  MASK_MBUFREN | MASK_MBUFWEN |                  \
173                                  MASK_MCMD12DRE | MASK_MBUFRE | MASK_MDTRANE |  \
174                                  MASK_MCMD12RBE | MASK_MCMD12CRE)
175 
176 /* CE_HOST_STS1 */
177 #define STS1_CMDSEQ             (1 << 31)
178 
179 /* CE_HOST_STS2 */
180 #define STS2_CRCSTE             (1 << 31)
181 #define STS2_CRC16E             (1 << 30)
182 #define STS2_AC12CRCE           (1 << 29)
183 #define STS2_RSPCRC7E           (1 << 28)
184 #define STS2_CRCSTEBE           (1 << 27)
185 #define STS2_RDATEBE            (1 << 26)
186 #define STS2_AC12REBE           (1 << 25)
187 #define STS2_RSPEBE             (1 << 24)
188 #define STS2_AC12IDXE           (1 << 23)
189 #define STS2_RSPIDXE            (1 << 22)
190 #define STS2_CCSTO              (1 << 15)
191 #define STS2_RDATTO             (1 << 14)
192 #define STS2_DATBSYTO           (1 << 13)
193 #define STS2_CRCSTTO            (1 << 12)
194 #define STS2_AC12BSYTO          (1 << 11)
195 #define STS2_RSPBSYTO           (1 << 10)
196 #define STS2_AC12RSPTO          (1 << 9)
197 #define STS2_RSPTO              (1 << 8)
198 #define STS2_CRC_ERR            (STS2_CRCSTE | STS2_CRC16E |            \
199                                  STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
200 #define STS2_TIMEOUT_ERR        (STS2_CCSTO | STS2_RDATTO |             \
201                                  STS2_DATBSYTO | STS2_CRCSTTO |         \
202                                  STS2_AC12BSYTO | STS2_RSPBSYTO |       \
203                                  STS2_AC12RSPTO | STS2_RSPTO)
204 
205 #define CLKDEV_EMMC_DATA        52000000 /* 52MHz */
206 #define CLKDEV_MMC_DATA         20000000 /* 20MHz */
207 #define CLKDEV_INIT             400000   /* 400 KHz */
208 
209 enum sh_mmcif_state {
210         STATE_IDLE,
211         STATE_REQUEST,
212         STATE_IOS,
213         STATE_TIMEOUT,
214 };
215 
216 enum sh_mmcif_wait_for {
217         MMCIF_WAIT_FOR_REQUEST,
218         MMCIF_WAIT_FOR_CMD,
219         MMCIF_WAIT_FOR_MREAD,
220         MMCIF_WAIT_FOR_MWRITE,
221         MMCIF_WAIT_FOR_READ,
222         MMCIF_WAIT_FOR_WRITE,
223         MMCIF_WAIT_FOR_READ_END,
224         MMCIF_WAIT_FOR_WRITE_END,
225         MMCIF_WAIT_FOR_STOP,
226 };
227 
228 /*
229  * difference for each SoC
230  */
231 struct sh_mmcif_host {
232         struct mmc_host *mmc;
233         struct mmc_request *mrq;
234         struct platform_device *pd;
235         struct clk *clk;
236         int bus_width;
237         unsigned char timing;
238         bool sd_error;
239         bool dying;
240         long timeout;
241         void __iomem *addr;
242         u32 *pio_ptr;
243         spinlock_t lock;                /* protect sh_mmcif_host::state */
244         enum sh_mmcif_state state;
245         enum sh_mmcif_wait_for wait_for;
246         struct delayed_work timeout_work;
247         size_t blocksize;
248         int sg_idx;
249         int sg_blkidx;
250         bool power;
251         bool ccs_enable;                /* Command Completion Signal support */
252         bool clk_ctrl2_enable;
253         struct mutex thread_lock;
254         u32 clkdiv_map;         /* see CE_CLK_CTRL::CLKDIV */
255 
256         /* DMA support */
257         struct dma_chan         *chan_rx;
258         struct dma_chan         *chan_tx;
259         struct completion       dma_complete;
260         bool                    dma_active;
261 };
262 
263 static const struct of_device_id sh_mmcif_of_match[] = {
264         { .compatible = "renesas,sh-mmcif" },
265         { }
266 };
267 MODULE_DEVICE_TABLE(of, sh_mmcif_of_match);
268 
269 #define sh_mmcif_host_to_dev(host) (&host->pd->dev)
270 
271 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
272                                         unsigned int reg, u32 val)
273 {
274         writel(val | readl(host->addr + reg), host->addr + reg);
275 }
276 
277 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
278                                         unsigned int reg, u32 val)
279 {
280         writel(~val & readl(host->addr + reg), host->addr + reg);
281 }
282 
283 static void sh_mmcif_dma_complete(void *arg)
284 {
285         struct sh_mmcif_host *host = arg;
286         struct mmc_request *mrq = host->mrq;
287         struct device *dev = sh_mmcif_host_to_dev(host);
288 
289         dev_dbg(dev, "Command completed\n");
290 
291         if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n",
292                  dev_name(dev)))
293                 return;
294 
295         complete(&host->dma_complete);
296 }
297 
298 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
299 {
300         struct mmc_data *data = host->mrq->data;
301         struct scatterlist *sg = data->sg;
302         struct dma_async_tx_descriptor *desc = NULL;
303         struct dma_chan *chan = host->chan_rx;
304         struct device *dev = sh_mmcif_host_to_dev(host);
305         dma_cookie_t cookie = -EINVAL;
306         int ret;
307 
308         ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
309                          DMA_FROM_DEVICE);
310         if (ret > 0) {
311                 host->dma_active = true;
312                 desc = dmaengine_prep_slave_sg(chan, sg, ret,
313                         DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
314         }
315 
316         if (desc) {
317                 desc->callback = sh_mmcif_dma_complete;
318                 desc->callback_param = host;
319                 cookie = dmaengine_submit(desc);
320                 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
321                 dma_async_issue_pending(chan);
322         }
323         dev_dbg(dev, "%s(): mapped %d -> %d, cookie %d\n",
324                 __func__, data->sg_len, ret, cookie);
325 
326         if (!desc) {
327                 /* DMA failed, fall back to PIO */
328                 if (ret >= 0)
329                         ret = -EIO;
330                 host->chan_rx = NULL;
331                 host->dma_active = false;
332                 dma_release_channel(chan);
333                 /* Free the Tx channel too */
334                 chan = host->chan_tx;
335                 if (chan) {
336                         host->chan_tx = NULL;
337                         dma_release_channel(chan);
338                 }
339                 dev_warn(dev,
340                          "DMA failed: %d, falling back to PIO\n", ret);
341                 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
342         }
343 
344         dev_dbg(dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
345                 desc, cookie, data->sg_len);
346 }
347 
348 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
349 {
350         struct mmc_data *data = host->mrq->data;
351         struct scatterlist *sg = data->sg;
352         struct dma_async_tx_descriptor *desc = NULL;
353         struct dma_chan *chan = host->chan_tx;
354         struct device *dev = sh_mmcif_host_to_dev(host);
355         dma_cookie_t cookie = -EINVAL;
356         int ret;
357 
358         ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
359                          DMA_TO_DEVICE);
360         if (ret > 0) {
361                 host->dma_active = true;
362                 desc = dmaengine_prep_slave_sg(chan, sg, ret,
363                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
364         }
365 
366         if (desc) {
367                 desc->callback = sh_mmcif_dma_complete;
368                 desc->callback_param = host;
369                 cookie = dmaengine_submit(desc);
370                 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
371                 dma_async_issue_pending(chan);
372         }
373         dev_dbg(dev, "%s(): mapped %d -> %d, cookie %d\n",
374                 __func__, data->sg_len, ret, cookie);
375 
376         if (!desc) {
377                 /* DMA failed, fall back to PIO */
378                 if (ret >= 0)
379                         ret = -EIO;
380                 host->chan_tx = NULL;
381                 host->dma_active = false;
382                 dma_release_channel(chan);
383                 /* Free the Rx channel too */
384                 chan = host->chan_rx;
385                 if (chan) {
386                         host->chan_rx = NULL;
387                         dma_release_channel(chan);
388                 }
389                 dev_warn(dev,
390                          "DMA failed: %d, falling back to PIO\n", ret);
391                 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
392         }
393 
394         dev_dbg(dev, "%s(): desc %p, cookie %d\n", __func__,
395                 desc, cookie);
396 }
397 
398 static struct dma_chan *
399 sh_mmcif_request_dma_pdata(struct sh_mmcif_host *host, uintptr_t slave_id)
400 {
401         dma_cap_mask_t mask;
402 
403         dma_cap_zero(mask);
404         dma_cap_set(DMA_SLAVE, mask);
405         if (slave_id <= 0)
406                 return NULL;
407 
408         return dma_request_channel(mask, shdma_chan_filter, (void *)slave_id);
409 }
410 
411 static int sh_mmcif_dma_slave_config(struct sh_mmcif_host *host,
412                                      struct dma_chan *chan,
413                                      enum dma_transfer_direction direction)
414 {
415         struct resource *res;
416         struct dma_slave_config cfg = { 0, };
417 
418         res = platform_get_resource(host->pd, IORESOURCE_MEM, 0);
419         cfg.direction = direction;
420 
421         if (direction == DMA_DEV_TO_MEM) {
422                 cfg.src_addr = res->start + MMCIF_CE_DATA;
423                 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
424         } else {
425                 cfg.dst_addr = res->start + MMCIF_CE_DATA;
426                 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
427         }
428 
429         return dmaengine_slave_config(chan, &cfg);
430 }
431 
432 static void sh_mmcif_request_dma(struct sh_mmcif_host *host)
433 {
434         struct device *dev = sh_mmcif_host_to_dev(host);
435         host->dma_active = false;
436 
437         /* We can only either use DMA for both Tx and Rx or not use it at all */
438         if (IS_ENABLED(CONFIG_SUPERH) && dev->platform_data) {
439                 struct sh_mmcif_plat_data *pdata = dev->platform_data;
440 
441                 host->chan_tx = sh_mmcif_request_dma_pdata(host,
442                                                         pdata->slave_id_tx);
443                 host->chan_rx = sh_mmcif_request_dma_pdata(host,
444                                                         pdata->slave_id_rx);
445         } else {
446                 host->chan_tx = dma_request_slave_channel(dev, "tx");
447                 host->chan_rx = dma_request_slave_channel(dev, "rx");
448         }
449         dev_dbg(dev, "%s: got channel TX %p RX %p\n", __func__, host->chan_tx,
450                 host->chan_rx);
451 
452         if (!host->chan_tx || !host->chan_rx ||
453             sh_mmcif_dma_slave_config(host, host->chan_tx, DMA_MEM_TO_DEV) ||
454             sh_mmcif_dma_slave_config(host, host->chan_rx, DMA_DEV_TO_MEM))
455                 goto error;
456 
457         return;
458 
459 error:
460         if (host->chan_tx)
461                 dma_release_channel(host->chan_tx);
462         if (host->chan_rx)
463                 dma_release_channel(host->chan_rx);
464         host->chan_tx = host->chan_rx = NULL;
465 }
466 
467 static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
468 {
469         sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
470         /* Descriptors are freed automatically */
471         if (host->chan_tx) {
472                 struct dma_chan *chan = host->chan_tx;
473                 host->chan_tx = NULL;
474                 dma_release_channel(chan);
475         }
476         if (host->chan_rx) {
477                 struct dma_chan *chan = host->chan_rx;
478                 host->chan_rx = NULL;
479                 dma_release_channel(chan);
480         }
481 
482         host->dma_active = false;
483 }
484 
485 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
486 {
487         struct device *dev = sh_mmcif_host_to_dev(host);
488         struct sh_mmcif_plat_data *p = dev->platform_data;
489         bool sup_pclk = p ? p->sup_pclk : false;
490         unsigned int current_clk = clk_get_rate(host->clk);
491         unsigned int clkdiv;
492 
493         sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
494         sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
495 
496         if (!clk)
497                 return;
498 
499         if (host->clkdiv_map) {
500                 unsigned int freq, best_freq, myclk, div, diff_min, diff;
501                 int i;
502 
503                 clkdiv = 0;
504                 diff_min = ~0;
505                 best_freq = 0;
506                 for (i = 31; i >= 0; i--) {
507                         if (!((1 << i) & host->clkdiv_map))
508                                 continue;
509 
510                         /*
511                          * clk = parent_freq / div
512                          * -> parent_freq = clk x div
513                          */
514 
515                         div = 1 << (i + 1);
516                         freq = clk_round_rate(host->clk, clk * div);
517                         myclk = freq / div;
518                         diff = (myclk > clk) ? myclk - clk : clk - myclk;
519 
520                         if (diff <= diff_min) {
521                                 best_freq = freq;
522                                 clkdiv = i;
523                                 diff_min = diff;
524                         }
525                 }
526 
527                 dev_dbg(dev, "clk %u/%u (%u, 0x%x)\n",
528                         (best_freq / (1 << (clkdiv + 1))), clk,
529                         best_freq, clkdiv);
530 
531                 clk_set_rate(host->clk, best_freq);
532                 clkdiv = clkdiv << 16;
533         } else if (sup_pclk && clk == current_clk) {
534                 clkdiv = CLK_SUP_PCLK;
535         } else {
536                 clkdiv = (fls(DIV_ROUND_UP(current_clk, clk) - 1) - 1) << 16;
537         }
538 
539         sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & clkdiv);
540         sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
541 }
542 
543 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
544 {
545         u32 tmp;
546 
547         tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
548 
549         sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
550         sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
551         if (host->ccs_enable)
552                 tmp |= SCCSTO_29;
553         if (host->clk_ctrl2_enable)
554                 sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000);
555         sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
556                 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29);
557         /* byte swap on */
558         sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
559 }
560 
561 static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
562 {
563         struct device *dev = sh_mmcif_host_to_dev(host);
564         u32 state1, state2;
565         int ret, timeout;
566 
567         host->sd_error = false;
568 
569         state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
570         state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
571         dev_dbg(dev, "ERR HOST_STS1 = %08x\n", state1);
572         dev_dbg(dev, "ERR HOST_STS2 = %08x\n", state2);
573 
574         if (state1 & STS1_CMDSEQ) {
575                 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
576                 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
577                 for (timeout = 10000; timeout; timeout--) {
578                         if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
579                               & STS1_CMDSEQ))
580                                 break;
581                         mdelay(1);
582                 }
583                 if (!timeout) {
584                         dev_err(dev,
585                                 "Forced end of command sequence timeout err\n");
586                         return -EIO;
587                 }
588                 sh_mmcif_sync_reset(host);
589                 dev_dbg(dev, "Forced end of command sequence\n");
590                 return -EIO;
591         }
592 
593         if (state2 & STS2_CRC_ERR) {
594                 dev_err(dev, " CRC error: state %u, wait %u\n",
595                         host->state, host->wait_for);
596                 ret = -EIO;
597         } else if (state2 & STS2_TIMEOUT_ERR) {
598                 dev_err(dev, " Timeout: state %u, wait %u\n",
599                         host->state, host->wait_for);
600                 ret = -ETIMEDOUT;
601         } else {
602                 dev_dbg(dev, " End/Index error: state %u, wait %u\n",
603                         host->state, host->wait_for);
604                 ret = -EIO;
605         }
606         return ret;
607 }
608 
609 static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p)
610 {
611         struct mmc_data *data = host->mrq->data;
612 
613         host->sg_blkidx += host->blocksize;
614 
615         /* data->sg->length must be a multiple of host->blocksize? */
616         BUG_ON(host->sg_blkidx > data->sg->length);
617 
618         if (host->sg_blkidx == data->sg->length) {
619                 host->sg_blkidx = 0;
620                 if (++host->sg_idx < data->sg_len)
621                         host->pio_ptr = sg_virt(++data->sg);
622         } else {
623                 host->pio_ptr = p;
624         }
625 
626         return host->sg_idx != data->sg_len;
627 }
628 
629 static void sh_mmcif_single_read(struct sh_mmcif_host *host,
630                                  struct mmc_request *mrq)
631 {
632         host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
633                            BLOCK_SIZE_MASK) + 3;
634 
635         host->wait_for = MMCIF_WAIT_FOR_READ;
636 
637         /* buf read enable */
638         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
639 }
640 
641 static bool sh_mmcif_read_block(struct sh_mmcif_host *host)
642 {
643         struct device *dev = sh_mmcif_host_to_dev(host);
644         struct mmc_data *data = host->mrq->data;
645         u32 *p = sg_virt(data->sg);
646         int i;
647 
648         if (host->sd_error) {
649                 data->error = sh_mmcif_error_manage(host);
650                 dev_dbg(dev, "%s(): %d\n", __func__, data->error);
651                 return false;
652         }
653 
654         for (i = 0; i < host->blocksize / 4; i++)
655                 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
656 
657         /* buffer read end */
658         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
659         host->wait_for = MMCIF_WAIT_FOR_READ_END;
660 
661         return true;
662 }
663 
664 static void sh_mmcif_multi_read(struct sh_mmcif_host *host,
665                                 struct mmc_request *mrq)
666 {
667         struct mmc_data *data = mrq->data;
668 
669         if (!data->sg_len || !data->sg->length)
670                 return;
671 
672         host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
673                 BLOCK_SIZE_MASK;
674 
675         host->wait_for = MMCIF_WAIT_FOR_MREAD;
676         host->sg_idx = 0;
677         host->sg_blkidx = 0;
678         host->pio_ptr = sg_virt(data->sg);
679 
680         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
681 }
682 
683 static bool sh_mmcif_mread_block(struct sh_mmcif_host *host)
684 {
685         struct device *dev = sh_mmcif_host_to_dev(host);
686         struct mmc_data *data = host->mrq->data;
687         u32 *p = host->pio_ptr;
688         int i;
689 
690         if (host->sd_error) {
691                 data->error = sh_mmcif_error_manage(host);
692                 dev_dbg(dev, "%s(): %d\n", __func__, data->error);
693                 return false;
694         }
695 
696         BUG_ON(!data->sg->length);
697 
698         for (i = 0; i < host->blocksize / 4; i++)
699                 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
700 
701         if (!sh_mmcif_next_block(host, p))
702                 return false;
703 
704         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
705 
706         return true;
707 }
708 
709 static void sh_mmcif_single_write(struct sh_mmcif_host *host,
710                                         struct mmc_request *mrq)
711 {
712         host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
713                            BLOCK_SIZE_MASK) + 3;
714 
715         host->wait_for = MMCIF_WAIT_FOR_WRITE;
716 
717         /* buf write enable */
718         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
719 }
720 
721 static bool sh_mmcif_write_block(struct sh_mmcif_host *host)
722 {
723         struct device *dev = sh_mmcif_host_to_dev(host);
724         struct mmc_data *data = host->mrq->data;
725         u32 *p = sg_virt(data->sg);
726         int i;
727 
728         if (host->sd_error) {
729                 data->error = sh_mmcif_error_manage(host);
730                 dev_dbg(dev, "%s(): %d\n", __func__, data->error);
731                 return false;
732         }
733 
734         for (i = 0; i < host->blocksize / 4; i++)
735                 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
736 
737         /* buffer write end */
738         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
739         host->wait_for = MMCIF_WAIT_FOR_WRITE_END;
740 
741         return true;
742 }
743 
744 static void sh_mmcif_multi_write(struct sh_mmcif_host *host,
745                                 struct mmc_request *mrq)
746 {
747         struct mmc_data *data = mrq->data;
748 
749         if (!data->sg_len || !data->sg->length)
750                 return;
751 
752         host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
753                 BLOCK_SIZE_MASK;
754 
755         host->wait_for = MMCIF_WAIT_FOR_MWRITE;
756         host->sg_idx = 0;
757         host->sg_blkidx = 0;
758         host->pio_ptr = sg_virt(data->sg);
759 
760         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
761 }
762 
763 static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host)
764 {
765         struct device *dev = sh_mmcif_host_to_dev(host);
766         struct mmc_data *data = host->mrq->data;
767         u32 *p = host->pio_ptr;
768         int i;
769 
770         if (host->sd_error) {
771                 data->error = sh_mmcif_error_manage(host);
772                 dev_dbg(dev, "%s(): %d\n", __func__, data->error);
773                 return false;
774         }
775 
776         BUG_ON(!data->sg->length);
777 
778         for (i = 0; i < host->blocksize / 4; i++)
779                 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
780 
781         if (!sh_mmcif_next_block(host, p))
782                 return false;
783 
784         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
785 
786         return true;
787 }
788 
789 static void sh_mmcif_get_response(struct sh_mmcif_host *host,
790                                                 struct mmc_command *cmd)
791 {
792         if (cmd->flags & MMC_RSP_136) {
793                 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
794                 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
795                 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
796                 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
797         } else
798                 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
799 }
800 
801 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
802                                                 struct mmc_command *cmd)
803 {
804         cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
805 }
806 
807 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
808                             struct mmc_request *mrq)
809 {
810         struct device *dev = sh_mmcif_host_to_dev(host);
811         struct mmc_data *data = mrq->data;
812         struct mmc_command *cmd = mrq->cmd;
813         u32 opc = cmd->opcode;
814         u32 tmp = 0;
815 
816         /* Response Type check */
817         switch (mmc_resp_type(cmd)) {
818         case MMC_RSP_NONE:
819                 tmp |= CMD_SET_RTYP_NO;
820                 break;
821         case MMC_RSP_R1:
822         case MMC_RSP_R3:
823                 tmp |= CMD_SET_RTYP_6B;
824                 break;
825         case MMC_RSP_R1B:
826                 tmp |= CMD_SET_RBSY | CMD_SET_RTYP_6B;
827                 break;
828         case MMC_RSP_R2:
829                 tmp |= CMD_SET_RTYP_17B;
830                 break;
831         default:
832                 dev_err(dev, "Unsupported response type.\n");
833                 break;
834         }
835 
836         /* WDAT / DATW */
837         if (data) {
838                 tmp |= CMD_SET_WDAT;
839                 switch (host->bus_width) {
840                 case MMC_BUS_WIDTH_1:
841                         tmp |= CMD_SET_DATW_1;
842                         break;
843                 case MMC_BUS_WIDTH_4:
844                         tmp |= CMD_SET_DATW_4;
845                         break;
846                 case MMC_BUS_WIDTH_8:
847                         tmp |= CMD_SET_DATW_8;
848                         break;
849                 default:
850                         dev_err(dev, "Unsupported bus width.\n");
851                         break;
852                 }
853                 switch (host->timing) {
854                 case MMC_TIMING_MMC_DDR52:
855                         /*
856                          * MMC core will only set this timing, if the host
857                          * advertises the MMC_CAP_1_8V_DDR/MMC_CAP_1_2V_DDR
858                          * capability. MMCIF implementations with this
859                          * capability, e.g. sh73a0, will have to set it
860                          * in their platform data.
861                          */
862                         tmp |= CMD_SET_DARS;
863                         break;
864                 }
865         }
866         /* DWEN */
867         if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
868                 tmp |= CMD_SET_DWEN;
869         /* CMLTE/CMD12EN */
870         if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
871                 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
872                 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
873                                 data->blocks << 16);
874         }
875         /* RIDXC[1:0] check bits */
876         if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
877             opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
878                 tmp |= CMD_SET_RIDXC_BITS;
879         /* RCRC7C[1:0] check bits */
880         if (opc == MMC_SEND_OP_COND)
881                 tmp |= CMD_SET_CRC7C_BITS;
882         /* RCRC7C[1:0] internal CRC7 */
883         if (opc == MMC_ALL_SEND_CID ||
884                 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
885                 tmp |= CMD_SET_CRC7C_INTERNAL;
886 
887         return (opc << 24) | tmp;
888 }
889 
890 static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
891                                struct mmc_request *mrq, u32 opc)
892 {
893         struct device *dev = sh_mmcif_host_to_dev(host);
894 
895         switch (opc) {
896         case MMC_READ_MULTIPLE_BLOCK:
897                 sh_mmcif_multi_read(host, mrq);
898                 return 0;
899         case MMC_WRITE_MULTIPLE_BLOCK:
900                 sh_mmcif_multi_write(host, mrq);
901                 return 0;
902         case MMC_WRITE_BLOCK:
903                 sh_mmcif_single_write(host, mrq);
904                 return 0;
905         case MMC_READ_SINGLE_BLOCK:
906         case MMC_SEND_EXT_CSD:
907                 sh_mmcif_single_read(host, mrq);
908                 return 0;
909         default:
910                 dev_err(dev, "Unsupported CMD%d\n", opc);
911                 return -EINVAL;
912         }
913 }
914 
915 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
916                                struct mmc_request *mrq)
917 {
918         struct mmc_command *cmd = mrq->cmd;
919         u32 opc = cmd->opcode;
920         u32 mask = 0;
921         unsigned long flags;
922 
923         if (cmd->flags & MMC_RSP_BUSY)
924                 mask = MASK_START_CMD | MASK_MRBSYE;
925         else
926                 mask = MASK_START_CMD | MASK_MCRSPE;
927 
928         if (host->ccs_enable)
929                 mask |= MASK_MCCSTO;
930 
931         if (mrq->data) {
932                 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
933                 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
934                                 mrq->data->blksz);
935         }
936         opc = sh_mmcif_set_cmd(host, mrq);
937 
938         if (host->ccs_enable)
939                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
940         else
941                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS);
942         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
943         /* set arg */
944         sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
945         /* set cmd */
946         spin_lock_irqsave(&host->lock, flags);
947         sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
948 
949         host->wait_for = MMCIF_WAIT_FOR_CMD;
950         schedule_delayed_work(&host->timeout_work, host->timeout);
951         spin_unlock_irqrestore(&host->lock, flags);
952 }
953 
954 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
955                               struct mmc_request *mrq)
956 {
957         struct device *dev = sh_mmcif_host_to_dev(host);
958 
959         switch (mrq->cmd->opcode) {
960         case MMC_READ_MULTIPLE_BLOCK:
961                 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
962                 break;
963         case MMC_WRITE_MULTIPLE_BLOCK:
964                 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
965                 break;
966         default:
967                 dev_err(dev, "unsupported stop cmd\n");
968                 mrq->stop->error = sh_mmcif_error_manage(host);
969                 return;
970         }
971 
972         host->wait_for = MMCIF_WAIT_FOR_STOP;
973 }
974 
975 static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
976 {
977         struct sh_mmcif_host *host = mmc_priv(mmc);
978         struct device *dev = sh_mmcif_host_to_dev(host);
979         unsigned long flags;
980 
981         spin_lock_irqsave(&host->lock, flags);
982         if (host->state != STATE_IDLE) {
983                 dev_dbg(dev, "%s() rejected, state %u\n",
984                         __func__, host->state);
985                 spin_unlock_irqrestore(&host->lock, flags);
986                 mrq->cmd->error = -EAGAIN;
987                 mmc_request_done(mmc, mrq);
988                 return;
989         }
990 
991         host->state = STATE_REQUEST;
992         spin_unlock_irqrestore(&host->lock, flags);
993 
994         host->mrq = mrq;
995 
996         sh_mmcif_start_cmd(host, mrq);
997 }
998 
999 static void sh_mmcif_clk_setup(struct sh_mmcif_host *host)
1000 {
1001         struct device *dev = sh_mmcif_host_to_dev(host);
1002 
1003         if (host->mmc->f_max) {
1004                 unsigned int f_max, f_min = 0, f_min_old;
1005 
1006                 f_max = host->mmc->f_max;
1007                 for (f_min_old = f_max; f_min_old > 2;) {
1008                         f_min = clk_round_rate(host->clk, f_min_old / 2);
1009                         if (f_min == f_min_old)
1010                                 break;
1011                         f_min_old = f_min;
1012                 }
1013 
1014                 /*
1015                  * This driver assumes this SoC is R-Car Gen2 or later
1016                  */
1017                 host->clkdiv_map = 0x3ff;
1018 
1019                 host->mmc->f_max = f_max / (1 << ffs(host->clkdiv_map));
1020                 host->mmc->f_min = f_min / (1 << fls(host->clkdiv_map));
1021         } else {
1022                 unsigned int clk = clk_get_rate(host->clk);
1023 
1024                 host->mmc->f_max = clk / 2;
1025                 host->mmc->f_min = clk / 512;
1026         }
1027 
1028         dev_dbg(dev, "clk max/min = %d/%d\n",
1029                 host->mmc->f_max, host->mmc->f_min);
1030 }
1031 
1032 static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1033 {
1034         struct sh_mmcif_host *host = mmc_priv(mmc);
1035         struct device *dev = sh_mmcif_host_to_dev(host);
1036         unsigned long flags;
1037 
1038         spin_lock_irqsave(&host->lock, flags);
1039         if (host->state != STATE_IDLE) {
1040                 dev_dbg(dev, "%s() rejected, state %u\n",
1041                         __func__, host->state);
1042                 spin_unlock_irqrestore(&host->lock, flags);
1043                 return;
1044         }
1045 
1046         host->state = STATE_IOS;
1047         spin_unlock_irqrestore(&host->lock, flags);
1048 
1049         switch (ios->power_mode) {
1050         case MMC_POWER_UP:
1051                 if (!IS_ERR(mmc->supply.vmmc))
1052                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1053                 if (!host->power) {
1054                         clk_prepare_enable(host->clk);
1055                         pm_runtime_get_sync(dev);
1056                         sh_mmcif_sync_reset(host);
1057                         sh_mmcif_request_dma(host);
1058                         host->power = true;
1059                 }
1060                 break;
1061         case MMC_POWER_OFF:
1062                 if (!IS_ERR(mmc->supply.vmmc))
1063                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1064                 if (host->power) {
1065                         sh_mmcif_clock_control(host, 0);
1066                         sh_mmcif_release_dma(host);
1067                         pm_runtime_put(dev);
1068                         clk_disable_unprepare(host->clk);
1069                         host->power = false;
1070                 }
1071                 break;
1072         case MMC_POWER_ON:
1073                 sh_mmcif_clock_control(host, ios->clock);
1074                 break;
1075         }
1076 
1077         host->timing = ios->timing;
1078         host->bus_width = ios->bus_width;
1079         host->state = STATE_IDLE;
1080 }
1081 
1082 static int sh_mmcif_get_cd(struct mmc_host *mmc)
1083 {
1084         struct sh_mmcif_host *host = mmc_priv(mmc);
1085         struct device *dev = sh_mmcif_host_to_dev(host);
1086         struct sh_mmcif_plat_data *p = dev->platform_data;
1087         int ret = mmc_gpio_get_cd(mmc);
1088 
1089         if (ret >= 0)
1090                 return ret;
1091 
1092         if (!p || !p->get_cd)
1093                 return -ENOSYS;
1094         else
1095                 return p->get_cd(host->pd);
1096 }
1097 
1098 static struct mmc_host_ops sh_mmcif_ops = {
1099         .request        = sh_mmcif_request,
1100         .set_ios        = sh_mmcif_set_ios,
1101         .get_cd         = sh_mmcif_get_cd,
1102 };
1103 
1104 static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host)
1105 {
1106         struct mmc_command *cmd = host->mrq->cmd;
1107         struct mmc_data *data = host->mrq->data;
1108         struct device *dev = sh_mmcif_host_to_dev(host);
1109         long time;
1110 
1111         if (host->sd_error) {
1112                 switch (cmd->opcode) {
1113                 case MMC_ALL_SEND_CID:
1114                 case MMC_SELECT_CARD:
1115                 case MMC_APP_CMD:
1116                         cmd->error = -ETIMEDOUT;
1117                         break;
1118                 default:
1119                         cmd->error = sh_mmcif_error_manage(host);
1120                         break;
1121                 }
1122                 dev_dbg(dev, "CMD%d error %d\n",
1123                         cmd->opcode, cmd->error);
1124                 host->sd_error = false;
1125                 return false;
1126         }
1127         if (!(cmd->flags & MMC_RSP_PRESENT)) {
1128                 cmd->error = 0;
1129                 return false;
1130         }
1131 
1132         sh_mmcif_get_response(host, cmd);
1133 
1134         if (!data)
1135                 return false;
1136 
1137         /*
1138          * Completion can be signalled from DMA callback and error, so, have to
1139          * reset here, before setting .dma_active
1140          */
1141         init_completion(&host->dma_complete);
1142 
1143         if (data->flags & MMC_DATA_READ) {
1144                 if (host->chan_rx)
1145                         sh_mmcif_start_dma_rx(host);
1146         } else {
1147                 if (host->chan_tx)
1148                         sh_mmcif_start_dma_tx(host);
1149         }
1150 
1151         if (!host->dma_active) {
1152                 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode);
1153                 return !data->error;
1154         }
1155 
1156         /* Running in the IRQ thread, can sleep */
1157         time = wait_for_completion_interruptible_timeout(&host->dma_complete,
1158                                                          host->timeout);
1159 
1160         if (data->flags & MMC_DATA_READ)
1161                 dma_unmap_sg(host->chan_rx->device->dev,
1162                              data->sg, data->sg_len,
1163                              DMA_FROM_DEVICE);
1164         else
1165                 dma_unmap_sg(host->chan_tx->device->dev,
1166                              data->sg, data->sg_len,
1167                              DMA_TO_DEVICE);
1168 
1169         if (host->sd_error) {
1170                 dev_err(host->mmc->parent,
1171                         "Error IRQ while waiting for DMA completion!\n");
1172                 /* Woken up by an error IRQ: abort DMA */
1173                 data->error = sh_mmcif_error_manage(host);
1174         } else if (!time) {
1175                 dev_err(host->mmc->parent, "DMA timeout!\n");
1176                 data->error = -ETIMEDOUT;
1177         } else if (time < 0) {
1178                 dev_err(host->mmc->parent,
1179                         "wait_for_completion_...() error %ld!\n", time);
1180                 data->error = time;
1181         }
1182         sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
1183                         BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
1184         host->dma_active = false;
1185 
1186         if (data->error) {
1187                 data->bytes_xfered = 0;
1188                 /* Abort DMA */
1189                 if (data->flags & MMC_DATA_READ)
1190                         dmaengine_terminate_all(host->chan_rx);
1191                 else
1192                         dmaengine_terminate_all(host->chan_tx);
1193         }
1194 
1195         return false;
1196 }
1197 
1198 static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id)
1199 {
1200         struct sh_mmcif_host *host = dev_id;
1201         struct mmc_request *mrq;
1202         struct device *dev = sh_mmcif_host_to_dev(host);
1203         bool wait = false;
1204         unsigned long flags;
1205         int wait_work;
1206 
1207         spin_lock_irqsave(&host->lock, flags);
1208         wait_work = host->wait_for;
1209         spin_unlock_irqrestore(&host->lock, flags);
1210 
1211         cancel_delayed_work_sync(&host->timeout_work);
1212 
1213         mutex_lock(&host->thread_lock);
1214 
1215         mrq = host->mrq;
1216         if (!mrq) {
1217                 dev_dbg(dev, "IRQ thread state %u, wait %u: NULL mrq!\n",
1218                         host->state, host->wait_for);
1219                 mutex_unlock(&host->thread_lock);
1220                 return IRQ_HANDLED;
1221         }
1222 
1223         /*
1224          * All handlers return true, if processing continues, and false, if the
1225          * request has to be completed - successfully or not
1226          */
1227         switch (wait_work) {
1228         case MMCIF_WAIT_FOR_REQUEST:
1229                 /* We're too late, the timeout has already kicked in */
1230                 mutex_unlock(&host->thread_lock);
1231                 return IRQ_HANDLED;
1232         case MMCIF_WAIT_FOR_CMD:
1233                 /* Wait for data? */
1234                 wait = sh_mmcif_end_cmd(host);
1235                 break;
1236         case MMCIF_WAIT_FOR_MREAD:
1237                 /* Wait for more data? */
1238                 wait = sh_mmcif_mread_block(host);
1239                 break;
1240         case MMCIF_WAIT_FOR_READ:
1241                 /* Wait for data end? */
1242                 wait = sh_mmcif_read_block(host);
1243                 break;
1244         case MMCIF_WAIT_FOR_MWRITE:
1245                 /* Wait data to write? */
1246                 wait = sh_mmcif_mwrite_block(host);
1247                 break;
1248         case MMCIF_WAIT_FOR_WRITE:
1249                 /* Wait for data end? */
1250                 wait = sh_mmcif_write_block(host);
1251                 break;
1252         case MMCIF_WAIT_FOR_STOP:
1253                 if (host->sd_error) {
1254                         mrq->stop->error = sh_mmcif_error_manage(host);
1255                         dev_dbg(dev, "%s(): %d\n", __func__, mrq->stop->error);
1256                         break;
1257                 }
1258                 sh_mmcif_get_cmd12response(host, mrq->stop);
1259                 mrq->stop->error = 0;
1260                 break;
1261         case MMCIF_WAIT_FOR_READ_END:
1262         case MMCIF_WAIT_FOR_WRITE_END:
1263                 if (host->sd_error) {
1264                         mrq->data->error = sh_mmcif_error_manage(host);
1265                         dev_dbg(dev, "%s(): %d\n", __func__, mrq->data->error);
1266                 }
1267                 break;
1268         default:
1269                 BUG();
1270         }
1271 
1272         if (wait) {
1273                 schedule_delayed_work(&host->timeout_work, host->timeout);
1274                 /* Wait for more data */
1275                 mutex_unlock(&host->thread_lock);
1276                 return IRQ_HANDLED;
1277         }
1278 
1279         if (host->wait_for != MMCIF_WAIT_FOR_STOP) {
1280                 struct mmc_data *data = mrq->data;
1281                 if (!mrq->cmd->error && data && !data->error)
1282                         data->bytes_xfered =
1283                                 data->blocks * data->blksz;
1284 
1285                 if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) {
1286                         sh_mmcif_stop_cmd(host, mrq);
1287                         if (!mrq->stop->error) {
1288                                 schedule_delayed_work(&host->timeout_work, host->timeout);
1289                                 mutex_unlock(&host->thread_lock);
1290                                 return IRQ_HANDLED;
1291                         }
1292                 }
1293         }
1294 
1295         host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1296         host->state = STATE_IDLE;
1297         host->mrq = NULL;
1298         mmc_request_done(host->mmc, mrq);
1299 
1300         mutex_unlock(&host->thread_lock);
1301 
1302         return IRQ_HANDLED;
1303 }
1304 
1305 static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
1306 {
1307         struct sh_mmcif_host *host = dev_id;
1308         struct device *dev = sh_mmcif_host_to_dev(host);
1309         u32 state, mask;
1310 
1311         state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
1312         mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK);
1313         if (host->ccs_enable)
1314                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask));
1315         else
1316                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask));
1317         sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN);
1318 
1319         if (state & ~MASK_CLEAN)
1320                 dev_dbg(dev, "IRQ state = 0x%08x incompletely cleared\n",
1321                         state);
1322 
1323         if (state & INT_ERR_STS || state & ~INT_ALL) {
1324                 host->sd_error = true;
1325                 dev_dbg(dev, "int err state = 0x%08x\n", state);
1326         }
1327         if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) {
1328                 if (!host->mrq)
1329                         dev_dbg(dev, "NULL IRQ state = 0x%08x\n", state);
1330                 if (!host->dma_active)
1331                         return IRQ_WAKE_THREAD;
1332                 else if (host->sd_error)
1333                         sh_mmcif_dma_complete(host);
1334         } else {
1335                 dev_dbg(dev, "Unexpected IRQ 0x%x\n", state);
1336         }
1337 
1338         return IRQ_HANDLED;
1339 }
1340 
1341 static void sh_mmcif_timeout_work(struct work_struct *work)
1342 {
1343         struct delayed_work *d = to_delayed_work(work);
1344         struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work);
1345         struct mmc_request *mrq = host->mrq;
1346         struct device *dev = sh_mmcif_host_to_dev(host);
1347         unsigned long flags;
1348 
1349         if (host->dying)
1350                 /* Don't run after mmc_remove_host() */
1351                 return;
1352 
1353         spin_lock_irqsave(&host->lock, flags);
1354         if (host->state == STATE_IDLE) {
1355                 spin_unlock_irqrestore(&host->lock, flags);
1356                 return;
1357         }
1358 
1359         dev_err(dev, "Timeout waiting for %u on CMD%u\n",
1360                 host->wait_for, mrq->cmd->opcode);
1361 
1362         host->state = STATE_TIMEOUT;
1363         spin_unlock_irqrestore(&host->lock, flags);
1364 
1365         /*
1366          * Handle races with cancel_delayed_work(), unless
1367          * cancel_delayed_work_sync() is used
1368          */
1369         switch (host->wait_for) {
1370         case MMCIF_WAIT_FOR_CMD:
1371                 mrq->cmd->error = sh_mmcif_error_manage(host);
1372                 break;
1373         case MMCIF_WAIT_FOR_STOP:
1374                 mrq->stop->error = sh_mmcif_error_manage(host);
1375                 break;
1376         case MMCIF_WAIT_FOR_MREAD:
1377         case MMCIF_WAIT_FOR_MWRITE:
1378         case MMCIF_WAIT_FOR_READ:
1379         case MMCIF_WAIT_FOR_WRITE:
1380         case MMCIF_WAIT_FOR_READ_END:
1381         case MMCIF_WAIT_FOR_WRITE_END:
1382                 mrq->data->error = sh_mmcif_error_manage(host);
1383                 break;
1384         default:
1385                 BUG();
1386         }
1387 
1388         host->state = STATE_IDLE;
1389         host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1390         host->mrq = NULL;
1391         mmc_request_done(host->mmc, mrq);
1392 }
1393 
1394 static void sh_mmcif_init_ocr(struct sh_mmcif_host *host)
1395 {
1396         struct device *dev = sh_mmcif_host_to_dev(host);
1397         struct sh_mmcif_plat_data *pd = dev->platform_data;
1398         struct mmc_host *mmc = host->mmc;
1399 
1400         mmc_regulator_get_supply(mmc);
1401 
1402         if (!pd)
1403                 return;
1404 
1405         if (!mmc->ocr_avail)
1406                 mmc->ocr_avail = pd->ocr;
1407         else if (pd->ocr)
1408                 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1409 }
1410 
1411 static int sh_mmcif_probe(struct platform_device *pdev)
1412 {
1413         int ret = 0, irq[2];
1414         struct mmc_host *mmc;
1415         struct sh_mmcif_host *host;
1416         struct device *dev = &pdev->dev;
1417         struct sh_mmcif_plat_data *pd = dev->platform_data;
1418         struct resource *res;
1419         void __iomem *reg;
1420         const char *name;
1421 
1422         irq[0] = platform_get_irq(pdev, 0);
1423         irq[1] = platform_get_irq(pdev, 1);
1424         if (irq[0] < 0) {
1425                 dev_err(dev, "Get irq error\n");
1426                 return -ENXIO;
1427         }
1428 
1429         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1430         reg = devm_ioremap_resource(dev, res);
1431         if (IS_ERR(reg))
1432                 return PTR_ERR(reg);
1433 
1434         mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), dev);
1435         if (!mmc)
1436                 return -ENOMEM;
1437 
1438         ret = mmc_of_parse(mmc);
1439         if (ret < 0)
1440                 goto err_host;
1441 
1442         host            = mmc_priv(mmc);
1443         host->mmc       = mmc;
1444         host->addr      = reg;
1445         host->timeout   = msecs_to_jiffies(10000);
1446         host->ccs_enable = !pd || !pd->ccs_unsupported;
1447         host->clk_ctrl2_enable = pd && pd->clk_ctrl2_present;
1448 
1449         host->pd = pdev;
1450 
1451         spin_lock_init(&host->lock);
1452 
1453         mmc->ops = &sh_mmcif_ops;
1454         sh_mmcif_init_ocr(host);
1455 
1456         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY;
1457         mmc->caps2 |= MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO;
1458         mmc->max_busy_timeout = 10000;
1459 
1460         if (pd && pd->caps)
1461                 mmc->caps |= pd->caps;
1462         mmc->max_segs = 32;
1463         mmc->max_blk_size = 512;
1464         mmc->max_req_size = PAGE_SIZE * mmc->max_segs;
1465         mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
1466         mmc->max_seg_size = mmc->max_req_size;
1467 
1468         platform_set_drvdata(pdev, host);
1469 
1470         host->clk = devm_clk_get(dev, NULL);
1471         if (IS_ERR(host->clk)) {
1472                 ret = PTR_ERR(host->clk);
1473                 dev_err(dev, "cannot get clock: %d\n", ret);
1474                 goto err_host;
1475         }
1476 
1477         ret = clk_prepare_enable(host->clk);
1478         if (ret < 0)
1479                 goto err_host;
1480 
1481         sh_mmcif_clk_setup(host);
1482 
1483         pm_runtime_enable(dev);
1484         host->power = false;
1485 
1486         ret = pm_runtime_get_sync(dev);
1487         if (ret < 0)
1488                 goto err_clk;
1489 
1490         INIT_DELAYED_WORK(&host->timeout_work, sh_mmcif_timeout_work);
1491 
1492         sh_mmcif_sync_reset(host);
1493         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1494 
1495         name = irq[1] < 0 ? dev_name(dev) : "sh_mmc:error";
1496         ret = devm_request_threaded_irq(dev, irq[0], sh_mmcif_intr,
1497                                         sh_mmcif_irqt, 0, name, host);
1498         if (ret) {
1499                 dev_err(dev, "request_irq error (%s)\n", name);
1500                 goto err_clk;
1501         }
1502         if (irq[1] >= 0) {
1503                 ret = devm_request_threaded_irq(dev, irq[1],
1504                                                 sh_mmcif_intr, sh_mmcif_irqt,
1505                                                 0, "sh_mmc:int", host);
1506                 if (ret) {
1507                         dev_err(dev, "request_irq error (sh_mmc:int)\n");
1508                         goto err_clk;
1509                 }
1510         }
1511 
1512         if (pd && pd->use_cd_gpio) {
1513                 ret = mmc_gpio_request_cd(mmc, pd->cd_gpio, 0);
1514                 if (ret < 0)
1515                         goto err_clk;
1516         }
1517 
1518         mutex_init(&host->thread_lock);
1519 
1520         ret = mmc_add_host(mmc);
1521         if (ret < 0)
1522                 goto err_clk;
1523 
1524         dev_pm_qos_expose_latency_limit(dev, 100);
1525 
1526         dev_info(dev, "Chip version 0x%04x, clock rate %luMHz\n",
1527                  sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0xffff,
1528                  clk_get_rate(host->clk) / 1000000UL);
1529 
1530         pm_runtime_put(dev);
1531         clk_disable_unprepare(host->clk);
1532         return ret;
1533 
1534 err_clk:
1535         clk_disable_unprepare(host->clk);
1536         pm_runtime_put_sync(dev);
1537         pm_runtime_disable(dev);
1538 err_host:
1539         mmc_free_host(mmc);
1540         return ret;
1541 }
1542 
1543 static int sh_mmcif_remove(struct platform_device *pdev)
1544 {
1545         struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1546 
1547         host->dying = true;
1548         clk_prepare_enable(host->clk);
1549         pm_runtime_get_sync(&pdev->dev);
1550 
1551         dev_pm_qos_hide_latency_limit(&pdev->dev);
1552 
1553         mmc_remove_host(host->mmc);
1554         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1555 
1556         /*
1557          * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the
1558          * mmc_remove_host() call above. But swapping order doesn't help either
1559          * (a query on the linux-mmc mailing list didn't bring any replies).
1560          */
1561         cancel_delayed_work_sync(&host->timeout_work);
1562 
1563         clk_disable_unprepare(host->clk);
1564         mmc_free_host(host->mmc);
1565         pm_runtime_put_sync(&pdev->dev);
1566         pm_runtime_disable(&pdev->dev);
1567 
1568         return 0;
1569 }
1570 
1571 #ifdef CONFIG_PM_SLEEP
1572 static int sh_mmcif_suspend(struct device *dev)
1573 {
1574         struct sh_mmcif_host *host = dev_get_drvdata(dev);
1575 
1576         pm_runtime_get_sync(dev);
1577         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1578         pm_runtime_put(dev);
1579 
1580         return 0;
1581 }
1582 
1583 static int sh_mmcif_resume(struct device *dev)
1584 {
1585         return 0;
1586 }
1587 #endif
1588 
1589 static const struct dev_pm_ops sh_mmcif_dev_pm_ops = {
1590         SET_SYSTEM_SLEEP_PM_OPS(sh_mmcif_suspend, sh_mmcif_resume)
1591 };
1592 
1593 static struct platform_driver sh_mmcif_driver = {
1594         .probe          = sh_mmcif_probe,
1595         .remove         = sh_mmcif_remove,
1596         .driver         = {
1597                 .name   = DRIVER_NAME,
1598                 .pm     = &sh_mmcif_dev_pm_ops,
1599                 .of_match_table = sh_mmcif_of_match,
1600         },
1601 };
1602 
1603 module_platform_driver(sh_mmcif_driver);
1604 
1605 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
1606 MODULE_LICENSE("GPL");
1607 MODULE_ALIAS("platform:" DRIVER_NAME);
1608 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");
1609 

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