Version:  2.0.40 2.2.26 2.4.37 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1

Linux/drivers/mmc/host/sdhci.c

  1 /*
  2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
  3  *
  4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License as published by
  8  * the Free Software Foundation; either version 2 of the License, or (at
  9  * your option) any later version.
 10  *
 11  * Thanks to the following companies for their support:
 12  *
 13  *     - JMicron (hardware and technical support)
 14  */
 15 
 16 #include <linux/delay.h>
 17 #include <linux/highmem.h>
 18 #include <linux/io.h>
 19 #include <linux/module.h>
 20 #include <linux/dma-mapping.h>
 21 #include <linux/slab.h>
 22 #include <linux/scatterlist.h>
 23 #include <linux/regulator/consumer.h>
 24 #include <linux/pm_runtime.h>
 25 
 26 #include <linux/leds.h>
 27 
 28 #include <linux/mmc/mmc.h>
 29 #include <linux/mmc/host.h>
 30 #include <linux/mmc/card.h>
 31 #include <linux/mmc/sdio.h>
 32 #include <linux/mmc/slot-gpio.h>
 33 
 34 #include "sdhci.h"
 35 
 36 #define DRIVER_NAME "sdhci"
 37 
 38 #define DBG(f, x...) \
 39         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
 40 
 41 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
 42         defined(CONFIG_MMC_SDHCI_MODULE))
 43 #define SDHCI_USE_LEDS_CLASS
 44 #endif
 45 
 46 #define MAX_TUNING_LOOP 40
 47 
 48 static unsigned int debug_quirks = 0;
 49 static unsigned int debug_quirks2;
 50 
 51 static void sdhci_finish_data(struct sdhci_host *);
 52 
 53 static void sdhci_finish_command(struct sdhci_host *);
 54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
 55 static void sdhci_tuning_timer(unsigned long data);
 56 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
 57 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
 58                                         struct mmc_data *data,
 59                                         struct sdhci_host_next *next);
 60 static int sdhci_do_get_cd(struct sdhci_host *host);
 61 
 62 #ifdef CONFIG_PM
 63 static int sdhci_runtime_pm_get(struct sdhci_host *host);
 64 static int sdhci_runtime_pm_put(struct sdhci_host *host);
 65 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
 66 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
 67 #else
 68 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
 69 {
 70         return 0;
 71 }
 72 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
 73 {
 74         return 0;
 75 }
 76 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
 77 {
 78 }
 79 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
 80 {
 81 }
 82 #endif
 83 
 84 static void sdhci_dumpregs(struct sdhci_host *host)
 85 {
 86         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
 87                 mmc_hostname(host->mmc));
 88 
 89         pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
 90                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
 91                 sdhci_readw(host, SDHCI_HOST_VERSION));
 92         pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
 93                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
 94                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
 95         pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
 96                 sdhci_readl(host, SDHCI_ARGUMENT),
 97                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
 98         pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
 99                 sdhci_readl(host, SDHCI_PRESENT_STATE),
100                 sdhci_readb(host, SDHCI_HOST_CONTROL));
101         pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
102                 sdhci_readb(host, SDHCI_POWER_CONTROL),
103                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
104         pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
105                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
106                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
107         pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
108                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
109                 sdhci_readl(host, SDHCI_INT_STATUS));
110         pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
111                 sdhci_readl(host, SDHCI_INT_ENABLE),
112                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
113         pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
114                 sdhci_readw(host, SDHCI_ACMD12_ERR),
115                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
116         pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
117                 sdhci_readl(host, SDHCI_CAPABILITIES),
118                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
119         pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
120                 sdhci_readw(host, SDHCI_COMMAND),
121                 sdhci_readl(host, SDHCI_MAX_CURRENT));
122         pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
123                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
124 
125         if (host->flags & SDHCI_USE_ADMA) {
126                 if (host->flags & SDHCI_USE_64_BIT_DMA)
127                         pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
128                                  readl(host->ioaddr + SDHCI_ADMA_ERROR),
129                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
130                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
131                 else
132                         pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
133                                  readl(host->ioaddr + SDHCI_ADMA_ERROR),
134                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
135         }
136 
137         pr_debug(DRIVER_NAME ": ===========================================\n");
138 }
139 
140 /*****************************************************************************\
141  *                                                                           *
142  * Low level functions                                                       *
143  *                                                                           *
144 \*****************************************************************************/
145 
146 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
147 {
148         u32 present;
149 
150         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
151             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
152                 return;
153 
154         if (enable) {
155                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
156                                       SDHCI_CARD_PRESENT;
157 
158                 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
159                                        SDHCI_INT_CARD_INSERT;
160         } else {
161                 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
162         }
163 
164         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
165         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
166 }
167 
168 static void sdhci_enable_card_detection(struct sdhci_host *host)
169 {
170         sdhci_set_card_detection(host, true);
171 }
172 
173 static void sdhci_disable_card_detection(struct sdhci_host *host)
174 {
175         sdhci_set_card_detection(host, false);
176 }
177 
178 void sdhci_reset(struct sdhci_host *host, u8 mask)
179 {
180         unsigned long timeout;
181 
182         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
183 
184         if (mask & SDHCI_RESET_ALL) {
185                 host->clock = 0;
186                 /* Reset-all turns off SD Bus Power */
187                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
188                         sdhci_runtime_pm_bus_off(host);
189         }
190 
191         /* Wait max 100 ms */
192         timeout = 100;
193 
194         /* hw clears the bit when it's done */
195         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
196                 if (timeout == 0) {
197                         pr_err("%s: Reset 0x%x never completed.\n",
198                                 mmc_hostname(host->mmc), (int)mask);
199                         sdhci_dumpregs(host);
200                         return;
201                 }
202                 timeout--;
203                 mdelay(1);
204         }
205 }
206 EXPORT_SYMBOL_GPL(sdhci_reset);
207 
208 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
209 {
210         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
211                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
212                         SDHCI_CARD_PRESENT))
213                         return;
214         }
215 
216         host->ops->reset(host, mask);
217 
218         if (mask & SDHCI_RESET_ALL) {
219                 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
220                         if (host->ops->enable_dma)
221                                 host->ops->enable_dma(host);
222                 }
223 
224                 /* Resetting the controller clears many */
225                 host->preset_enabled = false;
226         }
227 }
228 
229 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
230 
231 static void sdhci_init(struct sdhci_host *host, int soft)
232 {
233         if (soft)
234                 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
235         else
236                 sdhci_do_reset(host, SDHCI_RESET_ALL);
237 
238         host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
239                     SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
240                     SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
241                     SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
242                     SDHCI_INT_RESPONSE;
243 
244         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
245         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
246 
247         if (soft) {
248                 /* force clock reconfiguration */
249                 host->clock = 0;
250                 sdhci_set_ios(host->mmc, &host->mmc->ios);
251         }
252 }
253 
254 static void sdhci_reinit(struct sdhci_host *host)
255 {
256         sdhci_init(host, 0);
257         /*
258          * Retuning stuffs are affected by different cards inserted and only
259          * applicable to UHS-I cards. So reset these fields to their initial
260          * value when card is removed.
261          */
262         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
263                 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
264 
265                 del_timer_sync(&host->tuning_timer);
266                 host->flags &= ~SDHCI_NEEDS_RETUNING;
267         }
268         sdhci_enable_card_detection(host);
269 }
270 
271 static void sdhci_activate_led(struct sdhci_host *host)
272 {
273         u8 ctrl;
274 
275         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
276         ctrl |= SDHCI_CTRL_LED;
277         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
278 }
279 
280 static void sdhci_deactivate_led(struct sdhci_host *host)
281 {
282         u8 ctrl;
283 
284         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
285         ctrl &= ~SDHCI_CTRL_LED;
286         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
287 }
288 
289 #ifdef SDHCI_USE_LEDS_CLASS
290 static void sdhci_led_control(struct led_classdev *led,
291         enum led_brightness brightness)
292 {
293         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
294         unsigned long flags;
295 
296         spin_lock_irqsave(&host->lock, flags);
297 
298         if (host->runtime_suspended)
299                 goto out;
300 
301         if (brightness == LED_OFF)
302                 sdhci_deactivate_led(host);
303         else
304                 sdhci_activate_led(host);
305 out:
306         spin_unlock_irqrestore(&host->lock, flags);
307 }
308 #endif
309 
310 /*****************************************************************************\
311  *                                                                           *
312  * Core functions                                                            *
313  *                                                                           *
314 \*****************************************************************************/
315 
316 static void sdhci_read_block_pio(struct sdhci_host *host)
317 {
318         unsigned long flags;
319         size_t blksize, len, chunk;
320         u32 uninitialized_var(scratch);
321         u8 *buf;
322 
323         DBG("PIO reading\n");
324 
325         blksize = host->data->blksz;
326         chunk = 0;
327 
328         local_irq_save(flags);
329 
330         while (blksize) {
331                 if (!sg_miter_next(&host->sg_miter))
332                         BUG();
333 
334                 len = min(host->sg_miter.length, blksize);
335 
336                 blksize -= len;
337                 host->sg_miter.consumed = len;
338 
339                 buf = host->sg_miter.addr;
340 
341                 while (len) {
342                         if (chunk == 0) {
343                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
344                                 chunk = 4;
345                         }
346 
347                         *buf = scratch & 0xFF;
348 
349                         buf++;
350                         scratch >>= 8;
351                         chunk--;
352                         len--;
353                 }
354         }
355 
356         sg_miter_stop(&host->sg_miter);
357 
358         local_irq_restore(flags);
359 }
360 
361 static void sdhci_write_block_pio(struct sdhci_host *host)
362 {
363         unsigned long flags;
364         size_t blksize, len, chunk;
365         u32 scratch;
366         u8 *buf;
367 
368         DBG("PIO writing\n");
369 
370         blksize = host->data->blksz;
371         chunk = 0;
372         scratch = 0;
373 
374         local_irq_save(flags);
375 
376         while (blksize) {
377                 if (!sg_miter_next(&host->sg_miter))
378                         BUG();
379 
380                 len = min(host->sg_miter.length, blksize);
381 
382                 blksize -= len;
383                 host->sg_miter.consumed = len;
384 
385                 buf = host->sg_miter.addr;
386 
387                 while (len) {
388                         scratch |= (u32)*buf << (chunk * 8);
389 
390                         buf++;
391                         chunk++;
392                         len--;
393 
394                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
395                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
396                                 chunk = 0;
397                                 scratch = 0;
398                         }
399                 }
400         }
401 
402         sg_miter_stop(&host->sg_miter);
403 
404         local_irq_restore(flags);
405 }
406 
407 static void sdhci_transfer_pio(struct sdhci_host *host)
408 {
409         u32 mask;
410 
411         BUG_ON(!host->data);
412 
413         if (host->blocks == 0)
414                 return;
415 
416         if (host->data->flags & MMC_DATA_READ)
417                 mask = SDHCI_DATA_AVAILABLE;
418         else
419                 mask = SDHCI_SPACE_AVAILABLE;
420 
421         /*
422          * Some controllers (JMicron JMB38x) mess up the buffer bits
423          * for transfers < 4 bytes. As long as it is just one block,
424          * we can ignore the bits.
425          */
426         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
427                 (host->data->blocks == 1))
428                 mask = ~0;
429 
430         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
431                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
432                         udelay(100);
433 
434                 if (host->data->flags & MMC_DATA_READ)
435                         sdhci_read_block_pio(host);
436                 else
437                         sdhci_write_block_pio(host);
438 
439                 host->blocks--;
440                 if (host->blocks == 0)
441                         break;
442         }
443 
444         DBG("PIO transfer complete.\n");
445 }
446 
447 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
448 {
449         local_irq_save(*flags);
450         return kmap_atomic(sg_page(sg)) + sg->offset;
451 }
452 
453 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
454 {
455         kunmap_atomic(buffer);
456         local_irq_restore(*flags);
457 }
458 
459 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
460                                   dma_addr_t addr, int len, unsigned cmd)
461 {
462         struct sdhci_adma2_64_desc *dma_desc = desc;
463 
464         /* 32-bit and 64-bit descriptors have these members in same position */
465         dma_desc->cmd = cpu_to_le16(cmd);
466         dma_desc->len = cpu_to_le16(len);
467         dma_desc->addr_lo = cpu_to_le32((u32)addr);
468 
469         if (host->flags & SDHCI_USE_64_BIT_DMA)
470                 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
471 }
472 
473 static void sdhci_adma_mark_end(void *desc)
474 {
475         struct sdhci_adma2_64_desc *dma_desc = desc;
476 
477         /* 32-bit and 64-bit descriptors have 'cmd' in same position */
478         dma_desc->cmd |= cpu_to_le16(ADMA2_END);
479 }
480 
481 static int sdhci_adma_table_pre(struct sdhci_host *host,
482         struct mmc_data *data)
483 {
484         int direction;
485 
486         void *desc;
487         void *align;
488         dma_addr_t addr;
489         dma_addr_t align_addr;
490         int len, offset;
491 
492         struct scatterlist *sg;
493         int i;
494         char *buffer;
495         unsigned long flags;
496 
497         /*
498          * The spec does not specify endianness of descriptor table.
499          * We currently guess that it is LE.
500          */
501 
502         if (data->flags & MMC_DATA_READ)
503                 direction = DMA_FROM_DEVICE;
504         else
505                 direction = DMA_TO_DEVICE;
506 
507         host->align_addr = dma_map_single(mmc_dev(host->mmc),
508                 host->align_buffer, host->align_buffer_sz, direction);
509         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
510                 goto fail;
511         BUG_ON(host->align_addr & host->align_mask);
512 
513         host->sg_count = sdhci_pre_dma_transfer(host, data, NULL);
514         if (host->sg_count < 0)
515                 goto unmap_align;
516 
517         desc = host->adma_table;
518         align = host->align_buffer;
519 
520         align_addr = host->align_addr;
521 
522         for_each_sg(data->sg, sg, host->sg_count, i) {
523                 addr = sg_dma_address(sg);
524                 len = sg_dma_len(sg);
525 
526                 /*
527                  * The SDHCI specification states that ADMA
528                  * addresses must be 32-bit aligned. If they
529                  * aren't, then we use a bounce buffer for
530                  * the (up to three) bytes that screw up the
531                  * alignment.
532                  */
533                 offset = (host->align_sz - (addr & host->align_mask)) &
534                          host->align_mask;
535                 if (offset) {
536                         if (data->flags & MMC_DATA_WRITE) {
537                                 buffer = sdhci_kmap_atomic(sg, &flags);
538                                 memcpy(align, buffer, offset);
539                                 sdhci_kunmap_atomic(buffer, &flags);
540                         }
541 
542                         /* tran, valid */
543                         sdhci_adma_write_desc(host, desc, align_addr, offset,
544                                               ADMA2_TRAN_VALID);
545 
546                         BUG_ON(offset > 65536);
547 
548                         align += host->align_sz;
549                         align_addr += host->align_sz;
550 
551                         desc += host->desc_sz;
552 
553                         addr += offset;
554                         len -= offset;
555                 }
556 
557                 BUG_ON(len > 65536);
558 
559                 /* tran, valid */
560                 sdhci_adma_write_desc(host, desc, addr, len, ADMA2_TRAN_VALID);
561                 desc += host->desc_sz;
562 
563                 /*
564                  * If this triggers then we have a calculation bug
565                  * somewhere. :/
566                  */
567                 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
568         }
569 
570         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
571                 /*
572                 * Mark the last descriptor as the terminating descriptor
573                 */
574                 if (desc != host->adma_table) {
575                         desc -= host->desc_sz;
576                         sdhci_adma_mark_end(desc);
577                 }
578         } else {
579                 /*
580                 * Add a terminating entry.
581                 */
582 
583                 /* nop, end, valid */
584                 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
585         }
586 
587         /*
588          * Resync align buffer as we might have changed it.
589          */
590         if (data->flags & MMC_DATA_WRITE) {
591                 dma_sync_single_for_device(mmc_dev(host->mmc),
592                         host->align_addr, host->align_buffer_sz, direction);
593         }
594 
595         return 0;
596 
597 unmap_align:
598         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
599                 host->align_buffer_sz, direction);
600 fail:
601         return -EINVAL;
602 }
603 
604 static void sdhci_adma_table_post(struct sdhci_host *host,
605         struct mmc_data *data)
606 {
607         int direction;
608 
609         struct scatterlist *sg;
610         int i, size;
611         void *align;
612         char *buffer;
613         unsigned long flags;
614         bool has_unaligned;
615 
616         if (data->flags & MMC_DATA_READ)
617                 direction = DMA_FROM_DEVICE;
618         else
619                 direction = DMA_TO_DEVICE;
620 
621         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
622                 host->align_buffer_sz, direction);
623 
624         /* Do a quick scan of the SG list for any unaligned mappings */
625         has_unaligned = false;
626         for_each_sg(data->sg, sg, host->sg_count, i)
627                 if (sg_dma_address(sg) & host->align_mask) {
628                         has_unaligned = true;
629                         break;
630                 }
631 
632         if (has_unaligned && data->flags & MMC_DATA_READ) {
633                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
634                         data->sg_len, direction);
635 
636                 align = host->align_buffer;
637 
638                 for_each_sg(data->sg, sg, host->sg_count, i) {
639                         if (sg_dma_address(sg) & host->align_mask) {
640                                 size = host->align_sz -
641                                        (sg_dma_address(sg) & host->align_mask);
642 
643                                 buffer = sdhci_kmap_atomic(sg, &flags);
644                                 memcpy(buffer, align, size);
645                                 sdhci_kunmap_atomic(buffer, &flags);
646 
647                                 align += host->align_sz;
648                         }
649                 }
650         }
651 
652         if (!data->host_cookie)
653                 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
654                         data->sg_len, direction);
655 }
656 
657 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
658 {
659         u8 count;
660         struct mmc_data *data = cmd->data;
661         unsigned target_timeout, current_timeout;
662 
663         /*
664          * If the host controller provides us with an incorrect timeout
665          * value, just skip the check and use 0xE.  The hardware may take
666          * longer to time out, but that's much better than having a too-short
667          * timeout value.
668          */
669         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
670                 return 0xE;
671 
672         /* Unspecified timeout, assume max */
673         if (!data && !cmd->busy_timeout)
674                 return 0xE;
675 
676         /* timeout in us */
677         if (!data)
678                 target_timeout = cmd->busy_timeout * 1000;
679         else {
680                 target_timeout = data->timeout_ns / 1000;
681                 if (host->clock)
682                         target_timeout += data->timeout_clks / host->clock;
683         }
684 
685         /*
686          * Figure out needed cycles.
687          * We do this in steps in order to fit inside a 32 bit int.
688          * The first step is the minimum timeout, which will have a
689          * minimum resolution of 6 bits:
690          * (1) 2^13*1000 > 2^22,
691          * (2) host->timeout_clk < 2^16
692          *     =>
693          *     (1) / (2) > 2^6
694          */
695         count = 0;
696         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
697         while (current_timeout < target_timeout) {
698                 count++;
699                 current_timeout <<= 1;
700                 if (count >= 0xF)
701                         break;
702         }
703 
704         if (count >= 0xF) {
705                 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
706                     mmc_hostname(host->mmc), count, cmd->opcode);
707                 count = 0xE;
708         }
709 
710         return count;
711 }
712 
713 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
714 {
715         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
716         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
717 
718         if (host->flags & SDHCI_REQ_USE_DMA)
719                 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
720         else
721                 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
722 
723         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
724         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
725 }
726 
727 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
728 {
729         u8 count;
730 
731         if (host->ops->set_timeout) {
732                 host->ops->set_timeout(host, cmd);
733         } else {
734                 count = sdhci_calc_timeout(host, cmd);
735                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
736         }
737 }
738 
739 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
740 {
741         u8 ctrl;
742         struct mmc_data *data = cmd->data;
743         int ret;
744 
745         WARN_ON(host->data);
746 
747         if (data || (cmd->flags & MMC_RSP_BUSY))
748                 sdhci_set_timeout(host, cmd);
749 
750         if (!data)
751                 return;
752 
753         /* Sanity checks */
754         BUG_ON(data->blksz * data->blocks > 524288);
755         BUG_ON(data->blksz > host->mmc->max_blk_size);
756         BUG_ON(data->blocks > 65535);
757 
758         host->data = data;
759         host->data_early = 0;
760         host->data->bytes_xfered = 0;
761 
762         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
763                 host->flags |= SDHCI_REQ_USE_DMA;
764 
765         /*
766          * FIXME: This doesn't account for merging when mapping the
767          * scatterlist.
768          */
769         if (host->flags & SDHCI_REQ_USE_DMA) {
770                 int broken, i;
771                 struct scatterlist *sg;
772 
773                 broken = 0;
774                 if (host->flags & SDHCI_USE_ADMA) {
775                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
776                                 broken = 1;
777                 } else {
778                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
779                                 broken = 1;
780                 }
781 
782                 if (unlikely(broken)) {
783                         for_each_sg(data->sg, sg, data->sg_len, i) {
784                                 if (sg->length & 0x3) {
785                                         DBG("Reverting to PIO because of "
786                                                 "transfer size (%d)\n",
787                                                 sg->length);
788                                         host->flags &= ~SDHCI_REQ_USE_DMA;
789                                         break;
790                                 }
791                         }
792                 }
793         }
794 
795         /*
796          * The assumption here being that alignment is the same after
797          * translation to device address space.
798          */
799         if (host->flags & SDHCI_REQ_USE_DMA) {
800                 int broken, i;
801                 struct scatterlist *sg;
802 
803                 broken = 0;
804                 if (host->flags & SDHCI_USE_ADMA) {
805                         /*
806                          * As we use 3 byte chunks to work around
807                          * alignment problems, we need to check this
808                          * quirk.
809                          */
810                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
811                                 broken = 1;
812                 } else {
813                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
814                                 broken = 1;
815                 }
816 
817                 if (unlikely(broken)) {
818                         for_each_sg(data->sg, sg, data->sg_len, i) {
819                                 if (sg->offset & 0x3) {
820                                         DBG("Reverting to PIO because of "
821                                                 "bad alignment\n");
822                                         host->flags &= ~SDHCI_REQ_USE_DMA;
823                                         break;
824                                 }
825                         }
826                 }
827         }
828 
829         if (host->flags & SDHCI_REQ_USE_DMA) {
830                 if (host->flags & SDHCI_USE_ADMA) {
831                         ret = sdhci_adma_table_pre(host, data);
832                         if (ret) {
833                                 /*
834                                  * This only happens when someone fed
835                                  * us an invalid request.
836                                  */
837                                 WARN_ON(1);
838                                 host->flags &= ~SDHCI_REQ_USE_DMA;
839                         } else {
840                                 sdhci_writel(host, host->adma_addr,
841                                         SDHCI_ADMA_ADDRESS);
842                                 if (host->flags & SDHCI_USE_64_BIT_DMA)
843                                         sdhci_writel(host,
844                                                      (u64)host->adma_addr >> 32,
845                                                      SDHCI_ADMA_ADDRESS_HI);
846                         }
847                 } else {
848                         int sg_cnt;
849 
850                         sg_cnt = sdhci_pre_dma_transfer(host, data, NULL);
851                         if (sg_cnt == 0) {
852                                 /*
853                                  * This only happens when someone fed
854                                  * us an invalid request.
855                                  */
856                                 WARN_ON(1);
857                                 host->flags &= ~SDHCI_REQ_USE_DMA;
858                         } else {
859                                 WARN_ON(sg_cnt != 1);
860                                 sdhci_writel(host, sg_dma_address(data->sg),
861                                         SDHCI_DMA_ADDRESS);
862                         }
863                 }
864         }
865 
866         /*
867          * Always adjust the DMA selection as some controllers
868          * (e.g. JMicron) can't do PIO properly when the selection
869          * is ADMA.
870          */
871         if (host->version >= SDHCI_SPEC_200) {
872                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
873                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
874                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
875                         (host->flags & SDHCI_USE_ADMA)) {
876                         if (host->flags & SDHCI_USE_64_BIT_DMA)
877                                 ctrl |= SDHCI_CTRL_ADMA64;
878                         else
879                                 ctrl |= SDHCI_CTRL_ADMA32;
880                 } else {
881                         ctrl |= SDHCI_CTRL_SDMA;
882                 }
883                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
884         }
885 
886         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
887                 int flags;
888 
889                 flags = SG_MITER_ATOMIC;
890                 if (host->data->flags & MMC_DATA_READ)
891                         flags |= SG_MITER_TO_SG;
892                 else
893                         flags |= SG_MITER_FROM_SG;
894                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
895                 host->blocks = data->blocks;
896         }
897 
898         sdhci_set_transfer_irqs(host);
899 
900         /* Set the DMA boundary value and block size */
901         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
902                 data->blksz), SDHCI_BLOCK_SIZE);
903         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
904 }
905 
906 static void sdhci_set_transfer_mode(struct sdhci_host *host,
907         struct mmc_command *cmd)
908 {
909         u16 mode = 0;
910         struct mmc_data *data = cmd->data;
911 
912         if (data == NULL) {
913                 if (host->quirks2 &
914                         SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
915                         sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
916                 } else {
917                 /* clear Auto CMD settings for no data CMDs */
918                         mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
919                         sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
920                                 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
921                 }
922                 return;
923         }
924 
925         WARN_ON(!host->data);
926 
927         if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
928                 mode = SDHCI_TRNS_BLK_CNT_EN;
929 
930         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
931                 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
932                 /*
933                  * If we are sending CMD23, CMD12 never gets sent
934                  * on successful completion (so no Auto-CMD12).
935                  */
936                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
937                     (cmd->opcode != SD_IO_RW_EXTENDED))
938                         mode |= SDHCI_TRNS_AUTO_CMD12;
939                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
940                         mode |= SDHCI_TRNS_AUTO_CMD23;
941                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
942                 }
943         }
944 
945         if (data->flags & MMC_DATA_READ)
946                 mode |= SDHCI_TRNS_READ;
947         if (host->flags & SDHCI_REQ_USE_DMA)
948                 mode |= SDHCI_TRNS_DMA;
949 
950         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
951 }
952 
953 static void sdhci_finish_data(struct sdhci_host *host)
954 {
955         struct mmc_data *data;
956 
957         BUG_ON(!host->data);
958 
959         data = host->data;
960         host->data = NULL;
961 
962         if (host->flags & SDHCI_REQ_USE_DMA) {
963                 if (host->flags & SDHCI_USE_ADMA)
964                         sdhci_adma_table_post(host, data);
965                 else {
966                         if (!data->host_cookie)
967                                 dma_unmap_sg(mmc_dev(host->mmc),
968                                         data->sg, data->sg_len,
969                                         (data->flags & MMC_DATA_READ) ?
970                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
971                 }
972         }
973 
974         /*
975          * The specification states that the block count register must
976          * be updated, but it does not specify at what point in the
977          * data flow. That makes the register entirely useless to read
978          * back so we have to assume that nothing made it to the card
979          * in the event of an error.
980          */
981         if (data->error)
982                 data->bytes_xfered = 0;
983         else
984                 data->bytes_xfered = data->blksz * data->blocks;
985 
986         /*
987          * Need to send CMD12 if -
988          * a) open-ended multiblock transfer (no CMD23)
989          * b) error in multiblock transfer
990          */
991         if (data->stop &&
992             (data->error ||
993              !host->mrq->sbc)) {
994 
995                 /*
996                  * The controller needs a reset of internal state machines
997                  * upon error conditions.
998                  */
999                 if (data->error) {
1000                         sdhci_do_reset(host, SDHCI_RESET_CMD);
1001                         sdhci_do_reset(host, SDHCI_RESET_DATA);
1002                 }
1003 
1004                 sdhci_send_command(host, data->stop);
1005         } else
1006                 tasklet_schedule(&host->finish_tasklet);
1007 }
1008 
1009 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1010 {
1011         int flags;
1012         u32 mask;
1013         unsigned long timeout;
1014 
1015         WARN_ON(host->cmd);
1016 
1017         /* Wait max 10 ms */
1018         timeout = 10;
1019 
1020         mask = SDHCI_CMD_INHIBIT;
1021         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1022                 mask |= SDHCI_DATA_INHIBIT;
1023 
1024         /* We shouldn't wait for data inihibit for stop commands, even
1025            though they might use busy signaling */
1026         if (host->mrq->data && (cmd == host->mrq->data->stop))
1027                 mask &= ~SDHCI_DATA_INHIBIT;
1028 
1029         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1030                 if (timeout == 0) {
1031                         pr_err("%s: Controller never released "
1032                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1033                         sdhci_dumpregs(host);
1034                         cmd->error = -EIO;
1035                         tasklet_schedule(&host->finish_tasklet);
1036                         return;
1037                 }
1038                 timeout--;
1039                 mdelay(1);
1040         }
1041 
1042         timeout = jiffies;
1043         if (!cmd->data && cmd->busy_timeout > 9000)
1044                 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1045         else
1046                 timeout += 10 * HZ;
1047         mod_timer(&host->timer, timeout);
1048 
1049         host->cmd = cmd;
1050         host->busy_handle = 0;
1051 
1052         sdhci_prepare_data(host, cmd);
1053 
1054         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1055 
1056         sdhci_set_transfer_mode(host, cmd);
1057 
1058         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1059                 pr_err("%s: Unsupported response type!\n",
1060                         mmc_hostname(host->mmc));
1061                 cmd->error = -EINVAL;
1062                 tasklet_schedule(&host->finish_tasklet);
1063                 return;
1064         }
1065 
1066         if (!(cmd->flags & MMC_RSP_PRESENT))
1067                 flags = SDHCI_CMD_RESP_NONE;
1068         else if (cmd->flags & MMC_RSP_136)
1069                 flags = SDHCI_CMD_RESP_LONG;
1070         else if (cmd->flags & MMC_RSP_BUSY)
1071                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1072         else
1073                 flags = SDHCI_CMD_RESP_SHORT;
1074 
1075         if (cmd->flags & MMC_RSP_CRC)
1076                 flags |= SDHCI_CMD_CRC;
1077         if (cmd->flags & MMC_RSP_OPCODE)
1078                 flags |= SDHCI_CMD_INDEX;
1079 
1080         /* CMD19 is special in that the Data Present Select should be set */
1081         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1082             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1083                 flags |= SDHCI_CMD_DATA;
1084 
1085         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1086 }
1087 EXPORT_SYMBOL_GPL(sdhci_send_command);
1088 
1089 static void sdhci_finish_command(struct sdhci_host *host)
1090 {
1091         int i;
1092 
1093         BUG_ON(host->cmd == NULL);
1094 
1095         if (host->cmd->flags & MMC_RSP_PRESENT) {
1096                 if (host->cmd->flags & MMC_RSP_136) {
1097                         /* CRC is stripped so we need to do some shifting. */
1098                         for (i = 0;i < 4;i++) {
1099                                 host->cmd->resp[i] = sdhci_readl(host,
1100                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1101                                 if (i != 3)
1102                                         host->cmd->resp[i] |=
1103                                                 sdhci_readb(host,
1104                                                 SDHCI_RESPONSE + (3-i)*4-1);
1105                         }
1106                 } else {
1107                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1108                 }
1109         }
1110 
1111         host->cmd->error = 0;
1112 
1113         /* Finished CMD23, now send actual command. */
1114         if (host->cmd == host->mrq->sbc) {
1115                 host->cmd = NULL;
1116                 sdhci_send_command(host, host->mrq->cmd);
1117         } else {
1118 
1119                 /* Processed actual command. */
1120                 if (host->data && host->data_early)
1121                         sdhci_finish_data(host);
1122 
1123                 if (!host->cmd->data)
1124                         tasklet_schedule(&host->finish_tasklet);
1125 
1126                 host->cmd = NULL;
1127         }
1128 }
1129 
1130 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1131 {
1132         u16 preset = 0;
1133 
1134         switch (host->timing) {
1135         case MMC_TIMING_UHS_SDR12:
1136                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1137                 break;
1138         case MMC_TIMING_UHS_SDR25:
1139                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1140                 break;
1141         case MMC_TIMING_UHS_SDR50:
1142                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1143                 break;
1144         case MMC_TIMING_UHS_SDR104:
1145         case MMC_TIMING_MMC_HS200:
1146                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1147                 break;
1148         case MMC_TIMING_UHS_DDR50:
1149                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1150                 break;
1151         case MMC_TIMING_MMC_HS400:
1152                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1153                 break;
1154         default:
1155                 pr_warn("%s: Invalid UHS-I mode selected\n",
1156                         mmc_hostname(host->mmc));
1157                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1158                 break;
1159         }
1160         return preset;
1161 }
1162 
1163 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1164 {
1165         int div = 0; /* Initialized for compiler warning */
1166         int real_div = div, clk_mul = 1;
1167         u16 clk = 0;
1168         unsigned long timeout;
1169 
1170         host->mmc->actual_clock = 0;
1171 
1172         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1173 
1174         if (clock == 0)
1175                 return;
1176 
1177         if (host->version >= SDHCI_SPEC_300) {
1178                 if (host->preset_enabled) {
1179                         u16 pre_val;
1180 
1181                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1182                         pre_val = sdhci_get_preset_value(host);
1183                         div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1184                                 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1185                         if (host->clk_mul &&
1186                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1187                                 clk = SDHCI_PROG_CLOCK_MODE;
1188                                 real_div = div + 1;
1189                                 clk_mul = host->clk_mul;
1190                         } else {
1191                                 real_div = max_t(int, 1, div << 1);
1192                         }
1193                         goto clock_set;
1194                 }
1195 
1196                 /*
1197                  * Check if the Host Controller supports Programmable Clock
1198                  * Mode.
1199                  */
1200                 if (host->clk_mul) {
1201                         for (div = 1; div <= 1024; div++) {
1202                                 if ((host->max_clk * host->clk_mul / div)
1203                                         <= clock)
1204                                         break;
1205                         }
1206                         /*
1207                          * Set Programmable Clock Mode in the Clock
1208                          * Control register.
1209                          */
1210                         clk = SDHCI_PROG_CLOCK_MODE;
1211                         real_div = div;
1212                         clk_mul = host->clk_mul;
1213                         div--;
1214                 } else {
1215                         /* Version 3.00 divisors must be a multiple of 2. */
1216                         if (host->max_clk <= clock)
1217                                 div = 1;
1218                         else {
1219                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1220                                      div += 2) {
1221                                         if ((host->max_clk / div) <= clock)
1222                                                 break;
1223                                 }
1224                         }
1225                         real_div = div;
1226                         div >>= 1;
1227                 }
1228         } else {
1229                 /* Version 2.00 divisors must be a power of 2. */
1230                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1231                         if ((host->max_clk / div) <= clock)
1232                                 break;
1233                 }
1234                 real_div = div;
1235                 div >>= 1;
1236         }
1237 
1238 clock_set:
1239         if (real_div)
1240                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1241         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1242         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1243                 << SDHCI_DIVIDER_HI_SHIFT;
1244         clk |= SDHCI_CLOCK_INT_EN;
1245         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1246 
1247         /* Wait max 20 ms */
1248         timeout = 20;
1249         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1250                 & SDHCI_CLOCK_INT_STABLE)) {
1251                 if (timeout == 0) {
1252                         pr_err("%s: Internal clock never "
1253                                 "stabilised.\n", mmc_hostname(host->mmc));
1254                         sdhci_dumpregs(host);
1255                         return;
1256                 }
1257                 timeout--;
1258                 mdelay(1);
1259         }
1260 
1261         clk |= SDHCI_CLOCK_CARD_EN;
1262         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1263 }
1264 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1265 
1266 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1267                             unsigned short vdd)
1268 {
1269         struct mmc_host *mmc = host->mmc;
1270         u8 pwr = 0;
1271 
1272         if (!IS_ERR(mmc->supply.vmmc)) {
1273                 spin_unlock_irq(&host->lock);
1274                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1275                 spin_lock_irq(&host->lock);
1276 
1277                 if (mode != MMC_POWER_OFF)
1278                         sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1279                 else
1280                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1281 
1282                 return;
1283         }
1284 
1285         if (mode != MMC_POWER_OFF) {
1286                 switch (1 << vdd) {
1287                 case MMC_VDD_165_195:
1288                         pwr = SDHCI_POWER_180;
1289                         break;
1290                 case MMC_VDD_29_30:
1291                 case MMC_VDD_30_31:
1292                         pwr = SDHCI_POWER_300;
1293                         break;
1294                 case MMC_VDD_32_33:
1295                 case MMC_VDD_33_34:
1296                         pwr = SDHCI_POWER_330;
1297                         break;
1298                 default:
1299                         BUG();
1300                 }
1301         }
1302 
1303         if (host->pwr == pwr)
1304                 return;
1305 
1306         host->pwr = pwr;
1307 
1308         if (pwr == 0) {
1309                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1310                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1311                         sdhci_runtime_pm_bus_off(host);
1312                 vdd = 0;
1313         } else {
1314                 /*
1315                  * Spec says that we should clear the power reg before setting
1316                  * a new value. Some controllers don't seem to like this though.
1317                  */
1318                 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1319                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1320 
1321                 /*
1322                  * At least the Marvell CaFe chip gets confused if we set the
1323                  * voltage and set turn on power at the same time, so set the
1324                  * voltage first.
1325                  */
1326                 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1327                         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1328 
1329                 pwr |= SDHCI_POWER_ON;
1330 
1331                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1332 
1333                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1334                         sdhci_runtime_pm_bus_on(host);
1335 
1336                 /*
1337                  * Some controllers need an extra 10ms delay of 10ms before
1338                  * they can apply clock after applying power
1339                  */
1340                 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1341                         mdelay(10);
1342         }
1343 }
1344 
1345 /*****************************************************************************\
1346  *                                                                           *
1347  * MMC callbacks                                                             *
1348  *                                                                           *
1349 \*****************************************************************************/
1350 
1351 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1352 {
1353         struct sdhci_host *host;
1354         int present;
1355         unsigned long flags;
1356         u32 tuning_opcode;
1357 
1358         host = mmc_priv(mmc);
1359 
1360         sdhci_runtime_pm_get(host);
1361 
1362         /* Firstly check card presence */
1363         present = sdhci_do_get_cd(host);
1364 
1365         spin_lock_irqsave(&host->lock, flags);
1366 
1367         WARN_ON(host->mrq != NULL);
1368 
1369 #ifndef SDHCI_USE_LEDS_CLASS
1370         sdhci_activate_led(host);
1371 #endif
1372 
1373         /*
1374          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1375          * requests if Auto-CMD12 is enabled.
1376          */
1377         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1378                 if (mrq->stop) {
1379                         mrq->data->stop = NULL;
1380                         mrq->stop = NULL;
1381                 }
1382         }
1383 
1384         host->mrq = mrq;
1385 
1386         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1387                 host->mrq->cmd->error = -ENOMEDIUM;
1388                 tasklet_schedule(&host->finish_tasklet);
1389         } else {
1390                 u32 present_state;
1391 
1392                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1393                 /*
1394                  * Check if the re-tuning timer has already expired and there
1395                  * is no on-going data transfer and DAT0 is not busy. If so,
1396                  * we need to execute tuning procedure before sending command.
1397                  */
1398                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1399                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ)) &&
1400                     (present_state & SDHCI_DATA_0_LVL_MASK)) {
1401                         if (mmc->card) {
1402                                 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1403                                 tuning_opcode =
1404                                         mmc->card->type == MMC_TYPE_MMC ?
1405                                         MMC_SEND_TUNING_BLOCK_HS200 :
1406                                         MMC_SEND_TUNING_BLOCK;
1407 
1408                                 /* Here we need to set the host->mrq to NULL,
1409                                  * in case the pending finish_tasklet
1410                                  * finishes it incorrectly.
1411                                  */
1412                                 host->mrq = NULL;
1413 
1414                                 spin_unlock_irqrestore(&host->lock, flags);
1415                                 sdhci_execute_tuning(mmc, tuning_opcode);
1416                                 spin_lock_irqsave(&host->lock, flags);
1417 
1418                                 /* Restore original mmc_request structure */
1419                                 host->mrq = mrq;
1420                         }
1421                 }
1422 
1423                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1424                         sdhci_send_command(host, mrq->sbc);
1425                 else
1426                         sdhci_send_command(host, mrq->cmd);
1427         }
1428 
1429         mmiowb();
1430         spin_unlock_irqrestore(&host->lock, flags);
1431 }
1432 
1433 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1434 {
1435         u8 ctrl;
1436 
1437         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1438         if (width == MMC_BUS_WIDTH_8) {
1439                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1440                 if (host->version >= SDHCI_SPEC_300)
1441                         ctrl |= SDHCI_CTRL_8BITBUS;
1442         } else {
1443                 if (host->version >= SDHCI_SPEC_300)
1444                         ctrl &= ~SDHCI_CTRL_8BITBUS;
1445                 if (width == MMC_BUS_WIDTH_4)
1446                         ctrl |= SDHCI_CTRL_4BITBUS;
1447                 else
1448                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1449         }
1450         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1451 }
1452 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1453 
1454 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1455 {
1456         u16 ctrl_2;
1457 
1458         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1459         /* Select Bus Speed Mode for host */
1460         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1461         if ((timing == MMC_TIMING_MMC_HS200) ||
1462             (timing == MMC_TIMING_UHS_SDR104))
1463                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1464         else if (timing == MMC_TIMING_UHS_SDR12)
1465                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1466         else if (timing == MMC_TIMING_UHS_SDR25)
1467                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1468         else if (timing == MMC_TIMING_UHS_SDR50)
1469                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1470         else if ((timing == MMC_TIMING_UHS_DDR50) ||
1471                  (timing == MMC_TIMING_MMC_DDR52))
1472                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1473         else if (timing == MMC_TIMING_MMC_HS400)
1474                 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1475         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1476 }
1477 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1478 
1479 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1480 {
1481         unsigned long flags;
1482         u8 ctrl;
1483         struct mmc_host *mmc = host->mmc;
1484 
1485         spin_lock_irqsave(&host->lock, flags);
1486 
1487         if (host->flags & SDHCI_DEVICE_DEAD) {
1488                 spin_unlock_irqrestore(&host->lock, flags);
1489                 if (!IS_ERR(mmc->supply.vmmc) &&
1490                     ios->power_mode == MMC_POWER_OFF)
1491                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1492                 return;
1493         }
1494 
1495         /*
1496          * Reset the chip on each power off.
1497          * Should clear out any weird states.
1498          */
1499         if (ios->power_mode == MMC_POWER_OFF) {
1500                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1501                 sdhci_reinit(host);
1502         }
1503 
1504         if (host->version >= SDHCI_SPEC_300 &&
1505                 (ios->power_mode == MMC_POWER_UP) &&
1506                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1507                 sdhci_enable_preset_value(host, false);
1508 
1509         if (!ios->clock || ios->clock != host->clock) {
1510                 host->ops->set_clock(host, ios->clock);
1511                 host->clock = ios->clock;
1512 
1513                 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1514                     host->clock) {
1515                         host->timeout_clk = host->mmc->actual_clock ?
1516                                                 host->mmc->actual_clock / 1000 :
1517                                                 host->clock / 1000;
1518                         host->mmc->max_busy_timeout =
1519                                 host->ops->get_max_timeout_count ?
1520                                 host->ops->get_max_timeout_count(host) :
1521                                 1 << 27;
1522                         host->mmc->max_busy_timeout /= host->timeout_clk;
1523                 }
1524         }
1525 
1526         sdhci_set_power(host, ios->power_mode, ios->vdd);
1527 
1528         if (host->ops->platform_send_init_74_clocks)
1529                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1530 
1531         host->ops->set_bus_width(host, ios->bus_width);
1532 
1533         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1534 
1535         if ((ios->timing == MMC_TIMING_SD_HS ||
1536              ios->timing == MMC_TIMING_MMC_HS)
1537             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1538                 ctrl |= SDHCI_CTRL_HISPD;
1539         else
1540                 ctrl &= ~SDHCI_CTRL_HISPD;
1541 
1542         if (host->version >= SDHCI_SPEC_300) {
1543                 u16 clk, ctrl_2;
1544 
1545                 /* In case of UHS-I modes, set High Speed Enable */
1546                 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1547                     (ios->timing == MMC_TIMING_MMC_HS200) ||
1548                     (ios->timing == MMC_TIMING_MMC_DDR52) ||
1549                     (ios->timing == MMC_TIMING_UHS_SDR50) ||
1550                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1551                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1552                     (ios->timing == MMC_TIMING_UHS_SDR25))
1553                         ctrl |= SDHCI_CTRL_HISPD;
1554 
1555                 if (!host->preset_enabled) {
1556                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1557                         /*
1558                          * We only need to set Driver Strength if the
1559                          * preset value enable is not set.
1560                          */
1561                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1562                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1563                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1564                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1565                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1566                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1567 
1568                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1569                 } else {
1570                         /*
1571                          * According to SDHC Spec v3.00, if the Preset Value
1572                          * Enable in the Host Control 2 register is set, we
1573                          * need to reset SD Clock Enable before changing High
1574                          * Speed Enable to avoid generating clock gliches.
1575                          */
1576 
1577                         /* Reset SD Clock Enable */
1578                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1579                         clk &= ~SDHCI_CLOCK_CARD_EN;
1580                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1581 
1582                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1583 
1584                         /* Re-enable SD Clock */
1585                         host->ops->set_clock(host, host->clock);
1586                 }
1587 
1588                 /* Reset SD Clock Enable */
1589                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1590                 clk &= ~SDHCI_CLOCK_CARD_EN;
1591                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1592 
1593                 host->ops->set_uhs_signaling(host, ios->timing);
1594                 host->timing = ios->timing;
1595 
1596                 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1597                                 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1598                                  (ios->timing == MMC_TIMING_UHS_SDR25) ||
1599                                  (ios->timing == MMC_TIMING_UHS_SDR50) ||
1600                                  (ios->timing == MMC_TIMING_UHS_SDR104) ||
1601                                  (ios->timing == MMC_TIMING_UHS_DDR50))) {
1602                         u16 preset;
1603 
1604                         sdhci_enable_preset_value(host, true);
1605                         preset = sdhci_get_preset_value(host);
1606                         ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1607                                 >> SDHCI_PRESET_DRV_SHIFT;
1608                 }
1609 
1610                 /* Re-enable SD Clock */
1611                 host->ops->set_clock(host, host->clock);
1612         } else
1613                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1614 
1615         /*
1616          * Some (ENE) controllers go apeshit on some ios operation,
1617          * signalling timeout and CRC errors even on CMD0. Resetting
1618          * it on each ios seems to solve the problem.
1619          */
1620         if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1621                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1622 
1623         mmiowb();
1624         spin_unlock_irqrestore(&host->lock, flags);
1625 }
1626 
1627 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1628 {
1629         struct sdhci_host *host = mmc_priv(mmc);
1630 
1631         sdhci_runtime_pm_get(host);
1632         sdhci_do_set_ios(host, ios);
1633         sdhci_runtime_pm_put(host);
1634 }
1635 
1636 static int sdhci_do_get_cd(struct sdhci_host *host)
1637 {
1638         int gpio_cd = mmc_gpio_get_cd(host->mmc);
1639 
1640         if (host->flags & SDHCI_DEVICE_DEAD)
1641                 return 0;
1642 
1643         /* If polling/nonremovable, assume that the card is always present. */
1644         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1645             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1646                 return 1;
1647 
1648         /* Try slot gpio detect */
1649         if (!IS_ERR_VALUE(gpio_cd))
1650                 return !!gpio_cd;
1651 
1652         /* Host native card detect */
1653         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1654 }
1655 
1656 static int sdhci_get_cd(struct mmc_host *mmc)
1657 {
1658         struct sdhci_host *host = mmc_priv(mmc);
1659         int ret;
1660 
1661         sdhci_runtime_pm_get(host);
1662         ret = sdhci_do_get_cd(host);
1663         sdhci_runtime_pm_put(host);
1664         return ret;
1665 }
1666 
1667 static int sdhci_check_ro(struct sdhci_host *host)
1668 {
1669         unsigned long flags;
1670         int is_readonly;
1671 
1672         spin_lock_irqsave(&host->lock, flags);
1673 
1674         if (host->flags & SDHCI_DEVICE_DEAD)
1675                 is_readonly = 0;
1676         else if (host->ops->get_ro)
1677                 is_readonly = host->ops->get_ro(host);
1678         else
1679                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1680                                 & SDHCI_WRITE_PROTECT);
1681 
1682         spin_unlock_irqrestore(&host->lock, flags);
1683 
1684         /* This quirk needs to be replaced by a callback-function later */
1685         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1686                 !is_readonly : is_readonly;
1687 }
1688 
1689 #define SAMPLE_COUNT    5
1690 
1691 static int sdhci_do_get_ro(struct sdhci_host *host)
1692 {
1693         int i, ro_count;
1694 
1695         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1696                 return sdhci_check_ro(host);
1697 
1698         ro_count = 0;
1699         for (i = 0; i < SAMPLE_COUNT; i++) {
1700                 if (sdhci_check_ro(host)) {
1701                         if (++ro_count > SAMPLE_COUNT / 2)
1702                                 return 1;
1703                 }
1704                 msleep(30);
1705         }
1706         return 0;
1707 }
1708 
1709 static void sdhci_hw_reset(struct mmc_host *mmc)
1710 {
1711         struct sdhci_host *host = mmc_priv(mmc);
1712 
1713         if (host->ops && host->ops->hw_reset)
1714                 host->ops->hw_reset(host);
1715 }
1716 
1717 static int sdhci_get_ro(struct mmc_host *mmc)
1718 {
1719         struct sdhci_host *host = mmc_priv(mmc);
1720         int ret;
1721 
1722         sdhci_runtime_pm_get(host);
1723         ret = sdhci_do_get_ro(host);
1724         sdhci_runtime_pm_put(host);
1725         return ret;
1726 }
1727 
1728 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1729 {
1730         if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1731                 if (enable)
1732                         host->ier |= SDHCI_INT_CARD_INT;
1733                 else
1734                         host->ier &= ~SDHCI_INT_CARD_INT;
1735 
1736                 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1737                 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1738                 mmiowb();
1739         }
1740 }
1741 
1742 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1743 {
1744         struct sdhci_host *host = mmc_priv(mmc);
1745         unsigned long flags;
1746 
1747         sdhci_runtime_pm_get(host);
1748 
1749         spin_lock_irqsave(&host->lock, flags);
1750         if (enable)
1751                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1752         else
1753                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1754 
1755         sdhci_enable_sdio_irq_nolock(host, enable);
1756         spin_unlock_irqrestore(&host->lock, flags);
1757 
1758         sdhci_runtime_pm_put(host);
1759 }
1760 
1761 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1762                                                 struct mmc_ios *ios)
1763 {
1764         struct mmc_host *mmc = host->mmc;
1765         u16 ctrl;
1766         int ret;
1767 
1768         /*
1769          * Signal Voltage Switching is only applicable for Host Controllers
1770          * v3.00 and above.
1771          */
1772         if (host->version < SDHCI_SPEC_300)
1773                 return 0;
1774 
1775         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1776 
1777         switch (ios->signal_voltage) {
1778         case MMC_SIGNAL_VOLTAGE_330:
1779                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1780                 ctrl &= ~SDHCI_CTRL_VDD_180;
1781                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1782 
1783                 if (!IS_ERR(mmc->supply.vqmmc)) {
1784                         ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1785                                                     3600000);
1786                         if (ret) {
1787                                 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1788                                         mmc_hostname(mmc));
1789                                 return -EIO;
1790                         }
1791                 }
1792                 /* Wait for 5ms */
1793                 usleep_range(5000, 5500);
1794 
1795                 /* 3.3V regulator output should be stable within 5 ms */
1796                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1797                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1798                         return 0;
1799 
1800                 pr_warn("%s: 3.3V regulator output did not became stable\n",
1801                         mmc_hostname(mmc));
1802 
1803                 return -EAGAIN;
1804         case MMC_SIGNAL_VOLTAGE_180:
1805                 if (!IS_ERR(mmc->supply.vqmmc)) {
1806                         ret = regulator_set_voltage(mmc->supply.vqmmc,
1807                                         1700000, 1950000);
1808                         if (ret) {
1809                                 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1810                                         mmc_hostname(mmc));
1811                                 return -EIO;
1812                         }
1813                 }
1814 
1815                 /*
1816                  * Enable 1.8V Signal Enable in the Host Control2
1817                  * register
1818                  */
1819                 ctrl |= SDHCI_CTRL_VDD_180;
1820                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1821 
1822                 /* Some controller need to do more when switching */
1823                 if (host->ops->voltage_switch)
1824                         host->ops->voltage_switch(host);
1825 
1826                 /* 1.8V regulator output should be stable within 5 ms */
1827                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1828                 if (ctrl & SDHCI_CTRL_VDD_180)
1829                         return 0;
1830 
1831                 pr_warn("%s: 1.8V regulator output did not became stable\n",
1832                         mmc_hostname(mmc));
1833 
1834                 return -EAGAIN;
1835         case MMC_SIGNAL_VOLTAGE_120:
1836                 if (!IS_ERR(mmc->supply.vqmmc)) {
1837                         ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1838                                                     1300000);
1839                         if (ret) {
1840                                 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1841                                         mmc_hostname(mmc));
1842                                 return -EIO;
1843                         }
1844                 }
1845                 return 0;
1846         default:
1847                 /* No signal voltage switch required */
1848                 return 0;
1849         }
1850 }
1851 
1852 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1853         struct mmc_ios *ios)
1854 {
1855         struct sdhci_host *host = mmc_priv(mmc);
1856         int err;
1857 
1858         if (host->version < SDHCI_SPEC_300)
1859                 return 0;
1860         sdhci_runtime_pm_get(host);
1861         err = sdhci_do_start_signal_voltage_switch(host, ios);
1862         sdhci_runtime_pm_put(host);
1863         return err;
1864 }
1865 
1866 static int sdhci_card_busy(struct mmc_host *mmc)
1867 {
1868         struct sdhci_host *host = mmc_priv(mmc);
1869         u32 present_state;
1870 
1871         sdhci_runtime_pm_get(host);
1872         /* Check whether DAT[3:0] is 0000 */
1873         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1874         sdhci_runtime_pm_put(host);
1875 
1876         return !(present_state & SDHCI_DATA_LVL_MASK);
1877 }
1878 
1879 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1880 {
1881         struct sdhci_host *host = mmc_priv(mmc);
1882         unsigned long flags;
1883 
1884         spin_lock_irqsave(&host->lock, flags);
1885         host->flags |= SDHCI_HS400_TUNING;
1886         spin_unlock_irqrestore(&host->lock, flags);
1887 
1888         return 0;
1889 }
1890 
1891 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1892 {
1893         struct sdhci_host *host = mmc_priv(mmc);
1894         u16 ctrl;
1895         int tuning_loop_counter = MAX_TUNING_LOOP;
1896         int err = 0;
1897         unsigned long flags;
1898         unsigned int tuning_count = 0;
1899         bool hs400_tuning;
1900 
1901         sdhci_runtime_pm_get(host);
1902         spin_lock_irqsave(&host->lock, flags);
1903 
1904         hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1905         host->flags &= ~SDHCI_HS400_TUNING;
1906 
1907         if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1908                 tuning_count = host->tuning_count;
1909 
1910         /*
1911          * The Host Controller needs tuning only in case of SDR104 mode
1912          * and for SDR50 mode when Use Tuning for SDR50 is set in the
1913          * Capabilities register.
1914          * If the Host Controller supports the HS200 mode then the
1915          * tuning function has to be executed.
1916          */
1917         switch (host->timing) {
1918         /* HS400 tuning is done in HS200 mode */
1919         case MMC_TIMING_MMC_HS400:
1920                 err = -EINVAL;
1921                 goto out_unlock;
1922 
1923         case MMC_TIMING_MMC_HS200:
1924                 /*
1925                  * Periodic re-tuning for HS400 is not expected to be needed, so
1926                  * disable it here.
1927                  */
1928                 if (hs400_tuning)
1929                         tuning_count = 0;
1930                 break;
1931 
1932         case MMC_TIMING_UHS_SDR104:
1933                 break;
1934 
1935         case MMC_TIMING_UHS_SDR50:
1936                 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1937                     host->flags & SDHCI_SDR104_NEEDS_TUNING)
1938                         break;
1939                 /* FALLTHROUGH */
1940 
1941         default:
1942                 goto out_unlock;
1943         }
1944 
1945         if (host->ops->platform_execute_tuning) {
1946                 spin_unlock_irqrestore(&host->lock, flags);
1947                 err = host->ops->platform_execute_tuning(host, opcode);
1948                 sdhci_runtime_pm_put(host);
1949                 return err;
1950         }
1951 
1952         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1953         ctrl |= SDHCI_CTRL_EXEC_TUNING;
1954         if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1955                 ctrl |= SDHCI_CTRL_TUNED_CLK;
1956         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1957 
1958         /*
1959          * As per the Host Controller spec v3.00, tuning command
1960          * generates Buffer Read Ready interrupt, so enable that.
1961          *
1962          * Note: The spec clearly says that when tuning sequence
1963          * is being performed, the controller does not generate
1964          * interrupts other than Buffer Read Ready interrupt. But
1965          * to make sure we don't hit a controller bug, we _only_
1966          * enable Buffer Read Ready interrupt here.
1967          */
1968         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1969         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1970 
1971         /*
1972          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1973          * of loops reaches 40 times or a timeout of 150ms occurs.
1974          */
1975         do {
1976                 struct mmc_command cmd = {0};
1977                 struct mmc_request mrq = {NULL};
1978 
1979                 cmd.opcode = opcode;
1980                 cmd.arg = 0;
1981                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1982                 cmd.retries = 0;
1983                 cmd.data = NULL;
1984                 cmd.error = 0;
1985 
1986                 if (tuning_loop_counter-- == 0)
1987                         break;
1988 
1989                 mrq.cmd = &cmd;
1990                 host->mrq = &mrq;
1991 
1992                 /*
1993                  * In response to CMD19, the card sends 64 bytes of tuning
1994                  * block to the Host Controller. So we set the block size
1995                  * to 64 here.
1996                  */
1997                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1998                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1999                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
2000                                              SDHCI_BLOCK_SIZE);
2001                         else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
2002                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2003                                              SDHCI_BLOCK_SIZE);
2004                 } else {
2005                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2006                                      SDHCI_BLOCK_SIZE);
2007                 }
2008 
2009                 /*
2010                  * The tuning block is sent by the card to the host controller.
2011                  * So we set the TRNS_READ bit in the Transfer Mode register.
2012                  * This also takes care of setting DMA Enable and Multi Block
2013                  * Select in the same register to 0.
2014                  */
2015                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2016 
2017                 sdhci_send_command(host, &cmd);
2018 
2019                 host->cmd = NULL;
2020                 host->mrq = NULL;
2021 
2022                 spin_unlock_irqrestore(&host->lock, flags);
2023                 /* Wait for Buffer Read Ready interrupt */
2024                 wait_event_interruptible_timeout(host->buf_ready_int,
2025                                         (host->tuning_done == 1),
2026                                         msecs_to_jiffies(50));
2027                 spin_lock_irqsave(&host->lock, flags);
2028 
2029                 if (!host->tuning_done) {
2030                         pr_info(DRIVER_NAME ": Timeout waiting for "
2031                                 "Buffer Read Ready interrupt during tuning "
2032                                 "procedure, falling back to fixed sampling "
2033                                 "clock\n");
2034                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2035                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2036                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2037                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2038 
2039                         err = -EIO;
2040                         goto out;
2041                 }
2042 
2043                 host->tuning_done = 0;
2044 
2045                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2046 
2047                 /* eMMC spec does not require a delay between tuning cycles */
2048                 if (opcode == MMC_SEND_TUNING_BLOCK)
2049                         mdelay(1);
2050         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2051 
2052         /*
2053          * The Host Driver has exhausted the maximum number of loops allowed,
2054          * so use fixed sampling frequency.
2055          */
2056         if (tuning_loop_counter < 0) {
2057                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2058                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2059         }
2060         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2061                 pr_info(DRIVER_NAME ": Tuning procedure"
2062                         " failed, falling back to fixed sampling"
2063                         " clock\n");
2064                 err = -EIO;
2065         }
2066 
2067 out:
2068         host->flags &= ~SDHCI_NEEDS_RETUNING;
2069 
2070         if (tuning_count) {
2071                 host->flags |= SDHCI_USING_RETUNING_TIMER;
2072                 mod_timer(&host->tuning_timer, jiffies + tuning_count * HZ);
2073         }
2074 
2075         /*
2076          * In case tuning fails, host controllers which support re-tuning can
2077          * try tuning again at a later time, when the re-tuning timer expires.
2078          * So for these controllers, we return 0. Since there might be other
2079          * controllers who do not have this capability, we return error for
2080          * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2081          * a retuning timer to do the retuning for the card.
2082          */
2083         if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2084                 err = 0;
2085 
2086         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2087         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2088 out_unlock:
2089         spin_unlock_irqrestore(&host->lock, flags);
2090         sdhci_runtime_pm_put(host);
2091 
2092         return err;
2093 }
2094 
2095 
2096 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2097 {
2098         /* Host Controller v3.00 defines preset value registers */
2099         if (host->version < SDHCI_SPEC_300)
2100                 return;
2101 
2102         /*
2103          * We only enable or disable Preset Value if they are not already
2104          * enabled or disabled respectively. Otherwise, we bail out.
2105          */
2106         if (host->preset_enabled != enable) {
2107                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2108 
2109                 if (enable)
2110                         ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2111                 else
2112                         ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2113 
2114                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2115 
2116                 if (enable)
2117                         host->flags |= SDHCI_PV_ENABLED;
2118                 else
2119                         host->flags &= ~SDHCI_PV_ENABLED;
2120 
2121                 host->preset_enabled = enable;
2122         }
2123 }
2124 
2125 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2126                                 int err)
2127 {
2128         struct sdhci_host *host = mmc_priv(mmc);
2129         struct mmc_data *data = mrq->data;
2130 
2131         if (host->flags & SDHCI_REQ_USE_DMA) {
2132                 if (data->host_cookie)
2133                         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2134                                          data->flags & MMC_DATA_WRITE ?
2135                                          DMA_TO_DEVICE : DMA_FROM_DEVICE);
2136                 mrq->data->host_cookie = 0;
2137         }
2138 }
2139 
2140 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
2141                                        struct mmc_data *data,
2142                                        struct sdhci_host_next *next)
2143 {
2144         int sg_count;
2145 
2146         if (!next && data->host_cookie &&
2147             data->host_cookie != host->next_data.cookie) {
2148                 pr_debug(DRIVER_NAME "[%s] invalid cookie: %d, next-cookie %d\n",
2149                         __func__, data->host_cookie, host->next_data.cookie);
2150                 data->host_cookie = 0;
2151         }
2152 
2153         /* Check if next job is already prepared */
2154         if (next ||
2155             (!next && data->host_cookie != host->next_data.cookie)) {
2156                 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg,
2157                                      data->sg_len,
2158                                      data->flags & MMC_DATA_WRITE ?
2159                                      DMA_TO_DEVICE : DMA_FROM_DEVICE);
2160 
2161         } else {
2162                 sg_count = host->next_data.sg_count;
2163                 host->next_data.sg_count = 0;
2164         }
2165 
2166 
2167         if (sg_count == 0)
2168                 return -EINVAL;
2169 
2170         if (next) {
2171                 next->sg_count = sg_count;
2172                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
2173         } else
2174                 host->sg_count = sg_count;
2175 
2176         return sg_count;
2177 }
2178 
2179 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2180                                bool is_first_req)
2181 {
2182         struct sdhci_host *host = mmc_priv(mmc);
2183 
2184         if (mrq->data->host_cookie) {
2185                 mrq->data->host_cookie = 0;
2186                 return;
2187         }
2188 
2189         if (host->flags & SDHCI_REQ_USE_DMA)
2190                 if (sdhci_pre_dma_transfer(host,
2191                                         mrq->data,
2192                                         &host->next_data) < 0)
2193                         mrq->data->host_cookie = 0;
2194 }
2195 
2196 static void sdhci_card_event(struct mmc_host *mmc)
2197 {
2198         struct sdhci_host *host = mmc_priv(mmc);
2199         unsigned long flags;
2200         int present;
2201 
2202         /* First check if client has provided their own card event */
2203         if (host->ops->card_event)
2204                 host->ops->card_event(host);
2205 
2206         present = sdhci_do_get_cd(host);
2207 
2208         spin_lock_irqsave(&host->lock, flags);
2209 
2210         /* Check host->mrq first in case we are runtime suspended */
2211         if (host->mrq && !present) {
2212                 pr_err("%s: Card removed during transfer!\n",
2213                         mmc_hostname(host->mmc));
2214                 pr_err("%s: Resetting controller.\n",
2215                         mmc_hostname(host->mmc));
2216 
2217                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2218                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2219 
2220                 host->mrq->cmd->error = -ENOMEDIUM;
2221                 tasklet_schedule(&host->finish_tasklet);
2222         }
2223 
2224         spin_unlock_irqrestore(&host->lock, flags);
2225 }
2226 
2227 static const struct mmc_host_ops sdhci_ops = {
2228         .request        = sdhci_request,
2229         .post_req       = sdhci_post_req,
2230         .pre_req        = sdhci_pre_req,
2231         .set_ios        = sdhci_set_ios,
2232         .get_cd         = sdhci_get_cd,
2233         .get_ro         = sdhci_get_ro,
2234         .hw_reset       = sdhci_hw_reset,
2235         .enable_sdio_irq = sdhci_enable_sdio_irq,
2236         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2237         .prepare_hs400_tuning           = sdhci_prepare_hs400_tuning,
2238         .execute_tuning                 = sdhci_execute_tuning,
2239         .card_event                     = sdhci_card_event,
2240         .card_busy      = sdhci_card_busy,
2241 };
2242 
2243 /*****************************************************************************\
2244  *                                                                           *
2245  * Tasklets                                                                  *
2246  *                                                                           *
2247 \*****************************************************************************/
2248 
2249 static void sdhci_tasklet_finish(unsigned long param)
2250 {
2251         struct sdhci_host *host;
2252         unsigned long flags;
2253         struct mmc_request *mrq;
2254 
2255         host = (struct sdhci_host*)param;
2256 
2257         spin_lock_irqsave(&host->lock, flags);
2258 
2259         /*
2260          * If this tasklet gets rescheduled while running, it will
2261          * be run again afterwards but without any active request.
2262          */
2263         if (!host->mrq) {
2264                 spin_unlock_irqrestore(&host->lock, flags);
2265                 return;
2266         }
2267 
2268         del_timer(&host->timer);
2269 
2270         mrq = host->mrq;
2271 
2272         /*
2273          * The controller needs a reset of internal state machines
2274          * upon error conditions.
2275          */
2276         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2277             ((mrq->cmd && mrq->cmd->error) ||
2278              (mrq->sbc && mrq->sbc->error) ||
2279              (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2280                             (mrq->data->stop && mrq->data->stop->error))) ||
2281              (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2282 
2283                 /* Some controllers need this kick or reset won't work here */
2284                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2285                         /* This is to force an update */
2286                         host->ops->set_clock(host, host->clock);
2287 
2288                 /* Spec says we should do both at the same time, but Ricoh
2289                    controllers do not like that. */
2290                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2291                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2292         }
2293 
2294         host->mrq = NULL;
2295         host->cmd = NULL;
2296         host->data = NULL;
2297 
2298 #ifndef SDHCI_USE_LEDS_CLASS
2299         sdhci_deactivate_led(host);
2300 #endif
2301 
2302         mmiowb();
2303         spin_unlock_irqrestore(&host->lock, flags);
2304 
2305         mmc_request_done(host->mmc, mrq);
2306         sdhci_runtime_pm_put(host);
2307 }
2308 
2309 static void sdhci_timeout_timer(unsigned long data)
2310 {
2311         struct sdhci_host *host;
2312         unsigned long flags;
2313 
2314         host = (struct sdhci_host*)data;
2315 
2316         spin_lock_irqsave(&host->lock, flags);
2317 
2318         if (host->mrq) {
2319                 pr_err("%s: Timeout waiting for hardware "
2320                         "interrupt.\n", mmc_hostname(host->mmc));
2321                 sdhci_dumpregs(host);
2322 
2323                 if (host->data) {
2324                         host->data->error = -ETIMEDOUT;
2325                         sdhci_finish_data(host);
2326                 } else {
2327                         if (host->cmd)
2328                                 host->cmd->error = -ETIMEDOUT;
2329                         else
2330                                 host->mrq->cmd->error = -ETIMEDOUT;
2331 
2332                         tasklet_schedule(&host->finish_tasklet);
2333                 }
2334         }
2335 
2336         mmiowb();
2337         spin_unlock_irqrestore(&host->lock, flags);
2338 }
2339 
2340 static void sdhci_tuning_timer(unsigned long data)
2341 {
2342         struct sdhci_host *host;
2343         unsigned long flags;
2344 
2345         host = (struct sdhci_host *)data;
2346 
2347         spin_lock_irqsave(&host->lock, flags);
2348 
2349         host->flags |= SDHCI_NEEDS_RETUNING;
2350 
2351         spin_unlock_irqrestore(&host->lock, flags);
2352 }
2353 
2354 /*****************************************************************************\
2355  *                                                                           *
2356  * Interrupt handling                                                        *
2357  *                                                                           *
2358 \*****************************************************************************/
2359 
2360 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2361 {
2362         BUG_ON(intmask == 0);
2363 
2364         if (!host->cmd) {
2365                 pr_err("%s: Got command interrupt 0x%08x even "
2366                         "though no command operation was in progress.\n",
2367                         mmc_hostname(host->mmc), (unsigned)intmask);
2368                 sdhci_dumpregs(host);
2369                 return;
2370         }
2371 
2372         if (intmask & SDHCI_INT_TIMEOUT)
2373                 host->cmd->error = -ETIMEDOUT;
2374         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2375                         SDHCI_INT_INDEX))
2376                 host->cmd->error = -EILSEQ;
2377 
2378         if (host->cmd->error) {
2379                 tasklet_schedule(&host->finish_tasklet);
2380                 return;
2381         }
2382 
2383         /*
2384          * The host can send and interrupt when the busy state has
2385          * ended, allowing us to wait without wasting CPU cycles.
2386          * Unfortunately this is overloaded on the "data complete"
2387          * interrupt, so we need to take some care when handling
2388          * it.
2389          *
2390          * Note: The 1.0 specification is a bit ambiguous about this
2391          *       feature so there might be some problems with older
2392          *       controllers.
2393          */
2394         if (host->cmd->flags & MMC_RSP_BUSY) {
2395                 if (host->cmd->data)
2396                         DBG("Cannot wait for busy signal when also "
2397                                 "doing a data transfer");
2398                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2399                                 && !host->busy_handle) {
2400                         /* Mark that command complete before busy is ended */
2401                         host->busy_handle = 1;
2402                         return;
2403                 }
2404 
2405                 /* The controller does not support the end-of-busy IRQ,
2406                  * fall through and take the SDHCI_INT_RESPONSE */
2407         } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2408                    host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2409                 *mask &= ~SDHCI_INT_DATA_END;
2410         }
2411 
2412         if (intmask & SDHCI_INT_RESPONSE)
2413                 sdhci_finish_command(host);
2414 }
2415 
2416 #ifdef CONFIG_MMC_DEBUG
2417 static void sdhci_adma_show_error(struct sdhci_host *host)
2418 {
2419         const char *name = mmc_hostname(host->mmc);
2420         void *desc = host->adma_table;
2421 
2422         sdhci_dumpregs(host);
2423 
2424         while (true) {
2425                 struct sdhci_adma2_64_desc *dma_desc = desc;
2426 
2427                 if (host->flags & SDHCI_USE_64_BIT_DMA)
2428                         DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2429                             name, desc, le32_to_cpu(dma_desc->addr_hi),
2430                             le32_to_cpu(dma_desc->addr_lo),
2431                             le16_to_cpu(dma_desc->len),
2432                             le16_to_cpu(dma_desc->cmd));
2433                 else
2434                         DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2435                             name, desc, le32_to_cpu(dma_desc->addr_lo),
2436                             le16_to_cpu(dma_desc->len),
2437                             le16_to_cpu(dma_desc->cmd));
2438 
2439                 desc += host->desc_sz;
2440 
2441                 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2442                         break;
2443         }
2444 }
2445 #else
2446 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2447 #endif
2448 
2449 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2450 {
2451         u32 command;
2452         BUG_ON(intmask == 0);
2453 
2454         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2455         if (intmask & SDHCI_INT_DATA_AVAIL) {
2456                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2457                 if (command == MMC_SEND_TUNING_BLOCK ||
2458                     command == MMC_SEND_TUNING_BLOCK_HS200) {
2459                         host->tuning_done = 1;
2460                         wake_up(&host->buf_ready_int);
2461                         return;
2462                 }
2463         }
2464 
2465         if (!host->data) {
2466                 /*
2467                  * The "data complete" interrupt is also used to
2468                  * indicate that a busy state has ended. See comment
2469                  * above in sdhci_cmd_irq().
2470                  */
2471                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2472                         if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2473                                 host->cmd->error = -ETIMEDOUT;
2474                                 tasklet_schedule(&host->finish_tasklet);
2475                                 return;
2476                         }
2477                         if (intmask & SDHCI_INT_DATA_END) {
2478                                 /*
2479                                  * Some cards handle busy-end interrupt
2480                                  * before the command completed, so make
2481                                  * sure we do things in the proper order.
2482                                  */
2483                                 if (host->busy_handle)
2484                                         sdhci_finish_command(host);
2485                                 else
2486                                         host->busy_handle = 1;
2487                                 return;
2488                         }
2489                 }
2490 
2491                 pr_err("%s: Got data interrupt 0x%08x even "
2492                         "though no data operation was in progress.\n",
2493                         mmc_hostname(host->mmc), (unsigned)intmask);
2494                 sdhci_dumpregs(host);
2495 
2496                 return;
2497         }
2498 
2499         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2500                 host->data->error = -ETIMEDOUT;
2501         else if (intmask & SDHCI_INT_DATA_END_BIT)
2502                 host->data->error = -EILSEQ;
2503         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2504                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2505                         != MMC_BUS_TEST_R)
2506                 host->data->error = -EILSEQ;
2507         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2508                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2509                 sdhci_adma_show_error(host);
2510                 host->data->error = -EIO;
2511                 if (host->ops->adma_workaround)
2512                         host->ops->adma_workaround(host, intmask);
2513         }
2514 
2515         if (host->data->error)
2516                 sdhci_finish_data(host);
2517         else {
2518                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2519                         sdhci_transfer_pio(host);
2520 
2521                 /*
2522                  * We currently don't do anything fancy with DMA
2523                  * boundaries, but as we can't disable the feature
2524                  * we need to at least restart the transfer.
2525                  *
2526                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2527                  * should return a valid address to continue from, but as
2528                  * some controllers are faulty, don't trust them.
2529                  */
2530                 if (intmask & SDHCI_INT_DMA_END) {
2531                         u32 dmastart, dmanow;
2532                         dmastart = sg_dma_address(host->data->sg);
2533                         dmanow = dmastart + host->data->bytes_xfered;
2534                         /*
2535                          * Force update to the next DMA block boundary.
2536                          */
2537                         dmanow = (dmanow &
2538                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2539                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2540                         host->data->bytes_xfered = dmanow - dmastart;
2541                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2542                                 " next 0x%08x\n",
2543                                 mmc_hostname(host->mmc), dmastart,
2544                                 host->data->bytes_xfered, dmanow);
2545                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2546                 }
2547 
2548                 if (intmask & SDHCI_INT_DATA_END) {
2549                         if (host->cmd) {
2550                                 /*
2551                                  * Data managed to finish before the
2552                                  * command completed. Make sure we do
2553                                  * things in the proper order.
2554                                  */
2555                                 host->data_early = 1;
2556                         } else {
2557                                 sdhci_finish_data(host);
2558                         }
2559                 }
2560         }
2561 }
2562 
2563 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2564 {
2565         irqreturn_t result = IRQ_NONE;
2566         struct sdhci_host *host = dev_id;
2567         u32 intmask, mask, unexpected = 0;
2568         int max_loops = 16;
2569 
2570         spin_lock(&host->lock);
2571 
2572         if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2573                 spin_unlock(&host->lock);
2574                 return IRQ_NONE;
2575         }
2576 
2577         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2578         if (!intmask || intmask == 0xffffffff) {
2579                 result = IRQ_NONE;
2580                 goto out;
2581         }
2582 
2583         do {
2584                 /* Clear selected interrupts. */
2585                 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2586                                   SDHCI_INT_BUS_POWER);
2587                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2588 
2589                 DBG("*** %s got interrupt: 0x%08x\n",
2590                         mmc_hostname(host->mmc), intmask);
2591 
2592                 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2593                         u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2594                                       SDHCI_CARD_PRESENT;
2595 
2596                         /*
2597                          * There is a observation on i.mx esdhc.  INSERT
2598                          * bit will be immediately set again when it gets
2599                          * cleared, if a card is inserted.  We have to mask
2600                          * the irq to prevent interrupt storm which will
2601                          * freeze the system.  And the REMOVE gets the
2602                          * same situation.
2603                          *
2604                          * More testing are needed here to ensure it works
2605                          * for other platforms though.
2606                          */
2607                         host->ier &= ~(SDHCI_INT_CARD_INSERT |
2608                                        SDHCI_INT_CARD_REMOVE);
2609                         host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2610                                                SDHCI_INT_CARD_INSERT;
2611                         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2612                         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2613 
2614                         sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2615                                      SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2616 
2617                         host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2618                                                        SDHCI_INT_CARD_REMOVE);
2619                         result = IRQ_WAKE_THREAD;
2620                 }
2621 
2622                 if (intmask & SDHCI_INT_CMD_MASK)
2623                         sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2624                                       &intmask);
2625 
2626                 if (intmask & SDHCI_INT_DATA_MASK)
2627                         sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2628 
2629                 if (intmask & SDHCI_INT_BUS_POWER)
2630                         pr_err("%s: Card is consuming too much power!\n",
2631                                 mmc_hostname(host->mmc));
2632 
2633                 if (intmask & SDHCI_INT_CARD_INT) {
2634                         sdhci_enable_sdio_irq_nolock(host, false);
2635                         host->thread_isr |= SDHCI_INT_CARD_INT;
2636                         result = IRQ_WAKE_THREAD;
2637                 }
2638 
2639                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2640                              SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2641                              SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2642                              SDHCI_INT_CARD_INT);
2643 
2644                 if (intmask) {
2645                         unexpected |= intmask;
2646                         sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2647                 }
2648 
2649                 if (result == IRQ_NONE)
2650                         result = IRQ_HANDLED;
2651 
2652                 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2653         } while (intmask && --max_loops);
2654 out:
2655         spin_unlock(&host->lock);
2656 
2657         if (unexpected) {
2658                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2659                            mmc_hostname(host->mmc), unexpected);
2660                 sdhci_dumpregs(host);
2661         }
2662 
2663         return result;
2664 }
2665 
2666 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2667 {
2668         struct sdhci_host *host = dev_id;
2669         unsigned long flags;
2670         u32 isr;
2671 
2672         spin_lock_irqsave(&host->lock, flags);
2673         isr = host->thread_isr;
2674         host->thread_isr = 0;
2675         spin_unlock_irqrestore(&host->lock, flags);
2676 
2677         if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2678                 sdhci_card_event(host->mmc);
2679                 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2680         }
2681 
2682         if (isr & SDHCI_INT_CARD_INT) {
2683                 sdio_run_irqs(host->mmc);
2684 
2685                 spin_lock_irqsave(&host->lock, flags);
2686                 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2687                         sdhci_enable_sdio_irq_nolock(host, true);
2688                 spin_unlock_irqrestore(&host->lock, flags);
2689         }
2690 
2691         return isr ? IRQ_HANDLED : IRQ_NONE;
2692 }
2693 
2694 /*****************************************************************************\
2695  *                                                                           *
2696  * Suspend/resume                                                            *
2697  *                                                                           *
2698 \*****************************************************************************/
2699 
2700 #ifdef CONFIG_PM
2701 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2702 {
2703         u8 val;
2704         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2705                         | SDHCI_WAKE_ON_INT;
2706 
2707         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2708         val |= mask ;
2709         /* Avoid fake wake up */
2710         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2711                 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2712         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2713 }
2714 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2715 
2716 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2717 {
2718         u8 val;
2719         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2720                         | SDHCI_WAKE_ON_INT;
2721 
2722         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2723         val &= ~mask;
2724         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2725 }
2726 
2727 int sdhci_suspend_host(struct sdhci_host *host)
2728 {
2729         sdhci_disable_card_detection(host);
2730 
2731         /* Disable tuning since we are suspending */
2732         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2733                 del_timer_sync(&host->tuning_timer);
2734                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2735         }
2736 
2737         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2738                 host->ier = 0;
2739                 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2740                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2741                 free_irq(host->irq, host);
2742         } else {
2743                 sdhci_enable_irq_wakeups(host);
2744                 enable_irq_wake(host->irq);
2745         }
2746         return 0;
2747 }
2748 
2749 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2750 
2751 int sdhci_resume_host(struct sdhci_host *host)
2752 {
2753         int ret = 0;
2754 
2755         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2756                 if (host->ops->enable_dma)
2757                         host->ops->enable_dma(host);
2758         }
2759 
2760         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2761                 ret = request_threaded_irq(host->irq, sdhci_irq,
2762                                            sdhci_thread_irq, IRQF_SHARED,
2763                                            mmc_hostname(host->mmc), host);
2764                 if (ret)
2765                         return ret;
2766         } else {
2767                 sdhci_disable_irq_wakeups(host);
2768                 disable_irq_wake(host->irq);
2769         }
2770 
2771         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2772             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2773                 /* Card keeps power but host controller does not */
2774                 sdhci_init(host, 0);
2775                 host->pwr = 0;
2776                 host->clock = 0;
2777                 sdhci_do_set_ios(host, &host->mmc->ios);
2778         } else {
2779                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2780                 mmiowb();
2781         }
2782 
2783         sdhci_enable_card_detection(host);
2784 
2785         /* Set the re-tuning expiration flag */
2786         if (host->flags & SDHCI_USING_RETUNING_TIMER)
2787                 host->flags |= SDHCI_NEEDS_RETUNING;
2788 
2789         return ret;
2790 }
2791 
2792 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2793 
2794 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2795 {
2796         return pm_runtime_get_sync(host->mmc->parent);
2797 }
2798 
2799 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2800 {
2801         pm_runtime_mark_last_busy(host->mmc->parent);
2802         return pm_runtime_put_autosuspend(host->mmc->parent);
2803 }
2804 
2805 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2806 {
2807         if (host->runtime_suspended || host->bus_on)
2808                 return;
2809         host->bus_on = true;
2810         pm_runtime_get_noresume(host->mmc->parent);
2811 }
2812 
2813 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2814 {
2815         if (host->runtime_suspended || !host->bus_on)
2816                 return;
2817         host->bus_on = false;
2818         pm_runtime_put_noidle(host->mmc->parent);
2819 }
2820 
2821 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2822 {
2823         unsigned long flags;
2824 
2825         /* Disable tuning since we are suspending */
2826         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2827                 del_timer_sync(&host->tuning_timer);
2828                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2829         }
2830 
2831         spin_lock_irqsave(&host->lock, flags);
2832         host->ier &= SDHCI_INT_CARD_INT;
2833         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2834         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2835         spin_unlock_irqrestore(&host->lock, flags);
2836 
2837         synchronize_hardirq(host->irq);
2838 
2839         spin_lock_irqsave(&host->lock, flags);
2840         host->runtime_suspended = true;
2841         spin_unlock_irqrestore(&host->lock, flags);
2842 
2843         return 0;
2844 }
2845 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2846 
2847 int sdhci_runtime_resume_host(struct sdhci_host *host)
2848 {
2849         unsigned long flags;
2850         int host_flags = host->flags;
2851 
2852         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2853                 if (host->ops->enable_dma)
2854                         host->ops->enable_dma(host);
2855         }
2856 
2857         sdhci_init(host, 0);
2858 
2859         /* Force clock and power re-program */
2860         host->pwr = 0;
2861         host->clock = 0;
2862         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2863         sdhci_do_set_ios(host, &host->mmc->ios);
2864 
2865         if ((host_flags & SDHCI_PV_ENABLED) &&
2866                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2867                 spin_lock_irqsave(&host->lock, flags);
2868                 sdhci_enable_preset_value(host, true);
2869                 spin_unlock_irqrestore(&host->lock, flags);
2870         }
2871 
2872         /* Set the re-tuning expiration flag */
2873         if (host->flags & SDHCI_USING_RETUNING_TIMER)
2874                 host->flags |= SDHCI_NEEDS_RETUNING;
2875 
2876         spin_lock_irqsave(&host->lock, flags);
2877 
2878         host->runtime_suspended = false;
2879 
2880         /* Enable SDIO IRQ */
2881         if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2882                 sdhci_enable_sdio_irq_nolock(host, true);
2883 
2884         /* Enable Card Detection */
2885         sdhci_enable_card_detection(host);
2886 
2887         spin_unlock_irqrestore(&host->lock, flags);
2888 
2889         return 0;
2890 }
2891 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2892 
2893 #endif /* CONFIG_PM */
2894 
2895 /*****************************************************************************\
2896  *                                                                           *
2897  * Device allocation/registration                                            *
2898  *                                                                           *
2899 \*****************************************************************************/
2900 
2901 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2902         size_t priv_size)
2903 {
2904         struct mmc_host *mmc;
2905         struct sdhci_host *host;
2906 
2907         WARN_ON(dev == NULL);
2908 
2909         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2910         if (!mmc)
2911                 return ERR_PTR(-ENOMEM);
2912 
2913         host = mmc_priv(mmc);
2914         host->mmc = mmc;
2915 
2916         return host;
2917 }
2918 
2919 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2920 
2921 int sdhci_add_host(struct sdhci_host *host)
2922 {
2923         struct mmc_host *mmc;
2924         u32 caps[2] = {0, 0};
2925         u32 max_current_caps;
2926         unsigned int ocr_avail;
2927         unsigned int override_timeout_clk;
2928         int ret;
2929 
2930         WARN_ON(host == NULL);
2931         if (host == NULL)
2932                 return -EINVAL;
2933 
2934         mmc = host->mmc;
2935 
2936         if (debug_quirks)
2937                 host->quirks = debug_quirks;
2938         if (debug_quirks2)
2939                 host->quirks2 = debug_quirks2;
2940 
2941         override_timeout_clk = host->timeout_clk;
2942 
2943         sdhci_do_reset(host, SDHCI_RESET_ALL);
2944 
2945         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2946         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2947                                 >> SDHCI_SPEC_VER_SHIFT;
2948         if (host->version > SDHCI_SPEC_300) {
2949                 pr_err("%s: Unknown controller version (%d). "
2950                         "You may experience problems.\n", mmc_hostname(mmc),
2951                         host->version);
2952         }
2953 
2954         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2955                 sdhci_readl(host, SDHCI_CAPABILITIES);
2956 
2957         if (host->version >= SDHCI_SPEC_300)
2958                 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2959                         host->caps1 :
2960                         sdhci_readl(host, SDHCI_CAPABILITIES_1);
2961 
2962         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2963                 host->flags |= SDHCI_USE_SDMA;
2964         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2965                 DBG("Controller doesn't have SDMA capability\n");
2966         else
2967                 host->flags |= SDHCI_USE_SDMA;
2968 
2969         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2970                 (host->flags & SDHCI_USE_SDMA)) {
2971                 DBG("Disabling DMA as it is marked broken\n");
2972                 host->flags &= ~SDHCI_USE_SDMA;
2973         }
2974 
2975         if ((host->version >= SDHCI_SPEC_200) &&
2976                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2977                 host->flags |= SDHCI_USE_ADMA;
2978 
2979         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2980                 (host->flags & SDHCI_USE_ADMA)) {
2981                 DBG("Disabling ADMA as it is marked broken\n");
2982                 host->flags &= ~SDHCI_USE_ADMA;
2983         }
2984 
2985         /*
2986          * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2987          * and *must* do 64-bit DMA.  A driver has the opportunity to change
2988          * that during the first call to ->enable_dma().  Similarly
2989          * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2990          * implement.
2991          */
2992         if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
2993                 host->flags |= SDHCI_USE_64_BIT_DMA;
2994 
2995         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2996                 if (host->ops->enable_dma) {
2997                         if (host->ops->enable_dma(host)) {
2998                                 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2999                                         mmc_hostname(mmc));
3000                                 host->flags &=
3001                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3002                         }
3003                 }
3004         }
3005 
3006         /* SDMA does not support 64-bit DMA */
3007         if (host->flags & SDHCI_USE_64_BIT_DMA)
3008                 host->flags &= ~SDHCI_USE_SDMA;
3009 
3010         if (host->flags & SDHCI_USE_ADMA) {
3011                 /*
3012                  * The DMA descriptor table size is calculated as the maximum
3013                  * number of segments times 2, to allow for an alignment
3014                  * descriptor for each segment, plus 1 for a nop end descriptor,
3015                  * all multipled by the descriptor size.
3016                  */
3017                 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3018                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3019                                               SDHCI_ADMA2_64_DESC_SZ;
3020                         host->align_buffer_sz = SDHCI_MAX_SEGS *
3021                                                 SDHCI_ADMA2_64_ALIGN;
3022                         host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
3023                         host->align_sz = SDHCI_ADMA2_64_ALIGN;
3024                         host->align_mask = SDHCI_ADMA2_64_ALIGN - 1;
3025                 } else {
3026                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3027                                               SDHCI_ADMA2_32_DESC_SZ;
3028                         host->align_buffer_sz = SDHCI_MAX_SEGS *
3029                                                 SDHCI_ADMA2_32_ALIGN;
3030                         host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
3031                         host->align_sz = SDHCI_ADMA2_32_ALIGN;
3032                         host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
3033                 }
3034                 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
3035                                                       host->adma_table_sz,
3036                                                       &host->adma_addr,
3037                                                       GFP_KERNEL);
3038                 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
3039                 if (!host->adma_table || !host->align_buffer) {
3040                         dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3041                                           host->adma_table, host->adma_addr);
3042                         kfree(host->align_buffer);
3043                         pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3044                                 mmc_hostname(mmc));
3045                         host->flags &= ~SDHCI_USE_ADMA;
3046                         host->adma_table = NULL;
3047                         host->align_buffer = NULL;
3048                 } else if (host->adma_addr & host->align_mask) {
3049                         pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3050                                 mmc_hostname(mmc));
3051                         host->flags &= ~SDHCI_USE_ADMA;
3052                         dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3053                                           host->adma_table, host->adma_addr);
3054                         kfree(host->align_buffer);
3055                         host->adma_table = NULL;
3056                         host->align_buffer = NULL;
3057                 }
3058         }
3059 
3060         /*
3061          * If we use DMA, then it's up to the caller to set the DMA
3062          * mask, but PIO does not need the hw shim so we set a new
3063          * mask here in that case.
3064          */
3065         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3066                 host->dma_mask = DMA_BIT_MASK(64);
3067                 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3068         }
3069 
3070         if (host->version >= SDHCI_SPEC_300)
3071                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
3072                         >> SDHCI_CLOCK_BASE_SHIFT;
3073         else
3074                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
3075                         >> SDHCI_CLOCK_BASE_SHIFT;
3076 
3077         host->max_clk *= 1000000;
3078         if (host->max_clk == 0 || host->quirks &
3079                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3080                 if (!host->ops->get_max_clock) {
3081                         pr_err("%s: Hardware doesn't specify base clock "
3082                                "frequency.\n", mmc_hostname(mmc));
3083                         return -ENODEV;
3084                 }
3085                 host->max_clk = host->ops->get_max_clock(host);
3086         }
3087 
3088         host->next_data.cookie = 1;
3089         /*
3090          * In case of Host Controller v3.00, find out whether clock
3091          * multiplier is supported.
3092          */
3093         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3094                         SDHCI_CLOCK_MUL_SHIFT;
3095 
3096         /*
3097          * In case the value in Clock Multiplier is 0, then programmable
3098          * clock mode is not supported, otherwise the actual clock
3099          * multiplier is one more than the value of Clock Multiplier
3100          * in the Capabilities Register.
3101          */
3102         if (host->clk_mul)
3103                 host->clk_mul += 1;
3104 
3105         /*
3106          * Set host parameters.
3107          */
3108         mmc->ops = &sdhci_ops;
3109         mmc->f_max = host->max_clk;
3110         if (host->ops->get_min_clock)
3111                 mmc->f_min = host->ops->get_min_clock(host);
3112         else if (host->version >= SDHCI_SPEC_300) {
3113                 if (host->clk_mul) {
3114                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3115                         mmc->f_max = host->max_clk * host->clk_mul;
3116                 } else
3117                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3118         } else
3119                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3120 
3121         if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3122                 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3123                                         SDHCI_TIMEOUT_CLK_SHIFT;
3124                 if (host->timeout_clk == 0) {
3125                         if (host->ops->get_timeout_clock) {
3126                                 host->timeout_clk =
3127                                         host->ops->get_timeout_clock(host);
3128                         } else {
3129                                 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3130                                         mmc_hostname(mmc));
3131                                 return -ENODEV;
3132                         }
3133                 }
3134 
3135                 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3136                         host->timeout_clk *= 1000;
3137 
3138                 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3139                         host->ops->get_max_timeout_count(host) : 1 << 27;
3140                 mmc->max_busy_timeout /= host->timeout_clk;
3141         }
3142 
3143         if (override_timeout_clk)
3144                 host->timeout_clk = override_timeout_clk;
3145 
3146         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3147         mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3148 
3149         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3150                 host->flags |= SDHCI_AUTO_CMD12;
3151 
3152         /* Auto-CMD23 stuff only works in ADMA or PIO. */
3153         if ((host->version >= SDHCI_SPEC_300) &&
3154             ((host->flags & SDHCI_USE_ADMA) ||
3155              !(host->flags & SDHCI_USE_SDMA)) &&
3156              !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3157                 host->flags |= SDHCI_AUTO_CMD23;
3158                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3159         } else {
3160                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3161         }
3162 
3163         /*
3164          * A controller may support 8-bit width, but the board itself
3165          * might not have the pins brought out.  Boards that support
3166          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3167          * their platform code before calling sdhci_add_host(), and we
3168          * won't assume 8-bit width for hosts without that CAP.
3169          */
3170         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3171                 mmc->caps |= MMC_CAP_4_BIT_DATA;
3172 
3173         if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3174                 mmc->caps &= ~MMC_CAP_CMD23;
3175 
3176         if (caps[0] & SDHCI_CAN_DO_HISPD)
3177                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3178 
3179         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3180             !(mmc->caps & MMC_CAP_NONREMOVABLE))
3181                 mmc->caps |= MMC_CAP_NEEDS_POLL;
3182 
3183         /* If there are external regulators, get them */
3184         if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3185                 return -EPROBE_DEFER;
3186 
3187         /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3188         if (!IS_ERR(mmc->supply.vqmmc)) {
3189                 ret = regulator_enable(mmc->supply.vqmmc);
3190                 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3191                                                     1950000))
3192                         caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3193                                         SDHCI_SUPPORT_SDR50 |
3194                                         SDHCI_SUPPORT_DDR50);
3195                 if (ret) {
3196                         pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3197                                 mmc_hostname(mmc), ret);
3198                         mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3199                 }
3200         }
3201 
3202         if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3203                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3204                        SDHCI_SUPPORT_DDR50);
3205 
3206         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3207         if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3208                        SDHCI_SUPPORT_DDR50))
3209                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3210 
3211         /* SDR104 supports also implies SDR50 support */
3212         if (caps[1] & SDHCI_SUPPORT_SDR104) {
3213                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3214                 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3215                  * field can be promoted to support HS200.
3216                  */
3217                 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3218                         mmc->caps2 |= MMC_CAP2_HS200;
3219         } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3220                 mmc->caps |= MMC_CAP_UHS_SDR50;
3221 
3222         if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3223             (caps[1] & SDHCI_SUPPORT_HS400))
3224                 mmc->caps2 |= MMC_CAP2_HS400;
3225 
3226         if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3227             (IS_ERR(mmc->supply.vqmmc) ||
3228              !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3229                                              1300000)))
3230                 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3231 
3232         if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3233                 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3234                 mmc->caps |= MMC_CAP_UHS_DDR50;
3235 
3236         /* Does the host need tuning for SDR50? */
3237         if (caps[1] & SDHCI_USE_SDR50_TUNING)
3238                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3239 
3240         /* Does the host need tuning for SDR104 / HS200? */
3241         if (mmc->caps2 & MMC_CAP2_HS200)
3242                 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3243 
3244         /* Driver Type(s) (A, C, D) supported by the host */
3245         if (caps[1] & SDHCI_DRIVER_TYPE_A)
3246                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3247         if (caps[1] & SDHCI_DRIVER_TYPE_C)
3248                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3249         if (caps[1] & SDHCI_DRIVER_TYPE_D)
3250                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3251 
3252         /* Initial value for re-tuning timer count */
3253         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3254                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3255 
3256         /*
3257          * In case Re-tuning Timer is not disabled, the actual value of
3258          * re-tuning timer will be 2 ^ (n - 1).
3259          */
3260         if (host->tuning_count)
3261                 host->tuning_count = 1 << (host->tuning_count - 1);
3262 
3263         /* Re-tuning mode supported by the Host Controller */
3264         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3265                              SDHCI_RETUNING_MODE_SHIFT;
3266 
3267         ocr_avail = 0;
3268 
3269         /*
3270          * According to SD Host Controller spec v3.00, if the Host System
3271          * can afford more than 150mA, Host Driver should set XPC to 1. Also
3272          * the value is meaningful only if Voltage Support in the Capabilities
3273          * register is set. The actual current value is 4 times the register
3274          * value.
3275          */
3276         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3277         if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3278                 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3279                 if (curr > 0) {
3280 
3281                         /* convert to SDHCI_MAX_CURRENT format */
3282                         curr = curr/1000;  /* convert to mA */
3283                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3284 
3285                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3286                         max_current_caps =
3287                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3288                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3289                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3290                 }
3291         }
3292 
3293         if (caps[0] & SDHCI_CAN_VDD_330) {
3294                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3295 
3296                 mmc->max_current_330 = ((max_current_caps &
3297                                    SDHCI_MAX_CURRENT_330_MASK) >>
3298                                    SDHCI_MAX_CURRENT_330_SHIFT) *
3299                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3300         }
3301         if (caps[0] & SDHCI_CAN_VDD_300) {
3302                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3303 
3304                 mmc->max_current_300 = ((max_current_caps &
3305                                    SDHCI_MAX_CURRENT_300_MASK) >>
3306                                    SDHCI_MAX_CURRENT_300_SHIFT) *
3307                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3308         }
3309         if (caps[0] & SDHCI_CAN_VDD_180) {
3310                 ocr_avail |= MMC_VDD_165_195;
3311 
3312                 mmc->max_current_180 = ((max_current_caps &
3313                                    SDHCI_MAX_CURRENT_180_MASK) >>
3314                                    SDHCI_MAX_CURRENT_180_SHIFT) *
3315                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3316         }
3317 
3318         /* If OCR set by external regulators, use it instead */
3319         if (mmc->ocr_avail)
3320                 ocr_avail = mmc->ocr_avail;
3321 
3322         if (host->ocr_mask)
3323                 ocr_avail &= host->ocr_mask;
3324 
3325         mmc->ocr_avail = ocr_avail;
3326         mmc->ocr_avail_sdio = ocr_avail;
3327         if (host->ocr_avail_sdio)
3328                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3329         mmc->ocr_avail_sd = ocr_avail;
3330         if (host->ocr_avail_sd)
3331                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3332         else /* normal SD controllers don't support 1.8V */
3333                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3334         mmc->ocr_avail_mmc = ocr_avail;
3335         if (host->ocr_avail_mmc)
3336                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3337 
3338         if (mmc->ocr_avail == 0) {
3339                 pr_err("%s: Hardware doesn't report any "
3340                         "support voltages.\n", mmc_hostname(mmc));
3341                 return -ENODEV;
3342         }
3343 
3344         spin_lock_init(&host->lock);
3345 
3346         /*
3347          * Maximum number of segments. Depends on if the hardware
3348          * can do scatter/gather or not.
3349          */
3350         if (host->flags & SDHCI_USE_ADMA)
3351                 mmc->max_segs = SDHCI_MAX_SEGS;
3352         else if (host->flags & SDHCI_USE_SDMA)
3353                 mmc->max_segs = 1;
3354         else /* PIO */
3355                 mmc->max_segs = SDHCI_MAX_SEGS;
3356 
3357         /*
3358          * Maximum number of sectors in one transfer. Limited by SDMA boundary
3359          * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3360          * is less anyway.
3361          */
3362         mmc->max_req_size = 524288;
3363 
3364         /*
3365          * Maximum segment size. Could be one segment with the maximum number
3366          * of bytes. When doing hardware scatter/gather, each entry cannot
3367          * be larger than 64 KiB though.
3368          */
3369         if (host->flags & SDHCI_USE_ADMA) {
3370                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3371                         mmc->max_seg_size = 65535;
3372                 else
3373                         mmc->max_seg_size = 65536;
3374         } else {
3375                 mmc->max_seg_size = mmc->max_req_size;
3376         }
3377 
3378         /*
3379          * Maximum block size. This varies from controller to controller and
3380          * is specified in the capabilities register.
3381          */
3382         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3383                 mmc->max_blk_size = 2;
3384         } else {
3385                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3386                                 SDHCI_MAX_BLOCK_SHIFT;
3387                 if (mmc->max_blk_size >= 3) {
3388                         pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3389                                 mmc_hostname(mmc));
3390                         mmc->max_blk_size = 0;
3391                 }
3392         }
3393 
3394         mmc->max_blk_size = 512 << mmc->max_blk_size;
3395 
3396         /*
3397          * Maximum block count.
3398          */
3399         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3400 
3401         /*
3402          * Init tasklets.
3403          */
3404         tasklet_init(&host->finish_tasklet,
3405                 sdhci_tasklet_finish, (unsigned long)host);
3406 
3407         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3408 
3409         init_waitqueue_head(&host->buf_ready_int);
3410 
3411         if (host->version >= SDHCI_SPEC_300) {
3412                 /* Initialize re-tuning timer */
3413                 init_timer(&host->tuning_timer);
3414                 host->tuning_timer.data = (unsigned long)host;
3415                 host->tuning_timer.function = sdhci_tuning_timer;
3416         }
3417 
3418         sdhci_init(host, 0);
3419 
3420         ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3421                                    IRQF_SHARED, mmc_hostname(mmc), host);
3422         if (ret) {
3423                 pr_err("%s: Failed to request IRQ %d: %d\n",
3424                        mmc_hostname(mmc), host->irq, ret);
3425                 goto untasklet;
3426         }
3427 
3428 #ifdef CONFIG_MMC_DEBUG
3429         sdhci_dumpregs(host);
3430 #endif
3431 
3432 #ifdef SDHCI_USE_LEDS_CLASS
3433         snprintf(host->led_name, sizeof(host->led_name),
3434                 "%s::", mmc_hostname(mmc));
3435         host->led.name = host->led_name;
3436         host->led.brightness = LED_OFF;
3437         host->led.default_trigger = mmc_hostname(mmc);
3438         host->led.brightness_set = sdhci_led_control;
3439 
3440         ret = led_classdev_register(mmc_dev(mmc), &host->led);
3441         if (ret) {
3442                 pr_err("%s: Failed to register LED device: %d\n",
3443                        mmc_hostname(mmc), ret);
3444                 goto reset;
3445         }
3446 #endif
3447 
3448         mmiowb();
3449 
3450         mmc_add_host(mmc);
3451 
3452         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3453                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3454                 (host->flags & SDHCI_USE_ADMA) ?
3455                 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3456                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3457 
3458         sdhci_enable_card_detection(host);
3459 
3460         return 0;
3461 
3462 #ifdef SDHCI_USE_LEDS_CLASS
3463 reset:
3464         sdhci_do_reset(host, SDHCI_RESET_ALL);
3465         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3466         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3467         free_irq(host->irq, host);
3468 #endif
3469 untasklet:
3470         tasklet_kill(&host->finish_tasklet);
3471 
3472         return ret;
3473 }
3474 
3475 EXPORT_SYMBOL_GPL(sdhci_add_host);
3476 
3477 void sdhci_remove_host(struct sdhci_host *host, int dead)
3478 {
3479         struct mmc_host *mmc = host->mmc;
3480         unsigned long flags;
3481 
3482         if (dead) {
3483                 spin_lock_irqsave(&host->lock, flags);
3484 
3485                 host->flags |= SDHCI_DEVICE_DEAD;
3486 
3487                 if (host->mrq) {
3488                         pr_err("%s: Controller removed during "
3489                                 " transfer!\n", mmc_hostname(mmc));
3490 
3491                         host->mrq->cmd->error = -ENOMEDIUM;
3492                         tasklet_schedule(&host->finish_tasklet);
3493                 }
3494 
3495                 spin_unlock_irqrestore(&host->lock, flags);
3496         }
3497 
3498         sdhci_disable_card_detection(host);
3499 
3500         mmc_remove_host(mmc);
3501 
3502 #ifdef SDHCI_USE_LEDS_CLASS
3503         led_classdev_unregister(&host->led);
3504 #endif
3505 
3506         if (!dead)
3507                 sdhci_do_reset(host, SDHCI_RESET_ALL);
3508 
3509         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3510         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3511         free_irq(host->irq, host);
3512 
3513         del_timer_sync(&host->timer);
3514 
3515         tasklet_kill(&host->finish_tasklet);
3516 
3517         if (!IS_ERR(mmc->supply.vqmmc))
3518                 regulator_disable(mmc->supply.vqmmc);
3519 
3520         if (host->adma_table)
3521                 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3522                                   host->adma_table, host->adma_addr);
3523         kfree(host->align_buffer);
3524 
3525         host->adma_table = NULL;
3526         host->align_buffer = NULL;
3527 }
3528 
3529 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3530 
3531 void sdhci_free_host(struct sdhci_host *host)
3532 {
3533         mmc_free_host(host->mmc);
3534 }
3535 
3536 EXPORT_SYMBOL_GPL(sdhci_free_host);
3537 
3538 /*****************************************************************************\
3539  *                                                                           *
3540  * Driver init/exit                                                          *
3541  *                                                                           *
3542 \*****************************************************************************/
3543 
3544 static int __init sdhci_drv_init(void)
3545 {
3546         pr_info(DRIVER_NAME
3547                 ": Secure Digital Host Controller Interface driver\n");
3548         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3549 
3550         return 0;
3551 }
3552 
3553 static void __exit sdhci_drv_exit(void)
3554 {
3555 }
3556 
3557 module_init(sdhci_drv_init);
3558 module_exit(sdhci_drv_exit);
3559 
3560 module_param(debug_quirks, uint, 0444);
3561 module_param(debug_quirks2, uint, 0444);
3562 
3563 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3564 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3565 MODULE_LICENSE("GPL");
3566 
3567 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3568 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
3569 

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