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Linux/drivers/mmc/host/sdhci.c

  1 /*
  2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
  3  *
  4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License as published by
  8  * the Free Software Foundation; either version 2 of the License, or (at
  9  * your option) any later version.
 10  *
 11  * Thanks to the following companies for their support:
 12  *
 13  *     - JMicron (hardware and technical support)
 14  */
 15 
 16 #include <linux/delay.h>
 17 #include <linux/highmem.h>
 18 #include <linux/io.h>
 19 #include <linux/module.h>
 20 #include <linux/dma-mapping.h>
 21 #include <linux/slab.h>
 22 #include <linux/scatterlist.h>
 23 #include <linux/regulator/consumer.h>
 24 #include <linux/pm_runtime.h>
 25 
 26 #include <linux/leds.h>
 27 
 28 #include <linux/mmc/mmc.h>
 29 #include <linux/mmc/host.h>
 30 #include <linux/mmc/card.h>
 31 #include <linux/mmc/slot-gpio.h>
 32 
 33 #include "sdhci.h"
 34 
 35 #define DRIVER_NAME "sdhci"
 36 
 37 #define DBG(f, x...) \
 38         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
 39 
 40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
 41         defined(CONFIG_MMC_SDHCI_MODULE))
 42 #define SDHCI_USE_LEDS_CLASS
 43 #endif
 44 
 45 #define MAX_TUNING_LOOP 40
 46 
 47 #define ADMA_SIZE       ((128 * 2 + 1) * 4)
 48 
 49 static unsigned int debug_quirks = 0;
 50 static unsigned int debug_quirks2;
 51 
 52 static void sdhci_finish_data(struct sdhci_host *);
 53 
 54 static void sdhci_finish_command(struct sdhci_host *);
 55 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
 56 static void sdhci_tuning_timer(unsigned long data);
 57 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
 58 
 59 #ifdef CONFIG_PM_RUNTIME
 60 static int sdhci_runtime_pm_get(struct sdhci_host *host);
 61 static int sdhci_runtime_pm_put(struct sdhci_host *host);
 62 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
 63 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
 64 #else
 65 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
 66 {
 67         return 0;
 68 }
 69 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
 70 {
 71         return 0;
 72 }
 73 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
 74 {
 75 }
 76 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
 77 {
 78 }
 79 #endif
 80 
 81 static void sdhci_dumpregs(struct sdhci_host *host)
 82 {
 83         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
 84                 mmc_hostname(host->mmc));
 85 
 86         pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
 87                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
 88                 sdhci_readw(host, SDHCI_HOST_VERSION));
 89         pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
 90                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
 91                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
 92         pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
 93                 sdhci_readl(host, SDHCI_ARGUMENT),
 94                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
 95         pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
 96                 sdhci_readl(host, SDHCI_PRESENT_STATE),
 97                 sdhci_readb(host, SDHCI_HOST_CONTROL));
 98         pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
 99                 sdhci_readb(host, SDHCI_POWER_CONTROL),
100                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
101         pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
102                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
103                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
104         pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
105                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
106                 sdhci_readl(host, SDHCI_INT_STATUS));
107         pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
108                 sdhci_readl(host, SDHCI_INT_ENABLE),
109                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
110         pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
111                 sdhci_readw(host, SDHCI_ACMD12_ERR),
112                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
113         pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
114                 sdhci_readl(host, SDHCI_CAPABILITIES),
115                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
116         pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
117                 sdhci_readw(host, SDHCI_COMMAND),
118                 sdhci_readl(host, SDHCI_MAX_CURRENT));
119         pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
120                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
121 
122         if (host->flags & SDHCI_USE_ADMA)
123                 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
124                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
125                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
126 
127         pr_debug(DRIVER_NAME ": ===========================================\n");
128 }
129 
130 /*****************************************************************************\
131  *                                                                           *
132  * Low level functions                                                       *
133  *                                                                           *
134 \*****************************************************************************/
135 
136 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
137 {
138         u32 present;
139 
140         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
141             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
142                 return;
143 
144         if (enable) {
145                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
146                                       SDHCI_CARD_PRESENT;
147 
148                 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
149                                        SDHCI_INT_CARD_INSERT;
150         } else {
151                 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
152         }
153 
154         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
155         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
156 }
157 
158 static void sdhci_enable_card_detection(struct sdhci_host *host)
159 {
160         sdhci_set_card_detection(host, true);
161 }
162 
163 static void sdhci_disable_card_detection(struct sdhci_host *host)
164 {
165         sdhci_set_card_detection(host, false);
166 }
167 
168 void sdhci_reset(struct sdhci_host *host, u8 mask)
169 {
170         unsigned long timeout;
171 
172         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
173 
174         if (mask & SDHCI_RESET_ALL) {
175                 host->clock = 0;
176                 /* Reset-all turns off SD Bus Power */
177                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
178                         sdhci_runtime_pm_bus_off(host);
179         }
180 
181         /* Wait max 100 ms */
182         timeout = 100;
183 
184         /* hw clears the bit when it's done */
185         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
186                 if (timeout == 0) {
187                         pr_err("%s: Reset 0x%x never completed.\n",
188                                 mmc_hostname(host->mmc), (int)mask);
189                         sdhci_dumpregs(host);
190                         return;
191                 }
192                 timeout--;
193                 mdelay(1);
194         }
195 }
196 EXPORT_SYMBOL_GPL(sdhci_reset);
197 
198 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
199 {
200         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
201                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
202                         SDHCI_CARD_PRESENT))
203                         return;
204         }
205 
206         host->ops->reset(host, mask);
207 
208         if (mask & SDHCI_RESET_ALL) {
209                 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
210                         if (host->ops->enable_dma)
211                                 host->ops->enable_dma(host);
212                 }
213 
214                 /* Resetting the controller clears many */
215                 host->preset_enabled = false;
216         }
217 }
218 
219 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
220 
221 static void sdhci_init(struct sdhci_host *host, int soft)
222 {
223         if (soft)
224                 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
225         else
226                 sdhci_do_reset(host, SDHCI_RESET_ALL);
227 
228         host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
229                     SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
230                     SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
231                     SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
232                     SDHCI_INT_RESPONSE;
233 
234         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
235         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
236 
237         if (soft) {
238                 /* force clock reconfiguration */
239                 host->clock = 0;
240                 sdhci_set_ios(host->mmc, &host->mmc->ios);
241         }
242 }
243 
244 static void sdhci_reinit(struct sdhci_host *host)
245 {
246         sdhci_init(host, 0);
247         /*
248          * Retuning stuffs are affected by different cards inserted and only
249          * applicable to UHS-I cards. So reset these fields to their initial
250          * value when card is removed.
251          */
252         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
253                 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
254 
255                 del_timer_sync(&host->tuning_timer);
256                 host->flags &= ~SDHCI_NEEDS_RETUNING;
257                 host->mmc->max_blk_count =
258                         (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
259         }
260         sdhci_enable_card_detection(host);
261 }
262 
263 static void sdhci_activate_led(struct sdhci_host *host)
264 {
265         u8 ctrl;
266 
267         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
268         ctrl |= SDHCI_CTRL_LED;
269         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
270 }
271 
272 static void sdhci_deactivate_led(struct sdhci_host *host)
273 {
274         u8 ctrl;
275 
276         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
277         ctrl &= ~SDHCI_CTRL_LED;
278         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
279 }
280 
281 #ifdef SDHCI_USE_LEDS_CLASS
282 static void sdhci_led_control(struct led_classdev *led,
283         enum led_brightness brightness)
284 {
285         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
286         unsigned long flags;
287 
288         spin_lock_irqsave(&host->lock, flags);
289 
290         if (host->runtime_suspended)
291                 goto out;
292 
293         if (brightness == LED_OFF)
294                 sdhci_deactivate_led(host);
295         else
296                 sdhci_activate_led(host);
297 out:
298         spin_unlock_irqrestore(&host->lock, flags);
299 }
300 #endif
301 
302 /*****************************************************************************\
303  *                                                                           *
304  * Core functions                                                            *
305  *                                                                           *
306 \*****************************************************************************/
307 
308 static void sdhci_read_block_pio(struct sdhci_host *host)
309 {
310         unsigned long flags;
311         size_t blksize, len, chunk;
312         u32 uninitialized_var(scratch);
313         u8 *buf;
314 
315         DBG("PIO reading\n");
316 
317         blksize = host->data->blksz;
318         chunk = 0;
319 
320         local_irq_save(flags);
321 
322         while (blksize) {
323                 if (!sg_miter_next(&host->sg_miter))
324                         BUG();
325 
326                 len = min(host->sg_miter.length, blksize);
327 
328                 blksize -= len;
329                 host->sg_miter.consumed = len;
330 
331                 buf = host->sg_miter.addr;
332 
333                 while (len) {
334                         if (chunk == 0) {
335                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
336                                 chunk = 4;
337                         }
338 
339                         *buf = scratch & 0xFF;
340 
341                         buf++;
342                         scratch >>= 8;
343                         chunk--;
344                         len--;
345                 }
346         }
347 
348         sg_miter_stop(&host->sg_miter);
349 
350         local_irq_restore(flags);
351 }
352 
353 static void sdhci_write_block_pio(struct sdhci_host *host)
354 {
355         unsigned long flags;
356         size_t blksize, len, chunk;
357         u32 scratch;
358         u8 *buf;
359 
360         DBG("PIO writing\n");
361 
362         blksize = host->data->blksz;
363         chunk = 0;
364         scratch = 0;
365 
366         local_irq_save(flags);
367 
368         while (blksize) {
369                 if (!sg_miter_next(&host->sg_miter))
370                         BUG();
371 
372                 len = min(host->sg_miter.length, blksize);
373 
374                 blksize -= len;
375                 host->sg_miter.consumed = len;
376 
377                 buf = host->sg_miter.addr;
378 
379                 while (len) {
380                         scratch |= (u32)*buf << (chunk * 8);
381 
382                         buf++;
383                         chunk++;
384                         len--;
385 
386                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
387                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
388                                 chunk = 0;
389                                 scratch = 0;
390                         }
391                 }
392         }
393 
394         sg_miter_stop(&host->sg_miter);
395 
396         local_irq_restore(flags);
397 }
398 
399 static void sdhci_transfer_pio(struct sdhci_host *host)
400 {
401         u32 mask;
402 
403         BUG_ON(!host->data);
404 
405         if (host->blocks == 0)
406                 return;
407 
408         if (host->data->flags & MMC_DATA_READ)
409                 mask = SDHCI_DATA_AVAILABLE;
410         else
411                 mask = SDHCI_SPACE_AVAILABLE;
412 
413         /*
414          * Some controllers (JMicron JMB38x) mess up the buffer bits
415          * for transfers < 4 bytes. As long as it is just one block,
416          * we can ignore the bits.
417          */
418         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
419                 (host->data->blocks == 1))
420                 mask = ~0;
421 
422         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
423                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
424                         udelay(100);
425 
426                 if (host->data->flags & MMC_DATA_READ)
427                         sdhci_read_block_pio(host);
428                 else
429                         sdhci_write_block_pio(host);
430 
431                 host->blocks--;
432                 if (host->blocks == 0)
433                         break;
434         }
435 
436         DBG("PIO transfer complete.\n");
437 }
438 
439 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
440 {
441         local_irq_save(*flags);
442         return kmap_atomic(sg_page(sg)) + sg->offset;
443 }
444 
445 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
446 {
447         kunmap_atomic(buffer);
448         local_irq_restore(*flags);
449 }
450 
451 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
452 {
453         __le32 *dataddr = (__le32 __force *)(desc + 4);
454         __le16 *cmdlen = (__le16 __force *)desc;
455 
456         /* SDHCI specification says ADMA descriptors should be 4 byte
457          * aligned, so using 16 or 32bit operations should be safe. */
458 
459         cmdlen[0] = cpu_to_le16(cmd);
460         cmdlen[1] = cpu_to_le16(len);
461 
462         dataddr[0] = cpu_to_le32(addr);
463 }
464 
465 static int sdhci_adma_table_pre(struct sdhci_host *host,
466         struct mmc_data *data)
467 {
468         int direction;
469 
470         u8 *desc;
471         u8 *align;
472         dma_addr_t addr;
473         dma_addr_t align_addr;
474         int len, offset;
475 
476         struct scatterlist *sg;
477         int i;
478         char *buffer;
479         unsigned long flags;
480 
481         /*
482          * The spec does not specify endianness of descriptor table.
483          * We currently guess that it is LE.
484          */
485 
486         if (data->flags & MMC_DATA_READ)
487                 direction = DMA_FROM_DEVICE;
488         else
489                 direction = DMA_TO_DEVICE;
490 
491         host->align_addr = dma_map_single(mmc_dev(host->mmc),
492                 host->align_buffer, 128 * 4, direction);
493         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
494                 goto fail;
495         BUG_ON(host->align_addr & 0x3);
496 
497         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
498                 data->sg, data->sg_len, direction);
499         if (host->sg_count == 0)
500                 goto unmap_align;
501 
502         desc = host->adma_desc;
503         align = host->align_buffer;
504 
505         align_addr = host->align_addr;
506 
507         for_each_sg(data->sg, sg, host->sg_count, i) {
508                 addr = sg_dma_address(sg);
509                 len = sg_dma_len(sg);
510 
511                 /*
512                  * The SDHCI specification states that ADMA
513                  * addresses must be 32-bit aligned. If they
514                  * aren't, then we use a bounce buffer for
515                  * the (up to three) bytes that screw up the
516                  * alignment.
517                  */
518                 offset = (4 - (addr & 0x3)) & 0x3;
519                 if (offset) {
520                         if (data->flags & MMC_DATA_WRITE) {
521                                 buffer = sdhci_kmap_atomic(sg, &flags);
522                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
523                                 memcpy(align, buffer, offset);
524                                 sdhci_kunmap_atomic(buffer, &flags);
525                         }
526 
527                         /* tran, valid */
528                         sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
529 
530                         BUG_ON(offset > 65536);
531 
532                         align += 4;
533                         align_addr += 4;
534 
535                         desc += 8;
536 
537                         addr += offset;
538                         len -= offset;
539                 }
540 
541                 BUG_ON(len > 65536);
542 
543                 /* tran, valid */
544                 sdhci_set_adma_desc(desc, addr, len, 0x21);
545                 desc += 8;
546 
547                 /*
548                  * If this triggers then we have a calculation bug
549                  * somewhere. :/
550                  */
551                 WARN_ON((desc - host->adma_desc) > ADMA_SIZE);
552         }
553 
554         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
555                 /*
556                 * Mark the last descriptor as the terminating descriptor
557                 */
558                 if (desc != host->adma_desc) {
559                         desc -= 8;
560                         desc[0] |= 0x2; /* end */
561                 }
562         } else {
563                 /*
564                 * Add a terminating entry.
565                 */
566 
567                 /* nop, end, valid */
568                 sdhci_set_adma_desc(desc, 0, 0, 0x3);
569         }
570 
571         /*
572          * Resync align buffer as we might have changed it.
573          */
574         if (data->flags & MMC_DATA_WRITE) {
575                 dma_sync_single_for_device(mmc_dev(host->mmc),
576                         host->align_addr, 128 * 4, direction);
577         }
578 
579         return 0;
580 
581 unmap_align:
582         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
583                 128 * 4, direction);
584 fail:
585         return -EINVAL;
586 }
587 
588 static void sdhci_adma_table_post(struct sdhci_host *host,
589         struct mmc_data *data)
590 {
591         int direction;
592 
593         struct scatterlist *sg;
594         int i, size;
595         u8 *align;
596         char *buffer;
597         unsigned long flags;
598         bool has_unaligned;
599 
600         if (data->flags & MMC_DATA_READ)
601                 direction = DMA_FROM_DEVICE;
602         else
603                 direction = DMA_TO_DEVICE;
604 
605         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
606                 128 * 4, direction);
607 
608         /* Do a quick scan of the SG list for any unaligned mappings */
609         has_unaligned = false;
610         for_each_sg(data->sg, sg, host->sg_count, i)
611                 if (sg_dma_address(sg) & 3) {
612                         has_unaligned = true;
613                         break;
614                 }
615 
616         if (has_unaligned && data->flags & MMC_DATA_READ) {
617                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
618                         data->sg_len, direction);
619 
620                 align = host->align_buffer;
621 
622                 for_each_sg(data->sg, sg, host->sg_count, i) {
623                         if (sg_dma_address(sg) & 0x3) {
624                                 size = 4 - (sg_dma_address(sg) & 0x3);
625 
626                                 buffer = sdhci_kmap_atomic(sg, &flags);
627                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
628                                 memcpy(buffer, align, size);
629                                 sdhci_kunmap_atomic(buffer, &flags);
630 
631                                 align += 4;
632                         }
633                 }
634         }
635 
636         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
637                 data->sg_len, direction);
638 }
639 
640 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
641 {
642         u8 count;
643         struct mmc_data *data = cmd->data;
644         unsigned target_timeout, current_timeout;
645 
646         /*
647          * If the host controller provides us with an incorrect timeout
648          * value, just skip the check and use 0xE.  The hardware may take
649          * longer to time out, but that's much better than having a too-short
650          * timeout value.
651          */
652         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
653                 return 0xE;
654 
655         /* Unspecified timeout, assume max */
656         if (!data && !cmd->busy_timeout)
657                 return 0xE;
658 
659         /* timeout in us */
660         if (!data)
661                 target_timeout = cmd->busy_timeout * 1000;
662         else {
663                 target_timeout = data->timeout_ns / 1000;
664                 if (host->clock)
665                         target_timeout += data->timeout_clks / host->clock;
666         }
667 
668         /*
669          * Figure out needed cycles.
670          * We do this in steps in order to fit inside a 32 bit int.
671          * The first step is the minimum timeout, which will have a
672          * minimum resolution of 6 bits:
673          * (1) 2^13*1000 > 2^22,
674          * (2) host->timeout_clk < 2^16
675          *     =>
676          *     (1) / (2) > 2^6
677          */
678         count = 0;
679         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
680         while (current_timeout < target_timeout) {
681                 count++;
682                 current_timeout <<= 1;
683                 if (count >= 0xF)
684                         break;
685         }
686 
687         if (count >= 0xF) {
688                 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
689                     mmc_hostname(host->mmc), count, cmd->opcode);
690                 count = 0xE;
691         }
692 
693         return count;
694 }
695 
696 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
697 {
698         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
699         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
700 
701         if (host->flags & SDHCI_REQ_USE_DMA)
702                 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
703         else
704                 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
705 
706         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
707         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
708 }
709 
710 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
711 {
712         u8 count;
713         u8 ctrl;
714         struct mmc_data *data = cmd->data;
715         int ret;
716 
717         WARN_ON(host->data);
718 
719         if (data || (cmd->flags & MMC_RSP_BUSY)) {
720                 count = sdhci_calc_timeout(host, cmd);
721                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
722         }
723 
724         if (!data)
725                 return;
726 
727         /* Sanity checks */
728         BUG_ON(data->blksz * data->blocks > 524288);
729         BUG_ON(data->blksz > host->mmc->max_blk_size);
730         BUG_ON(data->blocks > 65535);
731 
732         host->data = data;
733         host->data_early = 0;
734         host->data->bytes_xfered = 0;
735 
736         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
737                 host->flags |= SDHCI_REQ_USE_DMA;
738 
739         /*
740          * FIXME: This doesn't account for merging when mapping the
741          * scatterlist.
742          */
743         if (host->flags & SDHCI_REQ_USE_DMA) {
744                 int broken, i;
745                 struct scatterlist *sg;
746 
747                 broken = 0;
748                 if (host->flags & SDHCI_USE_ADMA) {
749                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
750                                 broken = 1;
751                 } else {
752                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
753                                 broken = 1;
754                 }
755 
756                 if (unlikely(broken)) {
757                         for_each_sg(data->sg, sg, data->sg_len, i) {
758                                 if (sg->length & 0x3) {
759                                         DBG("Reverting to PIO because of "
760                                                 "transfer size (%d)\n",
761                                                 sg->length);
762                                         host->flags &= ~SDHCI_REQ_USE_DMA;
763                                         break;
764                                 }
765                         }
766                 }
767         }
768 
769         /*
770          * The assumption here being that alignment is the same after
771          * translation to device address space.
772          */
773         if (host->flags & SDHCI_REQ_USE_DMA) {
774                 int broken, i;
775                 struct scatterlist *sg;
776 
777                 broken = 0;
778                 if (host->flags & SDHCI_USE_ADMA) {
779                         /*
780                          * As we use 3 byte chunks to work around
781                          * alignment problems, we need to check this
782                          * quirk.
783                          */
784                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
785                                 broken = 1;
786                 } else {
787                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
788                                 broken = 1;
789                 }
790 
791                 if (unlikely(broken)) {
792                         for_each_sg(data->sg, sg, data->sg_len, i) {
793                                 if (sg->offset & 0x3) {
794                                         DBG("Reverting to PIO because of "
795                                                 "bad alignment\n");
796                                         host->flags &= ~SDHCI_REQ_USE_DMA;
797                                         break;
798                                 }
799                         }
800                 }
801         }
802 
803         if (host->flags & SDHCI_REQ_USE_DMA) {
804                 if (host->flags & SDHCI_USE_ADMA) {
805                         ret = sdhci_adma_table_pre(host, data);
806                         if (ret) {
807                                 /*
808                                  * This only happens when someone fed
809                                  * us an invalid request.
810                                  */
811                                 WARN_ON(1);
812                                 host->flags &= ~SDHCI_REQ_USE_DMA;
813                         } else {
814                                 sdhci_writel(host, host->adma_addr,
815                                         SDHCI_ADMA_ADDRESS);
816                         }
817                 } else {
818                         int sg_cnt;
819 
820                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
821                                         data->sg, data->sg_len,
822                                         (data->flags & MMC_DATA_READ) ?
823                                                 DMA_FROM_DEVICE :
824                                                 DMA_TO_DEVICE);
825                         if (sg_cnt == 0) {
826                                 /*
827                                  * This only happens when someone fed
828                                  * us an invalid request.
829                                  */
830                                 WARN_ON(1);
831                                 host->flags &= ~SDHCI_REQ_USE_DMA;
832                         } else {
833                                 WARN_ON(sg_cnt != 1);
834                                 sdhci_writel(host, sg_dma_address(data->sg),
835                                         SDHCI_DMA_ADDRESS);
836                         }
837                 }
838         }
839 
840         /*
841          * Always adjust the DMA selection as some controllers
842          * (e.g. JMicron) can't do PIO properly when the selection
843          * is ADMA.
844          */
845         if (host->version >= SDHCI_SPEC_200) {
846                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
847                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
848                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
849                         (host->flags & SDHCI_USE_ADMA))
850                         ctrl |= SDHCI_CTRL_ADMA32;
851                 else
852                         ctrl |= SDHCI_CTRL_SDMA;
853                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
854         }
855 
856         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
857                 int flags;
858 
859                 flags = SG_MITER_ATOMIC;
860                 if (host->data->flags & MMC_DATA_READ)
861                         flags |= SG_MITER_TO_SG;
862                 else
863                         flags |= SG_MITER_FROM_SG;
864                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
865                 host->blocks = data->blocks;
866         }
867 
868         sdhci_set_transfer_irqs(host);
869 
870         /* Set the DMA boundary value and block size */
871         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
872                 data->blksz), SDHCI_BLOCK_SIZE);
873         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
874 }
875 
876 static void sdhci_set_transfer_mode(struct sdhci_host *host,
877         struct mmc_command *cmd)
878 {
879         u16 mode;
880         struct mmc_data *data = cmd->data;
881 
882         if (data == NULL) {
883                 /* clear Auto CMD settings for no data CMDs */
884                 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
885                 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
886                                 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
887                 return;
888         }
889 
890         WARN_ON(!host->data);
891 
892         mode = SDHCI_TRNS_BLK_CNT_EN;
893         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
894                 mode |= SDHCI_TRNS_MULTI;
895                 /*
896                  * If we are sending CMD23, CMD12 never gets sent
897                  * on successful completion (so no Auto-CMD12).
898                  */
899                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
900                         mode |= SDHCI_TRNS_AUTO_CMD12;
901                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
902                         mode |= SDHCI_TRNS_AUTO_CMD23;
903                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
904                 }
905         }
906 
907         if (data->flags & MMC_DATA_READ)
908                 mode |= SDHCI_TRNS_READ;
909         if (host->flags & SDHCI_REQ_USE_DMA)
910                 mode |= SDHCI_TRNS_DMA;
911 
912         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
913 }
914 
915 static void sdhci_finish_data(struct sdhci_host *host)
916 {
917         struct mmc_data *data;
918 
919         BUG_ON(!host->data);
920 
921         data = host->data;
922         host->data = NULL;
923 
924         if (host->flags & SDHCI_REQ_USE_DMA) {
925                 if (host->flags & SDHCI_USE_ADMA)
926                         sdhci_adma_table_post(host, data);
927                 else {
928                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
929                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
930                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
931                 }
932         }
933 
934         /*
935          * The specification states that the block count register must
936          * be updated, but it does not specify at what point in the
937          * data flow. That makes the register entirely useless to read
938          * back so we have to assume that nothing made it to the card
939          * in the event of an error.
940          */
941         if (data->error)
942                 data->bytes_xfered = 0;
943         else
944                 data->bytes_xfered = data->blksz * data->blocks;
945 
946         /*
947          * Need to send CMD12 if -
948          * a) open-ended multiblock transfer (no CMD23)
949          * b) error in multiblock transfer
950          */
951         if (data->stop &&
952             (data->error ||
953              !host->mrq->sbc)) {
954 
955                 /*
956                  * The controller needs a reset of internal state machines
957                  * upon error conditions.
958                  */
959                 if (data->error) {
960                         sdhci_do_reset(host, SDHCI_RESET_CMD);
961                         sdhci_do_reset(host, SDHCI_RESET_DATA);
962                 }
963 
964                 sdhci_send_command(host, data->stop);
965         } else
966                 tasklet_schedule(&host->finish_tasklet);
967 }
968 
969 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
970 {
971         int flags;
972         u32 mask;
973         unsigned long timeout;
974 
975         WARN_ON(host->cmd);
976 
977         /* Wait max 10 ms */
978         timeout = 10;
979 
980         mask = SDHCI_CMD_INHIBIT;
981         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
982                 mask |= SDHCI_DATA_INHIBIT;
983 
984         /* We shouldn't wait for data inihibit for stop commands, even
985            though they might use busy signaling */
986         if (host->mrq->data && (cmd == host->mrq->data->stop))
987                 mask &= ~SDHCI_DATA_INHIBIT;
988 
989         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
990                 if (timeout == 0) {
991                         pr_err("%s: Controller never released "
992                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
993                         sdhci_dumpregs(host);
994                         cmd->error = -EIO;
995                         tasklet_schedule(&host->finish_tasklet);
996                         return;
997                 }
998                 timeout--;
999                 mdelay(1);
1000         }
1001 
1002         timeout = jiffies;
1003         if (!cmd->data && cmd->busy_timeout > 9000)
1004                 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1005         else
1006                 timeout += 10 * HZ;
1007         mod_timer(&host->timer, timeout);
1008 
1009         host->cmd = cmd;
1010 
1011         sdhci_prepare_data(host, cmd);
1012 
1013         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1014 
1015         sdhci_set_transfer_mode(host, cmd);
1016 
1017         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1018                 pr_err("%s: Unsupported response type!\n",
1019                         mmc_hostname(host->mmc));
1020                 cmd->error = -EINVAL;
1021                 tasklet_schedule(&host->finish_tasklet);
1022                 return;
1023         }
1024 
1025         if (!(cmd->flags & MMC_RSP_PRESENT))
1026                 flags = SDHCI_CMD_RESP_NONE;
1027         else if (cmd->flags & MMC_RSP_136)
1028                 flags = SDHCI_CMD_RESP_LONG;
1029         else if (cmd->flags & MMC_RSP_BUSY)
1030                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1031         else
1032                 flags = SDHCI_CMD_RESP_SHORT;
1033 
1034         if (cmd->flags & MMC_RSP_CRC)
1035                 flags |= SDHCI_CMD_CRC;
1036         if (cmd->flags & MMC_RSP_OPCODE)
1037                 flags |= SDHCI_CMD_INDEX;
1038 
1039         /* CMD19 is special in that the Data Present Select should be set */
1040         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1041             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1042                 flags |= SDHCI_CMD_DATA;
1043 
1044         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1045 }
1046 EXPORT_SYMBOL_GPL(sdhci_send_command);
1047 
1048 static void sdhci_finish_command(struct sdhci_host *host)
1049 {
1050         int i;
1051 
1052         BUG_ON(host->cmd == NULL);
1053 
1054         if (host->cmd->flags & MMC_RSP_PRESENT) {
1055                 if (host->cmd->flags & MMC_RSP_136) {
1056                         /* CRC is stripped so we need to do some shifting. */
1057                         for (i = 0;i < 4;i++) {
1058                                 host->cmd->resp[i] = sdhci_readl(host,
1059                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1060                                 if (i != 3)
1061                                         host->cmd->resp[i] |=
1062                                                 sdhci_readb(host,
1063                                                 SDHCI_RESPONSE + (3-i)*4-1);
1064                         }
1065                 } else {
1066                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1067                 }
1068         }
1069 
1070         host->cmd->error = 0;
1071 
1072         /* Finished CMD23, now send actual command. */
1073         if (host->cmd == host->mrq->sbc) {
1074                 host->cmd = NULL;
1075                 sdhci_send_command(host, host->mrq->cmd);
1076         } else {
1077 
1078                 /* Processed actual command. */
1079                 if (host->data && host->data_early)
1080                         sdhci_finish_data(host);
1081 
1082                 if (!host->cmd->data)
1083                         tasklet_schedule(&host->finish_tasklet);
1084 
1085                 host->cmd = NULL;
1086         }
1087 }
1088 
1089 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1090 {
1091         u16 preset = 0;
1092 
1093         switch (host->timing) {
1094         case MMC_TIMING_UHS_SDR12:
1095                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1096                 break;
1097         case MMC_TIMING_UHS_SDR25:
1098                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1099                 break;
1100         case MMC_TIMING_UHS_SDR50:
1101                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1102                 break;
1103         case MMC_TIMING_UHS_SDR104:
1104         case MMC_TIMING_MMC_HS200:
1105                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1106                 break;
1107         case MMC_TIMING_UHS_DDR50:
1108                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1109                 break;
1110         default:
1111                 pr_warn("%s: Invalid UHS-I mode selected\n",
1112                         mmc_hostname(host->mmc));
1113                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1114                 break;
1115         }
1116         return preset;
1117 }
1118 
1119 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1120 {
1121         int div = 0; /* Initialized for compiler warning */
1122         int real_div = div, clk_mul = 1;
1123         u16 clk = 0;
1124         unsigned long timeout;
1125 
1126         host->mmc->actual_clock = 0;
1127 
1128         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1129 
1130         if (clock == 0)
1131                 return;
1132 
1133         if (host->version >= SDHCI_SPEC_300) {
1134                 if (host->preset_enabled) {
1135                         u16 pre_val;
1136 
1137                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1138                         pre_val = sdhci_get_preset_value(host);
1139                         div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1140                                 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1141                         if (host->clk_mul &&
1142                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1143                                 clk = SDHCI_PROG_CLOCK_MODE;
1144                                 real_div = div + 1;
1145                                 clk_mul = host->clk_mul;
1146                         } else {
1147                                 real_div = max_t(int, 1, div << 1);
1148                         }
1149                         goto clock_set;
1150                 }
1151 
1152                 /*
1153                  * Check if the Host Controller supports Programmable Clock
1154                  * Mode.
1155                  */
1156                 if (host->clk_mul) {
1157                         for (div = 1; div <= 1024; div++) {
1158                                 if ((host->max_clk * host->clk_mul / div)
1159                                         <= clock)
1160                                         break;
1161                         }
1162                         /*
1163                          * Set Programmable Clock Mode in the Clock
1164                          * Control register.
1165                          */
1166                         clk = SDHCI_PROG_CLOCK_MODE;
1167                         real_div = div;
1168                         clk_mul = host->clk_mul;
1169                         div--;
1170                 } else {
1171                         /* Version 3.00 divisors must be a multiple of 2. */
1172                         if (host->max_clk <= clock)
1173                                 div = 1;
1174                         else {
1175                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1176                                      div += 2) {
1177                                         if ((host->max_clk / div) <= clock)
1178                                                 break;
1179                                 }
1180                         }
1181                         real_div = div;
1182                         div >>= 1;
1183                 }
1184         } else {
1185                 /* Version 2.00 divisors must be a power of 2. */
1186                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1187                         if ((host->max_clk / div) <= clock)
1188                                 break;
1189                 }
1190                 real_div = div;
1191                 div >>= 1;
1192         }
1193 
1194 clock_set:
1195         if (real_div)
1196                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1197 
1198         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1199         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1200                 << SDHCI_DIVIDER_HI_SHIFT;
1201         clk |= SDHCI_CLOCK_INT_EN;
1202         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1203 
1204         /* Wait max 20 ms */
1205         timeout = 20;
1206         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1207                 & SDHCI_CLOCK_INT_STABLE)) {
1208                 if (timeout == 0) {
1209                         pr_err("%s: Internal clock never "
1210                                 "stabilised.\n", mmc_hostname(host->mmc));
1211                         sdhci_dumpregs(host);
1212                         return;
1213                 }
1214                 timeout--;
1215                 mdelay(1);
1216         }
1217 
1218         clk |= SDHCI_CLOCK_CARD_EN;
1219         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1220 }
1221 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1222 
1223 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1224                             unsigned short vdd)
1225 {
1226         struct mmc_host *mmc = host->mmc;
1227         u8 pwr = 0;
1228 
1229         if (!IS_ERR(mmc->supply.vmmc)) {
1230                 spin_unlock_irq(&host->lock);
1231                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1232                 spin_lock_irq(&host->lock);
1233                 return;
1234         }
1235 
1236         if (mode != MMC_POWER_OFF) {
1237                 switch (1 << vdd) {
1238                 case MMC_VDD_165_195:
1239                         pwr = SDHCI_POWER_180;
1240                         break;
1241                 case MMC_VDD_29_30:
1242                 case MMC_VDD_30_31:
1243                         pwr = SDHCI_POWER_300;
1244                         break;
1245                 case MMC_VDD_32_33:
1246                 case MMC_VDD_33_34:
1247                         pwr = SDHCI_POWER_330;
1248                         break;
1249                 default:
1250                         BUG();
1251                 }
1252         }
1253 
1254         if (host->pwr == pwr)
1255                 return;
1256 
1257         host->pwr = pwr;
1258 
1259         if (pwr == 0) {
1260                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1261                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1262                         sdhci_runtime_pm_bus_off(host);
1263                 vdd = 0;
1264         } else {
1265                 /*
1266                  * Spec says that we should clear the power reg before setting
1267                  * a new value. Some controllers don't seem to like this though.
1268                  */
1269                 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1270                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1271 
1272                 /*
1273                  * At least the Marvell CaFe chip gets confused if we set the
1274                  * voltage and set turn on power at the same time, so set the
1275                  * voltage first.
1276                  */
1277                 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1278                         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1279 
1280                 pwr |= SDHCI_POWER_ON;
1281 
1282                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1283 
1284                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1285                         sdhci_runtime_pm_bus_on(host);
1286 
1287                 /*
1288                  * Some controllers need an extra 10ms delay of 10ms before
1289                  * they can apply clock after applying power
1290                  */
1291                 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1292                         mdelay(10);
1293         }
1294 }
1295 
1296 /*****************************************************************************\
1297  *                                                                           *
1298  * MMC callbacks                                                             *
1299  *                                                                           *
1300 \*****************************************************************************/
1301 
1302 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1303 {
1304         struct sdhci_host *host;
1305         int present;
1306         unsigned long flags;
1307         u32 tuning_opcode;
1308 
1309         host = mmc_priv(mmc);
1310 
1311         sdhci_runtime_pm_get(host);
1312 
1313         spin_lock_irqsave(&host->lock, flags);
1314 
1315         WARN_ON(host->mrq != NULL);
1316 
1317 #ifndef SDHCI_USE_LEDS_CLASS
1318         sdhci_activate_led(host);
1319 #endif
1320 
1321         /*
1322          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1323          * requests if Auto-CMD12 is enabled.
1324          */
1325         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1326                 if (mrq->stop) {
1327                         mrq->data->stop = NULL;
1328                         mrq->stop = NULL;
1329                 }
1330         }
1331 
1332         host->mrq = mrq;
1333 
1334         /*
1335          * Firstly check card presence from cd-gpio.  The return could
1336          * be one of the following possibilities:
1337          *     negative: cd-gpio is not available
1338          *     zero: cd-gpio is used, and card is removed
1339          *     one: cd-gpio is used, and card is present
1340          */
1341         present = mmc_gpio_get_cd(host->mmc);
1342         if (present < 0) {
1343                 /* If polling, assume that the card is always present. */
1344                 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1345                         present = 1;
1346                 else
1347                         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1348                                         SDHCI_CARD_PRESENT;
1349         }
1350 
1351         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1352                 host->mrq->cmd->error = -ENOMEDIUM;
1353                 tasklet_schedule(&host->finish_tasklet);
1354         } else {
1355                 u32 present_state;
1356 
1357                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1358                 /*
1359                  * Check if the re-tuning timer has already expired and there
1360                  * is no on-going data transfer. If so, we need to execute
1361                  * tuning procedure before sending command.
1362                  */
1363                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1364                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1365                         if (mmc->card) {
1366                                 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1367                                 tuning_opcode =
1368                                         mmc->card->type == MMC_TYPE_MMC ?
1369                                         MMC_SEND_TUNING_BLOCK_HS200 :
1370                                         MMC_SEND_TUNING_BLOCK;
1371 
1372                                 /* Here we need to set the host->mrq to NULL,
1373                                  * in case the pending finish_tasklet
1374                                  * finishes it incorrectly.
1375                                  */
1376                                 host->mrq = NULL;
1377 
1378                                 spin_unlock_irqrestore(&host->lock, flags);
1379                                 sdhci_execute_tuning(mmc, tuning_opcode);
1380                                 spin_lock_irqsave(&host->lock, flags);
1381 
1382                                 /* Restore original mmc_request structure */
1383                                 host->mrq = mrq;
1384                         }
1385                 }
1386 
1387                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1388                         sdhci_send_command(host, mrq->sbc);
1389                 else
1390                         sdhci_send_command(host, mrq->cmd);
1391         }
1392 
1393         mmiowb();
1394         spin_unlock_irqrestore(&host->lock, flags);
1395 }
1396 
1397 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1398 {
1399         u8 ctrl;
1400 
1401         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1402         if (width == MMC_BUS_WIDTH_8) {
1403                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1404                 if (host->version >= SDHCI_SPEC_300)
1405                         ctrl |= SDHCI_CTRL_8BITBUS;
1406         } else {
1407                 if (host->version >= SDHCI_SPEC_300)
1408                         ctrl &= ~SDHCI_CTRL_8BITBUS;
1409                 if (width == MMC_BUS_WIDTH_4)
1410                         ctrl |= SDHCI_CTRL_4BITBUS;
1411                 else
1412                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1413         }
1414         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1415 }
1416 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1417 
1418 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1419 {
1420         u16 ctrl_2;
1421 
1422         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1423         /* Select Bus Speed Mode for host */
1424         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1425         if ((timing == MMC_TIMING_MMC_HS200) ||
1426             (timing == MMC_TIMING_UHS_SDR104))
1427                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1428         else if (timing == MMC_TIMING_UHS_SDR12)
1429                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1430         else if (timing == MMC_TIMING_UHS_SDR25)
1431                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1432         else if (timing == MMC_TIMING_UHS_SDR50)
1433                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1434         else if ((timing == MMC_TIMING_UHS_DDR50) ||
1435                  (timing == MMC_TIMING_MMC_DDR52))
1436                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1437         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1438 }
1439 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1440 
1441 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1442 {
1443         unsigned long flags;
1444         u8 ctrl;
1445         struct mmc_host *mmc = host->mmc;
1446 
1447         spin_lock_irqsave(&host->lock, flags);
1448 
1449         if (host->flags & SDHCI_DEVICE_DEAD) {
1450                 spin_unlock_irqrestore(&host->lock, flags);
1451                 if (!IS_ERR(mmc->supply.vmmc) &&
1452                     ios->power_mode == MMC_POWER_OFF)
1453                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1454                 return;
1455         }
1456 
1457         /*
1458          * Reset the chip on each power off.
1459          * Should clear out any weird states.
1460          */
1461         if (ios->power_mode == MMC_POWER_OFF) {
1462                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1463                 sdhci_reinit(host);
1464         }
1465 
1466         if (host->version >= SDHCI_SPEC_300 &&
1467                 (ios->power_mode == MMC_POWER_UP) &&
1468                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1469                 sdhci_enable_preset_value(host, false);
1470 
1471         if (!ios->clock || ios->clock != host->clock) {
1472                 host->ops->set_clock(host, ios->clock);
1473                 host->clock = ios->clock;
1474         }
1475 
1476         sdhci_set_power(host, ios->power_mode, ios->vdd);
1477 
1478         if (host->ops->platform_send_init_74_clocks)
1479                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1480 
1481         host->ops->set_bus_width(host, ios->bus_width);
1482 
1483         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1484 
1485         if ((ios->timing == MMC_TIMING_SD_HS ||
1486              ios->timing == MMC_TIMING_MMC_HS)
1487             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1488                 ctrl |= SDHCI_CTRL_HISPD;
1489         else
1490                 ctrl &= ~SDHCI_CTRL_HISPD;
1491 
1492         if (host->version >= SDHCI_SPEC_300) {
1493                 u16 clk, ctrl_2;
1494 
1495                 /* In case of UHS-I modes, set High Speed Enable */
1496                 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1497                     (ios->timing == MMC_TIMING_MMC_DDR52) ||
1498                     (ios->timing == MMC_TIMING_UHS_SDR50) ||
1499                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1500                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1501                     (ios->timing == MMC_TIMING_UHS_SDR25))
1502                         ctrl |= SDHCI_CTRL_HISPD;
1503 
1504                 if (!host->preset_enabled) {
1505                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1506                         /*
1507                          * We only need to set Driver Strength if the
1508                          * preset value enable is not set.
1509                          */
1510                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1511                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1512                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1513                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1514                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1515                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1516 
1517                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1518                 } else {
1519                         /*
1520                          * According to SDHC Spec v3.00, if the Preset Value
1521                          * Enable in the Host Control 2 register is set, we
1522                          * need to reset SD Clock Enable before changing High
1523                          * Speed Enable to avoid generating clock gliches.
1524                          */
1525 
1526                         /* Reset SD Clock Enable */
1527                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1528                         clk &= ~SDHCI_CLOCK_CARD_EN;
1529                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1530 
1531                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1532 
1533                         /* Re-enable SD Clock */
1534                         host->ops->set_clock(host, host->clock);
1535                 }
1536 
1537                 /* Reset SD Clock Enable */
1538                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1539                 clk &= ~SDHCI_CLOCK_CARD_EN;
1540                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1541 
1542                 host->ops->set_uhs_signaling(host, ios->timing);
1543                 host->timing = ios->timing;
1544 
1545                 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1546                                 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1547                                  (ios->timing == MMC_TIMING_UHS_SDR25) ||
1548                                  (ios->timing == MMC_TIMING_UHS_SDR50) ||
1549                                  (ios->timing == MMC_TIMING_UHS_SDR104) ||
1550                                  (ios->timing == MMC_TIMING_UHS_DDR50))) {
1551                         u16 preset;
1552 
1553                         sdhci_enable_preset_value(host, true);
1554                         preset = sdhci_get_preset_value(host);
1555                         ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1556                                 >> SDHCI_PRESET_DRV_SHIFT;
1557                 }
1558 
1559                 /* Re-enable SD Clock */
1560                 host->ops->set_clock(host, host->clock);
1561         } else
1562                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1563 
1564         /*
1565          * Some (ENE) controllers go apeshit on some ios operation,
1566          * signalling timeout and CRC errors even on CMD0. Resetting
1567          * it on each ios seems to solve the problem.
1568          */
1569         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1570                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1571 
1572         mmiowb();
1573         spin_unlock_irqrestore(&host->lock, flags);
1574 }
1575 
1576 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1577 {
1578         struct sdhci_host *host = mmc_priv(mmc);
1579 
1580         sdhci_runtime_pm_get(host);
1581         sdhci_do_set_ios(host, ios);
1582         sdhci_runtime_pm_put(host);
1583 }
1584 
1585 static int sdhci_do_get_cd(struct sdhci_host *host)
1586 {
1587         int gpio_cd = mmc_gpio_get_cd(host->mmc);
1588 
1589         if (host->flags & SDHCI_DEVICE_DEAD)
1590                 return 0;
1591 
1592         /* If polling/nonremovable, assume that the card is always present. */
1593         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1594             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1595                 return 1;
1596 
1597         /* Try slot gpio detect */
1598         if (!IS_ERR_VALUE(gpio_cd))
1599                 return !!gpio_cd;
1600 
1601         /* Host native card detect */
1602         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1603 }
1604 
1605 static int sdhci_get_cd(struct mmc_host *mmc)
1606 {
1607         struct sdhci_host *host = mmc_priv(mmc);
1608         int ret;
1609 
1610         sdhci_runtime_pm_get(host);
1611         ret = sdhci_do_get_cd(host);
1612         sdhci_runtime_pm_put(host);
1613         return ret;
1614 }
1615 
1616 static int sdhci_check_ro(struct sdhci_host *host)
1617 {
1618         unsigned long flags;
1619         int is_readonly;
1620 
1621         spin_lock_irqsave(&host->lock, flags);
1622 
1623         if (host->flags & SDHCI_DEVICE_DEAD)
1624                 is_readonly = 0;
1625         else if (host->ops->get_ro)
1626                 is_readonly = host->ops->get_ro(host);
1627         else
1628                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1629                                 & SDHCI_WRITE_PROTECT);
1630 
1631         spin_unlock_irqrestore(&host->lock, flags);
1632 
1633         /* This quirk needs to be replaced by a callback-function later */
1634         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1635                 !is_readonly : is_readonly;
1636 }
1637 
1638 #define SAMPLE_COUNT    5
1639 
1640 static int sdhci_do_get_ro(struct sdhci_host *host)
1641 {
1642         int i, ro_count;
1643 
1644         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1645                 return sdhci_check_ro(host);
1646 
1647         ro_count = 0;
1648         for (i = 0; i < SAMPLE_COUNT; i++) {
1649                 if (sdhci_check_ro(host)) {
1650                         if (++ro_count > SAMPLE_COUNT / 2)
1651                                 return 1;
1652                 }
1653                 msleep(30);
1654         }
1655         return 0;
1656 }
1657 
1658 static void sdhci_hw_reset(struct mmc_host *mmc)
1659 {
1660         struct sdhci_host *host = mmc_priv(mmc);
1661 
1662         if (host->ops && host->ops->hw_reset)
1663                 host->ops->hw_reset(host);
1664 }
1665 
1666 static int sdhci_get_ro(struct mmc_host *mmc)
1667 {
1668         struct sdhci_host *host = mmc_priv(mmc);
1669         int ret;
1670 
1671         sdhci_runtime_pm_get(host);
1672         ret = sdhci_do_get_ro(host);
1673         sdhci_runtime_pm_put(host);
1674         return ret;
1675 }
1676 
1677 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1678 {
1679         if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1680                 if (enable)
1681                         host->ier |= SDHCI_INT_CARD_INT;
1682                 else
1683                         host->ier &= ~SDHCI_INT_CARD_INT;
1684 
1685                 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1686                 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1687                 mmiowb();
1688         }
1689 }
1690 
1691 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1692 {
1693         struct sdhci_host *host = mmc_priv(mmc);
1694         unsigned long flags;
1695 
1696         sdhci_runtime_pm_get(host);
1697 
1698         spin_lock_irqsave(&host->lock, flags);
1699         if (enable)
1700                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1701         else
1702                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1703 
1704         sdhci_enable_sdio_irq_nolock(host, enable);
1705         spin_unlock_irqrestore(&host->lock, flags);
1706 
1707         sdhci_runtime_pm_put(host);
1708 }
1709 
1710 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1711                                                 struct mmc_ios *ios)
1712 {
1713         struct mmc_host *mmc = host->mmc;
1714         u16 ctrl;
1715         int ret;
1716 
1717         /*
1718          * Signal Voltage Switching is only applicable for Host Controllers
1719          * v3.00 and above.
1720          */
1721         if (host->version < SDHCI_SPEC_300)
1722                 return 0;
1723 
1724         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1725 
1726         switch (ios->signal_voltage) {
1727         case MMC_SIGNAL_VOLTAGE_330:
1728                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1729                 ctrl &= ~SDHCI_CTRL_VDD_180;
1730                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1731 
1732                 if (!IS_ERR(mmc->supply.vqmmc)) {
1733                         ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1734                                                     3600000);
1735                         if (ret) {
1736                                 pr_warning("%s: Switching to 3.3V signalling voltage "
1737                                                 " failed\n", mmc_hostname(mmc));
1738                                 return -EIO;
1739                         }
1740                 }
1741                 /* Wait for 5ms */
1742                 usleep_range(5000, 5500);
1743 
1744                 /* 3.3V regulator output should be stable within 5 ms */
1745                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1746                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1747                         return 0;
1748 
1749                 pr_warning("%s: 3.3V regulator output did not became stable\n",
1750                                 mmc_hostname(mmc));
1751 
1752                 return -EAGAIN;
1753         case MMC_SIGNAL_VOLTAGE_180:
1754                 if (!IS_ERR(mmc->supply.vqmmc)) {
1755                         ret = regulator_set_voltage(mmc->supply.vqmmc,
1756                                         1700000, 1950000);
1757                         if (ret) {
1758                                 pr_warning("%s: Switching to 1.8V signalling voltage "
1759                                                 " failed\n", mmc_hostname(mmc));
1760                                 return -EIO;
1761                         }
1762                 }
1763 
1764                 /*
1765                  * Enable 1.8V Signal Enable in the Host Control2
1766                  * register
1767                  */
1768                 ctrl |= SDHCI_CTRL_VDD_180;
1769                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1770 
1771                 /* 1.8V regulator output should be stable within 5 ms */
1772                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1773                 if (ctrl & SDHCI_CTRL_VDD_180)
1774                         return 0;
1775 
1776                 pr_warning("%s: 1.8V regulator output did not became stable\n",
1777                                 mmc_hostname(mmc));
1778 
1779                 return -EAGAIN;
1780         case MMC_SIGNAL_VOLTAGE_120:
1781                 if (!IS_ERR(mmc->supply.vqmmc)) {
1782                         ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1783                                                     1300000);
1784                         if (ret) {
1785                                 pr_warning("%s: Switching to 1.2V signalling voltage "
1786                                                 " failed\n", mmc_hostname(mmc));
1787                                 return -EIO;
1788                         }
1789                 }
1790                 return 0;
1791         default:
1792                 /* No signal voltage switch required */
1793                 return 0;
1794         }
1795 }
1796 
1797 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1798         struct mmc_ios *ios)
1799 {
1800         struct sdhci_host *host = mmc_priv(mmc);
1801         int err;
1802 
1803         if (host->version < SDHCI_SPEC_300)
1804                 return 0;
1805         sdhci_runtime_pm_get(host);
1806         err = sdhci_do_start_signal_voltage_switch(host, ios);
1807         sdhci_runtime_pm_put(host);
1808         return err;
1809 }
1810 
1811 static int sdhci_card_busy(struct mmc_host *mmc)
1812 {
1813         struct sdhci_host *host = mmc_priv(mmc);
1814         u32 present_state;
1815 
1816         sdhci_runtime_pm_get(host);
1817         /* Check whether DAT[3:0] is 0000 */
1818         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1819         sdhci_runtime_pm_put(host);
1820 
1821         return !(present_state & SDHCI_DATA_LVL_MASK);
1822 }
1823 
1824 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1825 {
1826         struct sdhci_host *host = mmc_priv(mmc);
1827         u16 ctrl;
1828         int tuning_loop_counter = MAX_TUNING_LOOP;
1829         int err = 0;
1830         unsigned long flags;
1831 
1832         sdhci_runtime_pm_get(host);
1833         spin_lock_irqsave(&host->lock, flags);
1834 
1835         /*
1836          * The Host Controller needs tuning only in case of SDR104 mode
1837          * and for SDR50 mode when Use Tuning for SDR50 is set in the
1838          * Capabilities register.
1839          * If the Host Controller supports the HS200 mode then the
1840          * tuning function has to be executed.
1841          */
1842         switch (host->timing) {
1843         case MMC_TIMING_MMC_HS200:
1844         case MMC_TIMING_UHS_SDR104:
1845                 break;
1846 
1847         case MMC_TIMING_UHS_SDR50:
1848                 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1849                     host->flags & SDHCI_SDR104_NEEDS_TUNING)
1850                         break;
1851                 /* FALLTHROUGH */
1852 
1853         default:
1854                 spin_unlock_irqrestore(&host->lock, flags);
1855                 sdhci_runtime_pm_put(host);
1856                 return 0;
1857         }
1858 
1859         if (host->ops->platform_execute_tuning) {
1860                 spin_unlock_irqrestore(&host->lock, flags);
1861                 err = host->ops->platform_execute_tuning(host, opcode);
1862                 sdhci_runtime_pm_put(host);
1863                 return err;
1864         }
1865 
1866         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1867         ctrl |= SDHCI_CTRL_EXEC_TUNING;
1868         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1869 
1870         /*
1871          * As per the Host Controller spec v3.00, tuning command
1872          * generates Buffer Read Ready interrupt, so enable that.
1873          *
1874          * Note: The spec clearly says that when tuning sequence
1875          * is being performed, the controller does not generate
1876          * interrupts other than Buffer Read Ready interrupt. But
1877          * to make sure we don't hit a controller bug, we _only_
1878          * enable Buffer Read Ready interrupt here.
1879          */
1880         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1881         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1882 
1883         /*
1884          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1885          * of loops reaches 40 times or a timeout of 150ms occurs.
1886          */
1887         do {
1888                 struct mmc_command cmd = {0};
1889                 struct mmc_request mrq = {NULL};
1890 
1891                 cmd.opcode = opcode;
1892                 cmd.arg = 0;
1893                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1894                 cmd.retries = 0;
1895                 cmd.data = NULL;
1896                 cmd.error = 0;
1897 
1898                 if (tuning_loop_counter-- == 0)
1899                         break;
1900 
1901                 mrq.cmd = &cmd;
1902                 host->mrq = &mrq;
1903 
1904                 /*
1905                  * In response to CMD19, the card sends 64 bytes of tuning
1906                  * block to the Host Controller. So we set the block size
1907                  * to 64 here.
1908                  */
1909                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1910                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1911                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1912                                              SDHCI_BLOCK_SIZE);
1913                         else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1914                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1915                                              SDHCI_BLOCK_SIZE);
1916                 } else {
1917                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1918                                      SDHCI_BLOCK_SIZE);
1919                 }
1920 
1921                 /*
1922                  * The tuning block is sent by the card to the host controller.
1923                  * So we set the TRNS_READ bit in the Transfer Mode register.
1924                  * This also takes care of setting DMA Enable and Multi Block
1925                  * Select in the same register to 0.
1926                  */
1927                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1928 
1929                 sdhci_send_command(host, &cmd);
1930 
1931                 host->cmd = NULL;
1932                 host->mrq = NULL;
1933 
1934                 spin_unlock_irqrestore(&host->lock, flags);
1935                 /* Wait for Buffer Read Ready interrupt */
1936                 wait_event_interruptible_timeout(host->buf_ready_int,
1937                                         (host->tuning_done == 1),
1938                                         msecs_to_jiffies(50));
1939                 spin_lock_irqsave(&host->lock, flags);
1940 
1941                 if (!host->tuning_done) {
1942                         pr_info(DRIVER_NAME ": Timeout waiting for "
1943                                 "Buffer Read Ready interrupt during tuning "
1944                                 "procedure, falling back to fixed sampling "
1945                                 "clock\n");
1946                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1947                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1948                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1949                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1950 
1951                         err = -EIO;
1952                         goto out;
1953                 }
1954 
1955                 host->tuning_done = 0;
1956 
1957                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1958 
1959                 /* eMMC spec does not require a delay between tuning cycles */
1960                 if (opcode == MMC_SEND_TUNING_BLOCK)
1961                         mdelay(1);
1962         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1963 
1964         /*
1965          * The Host Driver has exhausted the maximum number of loops allowed,
1966          * so use fixed sampling frequency.
1967          */
1968         if (tuning_loop_counter < 0) {
1969                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1970                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1971         }
1972         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1973                 pr_info(DRIVER_NAME ": Tuning procedure"
1974                         " failed, falling back to fixed sampling"
1975                         " clock\n");
1976                 err = -EIO;
1977         }
1978 
1979 out:
1980         /*
1981          * If this is the very first time we are here, we start the retuning
1982          * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1983          * flag won't be set, we check this condition before actually starting
1984          * the timer.
1985          */
1986         if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1987             (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1988                 host->flags |= SDHCI_USING_RETUNING_TIMER;
1989                 mod_timer(&host->tuning_timer, jiffies +
1990                         host->tuning_count * HZ);
1991                 /* Tuning mode 1 limits the maximum data length to 4MB */
1992                 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1993         } else if (host->flags & SDHCI_USING_RETUNING_TIMER) {
1994                 host->flags &= ~SDHCI_NEEDS_RETUNING;
1995                 /* Reload the new initial value for timer */
1996                 mod_timer(&host->tuning_timer, jiffies +
1997                           host->tuning_count * HZ);
1998         }
1999 
2000         /*
2001          * In case tuning fails, host controllers which support re-tuning can
2002          * try tuning again at a later time, when the re-tuning timer expires.
2003          * So for these controllers, we return 0. Since there might be other
2004          * controllers who do not have this capability, we return error for
2005          * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2006          * a retuning timer to do the retuning for the card.
2007          */
2008         if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2009                 err = 0;
2010 
2011         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2012         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2013         spin_unlock_irqrestore(&host->lock, flags);
2014         sdhci_runtime_pm_put(host);
2015 
2016         return err;
2017 }
2018 
2019 
2020 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2021 {
2022         /* Host Controller v3.00 defines preset value registers */
2023         if (host->version < SDHCI_SPEC_300)
2024                 return;
2025 
2026         /*
2027          * We only enable or disable Preset Value if they are not already
2028          * enabled or disabled respectively. Otherwise, we bail out.
2029          */
2030         if (host->preset_enabled != enable) {
2031                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2032 
2033                 if (enable)
2034                         ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2035                 else
2036                         ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2037 
2038                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2039 
2040                 if (enable)
2041                         host->flags |= SDHCI_PV_ENABLED;
2042                 else
2043                         host->flags &= ~SDHCI_PV_ENABLED;
2044 
2045                 host->preset_enabled = enable;
2046         }
2047 }
2048 
2049 static void sdhci_card_event(struct mmc_host *mmc)
2050 {
2051         struct sdhci_host *host = mmc_priv(mmc);
2052         unsigned long flags;
2053 
2054         /* First check if client has provided their own card event */
2055         if (host->ops->card_event)
2056                 host->ops->card_event(host);
2057 
2058         spin_lock_irqsave(&host->lock, flags);
2059 
2060         /* Check host->mrq first in case we are runtime suspended */
2061         if (host->mrq && !sdhci_do_get_cd(host)) {
2062                 pr_err("%s: Card removed during transfer!\n",
2063                         mmc_hostname(host->mmc));
2064                 pr_err("%s: Resetting controller.\n",
2065                         mmc_hostname(host->mmc));
2066 
2067                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2068                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2069 
2070                 host->mrq->cmd->error = -ENOMEDIUM;
2071                 tasklet_schedule(&host->finish_tasklet);
2072         }
2073 
2074         spin_unlock_irqrestore(&host->lock, flags);
2075 }
2076 
2077 static const struct mmc_host_ops sdhci_ops = {
2078         .request        = sdhci_request,
2079         .set_ios        = sdhci_set_ios,
2080         .get_cd         = sdhci_get_cd,
2081         .get_ro         = sdhci_get_ro,
2082         .hw_reset       = sdhci_hw_reset,
2083         .enable_sdio_irq = sdhci_enable_sdio_irq,
2084         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2085         .execute_tuning                 = sdhci_execute_tuning,
2086         .card_event                     = sdhci_card_event,
2087         .card_busy      = sdhci_card_busy,
2088 };
2089 
2090 /*****************************************************************************\
2091  *                                                                           *
2092  * Tasklets                                                                  *
2093  *                                                                           *
2094 \*****************************************************************************/
2095 
2096 static void sdhci_tasklet_finish(unsigned long param)
2097 {
2098         struct sdhci_host *host;
2099         unsigned long flags;
2100         struct mmc_request *mrq;
2101 
2102         host = (struct sdhci_host*)param;
2103 
2104         spin_lock_irqsave(&host->lock, flags);
2105 
2106         /*
2107          * If this tasklet gets rescheduled while running, it will
2108          * be run again afterwards but without any active request.
2109          */
2110         if (!host->mrq) {
2111                 spin_unlock_irqrestore(&host->lock, flags);
2112                 return;
2113         }
2114 
2115         del_timer(&host->timer);
2116 
2117         mrq = host->mrq;
2118 
2119         /*
2120          * The controller needs a reset of internal state machines
2121          * upon error conditions.
2122          */
2123         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2124             ((mrq->cmd && mrq->cmd->error) ||
2125                  (mrq->data && (mrq->data->error ||
2126                   (mrq->data->stop && mrq->data->stop->error))) ||
2127                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2128 
2129                 /* Some controllers need this kick or reset won't work here */
2130                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2131                         /* This is to force an update */
2132                         host->ops->set_clock(host, host->clock);
2133 
2134                 /* Spec says we should do both at the same time, but Ricoh
2135                    controllers do not like that. */
2136                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2137                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2138         }
2139 
2140         host->mrq = NULL;
2141         host->cmd = NULL;
2142         host->data = NULL;
2143 
2144 #ifndef SDHCI_USE_LEDS_CLASS
2145         sdhci_deactivate_led(host);
2146 #endif
2147 
2148         mmiowb();
2149         spin_unlock_irqrestore(&host->lock, flags);
2150 
2151         mmc_request_done(host->mmc, mrq);
2152         sdhci_runtime_pm_put(host);
2153 }
2154 
2155 static void sdhci_timeout_timer(unsigned long data)
2156 {
2157         struct sdhci_host *host;
2158         unsigned long flags;
2159 
2160         host = (struct sdhci_host*)data;
2161 
2162         spin_lock_irqsave(&host->lock, flags);
2163 
2164         if (host->mrq) {
2165                 pr_err("%s: Timeout waiting for hardware "
2166                         "interrupt.\n", mmc_hostname(host->mmc));
2167                 sdhci_dumpregs(host);
2168 
2169                 if (host->data) {
2170                         host->data->error = -ETIMEDOUT;
2171                         sdhci_finish_data(host);
2172                 } else {
2173                         if (host->cmd)
2174                                 host->cmd->error = -ETIMEDOUT;
2175                         else
2176                                 host->mrq->cmd->error = -ETIMEDOUT;
2177 
2178                         tasklet_schedule(&host->finish_tasklet);
2179                 }
2180         }
2181 
2182         mmiowb();
2183         spin_unlock_irqrestore(&host->lock, flags);
2184 }
2185 
2186 static void sdhci_tuning_timer(unsigned long data)
2187 {
2188         struct sdhci_host *host;
2189         unsigned long flags;
2190 
2191         host = (struct sdhci_host *)data;
2192 
2193         spin_lock_irqsave(&host->lock, flags);
2194 
2195         host->flags |= SDHCI_NEEDS_RETUNING;
2196 
2197         spin_unlock_irqrestore(&host->lock, flags);
2198 }
2199 
2200 /*****************************************************************************\
2201  *                                                                           *
2202  * Interrupt handling                                                        *
2203  *                                                                           *
2204 \*****************************************************************************/
2205 
2206 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2207 {
2208         BUG_ON(intmask == 0);
2209 
2210         if (!host->cmd) {
2211                 pr_err("%s: Got command interrupt 0x%08x even "
2212                         "though no command operation was in progress.\n",
2213                         mmc_hostname(host->mmc), (unsigned)intmask);
2214                 sdhci_dumpregs(host);
2215                 return;
2216         }
2217 
2218         if (intmask & SDHCI_INT_TIMEOUT)
2219                 host->cmd->error = -ETIMEDOUT;
2220         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2221                         SDHCI_INT_INDEX))
2222                 host->cmd->error = -EILSEQ;
2223 
2224         if (host->cmd->error) {
2225                 tasklet_schedule(&host->finish_tasklet);
2226                 return;
2227         }
2228 
2229         /*
2230          * The host can send and interrupt when the busy state has
2231          * ended, allowing us to wait without wasting CPU cycles.
2232          * Unfortunately this is overloaded on the "data complete"
2233          * interrupt, so we need to take some care when handling
2234          * it.
2235          *
2236          * Note: The 1.0 specification is a bit ambiguous about this
2237          *       feature so there might be some problems with older
2238          *       controllers.
2239          */
2240         if (host->cmd->flags & MMC_RSP_BUSY) {
2241                 if (host->cmd->data)
2242                         DBG("Cannot wait for busy signal when also "
2243                                 "doing a data transfer");
2244                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2245                         return;
2246 
2247                 /* The controller does not support the end-of-busy IRQ,
2248                  * fall through and take the SDHCI_INT_RESPONSE */
2249         }
2250 
2251         if (intmask & SDHCI_INT_RESPONSE)
2252                 sdhci_finish_command(host);
2253 }
2254 
2255 #ifdef CONFIG_MMC_DEBUG
2256 static void sdhci_show_adma_error(struct sdhci_host *host)
2257 {
2258         const char *name = mmc_hostname(host->mmc);
2259         u8 *desc = host->adma_desc;
2260         __le32 *dma;
2261         __le16 *len;
2262         u8 attr;
2263 
2264         sdhci_dumpregs(host);
2265 
2266         while (true) {
2267                 dma = (__le32 *)(desc + 4);
2268                 len = (__le16 *)(desc + 2);
2269                 attr = *desc;
2270 
2271                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2272                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2273 
2274                 desc += 8;
2275 
2276                 if (attr & 2)
2277                         break;
2278         }
2279 }
2280 #else
2281 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2282 #endif
2283 
2284 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2285 {
2286         u32 command;
2287         BUG_ON(intmask == 0);
2288 
2289         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2290         if (intmask & SDHCI_INT_DATA_AVAIL) {
2291                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2292                 if (command == MMC_SEND_TUNING_BLOCK ||
2293                     command == MMC_SEND_TUNING_BLOCK_HS200) {
2294                         host->tuning_done = 1;
2295                         wake_up(&host->buf_ready_int);
2296                         return;
2297                 }
2298         }
2299 
2300         if (!host->data) {
2301                 /*
2302                  * The "data complete" interrupt is also used to
2303                  * indicate that a busy state has ended. See comment
2304                  * above in sdhci_cmd_irq().
2305                  */
2306                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2307                         if (intmask & SDHCI_INT_DATA_END) {
2308                                 sdhci_finish_command(host);
2309                                 return;
2310                         }
2311                 }
2312 
2313                 pr_err("%s: Got data interrupt 0x%08x even "
2314                         "though no data operation was in progress.\n",
2315                         mmc_hostname(host->mmc), (unsigned)intmask);
2316                 sdhci_dumpregs(host);
2317 
2318                 return;
2319         }
2320 
2321         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2322                 host->data->error = -ETIMEDOUT;
2323         else if (intmask & SDHCI_INT_DATA_END_BIT)
2324                 host->data->error = -EILSEQ;
2325         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2326                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2327                         != MMC_BUS_TEST_R)
2328                 host->data->error = -EILSEQ;
2329         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2330                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2331                 sdhci_show_adma_error(host);
2332                 host->data->error = -EIO;
2333                 if (host->ops->adma_workaround)
2334                         host->ops->adma_workaround(host, intmask);
2335         }
2336 
2337         if (host->data->error)
2338                 sdhci_finish_data(host);
2339         else {
2340                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2341                         sdhci_transfer_pio(host);
2342 
2343                 /*
2344                  * We currently don't do anything fancy with DMA
2345                  * boundaries, but as we can't disable the feature
2346                  * we need to at least restart the transfer.
2347                  *
2348                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2349                  * should return a valid address to continue from, but as
2350                  * some controllers are faulty, don't trust them.
2351                  */
2352                 if (intmask & SDHCI_INT_DMA_END) {
2353                         u32 dmastart, dmanow;
2354                         dmastart = sg_dma_address(host->data->sg);
2355                         dmanow = dmastart + host->data->bytes_xfered;
2356                         /*
2357                          * Force update to the next DMA block boundary.
2358                          */
2359                         dmanow = (dmanow &
2360                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2361                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2362                         host->data->bytes_xfered = dmanow - dmastart;
2363                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2364                                 " next 0x%08x\n",
2365                                 mmc_hostname(host->mmc), dmastart,
2366                                 host->data->bytes_xfered, dmanow);
2367                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2368                 }
2369 
2370                 if (intmask & SDHCI_INT_DATA_END) {
2371                         if (host->cmd) {
2372                                 /*
2373                                  * Data managed to finish before the
2374                                  * command completed. Make sure we do
2375                                  * things in the proper order.
2376                                  */
2377                                 host->data_early = 1;
2378                         } else {
2379                                 sdhci_finish_data(host);
2380                         }
2381                 }
2382         }
2383 }
2384 
2385 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2386 {
2387         irqreturn_t result = IRQ_NONE;
2388         struct sdhci_host *host = dev_id;
2389         u32 intmask, mask, unexpected = 0;
2390         int max_loops = 16;
2391 
2392         spin_lock(&host->lock);
2393 
2394         if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2395                 spin_unlock(&host->lock);
2396                 return IRQ_NONE;
2397         }
2398 
2399         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2400         if (!intmask || intmask == 0xffffffff) {
2401                 result = IRQ_NONE;
2402                 goto out;
2403         }
2404 
2405         do {
2406                 /* Clear selected interrupts. */
2407                 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2408                                   SDHCI_INT_BUS_POWER);
2409                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2410 
2411                 DBG("*** %s got interrupt: 0x%08x\n",
2412                         mmc_hostname(host->mmc), intmask);
2413 
2414                 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2415                         u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2416                                       SDHCI_CARD_PRESENT;
2417 
2418                         /*
2419                          * There is a observation on i.mx esdhc.  INSERT
2420                          * bit will be immediately set again when it gets
2421                          * cleared, if a card is inserted.  We have to mask
2422                          * the irq to prevent interrupt storm which will
2423                          * freeze the system.  And the REMOVE gets the
2424                          * same situation.
2425                          *
2426                          * More testing are needed here to ensure it works
2427                          * for other platforms though.
2428                          */
2429                         host->ier &= ~(SDHCI_INT_CARD_INSERT |
2430                                        SDHCI_INT_CARD_REMOVE);
2431                         host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2432                                                SDHCI_INT_CARD_INSERT;
2433                         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2434                         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2435 
2436                         sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2437                                      SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2438 
2439                         host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2440                                                        SDHCI_INT_CARD_REMOVE);
2441                         result = IRQ_WAKE_THREAD;
2442                 }
2443 
2444                 if (intmask & SDHCI_INT_CMD_MASK)
2445                         sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2446 
2447                 if (intmask & SDHCI_INT_DATA_MASK)
2448                         sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2449 
2450                 if (intmask & SDHCI_INT_BUS_POWER)
2451                         pr_err("%s: Card is consuming too much power!\n",
2452                                 mmc_hostname(host->mmc));
2453 
2454                 if (intmask & SDHCI_INT_CARD_INT) {
2455                         sdhci_enable_sdio_irq_nolock(host, false);
2456                         host->thread_isr |= SDHCI_INT_CARD_INT;
2457                         result = IRQ_WAKE_THREAD;
2458                 }
2459 
2460                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2461                              SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2462                              SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2463                              SDHCI_INT_CARD_INT);
2464 
2465                 if (intmask) {
2466                         unexpected |= intmask;
2467                         sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2468                 }
2469 
2470                 if (result == IRQ_NONE)
2471                         result = IRQ_HANDLED;
2472 
2473                 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2474         } while (intmask && --max_loops);
2475 out:
2476         spin_unlock(&host->lock);
2477 
2478         if (unexpected) {
2479                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2480                            mmc_hostname(host->mmc), unexpected);
2481                 sdhci_dumpregs(host);
2482         }
2483 
2484         return result;
2485 }
2486 
2487 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2488 {
2489         struct sdhci_host *host = dev_id;
2490         unsigned long flags;
2491         u32 isr;
2492 
2493         spin_lock_irqsave(&host->lock, flags);
2494         isr = host->thread_isr;
2495         host->thread_isr = 0;
2496         spin_unlock_irqrestore(&host->lock, flags);
2497 
2498         if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2499                 sdhci_card_event(host->mmc);
2500                 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2501         }
2502 
2503         if (isr & SDHCI_INT_CARD_INT) {
2504                 sdio_run_irqs(host->mmc);
2505 
2506                 spin_lock_irqsave(&host->lock, flags);
2507                 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2508                         sdhci_enable_sdio_irq_nolock(host, true);
2509                 spin_unlock_irqrestore(&host->lock, flags);
2510         }
2511 
2512         return isr ? IRQ_HANDLED : IRQ_NONE;
2513 }
2514 
2515 /*****************************************************************************\
2516  *                                                                           *
2517  * Suspend/resume                                                            *
2518  *                                                                           *
2519 \*****************************************************************************/
2520 
2521 #ifdef CONFIG_PM
2522 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2523 {
2524         u8 val;
2525         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2526                         | SDHCI_WAKE_ON_INT;
2527 
2528         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2529         val |= mask ;
2530         /* Avoid fake wake up */
2531         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2532                 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2533         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2534 }
2535 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2536 
2537 void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2538 {
2539         u8 val;
2540         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2541                         | SDHCI_WAKE_ON_INT;
2542 
2543         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2544         val &= ~mask;
2545         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2546 }
2547 EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
2548 
2549 int sdhci_suspend_host(struct sdhci_host *host)
2550 {
2551         sdhci_disable_card_detection(host);
2552 
2553         /* Disable tuning since we are suspending */
2554         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2555                 del_timer_sync(&host->tuning_timer);
2556                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2557         }
2558 
2559         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2560                 host->ier = 0;
2561                 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2562                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2563                 free_irq(host->irq, host);
2564         } else {
2565                 sdhci_enable_irq_wakeups(host);
2566                 enable_irq_wake(host->irq);
2567         }
2568         return 0;
2569 }
2570 
2571 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2572 
2573 int sdhci_resume_host(struct sdhci_host *host)
2574 {
2575         int ret = 0;
2576 
2577         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2578                 if (host->ops->enable_dma)
2579                         host->ops->enable_dma(host);
2580         }
2581 
2582         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2583                 ret = request_threaded_irq(host->irq, sdhci_irq,
2584                                            sdhci_thread_irq, IRQF_SHARED,
2585                                            mmc_hostname(host->mmc), host);
2586                 if (ret)
2587                         return ret;
2588         } else {
2589                 sdhci_disable_irq_wakeups(host);
2590                 disable_irq_wake(host->irq);
2591         }
2592 
2593         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2594             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2595                 /* Card keeps power but host controller does not */
2596                 sdhci_init(host, 0);
2597                 host->pwr = 0;
2598                 host->clock = 0;
2599                 sdhci_do_set_ios(host, &host->mmc->ios);
2600         } else {
2601                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2602                 mmiowb();
2603         }
2604 
2605         sdhci_enable_card_detection(host);
2606 
2607         /* Set the re-tuning expiration flag */
2608         if (host->flags & SDHCI_USING_RETUNING_TIMER)
2609                 host->flags |= SDHCI_NEEDS_RETUNING;
2610 
2611         return ret;
2612 }
2613 
2614 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2615 #endif /* CONFIG_PM */
2616 
2617 #ifdef CONFIG_PM_RUNTIME
2618 
2619 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2620 {
2621         return pm_runtime_get_sync(host->mmc->parent);
2622 }
2623 
2624 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2625 {
2626         pm_runtime_mark_last_busy(host->mmc->parent);
2627         return pm_runtime_put_autosuspend(host->mmc->parent);
2628 }
2629 
2630 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2631 {
2632         if (host->runtime_suspended || host->bus_on)
2633                 return;
2634         host->bus_on = true;
2635         pm_runtime_get_noresume(host->mmc->parent);
2636 }
2637 
2638 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2639 {
2640         if (host->runtime_suspended || !host->bus_on)
2641                 return;
2642         host->bus_on = false;
2643         pm_runtime_put_noidle(host->mmc->parent);
2644 }
2645 
2646 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2647 {
2648         unsigned long flags;
2649 
2650         /* Disable tuning since we are suspending */
2651         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2652                 del_timer_sync(&host->tuning_timer);
2653                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2654         }
2655 
2656         spin_lock_irqsave(&host->lock, flags);
2657         host->ier &= SDHCI_INT_CARD_INT;
2658         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2659         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2660         spin_unlock_irqrestore(&host->lock, flags);
2661 
2662         synchronize_hardirq(host->irq);
2663 
2664         spin_lock_irqsave(&host->lock, flags);
2665         host->runtime_suspended = true;
2666         spin_unlock_irqrestore(&host->lock, flags);
2667 
2668         return 0;
2669 }
2670 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2671 
2672 int sdhci_runtime_resume_host(struct sdhci_host *host)
2673 {
2674         unsigned long flags;
2675         int host_flags = host->flags;
2676 
2677         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2678                 if (host->ops->enable_dma)
2679                         host->ops->enable_dma(host);
2680         }
2681 
2682         sdhci_init(host, 0);
2683 
2684         /* Force clock and power re-program */
2685         host->pwr = 0;
2686         host->clock = 0;
2687         sdhci_do_set_ios(host, &host->mmc->ios);
2688 
2689         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2690         if ((host_flags & SDHCI_PV_ENABLED) &&
2691                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2692                 spin_lock_irqsave(&host->lock, flags);
2693                 sdhci_enable_preset_value(host, true);
2694                 spin_unlock_irqrestore(&host->lock, flags);
2695         }
2696 
2697         /* Set the re-tuning expiration flag */
2698         if (host->flags & SDHCI_USING_RETUNING_TIMER)
2699                 host->flags |= SDHCI_NEEDS_RETUNING;
2700 
2701         spin_lock_irqsave(&host->lock, flags);
2702 
2703         host->runtime_suspended = false;
2704 
2705         /* Enable SDIO IRQ */
2706         if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2707                 sdhci_enable_sdio_irq_nolock(host, true);
2708 
2709         /* Enable Card Detection */
2710         sdhci_enable_card_detection(host);
2711 
2712         spin_unlock_irqrestore(&host->lock, flags);
2713 
2714         return 0;
2715 }
2716 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2717 
2718 #endif
2719 
2720 /*****************************************************************************\
2721  *                                                                           *
2722  * Device allocation/registration                                            *
2723  *                                                                           *
2724 \*****************************************************************************/
2725 
2726 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2727         size_t priv_size)
2728 {
2729         struct mmc_host *mmc;
2730         struct sdhci_host *host;
2731 
2732         WARN_ON(dev == NULL);
2733 
2734         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2735         if (!mmc)
2736                 return ERR_PTR(-ENOMEM);
2737 
2738         host = mmc_priv(mmc);
2739         host->mmc = mmc;
2740 
2741         return host;
2742 }
2743 
2744 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2745 
2746 int sdhci_add_host(struct sdhci_host *host)
2747 {
2748         struct mmc_host *mmc;
2749         u32 caps[2] = {0, 0};
2750         u32 max_current_caps;
2751         unsigned int ocr_avail;
2752         int ret;
2753 
2754         WARN_ON(host == NULL);
2755         if (host == NULL)
2756                 return -EINVAL;
2757 
2758         mmc = host->mmc;
2759 
2760         if (debug_quirks)
2761                 host->quirks = debug_quirks;
2762         if (debug_quirks2)
2763                 host->quirks2 = debug_quirks2;
2764 
2765         sdhci_do_reset(host, SDHCI_RESET_ALL);
2766 
2767         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2768         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2769                                 >> SDHCI_SPEC_VER_SHIFT;
2770         if (host->version > SDHCI_SPEC_300) {
2771                 pr_err("%s: Unknown controller version (%d). "
2772                         "You may experience problems.\n", mmc_hostname(mmc),
2773                         host->version);
2774         }
2775 
2776         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2777                 sdhci_readl(host, SDHCI_CAPABILITIES);
2778 
2779         if (host->version >= SDHCI_SPEC_300)
2780                 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2781                         host->caps1 :
2782                         sdhci_readl(host, SDHCI_CAPABILITIES_1);
2783 
2784         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2785                 host->flags |= SDHCI_USE_SDMA;
2786         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2787                 DBG("Controller doesn't have SDMA capability\n");
2788         else
2789                 host->flags |= SDHCI_USE_SDMA;
2790 
2791         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2792                 (host->flags & SDHCI_USE_SDMA)) {
2793                 DBG("Disabling DMA as it is marked broken\n");
2794                 host->flags &= ~SDHCI_USE_SDMA;
2795         }
2796 
2797         if ((host->version >= SDHCI_SPEC_200) &&
2798                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2799                 host->flags |= SDHCI_USE_ADMA;
2800 
2801         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2802                 (host->flags & SDHCI_USE_ADMA)) {
2803                 DBG("Disabling ADMA as it is marked broken\n");
2804                 host->flags &= ~SDHCI_USE_ADMA;
2805         }
2806 
2807         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2808                 if (host->ops->enable_dma) {
2809                         if (host->ops->enable_dma(host)) {
2810                                 pr_warning("%s: No suitable DMA "
2811                                         "available. Falling back to PIO.\n",
2812                                         mmc_hostname(mmc));
2813                                 host->flags &=
2814                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2815                         }
2816                 }
2817         }
2818 
2819         if (host->flags & SDHCI_USE_ADMA) {
2820                 /*
2821                  * We need to allocate descriptors for all sg entries
2822                  * (128) and potentially one alignment transfer for
2823                  * each of those entries.
2824                  */
2825                 host->adma_desc = dma_alloc_coherent(mmc_dev(mmc),
2826                                                      ADMA_SIZE, &host->adma_addr,
2827                                                      GFP_KERNEL);
2828                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2829                 if (!host->adma_desc || !host->align_buffer) {
2830                         dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
2831                                           host->adma_desc, host->adma_addr);
2832                         kfree(host->align_buffer);
2833                         pr_warning("%s: Unable to allocate ADMA "
2834                                 "buffers. Falling back to standard DMA.\n",
2835                                 mmc_hostname(mmc));
2836                         host->flags &= ~SDHCI_USE_ADMA;
2837                         host->adma_desc = NULL;
2838                         host->align_buffer = NULL;
2839                 } else if (host->adma_addr & 3) {
2840                         pr_warning("%s: unable to allocate aligned ADMA descriptor\n",
2841                                    mmc_hostname(mmc));
2842                         host->flags &= ~SDHCI_USE_ADMA;
2843                         dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
2844                                           host->adma_desc, host->adma_addr);
2845                         kfree(host->align_buffer);
2846                         host->adma_desc = NULL;
2847                         host->align_buffer = NULL;
2848                 }
2849         }
2850 
2851         /*
2852          * If we use DMA, then it's up to the caller to set the DMA
2853          * mask, but PIO does not need the hw shim so we set a new
2854          * mask here in that case.
2855          */
2856         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2857                 host->dma_mask = DMA_BIT_MASK(64);
2858                 mmc_dev(mmc)->dma_mask = &host->dma_mask;
2859         }
2860 
2861         if (host->version >= SDHCI_SPEC_300)
2862                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2863                         >> SDHCI_CLOCK_BASE_SHIFT;
2864         else
2865                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2866                         >> SDHCI_CLOCK_BASE_SHIFT;
2867 
2868         host->max_clk *= 1000000;
2869         if (host->max_clk == 0 || host->quirks &
2870                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2871                 if (!host->ops->get_max_clock) {
2872                         pr_err("%s: Hardware doesn't specify base clock "
2873                                "frequency.\n", mmc_hostname(mmc));
2874                         return -ENODEV;
2875                 }
2876                 host->max_clk = host->ops->get_max_clock(host);
2877         }
2878 
2879         /*
2880          * In case of Host Controller v3.00, find out whether clock
2881          * multiplier is supported.
2882          */
2883         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2884                         SDHCI_CLOCK_MUL_SHIFT;
2885 
2886         /*
2887          * In case the value in Clock Multiplier is 0, then programmable
2888          * clock mode is not supported, otherwise the actual clock
2889          * multiplier is one more than the value of Clock Multiplier
2890          * in the Capabilities Register.
2891          */
2892         if (host->clk_mul)
2893                 host->clk_mul += 1;
2894 
2895         /*
2896          * Set host parameters.
2897          */
2898         mmc->ops = &sdhci_ops;
2899         mmc->f_max = host->max_clk;
2900         if (host->ops->get_min_clock)
2901                 mmc->f_min = host->ops->get_min_clock(host);
2902         else if (host->version >= SDHCI_SPEC_300) {
2903                 if (host->clk_mul) {
2904                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2905                         mmc->f_max = host->max_clk * host->clk_mul;
2906                 } else
2907                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2908         } else
2909                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2910 
2911         host->timeout_clk =
2912                 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2913         if (host->timeout_clk == 0) {
2914                 if (host->ops->get_timeout_clock) {
2915                         host->timeout_clk = host->ops->get_timeout_clock(host);
2916                 } else if (!(host->quirks &
2917                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2918                         pr_err("%s: Hardware doesn't specify timeout clock "
2919                                "frequency.\n", mmc_hostname(mmc));
2920                         return -ENODEV;
2921                 }
2922         }
2923         if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2924                 host->timeout_clk *= 1000;
2925 
2926         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2927                 host->timeout_clk = mmc->f_max / 1000;
2928 
2929         mmc->max_busy_timeout = (1 << 27) / host->timeout_clk;
2930 
2931         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2932         mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2933 
2934         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2935                 host->flags |= SDHCI_AUTO_CMD12;
2936 
2937         /* Auto-CMD23 stuff only works in ADMA or PIO. */
2938         if ((host->version >= SDHCI_SPEC_300) &&
2939             ((host->flags & SDHCI_USE_ADMA) ||
2940              !(host->flags & SDHCI_USE_SDMA))) {
2941                 host->flags |= SDHCI_AUTO_CMD23;
2942                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2943         } else {
2944                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2945         }
2946 
2947         /*
2948          * A controller may support 8-bit width, but the board itself
2949          * might not have the pins brought out.  Boards that support
2950          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2951          * their platform code before calling sdhci_add_host(), and we
2952          * won't assume 8-bit width for hosts without that CAP.
2953          */
2954         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2955                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2956 
2957         if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2958                 mmc->caps &= ~MMC_CAP_CMD23;
2959 
2960         if (caps[0] & SDHCI_CAN_DO_HISPD)
2961                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2962 
2963         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2964             !(mmc->caps & MMC_CAP_NONREMOVABLE))
2965                 mmc->caps |= MMC_CAP_NEEDS_POLL;
2966 
2967         /* If there are external regulators, get them */
2968         if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
2969                 return -EPROBE_DEFER;
2970 
2971         /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
2972         if (!IS_ERR(mmc->supply.vqmmc)) {
2973                 ret = regulator_enable(mmc->supply.vqmmc);
2974                 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
2975                                                     1950000))
2976                         caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
2977                                         SDHCI_SUPPORT_SDR50 |
2978                                         SDHCI_SUPPORT_DDR50);
2979                 if (ret) {
2980                         pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
2981                                 mmc_hostname(mmc), ret);
2982                         mmc->supply.vqmmc = NULL;
2983                 }
2984         }
2985 
2986         if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
2987                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2988                        SDHCI_SUPPORT_DDR50);
2989 
2990         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2991         if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2992                        SDHCI_SUPPORT_DDR50))
2993                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2994 
2995         /* SDR104 supports also implies SDR50 support */
2996         if (caps[1] & SDHCI_SUPPORT_SDR104) {
2997                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2998                 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
2999                  * field can be promoted to support HS200.
3000                  */
3001                 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3002                         mmc->caps2 |= MMC_CAP2_HS200;
3003         } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3004                 mmc->caps |= MMC_CAP_UHS_SDR50;
3005 
3006         if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3007                 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3008                 mmc->caps |= MMC_CAP_UHS_DDR50;
3009 
3010         /* Does the host need tuning for SDR50? */
3011         if (caps[1] & SDHCI_USE_SDR50_TUNING)
3012                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3013 
3014         /* Does the host need tuning for SDR104 / HS200? */
3015         if (mmc->caps2 & MMC_CAP2_HS200)
3016                 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3017 
3018         /* Driver Type(s) (A, C, D) supported by the host */
3019         if (caps[1] & SDHCI_DRIVER_TYPE_A)
3020                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3021         if (caps[1] & SDHCI_DRIVER_TYPE_C)
3022                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3023         if (caps[1] & SDHCI_DRIVER_TYPE_D)
3024                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3025 
3026         /* Initial value for re-tuning timer count */
3027         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3028                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3029 
3030         /*
3031          * In case Re-tuning Timer is not disabled, the actual value of
3032          * re-tuning timer will be 2 ^ (n - 1).
3033          */
3034         if (host->tuning_count)
3035                 host->tuning_count = 1 << (host->tuning_count - 1);
3036 
3037         /* Re-tuning mode supported by the Host Controller */
3038         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3039                              SDHCI_RETUNING_MODE_SHIFT;
3040 
3041         ocr_avail = 0;
3042 
3043         /*
3044          * According to SD Host Controller spec v3.00, if the Host System
3045          * can afford more than 150mA, Host Driver should set XPC to 1. Also
3046          * the value is meaningful only if Voltage Support in the Capabilities
3047          * register is set. The actual current value is 4 times the register
3048          * value.
3049          */
3050         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3051         if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3052                 u32 curr = regulator_get_current_limit(mmc->supply.vmmc);
3053                 if (curr > 0) {
3054 
3055                         /* convert to SDHCI_MAX_CURRENT format */
3056                         curr = curr/1000;  /* convert to mA */
3057                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3058 
3059                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3060                         max_current_caps =
3061                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3062                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3063                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3064                 }
3065         }
3066 
3067         if (caps[0] & SDHCI_CAN_VDD_330) {
3068                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3069 
3070                 mmc->max_current_330 = ((max_current_caps &
3071                                    SDHCI_MAX_CURRENT_330_MASK) >>
3072                                    SDHCI_MAX_CURRENT_330_SHIFT) *
3073                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3074         }
3075         if (caps[0] & SDHCI_CAN_VDD_300) {
3076                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3077 
3078                 mmc->max_current_300 = ((max_current_caps &
3079                                    SDHCI_MAX_CURRENT_300_MASK) >>
3080                                    SDHCI_MAX_CURRENT_300_SHIFT) *
3081                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3082         }
3083         if (caps[0] & SDHCI_CAN_VDD_180) {
3084                 ocr_avail |= MMC_VDD_165_195;
3085 
3086                 mmc->max_current_180 = ((max_current_caps &
3087                                    SDHCI_MAX_CURRENT_180_MASK) >>
3088                                    SDHCI_MAX_CURRENT_180_SHIFT) *
3089                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3090         }
3091 
3092         /* If OCR set by external regulators, use it instead */
3093         if (mmc->ocr_avail)
3094                 ocr_avail = mmc->ocr_avail;
3095 
3096         if (host->ocr_mask)
3097                 ocr_avail &= host->ocr_mask;
3098 
3099         mmc->ocr_avail = ocr_avail;
3100         mmc->ocr_avail_sdio = ocr_avail;
3101         if (host->ocr_avail_sdio)
3102                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3103         mmc->ocr_avail_sd = ocr_avail;
3104         if (host->ocr_avail_sd)
3105                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3106         else /* normal SD controllers don't support 1.8V */
3107                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3108         mmc->ocr_avail_mmc = ocr_avail;
3109         if (host->ocr_avail_mmc)
3110                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3111 
3112         if (mmc->ocr_avail == 0) {
3113                 pr_err("%s: Hardware doesn't report any "
3114                         "support voltages.\n", mmc_hostname(mmc));
3115                 return -ENODEV;
3116         }
3117 
3118         spin_lock_init(&host->lock);
3119 
3120         /*
3121          * Maximum number of segments. Depends on if the hardware
3122          * can do scatter/gather or not.
3123          */
3124         if (host->flags & SDHCI_USE_ADMA)
3125                 mmc->max_segs = 128;
3126         else if (host->flags & SDHCI_USE_SDMA)
3127                 mmc->max_segs = 1;
3128         else /* PIO */
3129                 mmc->max_segs = 128;
3130 
3131         /*
3132          * Maximum number of sectors in one transfer. Limited by DMA boundary
3133          * size (512KiB).
3134          */
3135         mmc->max_req_size = 524288;
3136 
3137         /*
3138          * Maximum segment size. Could be one segment with the maximum number
3139          * of bytes. When doing hardware scatter/gather, each entry cannot
3140          * be larger than 64 KiB though.
3141          */
3142         if (host->flags & SDHCI_USE_ADMA) {
3143                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3144                         mmc->max_seg_size = 65535;
3145                 else
3146                         mmc->max_seg_size = 65536;
3147         } else {
3148                 mmc->max_seg_size = mmc->max_req_size;
3149         }
3150 
3151         /*
3152          * Maximum block size. This varies from controller to controller and
3153          * is specified in the capabilities register.
3154          */
3155         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3156                 mmc->max_blk_size = 2;
3157         } else {
3158                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3159                                 SDHCI_MAX_BLOCK_SHIFT;
3160                 if (mmc->max_blk_size >= 3) {
3161                         pr_warning("%s: Invalid maximum block size, "
3162                                 "assuming 512 bytes\n", mmc_hostname(mmc));
3163                         mmc->max_blk_size = 0;
3164                 }
3165         }
3166 
3167         mmc->max_blk_size = 512 << mmc->max_blk_size;
3168 
3169         /*
3170          * Maximum block count.
3171          */
3172         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3173 
3174         /*
3175          * Init tasklets.
3176          */
3177         tasklet_init(&host->finish_tasklet,
3178                 sdhci_tasklet_finish, (unsigned long)host);
3179 
3180         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3181 
3182         if (host->version >= SDHCI_SPEC_300) {
3183                 init_waitqueue_head(&host->buf_ready_int);
3184 
3185                 /* Initialize re-tuning timer */
3186                 init_timer(&host->tuning_timer);
3187                 host->tuning_timer.data = (unsigned long)host;
3188                 host->tuning_timer.function = sdhci_tuning_timer;
3189         }
3190 
3191         sdhci_init(host, 0);
3192 
3193         ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3194                                    IRQF_SHARED, mmc_hostname(mmc), host);
3195         if (ret) {
3196                 pr_err("%s: Failed to request IRQ %d: %d\n",
3197                        mmc_hostname(mmc), host->irq, ret);
3198                 goto untasklet;
3199         }
3200 
3201 #ifdef CONFIG_MMC_DEBUG
3202         sdhci_dumpregs(host);
3203 #endif
3204 
3205 #ifdef SDHCI_USE_LEDS_CLASS
3206         snprintf(host->led_name, sizeof(host->led_name),
3207                 "%s::", mmc_hostname(mmc));
3208         host->led.name = host->led_name;
3209         host->led.brightness = LED_OFF;
3210         host->led.default_trigger = mmc_hostname(mmc);
3211         host->led.brightness_set = sdhci_led_control;
3212 
3213         ret = led_classdev_register(mmc_dev(mmc), &host->led);
3214         if (ret) {
3215                 pr_err("%s: Failed to register LED device: %d\n",
3216                        mmc_hostname(mmc), ret);
3217                 goto reset;
3218         }
3219 #endif
3220 
3221         mmiowb();
3222 
3223         mmc_add_host(mmc);
3224 
3225         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3226                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3227                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3228                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3229 
3230         sdhci_enable_card_detection(host);
3231 
3232         return 0;
3233 
3234 #ifdef SDHCI_USE_LEDS_CLASS
3235 reset:
3236         sdhci_do_reset(host, SDHCI_RESET_ALL);
3237         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3238         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3239         free_irq(host->irq, host);
3240 #endif
3241 untasklet:
3242         tasklet_kill(&host->finish_tasklet);
3243 
3244         return ret;
3245 }
3246 
3247 EXPORT_SYMBOL_GPL(sdhci_add_host);
3248 
3249 void sdhci_remove_host(struct sdhci_host *host, int dead)
3250 {
3251         struct mmc_host *mmc = host->mmc;
3252         unsigned long flags;
3253 
3254         if (dead) {
3255                 spin_lock_irqsave(&host->lock, flags);
3256 
3257                 host->flags |= SDHCI_DEVICE_DEAD;
3258 
3259                 if (host->mrq) {
3260                         pr_err("%s: Controller removed during "
3261                                 " transfer!\n", mmc_hostname(mmc));
3262 
3263                         host->mrq->cmd->error = -ENOMEDIUM;
3264                         tasklet_schedule(&host->finish_tasklet);
3265                 }
3266 
3267                 spin_unlock_irqrestore(&host->lock, flags);
3268         }
3269 
3270         sdhci_disable_card_detection(host);
3271 
3272         mmc_remove_host(mmc);
3273 
3274 #ifdef SDHCI_USE_LEDS_CLASS
3275         led_classdev_unregister(&host->led);
3276 #endif
3277 
3278         if (!dead)
3279                 sdhci_do_reset(host, SDHCI_RESET_ALL);
3280 
3281         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3282         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3283         free_irq(host->irq, host);
3284 
3285         del_timer_sync(&host->timer);
3286 
3287         tasklet_kill(&host->finish_tasklet);
3288 
3289         if (!IS_ERR(mmc->supply.vmmc))
3290                 regulator_disable(mmc->supply.vmmc);
3291 
3292         if (!IS_ERR(mmc->supply.vqmmc))
3293                 regulator_disable(mmc->supply.vqmmc);
3294 
3295         if (host->adma_desc)
3296                 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
3297                                   host->adma_desc, host->adma_addr);
3298         kfree(host->align_buffer);
3299 
3300         host->adma_desc = NULL;
3301         host->align_buffer = NULL;
3302 }
3303 
3304 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3305 
3306 void sdhci_free_host(struct sdhci_host *host)
3307 {
3308         mmc_free_host(host->mmc);
3309 }
3310 
3311 EXPORT_SYMBOL_GPL(sdhci_free_host);
3312 
3313 /*****************************************************************************\
3314  *                                                                           *
3315  * Driver init/exit                                                          *
3316  *                                                                           *
3317 \*****************************************************************************/
3318 
3319 static int __init sdhci_drv_init(void)
3320 {
3321         pr_info(DRIVER_NAME
3322                 ": Secure Digital Host Controller Interface driver\n");
3323         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3324 
3325         return 0;
3326 }
3327 
3328 static void __exit sdhci_drv_exit(void)
3329 {
3330 }
3331 
3332 module_init(sdhci_drv_init);
3333 module_exit(sdhci_drv_exit);
3334 
3335 module_param(debug_quirks, uint, 0444);
3336 module_param(debug_quirks2, uint, 0444);
3337 
3338 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3339 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3340 MODULE_LICENSE("GPL");
3341 
3342 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3343 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
3344 

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