Version:  2.0.40 2.2.26 2.4.37 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19

Linux/drivers/mmc/host/sdhci-s3c.c

  1 /* linux/drivers/mmc/host/sdhci-s3c.c
  2  *
  3  * Copyright 2008 Openmoko Inc.
  4  * Copyright 2008 Simtec Electronics
  5  *      Ben Dooks <ben@simtec.co.uk>
  6  *      http://armlinux.simtec.co.uk/
  7  *
  8  * SDHCI (HSMMC) support for Samsung SoC
  9  *
 10  * This program is free software; you can redistribute it and/or modify
 11  * it under the terms of the GNU General Public License version 2 as
 12  * published by the Free Software Foundation.
 13  */
 14 
 15 #include <linux/delay.h>
 16 #include <linux/dma-mapping.h>
 17 #include <linux/platform_device.h>
 18 #include <linux/platform_data/mmc-sdhci-s3c.h>
 19 #include <linux/slab.h>
 20 #include <linux/clk.h>
 21 #include <linux/io.h>
 22 #include <linux/gpio.h>
 23 #include <linux/module.h>
 24 #include <linux/of.h>
 25 #include <linux/of_gpio.h>
 26 #include <linux/pm.h>
 27 #include <linux/pm_runtime.h>
 28 
 29 #include <linux/mmc/host.h>
 30 
 31 #include "sdhci-s3c-regs.h"
 32 #include "sdhci.h"
 33 
 34 #define MAX_BUS_CLK     (4)
 35 
 36 /**
 37  * struct sdhci_s3c - S3C SDHCI instance
 38  * @host: The SDHCI host created
 39  * @pdev: The platform device we where created from.
 40  * @ioarea: The resource created when we claimed the IO area.
 41  * @pdata: The platform data for this controller.
 42  * @cur_clk: The index of the current bus clock.
 43  * @clk_io: The clock for the internal bus interface.
 44  * @clk_bus: The clocks that are available for the SD/MMC bus clock.
 45  */
 46 struct sdhci_s3c {
 47         struct sdhci_host       *host;
 48         struct platform_device  *pdev;
 49         struct resource         *ioarea;
 50         struct s3c_sdhci_platdata *pdata;
 51         int                     cur_clk;
 52         int                     ext_cd_irq;
 53         int                     ext_cd_gpio;
 54 
 55         struct clk              *clk_io;
 56         struct clk              *clk_bus[MAX_BUS_CLK];
 57         unsigned long           clk_rates[MAX_BUS_CLK];
 58 
 59         bool                    no_divider;
 60 };
 61 
 62 /**
 63  * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
 64  * @sdhci_quirks: sdhci host specific quirks.
 65  *
 66  * Specifies platform specific configuration of sdhci controller.
 67  * Note: A structure for driver specific platform data is used for future
 68  * expansion of its usage.
 69  */
 70 struct sdhci_s3c_drv_data {
 71         unsigned int    sdhci_quirks;
 72         bool            no_divider;
 73 };
 74 
 75 static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
 76 {
 77         return sdhci_priv(host);
 78 }
 79 
 80 /**
 81  * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
 82  * @host: The SDHCI host instance.
 83  *
 84  * Callback to return the maximum clock rate acheivable by the controller.
 85 */
 86 static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
 87 {
 88         struct sdhci_s3c *ourhost = to_s3c(host);
 89         unsigned long rate, max = 0;
 90         int src;
 91 
 92         for (src = 0; src < MAX_BUS_CLK; src++) {
 93                 rate = ourhost->clk_rates[src];
 94                 if (rate > max)
 95                         max = rate;
 96         }
 97 
 98         return max;
 99 }
100 
101 /**
102  * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
103  * @ourhost: Our SDHCI instance.
104  * @src: The source clock index.
105  * @wanted: The clock frequency wanted.
106  */
107 static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
108                                              unsigned int src,
109                                              unsigned int wanted)
110 {
111         unsigned long rate;
112         struct clk *clksrc = ourhost->clk_bus[src];
113         int shift;
114 
115         if (IS_ERR(clksrc))
116                 return UINT_MAX;
117 
118         /*
119          * If controller uses a non-standard clock division, find the best clock
120          * speed possible with selected clock source and skip the division.
121          */
122         if (ourhost->no_divider) {
123                 rate = clk_round_rate(clksrc, wanted);
124                 return wanted - rate;
125         }
126 
127         rate = ourhost->clk_rates[src];
128 
129         for (shift = 0; shift <= 8; ++shift) {
130                 if ((rate >> shift) <= wanted)
131                         break;
132         }
133 
134         if (shift > 8) {
135                 dev_dbg(&ourhost->pdev->dev,
136                         "clk %d: rate %ld, min rate %lu > wanted %u\n",
137                         src, rate, rate / 256, wanted);
138                 return UINT_MAX;
139         }
140 
141         dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
142                 src, rate, wanted, rate >> shift);
143 
144         return wanted - (rate >> shift);
145 }
146 
147 /**
148  * sdhci_s3c_set_clock - callback on clock change
149  * @host: The SDHCI host being changed
150  * @clock: The clock rate being requested.
151  *
152  * When the card's clock is going to be changed, look at the new frequency
153  * and find the best clock source to go with it.
154 */
155 static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
156 {
157         struct sdhci_s3c *ourhost = to_s3c(host);
158         unsigned int best = UINT_MAX;
159         unsigned int delta;
160         int best_src = 0;
161         int src;
162         u32 ctrl;
163 
164         host->mmc->actual_clock = 0;
165 
166         /* don't bother if the clock is going off. */
167         if (clock == 0) {
168                 sdhci_set_clock(host, clock);
169                 return;
170         }
171 
172         for (src = 0; src < MAX_BUS_CLK; src++) {
173                 delta = sdhci_s3c_consider_clock(ourhost, src, clock);
174                 if (delta < best) {
175                         best = delta;
176                         best_src = src;
177                 }
178         }
179 
180         dev_dbg(&ourhost->pdev->dev,
181                 "selected source %d, clock %d, delta %d\n",
182                  best_src, clock, best);
183 
184         /* select the new clock source */
185         if (ourhost->cur_clk != best_src) {
186                 struct clk *clk = ourhost->clk_bus[best_src];
187 
188                 clk_prepare_enable(clk);
189                 if (ourhost->cur_clk >= 0)
190                         clk_disable_unprepare(
191                                         ourhost->clk_bus[ourhost->cur_clk]);
192 
193                 ourhost->cur_clk = best_src;
194                 host->max_clk = ourhost->clk_rates[best_src];
195         }
196 
197         /* turn clock off to card before changing clock source */
198         writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
199 
200         ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
201         ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
202         ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
203         writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
204 
205         /* reprogram default hardware configuration */
206         writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
207                 host->ioaddr + S3C64XX_SDHCI_CONTROL4);
208 
209         ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
210         ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
211                   S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
212                   S3C_SDHCI_CTRL2_ENFBCLKRX |
213                   S3C_SDHCI_CTRL2_DFCNT_NONE |
214                   S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
215         writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
216 
217         /* reconfigure the controller for new clock rate */
218         ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
219         if (clock < 25 * 1000000)
220                 ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
221         writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
222 
223         sdhci_set_clock(host, clock);
224 }
225 
226 /**
227  * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
228  * @host: The SDHCI host being queried
229  *
230  * To init mmc host properly a minimal clock value is needed. For high system
231  * bus clock's values the standard formula gives values out of allowed range.
232  * The clock still can be set to lower values, if clock source other then
233  * system bus is selected.
234 */
235 static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
236 {
237         struct sdhci_s3c *ourhost = to_s3c(host);
238         unsigned long rate, min = ULONG_MAX;
239         int src;
240 
241         for (src = 0; src < MAX_BUS_CLK; src++) {
242                 rate = ourhost->clk_rates[src] / 256;
243                 if (!rate)
244                         continue;
245                 if (rate < min)
246                         min = rate;
247         }
248 
249         return min;
250 }
251 
252 /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
253 static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
254 {
255         struct sdhci_s3c *ourhost = to_s3c(host);
256         unsigned long rate, max = 0;
257         int src;
258 
259         for (src = 0; src < MAX_BUS_CLK; src++) {
260                 struct clk *clk;
261 
262                 clk = ourhost->clk_bus[src];
263                 if (IS_ERR(clk))
264                         continue;
265 
266                 rate = clk_round_rate(clk, ULONG_MAX);
267                 if (rate > max)
268                         max = rate;
269         }
270 
271         return max;
272 }
273 
274 /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
275 static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
276 {
277         struct sdhci_s3c *ourhost = to_s3c(host);
278         unsigned long rate, min = ULONG_MAX;
279         int src;
280 
281         for (src = 0; src < MAX_BUS_CLK; src++) {
282                 struct clk *clk;
283 
284                 clk = ourhost->clk_bus[src];
285                 if (IS_ERR(clk))
286                         continue;
287 
288                 rate = clk_round_rate(clk, 0);
289                 if (rate < min)
290                         min = rate;
291         }
292 
293         return min;
294 }
295 
296 /* sdhci_cmu_set_clock - callback on clock change.*/
297 static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
298 {
299         struct sdhci_s3c *ourhost = to_s3c(host);
300         struct device *dev = &ourhost->pdev->dev;
301         unsigned long timeout;
302         u16 clk = 0;
303         int ret;
304 
305         host->mmc->actual_clock = 0;
306 
307         /* If the clock is going off, set to 0 at clock control register */
308         if (clock == 0) {
309                 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
310                 return;
311         }
312 
313         sdhci_s3c_set_clock(host, clock);
314 
315         ret = clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
316         if (ret != 0) {
317                 dev_err(dev, "%s: failed to set clock rate %uHz\n",
318                         mmc_hostname(host->mmc), clock);
319                 return;
320         }
321 
322         clk = SDHCI_CLOCK_INT_EN;
323         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
324 
325         /* Wait max 20 ms */
326         timeout = 20;
327         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
328                 & SDHCI_CLOCK_INT_STABLE)) {
329                 if (timeout == 0) {
330                         dev_err(dev, "%s: Internal clock never stabilised.\n",
331                                 mmc_hostname(host->mmc));
332                         return;
333                 }
334                 timeout--;
335                 mdelay(1);
336         }
337 
338         clk |= SDHCI_CLOCK_CARD_EN;
339         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
340 }
341 
342 /**
343  * sdhci_s3c_set_bus_width - support 8bit buswidth
344  * @host: The SDHCI host being queried
345  * @width: MMC_BUS_WIDTH_ macro for the bus width being requested
346  *
347  * We have 8-bit width support but is not a v3 controller.
348  * So we add platform_bus_width() and support 8bit width.
349  */
350 static void sdhci_s3c_set_bus_width(struct sdhci_host *host, int width)
351 {
352         u8 ctrl;
353 
354         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
355 
356         switch (width) {
357         case MMC_BUS_WIDTH_8:
358                 ctrl |= SDHCI_CTRL_8BITBUS;
359                 ctrl &= ~SDHCI_CTRL_4BITBUS;
360                 break;
361         case MMC_BUS_WIDTH_4:
362                 ctrl |= SDHCI_CTRL_4BITBUS;
363                 ctrl &= ~SDHCI_CTRL_8BITBUS;
364                 break;
365         default:
366                 ctrl &= ~SDHCI_CTRL_4BITBUS;
367                 ctrl &= ~SDHCI_CTRL_8BITBUS;
368                 break;
369         }
370 
371         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
372 }
373 
374 static struct sdhci_ops sdhci_s3c_ops = {
375         .get_max_clock          = sdhci_s3c_get_max_clk,
376         .set_clock              = sdhci_s3c_set_clock,
377         .get_min_clock          = sdhci_s3c_get_min_clock,
378         .set_bus_width          = sdhci_s3c_set_bus_width,
379         .reset                  = sdhci_reset,
380         .set_uhs_signaling      = sdhci_set_uhs_signaling,
381 };
382 
383 #ifdef CONFIG_OF
384 static int sdhci_s3c_parse_dt(struct device *dev,
385                 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
386 {
387         struct device_node *node = dev->of_node;
388         u32 max_width;
389 
390         /* if the bus-width property is not specified, assume width as 1 */
391         if (of_property_read_u32(node, "bus-width", &max_width))
392                 max_width = 1;
393         pdata->max_width = max_width;
394 
395         /* get the card detection method */
396         if (of_get_property(node, "broken-cd", NULL)) {
397                 pdata->cd_type = S3C_SDHCI_CD_NONE;
398                 return 0;
399         }
400 
401         if (of_get_property(node, "non-removable", NULL)) {
402                 pdata->cd_type = S3C_SDHCI_CD_PERMANENT;
403                 return 0;
404         }
405 
406         if (of_get_named_gpio(node, "cd-gpios", 0))
407                 return 0;
408 
409         /* assuming internal card detect that will be configured by pinctrl */
410         pdata->cd_type = S3C_SDHCI_CD_INTERNAL;
411         return 0;
412 }
413 #else
414 static int sdhci_s3c_parse_dt(struct device *dev,
415                 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
416 {
417         return -EINVAL;
418 }
419 #endif
420 
421 static const struct of_device_id sdhci_s3c_dt_match[];
422 
423 static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
424                         struct platform_device *pdev)
425 {
426 #ifdef CONFIG_OF
427         if (pdev->dev.of_node) {
428                 const struct of_device_id *match;
429                 match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node);
430                 return (struct sdhci_s3c_drv_data *)match->data;
431         }
432 #endif
433         return (struct sdhci_s3c_drv_data *)
434                         platform_get_device_id(pdev)->driver_data;
435 }
436 
437 static int sdhci_s3c_probe(struct platform_device *pdev)
438 {
439         struct s3c_sdhci_platdata *pdata;
440         struct sdhci_s3c_drv_data *drv_data;
441         struct device *dev = &pdev->dev;
442         struct sdhci_host *host;
443         struct sdhci_s3c *sc;
444         struct resource *res;
445         int ret, irq, ptr, clks;
446 
447         if (!pdev->dev.platform_data && !pdev->dev.of_node) {
448                 dev_err(dev, "no device data specified\n");
449                 return -ENOENT;
450         }
451 
452         irq = platform_get_irq(pdev, 0);
453         if (irq < 0) {
454                 dev_err(dev, "no irq specified\n");
455                 return irq;
456         }
457 
458         host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
459         if (IS_ERR(host)) {
460                 dev_err(dev, "sdhci_alloc_host() failed\n");
461                 return PTR_ERR(host);
462         }
463         sc = sdhci_priv(host);
464 
465         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
466         if (!pdata) {
467                 ret = -ENOMEM;
468                 goto err_pdata_io_clk;
469         }
470 
471         if (pdev->dev.of_node) {
472                 ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata);
473                 if (ret)
474                         goto err_pdata_io_clk;
475         } else {
476                 memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
477                 sc->ext_cd_gpio = -1; /* invalid gpio number */
478         }
479 
480         drv_data = sdhci_s3c_get_driver_data(pdev);
481 
482         sc->host = host;
483         sc->pdev = pdev;
484         sc->pdata = pdata;
485         sc->cur_clk = -1;
486 
487         platform_set_drvdata(pdev, host);
488 
489         sc->clk_io = devm_clk_get(dev, "hsmmc");
490         if (IS_ERR(sc->clk_io)) {
491                 dev_err(dev, "failed to get io clock\n");
492                 ret = PTR_ERR(sc->clk_io);
493                 goto err_pdata_io_clk;
494         }
495 
496         /* enable the local io clock and keep it running for the moment. */
497         clk_prepare_enable(sc->clk_io);
498 
499         for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
500                 char name[14];
501 
502                 snprintf(name, 14, "mmc_busclk.%d", ptr);
503                 sc->clk_bus[ptr] = devm_clk_get(dev, name);
504                 if (IS_ERR(sc->clk_bus[ptr]))
505                         continue;
506 
507                 clks++;
508                 sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]);
509 
510                 dev_info(dev, "clock source %d: %s (%ld Hz)\n",
511                                 ptr, name, sc->clk_rates[ptr]);
512         }
513 
514         if (clks == 0) {
515                 dev_err(dev, "failed to find any bus clocks\n");
516                 ret = -ENOENT;
517                 goto err_no_busclks;
518         }
519 
520         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
521         host->ioaddr = devm_ioremap_resource(&pdev->dev, res);
522         if (IS_ERR(host->ioaddr)) {
523                 ret = PTR_ERR(host->ioaddr);
524                 goto err_req_regs;
525         }
526 
527         /* Ensure we have minimal gpio selected CMD/CLK/Detect */
528         if (pdata->cfg_gpio)
529                 pdata->cfg_gpio(pdev, pdata->max_width);
530 
531         host->hw_name = "samsung-hsmmc";
532         host->ops = &sdhci_s3c_ops;
533         host->quirks = 0;
534         host->quirks2 = 0;
535         host->irq = irq;
536 
537         /* Setup quirks for the controller */
538         host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
539         host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
540         if (drv_data) {
541                 host->quirks |= drv_data->sdhci_quirks;
542                 sc->no_divider = drv_data->no_divider;
543         }
544 
545 #ifndef CONFIG_MMC_SDHCI_S3C_DMA
546 
547         /* we currently see overruns on errors, so disable the SDMA
548          * support as well. */
549         host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
550 
551 #endif /* CONFIG_MMC_SDHCI_S3C_DMA */
552 
553         /* It seems we do not get an DATA transfer complete on non-busy
554          * transfers, not sure if this is a problem with this specific
555          * SDHCI block, or a missing configuration that needs to be set. */
556         host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
557 
558         /* This host supports the Auto CMD12 */
559         host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
560 
561         /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
562         host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
563 
564         if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
565             pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
566                 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
567 
568         if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
569                 host->mmc->caps = MMC_CAP_NONREMOVABLE;
570 
571         switch (pdata->max_width) {
572         case 8:
573                 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
574         case 4:
575                 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
576                 break;
577         }
578 
579         if (pdata->pm_caps)
580                 host->mmc->pm_caps |= pdata->pm_caps;
581 
582         host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
583                          SDHCI_QUIRK_32BIT_DMA_SIZE);
584 
585         /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
586         host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
587 
588         /*
589          * If controller does not have internal clock divider,
590          * we can use overriding functions instead of default.
591          */
592         if (sc->no_divider) {
593                 sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
594                 sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
595                 sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
596         }
597 
598         /* It supports additional host capabilities if needed */
599         if (pdata->host_caps)
600                 host->mmc->caps |= pdata->host_caps;
601 
602         if (pdata->host_caps2)
603                 host->mmc->caps2 |= pdata->host_caps2;
604 
605         pm_runtime_enable(&pdev->dev);
606         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
607         pm_runtime_use_autosuspend(&pdev->dev);
608         pm_suspend_ignore_children(&pdev->dev, 1);
609 
610         mmc_of_parse(host->mmc);
611 
612         ret = sdhci_add_host(host);
613         if (ret) {
614                 dev_err(dev, "sdhci_add_host() failed\n");
615                 goto err_req_regs;
616         }
617 
618 #ifdef CONFIG_PM
619         if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
620                 clk_disable_unprepare(sc->clk_io);
621 #endif
622         return 0;
623 
624  err_req_regs:
625         pm_runtime_disable(&pdev->dev);
626 
627  err_no_busclks:
628         clk_disable_unprepare(sc->clk_io);
629 
630  err_pdata_io_clk:
631         sdhci_free_host(host);
632 
633         return ret;
634 }
635 
636 static int sdhci_s3c_remove(struct platform_device *pdev)
637 {
638         struct sdhci_host *host =  platform_get_drvdata(pdev);
639         struct sdhci_s3c *sc = sdhci_priv(host);
640 
641         if (sc->ext_cd_irq)
642                 free_irq(sc->ext_cd_irq, sc);
643 
644 #ifdef CONFIG_PM
645         if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
646                 clk_prepare_enable(sc->clk_io);
647 #endif
648         sdhci_remove_host(host, 1);
649 
650         pm_runtime_dont_use_autosuspend(&pdev->dev);
651         pm_runtime_disable(&pdev->dev);
652 
653         clk_disable_unprepare(sc->clk_io);
654 
655         sdhci_free_host(host);
656 
657         return 0;
658 }
659 
660 #ifdef CONFIG_PM_SLEEP
661 static int sdhci_s3c_suspend(struct device *dev)
662 {
663         struct sdhci_host *host = dev_get_drvdata(dev);
664 
665         return sdhci_suspend_host(host);
666 }
667 
668 static int sdhci_s3c_resume(struct device *dev)
669 {
670         struct sdhci_host *host = dev_get_drvdata(dev);
671 
672         return sdhci_resume_host(host);
673 }
674 #endif
675 
676 #ifdef CONFIG_PM
677 static int sdhci_s3c_runtime_suspend(struct device *dev)
678 {
679         struct sdhci_host *host = dev_get_drvdata(dev);
680         struct sdhci_s3c *ourhost = to_s3c(host);
681         struct clk *busclk = ourhost->clk_io;
682         int ret;
683 
684         ret = sdhci_runtime_suspend_host(host);
685 
686         if (ourhost->cur_clk >= 0)
687                 clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]);
688         clk_disable_unprepare(busclk);
689         return ret;
690 }
691 
692 static int sdhci_s3c_runtime_resume(struct device *dev)
693 {
694         struct sdhci_host *host = dev_get_drvdata(dev);
695         struct sdhci_s3c *ourhost = to_s3c(host);
696         struct clk *busclk = ourhost->clk_io;
697         int ret;
698 
699         clk_prepare_enable(busclk);
700         if (ourhost->cur_clk >= 0)
701                 clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]);
702         ret = sdhci_runtime_resume_host(host);
703         return ret;
704 }
705 #endif
706 
707 #ifdef CONFIG_PM
708 static const struct dev_pm_ops sdhci_s3c_pmops = {
709         SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
710         SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
711                            NULL)
712 };
713 
714 #define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops)
715 
716 #else
717 #define SDHCI_S3C_PMOPS NULL
718 #endif
719 
720 #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
721 static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
722         .no_divider = true,
723 };
724 #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data)
725 #else
726 #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)NULL)
727 #endif
728 
729 static struct platform_device_id sdhci_s3c_driver_ids[] = {
730         {
731                 .name           = "s3c-sdhci",
732                 .driver_data    = (kernel_ulong_t)NULL,
733         }, {
734                 .name           = "exynos4-sdhci",
735                 .driver_data    = EXYNOS4_SDHCI_DRV_DATA,
736         },
737         { }
738 };
739 MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
740 
741 #ifdef CONFIG_OF
742 static const struct of_device_id sdhci_s3c_dt_match[] = {
743         { .compatible = "samsung,s3c6410-sdhci", },
744         { .compatible = "samsung,exynos4210-sdhci",
745                 .data = (void *)EXYNOS4_SDHCI_DRV_DATA },
746         {},
747 };
748 MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match);
749 #endif
750 
751 static struct platform_driver sdhci_s3c_driver = {
752         .probe          = sdhci_s3c_probe,
753         .remove         = sdhci_s3c_remove,
754         .id_table       = sdhci_s3c_driver_ids,
755         .driver         = {
756                 .name   = "s3c-sdhci",
757                 .of_match_table = of_match_ptr(sdhci_s3c_dt_match),
758                 .pm     = SDHCI_S3C_PMOPS,
759         },
760 };
761 
762 module_platform_driver(sdhci_s3c_driver);
763 
764 MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
765 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
766 MODULE_LICENSE("GPL v2");
767 MODULE_ALIAS("platform:s3c-sdhci");
768 

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