Version:  2.0.40 2.2.26 2.4.37 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10

Linux/drivers/mmc/host/sdhci-s3c.c

  1 /* linux/drivers/mmc/host/sdhci-s3c.c
  2  *
  3  * Copyright 2008 Openmoko Inc.
  4  * Copyright 2008 Simtec Electronics
  5  *      Ben Dooks <ben@simtec.co.uk>
  6  *      http://armlinux.simtec.co.uk/
  7  *
  8  * SDHCI (HSMMC) support for Samsung SoC
  9  *
 10  * This program is free software; you can redistribute it and/or modify
 11  * it under the terms of the GNU General Public License version 2 as
 12  * published by the Free Software Foundation.
 13  */
 14 
 15 #include <linux/spinlock.h>
 16 #include <linux/delay.h>
 17 #include <linux/dma-mapping.h>
 18 #include <linux/platform_device.h>
 19 #include <linux/platform_data/mmc-sdhci-s3c.h>
 20 #include <linux/slab.h>
 21 #include <linux/clk.h>
 22 #include <linux/io.h>
 23 #include <linux/gpio.h>
 24 #include <linux/module.h>
 25 #include <linux/of.h>
 26 #include <linux/of_gpio.h>
 27 #include <linux/pm.h>
 28 #include <linux/pm_runtime.h>
 29 
 30 #include <linux/mmc/host.h>
 31 
 32 #include "sdhci-s3c-regs.h"
 33 #include "sdhci.h"
 34 
 35 #define MAX_BUS_CLK     (4)
 36 
 37 /**
 38  * struct sdhci_s3c - S3C SDHCI instance
 39  * @host: The SDHCI host created
 40  * @pdev: The platform device we where created from.
 41  * @ioarea: The resource created when we claimed the IO area.
 42  * @pdata: The platform data for this controller.
 43  * @cur_clk: The index of the current bus clock.
 44  * @clk_io: The clock for the internal bus interface.
 45  * @clk_bus: The clocks that are available for the SD/MMC bus clock.
 46  */
 47 struct sdhci_s3c {
 48         struct sdhci_host       *host;
 49         struct platform_device  *pdev;
 50         struct resource         *ioarea;
 51         struct s3c_sdhci_platdata *pdata;
 52         int                     cur_clk;
 53         int                     ext_cd_irq;
 54         int                     ext_cd_gpio;
 55 
 56         struct clk              *clk_io;
 57         struct clk              *clk_bus[MAX_BUS_CLK];
 58         unsigned long           clk_rates[MAX_BUS_CLK];
 59 
 60         bool                    no_divider;
 61 };
 62 
 63 /**
 64  * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
 65  * @sdhci_quirks: sdhci host specific quirks.
 66  *
 67  * Specifies platform specific configuration of sdhci controller.
 68  * Note: A structure for driver specific platform data is used for future
 69  * expansion of its usage.
 70  */
 71 struct sdhci_s3c_drv_data {
 72         unsigned int    sdhci_quirks;
 73         bool            no_divider;
 74 };
 75 
 76 static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
 77 {
 78         return sdhci_priv(host);
 79 }
 80 
 81 /**
 82  * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
 83  * @host: The SDHCI host instance.
 84  *
 85  * Callback to return the maximum clock rate acheivable by the controller.
 86 */
 87 static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
 88 {
 89         struct sdhci_s3c *ourhost = to_s3c(host);
 90         unsigned long rate, max = 0;
 91         int src;
 92 
 93         for (src = 0; src < MAX_BUS_CLK; src++) {
 94                 rate = ourhost->clk_rates[src];
 95                 if (rate > max)
 96                         max = rate;
 97         }
 98 
 99         return max;
100 }
101 
102 /**
103  * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
104  * @ourhost: Our SDHCI instance.
105  * @src: The source clock index.
106  * @wanted: The clock frequency wanted.
107  */
108 static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
109                                              unsigned int src,
110                                              unsigned int wanted)
111 {
112         unsigned long rate;
113         struct clk *clksrc = ourhost->clk_bus[src];
114         int shift;
115 
116         if (IS_ERR(clksrc))
117                 return UINT_MAX;
118 
119         /*
120          * If controller uses a non-standard clock division, find the best clock
121          * speed possible with selected clock source and skip the division.
122          */
123         if (ourhost->no_divider) {
124                 spin_unlock_irq(&ourhost->host->lock);
125                 rate = clk_round_rate(clksrc, wanted);
126                 spin_lock_irq(&ourhost->host->lock);
127                 return wanted - rate;
128         }
129 
130         rate = ourhost->clk_rates[src];
131 
132         for (shift = 0; shift <= 8; ++shift) {
133                 if ((rate >> shift) <= wanted)
134                         break;
135         }
136 
137         if (shift > 8) {
138                 dev_dbg(&ourhost->pdev->dev,
139                         "clk %d: rate %ld, min rate %lu > wanted %u\n",
140                         src, rate, rate / 256, wanted);
141                 return UINT_MAX;
142         }
143 
144         dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
145                 src, rate, wanted, rate >> shift);
146 
147         return wanted - (rate >> shift);
148 }
149 
150 /**
151  * sdhci_s3c_set_clock - callback on clock change
152  * @host: The SDHCI host being changed
153  * @clock: The clock rate being requested.
154  *
155  * When the card's clock is going to be changed, look at the new frequency
156  * and find the best clock source to go with it.
157 */
158 static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
159 {
160         struct sdhci_s3c *ourhost = to_s3c(host);
161         unsigned int best = UINT_MAX;
162         unsigned int delta;
163         int best_src = 0;
164         int src;
165         u32 ctrl;
166 
167         host->mmc->actual_clock = 0;
168 
169         /* don't bother if the clock is going off. */
170         if (clock == 0) {
171                 sdhci_set_clock(host, clock);
172                 return;
173         }
174 
175         for (src = 0; src < MAX_BUS_CLK; src++) {
176                 delta = sdhci_s3c_consider_clock(ourhost, src, clock);
177                 if (delta < best) {
178                         best = delta;
179                         best_src = src;
180                 }
181         }
182 
183         dev_dbg(&ourhost->pdev->dev,
184                 "selected source %d, clock %d, delta %d\n",
185                  best_src, clock, best);
186 
187         /* select the new clock source */
188         if (ourhost->cur_clk != best_src) {
189                 struct clk *clk = ourhost->clk_bus[best_src];
190 
191                 clk_prepare_enable(clk);
192                 if (ourhost->cur_clk >= 0)
193                         clk_disable_unprepare(
194                                         ourhost->clk_bus[ourhost->cur_clk]);
195 
196                 ourhost->cur_clk = best_src;
197                 host->max_clk = ourhost->clk_rates[best_src];
198         }
199 
200         /* turn clock off to card before changing clock source */
201         writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
202 
203         ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
204         ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
205         ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
206         writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
207 
208         /* reprogram default hardware configuration */
209         writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
210                 host->ioaddr + S3C64XX_SDHCI_CONTROL4);
211 
212         ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
213         ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
214                   S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
215                   S3C_SDHCI_CTRL2_ENFBCLKRX |
216                   S3C_SDHCI_CTRL2_DFCNT_NONE |
217                   S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
218         writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
219 
220         /* reconfigure the controller for new clock rate */
221         ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
222         if (clock < 25 * 1000000)
223                 ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
224         writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
225 
226         sdhci_set_clock(host, clock);
227 }
228 
229 /**
230  * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
231  * @host: The SDHCI host being queried
232  *
233  * To init mmc host properly a minimal clock value is needed. For high system
234  * bus clock's values the standard formula gives values out of allowed range.
235  * The clock still can be set to lower values, if clock source other then
236  * system bus is selected.
237 */
238 static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
239 {
240         struct sdhci_s3c *ourhost = to_s3c(host);
241         unsigned long rate, min = ULONG_MAX;
242         int src;
243 
244         for (src = 0; src < MAX_BUS_CLK; src++) {
245                 rate = ourhost->clk_rates[src] / 256;
246                 if (!rate)
247                         continue;
248                 if (rate < min)
249                         min = rate;
250         }
251 
252         return min;
253 }
254 
255 /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
256 static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
257 {
258         struct sdhci_s3c *ourhost = to_s3c(host);
259         unsigned long rate, max = 0;
260         int src;
261 
262         for (src = 0; src < MAX_BUS_CLK; src++) {
263                 struct clk *clk;
264 
265                 clk = ourhost->clk_bus[src];
266                 if (IS_ERR(clk))
267                         continue;
268 
269                 rate = clk_round_rate(clk, ULONG_MAX);
270                 if (rate > max)
271                         max = rate;
272         }
273 
274         return max;
275 }
276 
277 /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
278 static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
279 {
280         struct sdhci_s3c *ourhost = to_s3c(host);
281         unsigned long rate, min = ULONG_MAX;
282         int src;
283 
284         for (src = 0; src < MAX_BUS_CLK; src++) {
285                 struct clk *clk;
286 
287                 clk = ourhost->clk_bus[src];
288                 if (IS_ERR(clk))
289                         continue;
290 
291                 rate = clk_round_rate(clk, 0);
292                 if (rate < min)
293                         min = rate;
294         }
295 
296         return min;
297 }
298 
299 /* sdhci_cmu_set_clock - callback on clock change.*/
300 static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
301 {
302         struct sdhci_s3c *ourhost = to_s3c(host);
303         struct device *dev = &ourhost->pdev->dev;
304         unsigned long timeout;
305         u16 clk = 0;
306         int ret;
307 
308         host->mmc->actual_clock = 0;
309 
310         /* If the clock is going off, set to 0 at clock control register */
311         if (clock == 0) {
312                 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
313                 return;
314         }
315 
316         sdhci_s3c_set_clock(host, clock);
317 
318         /* Reset SD Clock Enable */
319         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
320         clk &= ~SDHCI_CLOCK_CARD_EN;
321         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
322 
323         spin_unlock_irq(&host->lock);
324         ret = clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
325         spin_lock_irq(&host->lock);
326         if (ret != 0) {
327                 dev_err(dev, "%s: failed to set clock rate %uHz\n",
328                         mmc_hostname(host->mmc), clock);
329                 return;
330         }
331 
332         clk = SDHCI_CLOCK_INT_EN;
333         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
334 
335         /* Wait max 20 ms */
336         timeout = 20;
337         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
338                 & SDHCI_CLOCK_INT_STABLE)) {
339                 if (timeout == 0) {
340                         dev_err(dev, "%s: Internal clock never stabilised.\n",
341                                 mmc_hostname(host->mmc));
342                         return;
343                 }
344                 timeout--;
345                 mdelay(1);
346         }
347 
348         clk |= SDHCI_CLOCK_CARD_EN;
349         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
350 }
351 
352 /**
353  * sdhci_s3c_set_bus_width - support 8bit buswidth
354  * @host: The SDHCI host being queried
355  * @width: MMC_BUS_WIDTH_ macro for the bus width being requested
356  *
357  * We have 8-bit width support but is not a v3 controller.
358  * So we add platform_bus_width() and support 8bit width.
359  */
360 static void sdhci_s3c_set_bus_width(struct sdhci_host *host, int width)
361 {
362         u8 ctrl;
363 
364         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
365 
366         switch (width) {
367         case MMC_BUS_WIDTH_8:
368                 ctrl |= SDHCI_CTRL_8BITBUS;
369                 ctrl &= ~SDHCI_CTRL_4BITBUS;
370                 break;
371         case MMC_BUS_WIDTH_4:
372                 ctrl |= SDHCI_CTRL_4BITBUS;
373                 ctrl &= ~SDHCI_CTRL_8BITBUS;
374                 break;
375         default:
376                 ctrl &= ~SDHCI_CTRL_4BITBUS;
377                 ctrl &= ~SDHCI_CTRL_8BITBUS;
378                 break;
379         }
380 
381         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
382 }
383 
384 static struct sdhci_ops sdhci_s3c_ops = {
385         .get_max_clock          = sdhci_s3c_get_max_clk,
386         .set_clock              = sdhci_s3c_set_clock,
387         .get_min_clock          = sdhci_s3c_get_min_clock,
388         .set_bus_width          = sdhci_s3c_set_bus_width,
389         .reset                  = sdhci_reset,
390         .set_uhs_signaling      = sdhci_set_uhs_signaling,
391 };
392 
393 #ifdef CONFIG_OF
394 static int sdhci_s3c_parse_dt(struct device *dev,
395                 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
396 {
397         struct device_node *node = dev->of_node;
398         u32 max_width;
399 
400         /* if the bus-width property is not specified, assume width as 1 */
401         if (of_property_read_u32(node, "bus-width", &max_width))
402                 max_width = 1;
403         pdata->max_width = max_width;
404 
405         /* get the card detection method */
406         if (of_get_property(node, "broken-cd", NULL)) {
407                 pdata->cd_type = S3C_SDHCI_CD_NONE;
408                 return 0;
409         }
410 
411         if (of_get_property(node, "non-removable", NULL)) {
412                 pdata->cd_type = S3C_SDHCI_CD_PERMANENT;
413                 return 0;
414         }
415 
416         if (of_get_named_gpio(node, "cd-gpios", 0))
417                 return 0;
418 
419         /* assuming internal card detect that will be configured by pinctrl */
420         pdata->cd_type = S3C_SDHCI_CD_INTERNAL;
421         return 0;
422 }
423 #else
424 static int sdhci_s3c_parse_dt(struct device *dev,
425                 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
426 {
427         return -EINVAL;
428 }
429 #endif
430 
431 static const struct of_device_id sdhci_s3c_dt_match[];
432 
433 static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
434                         struct platform_device *pdev)
435 {
436 #ifdef CONFIG_OF
437         if (pdev->dev.of_node) {
438                 const struct of_device_id *match;
439                 match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node);
440                 return (struct sdhci_s3c_drv_data *)match->data;
441         }
442 #endif
443         return (struct sdhci_s3c_drv_data *)
444                         platform_get_device_id(pdev)->driver_data;
445 }
446 
447 static int sdhci_s3c_probe(struct platform_device *pdev)
448 {
449         struct s3c_sdhci_platdata *pdata;
450         struct sdhci_s3c_drv_data *drv_data;
451         struct device *dev = &pdev->dev;
452         struct sdhci_host *host;
453         struct sdhci_s3c *sc;
454         struct resource *res;
455         int ret, irq, ptr, clks;
456 
457         if (!pdev->dev.platform_data && !pdev->dev.of_node) {
458                 dev_err(dev, "no device data specified\n");
459                 return -ENOENT;
460         }
461 
462         irq = platform_get_irq(pdev, 0);
463         if (irq < 0) {
464                 dev_err(dev, "no irq specified\n");
465                 return irq;
466         }
467 
468         host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
469         if (IS_ERR(host)) {
470                 dev_err(dev, "sdhci_alloc_host() failed\n");
471                 return PTR_ERR(host);
472         }
473         sc = sdhci_priv(host);
474 
475         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
476         if (!pdata) {
477                 ret = -ENOMEM;
478                 goto err_pdata_io_clk;
479         }
480 
481         if (pdev->dev.of_node) {
482                 ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata);
483                 if (ret)
484                         goto err_pdata_io_clk;
485         } else {
486                 memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
487                 sc->ext_cd_gpio = -1; /* invalid gpio number */
488         }
489 
490         drv_data = sdhci_s3c_get_driver_data(pdev);
491 
492         sc->host = host;
493         sc->pdev = pdev;
494         sc->pdata = pdata;
495         sc->cur_clk = -1;
496 
497         platform_set_drvdata(pdev, host);
498 
499         sc->clk_io = devm_clk_get(dev, "hsmmc");
500         if (IS_ERR(sc->clk_io)) {
501                 dev_err(dev, "failed to get io clock\n");
502                 ret = PTR_ERR(sc->clk_io);
503                 goto err_pdata_io_clk;
504         }
505 
506         /* enable the local io clock and keep it running for the moment. */
507         clk_prepare_enable(sc->clk_io);
508 
509         for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
510                 char name[14];
511 
512                 snprintf(name, 14, "mmc_busclk.%d", ptr);
513                 sc->clk_bus[ptr] = devm_clk_get(dev, name);
514                 if (IS_ERR(sc->clk_bus[ptr]))
515                         continue;
516 
517                 clks++;
518                 sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]);
519 
520                 dev_info(dev, "clock source %d: %s (%ld Hz)\n",
521                                 ptr, name, sc->clk_rates[ptr]);
522         }
523 
524         if (clks == 0) {
525                 dev_err(dev, "failed to find any bus clocks\n");
526                 ret = -ENOENT;
527                 goto err_no_busclks;
528         }
529 
530         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
531         host->ioaddr = devm_ioremap_resource(&pdev->dev, res);
532         if (IS_ERR(host->ioaddr)) {
533                 ret = PTR_ERR(host->ioaddr);
534                 goto err_req_regs;
535         }
536 
537         /* Ensure we have minimal gpio selected CMD/CLK/Detect */
538         if (pdata->cfg_gpio)
539                 pdata->cfg_gpio(pdev, pdata->max_width);
540 
541         host->hw_name = "samsung-hsmmc";
542         host->ops = &sdhci_s3c_ops;
543         host->quirks = 0;
544         host->quirks2 = 0;
545         host->irq = irq;
546 
547         /* Setup quirks for the controller */
548         host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
549         host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
550         if (drv_data) {
551                 host->quirks |= drv_data->sdhci_quirks;
552                 sc->no_divider = drv_data->no_divider;
553         }
554 
555 #ifndef CONFIG_MMC_SDHCI_S3C_DMA
556 
557         /* we currently see overruns on errors, so disable the SDMA
558          * support as well. */
559         host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
560 
561 #endif /* CONFIG_MMC_SDHCI_S3C_DMA */
562 
563         /* It seems we do not get an DATA transfer complete on non-busy
564          * transfers, not sure if this is a problem with this specific
565          * SDHCI block, or a missing configuration that needs to be set. */
566         host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
567 
568         /* This host supports the Auto CMD12 */
569         host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
570 
571         /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
572         host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
573 
574         if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
575             pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
576                 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
577 
578         if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
579                 host->mmc->caps = MMC_CAP_NONREMOVABLE;
580 
581         switch (pdata->max_width) {
582         case 8:
583                 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
584         case 4:
585                 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
586                 break;
587         }
588 
589         if (pdata->pm_caps)
590                 host->mmc->pm_caps |= pdata->pm_caps;
591 
592         host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
593                          SDHCI_QUIRK_32BIT_DMA_SIZE);
594 
595         /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
596         host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
597 
598         /*
599          * If controller does not have internal clock divider,
600          * we can use overriding functions instead of default.
601          */
602         if (sc->no_divider) {
603                 sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
604                 sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
605                 sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
606         }
607 
608         /* It supports additional host capabilities if needed */
609         if (pdata->host_caps)
610                 host->mmc->caps |= pdata->host_caps;
611 
612         if (pdata->host_caps2)
613                 host->mmc->caps2 |= pdata->host_caps2;
614 
615         pm_runtime_enable(&pdev->dev);
616         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
617         pm_runtime_use_autosuspend(&pdev->dev);
618         pm_suspend_ignore_children(&pdev->dev, 1);
619 
620         ret = mmc_of_parse(host->mmc);
621         if (ret)
622                 goto err_req_regs;
623 
624         ret = sdhci_add_host(host);
625         if (ret) {
626                 dev_err(dev, "sdhci_add_host() failed\n");
627                 goto err_req_regs;
628         }
629 
630 #ifdef CONFIG_PM
631         if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
632                 clk_disable_unprepare(sc->clk_io);
633 #endif
634         return 0;
635 
636  err_req_regs:
637         pm_runtime_disable(&pdev->dev);
638 
639  err_no_busclks:
640         clk_disable_unprepare(sc->clk_io);
641 
642  err_pdata_io_clk:
643         sdhci_free_host(host);
644 
645         return ret;
646 }
647 
648 static int sdhci_s3c_remove(struct platform_device *pdev)
649 {
650         struct sdhci_host *host =  platform_get_drvdata(pdev);
651         struct sdhci_s3c *sc = sdhci_priv(host);
652 
653         if (sc->ext_cd_irq)
654                 free_irq(sc->ext_cd_irq, sc);
655 
656 #ifdef CONFIG_PM
657         if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
658                 clk_prepare_enable(sc->clk_io);
659 #endif
660         sdhci_remove_host(host, 1);
661 
662         pm_runtime_dont_use_autosuspend(&pdev->dev);
663         pm_runtime_disable(&pdev->dev);
664 
665         clk_disable_unprepare(sc->clk_io);
666 
667         sdhci_free_host(host);
668 
669         return 0;
670 }
671 
672 #ifdef CONFIG_PM_SLEEP
673 static int sdhci_s3c_suspend(struct device *dev)
674 {
675         struct sdhci_host *host = dev_get_drvdata(dev);
676 
677         return sdhci_suspend_host(host);
678 }
679 
680 static int sdhci_s3c_resume(struct device *dev)
681 {
682         struct sdhci_host *host = dev_get_drvdata(dev);
683 
684         return sdhci_resume_host(host);
685 }
686 #endif
687 
688 #ifdef CONFIG_PM
689 static int sdhci_s3c_runtime_suspend(struct device *dev)
690 {
691         struct sdhci_host *host = dev_get_drvdata(dev);
692         struct sdhci_s3c *ourhost = to_s3c(host);
693         struct clk *busclk = ourhost->clk_io;
694         int ret;
695 
696         ret = sdhci_runtime_suspend_host(host);
697 
698         if (ourhost->cur_clk >= 0)
699                 clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]);
700         clk_disable_unprepare(busclk);
701         return ret;
702 }
703 
704 static int sdhci_s3c_runtime_resume(struct device *dev)
705 {
706         struct sdhci_host *host = dev_get_drvdata(dev);
707         struct sdhci_s3c *ourhost = to_s3c(host);
708         struct clk *busclk = ourhost->clk_io;
709         int ret;
710 
711         clk_prepare_enable(busclk);
712         if (ourhost->cur_clk >= 0)
713                 clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]);
714         ret = sdhci_runtime_resume_host(host);
715         return ret;
716 }
717 #endif
718 
719 static const struct dev_pm_ops sdhci_s3c_pmops = {
720         SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
721         SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
722                            NULL)
723 };
724 
725 #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
726 static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
727         .no_divider = true,
728 };
729 #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data)
730 #else
731 #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)NULL)
732 #endif
733 
734 static const struct platform_device_id sdhci_s3c_driver_ids[] = {
735         {
736                 .name           = "s3c-sdhci",
737                 .driver_data    = (kernel_ulong_t)NULL,
738         }, {
739                 .name           = "exynos4-sdhci",
740                 .driver_data    = EXYNOS4_SDHCI_DRV_DATA,
741         },
742         { }
743 };
744 MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
745 
746 #ifdef CONFIG_OF
747 static const struct of_device_id sdhci_s3c_dt_match[] = {
748         { .compatible = "samsung,s3c6410-sdhci", },
749         { .compatible = "samsung,exynos4210-sdhci",
750                 .data = (void *)EXYNOS4_SDHCI_DRV_DATA },
751         {},
752 };
753 MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match);
754 #endif
755 
756 static struct platform_driver sdhci_s3c_driver = {
757         .probe          = sdhci_s3c_probe,
758         .remove         = sdhci_s3c_remove,
759         .id_table       = sdhci_s3c_driver_ids,
760         .driver         = {
761                 .name   = "s3c-sdhci",
762                 .of_match_table = of_match_ptr(sdhci_s3c_dt_match),
763                 .pm     = &sdhci_s3c_pmops,
764         },
765 };
766 
767 module_platform_driver(sdhci_s3c_driver);
768 
769 MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
770 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
771 MODULE_LICENSE("GPL v2");
772 MODULE_ALIAS("platform:s3c-sdhci");
773 

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