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Linux/drivers/mmc/host/sdhci-pxav3.c

  1 /*
  2  * Copyright (C) 2010 Marvell International Ltd.
  3  *              Zhangfei Gao <zhangfei.gao@marvell.com>
  4  *              Kevin Wang <dwang4@marvell.com>
  5  *              Mingwei Wang <mwwang@marvell.com>
  6  *              Philip Rakity <prakity@marvell.com>
  7  *              Mark Brown <markb@marvell.com>
  8  *
  9  * This software is licensed under the terms of the GNU General Public
 10  * License version 2, as published by the Free Software Foundation, and
 11  * may be copied, distributed, and modified under those terms.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  * GNU General Public License for more details.
 17  *
 18  */
 19 #include <linux/err.h>
 20 #include <linux/init.h>
 21 #include <linux/platform_device.h>
 22 #include <linux/clk.h>
 23 #include <linux/io.h>
 24 #include <linux/gpio.h>
 25 #include <linux/mmc/card.h>
 26 #include <linux/mmc/host.h>
 27 #include <linux/mmc/slot-gpio.h>
 28 #include <linux/platform_data/pxa_sdhci.h>
 29 #include <linux/slab.h>
 30 #include <linux/delay.h>
 31 #include <linux/module.h>
 32 #include <linux/of.h>
 33 #include <linux/of_device.h>
 34 #include <linux/of_gpio.h>
 35 #include <linux/pm.h>
 36 #include <linux/pm_runtime.h>
 37 #include <linux/mbus.h>
 38 
 39 #include "sdhci.h"
 40 #include "sdhci-pltfm.h"
 41 
 42 #define PXAV3_RPM_DELAY_MS     50
 43 
 44 #define SD_CLOCK_BURST_SIZE_SETUP               0x10A
 45 #define SDCLK_SEL       0x100
 46 #define SDCLK_DELAY_SHIFT       9
 47 #define SDCLK_DELAY_MASK        0x1f
 48 
 49 #define SD_CFG_FIFO_PARAM       0x100
 50 #define SDCFG_GEN_PAD_CLK_ON    (1<<6)
 51 #define SDCFG_GEN_PAD_CLK_CNT_MASK      0xFF
 52 #define SDCFG_GEN_PAD_CLK_CNT_SHIFT     24
 53 
 54 #define SD_SPI_MODE          0x108
 55 #define SD_CE_ATA_1          0x10C
 56 
 57 #define SD_CE_ATA_2          0x10E
 58 #define SDCE_MISC_INT           (1<<2)
 59 #define SDCE_MISC_INT_EN        (1<<1)
 60 
 61 struct sdhci_pxa {
 62         struct clk *clk_core;
 63         struct clk *clk_io;
 64         u8      power_mode;
 65 };
 66 
 67 /*
 68  * These registers are relative to the second register region, for the
 69  * MBus bridge.
 70  */
 71 #define SDHCI_WINDOW_CTRL(i)    (0x80 + ((i) << 3))
 72 #define SDHCI_WINDOW_BASE(i)    (0x84 + ((i) << 3))
 73 #define SDHCI_MAX_WIN_NUM       8
 74 
 75 static int mv_conf_mbus_windows(struct platform_device *pdev,
 76                                 const struct mbus_dram_target_info *dram)
 77 {
 78         int i;
 79         void __iomem *regs;
 80         struct resource *res;
 81 
 82         if (!dram) {
 83                 dev_err(&pdev->dev, "no mbus dram info\n");
 84                 return -EINVAL;
 85         }
 86 
 87         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 88         if (!res) {
 89                 dev_err(&pdev->dev, "cannot get mbus registers\n");
 90                 return -EINVAL;
 91         }
 92 
 93         regs = ioremap(res->start, resource_size(res));
 94         if (!regs) {
 95                 dev_err(&pdev->dev, "cannot map mbus registers\n");
 96                 return -ENOMEM;
 97         }
 98 
 99         for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) {
100                 writel(0, regs + SDHCI_WINDOW_CTRL(i));
101                 writel(0, regs + SDHCI_WINDOW_BASE(i));
102         }
103 
104         for (i = 0; i < dram->num_cs; i++) {
105                 const struct mbus_dram_window *cs = dram->cs + i;
106 
107                 /* Write size, attributes and target id to control register */
108                 writel(((cs->size - 1) & 0xffff0000) |
109                         (cs->mbus_attr << 8) |
110                         (dram->mbus_dram_target_id << 4) | 1,
111                         regs + SDHCI_WINDOW_CTRL(i));
112                 /* Write base address to base register */
113                 writel(cs->base, regs + SDHCI_WINDOW_BASE(i));
114         }
115 
116         iounmap(regs);
117 
118         return 0;
119 }
120 
121 static void pxav3_reset(struct sdhci_host *host, u8 mask)
122 {
123         struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
124         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
125 
126         sdhci_reset(host, mask);
127 
128         if (mask == SDHCI_RESET_ALL) {
129                 /*
130                  * tune timing of read data/command when crc error happen
131                  * no performance impact
132                  */
133                 if (pdata && 0 != pdata->clk_delay_cycles) {
134                         u16 tmp;
135 
136                         tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
137                         tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
138                                 << SDCLK_DELAY_SHIFT;
139                         tmp |= SDCLK_SEL;
140                         writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
141                 }
142         }
143 }
144 
145 #define MAX_WAIT_COUNT 5
146 static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
147 {
148         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
149         struct sdhci_pxa *pxa = pltfm_host->priv;
150         u16 tmp;
151         int count;
152 
153         if (pxa->power_mode == MMC_POWER_UP
154                         && power_mode == MMC_POWER_ON) {
155 
156                 dev_dbg(mmc_dev(host->mmc),
157                                 "%s: slot->power_mode = %d,"
158                                 "ios->power_mode = %d\n",
159                                 __func__,
160                                 pxa->power_mode,
161                                 power_mode);
162 
163                 /* set we want notice of when 74 clocks are sent */
164                 tmp = readw(host->ioaddr + SD_CE_ATA_2);
165                 tmp |= SDCE_MISC_INT_EN;
166                 writew(tmp, host->ioaddr + SD_CE_ATA_2);
167 
168                 /* start sending the 74 clocks */
169                 tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
170                 tmp |= SDCFG_GEN_PAD_CLK_ON;
171                 writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
172 
173                 /* slowest speed is about 100KHz or 10usec per clock */
174                 udelay(740);
175                 count = 0;
176 
177                 while (count++ < MAX_WAIT_COUNT) {
178                         if ((readw(host->ioaddr + SD_CE_ATA_2)
179                                                 & SDCE_MISC_INT) == 0)
180                                 break;
181                         udelay(10);
182                 }
183 
184                 if (count == MAX_WAIT_COUNT)
185                         dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
186 
187                 /* clear the interrupt bit if posted */
188                 tmp = readw(host->ioaddr + SD_CE_ATA_2);
189                 tmp |= SDCE_MISC_INT;
190                 writew(tmp, host->ioaddr + SD_CE_ATA_2);
191         }
192         pxa->power_mode = power_mode;
193 }
194 
195 static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
196 {
197         u16 ctrl_2;
198 
199         /*
200          * Set V18_EN -- UHS modes do not work without this.
201          * does not change signaling voltage
202          */
203         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
204 
205         /* Select Bus Speed Mode for host */
206         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
207         switch (uhs) {
208         case MMC_TIMING_UHS_SDR12:
209                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
210                 break;
211         case MMC_TIMING_UHS_SDR25:
212                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
213                 break;
214         case MMC_TIMING_UHS_SDR50:
215                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
216                 break;
217         case MMC_TIMING_UHS_SDR104:
218                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
219                 break;
220         case MMC_TIMING_MMC_DDR52:
221         case MMC_TIMING_UHS_DDR50:
222                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
223                 break;
224         }
225 
226         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
227         dev_dbg(mmc_dev(host->mmc),
228                 "%s uhs = %d, ctrl_2 = %04X\n",
229                 __func__, uhs, ctrl_2);
230 }
231 
232 static const struct sdhci_ops pxav3_sdhci_ops = {
233         .set_clock = sdhci_set_clock,
234         .platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
235         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
236         .set_bus_width = sdhci_set_bus_width,
237         .reset = pxav3_reset,
238         .set_uhs_signaling = pxav3_set_uhs_signaling,
239 };
240 
241 static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
242         .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
243                 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
244                 | SDHCI_QUIRK_32BIT_ADMA_SIZE
245                 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
246         .ops = &pxav3_sdhci_ops,
247 };
248 
249 #ifdef CONFIG_OF
250 static const struct of_device_id sdhci_pxav3_of_match[] = {
251         {
252                 .compatible = "mrvl,pxav3-mmc",
253         },
254         {
255                 .compatible = "marvell,armada-380-sdhci",
256         },
257         {},
258 };
259 MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);
260 
261 static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
262 {
263         struct sdhci_pxa_platdata *pdata;
264         struct device_node *np = dev->of_node;
265         u32 clk_delay_cycles;
266 
267         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
268         if (!pdata)
269                 return NULL;
270 
271         of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
272         if (clk_delay_cycles > 0)
273                 pdata->clk_delay_cycles = clk_delay_cycles;
274 
275         return pdata;
276 }
277 #else
278 static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
279 {
280         return NULL;
281 }
282 #endif
283 
284 static int sdhci_pxav3_probe(struct platform_device *pdev)
285 {
286         struct sdhci_pltfm_host *pltfm_host;
287         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
288         struct device *dev = &pdev->dev;
289         struct device_node *np = pdev->dev.of_node;
290         struct sdhci_host *host = NULL;
291         struct sdhci_pxa *pxa = NULL;
292         const struct of_device_id *match;
293         int ret;
294 
295         pxa = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_pxa), GFP_KERNEL);
296         if (!pxa)
297                 return -ENOMEM;
298 
299         host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0);
300         if (IS_ERR(host))
301                 return PTR_ERR(host);
302 
303         pltfm_host = sdhci_priv(host);
304         pltfm_host->priv = pxa;
305 
306         pxa->clk_io = devm_clk_get(dev, "io");
307         if (IS_ERR(pxa->clk_io))
308                 pxa->clk_io = devm_clk_get(dev, NULL);
309         if (IS_ERR(pxa->clk_io)) {
310                 dev_err(dev, "failed to get io clock\n");
311                 ret = PTR_ERR(pxa->clk_io);
312                 goto err_clk_get;
313         }
314         pltfm_host->clk = pxa->clk_io;
315         clk_prepare_enable(pxa->clk_io);
316 
317         pxa->clk_core = devm_clk_get(dev, "core");
318         if (!IS_ERR(pxa->clk_core))
319                 clk_prepare_enable(pxa->clk_core);
320 
321         if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
322                 ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
323                 if (ret < 0)
324                         goto err_mbus_win;
325         }
326 
327         /* enable 1/8V DDR capable */
328         host->mmc->caps |= MMC_CAP_1_8V_DDR;
329 
330         match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
331         if (match) {
332                 ret = mmc_of_parse(host->mmc);
333                 if (ret)
334                         goto err_of_parse;
335                 sdhci_get_of_property(pdev);
336                 pdata = pxav3_get_mmc_pdata(dev);
337         } else if (pdata) {
338                 /* on-chip device */
339                 if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
340                         host->mmc->caps |= MMC_CAP_NONREMOVABLE;
341 
342                 /* If slot design supports 8 bit data, indicate this to MMC. */
343                 if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
344                         host->mmc->caps |= MMC_CAP_8_BIT_DATA;
345 
346                 if (pdata->quirks)
347                         host->quirks |= pdata->quirks;
348                 if (pdata->quirks2)
349                         host->quirks2 |= pdata->quirks2;
350                 if (pdata->host_caps)
351                         host->mmc->caps |= pdata->host_caps;
352                 if (pdata->host_caps2)
353                         host->mmc->caps2 |= pdata->host_caps2;
354                 if (pdata->pm_caps)
355                         host->mmc->pm_caps |= pdata->pm_caps;
356 
357                 if (gpio_is_valid(pdata->ext_cd_gpio)) {
358                         ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio,
359                                                   0);
360                         if (ret) {
361                                 dev_err(mmc_dev(host->mmc),
362                                         "failed to allocate card detect gpio\n");
363                                 goto err_cd_req;
364                         }
365                 }
366         }
367 
368         pm_runtime_enable(&pdev->dev);
369         pm_runtime_get_sync(&pdev->dev);
370         pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
371         pm_runtime_use_autosuspend(&pdev->dev);
372         pm_suspend_ignore_children(&pdev->dev, 1);
373 
374         ret = sdhci_add_host(host);
375         if (ret) {
376                 dev_err(&pdev->dev, "failed to add host\n");
377                 goto err_add_host;
378         }
379 
380         platform_set_drvdata(pdev, host);
381 
382         if (host->mmc->pm_caps & MMC_PM_KEEP_POWER) {
383                 device_init_wakeup(&pdev->dev, 1);
384                 host->mmc->pm_flags |= MMC_PM_WAKE_SDIO_IRQ;
385         } else {
386                 device_init_wakeup(&pdev->dev, 0);
387         }
388 
389         pm_runtime_put_autosuspend(&pdev->dev);
390 
391         return 0;
392 
393 err_add_host:
394         pm_runtime_put_sync(&pdev->dev);
395         pm_runtime_disable(&pdev->dev);
396 err_of_parse:
397 err_cd_req:
398 err_mbus_win:
399         clk_disable_unprepare(pxa->clk_io);
400         if (!IS_ERR(pxa->clk_core))
401                 clk_disable_unprepare(pxa->clk_core);
402 err_clk_get:
403         sdhci_pltfm_free(pdev);
404         return ret;
405 }
406 
407 static int sdhci_pxav3_remove(struct platform_device *pdev)
408 {
409         struct sdhci_host *host = platform_get_drvdata(pdev);
410         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
411         struct sdhci_pxa *pxa = pltfm_host->priv;
412 
413         pm_runtime_get_sync(&pdev->dev);
414         sdhci_remove_host(host, 1);
415         pm_runtime_disable(&pdev->dev);
416 
417         clk_disable_unprepare(pxa->clk_io);
418         if (!IS_ERR(pxa->clk_core))
419                 clk_disable_unprepare(pxa->clk_core);
420 
421         sdhci_pltfm_free(pdev);
422 
423         return 0;
424 }
425 
426 #ifdef CONFIG_PM_SLEEP
427 static int sdhci_pxav3_suspend(struct device *dev)
428 {
429         int ret;
430         struct sdhci_host *host = dev_get_drvdata(dev);
431 
432         pm_runtime_get_sync(dev);
433         ret = sdhci_suspend_host(host);
434         pm_runtime_mark_last_busy(dev);
435         pm_runtime_put_autosuspend(dev);
436 
437         return ret;
438 }
439 
440 static int sdhci_pxav3_resume(struct device *dev)
441 {
442         int ret;
443         struct sdhci_host *host = dev_get_drvdata(dev);
444 
445         pm_runtime_get_sync(dev);
446         ret = sdhci_resume_host(host);
447         pm_runtime_mark_last_busy(dev);
448         pm_runtime_put_autosuspend(dev);
449 
450         return ret;
451 }
452 #endif
453 
454 #ifdef CONFIG_PM
455 static int sdhci_pxav3_runtime_suspend(struct device *dev)
456 {
457         struct sdhci_host *host = dev_get_drvdata(dev);
458         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
459         struct sdhci_pxa *pxa = pltfm_host->priv;
460         unsigned long flags;
461 
462         spin_lock_irqsave(&host->lock, flags);
463         host->runtime_suspended = true;
464         spin_unlock_irqrestore(&host->lock, flags);
465 
466         clk_disable_unprepare(pxa->clk_io);
467         if (!IS_ERR(pxa->clk_core))
468                 clk_disable_unprepare(pxa->clk_core);
469 
470         return 0;
471 }
472 
473 static int sdhci_pxav3_runtime_resume(struct device *dev)
474 {
475         struct sdhci_host *host = dev_get_drvdata(dev);
476         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
477         struct sdhci_pxa *pxa = pltfm_host->priv;
478         unsigned long flags;
479 
480         clk_prepare_enable(pxa->clk_io);
481         if (!IS_ERR(pxa->clk_core))
482                 clk_prepare_enable(pxa->clk_core);
483 
484         spin_lock_irqsave(&host->lock, flags);
485         host->runtime_suspended = false;
486         spin_unlock_irqrestore(&host->lock, flags);
487 
488         return 0;
489 }
490 #endif
491 
492 #ifdef CONFIG_PM
493 static const struct dev_pm_ops sdhci_pxav3_pmops = {
494         SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
495         SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
496                 sdhci_pxav3_runtime_resume, NULL)
497 };
498 
499 #define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops)
500 
501 #else
502 #define SDHCI_PXAV3_PMOPS NULL
503 #endif
504 
505 static struct platform_driver sdhci_pxav3_driver = {
506         .driver         = {
507                 .name   = "sdhci-pxav3",
508 #ifdef CONFIG_OF
509                 .of_match_table = sdhci_pxav3_of_match,
510 #endif
511                 .pm     = SDHCI_PXAV3_PMOPS,
512         },
513         .probe          = sdhci_pxav3_probe,
514         .remove         = sdhci_pxav3_remove,
515 };
516 
517 module_platform_driver(sdhci_pxav3_driver);
518 
519 MODULE_DESCRIPTION("SDHCI driver for pxav3");
520 MODULE_AUTHOR("Marvell International Ltd.");
521 MODULE_LICENSE("GPL v2");
522 
523 

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