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Linux/drivers/mmc/host/sdhci-pxav3.c

  1 /*
  2  * Copyright (C) 2010 Marvell International Ltd.
  3  *              Zhangfei Gao <zhangfei.gao@marvell.com>
  4  *              Kevin Wang <dwang4@marvell.com>
  5  *              Mingwei Wang <mwwang@marvell.com>
  6  *              Philip Rakity <prakity@marvell.com>
  7  *              Mark Brown <markb@marvell.com>
  8  *
  9  * This software is licensed under the terms of the GNU General Public
 10  * License version 2, as published by the Free Software Foundation, and
 11  * may be copied, distributed, and modified under those terms.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  * GNU General Public License for more details.
 17  *
 18  */
 19 #include <linux/err.h>
 20 #include <linux/init.h>
 21 #include <linux/platform_device.h>
 22 #include <linux/clk.h>
 23 #include <linux/io.h>
 24 #include <linux/gpio.h>
 25 #include <linux/mmc/card.h>
 26 #include <linux/mmc/host.h>
 27 #include <linux/mmc/slot-gpio.h>
 28 #include <linux/platform_data/pxa_sdhci.h>
 29 #include <linux/slab.h>
 30 #include <linux/delay.h>
 31 #include <linux/module.h>
 32 #include <linux/of.h>
 33 #include <linux/of_device.h>
 34 #include <linux/of_gpio.h>
 35 #include <linux/pm.h>
 36 #include <linux/pm_runtime.h>
 37 #include <linux/mbus.h>
 38 
 39 #include "sdhci.h"
 40 #include "sdhci-pltfm.h"
 41 
 42 #define PXAV3_RPM_DELAY_MS     50
 43 
 44 #define SD_CLOCK_BURST_SIZE_SETUP               0x10A
 45 #define SDCLK_SEL       0x100
 46 #define SDCLK_DELAY_SHIFT       9
 47 #define SDCLK_DELAY_MASK        0x1f
 48 
 49 #define SD_CFG_FIFO_PARAM       0x100
 50 #define SDCFG_GEN_PAD_CLK_ON    (1<<6)
 51 #define SDCFG_GEN_PAD_CLK_CNT_MASK      0xFF
 52 #define SDCFG_GEN_PAD_CLK_CNT_SHIFT     24
 53 
 54 #define SD_SPI_MODE          0x108
 55 #define SD_CE_ATA_1          0x10C
 56 
 57 #define SD_CE_ATA_2          0x10E
 58 #define SDCE_MISC_INT           (1<<2)
 59 #define SDCE_MISC_INT_EN        (1<<1)
 60 
 61 /*
 62  * These registers are relative to the second register region, for the
 63  * MBus bridge.
 64  */
 65 #define SDHCI_WINDOW_CTRL(i)    (0x80 + ((i) << 3))
 66 #define SDHCI_WINDOW_BASE(i)    (0x84 + ((i) << 3))
 67 #define SDHCI_MAX_WIN_NUM       8
 68 
 69 static int mv_conf_mbus_windows(struct platform_device *pdev,
 70                                 const struct mbus_dram_target_info *dram)
 71 {
 72         int i;
 73         void __iomem *regs;
 74         struct resource *res;
 75 
 76         if (!dram) {
 77                 dev_err(&pdev->dev, "no mbus dram info\n");
 78                 return -EINVAL;
 79         }
 80 
 81         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 82         if (!res) {
 83                 dev_err(&pdev->dev, "cannot get mbus registers\n");
 84                 return -EINVAL;
 85         }
 86 
 87         regs = ioremap(res->start, resource_size(res));
 88         if (!regs) {
 89                 dev_err(&pdev->dev, "cannot map mbus registers\n");
 90                 return -ENOMEM;
 91         }
 92 
 93         for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) {
 94                 writel(0, regs + SDHCI_WINDOW_CTRL(i));
 95                 writel(0, regs + SDHCI_WINDOW_BASE(i));
 96         }
 97 
 98         for (i = 0; i < dram->num_cs; i++) {
 99                 const struct mbus_dram_window *cs = dram->cs + i;
100 
101                 /* Write size, attributes and target id to control register */
102                 writel(((cs->size - 1) & 0xffff0000) |
103                         (cs->mbus_attr << 8) |
104                         (dram->mbus_dram_target_id << 4) | 1,
105                         regs + SDHCI_WINDOW_CTRL(i));
106                 /* Write base address to base register */
107                 writel(cs->base, regs + SDHCI_WINDOW_BASE(i));
108         }
109 
110         iounmap(regs);
111 
112         return 0;
113 }
114 
115 static void pxav3_set_private_registers(struct sdhci_host *host, u8 mask)
116 {
117         struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
118         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
119 
120         if (mask == SDHCI_RESET_ALL) {
121                 /*
122                  * tune timing of read data/command when crc error happen
123                  * no performance impact
124                  */
125                 if (pdata && 0 != pdata->clk_delay_cycles) {
126                         u16 tmp;
127 
128                         tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
129                         tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
130                                 << SDCLK_DELAY_SHIFT;
131                         tmp |= SDCLK_SEL;
132                         writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
133                 }
134         }
135 }
136 
137 #define MAX_WAIT_COUNT 5
138 static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
139 {
140         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
141         struct sdhci_pxa *pxa = pltfm_host->priv;
142         u16 tmp;
143         int count;
144 
145         if (pxa->power_mode == MMC_POWER_UP
146                         && power_mode == MMC_POWER_ON) {
147 
148                 dev_dbg(mmc_dev(host->mmc),
149                                 "%s: slot->power_mode = %d,"
150                                 "ios->power_mode = %d\n",
151                                 __func__,
152                                 pxa->power_mode,
153                                 power_mode);
154 
155                 /* set we want notice of when 74 clocks are sent */
156                 tmp = readw(host->ioaddr + SD_CE_ATA_2);
157                 tmp |= SDCE_MISC_INT_EN;
158                 writew(tmp, host->ioaddr + SD_CE_ATA_2);
159 
160                 /* start sending the 74 clocks */
161                 tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
162                 tmp |= SDCFG_GEN_PAD_CLK_ON;
163                 writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
164 
165                 /* slowest speed is about 100KHz or 10usec per clock */
166                 udelay(740);
167                 count = 0;
168 
169                 while (count++ < MAX_WAIT_COUNT) {
170                         if ((readw(host->ioaddr + SD_CE_ATA_2)
171                                                 & SDCE_MISC_INT) == 0)
172                                 break;
173                         udelay(10);
174                 }
175 
176                 if (count == MAX_WAIT_COUNT)
177                         dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
178 
179                 /* clear the interrupt bit if posted */
180                 tmp = readw(host->ioaddr + SD_CE_ATA_2);
181                 tmp |= SDCE_MISC_INT;
182                 writew(tmp, host->ioaddr + SD_CE_ATA_2);
183         }
184         pxa->power_mode = power_mode;
185 }
186 
187 static int pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
188 {
189         u16 ctrl_2;
190 
191         /*
192          * Set V18_EN -- UHS modes do not work without this.
193          * does not change signaling voltage
194          */
195         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
196 
197         /* Select Bus Speed Mode for host */
198         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
199         switch (uhs) {
200         case MMC_TIMING_UHS_SDR12:
201                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
202                 break;
203         case MMC_TIMING_UHS_SDR25:
204                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
205                 break;
206         case MMC_TIMING_UHS_SDR50:
207                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
208                 break;
209         case MMC_TIMING_UHS_SDR104:
210                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
211                 break;
212         case MMC_TIMING_UHS_DDR50:
213                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
214                 break;
215         }
216 
217         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
218         dev_dbg(mmc_dev(host->mmc),
219                 "%s uhs = %d, ctrl_2 = %04X\n",
220                 __func__, uhs, ctrl_2);
221 
222         return 0;
223 }
224 
225 static const struct sdhci_ops pxav3_sdhci_ops = {
226         .platform_reset_exit = pxav3_set_private_registers,
227         .set_uhs_signaling = pxav3_set_uhs_signaling,
228         .platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
229         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
230 };
231 
232 static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
233         .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
234                 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
235                 | SDHCI_QUIRK_32BIT_ADMA_SIZE
236                 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
237         .ops = &pxav3_sdhci_ops,
238 };
239 
240 #ifdef CONFIG_OF
241 static const struct of_device_id sdhci_pxav3_of_match[] = {
242         {
243                 .compatible = "mrvl,pxav3-mmc",
244         },
245         {
246                 .compatible = "marvell,armada-380-sdhci",
247         },
248         {},
249 };
250 MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);
251 
252 static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
253 {
254         struct sdhci_pxa_platdata *pdata;
255         struct device_node *np = dev->of_node;
256         u32 clk_delay_cycles;
257 
258         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
259         if (!pdata)
260                 return NULL;
261 
262         of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
263         if (clk_delay_cycles > 0)
264                 pdata->clk_delay_cycles = clk_delay_cycles;
265 
266         return pdata;
267 }
268 #else
269 static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
270 {
271         return NULL;
272 }
273 #endif
274 
275 static int sdhci_pxav3_probe(struct platform_device *pdev)
276 {
277         struct sdhci_pltfm_host *pltfm_host;
278         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
279         struct device *dev = &pdev->dev;
280         struct device_node *np = pdev->dev.of_node;
281         struct sdhci_host *host = NULL;
282         struct sdhci_pxa *pxa = NULL;
283         const struct of_device_id *match;
284 
285         int ret;
286         struct clk *clk;
287 
288         pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL);
289         if (!pxa)
290                 return -ENOMEM;
291 
292         host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0);
293         if (IS_ERR(host)) {
294                 kfree(pxa);
295                 return PTR_ERR(host);
296         }
297 
298         if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
299                 ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
300                 if (ret < 0)
301                         goto err_mbus_win;
302         }
303 
304 
305         pltfm_host = sdhci_priv(host);
306         pltfm_host->priv = pxa;
307 
308         clk = clk_get(dev, NULL);
309         if (IS_ERR(clk)) {
310                 dev_err(dev, "failed to get io clock\n");
311                 ret = PTR_ERR(clk);
312                 goto err_clk_get;
313         }
314         pltfm_host->clk = clk;
315         clk_prepare_enable(clk);
316 
317         /* enable 1/8V DDR capable */
318         host->mmc->caps |= MMC_CAP_1_8V_DDR;
319 
320         match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
321         if (match) {
322                 ret = mmc_of_parse(host->mmc);
323                 if (ret)
324                         goto err_of_parse;
325                 sdhci_get_of_property(pdev);
326                 pdata = pxav3_get_mmc_pdata(dev);
327         } else if (pdata) {
328                 /* on-chip device */
329                 if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
330                         host->mmc->caps |= MMC_CAP_NONREMOVABLE;
331 
332                 /* If slot design supports 8 bit data, indicate this to MMC. */
333                 if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
334                         host->mmc->caps |= MMC_CAP_8_BIT_DATA;
335 
336                 if (pdata->quirks)
337                         host->quirks |= pdata->quirks;
338                 if (pdata->quirks2)
339                         host->quirks2 |= pdata->quirks2;
340                 if (pdata->host_caps)
341                         host->mmc->caps |= pdata->host_caps;
342                 if (pdata->host_caps2)
343                         host->mmc->caps2 |= pdata->host_caps2;
344                 if (pdata->pm_caps)
345                         host->mmc->pm_caps |= pdata->pm_caps;
346 
347                 if (gpio_is_valid(pdata->ext_cd_gpio)) {
348                         ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio,
349                                                   0);
350                         if (ret) {
351                                 dev_err(mmc_dev(host->mmc),
352                                         "failed to allocate card detect gpio\n");
353                                 goto err_cd_req;
354                         }
355                 }
356         }
357 
358         pm_runtime_enable(&pdev->dev);
359         pm_runtime_get_sync(&pdev->dev);
360         pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
361         pm_runtime_use_autosuspend(&pdev->dev);
362         pm_suspend_ignore_children(&pdev->dev, 1);
363 
364         ret = sdhci_add_host(host);
365         if (ret) {
366                 dev_err(&pdev->dev, "failed to add host\n");
367                 goto err_add_host;
368         }
369 
370         platform_set_drvdata(pdev, host);
371 
372         if (host->mmc->pm_caps & MMC_PM_KEEP_POWER) {
373                 device_init_wakeup(&pdev->dev, 1);
374                 host->mmc->pm_flags |= MMC_PM_WAKE_SDIO_IRQ;
375         } else {
376                 device_init_wakeup(&pdev->dev, 0);
377         }
378 
379         pm_runtime_put_autosuspend(&pdev->dev);
380 
381         return 0;
382 
383 err_of_parse:
384 err_cd_req:
385 err_add_host:
386         pm_runtime_put_sync(&pdev->dev);
387         pm_runtime_disable(&pdev->dev);
388         clk_disable_unprepare(clk);
389         clk_put(clk);
390 err_clk_get:
391 err_mbus_win:
392         sdhci_pltfm_free(pdev);
393         kfree(pxa);
394         return ret;
395 }
396 
397 static int sdhci_pxav3_remove(struct platform_device *pdev)
398 {
399         struct sdhci_host *host = platform_get_drvdata(pdev);
400         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
401         struct sdhci_pxa *pxa = pltfm_host->priv;
402 
403         pm_runtime_get_sync(&pdev->dev);
404         sdhci_remove_host(host, 1);
405         pm_runtime_disable(&pdev->dev);
406 
407         clk_disable_unprepare(pltfm_host->clk);
408         clk_put(pltfm_host->clk);
409 
410         sdhci_pltfm_free(pdev);
411         kfree(pxa);
412 
413         return 0;
414 }
415 
416 #ifdef CONFIG_PM_SLEEP
417 static int sdhci_pxav3_suspend(struct device *dev)
418 {
419         int ret;
420         struct sdhci_host *host = dev_get_drvdata(dev);
421 
422         pm_runtime_get_sync(dev);
423         ret = sdhci_suspend_host(host);
424         pm_runtime_mark_last_busy(dev);
425         pm_runtime_put_autosuspend(dev);
426 
427         return ret;
428 }
429 
430 static int sdhci_pxav3_resume(struct device *dev)
431 {
432         int ret;
433         struct sdhci_host *host = dev_get_drvdata(dev);
434 
435         pm_runtime_get_sync(dev);
436         ret = sdhci_resume_host(host);
437         pm_runtime_mark_last_busy(dev);
438         pm_runtime_put_autosuspend(dev);
439 
440         return ret;
441 }
442 #endif
443 
444 #ifdef CONFIG_PM_RUNTIME
445 static int sdhci_pxav3_runtime_suspend(struct device *dev)
446 {
447         struct sdhci_host *host = dev_get_drvdata(dev);
448         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
449         unsigned long flags;
450 
451         if (pltfm_host->clk) {
452                 spin_lock_irqsave(&host->lock, flags);
453                 host->runtime_suspended = true;
454                 spin_unlock_irqrestore(&host->lock, flags);
455 
456                 clk_disable_unprepare(pltfm_host->clk);
457         }
458 
459         return 0;
460 }
461 
462 static int sdhci_pxav3_runtime_resume(struct device *dev)
463 {
464         struct sdhci_host *host = dev_get_drvdata(dev);
465         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
466         unsigned long flags;
467 
468         if (pltfm_host->clk) {
469                 clk_prepare_enable(pltfm_host->clk);
470 
471                 spin_lock_irqsave(&host->lock, flags);
472                 host->runtime_suspended = false;
473                 spin_unlock_irqrestore(&host->lock, flags);
474         }
475 
476         return 0;
477 }
478 #endif
479 
480 #ifdef CONFIG_PM
481 static const struct dev_pm_ops sdhci_pxav3_pmops = {
482         SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
483         SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
484                 sdhci_pxav3_runtime_resume, NULL)
485 };
486 
487 #define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops)
488 
489 #else
490 #define SDHCI_PXAV3_PMOPS NULL
491 #endif
492 
493 static struct platform_driver sdhci_pxav3_driver = {
494         .driver         = {
495                 .name   = "sdhci-pxav3",
496 #ifdef CONFIG_OF
497                 .of_match_table = sdhci_pxav3_of_match,
498 #endif
499                 .owner  = THIS_MODULE,
500                 .pm     = SDHCI_PXAV3_PMOPS,
501         },
502         .probe          = sdhci_pxav3_probe,
503         .remove         = sdhci_pxav3_remove,
504 };
505 
506 module_platform_driver(sdhci_pxav3_driver);
507 
508 MODULE_DESCRIPTION("SDHCI driver for pxav3");
509 MODULE_AUTHOR("Marvell International Ltd.");
510 MODULE_LICENSE("GPL v2");
511 
512 

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