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Linux/drivers/mmc/host/sdhci-pxav3.c

  1 /*
  2  * Copyright (C) 2010 Marvell International Ltd.
  3  *              Zhangfei Gao <zhangfei.gao@marvell.com>
  4  *              Kevin Wang <dwang4@marvell.com>
  5  *              Mingwei Wang <mwwang@marvell.com>
  6  *              Philip Rakity <prakity@marvell.com>
  7  *              Mark Brown <markb@marvell.com>
  8  *
  9  * This software is licensed under the terms of the GNU General Public
 10  * License version 2, as published by the Free Software Foundation, and
 11  * may be copied, distributed, and modified under those terms.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  * GNU General Public License for more details.
 17  *
 18  */
 19 #include <linux/err.h>
 20 #include <linux/init.h>
 21 #include <linux/platform_device.h>
 22 #include <linux/clk.h>
 23 #include <linux/io.h>
 24 #include <linux/gpio.h>
 25 #include <linux/mmc/card.h>
 26 #include <linux/mmc/host.h>
 27 #include <linux/mmc/slot-gpio.h>
 28 #include <linux/platform_data/pxa_sdhci.h>
 29 #include <linux/slab.h>
 30 #include <linux/delay.h>
 31 #include <linux/module.h>
 32 #include <linux/of.h>
 33 #include <linux/of_device.h>
 34 #include <linux/of_gpio.h>
 35 #include <linux/pm.h>
 36 #include <linux/pm_runtime.h>
 37 #include <linux/mbus.h>
 38 
 39 #include "sdhci.h"
 40 #include "sdhci-pltfm.h"
 41 
 42 #define PXAV3_RPM_DELAY_MS     50
 43 
 44 #define SD_CLOCK_BURST_SIZE_SETUP               0x10A
 45 #define SDCLK_SEL       0x100
 46 #define SDCLK_DELAY_SHIFT       9
 47 #define SDCLK_DELAY_MASK        0x1f
 48 
 49 #define SD_CFG_FIFO_PARAM       0x100
 50 #define SDCFG_GEN_PAD_CLK_ON    (1<<6)
 51 #define SDCFG_GEN_PAD_CLK_CNT_MASK      0xFF
 52 #define SDCFG_GEN_PAD_CLK_CNT_SHIFT     24
 53 
 54 #define SD_SPI_MODE          0x108
 55 #define SD_CE_ATA_1          0x10C
 56 
 57 #define SD_CE_ATA_2          0x10E
 58 #define SDCE_MISC_INT           (1<<2)
 59 #define SDCE_MISC_INT_EN        (1<<1)
 60 
 61 /*
 62  * These registers are relative to the second register region, for the
 63  * MBus bridge.
 64  */
 65 #define SDHCI_WINDOW_CTRL(i)    (0x80 + ((i) << 3))
 66 #define SDHCI_WINDOW_BASE(i)    (0x84 + ((i) << 3))
 67 #define SDHCI_MAX_WIN_NUM       8
 68 
 69 static int mv_conf_mbus_windows(struct platform_device *pdev,
 70                                 const struct mbus_dram_target_info *dram)
 71 {
 72         int i;
 73         void __iomem *regs;
 74         struct resource *res;
 75 
 76         if (!dram) {
 77                 dev_err(&pdev->dev, "no mbus dram info\n");
 78                 return -EINVAL;
 79         }
 80 
 81         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 82         if (!res) {
 83                 dev_err(&pdev->dev, "cannot get mbus registers\n");
 84                 return -EINVAL;
 85         }
 86 
 87         regs = ioremap(res->start, resource_size(res));
 88         if (!regs) {
 89                 dev_err(&pdev->dev, "cannot map mbus registers\n");
 90                 return -ENOMEM;
 91         }
 92 
 93         for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) {
 94                 writel(0, regs + SDHCI_WINDOW_CTRL(i));
 95                 writel(0, regs + SDHCI_WINDOW_BASE(i));
 96         }
 97 
 98         for (i = 0; i < dram->num_cs; i++) {
 99                 const struct mbus_dram_window *cs = dram->cs + i;
100 
101                 /* Write size, attributes and target id to control register */
102                 writel(((cs->size - 1) & 0xffff0000) |
103                         (cs->mbus_attr << 8) |
104                         (dram->mbus_dram_target_id << 4) | 1,
105                         regs + SDHCI_WINDOW_CTRL(i));
106                 /* Write base address to base register */
107                 writel(cs->base, regs + SDHCI_WINDOW_BASE(i));
108         }
109 
110         iounmap(regs);
111 
112         return 0;
113 }
114 
115 static void pxav3_reset(struct sdhci_host *host, u8 mask)
116 {
117         struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
118         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
119 
120         sdhci_reset(host, mask);
121 
122         if (mask == SDHCI_RESET_ALL) {
123                 /*
124                  * tune timing of read data/command when crc error happen
125                  * no performance impact
126                  */
127                 if (pdata && 0 != pdata->clk_delay_cycles) {
128                         u16 tmp;
129 
130                         tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
131                         tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
132                                 << SDCLK_DELAY_SHIFT;
133                         tmp |= SDCLK_SEL;
134                         writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
135                 }
136         }
137 }
138 
139 #define MAX_WAIT_COUNT 5
140 static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
141 {
142         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
143         struct sdhci_pxa *pxa = pltfm_host->priv;
144         u16 tmp;
145         int count;
146 
147         if (pxa->power_mode == MMC_POWER_UP
148                         && power_mode == MMC_POWER_ON) {
149 
150                 dev_dbg(mmc_dev(host->mmc),
151                                 "%s: slot->power_mode = %d,"
152                                 "ios->power_mode = %d\n",
153                                 __func__,
154                                 pxa->power_mode,
155                                 power_mode);
156 
157                 /* set we want notice of when 74 clocks are sent */
158                 tmp = readw(host->ioaddr + SD_CE_ATA_2);
159                 tmp |= SDCE_MISC_INT_EN;
160                 writew(tmp, host->ioaddr + SD_CE_ATA_2);
161 
162                 /* start sending the 74 clocks */
163                 tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
164                 tmp |= SDCFG_GEN_PAD_CLK_ON;
165                 writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
166 
167                 /* slowest speed is about 100KHz or 10usec per clock */
168                 udelay(740);
169                 count = 0;
170 
171                 while (count++ < MAX_WAIT_COUNT) {
172                         if ((readw(host->ioaddr + SD_CE_ATA_2)
173                                                 & SDCE_MISC_INT) == 0)
174                                 break;
175                         udelay(10);
176                 }
177 
178                 if (count == MAX_WAIT_COUNT)
179                         dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
180 
181                 /* clear the interrupt bit if posted */
182                 tmp = readw(host->ioaddr + SD_CE_ATA_2);
183                 tmp |= SDCE_MISC_INT;
184                 writew(tmp, host->ioaddr + SD_CE_ATA_2);
185         }
186         pxa->power_mode = power_mode;
187 }
188 
189 static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
190 {
191         u16 ctrl_2;
192 
193         /*
194          * Set V18_EN -- UHS modes do not work without this.
195          * does not change signaling voltage
196          */
197         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
198 
199         /* Select Bus Speed Mode for host */
200         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
201         switch (uhs) {
202         case MMC_TIMING_UHS_SDR12:
203                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
204                 break;
205         case MMC_TIMING_UHS_SDR25:
206                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
207                 break;
208         case MMC_TIMING_UHS_SDR50:
209                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
210                 break;
211         case MMC_TIMING_UHS_SDR104:
212                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
213                 break;
214         case MMC_TIMING_UHS_DDR50:
215                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
216                 break;
217         }
218 
219         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
220         dev_dbg(mmc_dev(host->mmc),
221                 "%s uhs = %d, ctrl_2 = %04X\n",
222                 __func__, uhs, ctrl_2);
223 }
224 
225 static const struct sdhci_ops pxav3_sdhci_ops = {
226         .set_clock = sdhci_set_clock,
227         .set_uhs_signaling = pxav3_set_uhs_signaling,
228         .platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
229         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
230         .set_bus_width = sdhci_set_bus_width,
231         .reset = pxav3_reset,
232         .set_uhs_signaling = sdhci_set_uhs_signaling,
233 };
234 
235 static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
236         .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
237                 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
238                 | SDHCI_QUIRK_32BIT_ADMA_SIZE
239                 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
240         .ops = &pxav3_sdhci_ops,
241 };
242 
243 #ifdef CONFIG_OF
244 static const struct of_device_id sdhci_pxav3_of_match[] = {
245         {
246                 .compatible = "mrvl,pxav3-mmc",
247         },
248         {
249                 .compatible = "marvell,armada-380-sdhci",
250         },
251         {},
252 };
253 MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);
254 
255 static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
256 {
257         struct sdhci_pxa_platdata *pdata;
258         struct device_node *np = dev->of_node;
259         u32 clk_delay_cycles;
260 
261         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
262         if (!pdata)
263                 return NULL;
264 
265         of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
266         if (clk_delay_cycles > 0)
267                 pdata->clk_delay_cycles = clk_delay_cycles;
268 
269         return pdata;
270 }
271 #else
272 static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
273 {
274         return NULL;
275 }
276 #endif
277 
278 static int sdhci_pxav3_probe(struct platform_device *pdev)
279 {
280         struct sdhci_pltfm_host *pltfm_host;
281         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
282         struct device *dev = &pdev->dev;
283         struct device_node *np = pdev->dev.of_node;
284         struct sdhci_host *host = NULL;
285         struct sdhci_pxa *pxa = NULL;
286         const struct of_device_id *match;
287 
288         int ret;
289         struct clk *clk;
290 
291         pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL);
292         if (!pxa)
293                 return -ENOMEM;
294 
295         host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0);
296         if (IS_ERR(host)) {
297                 kfree(pxa);
298                 return PTR_ERR(host);
299         }
300 
301         if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
302                 ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
303                 if (ret < 0)
304                         goto err_mbus_win;
305         }
306 
307 
308         pltfm_host = sdhci_priv(host);
309         pltfm_host->priv = pxa;
310 
311         clk = clk_get(dev, NULL);
312         if (IS_ERR(clk)) {
313                 dev_err(dev, "failed to get io clock\n");
314                 ret = PTR_ERR(clk);
315                 goto err_clk_get;
316         }
317         pltfm_host->clk = clk;
318         clk_prepare_enable(clk);
319 
320         /* enable 1/8V DDR capable */
321         host->mmc->caps |= MMC_CAP_1_8V_DDR;
322 
323         match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
324         if (match) {
325                 ret = mmc_of_parse(host->mmc);
326                 if (ret)
327                         goto err_of_parse;
328                 sdhci_get_of_property(pdev);
329                 pdata = pxav3_get_mmc_pdata(dev);
330         } else if (pdata) {
331                 /* on-chip device */
332                 if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
333                         host->mmc->caps |= MMC_CAP_NONREMOVABLE;
334 
335                 /* If slot design supports 8 bit data, indicate this to MMC. */
336                 if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
337                         host->mmc->caps |= MMC_CAP_8_BIT_DATA;
338 
339                 if (pdata->quirks)
340                         host->quirks |= pdata->quirks;
341                 if (pdata->quirks2)
342                         host->quirks2 |= pdata->quirks2;
343                 if (pdata->host_caps)
344                         host->mmc->caps |= pdata->host_caps;
345                 if (pdata->host_caps2)
346                         host->mmc->caps2 |= pdata->host_caps2;
347                 if (pdata->pm_caps)
348                         host->mmc->pm_caps |= pdata->pm_caps;
349 
350                 if (gpio_is_valid(pdata->ext_cd_gpio)) {
351                         ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio,
352                                                   0);
353                         if (ret) {
354                                 dev_err(mmc_dev(host->mmc),
355                                         "failed to allocate card detect gpio\n");
356                                 goto err_cd_req;
357                         }
358                 }
359         }
360 
361         pm_runtime_enable(&pdev->dev);
362         pm_runtime_get_sync(&pdev->dev);
363         pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
364         pm_runtime_use_autosuspend(&pdev->dev);
365         pm_suspend_ignore_children(&pdev->dev, 1);
366 
367         ret = sdhci_add_host(host);
368         if (ret) {
369                 dev_err(&pdev->dev, "failed to add host\n");
370                 goto err_add_host;
371         }
372 
373         platform_set_drvdata(pdev, host);
374 
375         if (host->mmc->pm_caps & MMC_PM_KEEP_POWER) {
376                 device_init_wakeup(&pdev->dev, 1);
377                 host->mmc->pm_flags |= MMC_PM_WAKE_SDIO_IRQ;
378         } else {
379                 device_init_wakeup(&pdev->dev, 0);
380         }
381 
382         pm_runtime_put_autosuspend(&pdev->dev);
383 
384         return 0;
385 
386 err_of_parse:
387 err_cd_req:
388 err_add_host:
389         pm_runtime_put_sync(&pdev->dev);
390         pm_runtime_disable(&pdev->dev);
391         clk_disable_unprepare(clk);
392         clk_put(clk);
393 err_clk_get:
394 err_mbus_win:
395         sdhci_pltfm_free(pdev);
396         kfree(pxa);
397         return ret;
398 }
399 
400 static int sdhci_pxav3_remove(struct platform_device *pdev)
401 {
402         struct sdhci_host *host = platform_get_drvdata(pdev);
403         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
404         struct sdhci_pxa *pxa = pltfm_host->priv;
405 
406         pm_runtime_get_sync(&pdev->dev);
407         sdhci_remove_host(host, 1);
408         pm_runtime_disable(&pdev->dev);
409 
410         clk_disable_unprepare(pltfm_host->clk);
411         clk_put(pltfm_host->clk);
412 
413         sdhci_pltfm_free(pdev);
414         kfree(pxa);
415 
416         return 0;
417 }
418 
419 #ifdef CONFIG_PM_SLEEP
420 static int sdhci_pxav3_suspend(struct device *dev)
421 {
422         int ret;
423         struct sdhci_host *host = dev_get_drvdata(dev);
424 
425         pm_runtime_get_sync(dev);
426         ret = sdhci_suspend_host(host);
427         pm_runtime_mark_last_busy(dev);
428         pm_runtime_put_autosuspend(dev);
429 
430         return ret;
431 }
432 
433 static int sdhci_pxav3_resume(struct device *dev)
434 {
435         int ret;
436         struct sdhci_host *host = dev_get_drvdata(dev);
437 
438         pm_runtime_get_sync(dev);
439         ret = sdhci_resume_host(host);
440         pm_runtime_mark_last_busy(dev);
441         pm_runtime_put_autosuspend(dev);
442 
443         return ret;
444 }
445 #endif
446 
447 #ifdef CONFIG_PM_RUNTIME
448 static int sdhci_pxav3_runtime_suspend(struct device *dev)
449 {
450         struct sdhci_host *host = dev_get_drvdata(dev);
451         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
452         unsigned long flags;
453 
454         if (pltfm_host->clk) {
455                 spin_lock_irqsave(&host->lock, flags);
456                 host->runtime_suspended = true;
457                 spin_unlock_irqrestore(&host->lock, flags);
458 
459                 clk_disable_unprepare(pltfm_host->clk);
460         }
461 
462         return 0;
463 }
464 
465 static int sdhci_pxav3_runtime_resume(struct device *dev)
466 {
467         struct sdhci_host *host = dev_get_drvdata(dev);
468         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
469         unsigned long flags;
470 
471         if (pltfm_host->clk) {
472                 clk_prepare_enable(pltfm_host->clk);
473 
474                 spin_lock_irqsave(&host->lock, flags);
475                 host->runtime_suspended = false;
476                 spin_unlock_irqrestore(&host->lock, flags);
477         }
478 
479         return 0;
480 }
481 #endif
482 
483 #ifdef CONFIG_PM
484 static const struct dev_pm_ops sdhci_pxav3_pmops = {
485         SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
486         SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
487                 sdhci_pxav3_runtime_resume, NULL)
488 };
489 
490 #define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops)
491 
492 #else
493 #define SDHCI_PXAV3_PMOPS NULL
494 #endif
495 
496 static struct platform_driver sdhci_pxav3_driver = {
497         .driver         = {
498                 .name   = "sdhci-pxav3",
499 #ifdef CONFIG_OF
500                 .of_match_table = sdhci_pxav3_of_match,
501 #endif
502                 .owner  = THIS_MODULE,
503                 .pm     = SDHCI_PXAV3_PMOPS,
504         },
505         .probe          = sdhci_pxav3_probe,
506         .remove         = sdhci_pxav3_remove,
507 };
508 
509 module_platform_driver(sdhci_pxav3_driver);
510 
511 MODULE_DESCRIPTION("SDHCI driver for pxav3");
512 MODULE_AUTHOR("Marvell International Ltd.");
513 MODULE_LICENSE("GPL v2");
514 
515 

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