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Linux/drivers/mmc/host/sdhci-pxav3.c

  1 /*
  2  * Copyright (C) 2010 Marvell International Ltd.
  3  *              Zhangfei Gao <zhangfei.gao@marvell.com>
  4  *              Kevin Wang <dwang4@marvell.com>
  5  *              Mingwei Wang <mwwang@marvell.com>
  6  *              Philip Rakity <prakity@marvell.com>
  7  *              Mark Brown <markb@marvell.com>
  8  *
  9  * This software is licensed under the terms of the GNU General Public
 10  * License version 2, as published by the Free Software Foundation, and
 11  * may be copied, distributed, and modified under those terms.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  * GNU General Public License for more details.
 17  *
 18  */
 19 #include <linux/err.h>
 20 #include <linux/init.h>
 21 #include <linux/platform_device.h>
 22 #include <linux/clk.h>
 23 #include <linux/io.h>
 24 #include <linux/gpio.h>
 25 #include <linux/mmc/card.h>
 26 #include <linux/mmc/host.h>
 27 #include <linux/mmc/slot-gpio.h>
 28 #include <linux/platform_data/pxa_sdhci.h>
 29 #include <linux/slab.h>
 30 #include <linux/delay.h>
 31 #include <linux/module.h>
 32 #include <linux/of.h>
 33 #include <linux/of_device.h>
 34 #include <linux/of_gpio.h>
 35 #include <linux/pm.h>
 36 #include <linux/pm_runtime.h>
 37 #include <linux/mbus.h>
 38 
 39 #include "sdhci.h"
 40 #include "sdhci-pltfm.h"
 41 
 42 #define PXAV3_RPM_DELAY_MS     50
 43 
 44 #define SD_CLOCK_BURST_SIZE_SETUP               0x10A
 45 #define SDCLK_SEL       0x100
 46 #define SDCLK_DELAY_SHIFT       9
 47 #define SDCLK_DELAY_MASK        0x1f
 48 
 49 #define SD_CFG_FIFO_PARAM       0x100
 50 #define SDCFG_GEN_PAD_CLK_ON    (1<<6)
 51 #define SDCFG_GEN_PAD_CLK_CNT_MASK      0xFF
 52 #define SDCFG_GEN_PAD_CLK_CNT_SHIFT     24
 53 
 54 #define SD_SPI_MODE          0x108
 55 #define SD_CE_ATA_1          0x10C
 56 
 57 #define SD_CE_ATA_2          0x10E
 58 #define SDCE_MISC_INT           (1<<2)
 59 #define SDCE_MISC_INT_EN        (1<<1)
 60 
 61 struct sdhci_pxa {
 62         struct clk *clk_core;
 63         struct clk *clk_io;
 64         u8      power_mode;
 65         void __iomem *sdio3_conf_reg;
 66 };
 67 
 68 /*
 69  * These registers are relative to the second register region, for the
 70  * MBus bridge.
 71  */
 72 #define SDHCI_WINDOW_CTRL(i)    (0x80 + ((i) << 3))
 73 #define SDHCI_WINDOW_BASE(i)    (0x84 + ((i) << 3))
 74 #define SDHCI_MAX_WIN_NUM       8
 75 
 76 /*
 77  * Fields below belong to SDIO3 Configuration Register (third register
 78  * region for the Armada 38x flavor)
 79  */
 80 
 81 #define SDIO3_CONF_CLK_INV      BIT(0)
 82 #define SDIO3_CONF_SD_FB_CLK    BIT(2)
 83 
 84 static int mv_conf_mbus_windows(struct platform_device *pdev,
 85                                 const struct mbus_dram_target_info *dram)
 86 {
 87         int i;
 88         void __iomem *regs;
 89         struct resource *res;
 90 
 91         if (!dram) {
 92                 dev_err(&pdev->dev, "no mbus dram info\n");
 93                 return -EINVAL;
 94         }
 95 
 96         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 97         if (!res) {
 98                 dev_err(&pdev->dev, "cannot get mbus registers\n");
 99                 return -EINVAL;
100         }
101 
102         regs = ioremap(res->start, resource_size(res));
103         if (!regs) {
104                 dev_err(&pdev->dev, "cannot map mbus registers\n");
105                 return -ENOMEM;
106         }
107 
108         for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) {
109                 writel(0, regs + SDHCI_WINDOW_CTRL(i));
110                 writel(0, regs + SDHCI_WINDOW_BASE(i));
111         }
112 
113         for (i = 0; i < dram->num_cs; i++) {
114                 const struct mbus_dram_window *cs = dram->cs + i;
115 
116                 /* Write size, attributes and target id to control register */
117                 writel(((cs->size - 1) & 0xffff0000) |
118                         (cs->mbus_attr << 8) |
119                         (dram->mbus_dram_target_id << 4) | 1,
120                         regs + SDHCI_WINDOW_CTRL(i));
121                 /* Write base address to base register */
122                 writel(cs->base, regs + SDHCI_WINDOW_BASE(i));
123         }
124 
125         iounmap(regs);
126 
127         return 0;
128 }
129 
130 static int armada_38x_quirks(struct platform_device *pdev,
131                              struct sdhci_host *host)
132 {
133         struct device_node *np = pdev->dev.of_node;
134         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
135         struct sdhci_pxa *pxa = pltfm_host->priv;
136         struct resource *res;
137 
138         host->quirks |= SDHCI_QUIRK_MISSING_CAPS;
139         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
140                                            "conf-sdio3");
141         if (res) {
142                 pxa->sdio3_conf_reg = devm_ioremap_resource(&pdev->dev, res);
143                 if (IS_ERR(pxa->sdio3_conf_reg))
144                         return PTR_ERR(pxa->sdio3_conf_reg);
145         } else {
146                 /*
147                  * According to erratum 'FE-2946959' both SDR50 and DDR50
148                  * modes require specific clock adjustments in SDIO3
149                  * Configuration register, if the adjustment is not done,
150                  * remove them from the capabilities.
151                  */
152                 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
153                 host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
154 
155                 dev_warn(&pdev->dev, "conf-sdio3 register not found: disabling SDR50 and DDR50 modes.\nConsider updating your dtb\n");
156         }
157 
158         /*
159          * According to erratum 'ERR-7878951' Armada 38x SDHCI
160          * controller has different capabilities than the ones shown
161          * in its registers
162          */
163         host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
164         if (of_property_read_bool(np, "no-1-8-v")) {
165                 host->caps &= ~SDHCI_CAN_VDD_180;
166                 host->mmc->caps &= ~MMC_CAP_1_8V_DDR;
167         } else {
168                 host->caps &= ~SDHCI_CAN_VDD_330;
169         }
170         host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_USE_SDR50_TUNING);
171 
172         return 0;
173 }
174 
175 static void pxav3_reset(struct sdhci_host *host, u8 mask)
176 {
177         struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
178         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
179 
180         sdhci_reset(host, mask);
181 
182         if (mask == SDHCI_RESET_ALL) {
183                 /*
184                  * tune timing of read data/command when crc error happen
185                  * no performance impact
186                  */
187                 if (pdata && 0 != pdata->clk_delay_cycles) {
188                         u16 tmp;
189 
190                         tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
191                         tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
192                                 << SDCLK_DELAY_SHIFT;
193                         tmp |= SDCLK_SEL;
194                         writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
195                 }
196         }
197 }
198 
199 #define MAX_WAIT_COUNT 5
200 static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
201 {
202         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
203         struct sdhci_pxa *pxa = pltfm_host->priv;
204         u16 tmp;
205         int count;
206 
207         if (pxa->power_mode == MMC_POWER_UP
208                         && power_mode == MMC_POWER_ON) {
209 
210                 dev_dbg(mmc_dev(host->mmc),
211                                 "%s: slot->power_mode = %d,"
212                                 "ios->power_mode = %d\n",
213                                 __func__,
214                                 pxa->power_mode,
215                                 power_mode);
216 
217                 /* set we want notice of when 74 clocks are sent */
218                 tmp = readw(host->ioaddr + SD_CE_ATA_2);
219                 tmp |= SDCE_MISC_INT_EN;
220                 writew(tmp, host->ioaddr + SD_CE_ATA_2);
221 
222                 /* start sending the 74 clocks */
223                 tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
224                 tmp |= SDCFG_GEN_PAD_CLK_ON;
225                 writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
226 
227                 /* slowest speed is about 100KHz or 10usec per clock */
228                 udelay(740);
229                 count = 0;
230 
231                 while (count++ < MAX_WAIT_COUNT) {
232                         if ((readw(host->ioaddr + SD_CE_ATA_2)
233                                                 & SDCE_MISC_INT) == 0)
234                                 break;
235                         udelay(10);
236                 }
237 
238                 if (count == MAX_WAIT_COUNT)
239                         dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
240 
241                 /* clear the interrupt bit if posted */
242                 tmp = readw(host->ioaddr + SD_CE_ATA_2);
243                 tmp |= SDCE_MISC_INT;
244                 writew(tmp, host->ioaddr + SD_CE_ATA_2);
245         }
246         pxa->power_mode = power_mode;
247 }
248 
249 static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
250 {
251         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
252         struct sdhci_pxa *pxa = pltfm_host->priv;
253         u16 ctrl_2;
254 
255         /*
256          * Set V18_EN -- UHS modes do not work without this.
257          * does not change signaling voltage
258          */
259         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
260 
261         /* Select Bus Speed Mode for host */
262         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
263         switch (uhs) {
264         case MMC_TIMING_UHS_SDR12:
265                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
266                 break;
267         case MMC_TIMING_UHS_SDR25:
268                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
269                 break;
270         case MMC_TIMING_UHS_SDR50:
271                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
272                 break;
273         case MMC_TIMING_UHS_SDR104:
274                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
275                 break;
276         case MMC_TIMING_MMC_DDR52:
277         case MMC_TIMING_UHS_DDR50:
278                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
279                 break;
280         }
281 
282         /*
283          * Update SDIO3 Configuration register according to erratum
284          * FE-2946959
285          */
286         if (pxa->sdio3_conf_reg) {
287                 u8 reg_val  = readb(pxa->sdio3_conf_reg);
288 
289                 if (uhs == MMC_TIMING_UHS_SDR50 ||
290                     uhs == MMC_TIMING_UHS_DDR50) {
291                         reg_val &= ~SDIO3_CONF_CLK_INV;
292                         reg_val |= SDIO3_CONF_SD_FB_CLK;
293                 } else {
294                         reg_val |= SDIO3_CONF_CLK_INV;
295                         reg_val &= ~SDIO3_CONF_SD_FB_CLK;
296                 }
297                 writeb(reg_val, pxa->sdio3_conf_reg);
298         }
299 
300         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
301         dev_dbg(mmc_dev(host->mmc),
302                 "%s uhs = %d, ctrl_2 = %04X\n",
303                 __func__, uhs, ctrl_2);
304 }
305 
306 static const struct sdhci_ops pxav3_sdhci_ops = {
307         .set_clock = sdhci_set_clock,
308         .platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
309         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
310         .set_bus_width = sdhci_set_bus_width,
311         .reset = pxav3_reset,
312         .set_uhs_signaling = pxav3_set_uhs_signaling,
313 };
314 
315 static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
316         .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
317                 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
318                 | SDHCI_QUIRK_32BIT_ADMA_SIZE
319                 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
320         .ops = &pxav3_sdhci_ops,
321 };
322 
323 #ifdef CONFIG_OF
324 static const struct of_device_id sdhci_pxav3_of_match[] = {
325         {
326                 .compatible = "mrvl,pxav3-mmc",
327         },
328         {
329                 .compatible = "marvell,armada-380-sdhci",
330         },
331         {},
332 };
333 MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);
334 
335 static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
336 {
337         struct sdhci_pxa_platdata *pdata;
338         struct device_node *np = dev->of_node;
339         u32 clk_delay_cycles;
340 
341         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
342         if (!pdata)
343                 return NULL;
344 
345         if (!of_property_read_u32(np, "mrvl,clk-delay-cycles",
346                                   &clk_delay_cycles))
347                 pdata->clk_delay_cycles = clk_delay_cycles;
348 
349         return pdata;
350 }
351 #else
352 static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
353 {
354         return NULL;
355 }
356 #endif
357 
358 static int sdhci_pxav3_probe(struct platform_device *pdev)
359 {
360         struct sdhci_pltfm_host *pltfm_host;
361         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
362         struct device *dev = &pdev->dev;
363         struct device_node *np = pdev->dev.of_node;
364         struct sdhci_host *host = NULL;
365         struct sdhci_pxa *pxa = NULL;
366         const struct of_device_id *match;
367         int ret;
368 
369         pxa = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_pxa), GFP_KERNEL);
370         if (!pxa)
371                 return -ENOMEM;
372 
373         host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0);
374         if (IS_ERR(host))
375                 return PTR_ERR(host);
376 
377         pltfm_host = sdhci_priv(host);
378         pltfm_host->priv = pxa;
379 
380         pxa->clk_io = devm_clk_get(dev, "io");
381         if (IS_ERR(pxa->clk_io))
382                 pxa->clk_io = devm_clk_get(dev, NULL);
383         if (IS_ERR(pxa->clk_io)) {
384                 dev_err(dev, "failed to get io clock\n");
385                 ret = PTR_ERR(pxa->clk_io);
386                 goto err_clk_get;
387         }
388         pltfm_host->clk = pxa->clk_io;
389         clk_prepare_enable(pxa->clk_io);
390 
391         pxa->clk_core = devm_clk_get(dev, "core");
392         if (!IS_ERR(pxa->clk_core))
393                 clk_prepare_enable(pxa->clk_core);
394 
395         /* enable 1/8V DDR capable */
396         host->mmc->caps |= MMC_CAP_1_8V_DDR;
397 
398         if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
399                 ret = armada_38x_quirks(pdev, host);
400                 if (ret < 0)
401                         goto err_clk_get;
402                 ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
403                 if (ret < 0)
404                         goto err_mbus_win;
405         }
406 
407         match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
408         if (match) {
409                 ret = mmc_of_parse(host->mmc);
410                 if (ret)
411                         goto err_of_parse;
412                 sdhci_get_of_property(pdev);
413                 pdata = pxav3_get_mmc_pdata(dev);
414                 pdev->dev.platform_data = pdata;
415         } else if (pdata) {
416                 /* on-chip device */
417                 if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
418                         host->mmc->caps |= MMC_CAP_NONREMOVABLE;
419 
420                 /* If slot design supports 8 bit data, indicate this to MMC. */
421                 if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
422                         host->mmc->caps |= MMC_CAP_8_BIT_DATA;
423 
424                 if (pdata->quirks)
425                         host->quirks |= pdata->quirks;
426                 if (pdata->quirks2)
427                         host->quirks2 |= pdata->quirks2;
428                 if (pdata->host_caps)
429                         host->mmc->caps |= pdata->host_caps;
430                 if (pdata->host_caps2)
431                         host->mmc->caps2 |= pdata->host_caps2;
432                 if (pdata->pm_caps)
433                         host->mmc->pm_caps |= pdata->pm_caps;
434 
435                 if (gpio_is_valid(pdata->ext_cd_gpio)) {
436                         ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio,
437                                                   0);
438                         if (ret) {
439                                 dev_err(mmc_dev(host->mmc),
440                                         "failed to allocate card detect gpio\n");
441                                 goto err_cd_req;
442                         }
443                 }
444         }
445 
446         pm_runtime_get_noresume(&pdev->dev);
447         pm_runtime_set_active(&pdev->dev);
448         pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
449         pm_runtime_use_autosuspend(&pdev->dev);
450         pm_runtime_enable(&pdev->dev);
451         pm_suspend_ignore_children(&pdev->dev, 1);
452 
453         ret = sdhci_add_host(host);
454         if (ret) {
455                 dev_err(&pdev->dev, "failed to add host\n");
456                 goto err_add_host;
457         }
458 
459         platform_set_drvdata(pdev, host);
460 
461         if (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ)
462                 device_init_wakeup(&pdev->dev, 1);
463 
464         pm_runtime_put_autosuspend(&pdev->dev);
465 
466         return 0;
467 
468 err_add_host:
469         pm_runtime_disable(&pdev->dev);
470         pm_runtime_put_noidle(&pdev->dev);
471 err_of_parse:
472 err_cd_req:
473 err_mbus_win:
474         clk_disable_unprepare(pxa->clk_io);
475         clk_disable_unprepare(pxa->clk_core);
476 err_clk_get:
477         sdhci_pltfm_free(pdev);
478         return ret;
479 }
480 
481 static int sdhci_pxav3_remove(struct platform_device *pdev)
482 {
483         struct sdhci_host *host = platform_get_drvdata(pdev);
484         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
485         struct sdhci_pxa *pxa = pltfm_host->priv;
486 
487         pm_runtime_get_sync(&pdev->dev);
488         pm_runtime_disable(&pdev->dev);
489         pm_runtime_put_noidle(&pdev->dev);
490 
491         sdhci_remove_host(host, 1);
492 
493         clk_disable_unprepare(pxa->clk_io);
494         clk_disable_unprepare(pxa->clk_core);
495 
496         sdhci_pltfm_free(pdev);
497 
498         return 0;
499 }
500 
501 #ifdef CONFIG_PM_SLEEP
502 static int sdhci_pxav3_suspend(struct device *dev)
503 {
504         int ret;
505         struct sdhci_host *host = dev_get_drvdata(dev);
506 
507         pm_runtime_get_sync(dev);
508         ret = sdhci_suspend_host(host);
509         pm_runtime_mark_last_busy(dev);
510         pm_runtime_put_autosuspend(dev);
511 
512         return ret;
513 }
514 
515 static int sdhci_pxav3_resume(struct device *dev)
516 {
517         int ret;
518         struct sdhci_host *host = dev_get_drvdata(dev);
519 
520         pm_runtime_get_sync(dev);
521         ret = sdhci_resume_host(host);
522         pm_runtime_mark_last_busy(dev);
523         pm_runtime_put_autosuspend(dev);
524 
525         return ret;
526 }
527 #endif
528 
529 #ifdef CONFIG_PM
530 static int sdhci_pxav3_runtime_suspend(struct device *dev)
531 {
532         struct sdhci_host *host = dev_get_drvdata(dev);
533         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
534         struct sdhci_pxa *pxa = pltfm_host->priv;
535         int ret;
536 
537         ret = sdhci_runtime_suspend_host(host);
538         if (ret)
539                 return ret;
540 
541         clk_disable_unprepare(pxa->clk_io);
542         if (!IS_ERR(pxa->clk_core))
543                 clk_disable_unprepare(pxa->clk_core);
544 
545         return 0;
546 }
547 
548 static int sdhci_pxav3_runtime_resume(struct device *dev)
549 {
550         struct sdhci_host *host = dev_get_drvdata(dev);
551         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
552         struct sdhci_pxa *pxa = pltfm_host->priv;
553 
554         clk_prepare_enable(pxa->clk_io);
555         if (!IS_ERR(pxa->clk_core))
556                 clk_prepare_enable(pxa->clk_core);
557 
558         return sdhci_runtime_resume_host(host);
559 }
560 #endif
561 
562 #ifdef CONFIG_PM
563 static const struct dev_pm_ops sdhci_pxav3_pmops = {
564         SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
565         SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
566                 sdhci_pxav3_runtime_resume, NULL)
567 };
568 
569 #define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops)
570 
571 #else
572 #define SDHCI_PXAV3_PMOPS NULL
573 #endif
574 
575 static struct platform_driver sdhci_pxav3_driver = {
576         .driver         = {
577                 .name   = "sdhci-pxav3",
578                 .of_match_table = of_match_ptr(sdhci_pxav3_of_match),
579                 .pm     = SDHCI_PXAV3_PMOPS,
580         },
581         .probe          = sdhci_pxav3_probe,
582         .remove         = sdhci_pxav3_remove,
583 };
584 
585 module_platform_driver(sdhci_pxav3_driver);
586 
587 MODULE_DESCRIPTION("SDHCI driver for pxav3");
588 MODULE_AUTHOR("Marvell International Ltd.");
589 MODULE_LICENSE("GPL v2");
590 
591 

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