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Linux/drivers/mmc/host/sdhci-pxav2.c

  1 /*
  2  * Copyright (C) 2010 Marvell International Ltd.
  3  *              Zhangfei Gao <zhangfei.gao@marvell.com>
  4  *              Kevin Wang <dwang4@marvell.com>
  5  *              Jun Nie <njun@marvell.com>
  6  *              Qiming Wu <wuqm@marvell.com>
  7  *              Philip Rakity <prakity@marvell.com>
  8  *
  9  * This software is licensed under the terms of the GNU General Public
 10  * License version 2, as published by the Free Software Foundation, and
 11  * may be copied, distributed, and modified under those terms.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  * GNU General Public License for more details.
 17  *
 18  */
 19 
 20 #include <linux/err.h>
 21 #include <linux/init.h>
 22 #include <linux/platform_device.h>
 23 #include <linux/clk.h>
 24 #include <linux/module.h>
 25 #include <linux/io.h>
 26 #include <linux/gpio.h>
 27 #include <linux/mmc/card.h>
 28 #include <linux/mmc/host.h>
 29 #include <linux/platform_data/pxa_sdhci.h>
 30 #include <linux/slab.h>
 31 #include <linux/of.h>
 32 #include <linux/of_device.h>
 33 
 34 #include "sdhci.h"
 35 #include "sdhci-pltfm.h"
 36 
 37 #define SD_FIFO_PARAM           0xe0
 38 #define DIS_PAD_SD_CLK_GATE     0x0400 /* Turn on/off Dynamic SD Clock Gating */
 39 #define CLK_GATE_ON             0x0200 /* Disable/enable Clock Gate */
 40 #define CLK_GATE_CTL            0x0100 /* Clock Gate Control */
 41 #define CLK_GATE_SETTING_BITS   (DIS_PAD_SD_CLK_GATE | \
 42                 CLK_GATE_ON | CLK_GATE_CTL)
 43 
 44 #define SD_CLOCK_BURST_SIZE_SETUP       0xe6
 45 #define SDCLK_SEL_SHIFT         8
 46 #define SDCLK_SEL_MASK          0x3
 47 #define SDCLK_DELAY_SHIFT       10
 48 #define SDCLK_DELAY_MASK        0x3c
 49 
 50 #define SD_CE_ATA_2             0xea
 51 #define MMC_CARD                0x1000
 52 #define MMC_WIDTH               0x0100
 53 
 54 static void pxav2_set_private_registers(struct sdhci_host *host, u8 mask)
 55 {
 56         struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
 57         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
 58 
 59         if (mask == SDHCI_RESET_ALL) {
 60                 u16 tmp = 0;
 61 
 62                 /*
 63                  * tune timing of read data/command when crc error happen
 64                  * no performance impact
 65                  */
 66                 if (pdata && pdata->clk_delay_sel == 1) {
 67                         tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
 68 
 69                         tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
 70                         tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
 71                                 << SDCLK_DELAY_SHIFT;
 72                         tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
 73                         tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT;
 74 
 75                         writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
 76                 }
 77 
 78                 if (pdata && (pdata->flags & PXA_FLAG_ENABLE_CLOCK_GATING)) {
 79                         tmp = readw(host->ioaddr + SD_FIFO_PARAM);
 80                         tmp &= ~CLK_GATE_SETTING_BITS;
 81                         writew(tmp, host->ioaddr + SD_FIFO_PARAM);
 82                 } else {
 83                         tmp = readw(host->ioaddr + SD_FIFO_PARAM);
 84                         tmp &= ~CLK_GATE_SETTING_BITS;
 85                         tmp |= CLK_GATE_SETTING_BITS;
 86                         writew(tmp, host->ioaddr + SD_FIFO_PARAM);
 87                 }
 88         }
 89 }
 90 
 91 static int pxav2_mmc_set_width(struct sdhci_host *host, int width)
 92 {
 93         u8 ctrl;
 94         u16 tmp;
 95 
 96         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 97         tmp = readw(host->ioaddr + SD_CE_ATA_2);
 98         if (width == MMC_BUS_WIDTH_8) {
 99                 ctrl &= ~SDHCI_CTRL_4BITBUS;
100                 tmp |= MMC_CARD | MMC_WIDTH;
101         } else {
102                 tmp &= ~(MMC_CARD | MMC_WIDTH);
103                 if (width == MMC_BUS_WIDTH_4)
104                         ctrl |= SDHCI_CTRL_4BITBUS;
105                 else
106                         ctrl &= ~SDHCI_CTRL_4BITBUS;
107         }
108         writew(tmp, host->ioaddr + SD_CE_ATA_2);
109         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
110 
111         return 0;
112 }
113 
114 static const struct sdhci_ops pxav2_sdhci_ops = {
115         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
116         .platform_reset_exit = pxav2_set_private_registers,
117         .platform_bus_width = pxav2_mmc_set_width,
118 };
119 
120 #ifdef CONFIG_OF
121 static const struct of_device_id sdhci_pxav2_of_match[] = {
122         {
123                 .compatible = "mrvl,pxav2-mmc",
124         },
125         {},
126 };
127 MODULE_DEVICE_TABLE(of, sdhci_pxav2_of_match);
128 
129 static struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev)
130 {
131         struct sdhci_pxa_platdata *pdata;
132         struct device_node *np = dev->of_node;
133         u32 bus_width;
134         u32 clk_delay_cycles;
135 
136         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
137         if (!pdata)
138                 return NULL;
139 
140         if (of_find_property(np, "non-removable", NULL))
141                 pdata->flags |= PXA_FLAG_CARD_PERMANENT;
142 
143         of_property_read_u32(np, "bus-width", &bus_width);
144         if (bus_width == 8)
145                 pdata->flags |= PXA_FLAG_SD_8_BIT_CAPABLE_SLOT;
146 
147         of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
148         if (clk_delay_cycles > 0) {
149                 pdata->clk_delay_sel = 1;
150                 pdata->clk_delay_cycles = clk_delay_cycles;
151         }
152 
153         return pdata;
154 }
155 #else
156 static inline struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev)
157 {
158         return NULL;
159 }
160 #endif
161 
162 static int sdhci_pxav2_probe(struct platform_device *pdev)
163 {
164         struct sdhci_pltfm_host *pltfm_host;
165         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
166         struct device *dev = &pdev->dev;
167         struct sdhci_host *host = NULL;
168         struct sdhci_pxa *pxa = NULL;
169         const struct of_device_id *match;
170 
171         int ret;
172         struct clk *clk;
173 
174         pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL);
175         if (!pxa)
176                 return -ENOMEM;
177 
178         host = sdhci_pltfm_init(pdev, NULL, 0);
179         if (IS_ERR(host)) {
180                 kfree(pxa);
181                 return PTR_ERR(host);
182         }
183         pltfm_host = sdhci_priv(host);
184         pltfm_host->priv = pxa;
185 
186         clk = clk_get(dev, "PXA-SDHCLK");
187         if (IS_ERR(clk)) {
188                 dev_err(dev, "failed to get io clock\n");
189                 ret = PTR_ERR(clk);
190                 goto err_clk_get;
191         }
192         pltfm_host->clk = clk;
193         clk_prepare_enable(clk);
194 
195         host->quirks = SDHCI_QUIRK_BROKEN_ADMA
196                 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
197                 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
198 
199         match = of_match_device(of_match_ptr(sdhci_pxav2_of_match), &pdev->dev);
200         if (match) {
201                 pdata = pxav2_get_mmc_pdata(dev);
202         }
203         if (pdata) {
204                 if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
205                         /* on-chip device */
206                         host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
207                         host->mmc->caps |= MMC_CAP_NONREMOVABLE;
208                 }
209 
210                 /* If slot design supports 8 bit data, indicate this to MMC. */
211                 if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
212                         host->mmc->caps |= MMC_CAP_8_BIT_DATA;
213 
214                 if (pdata->quirks)
215                         host->quirks |= pdata->quirks;
216                 if (pdata->host_caps)
217                         host->mmc->caps |= pdata->host_caps;
218                 if (pdata->pm_caps)
219                         host->mmc->pm_caps |= pdata->pm_caps;
220         }
221 
222         host->ops = &pxav2_sdhci_ops;
223 
224         ret = sdhci_add_host(host);
225         if (ret) {
226                 dev_err(&pdev->dev, "failed to add host\n");
227                 goto err_add_host;
228         }
229 
230         platform_set_drvdata(pdev, host);
231 
232         return 0;
233 
234 err_add_host:
235         clk_disable_unprepare(clk);
236         clk_put(clk);
237 err_clk_get:
238         sdhci_pltfm_free(pdev);
239         kfree(pxa);
240         return ret;
241 }
242 
243 static int sdhci_pxav2_remove(struct platform_device *pdev)
244 {
245         struct sdhci_host *host = platform_get_drvdata(pdev);
246         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
247         struct sdhci_pxa *pxa = pltfm_host->priv;
248 
249         sdhci_remove_host(host, 1);
250 
251         clk_disable_unprepare(pltfm_host->clk);
252         clk_put(pltfm_host->clk);
253         sdhci_pltfm_free(pdev);
254         kfree(pxa);
255 
256         return 0;
257 }
258 
259 static struct platform_driver sdhci_pxav2_driver = {
260         .driver         = {
261                 .name   = "sdhci-pxav2",
262                 .owner  = THIS_MODULE,
263 #ifdef CONFIG_OF
264                 .of_match_table = sdhci_pxav2_of_match,
265 #endif
266                 .pm     = SDHCI_PLTFM_PMOPS,
267         },
268         .probe          = sdhci_pxav2_probe,
269         .remove         = sdhci_pxav2_remove,
270 };
271 
272 module_platform_driver(sdhci_pxav2_driver);
273 
274 MODULE_DESCRIPTION("SDHCI driver for pxav2");
275 MODULE_AUTHOR("Marvell International Ltd.");
276 MODULE_LICENSE("GPL v2");
277 
278 

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