Version:  2.0.40 2.2.26 2.4.37 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0

Linux/drivers/mmc/host/sdhci-pci.c

  1 /*  linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
  2  *
  3  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
  4  *
  5  * This program is free software; you can redistribute it and/or modify
  6  * it under the terms of the GNU General Public License as published by
  7  * the Free Software Foundation; either version 2 of the License, or (at
  8  * your option) any later version.
  9  *
 10  * Thanks to the following companies for their support:
 11  *
 12  *     - JMicron (hardware and technical support)
 13  */
 14 
 15 #include <linux/delay.h>
 16 #include <linux/highmem.h>
 17 #include <linux/module.h>
 18 #include <linux/pci.h>
 19 #include <linux/dma-mapping.h>
 20 #include <linux/slab.h>
 21 #include <linux/device.h>
 22 #include <linux/mmc/host.h>
 23 #include <linux/scatterlist.h>
 24 #include <linux/io.h>
 25 #include <linux/gpio.h>
 26 #include <linux/pm_runtime.h>
 27 #include <linux/mmc/slot-gpio.h>
 28 #include <linux/mmc/sdhci-pci-data.h>
 29 
 30 #include "sdhci.h"
 31 #include "sdhci-pci.h"
 32 #include "sdhci-pci-o2micro.h"
 33 
 34 /*****************************************************************************\
 35  *                                                                           *
 36  * Hardware specific quirk handling                                          *
 37  *                                                                           *
 38 \*****************************************************************************/
 39 
 40 static int ricoh_probe(struct sdhci_pci_chip *chip)
 41 {
 42         if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
 43             chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
 44                 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
 45         return 0;
 46 }
 47 
 48 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
 49 {
 50         slot->host->caps =
 51                 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
 52                         & SDHCI_TIMEOUT_CLK_MASK) |
 53 
 54                 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
 55                         & SDHCI_CLOCK_BASE_MASK) |
 56 
 57                 SDHCI_TIMEOUT_CLK_UNIT |
 58                 SDHCI_CAN_VDD_330 |
 59                 SDHCI_CAN_DO_HISPD |
 60                 SDHCI_CAN_DO_SDMA;
 61         return 0;
 62 }
 63 
 64 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
 65 {
 66         /* Apply a delay to allow controller to settle */
 67         /* Otherwise it becomes confused if card state changed
 68                 during suspend */
 69         msleep(500);
 70         return 0;
 71 }
 72 
 73 static const struct sdhci_pci_fixes sdhci_ricoh = {
 74         .probe          = ricoh_probe,
 75         .quirks         = SDHCI_QUIRK_32BIT_DMA_ADDR |
 76                           SDHCI_QUIRK_FORCE_DMA |
 77                           SDHCI_QUIRK_CLOCK_BEFORE_RESET,
 78 };
 79 
 80 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
 81         .probe_slot     = ricoh_mmc_probe_slot,
 82         .resume         = ricoh_mmc_resume,
 83         .quirks         = SDHCI_QUIRK_32BIT_DMA_ADDR |
 84                           SDHCI_QUIRK_CLOCK_BEFORE_RESET |
 85                           SDHCI_QUIRK_NO_CARD_NO_RESET |
 86                           SDHCI_QUIRK_MISSING_CAPS
 87 };
 88 
 89 static const struct sdhci_pci_fixes sdhci_ene_712 = {
 90         .quirks         = SDHCI_QUIRK_SINGLE_POWER_WRITE |
 91                           SDHCI_QUIRK_BROKEN_DMA,
 92 };
 93 
 94 static const struct sdhci_pci_fixes sdhci_ene_714 = {
 95         .quirks         = SDHCI_QUIRK_SINGLE_POWER_WRITE |
 96                           SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
 97                           SDHCI_QUIRK_BROKEN_DMA,
 98 };
 99 
100 static const struct sdhci_pci_fixes sdhci_cafe = {
101         .quirks         = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
102                           SDHCI_QUIRK_NO_BUSY_IRQ |
103                           SDHCI_QUIRK_BROKEN_CARD_DETECTION |
104                           SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
105 };
106 
107 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
108         .quirks         = SDHCI_QUIRK_NO_HISPD_BIT,
109 };
110 
111 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
112 {
113         slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
114         return 0;
115 }
116 
117 /*
118  * ADMA operation is disabled for Moorestown platform due to
119  * hardware bugs.
120  */
121 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
122 {
123         /*
124          * slots number is fixed here for MRST as SDIO3/5 are never used and
125          * have hardware bugs.
126          */
127         chip->num_slots = 1;
128         return 0;
129 }
130 
131 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
132 {
133         slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
134         return 0;
135 }
136 
137 #ifdef CONFIG_PM
138 
139 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
140 {
141         struct sdhci_pci_slot *slot = dev_id;
142         struct sdhci_host *host = slot->host;
143 
144         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
145         return IRQ_HANDLED;
146 }
147 
148 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
149 {
150         int err, irq, gpio = slot->cd_gpio;
151 
152         slot->cd_gpio = -EINVAL;
153         slot->cd_irq = -EINVAL;
154 
155         if (!gpio_is_valid(gpio))
156                 return;
157 
158         err = gpio_request(gpio, "sd_cd");
159         if (err < 0)
160                 goto out;
161 
162         err = gpio_direction_input(gpio);
163         if (err < 0)
164                 goto out_free;
165 
166         irq = gpio_to_irq(gpio);
167         if (irq < 0)
168                 goto out_free;
169 
170         err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
171                           IRQF_TRIGGER_FALLING, "sd_cd", slot);
172         if (err)
173                 goto out_free;
174 
175         slot->cd_gpio = gpio;
176         slot->cd_irq = irq;
177 
178         return;
179 
180 out_free:
181         gpio_free(gpio);
182 out:
183         dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
184 }
185 
186 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
187 {
188         if (slot->cd_irq >= 0)
189                 free_irq(slot->cd_irq, slot);
190         if (gpio_is_valid(slot->cd_gpio))
191                 gpio_free(slot->cd_gpio);
192 }
193 
194 #else
195 
196 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
197 {
198 }
199 
200 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
201 {
202 }
203 
204 #endif
205 
206 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
207 {
208         slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
209         slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
210                                   MMC_CAP2_HC_ERASE_SZ;
211         return 0;
212 }
213 
214 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
215 {
216         slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
217         return 0;
218 }
219 
220 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
221         .quirks         = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
222         .probe_slot     = mrst_hc_probe_slot,
223 };
224 
225 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
226         .quirks         = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
227         .probe          = mrst_hc_probe,
228 };
229 
230 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
231         .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
232         .allow_runtime_pm = true,
233         .own_cd_for_runtime_pm = true,
234 };
235 
236 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
237         .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
238         .quirks2        = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
239         .allow_runtime_pm = true,
240         .probe_slot     = mfd_sdio_probe_slot,
241 };
242 
243 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
244         .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
245         .allow_runtime_pm = true,
246         .probe_slot     = mfd_emmc_probe_slot,
247 };
248 
249 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
250         .quirks         = SDHCI_QUIRK_BROKEN_ADMA,
251         .probe_slot     = pch_hc_probe_slot,
252 };
253 
254 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
255 {
256         u8 reg;
257 
258         reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
259         reg |= 0x10;
260         sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
261         /* For eMMC, minimum is 1us but give it 9us for good measure */
262         udelay(9);
263         reg &= ~0x10;
264         sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
265         /* For eMMC, minimum is 200us but give it 300us for good measure */
266         usleep_range(300, 1000);
267 }
268 
269 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
270 {
271         slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
272                                  MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
273                                  MMC_CAP_BUS_WIDTH_TEST |
274                                  MMC_CAP_WAIT_WHILE_BUSY;
275         slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
276         slot->hw_reset = sdhci_pci_int_hw_reset;
277         if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
278                 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
279         return 0;
280 }
281 
282 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
283 {
284         slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
285                                  MMC_CAP_BUS_WIDTH_TEST |
286                                  MMC_CAP_WAIT_WHILE_BUSY;
287         return 0;
288 }
289 
290 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
291 {
292         slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST |
293                                  MMC_CAP_WAIT_WHILE_BUSY;
294         slot->cd_con_id = NULL;
295         slot->cd_idx = 0;
296         slot->cd_override_level = true;
297         return 0;
298 }
299 
300 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
301         .allow_runtime_pm = true,
302         .probe_slot     = byt_emmc_probe_slot,
303         .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
304         .quirks2        = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
305                           SDHCI_QUIRK2_STOP_WITH_TC,
306 };
307 
308 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
309         .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
310         .quirks2        = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
311                         SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
312         .allow_runtime_pm = true,
313         .probe_slot     = byt_sdio_probe_slot,
314 };
315 
316 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
317         .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
318         .quirks2        = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
319                           SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
320                           SDHCI_QUIRK2_STOP_WITH_TC,
321         .allow_runtime_pm = true,
322         .own_cd_for_runtime_pm = true,
323         .probe_slot     = byt_sd_probe_slot,
324 };
325 
326 /* Define Host controllers for Intel Merrifield platform */
327 #define INTEL_MRFL_EMMC_0       0
328 #define INTEL_MRFL_EMMC_1       1
329 
330 static int intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot *slot)
331 {
332         if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_0) &&
333             (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_1))
334                 /* SD support is not ready yet */
335                 return -ENODEV;
336 
337         slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
338                                  MMC_CAP_1_8V_DDR;
339 
340         return 0;
341 }
342 
343 static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = {
344         .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
345         .quirks2        = SDHCI_QUIRK2_BROKEN_HS200 |
346                         SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
347         .allow_runtime_pm = true,
348         .probe_slot     = intel_mrfl_mmc_probe_slot,
349 };
350 
351 /* O2Micro extra registers */
352 #define O2_SD_LOCK_WP           0xD3
353 #define O2_SD_MULTI_VCC3V       0xEE
354 #define O2_SD_CLKREQ            0xEC
355 #define O2_SD_CAPS              0xE0
356 #define O2_SD_ADMA1             0xE2
357 #define O2_SD_ADMA2             0xE7
358 #define O2_SD_INF_MOD           0xF1
359 
360 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
361 {
362         u8 scratch;
363         int ret;
364 
365         ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
366         if (ret)
367                 return ret;
368 
369         /*
370          * Turn PMOS on [bit 0], set over current detection to 2.4 V
371          * [bit 1:2] and enable over current debouncing [bit 6].
372          */
373         if (on)
374                 scratch |= 0x47;
375         else
376                 scratch &= ~0x47;
377 
378         ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
379         if (ret)
380                 return ret;
381 
382         return 0;
383 }
384 
385 static int jmicron_probe(struct sdhci_pci_chip *chip)
386 {
387         int ret;
388         u16 mmcdev = 0;
389 
390         if (chip->pdev->revision == 0) {
391                 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
392                           SDHCI_QUIRK_32BIT_DMA_SIZE |
393                           SDHCI_QUIRK_32BIT_ADMA_SIZE |
394                           SDHCI_QUIRK_RESET_AFTER_REQUEST |
395                           SDHCI_QUIRK_BROKEN_SMALL_PIO;
396         }
397 
398         /*
399          * JMicron chips can have two interfaces to the same hardware
400          * in order to work around limitations in Microsoft's driver.
401          * We need to make sure we only bind to one of them.
402          *
403          * This code assumes two things:
404          *
405          * 1. The PCI code adds subfunctions in order.
406          *
407          * 2. The MMC interface has a lower subfunction number
408          *    than the SD interface.
409          */
410         if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
411                 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
412         else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
413                 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
414 
415         if (mmcdev) {
416                 struct pci_dev *sd_dev;
417 
418                 sd_dev = NULL;
419                 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
420                                                 mmcdev, sd_dev)) != NULL) {
421                         if ((PCI_SLOT(chip->pdev->devfn) ==
422                                 PCI_SLOT(sd_dev->devfn)) &&
423                                 (chip->pdev->bus == sd_dev->bus))
424                                 break;
425                 }
426 
427                 if (sd_dev) {
428                         pci_dev_put(sd_dev);
429                         dev_info(&chip->pdev->dev, "Refusing to bind to "
430                                 "secondary interface.\n");
431                         return -ENODEV;
432                 }
433         }
434 
435         /*
436          * JMicron chips need a bit of a nudge to enable the power
437          * output pins.
438          */
439         ret = jmicron_pmos(chip, 1);
440         if (ret) {
441                 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
442                 return ret;
443         }
444 
445         /* quirk for unsable RO-detection on JM388 chips */
446         if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
447             chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
448                 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
449 
450         return 0;
451 }
452 
453 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
454 {
455         u8 scratch;
456 
457         scratch = readb(host->ioaddr + 0xC0);
458 
459         if (on)
460                 scratch |= 0x01;
461         else
462                 scratch &= ~0x01;
463 
464         writeb(scratch, host->ioaddr + 0xC0);
465 }
466 
467 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
468 {
469         if (slot->chip->pdev->revision == 0) {
470                 u16 version;
471 
472                 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
473                 version = (version & SDHCI_VENDOR_VER_MASK) >>
474                         SDHCI_VENDOR_VER_SHIFT;
475 
476                 /*
477                  * Older versions of the chip have lots of nasty glitches
478                  * in the ADMA engine. It's best just to avoid it
479                  * completely.
480                  */
481                 if (version < 0xAC)
482                         slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
483         }
484 
485         /* JM388 MMC doesn't support 1.8V while SD supports it */
486         if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
487                 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
488                         MMC_VDD_29_30 | MMC_VDD_30_31 |
489                         MMC_VDD_165_195; /* allow 1.8V */
490                 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
491                         MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
492         }
493 
494         /*
495          * The secondary interface requires a bit set to get the
496          * interrupts.
497          */
498         if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
499             slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
500                 jmicron_enable_mmc(slot->host, 1);
501 
502         slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
503 
504         return 0;
505 }
506 
507 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
508 {
509         if (dead)
510                 return;
511 
512         if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
513             slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
514                 jmicron_enable_mmc(slot->host, 0);
515 }
516 
517 static int jmicron_suspend(struct sdhci_pci_chip *chip)
518 {
519         int i;
520 
521         if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
522             chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
523                 for (i = 0; i < chip->num_slots; i++)
524                         jmicron_enable_mmc(chip->slots[i]->host, 0);
525         }
526 
527         return 0;
528 }
529 
530 static int jmicron_resume(struct sdhci_pci_chip *chip)
531 {
532         int ret, i;
533 
534         if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
535             chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
536                 for (i = 0; i < chip->num_slots; i++)
537                         jmicron_enable_mmc(chip->slots[i]->host, 1);
538         }
539 
540         ret = jmicron_pmos(chip, 1);
541         if (ret) {
542                 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
543                 return ret;
544         }
545 
546         return 0;
547 }
548 
549 static const struct sdhci_pci_fixes sdhci_o2 = {
550         .probe = sdhci_pci_o2_probe,
551         .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
552         .probe_slot = sdhci_pci_o2_probe_slot,
553         .resume = sdhci_pci_o2_resume,
554 };
555 
556 static const struct sdhci_pci_fixes sdhci_jmicron = {
557         .probe          = jmicron_probe,
558 
559         .probe_slot     = jmicron_probe_slot,
560         .remove_slot    = jmicron_remove_slot,
561 
562         .suspend        = jmicron_suspend,
563         .resume         = jmicron_resume,
564 };
565 
566 /* SysKonnect CardBus2SDIO extra registers */
567 #define SYSKT_CTRL              0x200
568 #define SYSKT_RDFIFO_STAT       0x204
569 #define SYSKT_WRFIFO_STAT       0x208
570 #define SYSKT_POWER_DATA        0x20c
571 #define   SYSKT_POWER_330       0xef
572 #define   SYSKT_POWER_300       0xf8
573 #define   SYSKT_POWER_184       0xcc
574 #define SYSKT_POWER_CMD         0x20d
575 #define   SYSKT_POWER_START     (1 << 7)
576 #define SYSKT_POWER_STATUS      0x20e
577 #define   SYSKT_POWER_STATUS_OK (1 << 0)
578 #define SYSKT_BOARD_REV         0x210
579 #define SYSKT_CHIP_REV          0x211
580 #define SYSKT_CONF_DATA         0x212
581 #define   SYSKT_CONF_DATA_1V8   (1 << 2)
582 #define   SYSKT_CONF_DATA_2V5   (1 << 1)
583 #define   SYSKT_CONF_DATA_3V3   (1 << 0)
584 
585 static int syskt_probe(struct sdhci_pci_chip *chip)
586 {
587         if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
588                 chip->pdev->class &= ~0x0000FF;
589                 chip->pdev->class |= PCI_SDHCI_IFDMA;
590         }
591         return 0;
592 }
593 
594 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
595 {
596         int tm, ps;
597 
598         u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
599         u8  chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
600         dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
601                                          "board rev %d.%d, chip rev %d.%d\n",
602                                          board_rev >> 4, board_rev & 0xf,
603                                          chip_rev >> 4,  chip_rev & 0xf);
604         if (chip_rev >= 0x20)
605                 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
606 
607         writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
608         writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
609         udelay(50);
610         tm = 10;  /* Wait max 1 ms */
611         do {
612                 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
613                 if (ps & SYSKT_POWER_STATUS_OK)
614                         break;
615                 udelay(100);
616         } while (--tm);
617         if (!tm) {
618                 dev_err(&slot->chip->pdev->dev,
619                         "power regulator never stabilized");
620                 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
621                 return -ENODEV;
622         }
623 
624         return 0;
625 }
626 
627 static const struct sdhci_pci_fixes sdhci_syskt = {
628         .quirks         = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
629         .probe          = syskt_probe,
630         .probe_slot     = syskt_probe_slot,
631 };
632 
633 static int via_probe(struct sdhci_pci_chip *chip)
634 {
635         if (chip->pdev->revision == 0x10)
636                 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
637 
638         return 0;
639 }
640 
641 static const struct sdhci_pci_fixes sdhci_via = {
642         .probe          = via_probe,
643 };
644 
645 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
646 {
647         slot->host->mmc->caps2 |= MMC_CAP2_HS200;
648         return 0;
649 }
650 
651 static const struct sdhci_pci_fixes sdhci_rtsx = {
652         .quirks2        = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
653                         SDHCI_QUIRK2_BROKEN_DDR50,
654         .probe_slot     = rtsx_probe_slot,
655 };
656 
657 static int amd_probe(struct sdhci_pci_chip *chip)
658 {
659         struct pci_dev  *smbus_dev;
660 
661         smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
662                         PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
663 
664         if (smbus_dev && (smbus_dev->revision < 0x51)) {
665                 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
666                 chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
667         }
668 
669         return 0;
670 }
671 
672 static const struct sdhci_pci_fixes sdhci_amd = {
673         .probe          = amd_probe,
674 };
675 
676 static const struct pci_device_id pci_ids[] = {
677         {
678                 .vendor         = PCI_VENDOR_ID_RICOH,
679                 .device         = PCI_DEVICE_ID_RICOH_R5C822,
680                 .subvendor      = PCI_ANY_ID,
681                 .subdevice      = PCI_ANY_ID,
682                 .driver_data    = (kernel_ulong_t)&sdhci_ricoh,
683         },
684 
685         {
686                 .vendor         = PCI_VENDOR_ID_RICOH,
687                 .device         = 0x843,
688                 .subvendor      = PCI_ANY_ID,
689                 .subdevice      = PCI_ANY_ID,
690                 .driver_data    = (kernel_ulong_t)&sdhci_ricoh_mmc,
691         },
692 
693         {
694                 .vendor         = PCI_VENDOR_ID_RICOH,
695                 .device         = 0xe822,
696                 .subvendor      = PCI_ANY_ID,
697                 .subdevice      = PCI_ANY_ID,
698                 .driver_data    = (kernel_ulong_t)&sdhci_ricoh_mmc,
699         },
700 
701         {
702                 .vendor         = PCI_VENDOR_ID_RICOH,
703                 .device         = 0xe823,
704                 .subvendor      = PCI_ANY_ID,
705                 .subdevice      = PCI_ANY_ID,
706                 .driver_data    = (kernel_ulong_t)&sdhci_ricoh_mmc,
707         },
708 
709         {
710                 .vendor         = PCI_VENDOR_ID_ENE,
711                 .device         = PCI_DEVICE_ID_ENE_CB712_SD,
712                 .subvendor      = PCI_ANY_ID,
713                 .subdevice      = PCI_ANY_ID,
714                 .driver_data    = (kernel_ulong_t)&sdhci_ene_712,
715         },
716 
717         {
718                 .vendor         = PCI_VENDOR_ID_ENE,
719                 .device         = PCI_DEVICE_ID_ENE_CB712_SD_2,
720                 .subvendor      = PCI_ANY_ID,
721                 .subdevice      = PCI_ANY_ID,
722                 .driver_data    = (kernel_ulong_t)&sdhci_ene_712,
723         },
724 
725         {
726                 .vendor         = PCI_VENDOR_ID_ENE,
727                 .device         = PCI_DEVICE_ID_ENE_CB714_SD,
728                 .subvendor      = PCI_ANY_ID,
729                 .subdevice      = PCI_ANY_ID,
730                 .driver_data    = (kernel_ulong_t)&sdhci_ene_714,
731         },
732 
733         {
734                 .vendor         = PCI_VENDOR_ID_ENE,
735                 .device         = PCI_DEVICE_ID_ENE_CB714_SD_2,
736                 .subvendor      = PCI_ANY_ID,
737                 .subdevice      = PCI_ANY_ID,
738                 .driver_data    = (kernel_ulong_t)&sdhci_ene_714,
739         },
740 
741         {
742                 .vendor         = PCI_VENDOR_ID_MARVELL,
743                 .device         = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
744                 .subvendor      = PCI_ANY_ID,
745                 .subdevice      = PCI_ANY_ID,
746                 .driver_data    = (kernel_ulong_t)&sdhci_cafe,
747         },
748 
749         {
750                 .vendor         = PCI_VENDOR_ID_JMICRON,
751                 .device         = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
752                 .subvendor      = PCI_ANY_ID,
753                 .subdevice      = PCI_ANY_ID,
754                 .driver_data    = (kernel_ulong_t)&sdhci_jmicron,
755         },
756 
757         {
758                 .vendor         = PCI_VENDOR_ID_JMICRON,
759                 .device         = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
760                 .subvendor      = PCI_ANY_ID,
761                 .subdevice      = PCI_ANY_ID,
762                 .driver_data    = (kernel_ulong_t)&sdhci_jmicron,
763         },
764 
765         {
766                 .vendor         = PCI_VENDOR_ID_JMICRON,
767                 .device         = PCI_DEVICE_ID_JMICRON_JMB388_SD,
768                 .subvendor      = PCI_ANY_ID,
769                 .subdevice      = PCI_ANY_ID,
770                 .driver_data    = (kernel_ulong_t)&sdhci_jmicron,
771         },
772 
773         {
774                 .vendor         = PCI_VENDOR_ID_JMICRON,
775                 .device         = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
776                 .subvendor      = PCI_ANY_ID,
777                 .subdevice      = PCI_ANY_ID,
778                 .driver_data    = (kernel_ulong_t)&sdhci_jmicron,
779         },
780 
781         {
782                 .vendor         = PCI_VENDOR_ID_SYSKONNECT,
783                 .device         = 0x8000,
784                 .subvendor      = PCI_ANY_ID,
785                 .subdevice      = PCI_ANY_ID,
786                 .driver_data    = (kernel_ulong_t)&sdhci_syskt,
787         },
788 
789         {
790                 .vendor         = PCI_VENDOR_ID_VIA,
791                 .device         = 0x95d0,
792                 .subvendor      = PCI_ANY_ID,
793                 .subdevice      = PCI_ANY_ID,
794                 .driver_data    = (kernel_ulong_t)&sdhci_via,
795         },
796 
797         {
798                 .vendor         = PCI_VENDOR_ID_REALTEK,
799                 .device         = 0x5250,
800                 .subvendor      = PCI_ANY_ID,
801                 .subdevice      = PCI_ANY_ID,
802                 .driver_data    = (kernel_ulong_t)&sdhci_rtsx,
803         },
804 
805         {
806                 .vendor         = PCI_VENDOR_ID_INTEL,
807                 .device         = PCI_DEVICE_ID_INTEL_QRK_SD,
808                 .subvendor      = PCI_ANY_ID,
809                 .subdevice      = PCI_ANY_ID,
810                 .driver_data    = (kernel_ulong_t)&sdhci_intel_qrk,
811         },
812 
813         {
814                 .vendor         = PCI_VENDOR_ID_INTEL,
815                 .device         = PCI_DEVICE_ID_INTEL_MRST_SD0,
816                 .subvendor      = PCI_ANY_ID,
817                 .subdevice      = PCI_ANY_ID,
818                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
819         },
820 
821         {
822                 .vendor         = PCI_VENDOR_ID_INTEL,
823                 .device         = PCI_DEVICE_ID_INTEL_MRST_SD1,
824                 .subvendor      = PCI_ANY_ID,
825                 .subdevice      = PCI_ANY_ID,
826                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
827         },
828 
829         {
830                 .vendor         = PCI_VENDOR_ID_INTEL,
831                 .device         = PCI_DEVICE_ID_INTEL_MRST_SD2,
832                 .subvendor      = PCI_ANY_ID,
833                 .subdevice      = PCI_ANY_ID,
834                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
835         },
836 
837         {
838                 .vendor         = PCI_VENDOR_ID_INTEL,
839                 .device         = PCI_DEVICE_ID_INTEL_MFD_SD,
840                 .subvendor      = PCI_ANY_ID,
841                 .subdevice      = PCI_ANY_ID,
842                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mfd_sd,
843         },
844 
845         {
846                 .vendor         = PCI_VENDOR_ID_INTEL,
847                 .device         = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
848                 .subvendor      = PCI_ANY_ID,
849                 .subdevice      = PCI_ANY_ID,
850                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
851         },
852 
853         {
854                 .vendor         = PCI_VENDOR_ID_INTEL,
855                 .device         = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
856                 .subvendor      = PCI_ANY_ID,
857                 .subdevice      = PCI_ANY_ID,
858                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
859         },
860 
861         {
862                 .vendor         = PCI_VENDOR_ID_INTEL,
863                 .device         = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
864                 .subvendor      = PCI_ANY_ID,
865                 .subdevice      = PCI_ANY_ID,
866                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
867         },
868 
869         {
870                 .vendor         = PCI_VENDOR_ID_INTEL,
871                 .device         = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
872                 .subvendor      = PCI_ANY_ID,
873                 .subdevice      = PCI_ANY_ID,
874                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
875         },
876 
877         {
878                 .vendor         = PCI_VENDOR_ID_INTEL,
879                 .device         = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
880                 .subvendor      = PCI_ANY_ID,
881                 .subdevice      = PCI_ANY_ID,
882                 .driver_data    = (kernel_ulong_t)&sdhci_intel_pch_sdio,
883         },
884 
885         {
886                 .vendor         = PCI_VENDOR_ID_INTEL,
887                 .device         = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
888                 .subvendor      = PCI_ANY_ID,
889                 .subdevice      = PCI_ANY_ID,
890                 .driver_data    = (kernel_ulong_t)&sdhci_intel_pch_sdio,
891         },
892 
893         {
894                 .vendor         = PCI_VENDOR_ID_INTEL,
895                 .device         = PCI_DEVICE_ID_INTEL_BYT_EMMC,
896                 .subvendor      = PCI_ANY_ID,
897                 .subdevice      = PCI_ANY_ID,
898                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_emmc,
899         },
900 
901         {
902                 .vendor         = PCI_VENDOR_ID_INTEL,
903                 .device         = PCI_DEVICE_ID_INTEL_BYT_SDIO,
904                 .subvendor      = PCI_ANY_ID,
905                 .subdevice      = PCI_ANY_ID,
906                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_sdio,
907         },
908 
909         {
910                 .vendor         = PCI_VENDOR_ID_INTEL,
911                 .device         = PCI_DEVICE_ID_INTEL_BYT_SD,
912                 .subvendor      = PCI_ANY_ID,
913                 .subdevice      = PCI_ANY_ID,
914                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_sd,
915         },
916 
917         {
918                 .vendor         = PCI_VENDOR_ID_INTEL,
919                 .device         = PCI_DEVICE_ID_INTEL_BYT_EMMC2,
920                 .subvendor      = PCI_ANY_ID,
921                 .subdevice      = PCI_ANY_ID,
922                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_emmc,
923         },
924 
925         {
926                 .vendor         = PCI_VENDOR_ID_INTEL,
927                 .device         = PCI_DEVICE_ID_INTEL_BSW_EMMC,
928                 .subvendor      = PCI_ANY_ID,
929                 .subdevice      = PCI_ANY_ID,
930                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_emmc,
931         },
932 
933         {
934                 .vendor         = PCI_VENDOR_ID_INTEL,
935                 .device         = PCI_DEVICE_ID_INTEL_BSW_SDIO,
936                 .subvendor      = PCI_ANY_ID,
937                 .subdevice      = PCI_ANY_ID,
938                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_sdio,
939         },
940 
941         {
942                 .vendor         = PCI_VENDOR_ID_INTEL,
943                 .device         = PCI_DEVICE_ID_INTEL_BSW_SD,
944                 .subvendor      = PCI_ANY_ID,
945                 .subdevice      = PCI_ANY_ID,
946                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_sd,
947         },
948 
949         {
950                 .vendor         = PCI_VENDOR_ID_INTEL,
951                 .device         = PCI_DEVICE_ID_INTEL_CLV_SDIO0,
952                 .subvendor      = PCI_ANY_ID,
953                 .subdevice      = PCI_ANY_ID,
954                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mfd_sd,
955         },
956 
957         {
958                 .vendor         = PCI_VENDOR_ID_INTEL,
959                 .device         = PCI_DEVICE_ID_INTEL_CLV_SDIO1,
960                 .subvendor      = PCI_ANY_ID,
961                 .subdevice      = PCI_ANY_ID,
962                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
963         },
964 
965         {
966                 .vendor         = PCI_VENDOR_ID_INTEL,
967                 .device         = PCI_DEVICE_ID_INTEL_CLV_SDIO2,
968                 .subvendor      = PCI_ANY_ID,
969                 .subdevice      = PCI_ANY_ID,
970                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
971         },
972 
973         {
974                 .vendor         = PCI_VENDOR_ID_INTEL,
975                 .device         = PCI_DEVICE_ID_INTEL_CLV_EMMC0,
976                 .subvendor      = PCI_ANY_ID,
977                 .subdevice      = PCI_ANY_ID,
978                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
979         },
980 
981         {
982                 .vendor         = PCI_VENDOR_ID_INTEL,
983                 .device         = PCI_DEVICE_ID_INTEL_CLV_EMMC1,
984                 .subvendor      = PCI_ANY_ID,
985                 .subdevice      = PCI_ANY_ID,
986                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
987         },
988 
989         {
990                 .vendor         = PCI_VENDOR_ID_INTEL,
991                 .device         = PCI_DEVICE_ID_INTEL_MRFL_MMC,
992                 .subvendor      = PCI_ANY_ID,
993                 .subdevice      = PCI_ANY_ID,
994                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mrfl_mmc,
995         },
996 
997         {
998                 .vendor         = PCI_VENDOR_ID_INTEL,
999                 .device         = PCI_DEVICE_ID_INTEL_SPT_EMMC,
1000                 .subvendor      = PCI_ANY_ID,
1001                 .subdevice      = PCI_ANY_ID,
1002                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1003         },
1004 
1005         {
1006                 .vendor         = PCI_VENDOR_ID_INTEL,
1007                 .device         = PCI_DEVICE_ID_INTEL_SPT_SDIO,
1008                 .subvendor      = PCI_ANY_ID,
1009                 .subdevice      = PCI_ANY_ID,
1010                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1011         },
1012 
1013         {
1014                 .vendor         = PCI_VENDOR_ID_INTEL,
1015                 .device         = PCI_DEVICE_ID_INTEL_SPT_SD,
1016                 .subvendor      = PCI_ANY_ID,
1017                 .subdevice      = PCI_ANY_ID,
1018                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_sd,
1019         },
1020 
1021         {
1022                 .vendor         = PCI_VENDOR_ID_O2,
1023                 .device         = PCI_DEVICE_ID_O2_8120,
1024                 .subvendor      = PCI_ANY_ID,
1025                 .subdevice      = PCI_ANY_ID,
1026                 .driver_data    = (kernel_ulong_t)&sdhci_o2,
1027         },
1028 
1029         {
1030                 .vendor         = PCI_VENDOR_ID_O2,
1031                 .device         = PCI_DEVICE_ID_O2_8220,
1032                 .subvendor      = PCI_ANY_ID,
1033                 .subdevice      = PCI_ANY_ID,
1034                 .driver_data    = (kernel_ulong_t)&sdhci_o2,
1035         },
1036 
1037         {
1038                 .vendor         = PCI_VENDOR_ID_O2,
1039                 .device         = PCI_DEVICE_ID_O2_8221,
1040                 .subvendor      = PCI_ANY_ID,
1041                 .subdevice      = PCI_ANY_ID,
1042                 .driver_data    = (kernel_ulong_t)&sdhci_o2,
1043         },
1044 
1045         {
1046                 .vendor         = PCI_VENDOR_ID_O2,
1047                 .device         = PCI_DEVICE_ID_O2_8320,
1048                 .subvendor      = PCI_ANY_ID,
1049                 .subdevice      = PCI_ANY_ID,
1050                 .driver_data    = (kernel_ulong_t)&sdhci_o2,
1051         },
1052 
1053         {
1054                 .vendor         = PCI_VENDOR_ID_O2,
1055                 .device         = PCI_DEVICE_ID_O2_8321,
1056                 .subvendor      = PCI_ANY_ID,
1057                 .subdevice      = PCI_ANY_ID,
1058                 .driver_data    = (kernel_ulong_t)&sdhci_o2,
1059         },
1060 
1061         {
1062                 .vendor         = PCI_VENDOR_ID_O2,
1063                 .device         = PCI_DEVICE_ID_O2_FUJIN2,
1064                 .subvendor      = PCI_ANY_ID,
1065                 .subdevice      = PCI_ANY_ID,
1066                 .driver_data    = (kernel_ulong_t)&sdhci_o2,
1067         },
1068 
1069         {
1070                 .vendor         = PCI_VENDOR_ID_O2,
1071                 .device         = PCI_DEVICE_ID_O2_SDS0,
1072                 .subvendor      = PCI_ANY_ID,
1073                 .subdevice      = PCI_ANY_ID,
1074                 .driver_data    = (kernel_ulong_t)&sdhci_o2,
1075         },
1076 
1077         {
1078                 .vendor         = PCI_VENDOR_ID_O2,
1079                 .device         = PCI_DEVICE_ID_O2_SDS1,
1080                 .subvendor      = PCI_ANY_ID,
1081                 .subdevice      = PCI_ANY_ID,
1082                 .driver_data    = (kernel_ulong_t)&sdhci_o2,
1083         },
1084 
1085         {
1086                 .vendor         = PCI_VENDOR_ID_O2,
1087                 .device         = PCI_DEVICE_ID_O2_SEABIRD0,
1088                 .subvendor      = PCI_ANY_ID,
1089                 .subdevice      = PCI_ANY_ID,
1090                 .driver_data    = (kernel_ulong_t)&sdhci_o2,
1091         },
1092 
1093         {
1094                 .vendor         = PCI_VENDOR_ID_O2,
1095                 .device         = PCI_DEVICE_ID_O2_SEABIRD1,
1096                 .subvendor      = PCI_ANY_ID,
1097                 .subdevice      = PCI_ANY_ID,
1098                 .driver_data    = (kernel_ulong_t)&sdhci_o2,
1099         },
1100         {
1101                 .vendor         = PCI_VENDOR_ID_AMD,
1102                 .device         = PCI_ANY_ID,
1103                 .class          = PCI_CLASS_SYSTEM_SDHCI << 8,
1104                 .class_mask     = 0xFFFF00,
1105                 .subvendor      = PCI_ANY_ID,
1106                 .subdevice      = PCI_ANY_ID,
1107                 .driver_data    = (kernel_ulong_t)&sdhci_amd,
1108         },
1109         {       /* Generic SD host controller */
1110                 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
1111         },
1112 
1113         { /* end: all zeroes */ },
1114 };
1115 
1116 MODULE_DEVICE_TABLE(pci, pci_ids);
1117 
1118 /*****************************************************************************\
1119  *                                                                           *
1120  * SDHCI core callbacks                                                      *
1121  *                                                                           *
1122 \*****************************************************************************/
1123 
1124 static int sdhci_pci_enable_dma(struct sdhci_host *host)
1125 {
1126         struct sdhci_pci_slot *slot;
1127         struct pci_dev *pdev;
1128         int ret = -1;
1129 
1130         slot = sdhci_priv(host);
1131         pdev = slot->chip->pdev;
1132 
1133         if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1134                 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1135                 (host->flags & SDHCI_USE_SDMA)) {
1136                 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1137                         "doesn't fully claim to support it.\n");
1138         }
1139 
1140         if (host->flags & SDHCI_USE_64_BIT_DMA) {
1141                 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) {
1142                         host->flags &= ~SDHCI_USE_64_BIT_DMA;
1143                 } else {
1144                         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1145                         if (ret)
1146                                 dev_warn(&pdev->dev, "Failed to set 64-bit DMA mask\n");
1147                 }
1148         }
1149         if (ret)
1150                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1151         if (ret)
1152                 return ret;
1153 
1154         pci_set_master(pdev);
1155 
1156         return 0;
1157 }
1158 
1159 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width)
1160 {
1161         u8 ctrl;
1162 
1163         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1164 
1165         switch (width) {
1166         case MMC_BUS_WIDTH_8:
1167                 ctrl |= SDHCI_CTRL_8BITBUS;
1168                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1169                 break;
1170         case MMC_BUS_WIDTH_4:
1171                 ctrl |= SDHCI_CTRL_4BITBUS;
1172                 ctrl &= ~SDHCI_CTRL_8BITBUS;
1173                 break;
1174         default:
1175                 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
1176                 break;
1177         }
1178 
1179         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1180 }
1181 
1182 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1183 {
1184         struct sdhci_pci_slot *slot = sdhci_priv(host);
1185         int rst_n_gpio = slot->rst_n_gpio;
1186 
1187         if (!gpio_is_valid(rst_n_gpio))
1188                 return;
1189         gpio_set_value_cansleep(rst_n_gpio, 0);
1190         /* For eMMC, minimum is 1us but give it 10us for good measure */
1191         udelay(10);
1192         gpio_set_value_cansleep(rst_n_gpio, 1);
1193         /* For eMMC, minimum is 200us but give it 300us for good measure */
1194         usleep_range(300, 1000);
1195 }
1196 
1197 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1198 {
1199         struct sdhci_pci_slot *slot = sdhci_priv(host);
1200 
1201         if (slot->hw_reset)
1202                 slot->hw_reset(host);
1203 }
1204 
1205 static const struct sdhci_ops sdhci_pci_ops = {
1206         .set_clock      = sdhci_set_clock,
1207         .enable_dma     = sdhci_pci_enable_dma,
1208         .set_bus_width  = sdhci_pci_set_bus_width,
1209         .reset          = sdhci_reset,
1210         .set_uhs_signaling = sdhci_set_uhs_signaling,
1211         .hw_reset               = sdhci_pci_hw_reset,
1212 };
1213 
1214 /*****************************************************************************\
1215  *                                                                           *
1216  * Suspend/resume                                                            *
1217  *                                                                           *
1218 \*****************************************************************************/
1219 
1220 #ifdef CONFIG_PM
1221 
1222 static int sdhci_pci_suspend(struct device *dev)
1223 {
1224         struct pci_dev *pdev = to_pci_dev(dev);
1225         struct sdhci_pci_chip *chip;
1226         struct sdhci_pci_slot *slot;
1227         mmc_pm_flag_t slot_pm_flags;
1228         mmc_pm_flag_t pm_flags = 0;
1229         int i, ret;
1230 
1231         chip = pci_get_drvdata(pdev);
1232         if (!chip)
1233                 return 0;
1234 
1235         for (i = 0; i < chip->num_slots; i++) {
1236                 slot = chip->slots[i];
1237                 if (!slot)
1238                         continue;
1239 
1240                 ret = sdhci_suspend_host(slot->host);
1241 
1242                 if (ret)
1243                         goto err_pci_suspend;
1244 
1245                 slot_pm_flags = slot->host->mmc->pm_flags;
1246                 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1247                         sdhci_enable_irq_wakeups(slot->host);
1248 
1249                 pm_flags |= slot_pm_flags;
1250         }
1251 
1252         if (chip->fixes && chip->fixes->suspend) {
1253                 ret = chip->fixes->suspend(chip);
1254                 if (ret)
1255                         goto err_pci_suspend;
1256         }
1257 
1258         if (pm_flags & MMC_PM_KEEP_POWER) {
1259                 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1260                         device_init_wakeup(dev, true);
1261                 else
1262                         device_init_wakeup(dev, false);
1263         } else
1264                 device_init_wakeup(dev, false);
1265 
1266         return 0;
1267 
1268 err_pci_suspend:
1269         while (--i >= 0)
1270                 sdhci_resume_host(chip->slots[i]->host);
1271         return ret;
1272 }
1273 
1274 static int sdhci_pci_resume(struct device *dev)
1275 {
1276         struct pci_dev *pdev = to_pci_dev(dev);
1277         struct sdhci_pci_chip *chip;
1278         struct sdhci_pci_slot *slot;
1279         int i, ret;
1280 
1281         chip = pci_get_drvdata(pdev);
1282         if (!chip)
1283                 return 0;
1284 
1285         if (chip->fixes && chip->fixes->resume) {
1286                 ret = chip->fixes->resume(chip);
1287                 if (ret)
1288                         return ret;
1289         }
1290 
1291         for (i = 0; i < chip->num_slots; i++) {
1292                 slot = chip->slots[i];
1293                 if (!slot)
1294                         continue;
1295 
1296                 ret = sdhci_resume_host(slot->host);
1297                 if (ret)
1298                         return ret;
1299         }
1300 
1301         return 0;
1302 }
1303 
1304 static int sdhci_pci_runtime_suspend(struct device *dev)
1305 {
1306         struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1307         struct sdhci_pci_chip *chip;
1308         struct sdhci_pci_slot *slot;
1309         int i, ret;
1310 
1311         chip = pci_get_drvdata(pdev);
1312         if (!chip)
1313                 return 0;
1314 
1315         for (i = 0; i < chip->num_slots; i++) {
1316                 slot = chip->slots[i];
1317                 if (!slot)
1318                         continue;
1319 
1320                 ret = sdhci_runtime_suspend_host(slot->host);
1321 
1322                 if (ret)
1323                         goto err_pci_runtime_suspend;
1324         }
1325 
1326         if (chip->fixes && chip->fixes->suspend) {
1327                 ret = chip->fixes->suspend(chip);
1328                 if (ret)
1329                         goto err_pci_runtime_suspend;
1330         }
1331 
1332         return 0;
1333 
1334 err_pci_runtime_suspend:
1335         while (--i >= 0)
1336                 sdhci_runtime_resume_host(chip->slots[i]->host);
1337         return ret;
1338 }
1339 
1340 static int sdhci_pci_runtime_resume(struct device *dev)
1341 {
1342         struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1343         struct sdhci_pci_chip *chip;
1344         struct sdhci_pci_slot *slot;
1345         int i, ret;
1346 
1347         chip = pci_get_drvdata(pdev);
1348         if (!chip)
1349                 return 0;
1350 
1351         if (chip->fixes && chip->fixes->resume) {
1352                 ret = chip->fixes->resume(chip);
1353                 if (ret)
1354                         return ret;
1355         }
1356 
1357         for (i = 0; i < chip->num_slots; i++) {
1358                 slot = chip->slots[i];
1359                 if (!slot)
1360                         continue;
1361 
1362                 ret = sdhci_runtime_resume_host(slot->host);
1363                 if (ret)
1364                         return ret;
1365         }
1366 
1367         return 0;
1368 }
1369 
1370 #else /* CONFIG_PM */
1371 
1372 #define sdhci_pci_suspend NULL
1373 #define sdhci_pci_resume NULL
1374 
1375 #endif /* CONFIG_PM */
1376 
1377 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1378         .suspend = sdhci_pci_suspend,
1379         .resume = sdhci_pci_resume,
1380         SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1381                         sdhci_pci_runtime_resume, NULL)
1382 };
1383 
1384 /*****************************************************************************\
1385  *                                                                           *
1386  * Device probing/removal                                                    *
1387  *                                                                           *
1388 \*****************************************************************************/
1389 
1390 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1391         struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1392         int slotno)
1393 {
1394         struct sdhci_pci_slot *slot;
1395         struct sdhci_host *host;
1396         int ret, bar = first_bar + slotno;
1397 
1398         if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1399                 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1400                 return ERR_PTR(-ENODEV);
1401         }
1402 
1403         if (pci_resource_len(pdev, bar) < 0x100) {
1404                 dev_err(&pdev->dev, "Invalid iomem size. You may "
1405                         "experience problems.\n");
1406         }
1407 
1408         if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1409                 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1410                 return ERR_PTR(-ENODEV);
1411         }
1412 
1413         if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1414                 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1415                 return ERR_PTR(-ENODEV);
1416         }
1417 
1418         host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1419         if (IS_ERR(host)) {
1420                 dev_err(&pdev->dev, "cannot allocate host\n");
1421                 return ERR_CAST(host);
1422         }
1423 
1424         slot = sdhci_priv(host);
1425 
1426         slot->chip = chip;
1427         slot->host = host;
1428         slot->pci_bar = bar;
1429         slot->rst_n_gpio = -EINVAL;
1430         slot->cd_gpio = -EINVAL;
1431         slot->cd_idx = -1;
1432 
1433         /* Retrieve platform data if there is any */
1434         if (*sdhci_pci_get_data)
1435                 slot->data = sdhci_pci_get_data(pdev, slotno);
1436 
1437         if (slot->data) {
1438                 if (slot->data->setup) {
1439                         ret = slot->data->setup(slot->data);
1440                         if (ret) {
1441                                 dev_err(&pdev->dev, "platform setup failed\n");
1442                                 goto free;
1443                         }
1444                 }
1445                 slot->rst_n_gpio = slot->data->rst_n_gpio;
1446                 slot->cd_gpio = slot->data->cd_gpio;
1447         }
1448 
1449         host->hw_name = "PCI";
1450         host->ops = &sdhci_pci_ops;
1451         host->quirks = chip->quirks;
1452         host->quirks2 = chip->quirks2;
1453 
1454         host->irq = pdev->irq;
1455 
1456         ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1457         if (ret) {
1458                 dev_err(&pdev->dev, "cannot request region\n");
1459                 goto cleanup;
1460         }
1461 
1462         host->ioaddr = pci_ioremap_bar(pdev, bar);
1463         if (!host->ioaddr) {
1464                 dev_err(&pdev->dev, "failed to remap registers\n");
1465                 ret = -ENOMEM;
1466                 goto release;
1467         }
1468 
1469         if (chip->fixes && chip->fixes->probe_slot) {
1470                 ret = chip->fixes->probe_slot(slot);
1471                 if (ret)
1472                         goto unmap;
1473         }
1474 
1475         if (gpio_is_valid(slot->rst_n_gpio)) {
1476                 if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) {
1477                         gpio_direction_output(slot->rst_n_gpio, 1);
1478                         slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1479                         slot->hw_reset = sdhci_pci_gpio_hw_reset;
1480                 } else {
1481                         dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1482                         slot->rst_n_gpio = -EINVAL;
1483                 }
1484         }
1485 
1486         host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1487         host->mmc->slotno = slotno;
1488         host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1489 
1490         if (slot->cd_idx >= 0 &&
1491             mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx,
1492                                  slot->cd_override_level, 0, NULL)) {
1493                 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1494                 slot->cd_idx = -1;
1495         }
1496 
1497         ret = sdhci_add_host(host);
1498         if (ret)
1499                 goto remove;
1500 
1501         sdhci_pci_add_own_cd(slot);
1502 
1503         /*
1504          * Check if the chip needs a separate GPIO for card detect to wake up
1505          * from runtime suspend.  If it is not there, don't allow runtime PM.
1506          * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1507          */
1508         if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1509             !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
1510                 chip->allow_runtime_pm = false;
1511 
1512         return slot;
1513 
1514 remove:
1515         if (gpio_is_valid(slot->rst_n_gpio))
1516                 gpio_free(slot->rst_n_gpio);
1517 
1518         if (chip->fixes && chip->fixes->remove_slot)
1519                 chip->fixes->remove_slot(slot, 0);
1520 
1521 unmap:
1522         iounmap(host->ioaddr);
1523 
1524 release:
1525         pci_release_region(pdev, bar);
1526 
1527 cleanup:
1528         if (slot->data && slot->data->cleanup)
1529                 slot->data->cleanup(slot->data);
1530 
1531 free:
1532         sdhci_free_host(host);
1533 
1534         return ERR_PTR(ret);
1535 }
1536 
1537 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1538 {
1539         int dead;
1540         u32 scratch;
1541 
1542         sdhci_pci_remove_own_cd(slot);
1543 
1544         dead = 0;
1545         scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1546         if (scratch == (u32)-1)
1547                 dead = 1;
1548 
1549         sdhci_remove_host(slot->host, dead);
1550 
1551         if (gpio_is_valid(slot->rst_n_gpio))
1552                 gpio_free(slot->rst_n_gpio);
1553 
1554         if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1555                 slot->chip->fixes->remove_slot(slot, dead);
1556 
1557         if (slot->data && slot->data->cleanup)
1558                 slot->data->cleanup(slot->data);
1559 
1560         pci_release_region(slot->chip->pdev, slot->pci_bar);
1561 
1562         sdhci_free_host(slot->host);
1563 }
1564 
1565 static void sdhci_pci_runtime_pm_allow(struct device *dev)
1566 {
1567         pm_runtime_put_noidle(dev);
1568         pm_runtime_allow(dev);
1569         pm_runtime_set_autosuspend_delay(dev, 50);
1570         pm_runtime_use_autosuspend(dev);
1571         pm_suspend_ignore_children(dev, 1);
1572 }
1573 
1574 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1575 {
1576         pm_runtime_forbid(dev);
1577         pm_runtime_get_noresume(dev);
1578 }
1579 
1580 static int sdhci_pci_probe(struct pci_dev *pdev,
1581                                      const struct pci_device_id *ent)
1582 {
1583         struct sdhci_pci_chip *chip;
1584         struct sdhci_pci_slot *slot;
1585 
1586         u8 slots, first_bar;
1587         int ret, i;
1588 
1589         BUG_ON(pdev == NULL);
1590         BUG_ON(ent == NULL);
1591 
1592         dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1593                  (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1594 
1595         ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1596         if (ret)
1597                 return ret;
1598 
1599         slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1600         dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1601         if (slots == 0)
1602                 return -ENODEV;
1603 
1604         BUG_ON(slots > MAX_SLOTS);
1605 
1606         ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1607         if (ret)
1608                 return ret;
1609 
1610         first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1611 
1612         if (first_bar > 5) {
1613                 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1614                 return -ENODEV;
1615         }
1616 
1617         ret = pci_enable_device(pdev);
1618         if (ret)
1619                 return ret;
1620 
1621         chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1622         if (!chip) {
1623                 ret = -ENOMEM;
1624                 goto err;
1625         }
1626 
1627         chip->pdev = pdev;
1628         chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1629         if (chip->fixes) {
1630                 chip->quirks = chip->fixes->quirks;
1631                 chip->quirks2 = chip->fixes->quirks2;
1632                 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1633         }
1634         chip->num_slots = slots;
1635 
1636         pci_set_drvdata(pdev, chip);
1637 
1638         if (chip->fixes && chip->fixes->probe) {
1639                 ret = chip->fixes->probe(chip);
1640                 if (ret)
1641                         goto free;
1642         }
1643 
1644         slots = chip->num_slots;        /* Quirk may have changed this */
1645 
1646         for (i = 0; i < slots; i++) {
1647                 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1648                 if (IS_ERR(slot)) {
1649                         for (i--; i >= 0; i--)
1650                                 sdhci_pci_remove_slot(chip->slots[i]);
1651                         ret = PTR_ERR(slot);
1652                         goto free;
1653                 }
1654 
1655                 chip->slots[i] = slot;
1656         }
1657 
1658         if (chip->allow_runtime_pm)
1659                 sdhci_pci_runtime_pm_allow(&pdev->dev);
1660 
1661         return 0;
1662 
1663 free:
1664         pci_set_drvdata(pdev, NULL);
1665         kfree(chip);
1666 
1667 err:
1668         pci_disable_device(pdev);
1669         return ret;
1670 }
1671 
1672 static void sdhci_pci_remove(struct pci_dev *pdev)
1673 {
1674         int i;
1675         struct sdhci_pci_chip *chip;
1676 
1677         chip = pci_get_drvdata(pdev);
1678 
1679         if (chip) {
1680                 if (chip->allow_runtime_pm)
1681                         sdhci_pci_runtime_pm_forbid(&pdev->dev);
1682 
1683                 for (i = 0; i < chip->num_slots; i++)
1684                         sdhci_pci_remove_slot(chip->slots[i]);
1685 
1686                 pci_set_drvdata(pdev, NULL);
1687                 kfree(chip);
1688         }
1689 
1690         pci_disable_device(pdev);
1691 }
1692 
1693 static struct pci_driver sdhci_driver = {
1694         .name =         "sdhci-pci",
1695         .id_table =     pci_ids,
1696         .probe =        sdhci_pci_probe,
1697         .remove =       sdhci_pci_remove,
1698         .driver =       {
1699                 .pm =   &sdhci_pci_pm_ops
1700         },
1701 };
1702 
1703 module_pci_driver(sdhci_driver);
1704 
1705 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1706 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1707 MODULE_LICENSE("GPL");
1708 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us