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Linux/drivers/mmc/host/sdhci-of-esdhc.c

  1 /*
  2  * Freescale eSDHC controller driver.
  3  *
  4  * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc.
  5  * Copyright (c) 2009 MontaVista Software, Inc.
  6  *
  7  * Authors: Xiaobo Xie <X.Xie@freescale.com>
  8  *          Anton Vorontsov <avorontsov@ru.mvista.com>
  9  *
 10  * This program is free software; you can redistribute it and/or modify
 11  * it under the terms of the GNU General Public License as published by
 12  * the Free Software Foundation; either version 2 of the License, or (at
 13  * your option) any later version.
 14  */
 15 
 16 #include <linux/err.h>
 17 #include <linux/io.h>
 18 #include <linux/of.h>
 19 #include <linux/delay.h>
 20 #include <linux/module.h>
 21 #include <linux/mmc/host.h>
 22 #include "sdhci-pltfm.h"
 23 #include "sdhci-esdhc.h"
 24 
 25 #define VENDOR_V_22     0x12
 26 #define VENDOR_V_23     0x13
 27 static u32 esdhc_readl(struct sdhci_host *host, int reg)
 28 {
 29         u32 ret;
 30 
 31         ret = in_be32(host->ioaddr + reg);
 32         /*
 33          * The bit of ADMA flag in eSDHC is not compatible with standard
 34          * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is
 35          * supported by eSDHC.
 36          * And for many FSL eSDHC controller, the reset value of field
 37          * SDHCI_CAN_DO_ADMA1 is one, but some of them can't support ADMA,
 38          * only these vendor version is greater than 2.2/0x12 support ADMA.
 39          * For FSL eSDHC, must aligned 4-byte, so use 0xFC to read the
 40          * the verdor version number, oxFE is SDHCI_HOST_VERSION.
 41          */
 42         if ((reg == SDHCI_CAPABILITIES) && (ret & SDHCI_CAN_DO_ADMA1)) {
 43                 u32 tmp = in_be32(host->ioaddr + SDHCI_SLOT_INT_STATUS);
 44                 tmp = (tmp & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT;
 45                 if (tmp > VENDOR_V_22)
 46                         ret |= SDHCI_CAN_DO_ADMA2;
 47         }
 48 
 49         return ret;
 50 }
 51 
 52 static u16 esdhc_readw(struct sdhci_host *host, int reg)
 53 {
 54         u16 ret;
 55         int base = reg & ~0x3;
 56         int shift = (reg & 0x2) * 8;
 57 
 58         if (unlikely(reg == SDHCI_HOST_VERSION))
 59                 ret = in_be32(host->ioaddr + base) & 0xffff;
 60         else
 61                 ret = (in_be32(host->ioaddr + base) >> shift) & 0xffff;
 62         return ret;
 63 }
 64 
 65 static u8 esdhc_readb(struct sdhci_host *host, int reg)
 66 {
 67         int base = reg & ~0x3;
 68         int shift = (reg & 0x3) * 8;
 69         u8 ret = (in_be32(host->ioaddr + base) >> shift) & 0xff;
 70 
 71         /*
 72          * "DMA select" locates at offset 0x28 in SD specification, but on
 73          * P5020 or P3041, it locates at 0x29.
 74          */
 75         if (reg == SDHCI_HOST_CONTROL) {
 76                 u32 dma_bits;
 77 
 78                 dma_bits = in_be32(host->ioaddr + reg);
 79                 /* DMA select is 22,23 bits in Protocol Control Register */
 80                 dma_bits = (dma_bits >> 5) & SDHCI_CTRL_DMA_MASK;
 81 
 82                 /* fixup the result */
 83                 ret &= ~SDHCI_CTRL_DMA_MASK;
 84                 ret |= dma_bits;
 85         }
 86 
 87         return ret;
 88 }
 89 
 90 static void esdhc_writel(struct sdhci_host *host, u32 val, int reg)
 91 {
 92         /*
 93          * Enable IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE]
 94          * when SYSCTL[RSTD]) is set for some special operations.
 95          * No any impact other operation.
 96          */
 97         if (reg == SDHCI_INT_ENABLE)
 98                 val |= SDHCI_INT_BLK_GAP;
 99         sdhci_be32bs_writel(host, val, reg);
100 }
101 
102 static void esdhc_writew(struct sdhci_host *host, u16 val, int reg)
103 {
104         if (reg == SDHCI_BLOCK_SIZE) {
105                 /*
106                  * Two last DMA bits are reserved, and first one is used for
107                  * non-standard blksz of 4096 bytes that we don't support
108                  * yet. So clear the DMA boundary bits.
109                  */
110                 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
111         }
112         sdhci_be32bs_writew(host, val, reg);
113 }
114 
115 static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)
116 {
117         /*
118          * "DMA select" location is offset 0x28 in SD specification, but on
119          * P5020 or P3041, it's located at 0x29.
120          */
121         if (reg == SDHCI_HOST_CONTROL) {
122                 u32 dma_bits;
123 
124                 /*
125                  * If host control register is not standard, exit
126                  * this function
127                  */
128                 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL)
129                         return;
130 
131                 /* DMA select is 22,23 bits in Protocol Control Register */
132                 dma_bits = (val & SDHCI_CTRL_DMA_MASK) << 5;
133                 clrsetbits_be32(host->ioaddr + reg , SDHCI_CTRL_DMA_MASK << 5,
134                         dma_bits);
135                 val &= ~SDHCI_CTRL_DMA_MASK;
136                 val |= in_be32(host->ioaddr + reg) & SDHCI_CTRL_DMA_MASK;
137         }
138 
139         /* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */
140         if (reg == SDHCI_HOST_CONTROL)
141                 val &= ~ESDHC_HOST_CONTROL_RES;
142         sdhci_be32bs_writeb(host, val, reg);
143 }
144 
145 /*
146  * For Abort or Suspend after Stop at Block Gap, ignore the ADMA
147  * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC])
148  * and Block Gap Event(IRQSTAT[BGE]) are also set.
149  * For Continue, apply soft reset for data(SYSCTL[RSTD]);
150  * and re-issue the entire read transaction from beginning.
151  */
152 static void esdhci_of_adma_workaround(struct sdhci_host *host, u32 intmask)
153 {
154         u32 tmp;
155         bool applicable;
156         dma_addr_t dmastart;
157         dma_addr_t dmanow;
158 
159         tmp = in_be32(host->ioaddr + SDHCI_SLOT_INT_STATUS);
160         tmp = (tmp & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT;
161 
162         applicable = (intmask & SDHCI_INT_DATA_END) &&
163                 (intmask & SDHCI_INT_BLK_GAP) &&
164                 (tmp == VENDOR_V_23);
165         if (!applicable)
166                 return;
167 
168         host->data->error = 0;
169         dmastart = sg_dma_address(host->data->sg);
170         dmanow = dmastart + host->data->bytes_xfered;
171         /*
172          * Force update to the next DMA block boundary.
173          */
174         dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
175                 SDHCI_DEFAULT_BOUNDARY_SIZE;
176         host->data->bytes_xfered = dmanow - dmastart;
177         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
178 }
179 
180 static int esdhc_of_enable_dma(struct sdhci_host *host)
181 {
182         setbits32(host->ioaddr + ESDHC_DMA_SYSCTL, ESDHC_DMA_SNOOP);
183         return 0;
184 }
185 
186 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
187 {
188         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
189 
190         return pltfm_host->clock;
191 }
192 
193 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
194 {
195         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
196 
197         return pltfm_host->clock / 256 / 16;
198 }
199 
200 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
201 {
202 
203         int pre_div = 2;
204         int div = 1;
205         u32 temp;
206 
207         if (clock == 0)
208                 goto out;
209 
210         /* Workaround to reduce the clock frequency for p1010 esdhc */
211         if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) {
212                 if (clock > 20000000)
213                         clock -= 5000000;
214                 if (clock > 40000000)
215                         clock -= 5000000;
216         }
217 
218         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
219         temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
220                 | ESDHC_CLOCK_MASK);
221         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
222 
223         while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
224                 pre_div *= 2;
225 
226         while (host->max_clk / pre_div / div > clock && div < 16)
227                 div++;
228 
229         dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
230                 clock, host->max_clk / pre_div / div);
231 
232         pre_div >>= 1;
233         div--;
234 
235         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
236         temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
237                 | (div << ESDHC_DIVIDER_SHIFT)
238                 | (pre_div << ESDHC_PREDIV_SHIFT));
239         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
240         mdelay(1);
241 out:
242         host->clock = clock;
243 }
244 
245 #ifdef CONFIG_PM
246 static u32 esdhc_proctl;
247 static void esdhc_of_suspend(struct sdhci_host *host)
248 {
249         esdhc_proctl = sdhci_be32bs_readl(host, SDHCI_HOST_CONTROL);
250 }
251 
252 static void esdhc_of_resume(struct sdhci_host *host)
253 {
254         esdhc_of_enable_dma(host);
255         sdhci_be32bs_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
256 }
257 #endif
258 
259 static void esdhc_of_platform_init(struct sdhci_host *host)
260 {
261         u32 vvn;
262 
263         vvn = in_be32(host->ioaddr + SDHCI_SLOT_INT_STATUS);
264         vvn = (vvn & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT;
265         if (vvn == VENDOR_V_22)
266                 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
267 
268         if (vvn > VENDOR_V_22)
269                 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
270 }
271 
272 static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width)
273 {
274         u32 ctrl;
275 
276         switch (width) {
277         case MMC_BUS_WIDTH_8:
278                 ctrl = ESDHC_CTRL_8BITBUS;
279                 break;
280 
281         case MMC_BUS_WIDTH_4:
282                 ctrl = ESDHC_CTRL_4BITBUS;
283                 break;
284 
285         default:
286                 ctrl = 0;
287                 break;
288         }
289 
290         clrsetbits_be32(host->ioaddr + SDHCI_HOST_CONTROL,
291                         ESDHC_CTRL_BUSWIDTH_MASK, ctrl);
292 
293         return 0;
294 }
295 
296 static const struct sdhci_ops sdhci_esdhc_ops = {
297         .read_l = esdhc_readl,
298         .read_w = esdhc_readw,
299         .read_b = esdhc_readb,
300         .write_l = esdhc_writel,
301         .write_w = esdhc_writew,
302         .write_b = esdhc_writeb,
303         .set_clock = esdhc_of_set_clock,
304         .enable_dma = esdhc_of_enable_dma,
305         .get_max_clock = esdhc_of_get_max_clock,
306         .get_min_clock = esdhc_of_get_min_clock,
307         .platform_init = esdhc_of_platform_init,
308 #ifdef CONFIG_PM
309         .platform_suspend = esdhc_of_suspend,
310         .platform_resume = esdhc_of_resume,
311 #endif
312         .adma_workaround = esdhci_of_adma_workaround,
313         .platform_bus_width = esdhc_pltfm_bus_width,
314 };
315 
316 static const struct sdhci_pltfm_data sdhci_esdhc_pdata = {
317         /*
318          * card detection could be handled via GPIO
319          * eSDHC cannot support End Attribute in NOP ADMA descriptor
320          */
321         .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_CARD_DETECTION
322                 | SDHCI_QUIRK_NO_CARD_NO_RESET
323                 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
324         .ops = &sdhci_esdhc_ops,
325 };
326 
327 static int sdhci_esdhc_probe(struct platform_device *pdev)
328 {
329         struct sdhci_host *host;
330         struct device_node *np;
331         int ret;
332 
333         host = sdhci_pltfm_init(pdev, &sdhci_esdhc_pdata, 0);
334         if (IS_ERR(host))
335                 return PTR_ERR(host);
336 
337         sdhci_get_of_property(pdev);
338 
339         np = pdev->dev.of_node;
340         if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {
341                 /*
342                  * Freescale messed up with P2020 as it has a non-standard
343                  * host control register
344                  */
345                 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL;
346         }
347 
348         /* call to generic mmc_of_parse to support additional capabilities */
349         mmc_of_parse(host->mmc);
350         mmc_of_parse_voltage(np, &host->ocr_mask);
351 
352         ret = sdhci_add_host(host);
353         if (ret)
354                 sdhci_pltfm_free(pdev);
355 
356         return ret;
357 }
358 
359 static int sdhci_esdhc_remove(struct platform_device *pdev)
360 {
361         return sdhci_pltfm_unregister(pdev);
362 }
363 
364 static const struct of_device_id sdhci_esdhc_of_match[] = {
365         { .compatible = "fsl,mpc8379-esdhc" },
366         { .compatible = "fsl,mpc8536-esdhc" },
367         { .compatible = "fsl,esdhc" },
368         { }
369 };
370 MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match);
371 
372 static struct platform_driver sdhci_esdhc_driver = {
373         .driver = {
374                 .name = "sdhci-esdhc",
375                 .owner = THIS_MODULE,
376                 .of_match_table = sdhci_esdhc_of_match,
377                 .pm = SDHCI_PLTFM_PMOPS,
378         },
379         .probe = sdhci_esdhc_probe,
380         .remove = sdhci_esdhc_remove,
381 };
382 
383 module_platform_driver(sdhci_esdhc_driver);
384 
385 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC");
386 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, "
387               "Anton Vorontsov <avorontsov@ru.mvista.com>");
388 MODULE_LICENSE("GPL v2");
389 

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