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Linux/drivers/mmc/host/sdhci-of-esdhc.c

  1 /*
  2  * Freescale eSDHC controller driver.
  3  *
  4  * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc.
  5  * Copyright (c) 2009 MontaVista Software, Inc.
  6  *
  7  * Authors: Xiaobo Xie <X.Xie@freescale.com>
  8  *          Anton Vorontsov <avorontsov@ru.mvista.com>
  9  *
 10  * This program is free software; you can redistribute it and/or modify
 11  * it under the terms of the GNU General Public License as published by
 12  * the Free Software Foundation; either version 2 of the License, or (at
 13  * your option) any later version.
 14  */
 15 
 16 #include <linux/err.h>
 17 #include <linux/io.h>
 18 #include <linux/of.h>
 19 #include <linux/delay.h>
 20 #include <linux/module.h>
 21 #include <linux/mmc/host.h>
 22 #include "sdhci-pltfm.h"
 23 #include "sdhci-esdhc.h"
 24 
 25 #define VENDOR_V_22     0x12
 26 #define VENDOR_V_23     0x13
 27 
 28 struct sdhci_esdhc {
 29         u8 vendor_ver;
 30         u8 spec_ver;
 31 };
 32 
 33 /**
 34  * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register
 35  *                     to make it compatible with SD spec.
 36  *
 37  * @host: pointer to sdhci_host
 38  * @spec_reg: SD spec register address
 39  * @value: 32bit eSDHC register value on spec_reg address
 40  *
 41  * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
 42  * registers are 32 bits. There are differences in register size, register
 43  * address, register function, bit position and function between eSDHC spec
 44  * and SD spec.
 45  *
 46  * Return a fixed up register value
 47  */
 48 static u32 esdhc_readl_fixup(struct sdhci_host *host,
 49                                      int spec_reg, u32 value)
 50 {
 51         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 52         struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
 53         u32 ret;
 54 
 55         /*
 56          * The bit of ADMA flag in eSDHC is not compatible with standard
 57          * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is
 58          * supported by eSDHC.
 59          * And for many FSL eSDHC controller, the reset value of field
 60          * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA,
 61          * only these vendor version is greater than 2.2/0x12 support ADMA.
 62          */
 63         if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) {
 64                 if (esdhc->vendor_ver > VENDOR_V_22) {
 65                         ret = value | SDHCI_CAN_DO_ADMA2;
 66                         return ret;
 67                 }
 68         }
 69         /*
 70          * The DAT[3:0] line signal levels and the CMD line signal level are
 71          * not compatible with standard SDHC register. The line signal levels
 72          * DAT[7:0] are at bits 31:24 and the command line signal level is at
 73          * bit 23. All other bits are the same as in the standard SDHC
 74          * register.
 75          */
 76         if (spec_reg == SDHCI_PRESENT_STATE) {
 77                 ret = value & 0x000fffff;
 78                 ret |= (value >> 4) & SDHCI_DATA_LVL_MASK;
 79                 ret |= (value << 1) & SDHCI_CMD_LVL;
 80                 return ret;
 81         }
 82 
 83         ret = value;
 84         return ret;
 85 }
 86 
 87 static u16 esdhc_readw_fixup(struct sdhci_host *host,
 88                                      int spec_reg, u32 value)
 89 {
 90         u16 ret;
 91         int shift = (spec_reg & 0x2) * 8;
 92 
 93         if (spec_reg == SDHCI_HOST_VERSION)
 94                 ret = value & 0xffff;
 95         else
 96                 ret = (value >> shift) & 0xffff;
 97         return ret;
 98 }
 99 
100 static u8 esdhc_readb_fixup(struct sdhci_host *host,
101                                      int spec_reg, u32 value)
102 {
103         u8 ret;
104         u8 dma_bits;
105         int shift = (spec_reg & 0x3) * 8;
106 
107         ret = (value >> shift) & 0xff;
108 
109         /*
110          * "DMA select" locates at offset 0x28 in SD specification, but on
111          * P5020 or P3041, it locates at 0x29.
112          */
113         if (spec_reg == SDHCI_HOST_CONTROL) {
114                 /* DMA select is 22,23 bits in Protocol Control Register */
115                 dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK;
116                 /* fixup the result */
117                 ret &= ~SDHCI_CTRL_DMA_MASK;
118                 ret |= dma_bits;
119         }
120         return ret;
121 }
122 
123 /**
124  * esdhc_write*_fixup - Fixup the SD spec register value so that it could be
125  *                      written into eSDHC register.
126  *
127  * @host: pointer to sdhci_host
128  * @spec_reg: SD spec register address
129  * @value: 8/16/32bit SD spec register value that would be written
130  * @old_value: 32bit eSDHC register value on spec_reg address
131  *
132  * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
133  * registers are 32 bits. There are differences in register size, register
134  * address, register function, bit position and function between eSDHC spec
135  * and SD spec.
136  *
137  * Return a fixed up register value
138  */
139 static u32 esdhc_writel_fixup(struct sdhci_host *host,
140                                      int spec_reg, u32 value, u32 old_value)
141 {
142         u32 ret;
143 
144         /*
145          * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE]
146          * when SYSCTL[RSTD] is set for some special operations.
147          * No any impact on other operation.
148          */
149         if (spec_reg == SDHCI_INT_ENABLE)
150                 ret = value | SDHCI_INT_BLK_GAP;
151         else
152                 ret = value;
153 
154         return ret;
155 }
156 
157 static u32 esdhc_writew_fixup(struct sdhci_host *host,
158                                      int spec_reg, u16 value, u32 old_value)
159 {
160         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
161         int shift = (spec_reg & 0x2) * 8;
162         u32 ret;
163 
164         switch (spec_reg) {
165         case SDHCI_TRANSFER_MODE:
166                 /*
167                  * Postpone this write, we must do it together with a
168                  * command write that is down below. Return old value.
169                  */
170                 pltfm_host->xfer_mode_shadow = value;
171                 return old_value;
172         case SDHCI_COMMAND:
173                 ret = (value << 16) | pltfm_host->xfer_mode_shadow;
174                 return ret;
175         }
176 
177         ret = old_value & (~(0xffff << shift));
178         ret |= (value << shift);
179 
180         if (spec_reg == SDHCI_BLOCK_SIZE) {
181                 /*
182                  * Two last DMA bits are reserved, and first one is used for
183                  * non-standard blksz of 4096 bytes that we don't support
184                  * yet. So clear the DMA boundary bits.
185                  */
186                 ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0));
187         }
188         return ret;
189 }
190 
191 static u32 esdhc_writeb_fixup(struct sdhci_host *host,
192                                      int spec_reg, u8 value, u32 old_value)
193 {
194         u32 ret;
195         u32 dma_bits;
196         u8 tmp;
197         int shift = (spec_reg & 0x3) * 8;
198 
199         /*
200          * eSDHC doesn't have a standard power control register, so we do
201          * nothing here to avoid incorrect operation.
202          */
203         if (spec_reg == SDHCI_POWER_CONTROL)
204                 return old_value;
205         /*
206          * "DMA select" location is offset 0x28 in SD specification, but on
207          * P5020 or P3041, it's located at 0x29.
208          */
209         if (spec_reg == SDHCI_HOST_CONTROL) {
210                 /*
211                  * If host control register is not standard, exit
212                  * this function
213                  */
214                 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL)
215                         return old_value;
216 
217                 /* DMA select is 22,23 bits in Protocol Control Register */
218                 dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5;
219                 ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits;
220                 tmp = (value & (~SDHCI_CTRL_DMA_MASK)) |
221                       (old_value & SDHCI_CTRL_DMA_MASK);
222                 ret = (ret & (~0xff)) | tmp;
223 
224                 /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */
225                 ret &= ~ESDHC_HOST_CONTROL_RES;
226                 return ret;
227         }
228 
229         ret = (old_value & (~(0xff << shift))) | (value << shift);
230         return ret;
231 }
232 
233 static u32 esdhc_be_readl(struct sdhci_host *host, int reg)
234 {
235         u32 ret;
236         u32 value;
237 
238         value = ioread32be(host->ioaddr + reg);
239         ret = esdhc_readl_fixup(host, reg, value);
240 
241         return ret;
242 }
243 
244 static u32 esdhc_le_readl(struct sdhci_host *host, int reg)
245 {
246         u32 ret;
247         u32 value;
248 
249         value = ioread32(host->ioaddr + reg);
250         ret = esdhc_readl_fixup(host, reg, value);
251 
252         return ret;
253 }
254 
255 static u16 esdhc_be_readw(struct sdhci_host *host, int reg)
256 {
257         u16 ret;
258         u32 value;
259         int base = reg & ~0x3;
260 
261         value = ioread32be(host->ioaddr + base);
262         ret = esdhc_readw_fixup(host, reg, value);
263         return ret;
264 }
265 
266 static u16 esdhc_le_readw(struct sdhci_host *host, int reg)
267 {
268         u16 ret;
269         u32 value;
270         int base = reg & ~0x3;
271 
272         value = ioread32(host->ioaddr + base);
273         ret = esdhc_readw_fixup(host, reg, value);
274         return ret;
275 }
276 
277 static u8 esdhc_be_readb(struct sdhci_host *host, int reg)
278 {
279         u8 ret;
280         u32 value;
281         int base = reg & ~0x3;
282 
283         value = ioread32be(host->ioaddr + base);
284         ret = esdhc_readb_fixup(host, reg, value);
285         return ret;
286 }
287 
288 static u8 esdhc_le_readb(struct sdhci_host *host, int reg)
289 {
290         u8 ret;
291         u32 value;
292         int base = reg & ~0x3;
293 
294         value = ioread32(host->ioaddr + base);
295         ret = esdhc_readb_fixup(host, reg, value);
296         return ret;
297 }
298 
299 static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg)
300 {
301         u32 value;
302 
303         value = esdhc_writel_fixup(host, reg, val, 0);
304         iowrite32be(value, host->ioaddr + reg);
305 }
306 
307 static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg)
308 {
309         u32 value;
310 
311         value = esdhc_writel_fixup(host, reg, val, 0);
312         iowrite32(value, host->ioaddr + reg);
313 }
314 
315 static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg)
316 {
317         int base = reg & ~0x3;
318         u32 value;
319         u32 ret;
320 
321         value = ioread32be(host->ioaddr + base);
322         ret = esdhc_writew_fixup(host, reg, val, value);
323         if (reg != SDHCI_TRANSFER_MODE)
324                 iowrite32be(ret, host->ioaddr + base);
325 }
326 
327 static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg)
328 {
329         int base = reg & ~0x3;
330         u32 value;
331         u32 ret;
332 
333         value = ioread32(host->ioaddr + base);
334         ret = esdhc_writew_fixup(host, reg, val, value);
335         if (reg != SDHCI_TRANSFER_MODE)
336                 iowrite32(ret, host->ioaddr + base);
337 }
338 
339 static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg)
340 {
341         int base = reg & ~0x3;
342         u32 value;
343         u32 ret;
344 
345         value = ioread32be(host->ioaddr + base);
346         ret = esdhc_writeb_fixup(host, reg, val, value);
347         iowrite32be(ret, host->ioaddr + base);
348 }
349 
350 static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg)
351 {
352         int base = reg & ~0x3;
353         u32 value;
354         u32 ret;
355 
356         value = ioread32(host->ioaddr + base);
357         ret = esdhc_writeb_fixup(host, reg, val, value);
358         iowrite32(ret, host->ioaddr + base);
359 }
360 
361 /*
362  * For Abort or Suspend after Stop at Block Gap, ignore the ADMA
363  * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC])
364  * and Block Gap Event(IRQSTAT[BGE]) are also set.
365  * For Continue, apply soft reset for data(SYSCTL[RSTD]);
366  * and re-issue the entire read transaction from beginning.
367  */
368 static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask)
369 {
370         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
371         struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
372         bool applicable;
373         dma_addr_t dmastart;
374         dma_addr_t dmanow;
375 
376         applicable = (intmask & SDHCI_INT_DATA_END) &&
377                      (intmask & SDHCI_INT_BLK_GAP) &&
378                      (esdhc->vendor_ver == VENDOR_V_23);
379         if (!applicable)
380                 return;
381 
382         host->data->error = 0;
383         dmastart = sg_dma_address(host->data->sg);
384         dmanow = dmastart + host->data->bytes_xfered;
385         /*
386          * Force update to the next DMA block boundary.
387          */
388         dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
389                 SDHCI_DEFAULT_BOUNDARY_SIZE;
390         host->data->bytes_xfered = dmanow - dmastart;
391         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
392 }
393 
394 static int esdhc_of_enable_dma(struct sdhci_host *host)
395 {
396         u32 value;
397 
398         value = sdhci_readl(host, ESDHC_DMA_SYSCTL);
399         value |= ESDHC_DMA_SNOOP;
400         sdhci_writel(host, value, ESDHC_DMA_SYSCTL);
401         return 0;
402 }
403 
404 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
405 {
406         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
407 
408         return pltfm_host->clock;
409 }
410 
411 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
412 {
413         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
414 
415         return pltfm_host->clock / 256 / 16;
416 }
417 
418 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
419 {
420         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
421         struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
422         int pre_div = 1;
423         int div = 1;
424         u32 temp;
425 
426         host->mmc->actual_clock = 0;
427 
428         if (clock == 0)
429                 return;
430 
431         /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */
432         if (esdhc->vendor_ver < VENDOR_V_23)
433                 pre_div = 2;
434 
435         /* Workaround to reduce the clock frequency for p1010 esdhc */
436         if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) {
437                 if (clock > 20000000)
438                         clock -= 5000000;
439                 if (clock > 40000000)
440                         clock -= 5000000;
441         }
442 
443         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
444         temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
445                 | ESDHC_CLOCK_MASK);
446         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
447 
448         while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
449                 pre_div *= 2;
450 
451         while (host->max_clk / pre_div / div > clock && div < 16)
452                 div++;
453 
454         dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
455                 clock, host->max_clk / pre_div / div);
456         host->mmc->actual_clock = host->max_clk / pre_div / div;
457         pre_div >>= 1;
458         div--;
459 
460         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
461         temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
462                 | (div << ESDHC_DIVIDER_SHIFT)
463                 | (pre_div << ESDHC_PREDIV_SHIFT));
464         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
465         mdelay(1);
466 }
467 
468 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
469 {
470         u32 ctrl;
471 
472         ctrl = sdhci_readl(host, ESDHC_PROCTL);
473         ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK);
474         switch (width) {
475         case MMC_BUS_WIDTH_8:
476                 ctrl |= ESDHC_CTRL_8BITBUS;
477                 break;
478 
479         case MMC_BUS_WIDTH_4:
480                 ctrl |= ESDHC_CTRL_4BITBUS;
481                 break;
482 
483         default:
484                 break;
485         }
486 
487         sdhci_writel(host, ctrl, ESDHC_PROCTL);
488 }
489 
490 static void esdhc_reset(struct sdhci_host *host, u8 mask)
491 {
492         sdhci_reset(host, mask);
493 
494         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
495         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
496 }
497 
498 #ifdef CONFIG_PM_SLEEP
499 static u32 esdhc_proctl;
500 static int esdhc_of_suspend(struct device *dev)
501 {
502         struct sdhci_host *host = dev_get_drvdata(dev);
503 
504         esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL);
505 
506         return sdhci_suspend_host(host);
507 }
508 
509 static int esdhc_of_resume(struct device *dev)
510 {
511         struct sdhci_host *host = dev_get_drvdata(dev);
512         int ret = sdhci_resume_host(host);
513 
514         if (ret == 0) {
515                 /* Isn't this already done by sdhci_resume_host() ? --rmk */
516                 esdhc_of_enable_dma(host);
517                 sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
518         }
519         return ret;
520 }
521 #endif
522 
523 static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops,
524                         esdhc_of_suspend,
525                         esdhc_of_resume);
526 
527 static const struct sdhci_ops sdhci_esdhc_be_ops = {
528         .read_l = esdhc_be_readl,
529         .read_w = esdhc_be_readw,
530         .read_b = esdhc_be_readb,
531         .write_l = esdhc_be_writel,
532         .write_w = esdhc_be_writew,
533         .write_b = esdhc_be_writeb,
534         .set_clock = esdhc_of_set_clock,
535         .enable_dma = esdhc_of_enable_dma,
536         .get_max_clock = esdhc_of_get_max_clock,
537         .get_min_clock = esdhc_of_get_min_clock,
538         .adma_workaround = esdhc_of_adma_workaround,
539         .set_bus_width = esdhc_pltfm_set_bus_width,
540         .reset = esdhc_reset,
541         .set_uhs_signaling = sdhci_set_uhs_signaling,
542 };
543 
544 static const struct sdhci_ops sdhci_esdhc_le_ops = {
545         .read_l = esdhc_le_readl,
546         .read_w = esdhc_le_readw,
547         .read_b = esdhc_le_readb,
548         .write_l = esdhc_le_writel,
549         .write_w = esdhc_le_writew,
550         .write_b = esdhc_le_writeb,
551         .set_clock = esdhc_of_set_clock,
552         .enable_dma = esdhc_of_enable_dma,
553         .get_max_clock = esdhc_of_get_max_clock,
554         .get_min_clock = esdhc_of_get_min_clock,
555         .adma_workaround = esdhc_of_adma_workaround,
556         .set_bus_width = esdhc_pltfm_set_bus_width,
557         .reset = esdhc_reset,
558         .set_uhs_signaling = sdhci_set_uhs_signaling,
559 };
560 
561 static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = {
562         .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_CARD_DETECTION
563                 | SDHCI_QUIRK_NO_CARD_NO_RESET
564                 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
565         .ops = &sdhci_esdhc_be_ops,
566 };
567 
568 static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = {
569         .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_CARD_DETECTION
570                 | SDHCI_QUIRK_NO_CARD_NO_RESET
571                 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
572         .ops = &sdhci_esdhc_le_ops,
573 };
574 
575 static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
576 {
577         struct sdhci_pltfm_host *pltfm_host;
578         struct sdhci_esdhc *esdhc;
579         u16 host_ver;
580 
581         pltfm_host = sdhci_priv(host);
582         esdhc = sdhci_pltfm_priv(pltfm_host);
583 
584         host_ver = sdhci_readw(host, SDHCI_HOST_VERSION);
585         esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >>
586                              SDHCI_VENDOR_VER_SHIFT;
587         esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK;
588 }
589 
590 static int sdhci_esdhc_probe(struct platform_device *pdev)
591 {
592         struct sdhci_host *host;
593         struct device_node *np;
594         struct sdhci_pltfm_host *pltfm_host;
595         struct sdhci_esdhc *esdhc;
596         int ret;
597 
598         np = pdev->dev.of_node;
599 
600         if (of_property_read_bool(np, "little-endian"))
601                 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata,
602                                         sizeof(struct sdhci_esdhc));
603         else
604                 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata,
605                                         sizeof(struct sdhci_esdhc));
606 
607         if (IS_ERR(host))
608                 return PTR_ERR(host);
609 
610         esdhc_init(pdev, host);
611 
612         sdhci_get_of_property(pdev);
613 
614         pltfm_host = sdhci_priv(host);
615         esdhc = sdhci_pltfm_priv(pltfm_host);
616         if (esdhc->vendor_ver == VENDOR_V_22)
617                 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
618 
619         if (esdhc->vendor_ver > VENDOR_V_22)
620                 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
621 
622         if (of_device_is_compatible(np, "fsl,p5040-esdhc") ||
623             of_device_is_compatible(np, "fsl,p5020-esdhc") ||
624             of_device_is_compatible(np, "fsl,p4080-esdhc") ||
625             of_device_is_compatible(np, "fsl,p1020-esdhc") ||
626             of_device_is_compatible(np, "fsl,t1040-esdhc") ||
627             of_device_is_compatible(np, "fsl,ls1021a-esdhc"))
628                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
629 
630         if (of_device_is_compatible(np, "fsl,ls1021a-esdhc"))
631                 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
632 
633         if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {
634                 /*
635                  * Freescale messed up with P2020 as it has a non-standard
636                  * host control register
637                  */
638                 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL;
639         }
640 
641         /* call to generic mmc_of_parse to support additional capabilities */
642         ret = mmc_of_parse(host->mmc);
643         if (ret)
644                 goto err;
645 
646         mmc_of_parse_voltage(np, &host->ocr_mask);
647 
648         ret = sdhci_add_host(host);
649         if (ret)
650                 goto err;
651 
652         return 0;
653  err:
654         sdhci_pltfm_free(pdev);
655         return ret;
656 }
657 
658 static const struct of_device_id sdhci_esdhc_of_match[] = {
659         { .compatible = "fsl,mpc8379-esdhc" },
660         { .compatible = "fsl,mpc8536-esdhc" },
661         { .compatible = "fsl,esdhc" },
662         { }
663 };
664 MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match);
665 
666 static struct platform_driver sdhci_esdhc_driver = {
667         .driver = {
668                 .name = "sdhci-esdhc",
669                 .of_match_table = sdhci_esdhc_of_match,
670                 .pm = &esdhc_of_dev_pm_ops,
671         },
672         .probe = sdhci_esdhc_probe,
673         .remove = sdhci_pltfm_unregister,
674 };
675 
676 module_platform_driver(sdhci_esdhc_driver);
677 
678 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC");
679 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, "
680               "Anton Vorontsov <avorontsov@ru.mvista.com>");
681 MODULE_LICENSE("GPL v2");
682 

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