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Linux/drivers/mmc/host/sdhci-of-esdhc.c

  1 /*
  2  * Freescale eSDHC controller driver.
  3  *
  4  * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc.
  5  * Copyright (c) 2009 MontaVista Software, Inc.
  6  *
  7  * Authors: Xiaobo Xie <X.Xie@freescale.com>
  8  *          Anton Vorontsov <avorontsov@ru.mvista.com>
  9  *
 10  * This program is free software; you can redistribute it and/or modify
 11  * it under the terms of the GNU General Public License as published by
 12  * the Free Software Foundation; either version 2 of the License, or (at
 13  * your option) any later version.
 14  */
 15 
 16 #include <linux/err.h>
 17 #include <linux/io.h>
 18 #include <linux/of.h>
 19 #include <linux/delay.h>
 20 #include <linux/module.h>
 21 #include <linux/sys_soc.h>
 22 #include <linux/mmc/host.h>
 23 #include "sdhci-pltfm.h"
 24 #include "sdhci-esdhc.h"
 25 
 26 #define VENDOR_V_22     0x12
 27 #define VENDOR_V_23     0x13
 28 
 29 struct sdhci_esdhc {
 30         u8 vendor_ver;
 31         u8 spec_ver;
 32         bool quirk_incorrect_hostver;
 33 };
 34 
 35 /**
 36  * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register
 37  *                     to make it compatible with SD spec.
 38  *
 39  * @host: pointer to sdhci_host
 40  * @spec_reg: SD spec register address
 41  * @value: 32bit eSDHC register value on spec_reg address
 42  *
 43  * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
 44  * registers are 32 bits. There are differences in register size, register
 45  * address, register function, bit position and function between eSDHC spec
 46  * and SD spec.
 47  *
 48  * Return a fixed up register value
 49  */
 50 static u32 esdhc_readl_fixup(struct sdhci_host *host,
 51                                      int spec_reg, u32 value)
 52 {
 53         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 54         struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
 55         u32 ret;
 56 
 57         /*
 58          * The bit of ADMA flag in eSDHC is not compatible with standard
 59          * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is
 60          * supported by eSDHC.
 61          * And for many FSL eSDHC controller, the reset value of field
 62          * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA,
 63          * only these vendor version is greater than 2.2/0x12 support ADMA.
 64          */
 65         if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) {
 66                 if (esdhc->vendor_ver > VENDOR_V_22) {
 67                         ret = value | SDHCI_CAN_DO_ADMA2;
 68                         return ret;
 69                 }
 70         }
 71         /*
 72          * The DAT[3:0] line signal levels and the CMD line signal level are
 73          * not compatible with standard SDHC register. The line signal levels
 74          * DAT[7:0] are at bits 31:24 and the command line signal level is at
 75          * bit 23. All other bits are the same as in the standard SDHC
 76          * register.
 77          */
 78         if (spec_reg == SDHCI_PRESENT_STATE) {
 79                 ret = value & 0x000fffff;
 80                 ret |= (value >> 4) & SDHCI_DATA_LVL_MASK;
 81                 ret |= (value << 1) & SDHCI_CMD_LVL;
 82                 return ret;
 83         }
 84 
 85         ret = value;
 86         return ret;
 87 }
 88 
 89 static u16 esdhc_readw_fixup(struct sdhci_host *host,
 90                                      int spec_reg, u32 value)
 91 {
 92         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 93         struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
 94         u16 ret;
 95         int shift = (spec_reg & 0x2) * 8;
 96 
 97         if (spec_reg == SDHCI_HOST_VERSION)
 98                 ret = value & 0xffff;
 99         else
100                 ret = (value >> shift) & 0xffff;
101         /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect
102          * vendor version and spec version information.
103          */
104         if ((spec_reg == SDHCI_HOST_VERSION) &&
105             (esdhc->quirk_incorrect_hostver))
106                 ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200;
107         return ret;
108 }
109 
110 static u8 esdhc_readb_fixup(struct sdhci_host *host,
111                                      int spec_reg, u32 value)
112 {
113         u8 ret;
114         u8 dma_bits;
115         int shift = (spec_reg & 0x3) * 8;
116 
117         ret = (value >> shift) & 0xff;
118 
119         /*
120          * "DMA select" locates at offset 0x28 in SD specification, but on
121          * P5020 or P3041, it locates at 0x29.
122          */
123         if (spec_reg == SDHCI_HOST_CONTROL) {
124                 /* DMA select is 22,23 bits in Protocol Control Register */
125                 dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK;
126                 /* fixup the result */
127                 ret &= ~SDHCI_CTRL_DMA_MASK;
128                 ret |= dma_bits;
129         }
130         return ret;
131 }
132 
133 /**
134  * esdhc_write*_fixup - Fixup the SD spec register value so that it could be
135  *                      written into eSDHC register.
136  *
137  * @host: pointer to sdhci_host
138  * @spec_reg: SD spec register address
139  * @value: 8/16/32bit SD spec register value that would be written
140  * @old_value: 32bit eSDHC register value on spec_reg address
141  *
142  * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
143  * registers are 32 bits. There are differences in register size, register
144  * address, register function, bit position and function between eSDHC spec
145  * and SD spec.
146  *
147  * Return a fixed up register value
148  */
149 static u32 esdhc_writel_fixup(struct sdhci_host *host,
150                                      int spec_reg, u32 value, u32 old_value)
151 {
152         u32 ret;
153 
154         /*
155          * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE]
156          * when SYSCTL[RSTD] is set for some special operations.
157          * No any impact on other operation.
158          */
159         if (spec_reg == SDHCI_INT_ENABLE)
160                 ret = value | SDHCI_INT_BLK_GAP;
161         else
162                 ret = value;
163 
164         return ret;
165 }
166 
167 static u32 esdhc_writew_fixup(struct sdhci_host *host,
168                                      int spec_reg, u16 value, u32 old_value)
169 {
170         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
171         int shift = (spec_reg & 0x2) * 8;
172         u32 ret;
173 
174         switch (spec_reg) {
175         case SDHCI_TRANSFER_MODE:
176                 /*
177                  * Postpone this write, we must do it together with a
178                  * command write that is down below. Return old value.
179                  */
180                 pltfm_host->xfer_mode_shadow = value;
181                 return old_value;
182         case SDHCI_COMMAND:
183                 ret = (value << 16) | pltfm_host->xfer_mode_shadow;
184                 return ret;
185         }
186 
187         ret = old_value & (~(0xffff << shift));
188         ret |= (value << shift);
189 
190         if (spec_reg == SDHCI_BLOCK_SIZE) {
191                 /*
192                  * Two last DMA bits are reserved, and first one is used for
193                  * non-standard blksz of 4096 bytes that we don't support
194                  * yet. So clear the DMA boundary bits.
195                  */
196                 ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0));
197         }
198         return ret;
199 }
200 
201 static u32 esdhc_writeb_fixup(struct sdhci_host *host,
202                                      int spec_reg, u8 value, u32 old_value)
203 {
204         u32 ret;
205         u32 dma_bits;
206         u8 tmp;
207         int shift = (spec_reg & 0x3) * 8;
208 
209         /*
210          * eSDHC doesn't have a standard power control register, so we do
211          * nothing here to avoid incorrect operation.
212          */
213         if (spec_reg == SDHCI_POWER_CONTROL)
214                 return old_value;
215         /*
216          * "DMA select" location is offset 0x28 in SD specification, but on
217          * P5020 or P3041, it's located at 0x29.
218          */
219         if (spec_reg == SDHCI_HOST_CONTROL) {
220                 /*
221                  * If host control register is not standard, exit
222                  * this function
223                  */
224                 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL)
225                         return old_value;
226 
227                 /* DMA select is 22,23 bits in Protocol Control Register */
228                 dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5;
229                 ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits;
230                 tmp = (value & (~SDHCI_CTRL_DMA_MASK)) |
231                       (old_value & SDHCI_CTRL_DMA_MASK);
232                 ret = (ret & (~0xff)) | tmp;
233 
234                 /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */
235                 ret &= ~ESDHC_HOST_CONTROL_RES;
236                 return ret;
237         }
238 
239         ret = (old_value & (~(0xff << shift))) | (value << shift);
240         return ret;
241 }
242 
243 static u32 esdhc_be_readl(struct sdhci_host *host, int reg)
244 {
245         u32 ret;
246         u32 value;
247 
248         value = ioread32be(host->ioaddr + reg);
249         ret = esdhc_readl_fixup(host, reg, value);
250 
251         return ret;
252 }
253 
254 static u32 esdhc_le_readl(struct sdhci_host *host, int reg)
255 {
256         u32 ret;
257         u32 value;
258 
259         value = ioread32(host->ioaddr + reg);
260         ret = esdhc_readl_fixup(host, reg, value);
261 
262         return ret;
263 }
264 
265 static u16 esdhc_be_readw(struct sdhci_host *host, int reg)
266 {
267         u16 ret;
268         u32 value;
269         int base = reg & ~0x3;
270 
271         value = ioread32be(host->ioaddr + base);
272         ret = esdhc_readw_fixup(host, reg, value);
273         return ret;
274 }
275 
276 static u16 esdhc_le_readw(struct sdhci_host *host, int reg)
277 {
278         u16 ret;
279         u32 value;
280         int base = reg & ~0x3;
281 
282         value = ioread32(host->ioaddr + base);
283         ret = esdhc_readw_fixup(host, reg, value);
284         return ret;
285 }
286 
287 static u8 esdhc_be_readb(struct sdhci_host *host, int reg)
288 {
289         u8 ret;
290         u32 value;
291         int base = reg & ~0x3;
292 
293         value = ioread32be(host->ioaddr + base);
294         ret = esdhc_readb_fixup(host, reg, value);
295         return ret;
296 }
297 
298 static u8 esdhc_le_readb(struct sdhci_host *host, int reg)
299 {
300         u8 ret;
301         u32 value;
302         int base = reg & ~0x3;
303 
304         value = ioread32(host->ioaddr + base);
305         ret = esdhc_readb_fixup(host, reg, value);
306         return ret;
307 }
308 
309 static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg)
310 {
311         u32 value;
312 
313         value = esdhc_writel_fixup(host, reg, val, 0);
314         iowrite32be(value, host->ioaddr + reg);
315 }
316 
317 static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg)
318 {
319         u32 value;
320 
321         value = esdhc_writel_fixup(host, reg, val, 0);
322         iowrite32(value, host->ioaddr + reg);
323 }
324 
325 static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg)
326 {
327         int base = reg & ~0x3;
328         u32 value;
329         u32 ret;
330 
331         value = ioread32be(host->ioaddr + base);
332         ret = esdhc_writew_fixup(host, reg, val, value);
333         if (reg != SDHCI_TRANSFER_MODE)
334                 iowrite32be(ret, host->ioaddr + base);
335 }
336 
337 static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg)
338 {
339         int base = reg & ~0x3;
340         u32 value;
341         u32 ret;
342 
343         value = ioread32(host->ioaddr + base);
344         ret = esdhc_writew_fixup(host, reg, val, value);
345         if (reg != SDHCI_TRANSFER_MODE)
346                 iowrite32(ret, host->ioaddr + base);
347 }
348 
349 static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg)
350 {
351         int base = reg & ~0x3;
352         u32 value;
353         u32 ret;
354 
355         value = ioread32be(host->ioaddr + base);
356         ret = esdhc_writeb_fixup(host, reg, val, value);
357         iowrite32be(ret, host->ioaddr + base);
358 }
359 
360 static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg)
361 {
362         int base = reg & ~0x3;
363         u32 value;
364         u32 ret;
365 
366         value = ioread32(host->ioaddr + base);
367         ret = esdhc_writeb_fixup(host, reg, val, value);
368         iowrite32(ret, host->ioaddr + base);
369 }
370 
371 /*
372  * For Abort or Suspend after Stop at Block Gap, ignore the ADMA
373  * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC])
374  * and Block Gap Event(IRQSTAT[BGE]) are also set.
375  * For Continue, apply soft reset for data(SYSCTL[RSTD]);
376  * and re-issue the entire read transaction from beginning.
377  */
378 static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask)
379 {
380         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
381         struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
382         bool applicable;
383         dma_addr_t dmastart;
384         dma_addr_t dmanow;
385 
386         applicable = (intmask & SDHCI_INT_DATA_END) &&
387                      (intmask & SDHCI_INT_BLK_GAP) &&
388                      (esdhc->vendor_ver == VENDOR_V_23);
389         if (!applicable)
390                 return;
391 
392         host->data->error = 0;
393         dmastart = sg_dma_address(host->data->sg);
394         dmanow = dmastart + host->data->bytes_xfered;
395         /*
396          * Force update to the next DMA block boundary.
397          */
398         dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
399                 SDHCI_DEFAULT_BOUNDARY_SIZE;
400         host->data->bytes_xfered = dmanow - dmastart;
401         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
402 }
403 
404 static int esdhc_of_enable_dma(struct sdhci_host *host)
405 {
406         u32 value;
407 
408         value = sdhci_readl(host, ESDHC_DMA_SYSCTL);
409         value |= ESDHC_DMA_SNOOP;
410         sdhci_writel(host, value, ESDHC_DMA_SYSCTL);
411         return 0;
412 }
413 
414 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
415 {
416         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
417 
418         return pltfm_host->clock;
419 }
420 
421 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
422 {
423         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
424 
425         return pltfm_host->clock / 256 / 16;
426 }
427 
428 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
429 {
430         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
431         struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
432         int pre_div = 1;
433         int div = 1;
434         u32 temp;
435 
436         host->mmc->actual_clock = 0;
437 
438         if (clock == 0)
439                 return;
440 
441         /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */
442         if (esdhc->vendor_ver < VENDOR_V_23)
443                 pre_div = 2;
444 
445         /* Workaround to reduce the clock frequency for p1010 esdhc */
446         if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) {
447                 if (clock > 20000000)
448                         clock -= 5000000;
449                 if (clock > 40000000)
450                         clock -= 5000000;
451         }
452 
453         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
454         temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
455                 | ESDHC_CLOCK_MASK);
456         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
457 
458         while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
459                 pre_div *= 2;
460 
461         while (host->max_clk / pre_div / div > clock && div < 16)
462                 div++;
463 
464         dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
465                 clock, host->max_clk / pre_div / div);
466         host->mmc->actual_clock = host->max_clk / pre_div / div;
467         pre_div >>= 1;
468         div--;
469 
470         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
471         temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
472                 | (div << ESDHC_DIVIDER_SHIFT)
473                 | (pre_div << ESDHC_PREDIV_SHIFT));
474         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
475         mdelay(1);
476 }
477 
478 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
479 {
480         u32 ctrl;
481 
482         ctrl = sdhci_readl(host, ESDHC_PROCTL);
483         ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK);
484         switch (width) {
485         case MMC_BUS_WIDTH_8:
486                 ctrl |= ESDHC_CTRL_8BITBUS;
487                 break;
488 
489         case MMC_BUS_WIDTH_4:
490                 ctrl |= ESDHC_CTRL_4BITBUS;
491                 break;
492 
493         default:
494                 break;
495         }
496 
497         sdhci_writel(host, ctrl, ESDHC_PROCTL);
498 }
499 
500 static void esdhc_reset(struct sdhci_host *host, u8 mask)
501 {
502         sdhci_reset(host, mask);
503 
504         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
505         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
506 }
507 
508 #ifdef CONFIG_PM_SLEEP
509 static u32 esdhc_proctl;
510 static int esdhc_of_suspend(struct device *dev)
511 {
512         struct sdhci_host *host = dev_get_drvdata(dev);
513 
514         esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL);
515 
516         return sdhci_suspend_host(host);
517 }
518 
519 static int esdhc_of_resume(struct device *dev)
520 {
521         struct sdhci_host *host = dev_get_drvdata(dev);
522         int ret = sdhci_resume_host(host);
523 
524         if (ret == 0) {
525                 /* Isn't this already done by sdhci_resume_host() ? --rmk */
526                 esdhc_of_enable_dma(host);
527                 sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
528         }
529         return ret;
530 }
531 #endif
532 
533 static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops,
534                         esdhc_of_suspend,
535                         esdhc_of_resume);
536 
537 static const struct sdhci_ops sdhci_esdhc_be_ops = {
538         .read_l = esdhc_be_readl,
539         .read_w = esdhc_be_readw,
540         .read_b = esdhc_be_readb,
541         .write_l = esdhc_be_writel,
542         .write_w = esdhc_be_writew,
543         .write_b = esdhc_be_writeb,
544         .set_clock = esdhc_of_set_clock,
545         .enable_dma = esdhc_of_enable_dma,
546         .get_max_clock = esdhc_of_get_max_clock,
547         .get_min_clock = esdhc_of_get_min_clock,
548         .adma_workaround = esdhc_of_adma_workaround,
549         .set_bus_width = esdhc_pltfm_set_bus_width,
550         .reset = esdhc_reset,
551         .set_uhs_signaling = sdhci_set_uhs_signaling,
552 };
553 
554 static const struct sdhci_ops sdhci_esdhc_le_ops = {
555         .read_l = esdhc_le_readl,
556         .read_w = esdhc_le_readw,
557         .read_b = esdhc_le_readb,
558         .write_l = esdhc_le_writel,
559         .write_w = esdhc_le_writew,
560         .write_b = esdhc_le_writeb,
561         .set_clock = esdhc_of_set_clock,
562         .enable_dma = esdhc_of_enable_dma,
563         .get_max_clock = esdhc_of_get_max_clock,
564         .get_min_clock = esdhc_of_get_min_clock,
565         .adma_workaround = esdhc_of_adma_workaround,
566         .set_bus_width = esdhc_pltfm_set_bus_width,
567         .reset = esdhc_reset,
568         .set_uhs_signaling = sdhci_set_uhs_signaling,
569 };
570 
571 static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = {
572         .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_CARD_DETECTION
573                 | SDHCI_QUIRK_NO_CARD_NO_RESET
574                 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
575         .ops = &sdhci_esdhc_be_ops,
576 };
577 
578 static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = {
579         .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_CARD_DETECTION
580                 | SDHCI_QUIRK_NO_CARD_NO_RESET
581                 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
582         .ops = &sdhci_esdhc_le_ops,
583 };
584 
585 static struct soc_device_attribute soc_incorrect_hostver[] = {
586         { .family = "QorIQ T4240", .revision = "1.0", },
587         { .family = "QorIQ T4240", .revision = "2.0", },
588         { },
589 };
590 
591 static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
592 {
593         struct sdhci_pltfm_host *pltfm_host;
594         struct sdhci_esdhc *esdhc;
595         u16 host_ver;
596 
597         pltfm_host = sdhci_priv(host);
598         esdhc = sdhci_pltfm_priv(pltfm_host);
599 
600         host_ver = sdhci_readw(host, SDHCI_HOST_VERSION);
601         esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >>
602                              SDHCI_VENDOR_VER_SHIFT;
603         esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK;
604         if (soc_device_match(soc_incorrect_hostver))
605                 esdhc->quirk_incorrect_hostver = true;
606         else
607                 esdhc->quirk_incorrect_hostver = false;
608 }
609 
610 static int sdhci_esdhc_probe(struct platform_device *pdev)
611 {
612         struct sdhci_host *host;
613         struct device_node *np;
614         struct sdhci_pltfm_host *pltfm_host;
615         struct sdhci_esdhc *esdhc;
616         int ret;
617 
618         np = pdev->dev.of_node;
619 
620         if (of_property_read_bool(np, "little-endian"))
621                 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata,
622                                         sizeof(struct sdhci_esdhc));
623         else
624                 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata,
625                                         sizeof(struct sdhci_esdhc));
626 
627         if (IS_ERR(host))
628                 return PTR_ERR(host);
629 
630         esdhc_init(pdev, host);
631 
632         sdhci_get_of_property(pdev);
633 
634         pltfm_host = sdhci_priv(host);
635         esdhc = sdhci_pltfm_priv(pltfm_host);
636         if (esdhc->vendor_ver == VENDOR_V_22)
637                 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
638 
639         if (esdhc->vendor_ver > VENDOR_V_22)
640                 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
641 
642         if (of_device_is_compatible(np, "fsl,p5040-esdhc") ||
643             of_device_is_compatible(np, "fsl,p5020-esdhc") ||
644             of_device_is_compatible(np, "fsl,p4080-esdhc") ||
645             of_device_is_compatible(np, "fsl,p1020-esdhc") ||
646             of_device_is_compatible(np, "fsl,t1040-esdhc") ||
647             of_device_is_compatible(np, "fsl,ls1021a-esdhc"))
648                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
649 
650         if (of_device_is_compatible(np, "fsl,ls1021a-esdhc"))
651                 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
652 
653         if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {
654                 /*
655                  * Freescale messed up with P2020 as it has a non-standard
656                  * host control register
657                  */
658                 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL;
659         }
660 
661         /* call to generic mmc_of_parse to support additional capabilities */
662         ret = mmc_of_parse(host->mmc);
663         if (ret)
664                 goto err;
665 
666         mmc_of_parse_voltage(np, &host->ocr_mask);
667 
668         ret = sdhci_add_host(host);
669         if (ret)
670                 goto err;
671 
672         return 0;
673  err:
674         sdhci_pltfm_free(pdev);
675         return ret;
676 }
677 
678 static const struct of_device_id sdhci_esdhc_of_match[] = {
679         { .compatible = "fsl,mpc8379-esdhc" },
680         { .compatible = "fsl,mpc8536-esdhc" },
681         { .compatible = "fsl,esdhc" },
682         { }
683 };
684 MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match);
685 
686 static struct platform_driver sdhci_esdhc_driver = {
687         .driver = {
688                 .name = "sdhci-esdhc",
689                 .of_match_table = sdhci_esdhc_of_match,
690                 .pm = &esdhc_of_dev_pm_ops,
691         },
692         .probe = sdhci_esdhc_probe,
693         .remove = sdhci_pltfm_unregister,
694 };
695 
696 module_platform_driver(sdhci_esdhc_driver);
697 
698 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC");
699 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, "
700               "Anton Vorontsov <avorontsov@ru.mvista.com>");
701 MODULE_LICENSE("GPL v2");
702 

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