Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4

Linux/drivers/mmc/host/sdhci-esdhc-imx.c

  1 /*
  2  * Freescale eSDHC i.MX controller driver for the platform bus.
  3  *
  4  * derived from the OF-version.
  5  *
  6  * Copyright (c) 2010 Pengutronix e.K.
  7  *   Author: Wolfram Sang <kernel@pengutronix.de>
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License as published by
 11  * the Free Software Foundation; either version 2 of the License.
 12  */
 13 
 14 #include <linux/io.h>
 15 #include <linux/delay.h>
 16 #include <linux/err.h>
 17 #include <linux/clk.h>
 18 #include <linux/gpio.h>
 19 #include <linux/module.h>
 20 #include <linux/slab.h>
 21 #include <linux/mmc/host.h>
 22 #include <linux/mmc/mmc.h>
 23 #include <linux/mmc/sdio.h>
 24 #include <linux/mmc/slot-gpio.h>
 25 #include <linux/of.h>
 26 #include <linux/of_device.h>
 27 #include <linux/of_gpio.h>
 28 #include <linux/pinctrl/consumer.h>
 29 #include <linux/platform_data/mmc-esdhc-imx.h>
 30 #include <linux/pm_runtime.h>
 31 #include "sdhci-pltfm.h"
 32 #include "sdhci-esdhc.h"
 33 
 34 #define ESDHC_CTRL_D3CD                 0x08
 35 #define ESDHC_BURST_LEN_EN_INCR         (1 << 27)
 36 /* VENDOR SPEC register */
 37 #define ESDHC_VENDOR_SPEC               0xc0
 38 #define  ESDHC_VENDOR_SPEC_SDIO_QUIRK   (1 << 1)
 39 #define  ESDHC_VENDOR_SPEC_VSELECT      (1 << 1)
 40 #define  ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
 41 #define ESDHC_WTMK_LVL                  0x44
 42 #define ESDHC_MIX_CTRL                  0x48
 43 #define  ESDHC_MIX_CTRL_DDREN           (1 << 3)
 44 #define  ESDHC_MIX_CTRL_AC23EN          (1 << 7)
 45 #define  ESDHC_MIX_CTRL_EXE_TUNE        (1 << 22)
 46 #define  ESDHC_MIX_CTRL_SMPCLK_SEL      (1 << 23)
 47 #define  ESDHC_MIX_CTRL_FBCLK_SEL       (1 << 25)
 48 #define  ESDHC_MIX_CTRL_HS400_EN        (1 << 26)
 49 /* Bits 3 and 6 are not SDHCI standard definitions */
 50 #define  ESDHC_MIX_CTRL_SDHCI_MASK      0xb7
 51 /* Tuning bits */
 52 #define  ESDHC_MIX_CTRL_TUNING_MASK     0x03c00000
 53 
 54 /* dll control register */
 55 #define ESDHC_DLL_CTRL                  0x60
 56 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT    9
 57 #define ESDHC_DLL_OVERRIDE_EN_SHIFT     8
 58 
 59 /* tune control register */
 60 #define ESDHC_TUNE_CTRL_STATUS          0x68
 61 #define  ESDHC_TUNE_CTRL_STEP           1
 62 #define  ESDHC_TUNE_CTRL_MIN            0
 63 #define  ESDHC_TUNE_CTRL_MAX            ((1 << 7) - 1)
 64 
 65 /* strobe dll register */
 66 #define ESDHC_STROBE_DLL_CTRL           0x70
 67 #define ESDHC_STROBE_DLL_CTRL_ENABLE    (1 << 0)
 68 #define ESDHC_STROBE_DLL_CTRL_RESET     (1 << 1)
 69 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT      3
 70 
 71 #define ESDHC_STROBE_DLL_STATUS         0x74
 72 #define ESDHC_STROBE_DLL_STS_REF_LOCK   (1 << 1)
 73 #define ESDHC_STROBE_DLL_STS_SLV_LOCK   0x1
 74 
 75 #define ESDHC_TUNING_CTRL               0xcc
 76 #define ESDHC_STD_TUNING_EN             (1 << 24)
 77 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
 78 #define ESDHC_TUNING_START_TAP          0x1
 79 #define ESDHC_TUNING_STEP_SHIFT         16
 80 
 81 /* pinctrl state */
 82 #define ESDHC_PINCTRL_STATE_100MHZ      "state_100mhz"
 83 #define ESDHC_PINCTRL_STATE_200MHZ      "state_200mhz"
 84 
 85 /*
 86  * Our interpretation of the SDHCI_HOST_CONTROL register
 87  */
 88 #define ESDHC_CTRL_4BITBUS              (0x1 << 1)
 89 #define ESDHC_CTRL_8BITBUS              (0x2 << 1)
 90 #define ESDHC_CTRL_BUSWIDTH_MASK        (0x3 << 1)
 91 
 92 /*
 93  * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
 94  * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
 95  * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
 96  * Define this macro DMA error INT for fsl eSDHC
 97  */
 98 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR   (1 << 28)
 99 
100 /*
101  * The CMDTYPE of the CMD register (offset 0xE) should be set to
102  * "11" when the STOP CMD12 is issued on imx53 to abort one
103  * open ended multi-blk IO. Otherwise the TC INT wouldn't
104  * be generated.
105  * In exact block transfer, the controller doesn't complete the
106  * operations automatically as required at the end of the
107  * transfer and remains on hold if the abort command is not sent.
108  * As a result, the TC flag is not asserted and SW  received timeout
109  * exeception. Bit1 of Vendor Spec registor is used to fix it.
110  */
111 #define ESDHC_FLAG_MULTIBLK_NO_INT      BIT(1)
112 /*
113  * The flag enables the workaround for ESDHC errata ENGcm07207 which
114  * affects i.MX25 and i.MX35.
115  */
116 #define ESDHC_FLAG_ENGCM07207           BIT(2)
117 /*
118  * The flag tells that the ESDHC controller is an USDHC block that is
119  * integrated on the i.MX6 series.
120  */
121 #define ESDHC_FLAG_USDHC                BIT(3)
122 /* The IP supports manual tuning process */
123 #define ESDHC_FLAG_MAN_TUNING           BIT(4)
124 /* The IP supports standard tuning process */
125 #define ESDHC_FLAG_STD_TUNING           BIT(5)
126 /* The IP has SDHCI_CAPABILITIES_1 register */
127 #define ESDHC_FLAG_HAVE_CAP1            BIT(6)
128 /*
129  * The IP has errata ERR004536
130  * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
131  * when reading data from the card
132  */
133 #define ESDHC_FLAG_ERR004536            BIT(7)
134 /* The IP supports HS200 mode */
135 #define ESDHC_FLAG_HS200                BIT(8)
136 /* The IP supports HS400 mode */
137 #define ESDHC_FLAG_HS400                BIT(9)
138 
139 /* A higher clock ferquency than this rate requires strobell dll control */
140 #define ESDHC_STROBE_DLL_CLK_FREQ       100000000
141 
142 struct esdhc_soc_data {
143         u32 flags;
144 };
145 
146 static struct esdhc_soc_data esdhc_imx25_data = {
147         .flags = ESDHC_FLAG_ENGCM07207,
148 };
149 
150 static struct esdhc_soc_data esdhc_imx35_data = {
151         .flags = ESDHC_FLAG_ENGCM07207,
152 };
153 
154 static struct esdhc_soc_data esdhc_imx51_data = {
155         .flags = 0,
156 };
157 
158 static struct esdhc_soc_data esdhc_imx53_data = {
159         .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
160 };
161 
162 static struct esdhc_soc_data usdhc_imx6q_data = {
163         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
164 };
165 
166 static struct esdhc_soc_data usdhc_imx6sl_data = {
167         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
168                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
169                         | ESDHC_FLAG_HS200,
170 };
171 
172 static struct esdhc_soc_data usdhc_imx6sx_data = {
173         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
174                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
175 };
176 
177 static struct esdhc_soc_data usdhc_imx7d_data = {
178         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
179                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
180                         | ESDHC_FLAG_HS400,
181 };
182 
183 struct pltfm_imx_data {
184         u32 scratchpad;
185         struct pinctrl *pinctrl;
186         struct pinctrl_state *pins_default;
187         struct pinctrl_state *pins_100mhz;
188         struct pinctrl_state *pins_200mhz;
189         const struct esdhc_soc_data *socdata;
190         struct esdhc_platform_data boarddata;
191         struct clk *clk_ipg;
192         struct clk *clk_ahb;
193         struct clk *clk_per;
194         enum {
195                 NO_CMD_PENDING,      /* no multiblock command pending*/
196                 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
197                 WAIT_FOR_INT,        /* sent CMD12, waiting for response INT */
198         } multiblock_status;
199         u32 is_ddr;
200 };
201 
202 static const struct platform_device_id imx_esdhc_devtype[] = {
203         {
204                 .name = "sdhci-esdhc-imx25",
205                 .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
206         }, {
207                 .name = "sdhci-esdhc-imx35",
208                 .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
209         }, {
210                 .name = "sdhci-esdhc-imx51",
211                 .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
212         }, {
213                 /* sentinel */
214         }
215 };
216 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
217 
218 static const struct of_device_id imx_esdhc_dt_ids[] = {
219         { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
220         { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
221         { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
222         { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
223         { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
224         { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
225         { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
226         { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
227         { /* sentinel */ }
228 };
229 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
230 
231 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
232 {
233         return data->socdata == &esdhc_imx25_data;
234 }
235 
236 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
237 {
238         return data->socdata == &esdhc_imx53_data;
239 }
240 
241 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
242 {
243         return data->socdata == &usdhc_imx6q_data;
244 }
245 
246 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
247 {
248         return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
249 }
250 
251 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
252 {
253         void __iomem *base = host->ioaddr + (reg & ~0x3);
254         u32 shift = (reg & 0x3) * 8;
255 
256         writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
257 }
258 
259 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
260 {
261         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
262         struct pltfm_imx_data *imx_data = pltfm_host->priv;
263         u32 val = readl(host->ioaddr + reg);
264 
265         if (unlikely(reg == SDHCI_PRESENT_STATE)) {
266                 u32 fsl_prss = val;
267                 /* save the least 20 bits */
268                 val = fsl_prss & 0x000FFFFF;
269                 /* move dat[0-3] bits */
270                 val |= (fsl_prss & 0x0F000000) >> 4;
271                 /* move cmd line bit */
272                 val |= (fsl_prss & 0x00800000) << 1;
273         }
274 
275         if (unlikely(reg == SDHCI_CAPABILITIES)) {
276                 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
277                 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
278                         val &= 0xffff0000;
279 
280                 /* In FSL esdhc IC module, only bit20 is used to indicate the
281                  * ADMA2 capability of esdhc, but this bit is messed up on
282                  * some SOCs (e.g. on MX25, MX35 this bit is set, but they
283                  * don't actually support ADMA2). So set the BROKEN_ADMA
284                  * uirk on MX25/35 platforms.
285                  */
286 
287                 if (val & SDHCI_CAN_DO_ADMA1) {
288                         val &= ~SDHCI_CAN_DO_ADMA1;
289                         val |= SDHCI_CAN_DO_ADMA2;
290                 }
291         }
292 
293         if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
294                 if (esdhc_is_usdhc(imx_data)) {
295                         if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
296                                 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
297                         else
298                                 /* imx6q/dl does not have cap_1 register, fake one */
299                                 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
300                                         | SDHCI_SUPPORT_SDR50
301                                         | SDHCI_USE_SDR50_TUNING;
302 
303                         if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
304                                 val |= SDHCI_SUPPORT_HS400;
305                 }
306         }
307 
308         if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
309                 val = 0;
310                 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
311                 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
312                 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
313         }
314 
315         if (unlikely(reg == SDHCI_INT_STATUS)) {
316                 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
317                         val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
318                         val |= SDHCI_INT_ADMA_ERROR;
319                 }
320 
321                 /*
322                  * mask off the interrupt we get in response to the manually
323                  * sent CMD12
324                  */
325                 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
326                     ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
327                         val &= ~SDHCI_INT_RESPONSE;
328                         writel(SDHCI_INT_RESPONSE, host->ioaddr +
329                                                    SDHCI_INT_STATUS);
330                         imx_data->multiblock_status = NO_CMD_PENDING;
331                 }
332         }
333 
334         return val;
335 }
336 
337 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
338 {
339         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
340         struct pltfm_imx_data *imx_data = pltfm_host->priv;
341         u32 data;
342 
343         if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
344                 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
345                         /*
346                          * Clear and then set D3CD bit to avoid missing the
347                          * card interrupt.  This is a eSDHC controller problem
348                          * so we need to apply the following workaround: clear
349                          * and set D3CD bit will make eSDHC re-sample the card
350                          * interrupt. In case a card interrupt was lost,
351                          * re-sample it by the following steps.
352                          */
353                         data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
354                         data &= ~ESDHC_CTRL_D3CD;
355                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
356                         data |= ESDHC_CTRL_D3CD;
357                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
358                 }
359 
360                 if (val & SDHCI_INT_ADMA_ERROR) {
361                         val &= ~SDHCI_INT_ADMA_ERROR;
362                         val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
363                 }
364         }
365 
366         if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
367                                 && (reg == SDHCI_INT_STATUS)
368                                 && (val & SDHCI_INT_DATA_END))) {
369                         u32 v;
370                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
371                         v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
372                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
373 
374                         if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
375                         {
376                                 /* send a manual CMD12 with RESPTYP=none */
377                                 data = MMC_STOP_TRANSMISSION << 24 |
378                                        SDHCI_CMD_ABORTCMD << 16;
379                                 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
380                                 imx_data->multiblock_status = WAIT_FOR_INT;
381                         }
382         }
383 
384         writel(val, host->ioaddr + reg);
385 }
386 
387 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
388 {
389         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
390         struct pltfm_imx_data *imx_data = pltfm_host->priv;
391         u16 ret = 0;
392         u32 val;
393 
394         if (unlikely(reg == SDHCI_HOST_VERSION)) {
395                 reg ^= 2;
396                 if (esdhc_is_usdhc(imx_data)) {
397                         /*
398                          * The usdhc register returns a wrong host version.
399                          * Correct it here.
400                          */
401                         return SDHCI_SPEC_300;
402                 }
403         }
404 
405         if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
406                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
407                 if (val & ESDHC_VENDOR_SPEC_VSELECT)
408                         ret |= SDHCI_CTRL_VDD_180;
409 
410                 if (esdhc_is_usdhc(imx_data)) {
411                         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
412                                 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
413                         else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
414                                 /* the std tuning bits is in ACMD12_ERR for imx6sl */
415                                 val = readl(host->ioaddr + SDHCI_ACMD12_ERR);
416                 }
417 
418                 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
419                         ret |= SDHCI_CTRL_EXEC_TUNING;
420                 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
421                         ret |= SDHCI_CTRL_TUNED_CLK;
422 
423                 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
424 
425                 return ret;
426         }
427 
428         if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
429                 if (esdhc_is_usdhc(imx_data)) {
430                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
431                         ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
432                         /* Swap AC23 bit */
433                         if (m & ESDHC_MIX_CTRL_AC23EN) {
434                                 ret &= ~ESDHC_MIX_CTRL_AC23EN;
435                                 ret |= SDHCI_TRNS_AUTO_CMD23;
436                         }
437                 } else {
438                         ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
439                 }
440 
441                 return ret;
442         }
443 
444         return readw(host->ioaddr + reg);
445 }
446 
447 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
448 {
449         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
450         struct pltfm_imx_data *imx_data = pltfm_host->priv;
451         u32 new_val = 0;
452 
453         switch (reg) {
454         case SDHCI_CLOCK_CONTROL:
455                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
456                 if (val & SDHCI_CLOCK_CARD_EN)
457                         new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
458                 else
459                         new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
460                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
461                 return;
462         case SDHCI_HOST_CONTROL2:
463                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
464                 if (val & SDHCI_CTRL_VDD_180)
465                         new_val |= ESDHC_VENDOR_SPEC_VSELECT;
466                 else
467                         new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
468                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
469                 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
470                         new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
471                         if (val & SDHCI_CTRL_TUNED_CLK)
472                                 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
473                         else
474                                 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
475                         writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
476                 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
477                         u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);
478                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
479                         u32 tuning_ctrl;
480                         if (val & SDHCI_CTRL_TUNED_CLK) {
481                                 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
482                         } else {
483                                 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
484                                 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
485                         }
486 
487                         if (val & SDHCI_CTRL_EXEC_TUNING) {
488                                 v |= ESDHC_MIX_CTRL_EXE_TUNE;
489                                 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
490                                 tuning_ctrl = readl(host->ioaddr + ESDHC_TUNING_CTRL);
491                                 tuning_ctrl |= ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP;
492                                 if (imx_data->boarddata.tuning_step)
493                                         tuning_ctrl |= imx_data->boarddata.tuning_step << ESDHC_TUNING_STEP_SHIFT;
494                                         writel(tuning_ctrl, host->ioaddr + ESDHC_TUNING_CTRL);
495                         } else {
496                                 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
497                         }
498 
499                         writel(v, host->ioaddr + SDHCI_ACMD12_ERR);
500                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
501                 }
502                 return;
503         case SDHCI_TRANSFER_MODE:
504                 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
505                                 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
506                                 && (host->cmd->data->blocks > 1)
507                                 && (host->cmd->data->flags & MMC_DATA_READ)) {
508                         u32 v;
509                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
510                         v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
511                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
512                 }
513 
514                 if (esdhc_is_usdhc(imx_data)) {
515                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
516                         /* Swap AC23 bit */
517                         if (val & SDHCI_TRNS_AUTO_CMD23) {
518                                 val &= ~SDHCI_TRNS_AUTO_CMD23;
519                                 val |= ESDHC_MIX_CTRL_AC23EN;
520                         }
521                         m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
522                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
523                 } else {
524                         /*
525                          * Postpone this write, we must do it together with a
526                          * command write that is down below.
527                          */
528                         imx_data->scratchpad = val;
529                 }
530                 return;
531         case SDHCI_COMMAND:
532                 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
533                         val |= SDHCI_CMD_ABORTCMD;
534 
535                 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
536                     (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
537                         imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
538 
539                 if (esdhc_is_usdhc(imx_data))
540                         writel(val << 16,
541                                host->ioaddr + SDHCI_TRANSFER_MODE);
542                 else
543                         writel(val << 16 | imx_data->scratchpad,
544                                host->ioaddr + SDHCI_TRANSFER_MODE);
545                 return;
546         case SDHCI_BLOCK_SIZE:
547                 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
548                 break;
549         }
550         esdhc_clrset_le(host, 0xffff, val, reg);
551 }
552 
553 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
554 {
555         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
556         struct pltfm_imx_data *imx_data = pltfm_host->priv;
557         u32 new_val;
558         u32 mask;
559 
560         switch (reg) {
561         case SDHCI_POWER_CONTROL:
562                 /*
563                  * FSL put some DMA bits here
564                  * If your board has a regulator, code should be here
565                  */
566                 return;
567         case SDHCI_HOST_CONTROL:
568                 /* FSL messed up here, so we need to manually compose it. */
569                 new_val = val & SDHCI_CTRL_LED;
570                 /* ensure the endianness */
571                 new_val |= ESDHC_HOST_CONTROL_LE;
572                 /* bits 8&9 are reserved on mx25 */
573                 if (!is_imx25_esdhc(imx_data)) {
574                         /* DMA mode bits are shifted */
575                         new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
576                 }
577 
578                 /*
579                  * Do not touch buswidth bits here. This is done in
580                  * esdhc_pltfm_bus_width.
581                  * Do not touch the D3CD bit either which is used for the
582                  * SDIO interrupt errata workaround.
583                  */
584                 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
585 
586                 esdhc_clrset_le(host, mask, new_val, reg);
587                 return;
588         }
589         esdhc_clrset_le(host, 0xff, val, reg);
590 
591         /*
592          * The esdhc has a design violation to SDHC spec which tells
593          * that software reset should not affect card detection circuit.
594          * But esdhc clears its SYSCTL register bits [0..2] during the
595          * software reset.  This will stop those clocks that card detection
596          * circuit relies on.  To work around it, we turn the clocks on back
597          * to keep card detection circuit functional.
598          */
599         if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) {
600                 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
601                 /*
602                  * The reset on usdhc fails to clear MIX_CTRL register.
603                  * Do it manually here.
604                  */
605                 if (esdhc_is_usdhc(imx_data)) {
606                         /* the tuning bits should be kept during reset */
607                         new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
608                         writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
609                                         host->ioaddr + ESDHC_MIX_CTRL);
610                         imx_data->is_ddr = 0;
611                 }
612         }
613 }
614 
615 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
616 {
617         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
618 
619         return pltfm_host->clock;
620 }
621 
622 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
623 {
624         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
625 
626         return pltfm_host->clock / 256 / 16;
627 }
628 
629 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
630                                          unsigned int clock)
631 {
632         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
633         struct pltfm_imx_data *imx_data = pltfm_host->priv;
634         unsigned int host_clock = pltfm_host->clock;
635         int pre_div = 2;
636         int div = 1;
637         u32 temp, val;
638 
639         if (clock == 0) {
640                 host->mmc->actual_clock = 0;
641 
642                 if (esdhc_is_usdhc(imx_data)) {
643                         val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
644                         writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
645                                         host->ioaddr + ESDHC_VENDOR_SPEC);
646                 }
647                 return;
648         }
649 
650         if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr)
651                 pre_div = 1;
652 
653         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
654         temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
655                 | ESDHC_CLOCK_MASK);
656         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
657 
658         while (host_clock / pre_div / 16 > clock && pre_div < 256)
659                 pre_div *= 2;
660 
661         while (host_clock / pre_div / div > clock && div < 16)
662                 div++;
663 
664         host->mmc->actual_clock = host_clock / pre_div / div;
665         dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
666                 clock, host->mmc->actual_clock);
667 
668         if (imx_data->is_ddr)
669                 pre_div >>= 2;
670         else
671                 pre_div >>= 1;
672         div--;
673 
674         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
675         temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
676                 | (div << ESDHC_DIVIDER_SHIFT)
677                 | (pre_div << ESDHC_PREDIV_SHIFT));
678         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
679 
680         if (esdhc_is_usdhc(imx_data)) {
681                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
682                 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
683                 host->ioaddr + ESDHC_VENDOR_SPEC);
684         }
685 
686         mdelay(1);
687 }
688 
689 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
690 {
691         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
692         struct pltfm_imx_data *imx_data = pltfm_host->priv;
693         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
694 
695         switch (boarddata->wp_type) {
696         case ESDHC_WP_GPIO:
697                 return mmc_gpio_get_ro(host->mmc);
698         case ESDHC_WP_CONTROLLER:
699                 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
700                                SDHCI_WRITE_PROTECT);
701         case ESDHC_WP_NONE:
702                 break;
703         }
704 
705         return -ENOSYS;
706 }
707 
708 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
709 {
710         u32 ctrl;
711 
712         switch (width) {
713         case MMC_BUS_WIDTH_8:
714                 ctrl = ESDHC_CTRL_8BITBUS;
715                 break;
716         case MMC_BUS_WIDTH_4:
717                 ctrl = ESDHC_CTRL_4BITBUS;
718                 break;
719         default:
720                 ctrl = 0;
721                 break;
722         }
723 
724         esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
725                         SDHCI_HOST_CONTROL);
726 }
727 
728 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
729 {
730         u32 reg;
731 
732         /* FIXME: delay a bit for card to be ready for next tuning due to errors */
733         mdelay(1);
734 
735         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
736         reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
737                         ESDHC_MIX_CTRL_FBCLK_SEL;
738         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
739         writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
740         dev_dbg(mmc_dev(host->mmc),
741                 "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
742                         val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
743 }
744 
745 static void esdhc_post_tuning(struct sdhci_host *host)
746 {
747         u32 reg;
748 
749         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
750         reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
751         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
752 }
753 
754 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
755 {
756         int min, max, avg, ret;
757 
758         /* find the mininum delay first which can pass tuning */
759         min = ESDHC_TUNE_CTRL_MIN;
760         while (min < ESDHC_TUNE_CTRL_MAX) {
761                 esdhc_prepare_tuning(host, min);
762                 if (!mmc_send_tuning(host->mmc, opcode, NULL))
763                         break;
764                 min += ESDHC_TUNE_CTRL_STEP;
765         }
766 
767         /* find the maxinum delay which can not pass tuning */
768         max = min + ESDHC_TUNE_CTRL_STEP;
769         while (max < ESDHC_TUNE_CTRL_MAX) {
770                 esdhc_prepare_tuning(host, max);
771                 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
772                         max -= ESDHC_TUNE_CTRL_STEP;
773                         break;
774                 }
775                 max += ESDHC_TUNE_CTRL_STEP;
776         }
777 
778         /* use average delay to get the best timing */
779         avg = (min + max) / 2;
780         esdhc_prepare_tuning(host, avg);
781         ret = mmc_send_tuning(host->mmc, opcode, NULL);
782         esdhc_post_tuning(host);
783 
784         dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n",
785                 ret ? "failed" : "passed", avg, ret);
786 
787         return ret;
788 }
789 
790 static int esdhc_change_pinstate(struct sdhci_host *host,
791                                                 unsigned int uhs)
792 {
793         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
794         struct pltfm_imx_data *imx_data = pltfm_host->priv;
795         struct pinctrl_state *pinctrl;
796 
797         dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
798 
799         if (IS_ERR(imx_data->pinctrl) ||
800                 IS_ERR(imx_data->pins_default) ||
801                 IS_ERR(imx_data->pins_100mhz) ||
802                 IS_ERR(imx_data->pins_200mhz))
803                 return -EINVAL;
804 
805         switch (uhs) {
806         case MMC_TIMING_UHS_SDR50:
807                 pinctrl = imx_data->pins_100mhz;
808                 break;
809         case MMC_TIMING_UHS_SDR104:
810         case MMC_TIMING_MMC_HS200:
811         case MMC_TIMING_MMC_HS400:
812                 pinctrl = imx_data->pins_200mhz;
813                 break;
814         default:
815                 /* back to default state for other legacy timing */
816                 pinctrl = imx_data->pins_default;
817         }
818 
819         return pinctrl_select_state(imx_data->pinctrl, pinctrl);
820 }
821 
822 /*
823  * For HS400 eMMC, there is a data_strobe line, this signal is generated
824  * by the device and used for data output and CRC status response output
825  * in HS400 mode. The frequency of this signal follows the frequency of
826  * CLK generated by host. Host receive the data which is aligned to the
827  * edge of data_strobe line. Due to the time delay between CLK line and
828  * data_strobe line, if the delay time is larger than one clock cycle,
829  * then CLK and data_strobe line will misaligned, read error shows up.
830  * So when the CLK is higher than 100MHz, each clock cycle is short enough,
831  * host should config the delay target.
832  */
833 static void esdhc_set_strobe_dll(struct sdhci_host *host)
834 {
835         u32 v;
836 
837         if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) {
838                 /* force a reset on strobe dll */
839                 writel(ESDHC_STROBE_DLL_CTRL_RESET,
840                         host->ioaddr + ESDHC_STROBE_DLL_CTRL);
841                 /*
842                  * enable strobe dll ctrl and adjust the delay target
843                  * for the uSDHC loopback read clock
844                  */
845                 v = ESDHC_STROBE_DLL_CTRL_ENABLE |
846                         (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
847                 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
848                 /* wait 1us to make sure strobe dll status register stable */
849                 udelay(1);
850                 v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS);
851                 if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK))
852                         dev_warn(mmc_dev(host->mmc),
853                                 "warning! HS400 strobe DLL status REF not lock!\n");
854                 if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK))
855                         dev_warn(mmc_dev(host->mmc),
856                                 "warning! HS400 strobe DLL status SLV not lock!\n");
857         }
858 }
859 
860 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
861 {
862         u32 m;
863         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
864         struct pltfm_imx_data *imx_data = pltfm_host->priv;
865         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
866 
867         /* disable ddr mode and disable HS400 mode */
868         m = readl(host->ioaddr + ESDHC_MIX_CTRL);
869         m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
870         imx_data->is_ddr = 0;
871 
872         switch (timing) {
873         case MMC_TIMING_UHS_SDR12:
874         case MMC_TIMING_UHS_SDR25:
875         case MMC_TIMING_UHS_SDR50:
876         case MMC_TIMING_UHS_SDR104:
877         case MMC_TIMING_MMC_HS200:
878                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
879                 break;
880         case MMC_TIMING_UHS_DDR50:
881         case MMC_TIMING_MMC_DDR52:
882                 m |= ESDHC_MIX_CTRL_DDREN;
883                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
884                 imx_data->is_ddr = 1;
885                 if (boarddata->delay_line) {
886                         u32 v;
887                         v = boarddata->delay_line <<
888                                 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
889                                 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
890                         if (is_imx53_esdhc(imx_data))
891                                 v <<= 1;
892                         writel(v, host->ioaddr + ESDHC_DLL_CTRL);
893                 }
894                 break;
895         case MMC_TIMING_MMC_HS400:
896                 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
897                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
898                 imx_data->is_ddr = 1;
899                 esdhc_set_strobe_dll(host);
900                 break;
901         }
902 
903         esdhc_change_pinstate(host, timing);
904 }
905 
906 static void esdhc_reset(struct sdhci_host *host, u8 mask)
907 {
908         sdhci_reset(host, mask);
909 
910         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
911         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
912 }
913 
914 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
915 {
916         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
917         struct pltfm_imx_data *imx_data = pltfm_host->priv;
918 
919         return esdhc_is_usdhc(imx_data) ? 1 << 28 : 1 << 27;
920 }
921 
922 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
923 {
924         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
925         struct pltfm_imx_data *imx_data = pltfm_host->priv;
926 
927         /* use maximum timeout counter */
928         sdhci_writeb(host, esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
929                         SDHCI_TIMEOUT_CONTROL);
930 }
931 
932 static struct sdhci_ops sdhci_esdhc_ops = {
933         .read_l = esdhc_readl_le,
934         .read_w = esdhc_readw_le,
935         .write_l = esdhc_writel_le,
936         .write_w = esdhc_writew_le,
937         .write_b = esdhc_writeb_le,
938         .set_clock = esdhc_pltfm_set_clock,
939         .get_max_clock = esdhc_pltfm_get_max_clock,
940         .get_min_clock = esdhc_pltfm_get_min_clock,
941         .get_max_timeout_count = esdhc_get_max_timeout_count,
942         .get_ro = esdhc_pltfm_get_ro,
943         .set_timeout = esdhc_set_timeout,
944         .set_bus_width = esdhc_pltfm_set_bus_width,
945         .set_uhs_signaling = esdhc_set_uhs_signaling,
946         .reset = esdhc_reset,
947 };
948 
949 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
950         .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
951                         | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
952                         | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
953                         | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
954         .ops = &sdhci_esdhc_ops,
955 };
956 
957 #ifdef CONFIG_OF
958 static int
959 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
960                          struct sdhci_host *host,
961                          struct pltfm_imx_data *imx_data)
962 {
963         struct device_node *np = pdev->dev.of_node;
964         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
965         int ret;
966 
967         if (of_get_property(np, "fsl,wp-controller", NULL))
968                 boarddata->wp_type = ESDHC_WP_CONTROLLER;
969 
970         boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
971         if (gpio_is_valid(boarddata->wp_gpio))
972                 boarddata->wp_type = ESDHC_WP_GPIO;
973 
974         of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
975 
976         if (of_find_property(np, "no-1-8-v", NULL))
977                 boarddata->support_vsel = false;
978         else
979                 boarddata->support_vsel = true;
980 
981         if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
982                 boarddata->delay_line = 0;
983 
984         mmc_of_parse_voltage(np, &host->ocr_mask);
985 
986         /* sdr50 and sdr104 needs work on 1.8v signal voltage */
987         if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) &&
988             !IS_ERR(imx_data->pins_default)) {
989                 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
990                                                 ESDHC_PINCTRL_STATE_100MHZ);
991                 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
992                                                 ESDHC_PINCTRL_STATE_200MHZ);
993                 if (IS_ERR(imx_data->pins_100mhz) ||
994                                 IS_ERR(imx_data->pins_200mhz)) {
995                         dev_warn(mmc_dev(host->mmc),
996                                 "could not get ultra high speed state, work on normal mode\n");
997                         /*
998                          * fall back to not support uhs by specify no 1.8v quirk
999                          */
1000                         host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1001                 }
1002         } else {
1003                 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1004         }
1005 
1006         /* call to generic mmc_of_parse to support additional capabilities */
1007         ret = mmc_of_parse(host->mmc);
1008         if (ret)
1009                 return ret;
1010 
1011         if (!IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
1012                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1013 
1014         return 0;
1015 }
1016 #else
1017 static inline int
1018 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1019                          struct sdhci_host *host,
1020                          struct pltfm_imx_data *imx_data)
1021 {
1022         return -ENODEV;
1023 }
1024 #endif
1025 
1026 static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev,
1027                          struct sdhci_host *host,
1028                          struct pltfm_imx_data *imx_data)
1029 {
1030         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1031         int err;
1032 
1033         if (!host->mmc->parent->platform_data) {
1034                 dev_err(mmc_dev(host->mmc), "no board data!\n");
1035                 return -EINVAL;
1036         }
1037 
1038         imx_data->boarddata = *((struct esdhc_platform_data *)
1039                                 host->mmc->parent->platform_data);
1040         /* write_protect */
1041         if (boarddata->wp_type == ESDHC_WP_GPIO) {
1042                 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
1043                 if (err) {
1044                         dev_err(mmc_dev(host->mmc),
1045                                 "failed to request write-protect gpio!\n");
1046                         return err;
1047                 }
1048                 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1049         }
1050 
1051         /* card_detect */
1052         switch (boarddata->cd_type) {
1053         case ESDHC_CD_GPIO:
1054                 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
1055                 if (err) {
1056                         dev_err(mmc_dev(host->mmc),
1057                                 "failed to request card-detect gpio!\n");
1058                         return err;
1059                 }
1060                 /* fall through */
1061 
1062         case ESDHC_CD_CONTROLLER:
1063                 /* we have a working card_detect back */
1064                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1065                 break;
1066 
1067         case ESDHC_CD_PERMANENT:
1068                 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
1069                 break;
1070 
1071         case ESDHC_CD_NONE:
1072                 break;
1073         }
1074 
1075         switch (boarddata->max_bus_width) {
1076         case 8:
1077                 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
1078                 break;
1079         case 4:
1080                 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
1081                 break;
1082         case 1:
1083         default:
1084                 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1085                 break;
1086         }
1087 
1088         return 0;
1089 }
1090 
1091 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1092 {
1093         const struct of_device_id *of_id =
1094                         of_match_device(imx_esdhc_dt_ids, &pdev->dev);
1095         struct sdhci_pltfm_host *pltfm_host;
1096         struct sdhci_host *host;
1097         int err;
1098         struct pltfm_imx_data *imx_data;
1099 
1100         host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0);
1101         if (IS_ERR(host))
1102                 return PTR_ERR(host);
1103 
1104         pltfm_host = sdhci_priv(host);
1105 
1106         imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL);
1107         if (!imx_data) {
1108                 err = -ENOMEM;
1109                 goto free_sdhci;
1110         }
1111 
1112         imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
1113                                                   pdev->id_entry->driver_data;
1114         pltfm_host->priv = imx_data;
1115 
1116         imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1117         if (IS_ERR(imx_data->clk_ipg)) {
1118                 err = PTR_ERR(imx_data->clk_ipg);
1119                 goto free_sdhci;
1120         }
1121 
1122         imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1123         if (IS_ERR(imx_data->clk_ahb)) {
1124                 err = PTR_ERR(imx_data->clk_ahb);
1125                 goto free_sdhci;
1126         }
1127 
1128         imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1129         if (IS_ERR(imx_data->clk_per)) {
1130                 err = PTR_ERR(imx_data->clk_per);
1131                 goto free_sdhci;
1132         }
1133 
1134         pltfm_host->clk = imx_data->clk_per;
1135         pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1136         clk_prepare_enable(imx_data->clk_per);
1137         clk_prepare_enable(imx_data->clk_ipg);
1138         clk_prepare_enable(imx_data->clk_ahb);
1139 
1140         imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1141         if (IS_ERR(imx_data->pinctrl)) {
1142                 err = PTR_ERR(imx_data->pinctrl);
1143                 goto disable_clk;
1144         }
1145 
1146         imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
1147                                                 PINCTRL_STATE_DEFAULT);
1148         if (IS_ERR(imx_data->pins_default))
1149                 dev_warn(mmc_dev(host->mmc), "could not get default state\n");
1150 
1151         host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
1152 
1153         if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207)
1154                 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
1155                 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
1156                         | SDHCI_QUIRK_BROKEN_ADMA;
1157 
1158         /*
1159          * The imx6q ROM code will change the default watermark level setting
1160          * to something insane.  Change it back here.
1161          */
1162         if (esdhc_is_usdhc(imx_data)) {
1163                 writel(0x10401040, host->ioaddr + ESDHC_WTMK_LVL);
1164 
1165                 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1166                 host->mmc->caps |= MMC_CAP_1_8V_DDR;
1167 
1168                 /*
1169                  * ROM code will change the bit burst_length_enable setting
1170                  * to zero if this usdhc is choosed to boot system. Change
1171                  * it back here, otherwise it will impact the performance a
1172                  * lot. This bit is used to enable/disable the burst length
1173                  * for the external AHB2AXI bridge, it's usefully especially
1174                  * for INCR transfer because without burst length indicator,
1175                  * the AHB2AXI bridge does not know the burst length in
1176                  * advance. And without burst length indicator, AHB INCR
1177                  * transfer can only be converted to singles on the AXI side.
1178                  */
1179                 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1180                         | ESDHC_BURST_LEN_EN_INCR,
1181                         host->ioaddr + SDHCI_HOST_CONTROL);
1182 
1183                 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1184                         host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1185 
1186                 /*
1187                 * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1188                 * TO1.1, it's harmless for MX6SL
1189                 */
1190                 writel(readl(host->ioaddr + 0x6c) | BIT(7),
1191                         host->ioaddr + 0x6c);
1192         }
1193 
1194         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1195                 sdhci_esdhc_ops.platform_execute_tuning =
1196                                         esdhc_executing_tuning;
1197 
1198         if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
1199                 writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) |
1200                         ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP,
1201                         host->ioaddr + ESDHC_TUNING_CTRL);
1202 
1203         if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1204                 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1205 
1206         if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
1207                 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
1208 
1209         if (of_id)
1210                 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1211         else
1212                 err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data);
1213         if (err)
1214                 goto disable_clk;
1215 
1216         err = sdhci_add_host(host);
1217         if (err)
1218                 goto disable_clk;
1219 
1220         pm_runtime_set_active(&pdev->dev);
1221         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1222         pm_runtime_use_autosuspend(&pdev->dev);
1223         pm_suspend_ignore_children(&pdev->dev, 1);
1224         pm_runtime_enable(&pdev->dev);
1225 
1226         return 0;
1227 
1228 disable_clk:
1229         clk_disable_unprepare(imx_data->clk_per);
1230         clk_disable_unprepare(imx_data->clk_ipg);
1231         clk_disable_unprepare(imx_data->clk_ahb);
1232 free_sdhci:
1233         sdhci_pltfm_free(pdev);
1234         return err;
1235 }
1236 
1237 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1238 {
1239         struct sdhci_host *host = platform_get_drvdata(pdev);
1240         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1241         struct pltfm_imx_data *imx_data = pltfm_host->priv;
1242         int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1243 
1244         pm_runtime_get_sync(&pdev->dev);
1245         pm_runtime_disable(&pdev->dev);
1246         pm_runtime_put_noidle(&pdev->dev);
1247 
1248         sdhci_remove_host(host, dead);
1249 
1250         clk_disable_unprepare(imx_data->clk_per);
1251         clk_disable_unprepare(imx_data->clk_ipg);
1252         clk_disable_unprepare(imx_data->clk_ahb);
1253 
1254         sdhci_pltfm_free(pdev);
1255 
1256         return 0;
1257 }
1258 
1259 #ifdef CONFIG_PM
1260 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1261 {
1262         struct sdhci_host *host = dev_get_drvdata(dev);
1263         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1264         struct pltfm_imx_data *imx_data = pltfm_host->priv;
1265         int ret;
1266 
1267         ret = sdhci_runtime_suspend_host(host);
1268 
1269         if (!sdhci_sdio_irq_enabled(host)) {
1270                 clk_disable_unprepare(imx_data->clk_per);
1271                 clk_disable_unprepare(imx_data->clk_ipg);
1272         }
1273         clk_disable_unprepare(imx_data->clk_ahb);
1274 
1275         return ret;
1276 }
1277 
1278 static int sdhci_esdhc_runtime_resume(struct device *dev)
1279 {
1280         struct sdhci_host *host = dev_get_drvdata(dev);
1281         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1282         struct pltfm_imx_data *imx_data = pltfm_host->priv;
1283 
1284         if (!sdhci_sdio_irq_enabled(host)) {
1285                 clk_prepare_enable(imx_data->clk_per);
1286                 clk_prepare_enable(imx_data->clk_ipg);
1287         }
1288         clk_prepare_enable(imx_data->clk_ahb);
1289 
1290         return sdhci_runtime_resume_host(host);
1291 }
1292 #endif
1293 
1294 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1295         SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_pltfm_resume)
1296         SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1297                                 sdhci_esdhc_runtime_resume, NULL)
1298 };
1299 
1300 static struct platform_driver sdhci_esdhc_imx_driver = {
1301         .driver         = {
1302                 .name   = "sdhci-esdhc-imx",
1303                 .of_match_table = imx_esdhc_dt_ids,
1304                 .pm     = &sdhci_esdhc_pmops,
1305         },
1306         .id_table       = imx_esdhc_devtype,
1307         .probe          = sdhci_esdhc_imx_probe,
1308         .remove         = sdhci_esdhc_imx_remove,
1309 };
1310 
1311 module_platform_driver(sdhci_esdhc_imx_driver);
1312 
1313 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1314 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1315 MODULE_LICENSE("GPL v2");
1316 

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