Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5

Linux/drivers/mmc/host/sdhci-esdhc-imx.c

  1 /*
  2  * Freescale eSDHC i.MX controller driver for the platform bus.
  3  *
  4  * derived from the OF-version.
  5  *
  6  * Copyright (c) 2010 Pengutronix e.K.
  7  *   Author: Wolfram Sang <kernel@pengutronix.de>
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License as published by
 11  * the Free Software Foundation; either version 2 of the License.
 12  */
 13 
 14 #include <linux/io.h>
 15 #include <linux/delay.h>
 16 #include <linux/err.h>
 17 #include <linux/clk.h>
 18 #include <linux/gpio.h>
 19 #include <linux/module.h>
 20 #include <linux/slab.h>
 21 #include <linux/mmc/host.h>
 22 #include <linux/mmc/mmc.h>
 23 #include <linux/mmc/sdio.h>
 24 #include <linux/mmc/slot-gpio.h>
 25 #include <linux/of.h>
 26 #include <linux/of_device.h>
 27 #include <linux/of_gpio.h>
 28 #include <linux/pinctrl/consumer.h>
 29 #include <linux/platform_data/mmc-esdhc-imx.h>
 30 #include <linux/pm_runtime.h>
 31 #include "sdhci-pltfm.h"
 32 #include "sdhci-esdhc.h"
 33 
 34 #define ESDHC_CTRL_D3CD                 0x08
 35 #define ESDHC_BURST_LEN_EN_INCR         (1 << 27)
 36 /* VENDOR SPEC register */
 37 #define ESDHC_VENDOR_SPEC               0xc0
 38 #define  ESDHC_VENDOR_SPEC_SDIO_QUIRK   (1 << 1)
 39 #define  ESDHC_VENDOR_SPEC_VSELECT      (1 << 1)
 40 #define  ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
 41 #define ESDHC_WTMK_LVL                  0x44
 42 #define ESDHC_MIX_CTRL                  0x48
 43 #define  ESDHC_MIX_CTRL_DDREN           (1 << 3)
 44 #define  ESDHC_MIX_CTRL_AC23EN          (1 << 7)
 45 #define  ESDHC_MIX_CTRL_EXE_TUNE        (1 << 22)
 46 #define  ESDHC_MIX_CTRL_SMPCLK_SEL      (1 << 23)
 47 #define  ESDHC_MIX_CTRL_FBCLK_SEL       (1 << 25)
 48 #define  ESDHC_MIX_CTRL_HS400_EN        (1 << 26)
 49 /* Bits 3 and 6 are not SDHCI standard definitions */
 50 #define  ESDHC_MIX_CTRL_SDHCI_MASK      0xb7
 51 /* Tuning bits */
 52 #define  ESDHC_MIX_CTRL_TUNING_MASK     0x03c00000
 53 
 54 /* dll control register */
 55 #define ESDHC_DLL_CTRL                  0x60
 56 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT    9
 57 #define ESDHC_DLL_OVERRIDE_EN_SHIFT     8
 58 
 59 /* tune control register */
 60 #define ESDHC_TUNE_CTRL_STATUS          0x68
 61 #define  ESDHC_TUNE_CTRL_STEP           1
 62 #define  ESDHC_TUNE_CTRL_MIN            0
 63 #define  ESDHC_TUNE_CTRL_MAX            ((1 << 7) - 1)
 64 
 65 /* strobe dll register */
 66 #define ESDHC_STROBE_DLL_CTRL           0x70
 67 #define ESDHC_STROBE_DLL_CTRL_ENABLE    (1 << 0)
 68 #define ESDHC_STROBE_DLL_CTRL_RESET     (1 << 1)
 69 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT      3
 70 
 71 #define ESDHC_STROBE_DLL_STATUS         0x74
 72 #define ESDHC_STROBE_DLL_STS_REF_LOCK   (1 << 1)
 73 #define ESDHC_STROBE_DLL_STS_SLV_LOCK   0x1
 74 
 75 #define ESDHC_TUNING_CTRL               0xcc
 76 #define ESDHC_STD_TUNING_EN             (1 << 24)
 77 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
 78 #define ESDHC_TUNING_START_TAP          0x1
 79 #define ESDHC_TUNING_STEP_MASK          0x00070000
 80 #define ESDHC_TUNING_STEP_SHIFT         16
 81 
 82 /* pinctrl state */
 83 #define ESDHC_PINCTRL_STATE_100MHZ      "state_100mhz"
 84 #define ESDHC_PINCTRL_STATE_200MHZ      "state_200mhz"
 85 
 86 /*
 87  * Our interpretation of the SDHCI_HOST_CONTROL register
 88  */
 89 #define ESDHC_CTRL_4BITBUS              (0x1 << 1)
 90 #define ESDHC_CTRL_8BITBUS              (0x2 << 1)
 91 #define ESDHC_CTRL_BUSWIDTH_MASK        (0x3 << 1)
 92 
 93 /*
 94  * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
 95  * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
 96  * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
 97  * Define this macro DMA error INT for fsl eSDHC
 98  */
 99 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR   (1 << 28)
100 
101 /*
102  * The CMDTYPE of the CMD register (offset 0xE) should be set to
103  * "11" when the STOP CMD12 is issued on imx53 to abort one
104  * open ended multi-blk IO. Otherwise the TC INT wouldn't
105  * be generated.
106  * In exact block transfer, the controller doesn't complete the
107  * operations automatically as required at the end of the
108  * transfer and remains on hold if the abort command is not sent.
109  * As a result, the TC flag is not asserted and SW  received timeout
110  * exeception. Bit1 of Vendor Spec registor is used to fix it.
111  */
112 #define ESDHC_FLAG_MULTIBLK_NO_INT      BIT(1)
113 /*
114  * The flag enables the workaround for ESDHC errata ENGcm07207 which
115  * affects i.MX25 and i.MX35.
116  */
117 #define ESDHC_FLAG_ENGCM07207           BIT(2)
118 /*
119  * The flag tells that the ESDHC controller is an USDHC block that is
120  * integrated on the i.MX6 series.
121  */
122 #define ESDHC_FLAG_USDHC                BIT(3)
123 /* The IP supports manual tuning process */
124 #define ESDHC_FLAG_MAN_TUNING           BIT(4)
125 /* The IP supports standard tuning process */
126 #define ESDHC_FLAG_STD_TUNING           BIT(5)
127 /* The IP has SDHCI_CAPABILITIES_1 register */
128 #define ESDHC_FLAG_HAVE_CAP1            BIT(6)
129 /*
130  * The IP has errata ERR004536
131  * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
132  * when reading data from the card
133  */
134 #define ESDHC_FLAG_ERR004536            BIT(7)
135 /* The IP supports HS200 mode */
136 #define ESDHC_FLAG_HS200                BIT(8)
137 /* The IP supports HS400 mode */
138 #define ESDHC_FLAG_HS400                BIT(9)
139 
140 /* A higher clock ferquency than this rate requires strobell dll control */
141 #define ESDHC_STROBE_DLL_CLK_FREQ       100000000
142 
143 struct esdhc_soc_data {
144         u32 flags;
145 };
146 
147 static struct esdhc_soc_data esdhc_imx25_data = {
148         .flags = ESDHC_FLAG_ENGCM07207,
149 };
150 
151 static struct esdhc_soc_data esdhc_imx35_data = {
152         .flags = ESDHC_FLAG_ENGCM07207,
153 };
154 
155 static struct esdhc_soc_data esdhc_imx51_data = {
156         .flags = 0,
157 };
158 
159 static struct esdhc_soc_data esdhc_imx53_data = {
160         .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
161 };
162 
163 static struct esdhc_soc_data usdhc_imx6q_data = {
164         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
165 };
166 
167 static struct esdhc_soc_data usdhc_imx6sl_data = {
168         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
169                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
170                         | ESDHC_FLAG_HS200,
171 };
172 
173 static struct esdhc_soc_data usdhc_imx6sx_data = {
174         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
175                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
176 };
177 
178 static struct esdhc_soc_data usdhc_imx7d_data = {
179         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
180                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
181                         | ESDHC_FLAG_HS400,
182 };
183 
184 struct pltfm_imx_data {
185         u32 scratchpad;
186         struct pinctrl *pinctrl;
187         struct pinctrl_state *pins_default;
188         struct pinctrl_state *pins_100mhz;
189         struct pinctrl_state *pins_200mhz;
190         const struct esdhc_soc_data *socdata;
191         struct esdhc_platform_data boarddata;
192         struct clk *clk_ipg;
193         struct clk *clk_ahb;
194         struct clk *clk_per;
195         enum {
196                 NO_CMD_PENDING,      /* no multiblock command pending*/
197                 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
198                 WAIT_FOR_INT,        /* sent CMD12, waiting for response INT */
199         } multiblock_status;
200         u32 is_ddr;
201 };
202 
203 static const struct platform_device_id imx_esdhc_devtype[] = {
204         {
205                 .name = "sdhci-esdhc-imx25",
206                 .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
207         }, {
208                 .name = "sdhci-esdhc-imx35",
209                 .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
210         }, {
211                 .name = "sdhci-esdhc-imx51",
212                 .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
213         }, {
214                 /* sentinel */
215         }
216 };
217 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
218 
219 static const struct of_device_id imx_esdhc_dt_ids[] = {
220         { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
221         { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
222         { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
223         { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
224         { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
225         { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
226         { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
227         { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
228         { /* sentinel */ }
229 };
230 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
231 
232 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
233 {
234         return data->socdata == &esdhc_imx25_data;
235 }
236 
237 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
238 {
239         return data->socdata == &esdhc_imx53_data;
240 }
241 
242 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
243 {
244         return data->socdata == &usdhc_imx6q_data;
245 }
246 
247 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
248 {
249         return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
250 }
251 
252 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
253 {
254         void __iomem *base = host->ioaddr + (reg & ~0x3);
255         u32 shift = (reg & 0x3) * 8;
256 
257         writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
258 }
259 
260 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
261 {
262         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
263         struct pltfm_imx_data *imx_data = pltfm_host->priv;
264         u32 val = readl(host->ioaddr + reg);
265 
266         if (unlikely(reg == SDHCI_PRESENT_STATE)) {
267                 u32 fsl_prss = val;
268                 /* save the least 20 bits */
269                 val = fsl_prss & 0x000FFFFF;
270                 /* move dat[0-3] bits */
271                 val |= (fsl_prss & 0x0F000000) >> 4;
272                 /* move cmd line bit */
273                 val |= (fsl_prss & 0x00800000) << 1;
274         }
275 
276         if (unlikely(reg == SDHCI_CAPABILITIES)) {
277                 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
278                 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
279                         val &= 0xffff0000;
280 
281                 /* In FSL esdhc IC module, only bit20 is used to indicate the
282                  * ADMA2 capability of esdhc, but this bit is messed up on
283                  * some SOCs (e.g. on MX25, MX35 this bit is set, but they
284                  * don't actually support ADMA2). So set the BROKEN_ADMA
285                  * uirk on MX25/35 platforms.
286                  */
287 
288                 if (val & SDHCI_CAN_DO_ADMA1) {
289                         val &= ~SDHCI_CAN_DO_ADMA1;
290                         val |= SDHCI_CAN_DO_ADMA2;
291                 }
292         }
293 
294         if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
295                 if (esdhc_is_usdhc(imx_data)) {
296                         if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
297                                 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
298                         else
299                                 /* imx6q/dl does not have cap_1 register, fake one */
300                                 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
301                                         | SDHCI_SUPPORT_SDR50
302                                         | SDHCI_USE_SDR50_TUNING;
303 
304                         if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
305                                 val |= SDHCI_SUPPORT_HS400;
306                 }
307         }
308 
309         if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
310                 val = 0;
311                 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
312                 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
313                 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
314         }
315 
316         if (unlikely(reg == SDHCI_INT_STATUS)) {
317                 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
318                         val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
319                         val |= SDHCI_INT_ADMA_ERROR;
320                 }
321 
322                 /*
323                  * mask off the interrupt we get in response to the manually
324                  * sent CMD12
325                  */
326                 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
327                     ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
328                         val &= ~SDHCI_INT_RESPONSE;
329                         writel(SDHCI_INT_RESPONSE, host->ioaddr +
330                                                    SDHCI_INT_STATUS);
331                         imx_data->multiblock_status = NO_CMD_PENDING;
332                 }
333         }
334 
335         return val;
336 }
337 
338 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
339 {
340         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
341         struct pltfm_imx_data *imx_data = pltfm_host->priv;
342         u32 data;
343 
344         if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
345                 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
346                         /*
347                          * Clear and then set D3CD bit to avoid missing the
348                          * card interrupt.  This is a eSDHC controller problem
349                          * so we need to apply the following workaround: clear
350                          * and set D3CD bit will make eSDHC re-sample the card
351                          * interrupt. In case a card interrupt was lost,
352                          * re-sample it by the following steps.
353                          */
354                         data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
355                         data &= ~ESDHC_CTRL_D3CD;
356                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
357                         data |= ESDHC_CTRL_D3CD;
358                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
359                 }
360 
361                 if (val & SDHCI_INT_ADMA_ERROR) {
362                         val &= ~SDHCI_INT_ADMA_ERROR;
363                         val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
364                 }
365         }
366 
367         if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
368                                 && (reg == SDHCI_INT_STATUS)
369                                 && (val & SDHCI_INT_DATA_END))) {
370                         u32 v;
371                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
372                         v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
373                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
374 
375                         if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
376                         {
377                                 /* send a manual CMD12 with RESPTYP=none */
378                                 data = MMC_STOP_TRANSMISSION << 24 |
379                                        SDHCI_CMD_ABORTCMD << 16;
380                                 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
381                                 imx_data->multiblock_status = WAIT_FOR_INT;
382                         }
383         }
384 
385         writel(val, host->ioaddr + reg);
386 }
387 
388 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
389 {
390         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
391         struct pltfm_imx_data *imx_data = pltfm_host->priv;
392         u16 ret = 0;
393         u32 val;
394 
395         if (unlikely(reg == SDHCI_HOST_VERSION)) {
396                 reg ^= 2;
397                 if (esdhc_is_usdhc(imx_data)) {
398                         /*
399                          * The usdhc register returns a wrong host version.
400                          * Correct it here.
401                          */
402                         return SDHCI_SPEC_300;
403                 }
404         }
405 
406         if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
407                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
408                 if (val & ESDHC_VENDOR_SPEC_VSELECT)
409                         ret |= SDHCI_CTRL_VDD_180;
410 
411                 if (esdhc_is_usdhc(imx_data)) {
412                         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
413                                 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
414                         else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
415                                 /* the std tuning bits is in ACMD12_ERR for imx6sl */
416                                 val = readl(host->ioaddr + SDHCI_ACMD12_ERR);
417                 }
418 
419                 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
420                         ret |= SDHCI_CTRL_EXEC_TUNING;
421                 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
422                         ret |= SDHCI_CTRL_TUNED_CLK;
423 
424                 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
425 
426                 return ret;
427         }
428 
429         if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
430                 if (esdhc_is_usdhc(imx_data)) {
431                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
432                         ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
433                         /* Swap AC23 bit */
434                         if (m & ESDHC_MIX_CTRL_AC23EN) {
435                                 ret &= ~ESDHC_MIX_CTRL_AC23EN;
436                                 ret |= SDHCI_TRNS_AUTO_CMD23;
437                         }
438                 } else {
439                         ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
440                 }
441 
442                 return ret;
443         }
444 
445         return readw(host->ioaddr + reg);
446 }
447 
448 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
449 {
450         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
451         struct pltfm_imx_data *imx_data = pltfm_host->priv;
452         u32 new_val = 0;
453 
454         switch (reg) {
455         case SDHCI_CLOCK_CONTROL:
456                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
457                 if (val & SDHCI_CLOCK_CARD_EN)
458                         new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
459                 else
460                         new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
461                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
462                 return;
463         case SDHCI_HOST_CONTROL2:
464                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
465                 if (val & SDHCI_CTRL_VDD_180)
466                         new_val |= ESDHC_VENDOR_SPEC_VSELECT;
467                 else
468                         new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
469                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
470                 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
471                         new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
472                         if (val & SDHCI_CTRL_TUNED_CLK)
473                                 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
474                         else
475                                 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
476                         writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
477                 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
478                         u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);
479                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
480                         u32 tuning_ctrl;
481                         if (val & SDHCI_CTRL_TUNED_CLK) {
482                                 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
483                         } else {
484                                 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
485                                 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
486                         }
487 
488                         if (val & SDHCI_CTRL_EXEC_TUNING) {
489                                 v |= ESDHC_MIX_CTRL_EXE_TUNE;
490                                 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
491                                 tuning_ctrl = readl(host->ioaddr + ESDHC_TUNING_CTRL);
492                                 tuning_ctrl |= ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP;
493                                 if (imx_data->boarddata.tuning_step) {
494                                         tuning_ctrl &= ~ESDHC_TUNING_STEP_MASK;
495                                         tuning_ctrl |= imx_data->boarddata.tuning_step << ESDHC_TUNING_STEP_SHIFT;
496                                 }
497                                 writel(tuning_ctrl, host->ioaddr + ESDHC_TUNING_CTRL);
498                         } else {
499                                 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
500                         }
501 
502                         writel(v, host->ioaddr + SDHCI_ACMD12_ERR);
503                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
504                 }
505                 return;
506         case SDHCI_TRANSFER_MODE:
507                 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
508                                 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
509                                 && (host->cmd->data->blocks > 1)
510                                 && (host->cmd->data->flags & MMC_DATA_READ)) {
511                         u32 v;
512                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
513                         v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
514                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
515                 }
516 
517                 if (esdhc_is_usdhc(imx_data)) {
518                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
519                         /* Swap AC23 bit */
520                         if (val & SDHCI_TRNS_AUTO_CMD23) {
521                                 val &= ~SDHCI_TRNS_AUTO_CMD23;
522                                 val |= ESDHC_MIX_CTRL_AC23EN;
523                         }
524                         m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
525                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
526                 } else {
527                         /*
528                          * Postpone this write, we must do it together with a
529                          * command write that is down below.
530                          */
531                         imx_data->scratchpad = val;
532                 }
533                 return;
534         case SDHCI_COMMAND:
535                 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
536                         val |= SDHCI_CMD_ABORTCMD;
537 
538                 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
539                     (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
540                         imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
541 
542                 if (esdhc_is_usdhc(imx_data))
543                         writel(val << 16,
544                                host->ioaddr + SDHCI_TRANSFER_MODE);
545                 else
546                         writel(val << 16 | imx_data->scratchpad,
547                                host->ioaddr + SDHCI_TRANSFER_MODE);
548                 return;
549         case SDHCI_BLOCK_SIZE:
550                 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
551                 break;
552         }
553         esdhc_clrset_le(host, 0xffff, val, reg);
554 }
555 
556 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
557 {
558         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
559         struct pltfm_imx_data *imx_data = pltfm_host->priv;
560         u32 new_val;
561         u32 mask;
562 
563         switch (reg) {
564         case SDHCI_POWER_CONTROL:
565                 /*
566                  * FSL put some DMA bits here
567                  * If your board has a regulator, code should be here
568                  */
569                 return;
570         case SDHCI_HOST_CONTROL:
571                 /* FSL messed up here, so we need to manually compose it. */
572                 new_val = val & SDHCI_CTRL_LED;
573                 /* ensure the endianness */
574                 new_val |= ESDHC_HOST_CONTROL_LE;
575                 /* bits 8&9 are reserved on mx25 */
576                 if (!is_imx25_esdhc(imx_data)) {
577                         /* DMA mode bits are shifted */
578                         new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
579                 }
580 
581                 /*
582                  * Do not touch buswidth bits here. This is done in
583                  * esdhc_pltfm_bus_width.
584                  * Do not touch the D3CD bit either which is used for the
585                  * SDIO interrupt errata workaround.
586                  */
587                 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
588 
589                 esdhc_clrset_le(host, mask, new_val, reg);
590                 return;
591         }
592         esdhc_clrset_le(host, 0xff, val, reg);
593 
594         /*
595          * The esdhc has a design violation to SDHC spec which tells
596          * that software reset should not affect card detection circuit.
597          * But esdhc clears its SYSCTL register bits [0..2] during the
598          * software reset.  This will stop those clocks that card detection
599          * circuit relies on.  To work around it, we turn the clocks on back
600          * to keep card detection circuit functional.
601          */
602         if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) {
603                 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
604                 /*
605                  * The reset on usdhc fails to clear MIX_CTRL register.
606                  * Do it manually here.
607                  */
608                 if (esdhc_is_usdhc(imx_data)) {
609                         /* the tuning bits should be kept during reset */
610                         new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
611                         writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
612                                         host->ioaddr + ESDHC_MIX_CTRL);
613                         imx_data->is_ddr = 0;
614                 }
615         }
616 }
617 
618 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
619 {
620         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
621 
622         return pltfm_host->clock;
623 }
624 
625 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
626 {
627         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
628 
629         return pltfm_host->clock / 256 / 16;
630 }
631 
632 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
633                                          unsigned int clock)
634 {
635         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
636         struct pltfm_imx_data *imx_data = pltfm_host->priv;
637         unsigned int host_clock = pltfm_host->clock;
638         int pre_div = 2;
639         int div = 1;
640         u32 temp, val;
641 
642         if (clock == 0) {
643                 host->mmc->actual_clock = 0;
644 
645                 if (esdhc_is_usdhc(imx_data)) {
646                         val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
647                         writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
648                                         host->ioaddr + ESDHC_VENDOR_SPEC);
649                 }
650                 return;
651         }
652 
653         if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr)
654                 pre_div = 1;
655 
656         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
657         temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
658                 | ESDHC_CLOCK_MASK);
659         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
660 
661         while (host_clock / pre_div / 16 > clock && pre_div < 256)
662                 pre_div *= 2;
663 
664         while (host_clock / pre_div / div > clock && div < 16)
665                 div++;
666 
667         host->mmc->actual_clock = host_clock / pre_div / div;
668         dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
669                 clock, host->mmc->actual_clock);
670 
671         if (imx_data->is_ddr)
672                 pre_div >>= 2;
673         else
674                 pre_div >>= 1;
675         div--;
676 
677         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
678         temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
679                 | (div << ESDHC_DIVIDER_SHIFT)
680                 | (pre_div << ESDHC_PREDIV_SHIFT));
681         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
682 
683         if (esdhc_is_usdhc(imx_data)) {
684                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
685                 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
686                 host->ioaddr + ESDHC_VENDOR_SPEC);
687         }
688 
689         mdelay(1);
690 }
691 
692 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
693 {
694         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
695         struct pltfm_imx_data *imx_data = pltfm_host->priv;
696         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
697 
698         switch (boarddata->wp_type) {
699         case ESDHC_WP_GPIO:
700                 return mmc_gpio_get_ro(host->mmc);
701         case ESDHC_WP_CONTROLLER:
702                 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
703                                SDHCI_WRITE_PROTECT);
704         case ESDHC_WP_NONE:
705                 break;
706         }
707 
708         return -ENOSYS;
709 }
710 
711 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
712 {
713         u32 ctrl;
714 
715         switch (width) {
716         case MMC_BUS_WIDTH_8:
717                 ctrl = ESDHC_CTRL_8BITBUS;
718                 break;
719         case MMC_BUS_WIDTH_4:
720                 ctrl = ESDHC_CTRL_4BITBUS;
721                 break;
722         default:
723                 ctrl = 0;
724                 break;
725         }
726 
727         esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
728                         SDHCI_HOST_CONTROL);
729 }
730 
731 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
732 {
733         u32 reg;
734 
735         /* FIXME: delay a bit for card to be ready for next tuning due to errors */
736         mdelay(1);
737 
738         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
739         reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
740                         ESDHC_MIX_CTRL_FBCLK_SEL;
741         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
742         writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
743         dev_dbg(mmc_dev(host->mmc),
744                 "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
745                         val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
746 }
747 
748 static void esdhc_post_tuning(struct sdhci_host *host)
749 {
750         u32 reg;
751 
752         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
753         reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
754         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
755 }
756 
757 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
758 {
759         int min, max, avg, ret;
760 
761         /* find the mininum delay first which can pass tuning */
762         min = ESDHC_TUNE_CTRL_MIN;
763         while (min < ESDHC_TUNE_CTRL_MAX) {
764                 esdhc_prepare_tuning(host, min);
765                 if (!mmc_send_tuning(host->mmc, opcode, NULL))
766                         break;
767                 min += ESDHC_TUNE_CTRL_STEP;
768         }
769 
770         /* find the maxinum delay which can not pass tuning */
771         max = min + ESDHC_TUNE_CTRL_STEP;
772         while (max < ESDHC_TUNE_CTRL_MAX) {
773                 esdhc_prepare_tuning(host, max);
774                 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
775                         max -= ESDHC_TUNE_CTRL_STEP;
776                         break;
777                 }
778                 max += ESDHC_TUNE_CTRL_STEP;
779         }
780 
781         /* use average delay to get the best timing */
782         avg = (min + max) / 2;
783         esdhc_prepare_tuning(host, avg);
784         ret = mmc_send_tuning(host->mmc, opcode, NULL);
785         esdhc_post_tuning(host);
786 
787         dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n",
788                 ret ? "failed" : "passed", avg, ret);
789 
790         return ret;
791 }
792 
793 static int esdhc_change_pinstate(struct sdhci_host *host,
794                                                 unsigned int uhs)
795 {
796         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
797         struct pltfm_imx_data *imx_data = pltfm_host->priv;
798         struct pinctrl_state *pinctrl;
799 
800         dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
801 
802         if (IS_ERR(imx_data->pinctrl) ||
803                 IS_ERR(imx_data->pins_default) ||
804                 IS_ERR(imx_data->pins_100mhz) ||
805                 IS_ERR(imx_data->pins_200mhz))
806                 return -EINVAL;
807 
808         switch (uhs) {
809         case MMC_TIMING_UHS_SDR50:
810                 pinctrl = imx_data->pins_100mhz;
811                 break;
812         case MMC_TIMING_UHS_SDR104:
813         case MMC_TIMING_MMC_HS200:
814         case MMC_TIMING_MMC_HS400:
815                 pinctrl = imx_data->pins_200mhz;
816                 break;
817         default:
818                 /* back to default state for other legacy timing */
819                 pinctrl = imx_data->pins_default;
820         }
821 
822         return pinctrl_select_state(imx_data->pinctrl, pinctrl);
823 }
824 
825 /*
826  * For HS400 eMMC, there is a data_strobe line, this signal is generated
827  * by the device and used for data output and CRC status response output
828  * in HS400 mode. The frequency of this signal follows the frequency of
829  * CLK generated by host. Host receive the data which is aligned to the
830  * edge of data_strobe line. Due to the time delay between CLK line and
831  * data_strobe line, if the delay time is larger than one clock cycle,
832  * then CLK and data_strobe line will misaligned, read error shows up.
833  * So when the CLK is higher than 100MHz, each clock cycle is short enough,
834  * host should config the delay target.
835  */
836 static void esdhc_set_strobe_dll(struct sdhci_host *host)
837 {
838         u32 v;
839 
840         if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) {
841                 /* force a reset on strobe dll */
842                 writel(ESDHC_STROBE_DLL_CTRL_RESET,
843                         host->ioaddr + ESDHC_STROBE_DLL_CTRL);
844                 /*
845                  * enable strobe dll ctrl and adjust the delay target
846                  * for the uSDHC loopback read clock
847                  */
848                 v = ESDHC_STROBE_DLL_CTRL_ENABLE |
849                         (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
850                 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
851                 /* wait 1us to make sure strobe dll status register stable */
852                 udelay(1);
853                 v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS);
854                 if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK))
855                         dev_warn(mmc_dev(host->mmc),
856                                 "warning! HS400 strobe DLL status REF not lock!\n");
857                 if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK))
858                         dev_warn(mmc_dev(host->mmc),
859                                 "warning! HS400 strobe DLL status SLV not lock!\n");
860         }
861 }
862 
863 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
864 {
865         u32 m;
866         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
867         struct pltfm_imx_data *imx_data = pltfm_host->priv;
868         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
869 
870         /* disable ddr mode and disable HS400 mode */
871         m = readl(host->ioaddr + ESDHC_MIX_CTRL);
872         m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
873         imx_data->is_ddr = 0;
874 
875         switch (timing) {
876         case MMC_TIMING_UHS_SDR12:
877         case MMC_TIMING_UHS_SDR25:
878         case MMC_TIMING_UHS_SDR50:
879         case MMC_TIMING_UHS_SDR104:
880         case MMC_TIMING_MMC_HS200:
881                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
882                 break;
883         case MMC_TIMING_UHS_DDR50:
884         case MMC_TIMING_MMC_DDR52:
885                 m |= ESDHC_MIX_CTRL_DDREN;
886                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
887                 imx_data->is_ddr = 1;
888                 if (boarddata->delay_line) {
889                         u32 v;
890                         v = boarddata->delay_line <<
891                                 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
892                                 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
893                         if (is_imx53_esdhc(imx_data))
894                                 v <<= 1;
895                         writel(v, host->ioaddr + ESDHC_DLL_CTRL);
896                 }
897                 break;
898         case MMC_TIMING_MMC_HS400:
899                 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
900                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
901                 imx_data->is_ddr = 1;
902                 esdhc_set_strobe_dll(host);
903                 break;
904         }
905 
906         esdhc_change_pinstate(host, timing);
907 }
908 
909 static void esdhc_reset(struct sdhci_host *host, u8 mask)
910 {
911         sdhci_reset(host, mask);
912 
913         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
914         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
915 }
916 
917 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
918 {
919         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
920         struct pltfm_imx_data *imx_data = pltfm_host->priv;
921 
922         return esdhc_is_usdhc(imx_data) ? 1 << 28 : 1 << 27;
923 }
924 
925 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
926 {
927         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
928         struct pltfm_imx_data *imx_data = pltfm_host->priv;
929 
930         /* use maximum timeout counter */
931         sdhci_writeb(host, esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
932                         SDHCI_TIMEOUT_CONTROL);
933 }
934 
935 static struct sdhci_ops sdhci_esdhc_ops = {
936         .read_l = esdhc_readl_le,
937         .read_w = esdhc_readw_le,
938         .write_l = esdhc_writel_le,
939         .write_w = esdhc_writew_le,
940         .write_b = esdhc_writeb_le,
941         .set_clock = esdhc_pltfm_set_clock,
942         .get_max_clock = esdhc_pltfm_get_max_clock,
943         .get_min_clock = esdhc_pltfm_get_min_clock,
944         .get_max_timeout_count = esdhc_get_max_timeout_count,
945         .get_ro = esdhc_pltfm_get_ro,
946         .set_timeout = esdhc_set_timeout,
947         .set_bus_width = esdhc_pltfm_set_bus_width,
948         .set_uhs_signaling = esdhc_set_uhs_signaling,
949         .reset = esdhc_reset,
950 };
951 
952 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
953         .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
954                         | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
955                         | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
956                         | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
957         .ops = &sdhci_esdhc_ops,
958 };
959 
960 #ifdef CONFIG_OF
961 static int
962 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
963                          struct sdhci_host *host,
964                          struct pltfm_imx_data *imx_data)
965 {
966         struct device_node *np = pdev->dev.of_node;
967         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
968         int ret;
969 
970         if (of_get_property(np, "fsl,wp-controller", NULL))
971                 boarddata->wp_type = ESDHC_WP_CONTROLLER;
972 
973         boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
974         if (gpio_is_valid(boarddata->wp_gpio))
975                 boarddata->wp_type = ESDHC_WP_GPIO;
976 
977         of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
978 
979         if (of_find_property(np, "no-1-8-v", NULL))
980                 boarddata->support_vsel = false;
981         else
982                 boarddata->support_vsel = true;
983 
984         if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
985                 boarddata->delay_line = 0;
986 
987         mmc_of_parse_voltage(np, &host->ocr_mask);
988 
989         /* sdr50 and sdr104 needs work on 1.8v signal voltage */
990         if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) &&
991             !IS_ERR(imx_data->pins_default)) {
992                 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
993                                                 ESDHC_PINCTRL_STATE_100MHZ);
994                 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
995                                                 ESDHC_PINCTRL_STATE_200MHZ);
996                 if (IS_ERR(imx_data->pins_100mhz) ||
997                                 IS_ERR(imx_data->pins_200mhz)) {
998                         dev_warn(mmc_dev(host->mmc),
999                                 "could not get ultra high speed state, work on normal mode\n");
1000                         /*
1001                          * fall back to not support uhs by specify no 1.8v quirk
1002                          */
1003                         host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1004                 }
1005         } else {
1006                 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1007         }
1008 
1009         /* call to generic mmc_of_parse to support additional capabilities */
1010         ret = mmc_of_parse(host->mmc);
1011         if (ret)
1012                 return ret;
1013 
1014         if (!IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
1015                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1016 
1017         return 0;
1018 }
1019 #else
1020 static inline int
1021 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1022                          struct sdhci_host *host,
1023                          struct pltfm_imx_data *imx_data)
1024 {
1025         return -ENODEV;
1026 }
1027 #endif
1028 
1029 static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev,
1030                          struct sdhci_host *host,
1031                          struct pltfm_imx_data *imx_data)
1032 {
1033         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1034         int err;
1035 
1036         if (!host->mmc->parent->platform_data) {
1037                 dev_err(mmc_dev(host->mmc), "no board data!\n");
1038                 return -EINVAL;
1039         }
1040 
1041         imx_data->boarddata = *((struct esdhc_platform_data *)
1042                                 host->mmc->parent->platform_data);
1043         /* write_protect */
1044         if (boarddata->wp_type == ESDHC_WP_GPIO) {
1045                 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
1046                 if (err) {
1047                         dev_err(mmc_dev(host->mmc),
1048                                 "failed to request write-protect gpio!\n");
1049                         return err;
1050                 }
1051                 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1052         }
1053 
1054         /* card_detect */
1055         switch (boarddata->cd_type) {
1056         case ESDHC_CD_GPIO:
1057                 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
1058                 if (err) {
1059                         dev_err(mmc_dev(host->mmc),
1060                                 "failed to request card-detect gpio!\n");
1061                         return err;
1062                 }
1063                 /* fall through */
1064 
1065         case ESDHC_CD_CONTROLLER:
1066                 /* we have a working card_detect back */
1067                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1068                 break;
1069 
1070         case ESDHC_CD_PERMANENT:
1071                 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
1072                 break;
1073 
1074         case ESDHC_CD_NONE:
1075                 break;
1076         }
1077 
1078         switch (boarddata->max_bus_width) {
1079         case 8:
1080                 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
1081                 break;
1082         case 4:
1083                 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
1084                 break;
1085         case 1:
1086         default:
1087                 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1088                 break;
1089         }
1090 
1091         return 0;
1092 }
1093 
1094 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1095 {
1096         const struct of_device_id *of_id =
1097                         of_match_device(imx_esdhc_dt_ids, &pdev->dev);
1098         struct sdhci_pltfm_host *pltfm_host;
1099         struct sdhci_host *host;
1100         int err;
1101         struct pltfm_imx_data *imx_data;
1102 
1103         host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0);
1104         if (IS_ERR(host))
1105                 return PTR_ERR(host);
1106 
1107         pltfm_host = sdhci_priv(host);
1108 
1109         imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL);
1110         if (!imx_data) {
1111                 err = -ENOMEM;
1112                 goto free_sdhci;
1113         }
1114 
1115         imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
1116                                                   pdev->id_entry->driver_data;
1117         pltfm_host->priv = imx_data;
1118 
1119         imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1120         if (IS_ERR(imx_data->clk_ipg)) {
1121                 err = PTR_ERR(imx_data->clk_ipg);
1122                 goto free_sdhci;
1123         }
1124 
1125         imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1126         if (IS_ERR(imx_data->clk_ahb)) {
1127                 err = PTR_ERR(imx_data->clk_ahb);
1128                 goto free_sdhci;
1129         }
1130 
1131         imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1132         if (IS_ERR(imx_data->clk_per)) {
1133                 err = PTR_ERR(imx_data->clk_per);
1134                 goto free_sdhci;
1135         }
1136 
1137         pltfm_host->clk = imx_data->clk_per;
1138         pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1139         clk_prepare_enable(imx_data->clk_per);
1140         clk_prepare_enable(imx_data->clk_ipg);
1141         clk_prepare_enable(imx_data->clk_ahb);
1142 
1143         imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1144         if (IS_ERR(imx_data->pinctrl)) {
1145                 err = PTR_ERR(imx_data->pinctrl);
1146                 goto disable_clk;
1147         }
1148 
1149         imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
1150                                                 PINCTRL_STATE_DEFAULT);
1151         if (IS_ERR(imx_data->pins_default))
1152                 dev_warn(mmc_dev(host->mmc), "could not get default state\n");
1153 
1154         host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
1155 
1156         if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207)
1157                 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
1158                 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
1159                         | SDHCI_QUIRK_BROKEN_ADMA;
1160 
1161         /*
1162          * The imx6q ROM code will change the default watermark level setting
1163          * to something insane.  Change it back here.
1164          */
1165         if (esdhc_is_usdhc(imx_data)) {
1166                 writel(0x10401040, host->ioaddr + ESDHC_WTMK_LVL);
1167 
1168                 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1169                 host->mmc->caps |= MMC_CAP_1_8V_DDR;
1170 
1171                 /*
1172                  * ROM code will change the bit burst_length_enable setting
1173                  * to zero if this usdhc is choosed to boot system. Change
1174                  * it back here, otherwise it will impact the performance a
1175                  * lot. This bit is used to enable/disable the burst length
1176                  * for the external AHB2AXI bridge, it's usefully especially
1177                  * for INCR transfer because without burst length indicator,
1178                  * the AHB2AXI bridge does not know the burst length in
1179                  * advance. And without burst length indicator, AHB INCR
1180                  * transfer can only be converted to singles on the AXI side.
1181                  */
1182                 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1183                         | ESDHC_BURST_LEN_EN_INCR,
1184                         host->ioaddr + SDHCI_HOST_CONTROL);
1185 
1186                 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1187                         host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1188 
1189                 /*
1190                 * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1191                 * TO1.1, it's harmless for MX6SL
1192                 */
1193                 writel(readl(host->ioaddr + 0x6c) | BIT(7),
1194                         host->ioaddr + 0x6c);
1195         }
1196 
1197         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1198                 sdhci_esdhc_ops.platform_execute_tuning =
1199                                         esdhc_executing_tuning;
1200 
1201         if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
1202                 writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) |
1203                         ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP,
1204                         host->ioaddr + ESDHC_TUNING_CTRL);
1205 
1206         if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1207                 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1208 
1209         if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
1210                 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
1211 
1212         if (of_id)
1213                 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1214         else
1215                 err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data);
1216         if (err)
1217                 goto disable_clk;
1218 
1219         err = sdhci_add_host(host);
1220         if (err)
1221                 goto disable_clk;
1222 
1223         pm_runtime_set_active(&pdev->dev);
1224         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1225         pm_runtime_use_autosuspend(&pdev->dev);
1226         pm_suspend_ignore_children(&pdev->dev, 1);
1227         pm_runtime_enable(&pdev->dev);
1228 
1229         return 0;
1230 
1231 disable_clk:
1232         clk_disable_unprepare(imx_data->clk_per);
1233         clk_disable_unprepare(imx_data->clk_ipg);
1234         clk_disable_unprepare(imx_data->clk_ahb);
1235 free_sdhci:
1236         sdhci_pltfm_free(pdev);
1237         return err;
1238 }
1239 
1240 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1241 {
1242         struct sdhci_host *host = platform_get_drvdata(pdev);
1243         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1244         struct pltfm_imx_data *imx_data = pltfm_host->priv;
1245         int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1246 
1247         pm_runtime_get_sync(&pdev->dev);
1248         pm_runtime_disable(&pdev->dev);
1249         pm_runtime_put_noidle(&pdev->dev);
1250 
1251         sdhci_remove_host(host, dead);
1252 
1253         clk_disable_unprepare(imx_data->clk_per);
1254         clk_disable_unprepare(imx_data->clk_ipg);
1255         clk_disable_unprepare(imx_data->clk_ahb);
1256 
1257         sdhci_pltfm_free(pdev);
1258 
1259         return 0;
1260 }
1261 
1262 #ifdef CONFIG_PM
1263 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1264 {
1265         struct sdhci_host *host = dev_get_drvdata(dev);
1266         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1267         struct pltfm_imx_data *imx_data = pltfm_host->priv;
1268         int ret;
1269 
1270         ret = sdhci_runtime_suspend_host(host);
1271 
1272         if (!sdhci_sdio_irq_enabled(host)) {
1273                 clk_disable_unprepare(imx_data->clk_per);
1274                 clk_disable_unprepare(imx_data->clk_ipg);
1275         }
1276         clk_disable_unprepare(imx_data->clk_ahb);
1277 
1278         return ret;
1279 }
1280 
1281 static int sdhci_esdhc_runtime_resume(struct device *dev)
1282 {
1283         struct sdhci_host *host = dev_get_drvdata(dev);
1284         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1285         struct pltfm_imx_data *imx_data = pltfm_host->priv;
1286 
1287         if (!sdhci_sdio_irq_enabled(host)) {
1288                 clk_prepare_enable(imx_data->clk_per);
1289                 clk_prepare_enable(imx_data->clk_ipg);
1290         }
1291         clk_prepare_enable(imx_data->clk_ahb);
1292 
1293         return sdhci_runtime_resume_host(host);
1294 }
1295 #endif
1296 
1297 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1298         SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_pltfm_resume)
1299         SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1300                                 sdhci_esdhc_runtime_resume, NULL)
1301 };
1302 
1303 static struct platform_driver sdhci_esdhc_imx_driver = {
1304         .driver         = {
1305                 .name   = "sdhci-esdhc-imx",
1306                 .of_match_table = imx_esdhc_dt_ids,
1307                 .pm     = &sdhci_esdhc_pmops,
1308         },
1309         .id_table       = imx_esdhc_devtype,
1310         .probe          = sdhci_esdhc_imx_probe,
1311         .remove         = sdhci_esdhc_imx_remove,
1312 };
1313 
1314 module_platform_driver(sdhci_esdhc_imx_driver);
1315 
1316 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1317 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1318 MODULE_LICENSE("GPL v2");
1319 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us