Version:  2.0.40 2.2.26 2.4.37 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8

Linux/drivers/mmc/host/sdhci-esdhc-imx.c

  1 /*
  2  * Freescale eSDHC i.MX controller driver for the platform bus.
  3  *
  4  * derived from the OF-version.
  5  *
  6  * Copyright (c) 2010 Pengutronix e.K.
  7  *   Author: Wolfram Sang <kernel@pengutronix.de>
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License as published by
 11  * the Free Software Foundation; either version 2 of the License.
 12  */
 13 
 14 #include <linux/io.h>
 15 #include <linux/delay.h>
 16 #include <linux/err.h>
 17 #include <linux/clk.h>
 18 #include <linux/gpio.h>
 19 #include <linux/module.h>
 20 #include <linux/slab.h>
 21 #include <linux/mmc/host.h>
 22 #include <linux/mmc/mmc.h>
 23 #include <linux/mmc/sdio.h>
 24 #include <linux/mmc/slot-gpio.h>
 25 #include <linux/of.h>
 26 #include <linux/of_device.h>
 27 #include <linux/of_gpio.h>
 28 #include <linux/pinctrl/consumer.h>
 29 #include <linux/platform_data/mmc-esdhc-imx.h>
 30 #include <linux/pm_runtime.h>
 31 #include "sdhci-pltfm.h"
 32 #include "sdhci-esdhc.h"
 33 
 34 #define ESDHC_CTRL_D3CD                 0x08
 35 #define ESDHC_BURST_LEN_EN_INCR         (1 << 27)
 36 /* VENDOR SPEC register */
 37 #define ESDHC_VENDOR_SPEC               0xc0
 38 #define  ESDHC_VENDOR_SPEC_SDIO_QUIRK   (1 << 1)
 39 #define  ESDHC_VENDOR_SPEC_VSELECT      (1 << 1)
 40 #define  ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
 41 #define ESDHC_WTMK_LVL                  0x44
 42 #define  ESDHC_WTMK_DEFAULT_VAL         0x10401040
 43 #define ESDHC_MIX_CTRL                  0x48
 44 #define  ESDHC_MIX_CTRL_DDREN           (1 << 3)
 45 #define  ESDHC_MIX_CTRL_AC23EN          (1 << 7)
 46 #define  ESDHC_MIX_CTRL_EXE_TUNE        (1 << 22)
 47 #define  ESDHC_MIX_CTRL_SMPCLK_SEL      (1 << 23)
 48 #define  ESDHC_MIX_CTRL_AUTO_TUNE_EN    (1 << 24)
 49 #define  ESDHC_MIX_CTRL_FBCLK_SEL       (1 << 25)
 50 #define  ESDHC_MIX_CTRL_HS400_EN        (1 << 26)
 51 /* Bits 3 and 6 are not SDHCI standard definitions */
 52 #define  ESDHC_MIX_CTRL_SDHCI_MASK      0xb7
 53 /* Tuning bits */
 54 #define  ESDHC_MIX_CTRL_TUNING_MASK     0x03c00000
 55 
 56 /* dll control register */
 57 #define ESDHC_DLL_CTRL                  0x60
 58 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT    9
 59 #define ESDHC_DLL_OVERRIDE_EN_SHIFT     8
 60 
 61 /* tune control register */
 62 #define ESDHC_TUNE_CTRL_STATUS          0x68
 63 #define  ESDHC_TUNE_CTRL_STEP           1
 64 #define  ESDHC_TUNE_CTRL_MIN            0
 65 #define  ESDHC_TUNE_CTRL_MAX            ((1 << 7) - 1)
 66 
 67 /* strobe dll register */
 68 #define ESDHC_STROBE_DLL_CTRL           0x70
 69 #define ESDHC_STROBE_DLL_CTRL_ENABLE    (1 << 0)
 70 #define ESDHC_STROBE_DLL_CTRL_RESET     (1 << 1)
 71 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT      3
 72 
 73 #define ESDHC_STROBE_DLL_STATUS         0x74
 74 #define ESDHC_STROBE_DLL_STS_REF_LOCK   (1 << 1)
 75 #define ESDHC_STROBE_DLL_STS_SLV_LOCK   0x1
 76 
 77 #define ESDHC_TUNING_CTRL               0xcc
 78 #define ESDHC_STD_TUNING_EN             (1 << 24)
 79 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
 80 #define ESDHC_TUNING_START_TAP_DEFAULT  0x1
 81 #define ESDHC_TUNING_START_TAP_MASK     0xff
 82 #define ESDHC_TUNING_STEP_MASK          0x00070000
 83 #define ESDHC_TUNING_STEP_SHIFT         16
 84 
 85 /* pinctrl state */
 86 #define ESDHC_PINCTRL_STATE_100MHZ      "state_100mhz"
 87 #define ESDHC_PINCTRL_STATE_200MHZ      "state_200mhz"
 88 
 89 /*
 90  * Our interpretation of the SDHCI_HOST_CONTROL register
 91  */
 92 #define ESDHC_CTRL_4BITBUS              (0x1 << 1)
 93 #define ESDHC_CTRL_8BITBUS              (0x2 << 1)
 94 #define ESDHC_CTRL_BUSWIDTH_MASK        (0x3 << 1)
 95 
 96 /*
 97  * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
 98  * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
 99  * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
100  * Define this macro DMA error INT for fsl eSDHC
101  */
102 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR   (1 << 28)
103 
104 /*
105  * The CMDTYPE of the CMD register (offset 0xE) should be set to
106  * "11" when the STOP CMD12 is issued on imx53 to abort one
107  * open ended multi-blk IO. Otherwise the TC INT wouldn't
108  * be generated.
109  * In exact block transfer, the controller doesn't complete the
110  * operations automatically as required at the end of the
111  * transfer and remains on hold if the abort command is not sent.
112  * As a result, the TC flag is not asserted and SW  received timeout
113  * exeception. Bit1 of Vendor Spec registor is used to fix it.
114  */
115 #define ESDHC_FLAG_MULTIBLK_NO_INT      BIT(1)
116 /*
117  * The flag enables the workaround for ESDHC errata ENGcm07207 which
118  * affects i.MX25 and i.MX35.
119  */
120 #define ESDHC_FLAG_ENGCM07207           BIT(2)
121 /*
122  * The flag tells that the ESDHC controller is an USDHC block that is
123  * integrated on the i.MX6 series.
124  */
125 #define ESDHC_FLAG_USDHC                BIT(3)
126 /* The IP supports manual tuning process */
127 #define ESDHC_FLAG_MAN_TUNING           BIT(4)
128 /* The IP supports standard tuning process */
129 #define ESDHC_FLAG_STD_TUNING           BIT(5)
130 /* The IP has SDHCI_CAPABILITIES_1 register */
131 #define ESDHC_FLAG_HAVE_CAP1            BIT(6)
132 /*
133  * The IP has errata ERR004536
134  * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
135  * when reading data from the card
136  */
137 #define ESDHC_FLAG_ERR004536            BIT(7)
138 /* The IP supports HS200 mode */
139 #define ESDHC_FLAG_HS200                BIT(8)
140 /* The IP supports HS400 mode */
141 #define ESDHC_FLAG_HS400                BIT(9)
142 
143 /* A higher clock ferquency than this rate requires strobell dll control */
144 #define ESDHC_STROBE_DLL_CLK_FREQ       100000000
145 
146 struct esdhc_soc_data {
147         u32 flags;
148 };
149 
150 static struct esdhc_soc_data esdhc_imx25_data = {
151         .flags = ESDHC_FLAG_ENGCM07207,
152 };
153 
154 static struct esdhc_soc_data esdhc_imx35_data = {
155         .flags = ESDHC_FLAG_ENGCM07207,
156 };
157 
158 static struct esdhc_soc_data esdhc_imx51_data = {
159         .flags = 0,
160 };
161 
162 static struct esdhc_soc_data esdhc_imx53_data = {
163         .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
164 };
165 
166 static struct esdhc_soc_data usdhc_imx6q_data = {
167         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
168 };
169 
170 static struct esdhc_soc_data usdhc_imx6sl_data = {
171         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
172                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
173                         | ESDHC_FLAG_HS200,
174 };
175 
176 static struct esdhc_soc_data usdhc_imx6sx_data = {
177         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
178                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
179 };
180 
181 static struct esdhc_soc_data usdhc_imx7d_data = {
182         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
183                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
184                         | ESDHC_FLAG_HS400,
185 };
186 
187 struct pltfm_imx_data {
188         u32 scratchpad;
189         struct pinctrl *pinctrl;
190         struct pinctrl_state *pins_default;
191         struct pinctrl_state *pins_100mhz;
192         struct pinctrl_state *pins_200mhz;
193         const struct esdhc_soc_data *socdata;
194         struct esdhc_platform_data boarddata;
195         struct clk *clk_ipg;
196         struct clk *clk_ahb;
197         struct clk *clk_per;
198         enum {
199                 NO_CMD_PENDING,      /* no multiblock command pending*/
200                 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
201                 WAIT_FOR_INT,        /* sent CMD12, waiting for response INT */
202         } multiblock_status;
203         u32 is_ddr;
204 };
205 
206 static const struct platform_device_id imx_esdhc_devtype[] = {
207         {
208                 .name = "sdhci-esdhc-imx25",
209                 .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
210         }, {
211                 .name = "sdhci-esdhc-imx35",
212                 .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
213         }, {
214                 .name = "sdhci-esdhc-imx51",
215                 .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
216         }, {
217                 /* sentinel */
218         }
219 };
220 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
221 
222 static const struct of_device_id imx_esdhc_dt_ids[] = {
223         { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
224         { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
225         { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
226         { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
227         { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
228         { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
229         { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
230         { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
231         { /* sentinel */ }
232 };
233 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
234 
235 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
236 {
237         return data->socdata == &esdhc_imx25_data;
238 }
239 
240 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
241 {
242         return data->socdata == &esdhc_imx53_data;
243 }
244 
245 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
246 {
247         return data->socdata == &usdhc_imx6q_data;
248 }
249 
250 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
251 {
252         return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
253 }
254 
255 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
256 {
257         void __iomem *base = host->ioaddr + (reg & ~0x3);
258         u32 shift = (reg & 0x3) * 8;
259 
260         writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
261 }
262 
263 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
264 {
265         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
266         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
267         u32 val = readl(host->ioaddr + reg);
268 
269         if (unlikely(reg == SDHCI_PRESENT_STATE)) {
270                 u32 fsl_prss = val;
271                 /* save the least 20 bits */
272                 val = fsl_prss & 0x000FFFFF;
273                 /* move dat[0-3] bits */
274                 val |= (fsl_prss & 0x0F000000) >> 4;
275                 /* move cmd line bit */
276                 val |= (fsl_prss & 0x00800000) << 1;
277         }
278 
279         if (unlikely(reg == SDHCI_CAPABILITIES)) {
280                 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
281                 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
282                         val &= 0xffff0000;
283 
284                 /* In FSL esdhc IC module, only bit20 is used to indicate the
285                  * ADMA2 capability of esdhc, but this bit is messed up on
286                  * some SOCs (e.g. on MX25, MX35 this bit is set, but they
287                  * don't actually support ADMA2). So set the BROKEN_ADMA
288                  * uirk on MX25/35 platforms.
289                  */
290 
291                 if (val & SDHCI_CAN_DO_ADMA1) {
292                         val &= ~SDHCI_CAN_DO_ADMA1;
293                         val |= SDHCI_CAN_DO_ADMA2;
294                 }
295         }
296 
297         if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
298                 if (esdhc_is_usdhc(imx_data)) {
299                         if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
300                                 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
301                         else
302                                 /* imx6q/dl does not have cap_1 register, fake one */
303                                 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
304                                         | SDHCI_SUPPORT_SDR50
305                                         | SDHCI_USE_SDR50_TUNING
306                                         | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT);
307 
308                         if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
309                                 val |= SDHCI_SUPPORT_HS400;
310                 }
311         }
312 
313         if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
314                 val = 0;
315                 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
316                 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
317                 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
318         }
319 
320         if (unlikely(reg == SDHCI_INT_STATUS)) {
321                 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
322                         val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
323                         val |= SDHCI_INT_ADMA_ERROR;
324                 }
325 
326                 /*
327                  * mask off the interrupt we get in response to the manually
328                  * sent CMD12
329                  */
330                 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
331                     ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
332                         val &= ~SDHCI_INT_RESPONSE;
333                         writel(SDHCI_INT_RESPONSE, host->ioaddr +
334                                                    SDHCI_INT_STATUS);
335                         imx_data->multiblock_status = NO_CMD_PENDING;
336                 }
337         }
338 
339         return val;
340 }
341 
342 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
343 {
344         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
345         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
346         u32 data;
347 
348         if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
349                 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
350                         /*
351                          * Clear and then set D3CD bit to avoid missing the
352                          * card interrupt.  This is a eSDHC controller problem
353                          * so we need to apply the following workaround: clear
354                          * and set D3CD bit will make eSDHC re-sample the card
355                          * interrupt. In case a card interrupt was lost,
356                          * re-sample it by the following steps.
357                          */
358                         data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
359                         data &= ~ESDHC_CTRL_D3CD;
360                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
361                         data |= ESDHC_CTRL_D3CD;
362                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
363                 }
364 
365                 if (val & SDHCI_INT_ADMA_ERROR) {
366                         val &= ~SDHCI_INT_ADMA_ERROR;
367                         val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
368                 }
369         }
370 
371         if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
372                                 && (reg == SDHCI_INT_STATUS)
373                                 && (val & SDHCI_INT_DATA_END))) {
374                         u32 v;
375                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
376                         v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
377                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
378 
379                         if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
380                         {
381                                 /* send a manual CMD12 with RESPTYP=none */
382                                 data = MMC_STOP_TRANSMISSION << 24 |
383                                        SDHCI_CMD_ABORTCMD << 16;
384                                 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
385                                 imx_data->multiblock_status = WAIT_FOR_INT;
386                         }
387         }
388 
389         writel(val, host->ioaddr + reg);
390 }
391 
392 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
393 {
394         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
395         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
396         u16 ret = 0;
397         u32 val;
398 
399         if (unlikely(reg == SDHCI_HOST_VERSION)) {
400                 reg ^= 2;
401                 if (esdhc_is_usdhc(imx_data)) {
402                         /*
403                          * The usdhc register returns a wrong host version.
404                          * Correct it here.
405                          */
406                         return SDHCI_SPEC_300;
407                 }
408         }
409 
410         if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
411                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
412                 if (val & ESDHC_VENDOR_SPEC_VSELECT)
413                         ret |= SDHCI_CTRL_VDD_180;
414 
415                 if (esdhc_is_usdhc(imx_data)) {
416                         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
417                                 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
418                         else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
419                                 /* the std tuning bits is in ACMD12_ERR for imx6sl */
420                                 val = readl(host->ioaddr + SDHCI_ACMD12_ERR);
421                 }
422 
423                 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
424                         ret |= SDHCI_CTRL_EXEC_TUNING;
425                 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
426                         ret |= SDHCI_CTRL_TUNED_CLK;
427 
428                 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
429 
430                 return ret;
431         }
432 
433         if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
434                 if (esdhc_is_usdhc(imx_data)) {
435                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
436                         ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
437                         /* Swap AC23 bit */
438                         if (m & ESDHC_MIX_CTRL_AC23EN) {
439                                 ret &= ~ESDHC_MIX_CTRL_AC23EN;
440                                 ret |= SDHCI_TRNS_AUTO_CMD23;
441                         }
442                 } else {
443                         ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
444                 }
445 
446                 return ret;
447         }
448 
449         return readw(host->ioaddr + reg);
450 }
451 
452 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
453 {
454         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
455         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
456         u32 new_val = 0;
457 
458         switch (reg) {
459         case SDHCI_CLOCK_CONTROL:
460                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
461                 if (val & SDHCI_CLOCK_CARD_EN)
462                         new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
463                 else
464                         new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
465                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
466                 return;
467         case SDHCI_HOST_CONTROL2:
468                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
469                 if (val & SDHCI_CTRL_VDD_180)
470                         new_val |= ESDHC_VENDOR_SPEC_VSELECT;
471                 else
472                         new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
473                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
474                 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
475                         new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
476                         if (val & SDHCI_CTRL_TUNED_CLK) {
477                                 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
478                                 new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
479                         } else {
480                                 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
481                                 new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
482                         }
483                         writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
484                 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
485                         u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);
486                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
487                         if (val & SDHCI_CTRL_TUNED_CLK) {
488                                 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
489                         } else {
490                                 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
491                                 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
492                                 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
493                         }
494 
495                         if (val & SDHCI_CTRL_EXEC_TUNING) {
496                                 v |= ESDHC_MIX_CTRL_EXE_TUNE;
497                                 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
498                                 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
499                         } else {
500                                 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
501                         }
502 
503                         writel(v, host->ioaddr + SDHCI_ACMD12_ERR);
504                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
505                 }
506                 return;
507         case SDHCI_TRANSFER_MODE:
508                 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
509                                 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
510                                 && (host->cmd->data->blocks > 1)
511                                 && (host->cmd->data->flags & MMC_DATA_READ)) {
512                         u32 v;
513                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
514                         v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
515                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
516                 }
517 
518                 if (esdhc_is_usdhc(imx_data)) {
519                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
520                         /* Swap AC23 bit */
521                         if (val & SDHCI_TRNS_AUTO_CMD23) {
522                                 val &= ~SDHCI_TRNS_AUTO_CMD23;
523                                 val |= ESDHC_MIX_CTRL_AC23EN;
524                         }
525                         m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
526                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
527                 } else {
528                         /*
529                          * Postpone this write, we must do it together with a
530                          * command write that is down below.
531                          */
532                         imx_data->scratchpad = val;
533                 }
534                 return;
535         case SDHCI_COMMAND:
536                 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
537                         val |= SDHCI_CMD_ABORTCMD;
538 
539                 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
540                     (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
541                         imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
542 
543                 if (esdhc_is_usdhc(imx_data))
544                         writel(val << 16,
545                                host->ioaddr + SDHCI_TRANSFER_MODE);
546                 else
547                         writel(val << 16 | imx_data->scratchpad,
548                                host->ioaddr + SDHCI_TRANSFER_MODE);
549                 return;
550         case SDHCI_BLOCK_SIZE:
551                 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
552                 break;
553         }
554         esdhc_clrset_le(host, 0xffff, val, reg);
555 }
556 
557 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
558 {
559         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
560         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
561         u32 new_val;
562         u32 mask;
563 
564         switch (reg) {
565         case SDHCI_POWER_CONTROL:
566                 /*
567                  * FSL put some DMA bits here
568                  * If your board has a regulator, code should be here
569                  */
570                 return;
571         case SDHCI_HOST_CONTROL:
572                 /* FSL messed up here, so we need to manually compose it. */
573                 new_val = val & SDHCI_CTRL_LED;
574                 /* ensure the endianness */
575                 new_val |= ESDHC_HOST_CONTROL_LE;
576                 /* bits 8&9 are reserved on mx25 */
577                 if (!is_imx25_esdhc(imx_data)) {
578                         /* DMA mode bits are shifted */
579                         new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
580                 }
581 
582                 /*
583                  * Do not touch buswidth bits here. This is done in
584                  * esdhc_pltfm_bus_width.
585                  * Do not touch the D3CD bit either which is used for the
586                  * SDIO interrupt errata workaround.
587                  */
588                 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
589 
590                 esdhc_clrset_le(host, mask, new_val, reg);
591                 return;
592         }
593         esdhc_clrset_le(host, 0xff, val, reg);
594 
595         /*
596          * The esdhc has a design violation to SDHC spec which tells
597          * that software reset should not affect card detection circuit.
598          * But esdhc clears its SYSCTL register bits [0..2] during the
599          * software reset.  This will stop those clocks that card detection
600          * circuit relies on.  To work around it, we turn the clocks on back
601          * to keep card detection circuit functional.
602          */
603         if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) {
604                 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
605                 /*
606                  * The reset on usdhc fails to clear MIX_CTRL register.
607                  * Do it manually here.
608                  */
609                 if (esdhc_is_usdhc(imx_data)) {
610                         /* the tuning bits should be kept during reset */
611                         new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
612                         writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
613                                         host->ioaddr + ESDHC_MIX_CTRL);
614                         imx_data->is_ddr = 0;
615                 }
616         }
617 }
618 
619 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
620 {
621         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
622 
623         return pltfm_host->clock;
624 }
625 
626 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
627 {
628         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
629 
630         return pltfm_host->clock / 256 / 16;
631 }
632 
633 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
634                                          unsigned int clock)
635 {
636         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
637         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
638         unsigned int host_clock = pltfm_host->clock;
639         int pre_div = 2;
640         int div = 1;
641         u32 temp, val;
642 
643         if (clock == 0) {
644                 host->mmc->actual_clock = 0;
645 
646                 if (esdhc_is_usdhc(imx_data)) {
647                         val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
648                         writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
649                                         host->ioaddr + ESDHC_VENDOR_SPEC);
650                 }
651                 return;
652         }
653 
654         if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr)
655                 pre_div = 1;
656 
657         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
658         temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
659                 | ESDHC_CLOCK_MASK);
660         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
661 
662         while (host_clock / pre_div / 16 > clock && pre_div < 256)
663                 pre_div *= 2;
664 
665         while (host_clock / pre_div / div > clock && div < 16)
666                 div++;
667 
668         host->mmc->actual_clock = host_clock / pre_div / div;
669         dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
670                 clock, host->mmc->actual_clock);
671 
672         if (imx_data->is_ddr)
673                 pre_div >>= 2;
674         else
675                 pre_div >>= 1;
676         div--;
677 
678         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
679         temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
680                 | (div << ESDHC_DIVIDER_SHIFT)
681                 | (pre_div << ESDHC_PREDIV_SHIFT));
682         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
683 
684         if (esdhc_is_usdhc(imx_data)) {
685                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
686                 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
687                 host->ioaddr + ESDHC_VENDOR_SPEC);
688         }
689 
690         mdelay(1);
691 }
692 
693 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
694 {
695         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
696         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
697         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
698 
699         switch (boarddata->wp_type) {
700         case ESDHC_WP_GPIO:
701                 return mmc_gpio_get_ro(host->mmc);
702         case ESDHC_WP_CONTROLLER:
703                 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
704                                SDHCI_WRITE_PROTECT);
705         case ESDHC_WP_NONE:
706                 break;
707         }
708 
709         return -ENOSYS;
710 }
711 
712 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
713 {
714         u32 ctrl;
715 
716         switch (width) {
717         case MMC_BUS_WIDTH_8:
718                 ctrl = ESDHC_CTRL_8BITBUS;
719                 break;
720         case MMC_BUS_WIDTH_4:
721                 ctrl = ESDHC_CTRL_4BITBUS;
722                 break;
723         default:
724                 ctrl = 0;
725                 break;
726         }
727 
728         esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
729                         SDHCI_HOST_CONTROL);
730 }
731 
732 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
733 {
734         u32 reg;
735 
736         /* FIXME: delay a bit for card to be ready for next tuning due to errors */
737         mdelay(1);
738 
739         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
740         reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
741                         ESDHC_MIX_CTRL_FBCLK_SEL;
742         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
743         writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
744         dev_dbg(mmc_dev(host->mmc),
745                 "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
746                         val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
747 }
748 
749 static void esdhc_post_tuning(struct sdhci_host *host)
750 {
751         u32 reg;
752 
753         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
754         reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
755         reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
756         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
757 }
758 
759 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
760 {
761         int min, max, avg, ret;
762 
763         /* find the mininum delay first which can pass tuning */
764         min = ESDHC_TUNE_CTRL_MIN;
765         while (min < ESDHC_TUNE_CTRL_MAX) {
766                 esdhc_prepare_tuning(host, min);
767                 if (!mmc_send_tuning(host->mmc, opcode, NULL))
768                         break;
769                 min += ESDHC_TUNE_CTRL_STEP;
770         }
771 
772         /* find the maxinum delay which can not pass tuning */
773         max = min + ESDHC_TUNE_CTRL_STEP;
774         while (max < ESDHC_TUNE_CTRL_MAX) {
775                 esdhc_prepare_tuning(host, max);
776                 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
777                         max -= ESDHC_TUNE_CTRL_STEP;
778                         break;
779                 }
780                 max += ESDHC_TUNE_CTRL_STEP;
781         }
782 
783         /* use average delay to get the best timing */
784         avg = (min + max) / 2;
785         esdhc_prepare_tuning(host, avg);
786         ret = mmc_send_tuning(host->mmc, opcode, NULL);
787         esdhc_post_tuning(host);
788 
789         dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n",
790                 ret ? "failed" : "passed", avg, ret);
791 
792         return ret;
793 }
794 
795 static int esdhc_change_pinstate(struct sdhci_host *host,
796                                                 unsigned int uhs)
797 {
798         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
799         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
800         struct pinctrl_state *pinctrl;
801 
802         dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
803 
804         if (IS_ERR(imx_data->pinctrl) ||
805                 IS_ERR(imx_data->pins_default) ||
806                 IS_ERR(imx_data->pins_100mhz) ||
807                 IS_ERR(imx_data->pins_200mhz))
808                 return -EINVAL;
809 
810         switch (uhs) {
811         case MMC_TIMING_UHS_SDR50:
812                 pinctrl = imx_data->pins_100mhz;
813                 break;
814         case MMC_TIMING_UHS_SDR104:
815         case MMC_TIMING_MMC_HS200:
816         case MMC_TIMING_MMC_HS400:
817                 pinctrl = imx_data->pins_200mhz;
818                 break;
819         default:
820                 /* back to default state for other legacy timing */
821                 pinctrl = imx_data->pins_default;
822         }
823 
824         return pinctrl_select_state(imx_data->pinctrl, pinctrl);
825 }
826 
827 /*
828  * For HS400 eMMC, there is a data_strobe line, this signal is generated
829  * by the device and used for data output and CRC status response output
830  * in HS400 mode. The frequency of this signal follows the frequency of
831  * CLK generated by host. Host receive the data which is aligned to the
832  * edge of data_strobe line. Due to the time delay between CLK line and
833  * data_strobe line, if the delay time is larger than one clock cycle,
834  * then CLK and data_strobe line will misaligned, read error shows up.
835  * So when the CLK is higher than 100MHz, each clock cycle is short enough,
836  * host should config the delay target.
837  */
838 static void esdhc_set_strobe_dll(struct sdhci_host *host)
839 {
840         u32 v;
841 
842         if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) {
843                 /* disable clock before enabling strobe dll */
844                 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
845                        ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
846                        host->ioaddr + ESDHC_VENDOR_SPEC);
847 
848                 /* force a reset on strobe dll */
849                 writel(ESDHC_STROBE_DLL_CTRL_RESET,
850                         host->ioaddr + ESDHC_STROBE_DLL_CTRL);
851                 /*
852                  * enable strobe dll ctrl and adjust the delay target
853                  * for the uSDHC loopback read clock
854                  */
855                 v = ESDHC_STROBE_DLL_CTRL_ENABLE |
856                         (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
857                 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
858                 /* wait 1us to make sure strobe dll status register stable */
859                 udelay(1);
860                 v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS);
861                 if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK))
862                         dev_warn(mmc_dev(host->mmc),
863                                 "warning! HS400 strobe DLL status REF not lock!\n");
864                 if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK))
865                         dev_warn(mmc_dev(host->mmc),
866                                 "warning! HS400 strobe DLL status SLV not lock!\n");
867         }
868 }
869 
870 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
871 {
872         u32 m;
873         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
874         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
875         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
876 
877         /* disable ddr mode and disable HS400 mode */
878         m = readl(host->ioaddr + ESDHC_MIX_CTRL);
879         m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
880         imx_data->is_ddr = 0;
881 
882         switch (timing) {
883         case MMC_TIMING_UHS_SDR12:
884         case MMC_TIMING_UHS_SDR25:
885         case MMC_TIMING_UHS_SDR50:
886         case MMC_TIMING_UHS_SDR104:
887         case MMC_TIMING_MMC_HS200:
888                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
889                 break;
890         case MMC_TIMING_UHS_DDR50:
891         case MMC_TIMING_MMC_DDR52:
892                 m |= ESDHC_MIX_CTRL_DDREN;
893                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
894                 imx_data->is_ddr = 1;
895                 if (boarddata->delay_line) {
896                         u32 v;
897                         v = boarddata->delay_line <<
898                                 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
899                                 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
900                         if (is_imx53_esdhc(imx_data))
901                                 v <<= 1;
902                         writel(v, host->ioaddr + ESDHC_DLL_CTRL);
903                 }
904                 break;
905         case MMC_TIMING_MMC_HS400:
906                 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
907                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
908                 imx_data->is_ddr = 1;
909                 /* update clock after enable DDR for strobe DLL lock */
910                 host->ops->set_clock(host, host->clock);
911                 esdhc_set_strobe_dll(host);
912                 break;
913         }
914 
915         esdhc_change_pinstate(host, timing);
916 }
917 
918 static void esdhc_reset(struct sdhci_host *host, u8 mask)
919 {
920         sdhci_reset(host, mask);
921 
922         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
923         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
924 }
925 
926 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
927 {
928         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
929         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
930 
931         return esdhc_is_usdhc(imx_data) ? 1 << 28 : 1 << 27;
932 }
933 
934 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
935 {
936         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
937         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
938 
939         /* use maximum timeout counter */
940         sdhci_writeb(host, esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
941                         SDHCI_TIMEOUT_CONTROL);
942 }
943 
944 static struct sdhci_ops sdhci_esdhc_ops = {
945         .read_l = esdhc_readl_le,
946         .read_w = esdhc_readw_le,
947         .write_l = esdhc_writel_le,
948         .write_w = esdhc_writew_le,
949         .write_b = esdhc_writeb_le,
950         .set_clock = esdhc_pltfm_set_clock,
951         .get_max_clock = esdhc_pltfm_get_max_clock,
952         .get_min_clock = esdhc_pltfm_get_min_clock,
953         .get_max_timeout_count = esdhc_get_max_timeout_count,
954         .get_ro = esdhc_pltfm_get_ro,
955         .set_timeout = esdhc_set_timeout,
956         .set_bus_width = esdhc_pltfm_set_bus_width,
957         .set_uhs_signaling = esdhc_set_uhs_signaling,
958         .reset = esdhc_reset,
959 };
960 
961 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
962         .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
963                         | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
964                         | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
965                         | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
966         .ops = &sdhci_esdhc_ops,
967 };
968 
969 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
970 {
971         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
972         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
973         int tmp;
974 
975         if (esdhc_is_usdhc(imx_data)) {
976                 /*
977                  * The imx6q ROM code will change the default watermark
978                  * level setting to something insane.  Change it back here.
979                  */
980                 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
981 
982                 /*
983                  * ROM code will change the bit burst_length_enable setting
984                  * to zero if this usdhc is choosed to boot system. Change
985                  * it back here, otherwise it will impact the performance a
986                  * lot. This bit is used to enable/disable the burst length
987                  * for the external AHB2AXI bridge, it's usefully especially
988                  * for INCR transfer because without burst length indicator,
989                  * the AHB2AXI bridge does not know the burst length in
990                  * advance. And without burst length indicator, AHB INCR
991                  * transfer can only be converted to singles on the AXI side.
992                  */
993                 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
994                         | ESDHC_BURST_LEN_EN_INCR,
995                         host->ioaddr + SDHCI_HOST_CONTROL);
996                 /*
997                 * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
998                 * TO1.1, it's harmless for MX6SL
999                 */
1000                 writel(readl(host->ioaddr + 0x6c) | BIT(7),
1001                         host->ioaddr + 0x6c);
1002 
1003                 /* disable DLL_CTRL delay line settings */
1004                 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1005 
1006                 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1007                         tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1008                         tmp |= ESDHC_STD_TUNING_EN |
1009                                 ESDHC_TUNING_START_TAP_DEFAULT;
1010                         if (imx_data->boarddata.tuning_start_tap) {
1011                                 tmp &= ~ESDHC_TUNING_START_TAP_MASK;
1012                                 tmp |= imx_data->boarddata.tuning_start_tap;
1013                         }
1014 
1015                         if (imx_data->boarddata.tuning_step) {
1016                                 tmp &= ~ESDHC_TUNING_STEP_MASK;
1017                                 tmp |= imx_data->boarddata.tuning_step
1018                                         << ESDHC_TUNING_STEP_SHIFT;
1019                         }
1020                         writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1021                 }
1022         }
1023 }
1024 
1025 #ifdef CONFIG_OF
1026 static int
1027 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1028                          struct sdhci_host *host,
1029                          struct pltfm_imx_data *imx_data)
1030 {
1031         struct device_node *np = pdev->dev.of_node;
1032         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1033         int ret;
1034 
1035         if (of_get_property(np, "fsl,wp-controller", NULL))
1036                 boarddata->wp_type = ESDHC_WP_CONTROLLER;
1037 
1038         boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
1039         if (gpio_is_valid(boarddata->wp_gpio))
1040                 boarddata->wp_type = ESDHC_WP_GPIO;
1041 
1042         of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
1043         of_property_read_u32(np, "fsl,tuning-start-tap",
1044                              &boarddata->tuning_start_tap);
1045 
1046         if (of_find_property(np, "no-1-8-v", NULL))
1047                 boarddata->support_vsel = false;
1048         else
1049                 boarddata->support_vsel = true;
1050 
1051         if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
1052                 boarddata->delay_line = 0;
1053 
1054         mmc_of_parse_voltage(np, &host->ocr_mask);
1055 
1056         /* sdr50 and sdr104 needs work on 1.8v signal voltage */
1057         if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) &&
1058             !IS_ERR(imx_data->pins_default)) {
1059                 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1060                                                 ESDHC_PINCTRL_STATE_100MHZ);
1061                 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1062                                                 ESDHC_PINCTRL_STATE_200MHZ);
1063                 if (IS_ERR(imx_data->pins_100mhz) ||
1064                                 IS_ERR(imx_data->pins_200mhz)) {
1065                         dev_warn(mmc_dev(host->mmc),
1066                                 "could not get ultra high speed state, work on normal mode\n");
1067                         /*
1068                          * fall back to not support uhs by specify no 1.8v quirk
1069                          */
1070                         host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1071                 }
1072         } else {
1073                 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1074         }
1075 
1076         /* call to generic mmc_of_parse to support additional capabilities */
1077         ret = mmc_of_parse(host->mmc);
1078         if (ret)
1079                 return ret;
1080 
1081         if (mmc_gpio_get_cd(host->mmc) >= 0)
1082                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1083 
1084         return 0;
1085 }
1086 #else
1087 static inline int
1088 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1089                          struct sdhci_host *host,
1090                          struct pltfm_imx_data *imx_data)
1091 {
1092         return -ENODEV;
1093 }
1094 #endif
1095 
1096 static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev,
1097                          struct sdhci_host *host,
1098                          struct pltfm_imx_data *imx_data)
1099 {
1100         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1101         int err;
1102 
1103         if (!host->mmc->parent->platform_data) {
1104                 dev_err(mmc_dev(host->mmc), "no board data!\n");
1105                 return -EINVAL;
1106         }
1107 
1108         imx_data->boarddata = *((struct esdhc_platform_data *)
1109                                 host->mmc->parent->platform_data);
1110         /* write_protect */
1111         if (boarddata->wp_type == ESDHC_WP_GPIO) {
1112                 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
1113                 if (err) {
1114                         dev_err(mmc_dev(host->mmc),
1115                                 "failed to request write-protect gpio!\n");
1116                         return err;
1117                 }
1118                 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1119         }
1120 
1121         /* card_detect */
1122         switch (boarddata->cd_type) {
1123         case ESDHC_CD_GPIO:
1124                 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
1125                 if (err) {
1126                         dev_err(mmc_dev(host->mmc),
1127                                 "failed to request card-detect gpio!\n");
1128                         return err;
1129                 }
1130                 /* fall through */
1131 
1132         case ESDHC_CD_CONTROLLER:
1133                 /* we have a working card_detect back */
1134                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1135                 break;
1136 
1137         case ESDHC_CD_PERMANENT:
1138                 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
1139                 break;
1140 
1141         case ESDHC_CD_NONE:
1142                 break;
1143         }
1144 
1145         switch (boarddata->max_bus_width) {
1146         case 8:
1147                 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
1148                 break;
1149         case 4:
1150                 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
1151                 break;
1152         case 1:
1153         default:
1154                 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1155                 break;
1156         }
1157 
1158         return 0;
1159 }
1160 
1161 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1162 {
1163         const struct of_device_id *of_id =
1164                         of_match_device(imx_esdhc_dt_ids, &pdev->dev);
1165         struct sdhci_pltfm_host *pltfm_host;
1166         struct sdhci_host *host;
1167         int err;
1168         struct pltfm_imx_data *imx_data;
1169 
1170         host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1171                                 sizeof(*imx_data));
1172         if (IS_ERR(host))
1173                 return PTR_ERR(host);
1174 
1175         pltfm_host = sdhci_priv(host);
1176 
1177         imx_data = sdhci_pltfm_priv(pltfm_host);
1178 
1179         imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
1180                                                   pdev->id_entry->driver_data;
1181 
1182         imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1183         if (IS_ERR(imx_data->clk_ipg)) {
1184                 err = PTR_ERR(imx_data->clk_ipg);
1185                 goto free_sdhci;
1186         }
1187 
1188         imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1189         if (IS_ERR(imx_data->clk_ahb)) {
1190                 err = PTR_ERR(imx_data->clk_ahb);
1191                 goto free_sdhci;
1192         }
1193 
1194         imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1195         if (IS_ERR(imx_data->clk_per)) {
1196                 err = PTR_ERR(imx_data->clk_per);
1197                 goto free_sdhci;
1198         }
1199 
1200         pltfm_host->clk = imx_data->clk_per;
1201         pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1202         clk_prepare_enable(imx_data->clk_per);
1203         clk_prepare_enable(imx_data->clk_ipg);
1204         clk_prepare_enable(imx_data->clk_ahb);
1205 
1206         imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1207         if (IS_ERR(imx_data->pinctrl)) {
1208                 err = PTR_ERR(imx_data->pinctrl);
1209                 goto disable_clk;
1210         }
1211 
1212         imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
1213                                                 PINCTRL_STATE_DEFAULT);
1214         if (IS_ERR(imx_data->pins_default))
1215                 dev_warn(mmc_dev(host->mmc), "could not get default state\n");
1216 
1217         if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207)
1218                 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
1219                 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
1220                         | SDHCI_QUIRK_BROKEN_ADMA;
1221 
1222         if (esdhc_is_usdhc(imx_data)) {
1223                 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1224                 host->mmc->caps |= MMC_CAP_1_8V_DDR;
1225                 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1226                         host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1227 
1228                 /* clear tuning bits in case ROM has set it already */
1229                 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1230                 writel(0x0, host->ioaddr + SDHCI_ACMD12_ERR);
1231                 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1232         }
1233 
1234         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1235                 sdhci_esdhc_ops.platform_execute_tuning =
1236                                         esdhc_executing_tuning;
1237 
1238         if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1239                 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1240 
1241         if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
1242                 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
1243 
1244         if (of_id)
1245                 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1246         else
1247                 err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data);
1248         if (err)
1249                 goto disable_clk;
1250 
1251         sdhci_esdhc_imx_hwinit(host);
1252 
1253         err = sdhci_add_host(host);
1254         if (err)
1255                 goto disable_clk;
1256 
1257         pm_runtime_set_active(&pdev->dev);
1258         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1259         pm_runtime_use_autosuspend(&pdev->dev);
1260         pm_suspend_ignore_children(&pdev->dev, 1);
1261         pm_runtime_enable(&pdev->dev);
1262 
1263         return 0;
1264 
1265 disable_clk:
1266         clk_disable_unprepare(imx_data->clk_per);
1267         clk_disable_unprepare(imx_data->clk_ipg);
1268         clk_disable_unprepare(imx_data->clk_ahb);
1269 free_sdhci:
1270         sdhci_pltfm_free(pdev);
1271         return err;
1272 }
1273 
1274 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1275 {
1276         struct sdhci_host *host = platform_get_drvdata(pdev);
1277         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1278         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1279         int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1280 
1281         pm_runtime_get_sync(&pdev->dev);
1282         pm_runtime_disable(&pdev->dev);
1283         pm_runtime_put_noidle(&pdev->dev);
1284 
1285         sdhci_remove_host(host, dead);
1286 
1287         clk_disable_unprepare(imx_data->clk_per);
1288         clk_disable_unprepare(imx_data->clk_ipg);
1289         clk_disable_unprepare(imx_data->clk_ahb);
1290 
1291         sdhci_pltfm_free(pdev);
1292 
1293         return 0;
1294 }
1295 
1296 #ifdef CONFIG_PM_SLEEP
1297 static int sdhci_esdhc_suspend(struct device *dev)
1298 {
1299         struct sdhci_host *host = dev_get_drvdata(dev);
1300 
1301         return sdhci_suspend_host(host);
1302 }
1303 
1304 static int sdhci_esdhc_resume(struct device *dev)
1305 {
1306         struct sdhci_host *host = dev_get_drvdata(dev);
1307 
1308         /* re-initialize hw state in case it's lost in low power mode */
1309         sdhci_esdhc_imx_hwinit(host);
1310 
1311         return sdhci_resume_host(host);
1312 }
1313 #endif
1314 
1315 #ifdef CONFIG_PM
1316 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1317 {
1318         struct sdhci_host *host = dev_get_drvdata(dev);
1319         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1320         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1321         int ret;
1322 
1323         ret = sdhci_runtime_suspend_host(host);
1324 
1325         if (!sdhci_sdio_irq_enabled(host)) {
1326                 clk_disable_unprepare(imx_data->clk_per);
1327                 clk_disable_unprepare(imx_data->clk_ipg);
1328         }
1329         clk_disable_unprepare(imx_data->clk_ahb);
1330 
1331         return ret;
1332 }
1333 
1334 static int sdhci_esdhc_runtime_resume(struct device *dev)
1335 {
1336         struct sdhci_host *host = dev_get_drvdata(dev);
1337         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1338         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1339 
1340         if (!sdhci_sdio_irq_enabled(host)) {
1341                 clk_prepare_enable(imx_data->clk_per);
1342                 clk_prepare_enable(imx_data->clk_ipg);
1343         }
1344         clk_prepare_enable(imx_data->clk_ahb);
1345 
1346         return sdhci_runtime_resume_host(host);
1347 }
1348 #endif
1349 
1350 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1351         SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
1352         SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1353                                 sdhci_esdhc_runtime_resume, NULL)
1354 };
1355 
1356 static struct platform_driver sdhci_esdhc_imx_driver = {
1357         .driver         = {
1358                 .name   = "sdhci-esdhc-imx",
1359                 .of_match_table = imx_esdhc_dt_ids,
1360                 .pm     = &sdhci_esdhc_pmops,
1361         },
1362         .id_table       = imx_esdhc_devtype,
1363         .probe          = sdhci_esdhc_imx_probe,
1364         .remove         = sdhci_esdhc_imx_remove,
1365 };
1366 
1367 module_platform_driver(sdhci_esdhc_imx_driver);
1368 
1369 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1370 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1371 MODULE_LICENSE("GPL v2");
1372 

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