Version:  2.0.40 2.2.26 2.4.37 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10

Linux/drivers/mmc/host/s3cmci.c

  1 /*
  2  *  linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
  3  *
  4  *  Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
  5  *
  6  * Current driver maintained by Ben Dooks and Simtec Electronics
  7  *  Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org>
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2 as
 11  * published by the Free Software Foundation.
 12  */
 13 
 14 #include <linux/module.h>
 15 #include <linux/dmaengine.h>
 16 #include <linux/dma-mapping.h>
 17 #include <linux/clk.h>
 18 #include <linux/mmc/host.h>
 19 #include <linux/platform_device.h>
 20 #include <linux/cpufreq.h>
 21 #include <linux/debugfs.h>
 22 #include <linux/seq_file.h>
 23 #include <linux/gpio.h>
 24 #include <linux/irq.h>
 25 #include <linux/io.h>
 26 
 27 #include <plat/gpio-cfg.h>
 28 #include <mach/dma.h>
 29 #include <mach/gpio-samsung.h>
 30 
 31 #include <linux/platform_data/mmc-s3cmci.h>
 32 
 33 #include "s3cmci.h"
 34 
 35 #define DRIVER_NAME "s3c-mci"
 36 
 37 #define S3C2410_SDICON                  (0x00)
 38 #define S3C2410_SDIPRE                  (0x04)
 39 #define S3C2410_SDICMDARG               (0x08)
 40 #define S3C2410_SDICMDCON               (0x0C)
 41 #define S3C2410_SDICMDSTAT              (0x10)
 42 #define S3C2410_SDIRSP0                 (0x14)
 43 #define S3C2410_SDIRSP1                 (0x18)
 44 #define S3C2410_SDIRSP2                 (0x1C)
 45 #define S3C2410_SDIRSP3                 (0x20)
 46 #define S3C2410_SDITIMER                (0x24)
 47 #define S3C2410_SDIBSIZE                (0x28)
 48 #define S3C2410_SDIDCON                 (0x2C)
 49 #define S3C2410_SDIDCNT                 (0x30)
 50 #define S3C2410_SDIDSTA                 (0x34)
 51 #define S3C2410_SDIFSTA                 (0x38)
 52 
 53 #define S3C2410_SDIDATA                 (0x3C)
 54 #define S3C2410_SDIIMSK                 (0x40)
 55 
 56 #define S3C2440_SDIDATA                 (0x40)
 57 #define S3C2440_SDIIMSK                 (0x3C)
 58 
 59 #define S3C2440_SDICON_SDRESET          (1 << 8)
 60 #define S3C2410_SDICON_SDIOIRQ          (1 << 3)
 61 #define S3C2410_SDICON_FIFORESET        (1 << 1)
 62 #define S3C2410_SDICON_CLOCKTYPE        (1 << 0)
 63 
 64 #define S3C2410_SDICMDCON_LONGRSP       (1 << 10)
 65 #define S3C2410_SDICMDCON_WAITRSP       (1 << 9)
 66 #define S3C2410_SDICMDCON_CMDSTART      (1 << 8)
 67 #define S3C2410_SDICMDCON_SENDERHOST    (1 << 6)
 68 #define S3C2410_SDICMDCON_INDEX         (0x3f)
 69 
 70 #define S3C2410_SDICMDSTAT_CRCFAIL      (1 << 12)
 71 #define S3C2410_SDICMDSTAT_CMDSENT      (1 << 11)
 72 #define S3C2410_SDICMDSTAT_CMDTIMEOUT   (1 << 10)
 73 #define S3C2410_SDICMDSTAT_RSPFIN       (1 << 9)
 74 
 75 #define S3C2440_SDIDCON_DS_WORD         (2 << 22)
 76 #define S3C2410_SDIDCON_TXAFTERRESP     (1 << 20)
 77 #define S3C2410_SDIDCON_RXAFTERCMD      (1 << 19)
 78 #define S3C2410_SDIDCON_BLOCKMODE       (1 << 17)
 79 #define S3C2410_SDIDCON_WIDEBUS         (1 << 16)
 80 #define S3C2410_SDIDCON_DMAEN           (1 << 15)
 81 #define S3C2410_SDIDCON_STOP            (1 << 14)
 82 #define S3C2440_SDIDCON_DATSTART        (1 << 14)
 83 
 84 #define S3C2410_SDIDCON_XFER_RXSTART    (2 << 12)
 85 #define S3C2410_SDIDCON_XFER_TXSTART    (3 << 12)
 86 
 87 #define S3C2410_SDIDCON_BLKNUM_MASK     (0xFFF)
 88 
 89 #define S3C2410_SDIDSTA_SDIOIRQDETECT   (1 << 9)
 90 #define S3C2410_SDIDSTA_FIFOFAIL        (1 << 8)
 91 #define S3C2410_SDIDSTA_CRCFAIL         (1 << 7)
 92 #define S3C2410_SDIDSTA_RXCRCFAIL       (1 << 6)
 93 #define S3C2410_SDIDSTA_DATATIMEOUT     (1 << 5)
 94 #define S3C2410_SDIDSTA_XFERFINISH      (1 << 4)
 95 #define S3C2410_SDIDSTA_TXDATAON        (1 << 1)
 96 #define S3C2410_SDIDSTA_RXDATAON        (1 << 0)
 97 
 98 #define S3C2440_SDIFSTA_FIFORESET       (1 << 16)
 99 #define S3C2440_SDIFSTA_FIFOFAIL        (3 << 14)
100 #define S3C2410_SDIFSTA_TFDET           (1 << 13)
101 #define S3C2410_SDIFSTA_RFDET           (1 << 12)
102 #define S3C2410_SDIFSTA_COUNTMASK       (0x7f)
103 
104 #define S3C2410_SDIIMSK_RESPONSECRC     (1 << 17)
105 #define S3C2410_SDIIMSK_CMDSENT         (1 << 16)
106 #define S3C2410_SDIIMSK_CMDTIMEOUT      (1 << 15)
107 #define S3C2410_SDIIMSK_RESPONSEND      (1 << 14)
108 #define S3C2410_SDIIMSK_SDIOIRQ         (1 << 12)
109 #define S3C2410_SDIIMSK_FIFOFAIL        (1 << 11)
110 #define S3C2410_SDIIMSK_CRCSTATUS       (1 << 10)
111 #define S3C2410_SDIIMSK_DATACRC         (1 << 9)
112 #define S3C2410_SDIIMSK_DATATIMEOUT     (1 << 8)
113 #define S3C2410_SDIIMSK_DATAFINISH      (1 << 7)
114 #define S3C2410_SDIIMSK_TXFIFOHALF      (1 << 4)
115 #define S3C2410_SDIIMSK_RXFIFOLAST      (1 << 2)
116 #define S3C2410_SDIIMSK_RXFIFOHALF      (1 << 0)
117 
118 enum dbg_channels {
119         dbg_err   = (1 << 0),
120         dbg_debug = (1 << 1),
121         dbg_info  = (1 << 2),
122         dbg_irq   = (1 << 3),
123         dbg_sg    = (1 << 4),
124         dbg_dma   = (1 << 5),
125         dbg_pio   = (1 << 6),
126         dbg_fail  = (1 << 7),
127         dbg_conf  = (1 << 8),
128 };
129 
130 static const int dbgmap_err   = dbg_fail;
131 static const int dbgmap_info  = dbg_info | dbg_conf;
132 static const int dbgmap_debug = dbg_err | dbg_debug;
133 
134 #define dbg(host, channels, args...)              \
135         do {                                      \
136         if (dbgmap_err & channels)                \
137                 dev_err(&host->pdev->dev, args);  \
138         else if (dbgmap_info & channels)          \
139                 dev_info(&host->pdev->dev, args); \
140         else if (dbgmap_debug & channels)         \
141                 dev_dbg(&host->pdev->dev, args);  \
142         } while (0)
143 
144 static void finalize_request(struct s3cmci_host *host);
145 static void s3cmci_send_request(struct mmc_host *mmc);
146 static void s3cmci_reset(struct s3cmci_host *host);
147 
148 #ifdef CONFIG_MMC_DEBUG
149 
150 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix)
151 {
152         u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize;
153         u32 datcon, datcnt, datsta, fsta, imask;
154 
155         con     = readl(host->base + S3C2410_SDICON);
156         pre     = readl(host->base + S3C2410_SDIPRE);
157         cmdarg  = readl(host->base + S3C2410_SDICMDARG);
158         cmdcon  = readl(host->base + S3C2410_SDICMDCON);
159         cmdsta  = readl(host->base + S3C2410_SDICMDSTAT);
160         r0      = readl(host->base + S3C2410_SDIRSP0);
161         r1      = readl(host->base + S3C2410_SDIRSP1);
162         r2      = readl(host->base + S3C2410_SDIRSP2);
163         r3      = readl(host->base + S3C2410_SDIRSP3);
164         timer   = readl(host->base + S3C2410_SDITIMER);
165         bsize   = readl(host->base + S3C2410_SDIBSIZE);
166         datcon  = readl(host->base + S3C2410_SDIDCON);
167         datcnt  = readl(host->base + S3C2410_SDIDCNT);
168         datsta  = readl(host->base + S3C2410_SDIDSTA);
169         fsta    = readl(host->base + S3C2410_SDIFSTA);
170         imask   = readl(host->base + host->sdiimsk);
171 
172         dbg(host, dbg_debug, "%s  CON:[%08x]  PRE:[%08x]  TMR:[%08x]\n",
173                                 prefix, con, pre, timer);
174 
175         dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
176                                 prefix, cmdcon, cmdarg, cmdsta);
177 
178         dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]"
179                                " DSTA:[%08x] DCNT:[%08x]\n",
180                                 prefix, datcon, fsta, datsta, datcnt);
181 
182         dbg(host, dbg_debug, "%s   R0:[%08x]   R1:[%08x]"
183                                "   R2:[%08x]   R3:[%08x]\n",
184                                 prefix, r0, r1, r2, r3);
185 }
186 
187 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
188                            int stop)
189 {
190         snprintf(host->dbgmsg_cmd, 300,
191                  "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u",
192                  host->ccnt, (stop ? " (STOP)" : ""),
193                  cmd->opcode, cmd->arg, cmd->flags, cmd->retries);
194 
195         if (cmd->data) {
196                 snprintf(host->dbgmsg_dat, 300,
197                          "#%u bsize:%u blocks:%u bytes:%u",
198                          host->dcnt, cmd->data->blksz,
199                          cmd->data->blocks,
200                          cmd->data->blocks * cmd->data->blksz);
201         } else {
202                 host->dbgmsg_dat[0] = '\0';
203         }
204 }
205 
206 static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd,
207                         int fail)
208 {
209         unsigned int dbglvl = fail ? dbg_fail : dbg_debug;
210 
211         if (!cmd)
212                 return;
213 
214         if (cmd->error == 0) {
215                 dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n",
216                         host->dbgmsg_cmd, cmd->resp[0]);
217         } else {
218                 dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n",
219                         cmd->error, host->dbgmsg_cmd, host->status);
220         }
221 
222         if (!cmd->data)
223                 return;
224 
225         if (cmd->data->error == 0) {
226                 dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat);
227         } else {
228                 dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n",
229                         cmd->data->error, host->dbgmsg_dat,
230                         readl(host->base + S3C2410_SDIDCNT));
231         }
232 }
233 #else
234 static void dbg_dumpcmd(struct s3cmci_host *host,
235                         struct mmc_command *cmd, int fail) { }
236 
237 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
238                            int stop) { }
239 
240 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
241 
242 #endif /* CONFIG_MMC_DEBUG */
243 
244 /**
245  * s3cmci_host_usedma - return whether the host is using dma or pio
246  * @host: The host state
247  *
248  * Return true if the host is using DMA to transfer data, else false
249  * to use PIO mode. Will return static data depending on the driver
250  * configuration.
251  */
252 static inline bool s3cmci_host_usedma(struct s3cmci_host *host)
253 {
254 #ifdef CONFIG_MMC_S3C_PIO
255         return false;
256 #else /* CONFIG_MMC_S3C_DMA */
257         return true;
258 #endif
259 }
260 
261 static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
262 {
263         u32 newmask;
264 
265         newmask = readl(host->base + host->sdiimsk);
266         newmask |= imask;
267 
268         writel(newmask, host->base + host->sdiimsk);
269 
270         return newmask;
271 }
272 
273 static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
274 {
275         u32 newmask;
276 
277         newmask = readl(host->base + host->sdiimsk);
278         newmask &= ~imask;
279 
280         writel(newmask, host->base + host->sdiimsk);
281 
282         return newmask;
283 }
284 
285 static inline void clear_imask(struct s3cmci_host *host)
286 {
287         u32 mask = readl(host->base + host->sdiimsk);
288 
289         /* preserve the SDIO IRQ mask state */
290         mask &= S3C2410_SDIIMSK_SDIOIRQ;
291         writel(mask, host->base + host->sdiimsk);
292 }
293 
294 /**
295  * s3cmci_check_sdio_irq - test whether the SDIO IRQ is being signalled
296  * @host: The host to check.
297  *
298  * Test to see if the SDIO interrupt is being signalled in case the
299  * controller has failed to re-detect a card interrupt. Read GPE8 and
300  * see if it is low and if so, signal a SDIO interrupt.
301  *
302  * This is currently called if a request is finished (we assume that the
303  * bus is now idle) and when the SDIO IRQ is enabled in case the IRQ is
304  * already being indicated.
305 */
306 static void s3cmci_check_sdio_irq(struct s3cmci_host *host)
307 {
308         if (host->sdio_irqen) {
309                 if (gpio_get_value(S3C2410_GPE(8)) == 0) {
310                         pr_debug("%s: signalling irq\n", __func__);
311                         mmc_signal_sdio_irq(host->mmc);
312                 }
313         }
314 }
315 
316 static inline int get_data_buffer(struct s3cmci_host *host,
317                                   u32 *bytes, u32 **pointer)
318 {
319         struct scatterlist *sg;
320 
321         if (host->pio_active == XFER_NONE)
322                 return -EINVAL;
323 
324         if ((!host->mrq) || (!host->mrq->data))
325                 return -EINVAL;
326 
327         if (host->pio_sgptr >= host->mrq->data->sg_len) {
328                 dbg(host, dbg_debug, "no more buffers (%i/%i)\n",
329                       host->pio_sgptr, host->mrq->data->sg_len);
330                 return -EBUSY;
331         }
332         sg = &host->mrq->data->sg[host->pio_sgptr];
333 
334         *bytes = sg->length;
335         *pointer = sg_virt(sg);
336 
337         host->pio_sgptr++;
338 
339         dbg(host, dbg_sg, "new buffer (%i/%i)\n",
340             host->pio_sgptr, host->mrq->data->sg_len);
341 
342         return 0;
343 }
344 
345 static inline u32 fifo_count(struct s3cmci_host *host)
346 {
347         u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
348 
349         fifostat &= S3C2410_SDIFSTA_COUNTMASK;
350         return fifostat;
351 }
352 
353 static inline u32 fifo_free(struct s3cmci_host *host)
354 {
355         u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
356 
357         fifostat &= S3C2410_SDIFSTA_COUNTMASK;
358         return 63 - fifostat;
359 }
360 
361 /**
362  * s3cmci_enable_irq - enable IRQ, after having disabled it.
363  * @host: The device state.
364  * @more: True if more IRQs are expected from transfer.
365  *
366  * Enable the main IRQ if needed after it has been disabled.
367  *
368  * The IRQ can be one of the following states:
369  *      - disabled during IDLE
370  *      - disabled whilst processing data
371  *      - enabled during transfer
372  *      - enabled whilst awaiting SDIO interrupt detection
373  */
374 static void s3cmci_enable_irq(struct s3cmci_host *host, bool more)
375 {
376         unsigned long flags;
377         bool enable = false;
378 
379         local_irq_save(flags);
380 
381         host->irq_enabled = more;
382         host->irq_disabled = false;
383 
384         enable = more | host->sdio_irqen;
385 
386         if (host->irq_state != enable) {
387                 host->irq_state = enable;
388 
389                 if (enable)
390                         enable_irq(host->irq);
391                 else
392                         disable_irq(host->irq);
393         }
394 
395         local_irq_restore(flags);
396 }
397 
398 /**
399  *
400  */
401 static void s3cmci_disable_irq(struct s3cmci_host *host, bool transfer)
402 {
403         unsigned long flags;
404 
405         local_irq_save(flags);
406 
407         /* pr_debug("%s: transfer %d\n", __func__, transfer); */
408 
409         host->irq_disabled = transfer;
410 
411         if (transfer && host->irq_state) {
412                 host->irq_state = false;
413                 disable_irq(host->irq);
414         }
415 
416         local_irq_restore(flags);
417 }
418 
419 static void do_pio_read(struct s3cmci_host *host)
420 {
421         int res;
422         u32 fifo;
423         u32 *ptr;
424         u32 fifo_words;
425         void __iomem *from_ptr;
426 
427         /* write real prescaler to host, it might be set slow to fix */
428         writel(host->prescaler, host->base + S3C2410_SDIPRE);
429 
430         from_ptr = host->base + host->sdidata;
431 
432         while ((fifo = fifo_count(host))) {
433                 if (!host->pio_bytes) {
434                         res = get_data_buffer(host, &host->pio_bytes,
435                                               &host->pio_ptr);
436                         if (res) {
437                                 host->pio_active = XFER_NONE;
438                                 host->complete_what = COMPLETION_FINALIZE;
439 
440                                 dbg(host, dbg_pio, "pio_read(): "
441                                     "complete (no more data).\n");
442                                 return;
443                         }
444 
445                         dbg(host, dbg_pio,
446                             "pio_read(): new target: [%i]@[%p]\n",
447                             host->pio_bytes, host->pio_ptr);
448                 }
449 
450                 dbg(host, dbg_pio,
451                     "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n",
452                     fifo, host->pio_bytes,
453                     readl(host->base + S3C2410_SDIDCNT));
454 
455                 /* If we have reached the end of the block, we can
456                  * read a word and get 1 to 3 bytes.  If we in the
457                  * middle of the block, we have to read full words,
458                  * otherwise we will write garbage, so round down to
459                  * an even multiple of 4. */
460                 if (fifo >= host->pio_bytes)
461                         fifo = host->pio_bytes;
462                 else
463                         fifo -= fifo & 3;
464 
465                 host->pio_bytes -= fifo;
466                 host->pio_count += fifo;
467 
468                 fifo_words = fifo >> 2;
469                 ptr = host->pio_ptr;
470                 while (fifo_words--)
471                         *ptr++ = readl(from_ptr);
472                 host->pio_ptr = ptr;
473 
474                 if (fifo & 3) {
475                         u32 n = fifo & 3;
476                         u32 data = readl(from_ptr);
477                         u8 *p = (u8 *)host->pio_ptr;
478 
479                         while (n--) {
480                                 *p++ = data;
481                                 data >>= 8;
482                         }
483                 }
484         }
485 
486         if (!host->pio_bytes) {
487                 res = get_data_buffer(host, &host->pio_bytes, &host->pio_ptr);
488                 if (res) {
489                         dbg(host, dbg_pio,
490                             "pio_read(): complete (no more buffers).\n");
491                         host->pio_active = XFER_NONE;
492                         host->complete_what = COMPLETION_FINALIZE;
493 
494                         return;
495                 }
496         }
497 
498         enable_imask(host,
499                      S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST);
500 }
501 
502 static void do_pio_write(struct s3cmci_host *host)
503 {
504         void __iomem *to_ptr;
505         int res;
506         u32 fifo;
507         u32 *ptr;
508 
509         to_ptr = host->base + host->sdidata;
510 
511         while ((fifo = fifo_free(host)) > 3) {
512                 if (!host->pio_bytes) {
513                         res = get_data_buffer(host, &host->pio_bytes,
514                                                         &host->pio_ptr);
515                         if (res) {
516                                 dbg(host, dbg_pio,
517                                     "pio_write(): complete (no more data).\n");
518                                 host->pio_active = XFER_NONE;
519 
520                                 return;
521                         }
522 
523                         dbg(host, dbg_pio,
524                             "pio_write(): new source: [%i]@[%p]\n",
525                             host->pio_bytes, host->pio_ptr);
526 
527                 }
528 
529                 /* If we have reached the end of the block, we have to
530                  * write exactly the remaining number of bytes.  If we
531                  * in the middle of the block, we have to write full
532                  * words, so round down to an even multiple of 4. */
533                 if (fifo >= host->pio_bytes)
534                         fifo = host->pio_bytes;
535                 else
536                         fifo -= fifo & 3;
537 
538                 host->pio_bytes -= fifo;
539                 host->pio_count += fifo;
540 
541                 fifo = (fifo + 3) >> 2;
542                 ptr = host->pio_ptr;
543                 while (fifo--)
544                         writel(*ptr++, to_ptr);
545                 host->pio_ptr = ptr;
546         }
547 
548         enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
549 }
550 
551 static void pio_tasklet(unsigned long data)
552 {
553         struct s3cmci_host *host = (struct s3cmci_host *) data;
554 
555         s3cmci_disable_irq(host, true);
556 
557         if (host->pio_active == XFER_WRITE)
558                 do_pio_write(host);
559 
560         if (host->pio_active == XFER_READ)
561                 do_pio_read(host);
562 
563         if (host->complete_what == COMPLETION_FINALIZE) {
564                 clear_imask(host);
565                 if (host->pio_active != XFER_NONE) {
566                         dbg(host, dbg_err, "unfinished %s "
567                             "- pio_count:[%u] pio_bytes:[%u]\n",
568                             (host->pio_active == XFER_READ) ? "read" : "write",
569                             host->pio_count, host->pio_bytes);
570 
571                         if (host->mrq->data)
572                                 host->mrq->data->error = -EINVAL;
573                 }
574 
575                 s3cmci_enable_irq(host, false);
576                 finalize_request(host);
577         } else
578                 s3cmci_enable_irq(host, true);
579 }
580 
581 /*
582  * ISR for SDI Interface IRQ
583  * Communication between driver and ISR works as follows:
584  *   host->mrq                  points to current request
585  *   host->complete_what        Indicates when the request is considered done
586  *     COMPLETION_CMDSENT         when the command was sent
587  *     COMPLETION_RSPFIN          when a response was received
588  *     COMPLETION_XFERFINISH      when the data transfer is finished
589  *     COMPLETION_XFERFINISH_RSPFIN both of the above.
590  *   host->complete_request     is the completion-object the driver waits for
591  *
592  * 1) Driver sets up host->mrq and host->complete_what
593  * 2) Driver prepares the transfer
594  * 3) Driver enables interrupts
595  * 4) Driver starts transfer
596  * 5) Driver waits for host->complete_rquest
597  * 6) ISR checks for request status (errors and success)
598  * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
599  * 7) ISR completes host->complete_request
600  * 8) ISR disables interrupts
601  * 9) Driver wakes up and takes care of the request
602  *
603  * Note: "->error"-fields are expected to be set to 0 before the request
604  *       was issued by mmc.c - therefore they are only set, when an error
605  *       contition comes up
606  */
607 
608 static irqreturn_t s3cmci_irq(int irq, void *dev_id)
609 {
610         struct s3cmci_host *host = dev_id;
611         struct mmc_command *cmd;
612         u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk;
613         u32 mci_cclear = 0, mci_dclear;
614         unsigned long iflags;
615 
616         mci_dsta = readl(host->base + S3C2410_SDIDSTA);
617         mci_imsk = readl(host->base + host->sdiimsk);
618 
619         if (mci_dsta & S3C2410_SDIDSTA_SDIOIRQDETECT) {
620                 if (mci_imsk & S3C2410_SDIIMSK_SDIOIRQ) {
621                         mci_dclear = S3C2410_SDIDSTA_SDIOIRQDETECT;
622                         writel(mci_dclear, host->base + S3C2410_SDIDSTA);
623 
624                         mmc_signal_sdio_irq(host->mmc);
625                         return IRQ_HANDLED;
626                 }
627         }
628 
629         spin_lock_irqsave(&host->complete_lock, iflags);
630 
631         mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
632         mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
633         mci_fsta = readl(host->base + S3C2410_SDIFSTA);
634         mci_dclear = 0;
635 
636         if ((host->complete_what == COMPLETION_NONE) ||
637             (host->complete_what == COMPLETION_FINALIZE)) {
638                 host->status = "nothing to complete";
639                 clear_imask(host);
640                 goto irq_out;
641         }
642 
643         if (!host->mrq) {
644                 host->status = "no active mrq";
645                 clear_imask(host);
646                 goto irq_out;
647         }
648 
649         cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd;
650 
651         if (!cmd) {
652                 host->status = "no active cmd";
653                 clear_imask(host);
654                 goto irq_out;
655         }
656 
657         if (!s3cmci_host_usedma(host)) {
658                 if ((host->pio_active == XFER_WRITE) &&
659                     (mci_fsta & S3C2410_SDIFSTA_TFDET)) {
660 
661                         disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
662                         tasklet_schedule(&host->pio_tasklet);
663                         host->status = "pio tx";
664                 }
665 
666                 if ((host->pio_active == XFER_READ) &&
667                     (mci_fsta & S3C2410_SDIFSTA_RFDET)) {
668 
669                         disable_imask(host,
670                                       S3C2410_SDIIMSK_RXFIFOHALF |
671                                       S3C2410_SDIIMSK_RXFIFOLAST);
672 
673                         tasklet_schedule(&host->pio_tasklet);
674                         host->status = "pio rx";
675                 }
676         }
677 
678         if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) {
679                 dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n");
680                 cmd->error = -ETIMEDOUT;
681                 host->status = "error: command timeout";
682                 goto fail_transfer;
683         }
684 
685         if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) {
686                 if (host->complete_what == COMPLETION_CMDSENT) {
687                         host->status = "ok: command sent";
688                         goto close_transfer;
689                 }
690 
691                 mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT;
692         }
693 
694         if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) {
695                 if (cmd->flags & MMC_RSP_CRC) {
696                         if (host->mrq->cmd->flags & MMC_RSP_136) {
697                                 dbg(host, dbg_irq,
698                                     "fixup: ignore CRC fail with long rsp\n");
699                         } else {
700                                 /* note, we used to fail the transfer
701                                  * here, but it seems that this is just
702                                  * the hardware getting it wrong.
703                                  *
704                                  * cmd->error = -EILSEQ;
705                                  * host->status = "error: bad command crc";
706                                  * goto fail_transfer;
707                                 */
708                         }
709                 }
710 
711                 mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL;
712         }
713 
714         if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) {
715                 if (host->complete_what == COMPLETION_RSPFIN) {
716                         host->status = "ok: command response received";
717                         goto close_transfer;
718                 }
719 
720                 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
721                         host->complete_what = COMPLETION_XFERFINISH;
722 
723                 mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN;
724         }
725 
726         /* errors handled after this point are only relevant
727            when a data transfer is in progress */
728 
729         if (!cmd->data)
730                 goto clear_status_bits;
731 
732         /* Check for FIFO failure */
733         if (host->is2440) {
734                 if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) {
735                         dbg(host, dbg_err, "FIFO failure\n");
736                         host->mrq->data->error = -EILSEQ;
737                         host->status = "error: 2440 fifo failure";
738                         goto fail_transfer;
739                 }
740         } else {
741                 if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) {
742                         dbg(host, dbg_err, "FIFO failure\n");
743                         cmd->data->error = -EILSEQ;
744                         host->status = "error:  fifo failure";
745                         goto fail_transfer;
746                 }
747         }
748 
749         if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) {
750                 dbg(host, dbg_err, "bad data crc (outgoing)\n");
751                 cmd->data->error = -EILSEQ;
752                 host->status = "error: bad data crc (outgoing)";
753                 goto fail_transfer;
754         }
755 
756         if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) {
757                 dbg(host, dbg_err, "bad data crc (incoming)\n");
758                 cmd->data->error = -EILSEQ;
759                 host->status = "error: bad data crc (incoming)";
760                 goto fail_transfer;
761         }
762 
763         if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) {
764                 dbg(host, dbg_err, "data timeout\n");
765                 cmd->data->error = -ETIMEDOUT;
766                 host->status = "error: data timeout";
767                 goto fail_transfer;
768         }
769 
770         if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) {
771                 if (host->complete_what == COMPLETION_XFERFINISH) {
772                         host->status = "ok: data transfer completed";
773                         goto close_transfer;
774                 }
775 
776                 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
777                         host->complete_what = COMPLETION_RSPFIN;
778 
779                 mci_dclear |= S3C2410_SDIDSTA_XFERFINISH;
780         }
781 
782 clear_status_bits:
783         writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
784         writel(mci_dclear, host->base + S3C2410_SDIDSTA);
785 
786         goto irq_out;
787 
788 fail_transfer:
789         host->pio_active = XFER_NONE;
790 
791 close_transfer:
792         host->complete_what = COMPLETION_FINALIZE;
793 
794         clear_imask(host);
795         tasklet_schedule(&host->pio_tasklet);
796 
797         goto irq_out;
798 
799 irq_out:
800         dbg(host, dbg_irq,
801             "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n",
802             mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status);
803 
804         spin_unlock_irqrestore(&host->complete_lock, iflags);
805         return IRQ_HANDLED;
806 
807 }
808 
809 /*
810  * ISR for the CardDetect Pin
811 */
812 
813 static irqreturn_t s3cmci_irq_cd(int irq, void *dev_id)
814 {
815         struct s3cmci_host *host = (struct s3cmci_host *)dev_id;
816 
817         dbg(host, dbg_irq, "card detect\n");
818 
819         mmc_detect_change(host->mmc, msecs_to_jiffies(500));
820 
821         return IRQ_HANDLED;
822 }
823 
824 static void s3cmci_dma_done_callback(void *arg)
825 {
826         struct s3cmci_host *host = arg;
827         unsigned long iflags;
828 
829         BUG_ON(!host->mrq);
830         BUG_ON(!host->mrq->data);
831 
832         spin_lock_irqsave(&host->complete_lock, iflags);
833 
834         dbg(host, dbg_dma, "DMA FINISHED\n");
835 
836         host->dma_complete = 1;
837         host->complete_what = COMPLETION_FINALIZE;
838 
839         tasklet_schedule(&host->pio_tasklet);
840         spin_unlock_irqrestore(&host->complete_lock, iflags);
841 
842 }
843 
844 static void finalize_request(struct s3cmci_host *host)
845 {
846         struct mmc_request *mrq = host->mrq;
847         struct mmc_command *cmd;
848         int debug_as_failure = 0;
849 
850         if (host->complete_what != COMPLETION_FINALIZE)
851                 return;
852 
853         if (!mrq)
854                 return;
855         cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
856 
857         if (cmd->data && (cmd->error == 0) &&
858             (cmd->data->error == 0)) {
859                 if (s3cmci_host_usedma(host) && (!host->dma_complete)) {
860                         dbg(host, dbg_dma, "DMA Missing (%d)!\n",
861                             host->dma_complete);
862                         return;
863                 }
864         }
865 
866         /* Read response from controller. */
867         cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0);
868         cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1);
869         cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2);
870         cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3);
871 
872         writel(host->prescaler, host->base + S3C2410_SDIPRE);
873 
874         if (cmd->error)
875                 debug_as_failure = 1;
876 
877         if (cmd->data && cmd->data->error)
878                 debug_as_failure = 1;
879 
880         dbg_dumpcmd(host, cmd, debug_as_failure);
881 
882         /* Cleanup controller */
883         writel(0, host->base + S3C2410_SDICMDARG);
884         writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
885         writel(0, host->base + S3C2410_SDICMDCON);
886         clear_imask(host);
887 
888         if (cmd->data && cmd->error)
889                 cmd->data->error = cmd->error;
890 
891         if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) {
892                 host->cmd_is_stop = 1;
893                 s3cmci_send_request(host->mmc);
894                 return;
895         }
896 
897         /* If we have no data transfer we are finished here */
898         if (!mrq->data)
899                 goto request_done;
900 
901         /* Calculate the amout of bytes transfer if there was no error */
902         if (mrq->data->error == 0) {
903                 mrq->data->bytes_xfered =
904                         (mrq->data->blocks * mrq->data->blksz);
905         } else {
906                 mrq->data->bytes_xfered = 0;
907         }
908 
909         /* If we had an error while transferring data we flush the
910          * DMA channel and the fifo to clear out any garbage. */
911         if (mrq->data->error != 0) {
912                 if (s3cmci_host_usedma(host))
913                         dmaengine_terminate_all(host->dma);
914 
915                 if (host->is2440) {
916                         /* Clear failure register and reset fifo. */
917                         writel(S3C2440_SDIFSTA_FIFORESET |
918                                S3C2440_SDIFSTA_FIFOFAIL,
919                                host->base + S3C2410_SDIFSTA);
920                 } else {
921                         u32 mci_con;
922 
923                         /* reset fifo */
924                         mci_con = readl(host->base + S3C2410_SDICON);
925                         mci_con |= S3C2410_SDICON_FIFORESET;
926 
927                         writel(mci_con, host->base + S3C2410_SDICON);
928                 }
929         }
930 
931 request_done:
932         host->complete_what = COMPLETION_NONE;
933         host->mrq = NULL;
934 
935         s3cmci_check_sdio_irq(host);
936         mmc_request_done(host->mmc, mrq);
937 }
938 
939 static void s3cmci_send_command(struct s3cmci_host *host,
940                                         struct mmc_command *cmd)
941 {
942         u32 ccon, imsk;
943 
944         imsk  = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT |
945                 S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT |
946                 S3C2410_SDIIMSK_RESPONSECRC;
947 
948         enable_imask(host, imsk);
949 
950         if (cmd->data)
951                 host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
952         else if (cmd->flags & MMC_RSP_PRESENT)
953                 host->complete_what = COMPLETION_RSPFIN;
954         else
955                 host->complete_what = COMPLETION_CMDSENT;
956 
957         writel(cmd->arg, host->base + S3C2410_SDICMDARG);
958 
959         ccon  = cmd->opcode & S3C2410_SDICMDCON_INDEX;
960         ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART;
961 
962         if (cmd->flags & MMC_RSP_PRESENT)
963                 ccon |= S3C2410_SDICMDCON_WAITRSP;
964 
965         if (cmd->flags & MMC_RSP_136)
966                 ccon |= S3C2410_SDICMDCON_LONGRSP;
967 
968         writel(ccon, host->base + S3C2410_SDICMDCON);
969 }
970 
971 static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
972 {
973         u32 dcon, imsk, stoptries = 3;
974 
975         /* write DCON register */
976 
977         if (!data) {
978                 writel(0, host->base + S3C2410_SDIDCON);
979                 return 0;
980         }
981 
982         if ((data->blksz & 3) != 0) {
983                 /* We cannot deal with unaligned blocks with more than
984                  * one block being transferred. */
985 
986                 if (data->blocks > 1) {
987                         pr_warn("%s: can't do non-word sized block transfers (blksz %d)\n",
988                                 __func__, data->blksz);
989                         return -EINVAL;
990                 }
991         }
992 
993         while (readl(host->base + S3C2410_SDIDSTA) &
994                (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) {
995 
996                 dbg(host, dbg_err,
997                     "mci_setup_data() transfer stillin progress.\n");
998 
999                 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
1000                 s3cmci_reset(host);
1001 
1002                 if ((stoptries--) == 0) {
1003                         dbg_dumpregs(host, "DRF");
1004                         return -EINVAL;
1005                 }
1006         }
1007 
1008         dcon  = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK;
1009 
1010         if (s3cmci_host_usedma(host))
1011                 dcon |= S3C2410_SDIDCON_DMAEN;
1012 
1013         if (host->bus_width == MMC_BUS_WIDTH_4)
1014                 dcon |= S3C2410_SDIDCON_WIDEBUS;
1015 
1016         dcon |= S3C2410_SDIDCON_BLOCKMODE;
1017 
1018         if (data->flags & MMC_DATA_WRITE) {
1019                 dcon |= S3C2410_SDIDCON_TXAFTERRESP;
1020                 dcon |= S3C2410_SDIDCON_XFER_TXSTART;
1021         }
1022 
1023         if (data->flags & MMC_DATA_READ) {
1024                 dcon |= S3C2410_SDIDCON_RXAFTERCMD;
1025                 dcon |= S3C2410_SDIDCON_XFER_RXSTART;
1026         }
1027 
1028         if (host->is2440) {
1029                 dcon |= S3C2440_SDIDCON_DS_WORD;
1030                 dcon |= S3C2440_SDIDCON_DATSTART;
1031         }
1032 
1033         writel(dcon, host->base + S3C2410_SDIDCON);
1034 
1035         /* write BSIZE register */
1036 
1037         writel(data->blksz, host->base + S3C2410_SDIBSIZE);
1038 
1039         /* add to IMASK register */
1040         imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
1041                S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
1042 
1043         enable_imask(host, imsk);
1044 
1045         /* write TIMER register */
1046 
1047         if (host->is2440) {
1048                 writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
1049         } else {
1050                 writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
1051 
1052                 /* FIX: set slow clock to prevent timeouts on read */
1053                 if (data->flags & MMC_DATA_READ)
1054                         writel(0xFF, host->base + S3C2410_SDIPRE);
1055         }
1056 
1057         return 0;
1058 }
1059 
1060 #define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
1061 
1062 static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
1063 {
1064         int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
1065 
1066         BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1067 
1068         host->pio_sgptr = 0;
1069         host->pio_bytes = 0;
1070         host->pio_count = 0;
1071         host->pio_active = rw ? XFER_WRITE : XFER_READ;
1072 
1073         if (rw) {
1074                 do_pio_write(host);
1075                 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
1076         } else {
1077                 enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF
1078                              | S3C2410_SDIIMSK_RXFIFOLAST);
1079         }
1080 
1081         return 0;
1082 }
1083 
1084 static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
1085 {
1086         int rw = data->flags & MMC_DATA_WRITE;
1087         struct dma_async_tx_descriptor *desc;
1088         struct dma_slave_config conf = {
1089                 .src_addr = host->mem->start + host->sdidata,
1090                 .dst_addr = host->mem->start + host->sdidata,
1091                 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1092                 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1093         };
1094 
1095         BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1096 
1097         /* Restore prescaler value */
1098         writel(host->prescaler, host->base + S3C2410_SDIPRE);
1099 
1100         if (!rw)
1101                 conf.direction = DMA_DEV_TO_MEM;
1102         else
1103                 conf.direction = DMA_MEM_TO_DEV;
1104 
1105         dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1106                              rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1107 
1108         dmaengine_slave_config(host->dma, &conf);
1109         desc = dmaengine_prep_slave_sg(host->dma, data->sg, data->sg_len,
1110                 conf.direction,
1111                 DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
1112         if (!desc)
1113                 goto unmap_exit;
1114         desc->callback = s3cmci_dma_done_callback;
1115         desc->callback_param = host;
1116         dmaengine_submit(desc);
1117         dma_async_issue_pending(host->dma);
1118 
1119         return 0;
1120 
1121 unmap_exit:
1122         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1123                              rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1124         return -ENOMEM;
1125 }
1126 
1127 static void s3cmci_send_request(struct mmc_host *mmc)
1128 {
1129         struct s3cmci_host *host = mmc_priv(mmc);
1130         struct mmc_request *mrq = host->mrq;
1131         struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
1132 
1133         host->ccnt++;
1134         prepare_dbgmsg(host, cmd, host->cmd_is_stop);
1135 
1136         /* Clear command, data and fifo status registers
1137            Fifo clear only necessary on 2440, but doesn't hurt on 2410
1138         */
1139         writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT);
1140         writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA);
1141         writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA);
1142 
1143         if (cmd->data) {
1144                 int res = s3cmci_setup_data(host, cmd->data);
1145 
1146                 host->dcnt++;
1147 
1148                 if (res) {
1149                         dbg(host, dbg_err, "setup data error %d\n", res);
1150                         cmd->error = res;
1151                         cmd->data->error = res;
1152 
1153                         mmc_request_done(mmc, mrq);
1154                         return;
1155                 }
1156 
1157                 if (s3cmci_host_usedma(host))
1158                         res = s3cmci_prepare_dma(host, cmd->data);
1159                 else
1160                         res = s3cmci_prepare_pio(host, cmd->data);
1161 
1162                 if (res) {
1163                         dbg(host, dbg_err, "data prepare error %d\n", res);
1164                         cmd->error = res;
1165                         cmd->data->error = res;
1166 
1167                         mmc_request_done(mmc, mrq);
1168                         return;
1169                 }
1170         }
1171 
1172         /* Send command */
1173         s3cmci_send_command(host, cmd);
1174 
1175         /* Enable Interrupt */
1176         s3cmci_enable_irq(host, true);
1177 }
1178 
1179 static int s3cmci_card_present(struct mmc_host *mmc)
1180 {
1181         struct s3cmci_host *host = mmc_priv(mmc);
1182         struct s3c24xx_mci_pdata *pdata = host->pdata;
1183         int ret;
1184 
1185         if (pdata->no_detect)
1186                 return -ENOSYS;
1187 
1188         ret = gpio_get_value(pdata->gpio_detect) ? 0 : 1;
1189         return ret ^ pdata->detect_invert;
1190 }
1191 
1192 static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1193 {
1194         struct s3cmci_host *host = mmc_priv(mmc);
1195 
1196         host->status = "mmc request";
1197         host->cmd_is_stop = 0;
1198         host->mrq = mrq;
1199 
1200         if (s3cmci_card_present(mmc) == 0) {
1201                 dbg(host, dbg_err, "%s: no medium present\n", __func__);
1202                 host->mrq->cmd->error = -ENOMEDIUM;
1203                 mmc_request_done(mmc, mrq);
1204         } else
1205                 s3cmci_send_request(mmc);
1206 }
1207 
1208 static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios)
1209 {
1210         u32 mci_psc;
1211 
1212         /* Set clock */
1213         for (mci_psc = 0; mci_psc < 255; mci_psc++) {
1214                 host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1));
1215 
1216                 if (host->real_rate <= ios->clock)
1217                         break;
1218         }
1219 
1220         if (mci_psc > 255)
1221                 mci_psc = 255;
1222 
1223         host->prescaler = mci_psc;
1224         writel(host->prescaler, host->base + S3C2410_SDIPRE);
1225 
1226         /* If requested clock is 0, real_rate will be 0, too */
1227         if (ios->clock == 0)
1228                 host->real_rate = 0;
1229 }
1230 
1231 static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1232 {
1233         struct s3cmci_host *host = mmc_priv(mmc);
1234         u32 mci_con;
1235 
1236         /* Set the power state */
1237 
1238         mci_con = readl(host->base + S3C2410_SDICON);
1239 
1240         switch (ios->power_mode) {
1241         case MMC_POWER_ON:
1242         case MMC_POWER_UP:
1243                 /* Configure GPE5...GPE10 pins in SD mode */
1244                 s3c_gpio_cfgall_range(S3C2410_GPE(5), 6, S3C_GPIO_SFN(2),
1245                                       S3C_GPIO_PULL_NONE);
1246 
1247                 if (host->pdata->set_power)
1248                         host->pdata->set_power(ios->power_mode, ios->vdd);
1249 
1250                 if (!host->is2440)
1251                         mci_con |= S3C2410_SDICON_FIFORESET;
1252 
1253                 break;
1254 
1255         case MMC_POWER_OFF:
1256         default:
1257                 gpio_direction_output(S3C2410_GPE(5), 0);
1258 
1259                 if (host->is2440)
1260                         mci_con |= S3C2440_SDICON_SDRESET;
1261 
1262                 if (host->pdata->set_power)
1263                         host->pdata->set_power(ios->power_mode, ios->vdd);
1264 
1265                 break;
1266         }
1267 
1268         s3cmci_set_clk(host, ios);
1269 
1270         /* Set CLOCK_ENABLE */
1271         if (ios->clock)
1272                 mci_con |= S3C2410_SDICON_CLOCKTYPE;
1273         else
1274                 mci_con &= ~S3C2410_SDICON_CLOCKTYPE;
1275 
1276         writel(mci_con, host->base + S3C2410_SDICON);
1277 
1278         if ((ios->power_mode == MMC_POWER_ON) ||
1279             (ios->power_mode == MMC_POWER_UP)) {
1280                 dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n",
1281                         host->real_rate/1000, ios->clock/1000);
1282         } else {
1283                 dbg(host, dbg_conf, "powered down.\n");
1284         }
1285 
1286         host->bus_width = ios->bus_width;
1287 }
1288 
1289 static void s3cmci_reset(struct s3cmci_host *host)
1290 {
1291         u32 con = readl(host->base + S3C2410_SDICON);
1292 
1293         con |= S3C2440_SDICON_SDRESET;
1294         writel(con, host->base + S3C2410_SDICON);
1295 }
1296 
1297 static int s3cmci_get_ro(struct mmc_host *mmc)
1298 {
1299         struct s3cmci_host *host = mmc_priv(mmc);
1300         struct s3c24xx_mci_pdata *pdata = host->pdata;
1301         int ret;
1302 
1303         if (pdata->no_wprotect)
1304                 return 0;
1305 
1306         ret = gpio_get_value(pdata->gpio_wprotect) ? 1 : 0;
1307         ret ^= pdata->wprotect_invert;
1308 
1309         return ret;
1310 }
1311 
1312 static void s3cmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1313 {
1314         struct s3cmci_host *host = mmc_priv(mmc);
1315         unsigned long flags;
1316         u32 con;
1317 
1318         local_irq_save(flags);
1319 
1320         con = readl(host->base + S3C2410_SDICON);
1321         host->sdio_irqen = enable;
1322 
1323         if (enable == host->sdio_irqen)
1324                 goto same_state;
1325 
1326         if (enable) {
1327                 con |= S3C2410_SDICON_SDIOIRQ;
1328                 enable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1329 
1330                 if (!host->irq_state && !host->irq_disabled) {
1331                         host->irq_state = true;
1332                         enable_irq(host->irq);
1333                 }
1334         } else {
1335                 disable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1336                 con &= ~S3C2410_SDICON_SDIOIRQ;
1337 
1338                 if (!host->irq_enabled && host->irq_state) {
1339                         disable_irq_nosync(host->irq);
1340                         host->irq_state = false;
1341                 }
1342         }
1343 
1344         writel(con, host->base + S3C2410_SDICON);
1345 
1346  same_state:
1347         local_irq_restore(flags);
1348 
1349         s3cmci_check_sdio_irq(host);
1350 }
1351 
1352 static struct mmc_host_ops s3cmci_ops = {
1353         .request        = s3cmci_request,
1354         .set_ios        = s3cmci_set_ios,
1355         .get_ro         = s3cmci_get_ro,
1356         .get_cd         = s3cmci_card_present,
1357         .enable_sdio_irq = s3cmci_enable_sdio_irq,
1358 };
1359 
1360 static struct s3c24xx_mci_pdata s3cmci_def_pdata = {
1361         /* This is currently here to avoid a number of if (host->pdata)
1362          * checks. Any zero fields to ensure reasonable defaults are picked. */
1363          .no_wprotect = 1,
1364          .no_detect = 1,
1365 };
1366 
1367 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1368 
1369 static int s3cmci_cpufreq_transition(struct notifier_block *nb,
1370                                      unsigned long val, void *data)
1371 {
1372         struct s3cmci_host *host;
1373         struct mmc_host *mmc;
1374         unsigned long newclk;
1375         unsigned long flags;
1376 
1377         host = container_of(nb, struct s3cmci_host, freq_transition);
1378         newclk = clk_get_rate(host->clk);
1379         mmc = host->mmc;
1380 
1381         if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) ||
1382             (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) {
1383                 spin_lock_irqsave(&mmc->lock, flags);
1384 
1385                 host->clk_rate = newclk;
1386 
1387                 if (mmc->ios.power_mode != MMC_POWER_OFF &&
1388                     mmc->ios.clock != 0)
1389                         s3cmci_set_clk(host, &mmc->ios);
1390 
1391                 spin_unlock_irqrestore(&mmc->lock, flags);
1392         }
1393 
1394         return 0;
1395 }
1396 
1397 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1398 {
1399         host->freq_transition.notifier_call = s3cmci_cpufreq_transition;
1400 
1401         return cpufreq_register_notifier(&host->freq_transition,
1402                                          CPUFREQ_TRANSITION_NOTIFIER);
1403 }
1404 
1405 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1406 {
1407         cpufreq_unregister_notifier(&host->freq_transition,
1408                                     CPUFREQ_TRANSITION_NOTIFIER);
1409 }
1410 
1411 #else
1412 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1413 {
1414         return 0;
1415 }
1416 
1417 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1418 {
1419 }
1420 #endif
1421 
1422 
1423 #ifdef CONFIG_DEBUG_FS
1424 
1425 static int s3cmci_state_show(struct seq_file *seq, void *v)
1426 {
1427         struct s3cmci_host *host = seq->private;
1428 
1429         seq_printf(seq, "Register base = 0x%08x\n", (u32)host->base);
1430         seq_printf(seq, "Clock rate = %ld\n", host->clk_rate);
1431         seq_printf(seq, "Prescale = %d\n", host->prescaler);
1432         seq_printf(seq, "is2440 = %d\n", host->is2440);
1433         seq_printf(seq, "IRQ = %d\n", host->irq);
1434         seq_printf(seq, "IRQ enabled = %d\n", host->irq_enabled);
1435         seq_printf(seq, "IRQ disabled = %d\n", host->irq_disabled);
1436         seq_printf(seq, "IRQ state = %d\n", host->irq_state);
1437         seq_printf(seq, "CD IRQ = %d\n", host->irq_cd);
1438         seq_printf(seq, "Do DMA = %d\n", s3cmci_host_usedma(host));
1439         seq_printf(seq, "SDIIMSK at %d\n", host->sdiimsk);
1440         seq_printf(seq, "SDIDATA at %d\n", host->sdidata);
1441 
1442         return 0;
1443 }
1444 
1445 static int s3cmci_state_open(struct inode *inode, struct file *file)
1446 {
1447         return single_open(file, s3cmci_state_show, inode->i_private);
1448 }
1449 
1450 static const struct file_operations s3cmci_fops_state = {
1451         .owner          = THIS_MODULE,
1452         .open           = s3cmci_state_open,
1453         .read           = seq_read,
1454         .llseek         = seq_lseek,
1455         .release        = single_release,
1456 };
1457 
1458 #define DBG_REG(_r) { .addr = S3C2410_SDI##_r, .name = #_r }
1459 
1460 struct s3cmci_reg {
1461         unsigned short  addr;
1462         unsigned char   *name;
1463 } debug_regs[] = {
1464         DBG_REG(CON),
1465         DBG_REG(PRE),
1466         DBG_REG(CMDARG),
1467         DBG_REG(CMDCON),
1468         DBG_REG(CMDSTAT),
1469         DBG_REG(RSP0),
1470         DBG_REG(RSP1),
1471         DBG_REG(RSP2),
1472         DBG_REG(RSP3),
1473         DBG_REG(TIMER),
1474         DBG_REG(BSIZE),
1475         DBG_REG(DCON),
1476         DBG_REG(DCNT),
1477         DBG_REG(DSTA),
1478         DBG_REG(FSTA),
1479         {}
1480 };
1481 
1482 static int s3cmci_regs_show(struct seq_file *seq, void *v)
1483 {
1484         struct s3cmci_host *host = seq->private;
1485         struct s3cmci_reg *rptr = debug_regs;
1486 
1487         for (; rptr->name; rptr++)
1488                 seq_printf(seq, "SDI%s\t=0x%08x\n", rptr->name,
1489                            readl(host->base + rptr->addr));
1490 
1491         seq_printf(seq, "SDIIMSK\t=0x%08x\n", readl(host->base + host->sdiimsk));
1492 
1493         return 0;
1494 }
1495 
1496 static int s3cmci_regs_open(struct inode *inode, struct file *file)
1497 {
1498         return single_open(file, s3cmci_regs_show, inode->i_private);
1499 }
1500 
1501 static const struct file_operations s3cmci_fops_regs = {
1502         .owner          = THIS_MODULE,
1503         .open           = s3cmci_regs_open,
1504         .read           = seq_read,
1505         .llseek         = seq_lseek,
1506         .release        = single_release,
1507 };
1508 
1509 static void s3cmci_debugfs_attach(struct s3cmci_host *host)
1510 {
1511         struct device *dev = &host->pdev->dev;
1512 
1513         host->debug_root = debugfs_create_dir(dev_name(dev), NULL);
1514         if (IS_ERR(host->debug_root)) {
1515                 dev_err(dev, "failed to create debugfs root\n");
1516                 return;
1517         }
1518 
1519         host->debug_state = debugfs_create_file("state", 0444,
1520                                                 host->debug_root, host,
1521                                                 &s3cmci_fops_state);
1522 
1523         if (IS_ERR(host->debug_state))
1524                 dev_err(dev, "failed to create debug state file\n");
1525 
1526         host->debug_regs = debugfs_create_file("regs", 0444,
1527                                                host->debug_root, host,
1528                                                &s3cmci_fops_regs);
1529 
1530         if (IS_ERR(host->debug_regs))
1531                 dev_err(dev, "failed to create debug regs file\n");
1532 }
1533 
1534 static void s3cmci_debugfs_remove(struct s3cmci_host *host)
1535 {
1536         debugfs_remove(host->debug_regs);
1537         debugfs_remove(host->debug_state);
1538         debugfs_remove(host->debug_root);
1539 }
1540 
1541 #else
1542 static inline void s3cmci_debugfs_attach(struct s3cmci_host *host) { }
1543 static inline void s3cmci_debugfs_remove(struct s3cmci_host *host) { }
1544 
1545 #endif /* CONFIG_DEBUG_FS */
1546 
1547 static int s3cmci_probe(struct platform_device *pdev)
1548 {
1549         struct s3cmci_host *host;
1550         struct mmc_host *mmc;
1551         int ret;
1552         int is2440;
1553         int i;
1554 
1555         is2440 = platform_get_device_id(pdev)->driver_data;
1556 
1557         mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
1558         if (!mmc) {
1559                 ret = -ENOMEM;
1560                 goto probe_out;
1561         }
1562 
1563         for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) {
1564                 ret = gpio_request(i, dev_name(&pdev->dev));
1565                 if (ret) {
1566                         dev_err(&pdev->dev, "failed to get gpio %d\n", i);
1567 
1568                         for (i--; i >= S3C2410_GPE(5); i--)
1569                                 gpio_free(i);
1570 
1571                         goto probe_free_host;
1572                 }
1573         }
1574 
1575         host = mmc_priv(mmc);
1576         host->mmc       = mmc;
1577         host->pdev      = pdev;
1578         host->is2440    = is2440;
1579 
1580         host->pdata = pdev->dev.platform_data;
1581         if (!host->pdata) {
1582                 pdev->dev.platform_data = &s3cmci_def_pdata;
1583                 host->pdata = &s3cmci_def_pdata;
1584         }
1585 
1586         spin_lock_init(&host->complete_lock);
1587         tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
1588 
1589         if (is2440) {
1590                 host->sdiimsk   = S3C2440_SDIIMSK;
1591                 host->sdidata   = S3C2440_SDIDATA;
1592                 host->clk_div   = 1;
1593         } else {
1594                 host->sdiimsk   = S3C2410_SDIIMSK;
1595                 host->sdidata   = S3C2410_SDIDATA;
1596                 host->clk_div   = 2;
1597         }
1598 
1599         host->complete_what     = COMPLETION_NONE;
1600         host->pio_active        = XFER_NONE;
1601 
1602         host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1603         if (!host->mem) {
1604                 dev_err(&pdev->dev,
1605                         "failed to get io memory region resource.\n");
1606 
1607                 ret = -ENOENT;
1608                 goto probe_free_gpio;
1609         }
1610 
1611         host->mem = request_mem_region(host->mem->start,
1612                                        resource_size(host->mem), pdev->name);
1613 
1614         if (!host->mem) {
1615                 dev_err(&pdev->dev, "failed to request io memory region.\n");
1616                 ret = -ENOENT;
1617                 goto probe_free_gpio;
1618         }
1619 
1620         host->base = ioremap(host->mem->start, resource_size(host->mem));
1621         if (!host->base) {
1622                 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
1623                 ret = -EINVAL;
1624                 goto probe_free_mem_region;
1625         }
1626 
1627         host->irq = platform_get_irq(pdev, 0);
1628         if (host->irq == 0) {
1629                 dev_err(&pdev->dev, "failed to get interrupt resource.\n");
1630                 ret = -EINVAL;
1631                 goto probe_iounmap;
1632         }
1633 
1634         if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) {
1635                 dev_err(&pdev->dev, "failed to request mci interrupt.\n");
1636                 ret = -ENOENT;
1637                 goto probe_iounmap;
1638         }
1639 
1640         /* We get spurious interrupts even when we have set the IMSK
1641          * register to ignore everything, so use disable_irq() to make
1642          * ensure we don't lock the system with un-serviceable requests. */
1643 
1644         disable_irq(host->irq);
1645         host->irq_state = false;
1646 
1647         if (!host->pdata->no_detect) {
1648                 ret = gpio_request(host->pdata->gpio_detect, "s3cmci detect");
1649                 if (ret) {
1650                         dev_err(&pdev->dev, "failed to get detect gpio\n");
1651                         goto probe_free_irq;
1652                 }
1653 
1654                 host->irq_cd = gpio_to_irq(host->pdata->gpio_detect);
1655 
1656                 if (host->irq_cd >= 0) {
1657                         if (request_irq(host->irq_cd, s3cmci_irq_cd,
1658                                         IRQF_TRIGGER_RISING |
1659                                         IRQF_TRIGGER_FALLING,
1660                                         DRIVER_NAME, host)) {
1661                                 dev_err(&pdev->dev,
1662                                         "can't get card detect irq.\n");
1663                                 ret = -ENOENT;
1664                                 goto probe_free_gpio_cd;
1665                         }
1666                 } else {
1667                         dev_warn(&pdev->dev,
1668                                  "host detect has no irq available\n");
1669                         gpio_direction_input(host->pdata->gpio_detect);
1670                 }
1671         } else
1672                 host->irq_cd = -1;
1673 
1674         if (!host->pdata->no_wprotect) {
1675                 ret = gpio_request(host->pdata->gpio_wprotect, "s3cmci wp");
1676                 if (ret) {
1677                         dev_err(&pdev->dev, "failed to get writeprotect\n");
1678                         goto probe_free_irq_cd;
1679                 }
1680 
1681                 gpio_direction_input(host->pdata->gpio_wprotect);
1682         }
1683 
1684         /* Depending on the dma state, get a DMA channel to use. */
1685 
1686         if (s3cmci_host_usedma(host)) {
1687                 host->dma = dma_request_chan(&pdev->dev, "rx-tx");
1688                 ret = PTR_ERR_OR_ZERO(host->dma);
1689                 if (ret) {
1690                         dev_err(&pdev->dev, "cannot get DMA channel.\n");
1691                         goto probe_free_gpio_wp;
1692                 }
1693         }
1694 
1695         host->clk = clk_get(&pdev->dev, "sdi");
1696         if (IS_ERR(host->clk)) {
1697                 dev_err(&pdev->dev, "failed to find clock source.\n");
1698                 ret = PTR_ERR(host->clk);
1699                 host->clk = NULL;
1700                 goto probe_free_dma;
1701         }
1702 
1703         ret = clk_prepare_enable(host->clk);
1704         if (ret) {
1705                 dev_err(&pdev->dev, "failed to enable clock source.\n");
1706                 goto clk_free;
1707         }
1708 
1709         host->clk_rate = clk_get_rate(host->clk);
1710 
1711         mmc->ops        = &s3cmci_ops;
1712         mmc->ocr_avail  = MMC_VDD_32_33 | MMC_VDD_33_34;
1713 #ifdef CONFIG_MMC_S3C_HW_SDIO_IRQ
1714         mmc->caps       = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1715 #else
1716         mmc->caps       = MMC_CAP_4_BIT_DATA;
1717 #endif
1718         mmc->f_min      = host->clk_rate / (host->clk_div * 256);
1719         mmc->f_max      = host->clk_rate / host->clk_div;
1720 
1721         if (host->pdata->ocr_avail)
1722                 mmc->ocr_avail = host->pdata->ocr_avail;
1723 
1724         mmc->max_blk_count      = 4095;
1725         mmc->max_blk_size       = 4095;
1726         mmc->max_req_size       = 4095 * 512;
1727         mmc->max_seg_size       = mmc->max_req_size;
1728 
1729         mmc->max_segs           = 128;
1730 
1731         dbg(host, dbg_debug,
1732             "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%p.\n",
1733             (host->is2440?"2440":""),
1734             host->base, host->irq, host->irq_cd, host->dma);
1735 
1736         ret = s3cmci_cpufreq_register(host);
1737         if (ret) {
1738                 dev_err(&pdev->dev, "failed to register cpufreq\n");
1739                 goto free_dmabuf;
1740         }
1741 
1742         ret = mmc_add_host(mmc);
1743         if (ret) {
1744                 dev_err(&pdev->dev, "failed to add mmc host.\n");
1745                 goto free_cpufreq;
1746         }
1747 
1748         s3cmci_debugfs_attach(host);
1749 
1750         platform_set_drvdata(pdev, mmc);
1751         dev_info(&pdev->dev, "%s - using %s, %s SDIO IRQ\n", mmc_hostname(mmc),
1752                  s3cmci_host_usedma(host) ? "dma" : "pio",
1753                  mmc->caps & MMC_CAP_SDIO_IRQ ? "hw" : "sw");
1754 
1755         return 0;
1756 
1757  free_cpufreq:
1758         s3cmci_cpufreq_deregister(host);
1759 
1760  free_dmabuf:
1761         clk_disable_unprepare(host->clk);
1762 
1763  clk_free:
1764         clk_put(host->clk);
1765 
1766  probe_free_dma:
1767         if (s3cmci_host_usedma(host))
1768                 dma_release_channel(host->dma);
1769 
1770  probe_free_gpio_wp:
1771         if (!host->pdata->no_wprotect)
1772                 gpio_free(host->pdata->gpio_wprotect);
1773 
1774  probe_free_gpio_cd:
1775         if (!host->pdata->no_detect)
1776                 gpio_free(host->pdata->gpio_detect);
1777 
1778  probe_free_irq_cd:
1779         if (host->irq_cd >= 0)
1780                 free_irq(host->irq_cd, host);
1781 
1782  probe_free_irq:
1783         free_irq(host->irq, host);
1784 
1785  probe_iounmap:
1786         iounmap(host->base);
1787 
1788  probe_free_mem_region:
1789         release_mem_region(host->mem->start, resource_size(host->mem));
1790 
1791  probe_free_gpio:
1792         for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1793                 gpio_free(i);
1794 
1795  probe_free_host:
1796         mmc_free_host(mmc);
1797 
1798  probe_out:
1799         return ret;
1800 }
1801 
1802 static void s3cmci_shutdown(struct platform_device *pdev)
1803 {
1804         struct mmc_host *mmc = platform_get_drvdata(pdev);
1805         struct s3cmci_host *host = mmc_priv(mmc);
1806 
1807         if (host->irq_cd >= 0)
1808                 free_irq(host->irq_cd, host);
1809 
1810         s3cmci_debugfs_remove(host);
1811         s3cmci_cpufreq_deregister(host);
1812         mmc_remove_host(mmc);
1813         clk_disable_unprepare(host->clk);
1814 }
1815 
1816 static int s3cmci_remove(struct platform_device *pdev)
1817 {
1818         struct mmc_host         *mmc  = platform_get_drvdata(pdev);
1819         struct s3cmci_host      *host = mmc_priv(mmc);
1820         struct s3c24xx_mci_pdata *pd = host->pdata;
1821         int i;
1822 
1823         s3cmci_shutdown(pdev);
1824 
1825         clk_put(host->clk);
1826 
1827         tasklet_disable(&host->pio_tasklet);
1828 
1829         if (s3cmci_host_usedma(host))
1830                 dma_release_channel(host->dma);
1831 
1832         free_irq(host->irq, host);
1833 
1834         if (!pd->no_wprotect)
1835                 gpio_free(pd->gpio_wprotect);
1836 
1837         if (!pd->no_detect)
1838                 gpio_free(pd->gpio_detect);
1839 
1840         for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1841                 gpio_free(i);
1842 
1843 
1844         iounmap(host->base);
1845         release_mem_region(host->mem->start, resource_size(host->mem));
1846 
1847         mmc_free_host(mmc);
1848         return 0;
1849 }
1850 
1851 static const struct platform_device_id s3cmci_driver_ids[] = {
1852         {
1853                 .name   = "s3c2410-sdi",
1854                 .driver_data    = 0,
1855         }, {
1856                 .name   = "s3c2412-sdi",
1857                 .driver_data    = 1,
1858         }, {
1859                 .name   = "s3c2440-sdi",
1860                 .driver_data    = 1,
1861         },
1862         { }
1863 };
1864 
1865 MODULE_DEVICE_TABLE(platform, s3cmci_driver_ids);
1866 
1867 static struct platform_driver s3cmci_driver = {
1868         .driver = {
1869                 .name   = "s3c-sdi",
1870         },
1871         .id_table       = s3cmci_driver_ids,
1872         .probe          = s3cmci_probe,
1873         .remove         = s3cmci_remove,
1874         .shutdown       = s3cmci_shutdown,
1875 };
1876 
1877 module_platform_driver(s3cmci_driver);
1878 
1879 MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
1880 MODULE_LICENSE("GPL v2");
1881 MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>");
1882 

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