Version:  2.0.40 2.2.26 2.4.37 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10

Linux/drivers/mmc/host/rtsx_pci_sdmmc.c

  1 /* Realtek PCI-Express SD/MMC Card Interface driver
  2  *
  3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
  4  *
  5  * This program is free software; you can redistribute it and/or modify it
  6  * under the terms of the GNU General Public License as published by the
  7  * Free Software Foundation; either version 2, or (at your option) any
  8  * later version.
  9  *
 10  * This program is distributed in the hope that it will be useful, but
 11  * WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 13  * General Public License for more details.
 14  *
 15  * You should have received a copy of the GNU General Public License along
 16  * with this program; if not, see <http://www.gnu.org/licenses/>.
 17  *
 18  * Author:
 19  *   Wei WANG <wei_wang@realsil.com.cn>
 20  */
 21 
 22 #include <linux/module.h>
 23 #include <linux/slab.h>
 24 #include <linux/highmem.h>
 25 #include <linux/delay.h>
 26 #include <linux/platform_device.h>
 27 #include <linux/workqueue.h>
 28 #include <linux/mmc/host.h>
 29 #include <linux/mmc/mmc.h>
 30 #include <linux/mmc/sd.h>
 31 #include <linux/mmc/sdio.h>
 32 #include <linux/mmc/card.h>
 33 #include <linux/mfd/rtsx_pci.h>
 34 #include <asm/unaligned.h>
 35 
 36 struct realtek_pci_sdmmc {
 37         struct platform_device  *pdev;
 38         struct rtsx_pcr         *pcr;
 39         struct mmc_host         *mmc;
 40         struct mmc_request      *mrq;
 41 #define SDMMC_WORKQ_NAME        "rtsx_pci_sdmmc_workq"
 42 
 43         struct work_struct      work;
 44         struct mutex            host_mutex;
 45 
 46         u8                      ssc_depth;
 47         unsigned int            clock;
 48         bool                    vpclk;
 49         bool                    double_clk;
 50         bool                    eject;
 51         bool                    initial_mode;
 52         int                     power_state;
 53 #define SDMMC_POWER_ON          1
 54 #define SDMMC_POWER_OFF         0
 55 
 56         int                     sg_count;
 57         s32                     cookie;
 58         int                     cookie_sg_count;
 59         bool                    using_cookie;
 60 };
 61 
 62 static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
 63 {
 64         return &(host->pdev->dev);
 65 }
 66 
 67 static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
 68 {
 69         rtsx_pci_write_register(host->pcr, CARD_STOP,
 70                         SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
 71 }
 72 
 73 #ifdef DEBUG
 74 static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end)
 75 {
 76         u16 len = end - start + 1;
 77         int i;
 78         u8 data[8];
 79 
 80         for (i = 0; i < len; i += 8) {
 81                 int j;
 82                 int n = min(8, len - i);
 83 
 84                 memset(&data, 0, sizeof(data));
 85                 for (j = 0; j < n; j++)
 86                         rtsx_pci_read_register(host->pcr, start + i + j,
 87                                 data + j);
 88                 dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n",
 89                         start + i, n, data);
 90         }
 91 }
 92 
 93 static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
 94 {
 95         dump_reg_range(host, 0xFDA0, 0xFDB3);
 96         dump_reg_range(host, 0xFD52, 0xFD69);
 97 }
 98 #else
 99 #define sd_print_debug_regs(host)
100 #endif /* DEBUG */
101 
102 static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host)
103 {
104         return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST;
105 }
106 
107 static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd)
108 {
109         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF,
110                 SD_CMD_START | cmd->opcode);
111         rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg);
112 }
113 
114 static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz)
115 {
116         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks);
117         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8);
118         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz);
119         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8);
120 }
121 
122 static int sd_response_type(struct mmc_command *cmd)
123 {
124         switch (mmc_resp_type(cmd)) {
125         case MMC_RSP_NONE:
126                 return SD_RSP_TYPE_R0;
127         case MMC_RSP_R1:
128                 return SD_RSP_TYPE_R1;
129         case MMC_RSP_R1_NO_CRC:
130                 return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
131         case MMC_RSP_R1B:
132                 return SD_RSP_TYPE_R1b;
133         case MMC_RSP_R2:
134                 return SD_RSP_TYPE_R2;
135         case MMC_RSP_R3:
136                 return SD_RSP_TYPE_R3;
137         default:
138                 return -EINVAL;
139         }
140 }
141 
142 static int sd_status_index(int resp_type)
143 {
144         if (resp_type == SD_RSP_TYPE_R0)
145                 return 0;
146         else if (resp_type == SD_RSP_TYPE_R2)
147                 return 16;
148 
149         return 5;
150 }
151 /*
152  * sd_pre_dma_transfer - do dma_map_sg() or using cookie
153  *
154  * @pre: if called in pre_req()
155  * return:
156  *      0 - do dma_map_sg()
157  *      1 - using cookie
158  */
159 static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host,
160                 struct mmc_data *data, bool pre)
161 {
162         struct rtsx_pcr *pcr = host->pcr;
163         int read = data->flags & MMC_DATA_READ;
164         int count = 0;
165         int using_cookie = 0;
166 
167         if (!pre && data->host_cookie && data->host_cookie != host->cookie) {
168                 dev_err(sdmmc_dev(host),
169                         "error: data->host_cookie = %d, host->cookie = %d\n",
170                         data->host_cookie, host->cookie);
171                 data->host_cookie = 0;
172         }
173 
174         if (pre || data->host_cookie != host->cookie) {
175                 count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read);
176         } else {
177                 count = host->cookie_sg_count;
178                 using_cookie = 1;
179         }
180 
181         if (pre) {
182                 host->cookie_sg_count = count;
183                 if (++host->cookie < 0)
184                         host->cookie = 1;
185                 data->host_cookie = host->cookie;
186         } else {
187                 host->sg_count = count;
188         }
189 
190         return using_cookie;
191 }
192 
193 static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
194 {
195         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
196         struct mmc_data *data = mrq->data;
197 
198         if (data->host_cookie) {
199                 dev_err(sdmmc_dev(host),
200                         "error: reset data->host_cookie = %d\n",
201                         data->host_cookie);
202                 data->host_cookie = 0;
203         }
204 
205         sd_pre_dma_transfer(host, data, true);
206         dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count);
207 }
208 
209 static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
210                 int err)
211 {
212         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
213         struct rtsx_pcr *pcr = host->pcr;
214         struct mmc_data *data = mrq->data;
215         int read = data->flags & MMC_DATA_READ;
216 
217         rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read);
218         data->host_cookie = 0;
219 }
220 
221 static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
222                 struct mmc_command *cmd)
223 {
224         struct rtsx_pcr *pcr = host->pcr;
225         u8 cmd_idx = (u8)cmd->opcode;
226         u32 arg = cmd->arg;
227         int err = 0;
228         int timeout = 100;
229         int i;
230         u8 *ptr;
231         int rsp_type;
232         int stat_idx;
233         bool clock_toggled = false;
234 
235         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
236                         __func__, cmd_idx, arg);
237 
238         rsp_type = sd_response_type(cmd);
239         if (rsp_type < 0)
240                 goto out;
241 
242         stat_idx = sd_status_index(rsp_type);
243 
244         if (rsp_type == SD_RSP_TYPE_R1b)
245                 timeout = cmd->busy_timeout ? cmd->busy_timeout : 3000;
246 
247         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
248                 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
249                                 0xFF, SD_CLK_TOGGLE_EN);
250                 if (err < 0)
251                         goto out;
252 
253                 clock_toggled = true;
254         }
255 
256         rtsx_pci_init_cmd(pcr);
257         sd_cmd_set_sd_cmd(pcr, cmd);
258         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
259         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
260                         0x01, PINGPONG_BUFFER);
261         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
262                         0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
263         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
264                      SD_TRANSFER_END | SD_STAT_IDLE,
265                      SD_TRANSFER_END | SD_STAT_IDLE);
266 
267         if (rsp_type == SD_RSP_TYPE_R2) {
268                 /* Read data from ping-pong buffer */
269                 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
270                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
271         } else if (rsp_type != SD_RSP_TYPE_R0) {
272                 /* Read data from SD_CMDx registers */
273                 for (i = SD_CMD0; i <= SD_CMD4; i++)
274                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
275         }
276 
277         rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
278 
279         err = rtsx_pci_send_cmd(pcr, timeout);
280         if (err < 0) {
281                 sd_print_debug_regs(host);
282                 sd_clear_error(host);
283                 dev_dbg(sdmmc_dev(host),
284                         "rtsx_pci_send_cmd error (err = %d)\n", err);
285                 goto out;
286         }
287 
288         if (rsp_type == SD_RSP_TYPE_R0) {
289                 err = 0;
290                 goto out;
291         }
292 
293         /* Eliminate returned value of CHECK_REG_CMD */
294         ptr = rtsx_pci_get_cmd_data(pcr) + 1;
295 
296         /* Check (Start,Transmission) bit of Response */
297         if ((ptr[0] & 0xC0) != 0) {
298                 err = -EILSEQ;
299                 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
300                 goto out;
301         }
302 
303         /* Check CRC7 */
304         if (!(rsp_type & SD_NO_CHECK_CRC7)) {
305                 if (ptr[stat_idx] & SD_CRC7_ERR) {
306                         err = -EILSEQ;
307                         dev_dbg(sdmmc_dev(host), "CRC7 error\n");
308                         goto out;
309                 }
310         }
311 
312         if (rsp_type == SD_RSP_TYPE_R2) {
313                 /*
314                  * The controller offloads the last byte {CRC-7, end bit 1'b1}
315                  * of response type R2. Assign dummy CRC, 0, and end bit to the
316                  * byte(ptr[16], goes into the LSB of resp[3] later).
317                  */
318                 ptr[16] = 1;
319 
320                 for (i = 0; i < 4; i++) {
321                         cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
322                         dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
323                                         i, cmd->resp[i]);
324                 }
325         } else {
326                 cmd->resp[0] = get_unaligned_be32(ptr + 1);
327                 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
328                                 cmd->resp[0]);
329         }
330 
331 out:
332         cmd->error = err;
333 
334         if (err && clock_toggled)
335                 rtsx_pci_write_register(pcr, SD_BUS_STAT,
336                                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
337 }
338 
339 static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd,
340         u16 byte_cnt, u8 *buf, int buf_len, int timeout)
341 {
342         struct rtsx_pcr *pcr = host->pcr;
343         int err;
344         u8 trans_mode;
345 
346         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
347                 __func__, cmd->opcode, cmd->arg);
348 
349         if (!buf)
350                 buf_len = 0;
351 
352         if (cmd->opcode == MMC_SEND_TUNING_BLOCK)
353                 trans_mode = SD_TM_AUTO_TUNING;
354         else
355                 trans_mode = SD_TM_NORMAL_READ;
356 
357         rtsx_pci_init_cmd(pcr);
358         sd_cmd_set_sd_cmd(pcr, cmd);
359         sd_cmd_set_data_len(pcr, 1, byte_cnt);
360         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
361                         SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
362                         SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
363         if (trans_mode != SD_TM_AUTO_TUNING)
364                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
365                                 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
366 
367         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
368                         0xFF, trans_mode | SD_TRANSFER_START);
369         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
370                         SD_TRANSFER_END, SD_TRANSFER_END);
371 
372         err = rtsx_pci_send_cmd(pcr, timeout);
373         if (err < 0) {
374                 sd_print_debug_regs(host);
375                 dev_dbg(sdmmc_dev(host),
376                         "rtsx_pci_send_cmd fail (err = %d)\n", err);
377                 return err;
378         }
379 
380         if (buf && buf_len) {
381                 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
382                 if (err < 0) {
383                         dev_dbg(sdmmc_dev(host),
384                                 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
385                         return err;
386                 }
387         }
388 
389         return 0;
390 }
391 
392 static int sd_write_data(struct realtek_pci_sdmmc *host,
393         struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len,
394         int timeout)
395 {
396         struct rtsx_pcr *pcr = host->pcr;
397         int err;
398 
399         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
400                 __func__, cmd->opcode, cmd->arg);
401 
402         if (!buf)
403                 buf_len = 0;
404 
405         sd_send_cmd_get_rsp(host, cmd);
406         if (cmd->error)
407                 return cmd->error;
408 
409         if (buf && buf_len) {
410                 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
411                 if (err < 0) {
412                         dev_dbg(sdmmc_dev(host),
413                                 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
414                         return err;
415                 }
416         }
417 
418         rtsx_pci_init_cmd(pcr);
419         sd_cmd_set_data_len(pcr, 1, byte_cnt);
420         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
421                 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
422                 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0);
423         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
424                         SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
425         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
426                         SD_TRANSFER_END, SD_TRANSFER_END);
427 
428         err = rtsx_pci_send_cmd(pcr, timeout);
429         if (err < 0) {
430                 sd_print_debug_regs(host);
431                 dev_dbg(sdmmc_dev(host),
432                         "rtsx_pci_send_cmd fail (err = %d)\n", err);
433                 return err;
434         }
435 
436         return 0;
437 }
438 
439 static int sd_read_long_data(struct realtek_pci_sdmmc *host,
440         struct mmc_request *mrq)
441 {
442         struct rtsx_pcr *pcr = host->pcr;
443         struct mmc_host *mmc = host->mmc;
444         struct mmc_card *card = mmc->card;
445         struct mmc_command *cmd = mrq->cmd;
446         struct mmc_data *data = mrq->data;
447         int uhs = mmc_card_uhs(card);
448         u8 cfg2 = 0;
449         int err;
450         int resp_type;
451         size_t data_len = data->blksz * data->blocks;
452 
453         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
454                 __func__, cmd->opcode, cmd->arg);
455 
456         resp_type = sd_response_type(cmd);
457         if (resp_type < 0)
458                 return resp_type;
459 
460         if (!uhs)
461                 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
462 
463         rtsx_pci_init_cmd(pcr);
464         sd_cmd_set_sd_cmd(pcr, cmd);
465         sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
466         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
467                         DMA_DONE_INT, DMA_DONE_INT);
468         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
469                 0xFF, (u8)(data_len >> 24));
470         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
471                 0xFF, (u8)(data_len >> 16));
472         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
473                 0xFF, (u8)(data_len >> 8));
474         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
475         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
476                 0x03 | DMA_PACK_SIZE_MASK,
477                 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
478         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
479                         0x01, RING_BUFFER);
480         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type);
481         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
482                         SD_TRANSFER_START | SD_TM_AUTO_READ_2);
483         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
484                         SD_TRANSFER_END, SD_TRANSFER_END);
485         rtsx_pci_send_cmd_no_wait(pcr);
486 
487         err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000);
488         if (err < 0) {
489                 sd_print_debug_regs(host);
490                 sd_clear_error(host);
491                 return err;
492         }
493 
494         return 0;
495 }
496 
497 static int sd_write_long_data(struct realtek_pci_sdmmc *host,
498         struct mmc_request *mrq)
499 {
500         struct rtsx_pcr *pcr = host->pcr;
501         struct mmc_host *mmc = host->mmc;
502         struct mmc_card *card = mmc->card;
503         struct mmc_command *cmd = mrq->cmd;
504         struct mmc_data *data = mrq->data;
505         int uhs = mmc_card_uhs(card);
506         u8 cfg2;
507         int err;
508         size_t data_len = data->blksz * data->blocks;
509 
510         sd_send_cmd_get_rsp(host, cmd);
511         if (cmd->error)
512                 return cmd->error;
513 
514         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
515                 __func__, cmd->opcode, cmd->arg);
516 
517         cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
518                 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
519 
520         if (!uhs)
521                 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
522 
523         rtsx_pci_init_cmd(pcr);
524         sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
525         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
526                         DMA_DONE_INT, DMA_DONE_INT);
527         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
528                 0xFF, (u8)(data_len >> 24));
529         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
530                 0xFF, (u8)(data_len >> 16));
531         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
532                 0xFF, (u8)(data_len >> 8));
533         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
534         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
535                 0x03 | DMA_PACK_SIZE_MASK,
536                 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
537         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
538                         0x01, RING_BUFFER);
539         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
540         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
541                         SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
542         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
543                         SD_TRANSFER_END, SD_TRANSFER_END);
544         rtsx_pci_send_cmd_no_wait(pcr);
545         err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000);
546         if (err < 0) {
547                 sd_clear_error(host);
548                 return err;
549         }
550 
551         return 0;
552 }
553 
554 static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
555 {
556         struct mmc_data *data = mrq->data;
557 
558         if (host->sg_count < 0) {
559                 data->error = host->sg_count;
560                 dev_dbg(sdmmc_dev(host), "%s: sg_count = %d is invalid\n",
561                         __func__, host->sg_count);
562                 return data->error;
563         }
564 
565         if (data->flags & MMC_DATA_READ)
566                 return sd_read_long_data(host, mrq);
567 
568         return sd_write_long_data(host, mrq);
569 }
570 
571 static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
572 {
573         rtsx_pci_write_register(host->pcr, SD_CFG1,
574                         SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
575 }
576 
577 static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
578 {
579         rtsx_pci_write_register(host->pcr, SD_CFG1,
580                         SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
581 }
582 
583 static void sd_normal_rw(struct realtek_pci_sdmmc *host,
584                 struct mmc_request *mrq)
585 {
586         struct mmc_command *cmd = mrq->cmd;
587         struct mmc_data *data = mrq->data;
588         u8 *buf;
589 
590         buf = kzalloc(data->blksz, GFP_NOIO);
591         if (!buf) {
592                 cmd->error = -ENOMEM;
593                 return;
594         }
595 
596         if (data->flags & MMC_DATA_READ) {
597                 if (host->initial_mode)
598                         sd_disable_initial_mode(host);
599 
600                 cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf,
601                                 data->blksz, 200);
602 
603                 if (host->initial_mode)
604                         sd_enable_initial_mode(host);
605 
606                 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
607         } else {
608                 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
609 
610                 cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf,
611                                 data->blksz, 200);
612         }
613 
614         kfree(buf);
615 }
616 
617 static int sd_change_phase(struct realtek_pci_sdmmc *host,
618                 u8 sample_point, bool rx)
619 {
620         struct rtsx_pcr *pcr = host->pcr;
621         int err;
622 
623         dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
624                         __func__, rx ? "RX" : "TX", sample_point);
625 
626         rtsx_pci_init_cmd(pcr);
627 
628         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
629         if (rx)
630                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
631                                 SD_VPRX_CTL, 0x1F, sample_point);
632         else
633                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
634                                 SD_VPTX_CTL, 0x1F, sample_point);
635         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
636         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
637                         PHASE_NOT_RESET, PHASE_NOT_RESET);
638         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0);
639         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
640 
641         err = rtsx_pci_send_cmd(pcr, 100);
642         if (err < 0)
643                 return err;
644 
645         return 0;
646 }
647 
648 static inline u32 test_phase_bit(u32 phase_map, unsigned int bit)
649 {
650         bit %= RTSX_PHASE_MAX;
651         return phase_map & (1 << bit);
652 }
653 
654 static int sd_get_phase_len(u32 phase_map, unsigned int start_bit)
655 {
656         int i;
657 
658         for (i = 0; i < RTSX_PHASE_MAX; i++) {
659                 if (test_phase_bit(phase_map, start_bit + i) == 0)
660                         return i;
661         }
662         return RTSX_PHASE_MAX;
663 }
664 
665 static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
666 {
667         int start = 0, len = 0;
668         int start_final = 0, len_final = 0;
669         u8 final_phase = 0xFF;
670 
671         if (phase_map == 0) {
672                 dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map);
673                 return final_phase;
674         }
675 
676         while (start < RTSX_PHASE_MAX) {
677                 len = sd_get_phase_len(phase_map, start);
678                 if (len_final < len) {
679                         start_final = start;
680                         len_final = len;
681                 }
682                 start += len ? len : 1;
683         }
684 
685         final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX;
686         dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n",
687                 phase_map, len_final, final_phase);
688 
689         return final_phase;
690 }
691 
692 static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
693 {
694         int err, i;
695         u8 val = 0;
696 
697         for (i = 0; i < 100; i++) {
698                 err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
699                 if (val & SD_DATA_IDLE)
700                         return;
701 
702                 udelay(100);
703         }
704 }
705 
706 static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
707                 u8 opcode, u8 sample_point)
708 {
709         int err;
710         struct mmc_command cmd = {0};
711 
712         err = sd_change_phase(host, sample_point, true);
713         if (err < 0)
714                 return err;
715 
716         cmd.opcode = opcode;
717         err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100);
718         if (err < 0) {
719                 /* Wait till SD DATA IDLE */
720                 sd_wait_data_idle(host);
721                 sd_clear_error(host);
722                 return err;
723         }
724 
725         return 0;
726 }
727 
728 static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
729                 u8 opcode, u32 *phase_map)
730 {
731         int err, i;
732         u32 raw_phase_map = 0;
733 
734         for (i = 0; i < RTSX_PHASE_MAX; i++) {
735                 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
736                 if (err == 0)
737                         raw_phase_map |= 1 << i;
738         }
739 
740         if (phase_map)
741                 *phase_map = raw_phase_map;
742 
743         return 0;
744 }
745 
746 static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
747 {
748         int err, i;
749         u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
750         u8 final_phase;
751 
752         for (i = 0; i < RX_TUNING_CNT; i++) {
753                 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
754                 if (err < 0)
755                         return err;
756 
757                 if (raw_phase_map[i] == 0)
758                         break;
759         }
760 
761         phase_map = 0xFFFFFFFF;
762         for (i = 0; i < RX_TUNING_CNT; i++) {
763                 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
764                                 i, raw_phase_map[i]);
765                 phase_map &= raw_phase_map[i];
766         }
767         dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
768 
769         if (phase_map) {
770                 final_phase = sd_search_final_phase(host, phase_map);
771                 if (final_phase == 0xFF)
772                         return -EINVAL;
773 
774                 err = sd_change_phase(host, final_phase, true);
775                 if (err < 0)
776                         return err;
777         } else {
778                 return -EINVAL;
779         }
780 
781         return 0;
782 }
783 
784 static inline int sdio_extblock_cmd(struct mmc_command *cmd,
785         struct mmc_data *data)
786 {
787         return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512);
788 }
789 
790 static inline int sd_rw_cmd(struct mmc_command *cmd)
791 {
792         return mmc_op_multi(cmd->opcode) ||
793                 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
794                 (cmd->opcode == MMC_WRITE_BLOCK);
795 }
796 
797 static void sd_request(struct work_struct *work)
798 {
799         struct realtek_pci_sdmmc *host = container_of(work,
800                         struct realtek_pci_sdmmc, work);
801         struct rtsx_pcr *pcr = host->pcr;
802 
803         struct mmc_host *mmc = host->mmc;
804         struct mmc_request *mrq = host->mrq;
805         struct mmc_command *cmd = mrq->cmd;
806         struct mmc_data *data = mrq->data;
807 
808         unsigned int data_size = 0;
809         int err;
810 
811         if (host->eject || !sd_get_cd_int(host)) {
812                 cmd->error = -ENOMEDIUM;
813                 goto finish;
814         }
815 
816         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
817         if (err) {
818                 cmd->error = err;
819                 goto finish;
820         }
821 
822         mutex_lock(&pcr->pcr_mutex);
823 
824         rtsx_pci_start_run(pcr);
825 
826         rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
827                         host->initial_mode, host->double_clk, host->vpclk);
828         rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
829         rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
830                         CARD_SHARE_MASK, CARD_SHARE_48_SD);
831 
832         mutex_lock(&host->host_mutex);
833         host->mrq = mrq;
834         mutex_unlock(&host->host_mutex);
835 
836         if (mrq->data)
837                 data_size = data->blocks * data->blksz;
838 
839         if (!data_size) {
840                 sd_send_cmd_get_rsp(host, cmd);
841         } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) {
842                 cmd->error = sd_rw_multi(host, mrq);
843                 if (!host->using_cookie)
844                         sdmmc_post_req(host->mmc, host->mrq, 0);
845 
846                 if (mmc_op_multi(cmd->opcode) && mrq->stop)
847                         sd_send_cmd_get_rsp(host, mrq->stop);
848         } else {
849                 sd_normal_rw(host, mrq);
850         }
851 
852         if (mrq->data) {
853                 if (cmd->error || data->error)
854                         data->bytes_xfered = 0;
855                 else
856                         data->bytes_xfered = data->blocks * data->blksz;
857         }
858 
859         mutex_unlock(&pcr->pcr_mutex);
860 
861 finish:
862         if (cmd->error) {
863                 dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n",
864                         cmd->opcode, cmd->arg, cmd->error);
865         }
866 
867         mutex_lock(&host->host_mutex);
868         host->mrq = NULL;
869         mutex_unlock(&host->host_mutex);
870 
871         mmc_request_done(mmc, mrq);
872 }
873 
874 static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
875 {
876         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
877         struct mmc_data *data = mrq->data;
878 
879         mutex_lock(&host->host_mutex);
880         host->mrq = mrq;
881         mutex_unlock(&host->host_mutex);
882 
883         if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data))
884                 host->using_cookie = sd_pre_dma_transfer(host, data, false);
885 
886         schedule_work(&host->work);
887 }
888 
889 static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
890                 unsigned char bus_width)
891 {
892         int err = 0;
893         u8 width[] = {
894                 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
895                 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
896                 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
897         };
898 
899         if (bus_width <= MMC_BUS_WIDTH_8)
900                 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
901                                 0x03, width[bus_width]);
902 
903         return err;
904 }
905 
906 static int sd_power_on(struct realtek_pci_sdmmc *host)
907 {
908         struct rtsx_pcr *pcr = host->pcr;
909         int err;
910 
911         if (host->power_state == SDMMC_POWER_ON)
912                 return 0;
913 
914         rtsx_pci_init_cmd(pcr);
915         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
916         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
917                         CARD_SHARE_MASK, CARD_SHARE_48_SD);
918         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
919                         SD_CLK_EN, SD_CLK_EN);
920         err = rtsx_pci_send_cmd(pcr, 100);
921         if (err < 0)
922                 return err;
923 
924         err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
925         if (err < 0)
926                 return err;
927 
928         err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
929         if (err < 0)
930                 return err;
931 
932         err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
933         if (err < 0)
934                 return err;
935 
936         host->power_state = SDMMC_POWER_ON;
937         return 0;
938 }
939 
940 static int sd_power_off(struct realtek_pci_sdmmc *host)
941 {
942         struct rtsx_pcr *pcr = host->pcr;
943         int err;
944 
945         host->power_state = SDMMC_POWER_OFF;
946 
947         rtsx_pci_init_cmd(pcr);
948 
949         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
950         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
951 
952         err = rtsx_pci_send_cmd(pcr, 100);
953         if (err < 0)
954                 return err;
955 
956         err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
957         if (err < 0)
958                 return err;
959 
960         return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
961 }
962 
963 static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
964                 unsigned char power_mode)
965 {
966         int err;
967 
968         if (power_mode == MMC_POWER_OFF)
969                 err = sd_power_off(host);
970         else
971                 err = sd_power_on(host);
972 
973         return err;
974 }
975 
976 static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
977 {
978         struct rtsx_pcr *pcr = host->pcr;
979         int err = 0;
980 
981         rtsx_pci_init_cmd(pcr);
982 
983         switch (timing) {
984         case MMC_TIMING_UHS_SDR104:
985         case MMC_TIMING_UHS_SDR50:
986                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
987                                 0x0C | SD_ASYNC_FIFO_NOT_RST,
988                                 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
989                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
990                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
991                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
992                                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
993                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
994                 break;
995 
996         case MMC_TIMING_MMC_DDR52:
997         case MMC_TIMING_UHS_DDR50:
998                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
999                                 0x0C | SD_ASYNC_FIFO_NOT_RST,
1000                                 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
1001                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1002                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1003                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1004                                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1005                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1006                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1007                                 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
1008                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1009                                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
1010                                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
1011                 break;
1012 
1013         case MMC_TIMING_MMC_HS:
1014         case MMC_TIMING_SD_HS:
1015                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1016                                 0x0C, SD_20_MODE);
1017                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1018                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1019                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1020                                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1021                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1022                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1023                                 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
1024                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1025                                 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
1026                 break;
1027 
1028         default:
1029                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1030                                 SD_CFG1, 0x0C, SD_20_MODE);
1031                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1032                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1033                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1034                                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1035                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1036                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1037                                 SD_PUSH_POINT_CTL, 0xFF, 0);
1038                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1039                                 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
1040                 break;
1041         }
1042 
1043         err = rtsx_pci_send_cmd(pcr, 100);
1044 
1045         return err;
1046 }
1047 
1048 static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1049 {
1050         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1051         struct rtsx_pcr *pcr = host->pcr;
1052 
1053         if (host->eject)
1054                 return;
1055 
1056         if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
1057                 return;
1058 
1059         mutex_lock(&pcr->pcr_mutex);
1060 
1061         rtsx_pci_start_run(pcr);
1062 
1063         sd_set_bus_width(host, ios->bus_width);
1064         sd_set_power_mode(host, ios->power_mode);
1065         sd_set_timing(host, ios->timing);
1066 
1067         host->vpclk = false;
1068         host->double_clk = true;
1069 
1070         switch (ios->timing) {
1071         case MMC_TIMING_UHS_SDR104:
1072         case MMC_TIMING_UHS_SDR50:
1073                 host->ssc_depth = RTSX_SSC_DEPTH_2M;
1074                 host->vpclk = true;
1075                 host->double_clk = false;
1076                 break;
1077         case MMC_TIMING_MMC_DDR52:
1078         case MMC_TIMING_UHS_DDR50:
1079         case MMC_TIMING_UHS_SDR25:
1080                 host->ssc_depth = RTSX_SSC_DEPTH_1M;
1081                 break;
1082         default:
1083                 host->ssc_depth = RTSX_SSC_DEPTH_500K;
1084                 break;
1085         }
1086 
1087         host->initial_mode = (ios->clock <= 1000000) ? true : false;
1088 
1089         host->clock = ios->clock;
1090         rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
1091                         host->initial_mode, host->double_clk, host->vpclk);
1092 
1093         mutex_unlock(&pcr->pcr_mutex);
1094 }
1095 
1096 static int sdmmc_get_ro(struct mmc_host *mmc)
1097 {
1098         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1099         struct rtsx_pcr *pcr = host->pcr;
1100         int ro = 0;
1101         u32 val;
1102 
1103         if (host->eject)
1104                 return -ENOMEDIUM;
1105 
1106         mutex_lock(&pcr->pcr_mutex);
1107 
1108         rtsx_pci_start_run(pcr);
1109 
1110         /* Check SD mechanical write-protect switch */
1111         val = rtsx_pci_readl(pcr, RTSX_BIPR);
1112         dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1113         if (val & SD_WRITE_PROTECT)
1114                 ro = 1;
1115 
1116         mutex_unlock(&pcr->pcr_mutex);
1117 
1118         return ro;
1119 }
1120 
1121 static int sdmmc_get_cd(struct mmc_host *mmc)
1122 {
1123         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1124         struct rtsx_pcr *pcr = host->pcr;
1125         int cd = 0;
1126         u32 val;
1127 
1128         if (host->eject)
1129                 return cd;
1130 
1131         mutex_lock(&pcr->pcr_mutex);
1132 
1133         rtsx_pci_start_run(pcr);
1134 
1135         /* Check SD card detect */
1136         val = rtsx_pci_card_exist(pcr);
1137         dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1138         if (val & SD_EXIST)
1139                 cd = 1;
1140 
1141         mutex_unlock(&pcr->pcr_mutex);
1142 
1143         return cd;
1144 }
1145 
1146 static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1147 {
1148         struct rtsx_pcr *pcr = host->pcr;
1149         int err;
1150         u8 stat;
1151 
1152         /* Reference to Signal Voltage Switch Sequence in SD spec.
1153          * Wait for a period of time so that the card can drive SD_CMD and
1154          * SD_DAT[3:0] to low after sending back CMD11 response.
1155          */
1156         mdelay(1);
1157 
1158         /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1159          * If either one of SD_CMD,SD_DAT[3:0] is not low,
1160          * abort the voltage switch sequence;
1161          */
1162         err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1163         if (err < 0)
1164                 return err;
1165 
1166         if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1167                                 SD_DAT1_STATUS | SD_DAT0_STATUS))
1168                 return -EINVAL;
1169 
1170         /* Stop toggle SD clock */
1171         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1172                         0xFF, SD_CLK_FORCE_STOP);
1173         if (err < 0)
1174                 return err;
1175 
1176         return 0;
1177 }
1178 
1179 static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1180 {
1181         struct rtsx_pcr *pcr = host->pcr;
1182         int err;
1183         u8 stat, mask, val;
1184 
1185         /* Wait 1.8V output of voltage regulator in card stable */
1186         msleep(50);
1187 
1188         /* Toggle SD clock again */
1189         err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1190         if (err < 0)
1191                 return err;
1192 
1193         /* Wait for a period of time so that the card can drive
1194          * SD_DAT[3:0] to high at 1.8V
1195          */
1196         msleep(20);
1197 
1198         /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1199         err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1200         if (err < 0)
1201                 return err;
1202 
1203         mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1204                 SD_DAT1_STATUS | SD_DAT0_STATUS;
1205         val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1206                 SD_DAT1_STATUS | SD_DAT0_STATUS;
1207         if ((stat & mask) != val) {
1208                 dev_dbg(sdmmc_dev(host),
1209                         "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1210                 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1211                                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1212                 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1213                 return -EINVAL;
1214         }
1215 
1216         return 0;
1217 }
1218 
1219 static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1220 {
1221         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1222         struct rtsx_pcr *pcr = host->pcr;
1223         int err = 0;
1224         u8 voltage;
1225 
1226         dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1227                         __func__, ios->signal_voltage);
1228 
1229         if (host->eject)
1230                 return -ENOMEDIUM;
1231 
1232         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1233         if (err)
1234                 return err;
1235 
1236         mutex_lock(&pcr->pcr_mutex);
1237 
1238         rtsx_pci_start_run(pcr);
1239 
1240         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1241                 voltage = OUTPUT_3V3;
1242         else
1243                 voltage = OUTPUT_1V8;
1244 
1245         if (voltage == OUTPUT_1V8) {
1246                 err = sd_wait_voltage_stable_1(host);
1247                 if (err < 0)
1248                         goto out;
1249         }
1250 
1251         err = rtsx_pci_switch_output_voltage(pcr, voltage);
1252         if (err < 0)
1253                 goto out;
1254 
1255         if (voltage == OUTPUT_1V8) {
1256                 err = sd_wait_voltage_stable_2(host);
1257                 if (err < 0)
1258                         goto out;
1259         }
1260 
1261 out:
1262         /* Stop toggle SD clock in idle */
1263         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1264                         SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1265 
1266         mutex_unlock(&pcr->pcr_mutex);
1267 
1268         return err;
1269 }
1270 
1271 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1272 {
1273         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1274         struct rtsx_pcr *pcr = host->pcr;
1275         int err = 0;
1276 
1277         if (host->eject)
1278                 return -ENOMEDIUM;
1279 
1280         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1281         if (err)
1282                 return err;
1283 
1284         mutex_lock(&pcr->pcr_mutex);
1285 
1286         rtsx_pci_start_run(pcr);
1287 
1288         /* Set initial TX phase */
1289         switch (mmc->ios.timing) {
1290         case MMC_TIMING_UHS_SDR104:
1291                 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1292                 break;
1293 
1294         case MMC_TIMING_UHS_SDR50:
1295                 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1296                 break;
1297 
1298         case MMC_TIMING_UHS_DDR50:
1299                 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1300                 break;
1301 
1302         default:
1303                 err = 0;
1304         }
1305 
1306         if (err)
1307                 goto out;
1308 
1309         /* Tuning RX phase */
1310         if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1311                         (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
1312                 err = sd_tuning_rx(host, opcode);
1313         else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1314                 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1315 
1316 out:
1317         mutex_unlock(&pcr->pcr_mutex);
1318 
1319         return err;
1320 }
1321 
1322 static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1323         .pre_req = sdmmc_pre_req,
1324         .post_req = sdmmc_post_req,
1325         .request = sdmmc_request,
1326         .set_ios = sdmmc_set_ios,
1327         .get_ro = sdmmc_get_ro,
1328         .get_cd = sdmmc_get_cd,
1329         .start_signal_voltage_switch = sdmmc_switch_voltage,
1330         .execute_tuning = sdmmc_execute_tuning,
1331 };
1332 
1333 static void init_extra_caps(struct realtek_pci_sdmmc *host)
1334 {
1335         struct mmc_host *mmc = host->mmc;
1336         struct rtsx_pcr *pcr = host->pcr;
1337 
1338         dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1339 
1340         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1341                 mmc->caps |= MMC_CAP_UHS_SDR50;
1342         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1343                 mmc->caps |= MMC_CAP_UHS_SDR104;
1344         if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1345                 mmc->caps |= MMC_CAP_UHS_DDR50;
1346         if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1347                 mmc->caps |= MMC_CAP_1_8V_DDR;
1348         if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1349                 mmc->caps |= MMC_CAP_8_BIT_DATA;
1350 }
1351 
1352 static void realtek_init_host(struct realtek_pci_sdmmc *host)
1353 {
1354         struct mmc_host *mmc = host->mmc;
1355 
1356         mmc->f_min = 250000;
1357         mmc->f_max = 208000000;
1358         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1359         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1360                 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1361                 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_ERASE;
1362         mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE;
1363         mmc->max_current_330 = 400;
1364         mmc->max_current_180 = 800;
1365         mmc->ops = &realtek_pci_sdmmc_ops;
1366 
1367         init_extra_caps(host);
1368 
1369         mmc->max_segs = 256;
1370         mmc->max_seg_size = 65536;
1371         mmc->max_blk_size = 512;
1372         mmc->max_blk_count = 65535;
1373         mmc->max_req_size = 524288;
1374 }
1375 
1376 static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1377 {
1378         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1379 
1380         host->cookie = -1;
1381         mmc_detect_change(host->mmc, 0);
1382 }
1383 
1384 static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1385 {
1386         struct mmc_host *mmc;
1387         struct realtek_pci_sdmmc *host;
1388         struct rtsx_pcr *pcr;
1389         struct pcr_handle *handle = pdev->dev.platform_data;
1390 
1391         if (!handle)
1392                 return -ENXIO;
1393 
1394         pcr = handle->pcr;
1395         if (!pcr)
1396                 return -ENXIO;
1397 
1398         dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1399 
1400         mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1401         if (!mmc)
1402                 return -ENOMEM;
1403 
1404         host = mmc_priv(mmc);
1405         host->pcr = pcr;
1406         host->mmc = mmc;
1407         host->pdev = pdev;
1408         host->cookie = -1;
1409         host->power_state = SDMMC_POWER_OFF;
1410         INIT_WORK(&host->work, sd_request);
1411         platform_set_drvdata(pdev, host);
1412         pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1413         pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1414 
1415         mutex_init(&host->host_mutex);
1416 
1417         realtek_init_host(host);
1418 
1419         mmc_add_host(mmc);
1420 
1421         return 0;
1422 }
1423 
1424 static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1425 {
1426         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1427         struct rtsx_pcr *pcr;
1428         struct mmc_host *mmc;
1429 
1430         if (!host)
1431                 return 0;
1432 
1433         pcr = host->pcr;
1434         pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1435         pcr->slots[RTSX_SD_CARD].card_event = NULL;
1436         mmc = host->mmc;
1437 
1438         cancel_work_sync(&host->work);
1439 
1440         mutex_lock(&host->host_mutex);
1441         if (host->mrq) {
1442                 dev_dbg(&(pdev->dev),
1443                         "%s: Controller removed during transfer\n",
1444                         mmc_hostname(mmc));
1445 
1446                 rtsx_pci_complete_unfinished_transfer(pcr);
1447 
1448                 host->mrq->cmd->error = -ENOMEDIUM;
1449                 if (host->mrq->stop)
1450                         host->mrq->stop->error = -ENOMEDIUM;
1451                 mmc_request_done(mmc, host->mrq);
1452         }
1453         mutex_unlock(&host->host_mutex);
1454 
1455         mmc_remove_host(mmc);
1456         host->eject = true;
1457 
1458         flush_work(&host->work);
1459 
1460         mmc_free_host(mmc);
1461 
1462         dev_dbg(&(pdev->dev),
1463                 ": Realtek PCI-E SDMMC controller has been removed\n");
1464 
1465         return 0;
1466 }
1467 
1468 static const struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1469         {
1470                 .name = DRV_NAME_RTSX_PCI_SDMMC,
1471         }, {
1472                 /* sentinel */
1473         }
1474 };
1475 MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1476 
1477 static struct platform_driver rtsx_pci_sdmmc_driver = {
1478         .probe          = rtsx_pci_sdmmc_drv_probe,
1479         .remove         = rtsx_pci_sdmmc_drv_remove,
1480         .id_table       = rtsx_pci_sdmmc_ids,
1481         .driver         = {
1482                 .name   = DRV_NAME_RTSX_PCI_SDMMC,
1483         },
1484 };
1485 module_platform_driver(rtsx_pci_sdmmc_driver);
1486 
1487 MODULE_LICENSE("GPL");
1488 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1489 MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");
1490 

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