Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/mmc/host/rtsx_pci_sdmmc.c

  1 /* Realtek PCI-Express SD/MMC Card Interface driver
  2  *
  3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
  4  *
  5  * This program is free software; you can redistribute it and/or modify it
  6  * under the terms of the GNU General Public License as published by the
  7  * Free Software Foundation; either version 2, or (at your option) any
  8  * later version.
  9  *
 10  * This program is distributed in the hope that it will be useful, but
 11  * WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 13  * General Public License for more details.
 14  *
 15  * You should have received a copy of the GNU General Public License along
 16  * with this program; if not, see <http://www.gnu.org/licenses/>.
 17  *
 18  * Author:
 19  *   Wei WANG <wei_wang@realsil.com.cn>
 20  */
 21 
 22 #include <linux/module.h>
 23 #include <linux/slab.h>
 24 #include <linux/highmem.h>
 25 #include <linux/delay.h>
 26 #include <linux/platform_device.h>
 27 #include <linux/mmc/host.h>
 28 #include <linux/mmc/mmc.h>
 29 #include <linux/mmc/sd.h>
 30 #include <linux/mmc/card.h>
 31 #include <linux/mfd/rtsx_pci.h>
 32 #include <asm/unaligned.h>
 33 
 34 struct realtek_pci_sdmmc {
 35         struct platform_device  *pdev;
 36         struct rtsx_pcr         *pcr;
 37         struct mmc_host         *mmc;
 38         struct mmc_request      *mrq;
 39 
 40         struct mutex            host_mutex;
 41 
 42         u8                      ssc_depth;
 43         unsigned int            clock;
 44         bool                    vpclk;
 45         bool                    double_clk;
 46         bool                    eject;
 47         bool                    initial_mode;
 48         int                     power_state;
 49 #define SDMMC_POWER_ON          1
 50 #define SDMMC_POWER_OFF         0
 51 };
 52 
 53 static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
 54 {
 55         return &(host->pdev->dev);
 56 }
 57 
 58 static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
 59 {
 60         rtsx_pci_write_register(host->pcr, CARD_STOP,
 61                         SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
 62 }
 63 
 64 #ifdef DEBUG
 65 static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
 66 {
 67         struct rtsx_pcr *pcr = host->pcr;
 68         u16 i;
 69         u8 *ptr;
 70 
 71         /* Print SD host internal registers */
 72         rtsx_pci_init_cmd(pcr);
 73         for (i = 0xFDA0; i <= 0xFDAE; i++)
 74                 rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
 75         for (i = 0xFD52; i <= 0xFD69; i++)
 76                 rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
 77         rtsx_pci_send_cmd(pcr, 100);
 78 
 79         ptr = rtsx_pci_get_cmd_data(pcr);
 80         for (i = 0xFDA0; i <= 0xFDAE; i++)
 81                 dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
 82         for (i = 0xFD52; i <= 0xFD69; i++)
 83                 dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
 84 }
 85 #else
 86 #define sd_print_debug_regs(host)
 87 #endif /* DEBUG */
 88 
 89 static int sd_read_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt,
 90                 u8 *buf, int buf_len, int timeout)
 91 {
 92         struct rtsx_pcr *pcr = host->pcr;
 93         int err, i;
 94         u8 trans_mode;
 95 
 96         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD%d\n", __func__, cmd[0] - 0x40);
 97 
 98         if (!buf)
 99                 buf_len = 0;
100 
101         if ((cmd[0] & 0x3F) == MMC_SEND_TUNING_BLOCK)
102                 trans_mode = SD_TM_AUTO_TUNING;
103         else
104                 trans_mode = SD_TM_NORMAL_READ;
105 
106         rtsx_pci_init_cmd(pcr);
107 
108         for (i = 0; i < 5; i++)
109                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0 + i, 0xFF, cmd[i]);
110 
111         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
112         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H,
113                         0xFF, (u8)(byte_cnt >> 8));
114         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
115         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
116 
117         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
118                         SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
119                         SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
120         if (trans_mode != SD_TM_AUTO_TUNING)
121                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
122                                 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
123 
124         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
125                         0xFF, trans_mode | SD_TRANSFER_START);
126         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
127                         SD_TRANSFER_END, SD_TRANSFER_END);
128 
129         err = rtsx_pci_send_cmd(pcr, timeout);
130         if (err < 0) {
131                 sd_print_debug_regs(host);
132                 dev_dbg(sdmmc_dev(host),
133                         "rtsx_pci_send_cmd fail (err = %d)\n", err);
134                 return err;
135         }
136 
137         if (buf && buf_len) {
138                 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
139                 if (err < 0) {
140                         dev_dbg(sdmmc_dev(host),
141                                 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
142                         return err;
143                 }
144         }
145 
146         return 0;
147 }
148 
149 static int sd_write_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt,
150                 u8 *buf, int buf_len, int timeout)
151 {
152         struct rtsx_pcr *pcr = host->pcr;
153         int err, i;
154         u8 trans_mode;
155 
156         if (!buf)
157                 buf_len = 0;
158 
159         if (buf && buf_len) {
160                 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
161                 if (err < 0) {
162                         dev_dbg(sdmmc_dev(host),
163                                 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
164                         return err;
165                 }
166         }
167 
168         trans_mode = cmd ? SD_TM_AUTO_WRITE_2 : SD_TM_AUTO_WRITE_3;
169         rtsx_pci_init_cmd(pcr);
170 
171         if (cmd) {
172                 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d\n", __func__,
173                                 cmd[0] - 0x40);
174 
175                 for (i = 0; i < 5; i++)
176                         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
177                                         SD_CMD0 + i, 0xFF, cmd[i]);
178         }
179 
180         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
181         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H,
182                         0xFF, (u8)(byte_cnt >> 8));
183         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
184         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
185 
186         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
187                 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
188                 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
189 
190         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
191                         trans_mode | SD_TRANSFER_START);
192         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
193                         SD_TRANSFER_END, SD_TRANSFER_END);
194 
195         err = rtsx_pci_send_cmd(pcr, timeout);
196         if (err < 0) {
197                 sd_print_debug_regs(host);
198                 dev_dbg(sdmmc_dev(host),
199                         "rtsx_pci_send_cmd fail (err = %d)\n", err);
200                 return err;
201         }
202 
203         return 0;
204 }
205 
206 static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
207                 struct mmc_command *cmd)
208 {
209         struct rtsx_pcr *pcr = host->pcr;
210         u8 cmd_idx = (u8)cmd->opcode;
211         u32 arg = cmd->arg;
212         int err = 0;
213         int timeout = 100;
214         int i;
215         u8 *ptr;
216         int stat_idx = 0;
217         u8 rsp_type;
218         int rsp_len = 5;
219         bool clock_toggled = false;
220 
221         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
222                         __func__, cmd_idx, arg);
223 
224         /* Response type:
225          * R0
226          * R1, R5, R6, R7
227          * R1b
228          * R2
229          * R3, R4
230          */
231         switch (mmc_resp_type(cmd)) {
232         case MMC_RSP_NONE:
233                 rsp_type = SD_RSP_TYPE_R0;
234                 rsp_len = 0;
235                 break;
236         case MMC_RSP_R1:
237                 rsp_type = SD_RSP_TYPE_R1;
238                 break;
239         case MMC_RSP_R1 & ~MMC_RSP_CRC:
240                 rsp_type = SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
241                 break;
242         case MMC_RSP_R1B:
243                 rsp_type = SD_RSP_TYPE_R1b;
244                 break;
245         case MMC_RSP_R2:
246                 rsp_type = SD_RSP_TYPE_R2;
247                 rsp_len = 16;
248                 break;
249         case MMC_RSP_R3:
250                 rsp_type = SD_RSP_TYPE_R3;
251                 break;
252         default:
253                 dev_dbg(sdmmc_dev(host), "cmd->flag is not valid\n");
254                 err = -EINVAL;
255                 goto out;
256         }
257 
258         if (rsp_type == SD_RSP_TYPE_R1b)
259                 timeout = 3000;
260 
261         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
262                 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
263                                 0xFF, SD_CLK_TOGGLE_EN);
264                 if (err < 0)
265                         goto out;
266 
267                 clock_toggled = true;
268         }
269 
270         rtsx_pci_init_cmd(pcr);
271 
272         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx);
273         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8)(arg >> 24));
274         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8)(arg >> 16));
275         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8)(arg >> 8));
276         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8)arg);
277 
278         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
279         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
280                         0x01, PINGPONG_BUFFER);
281         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
282                         0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
283         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
284                      SD_TRANSFER_END | SD_STAT_IDLE,
285                      SD_TRANSFER_END | SD_STAT_IDLE);
286 
287         if (rsp_type == SD_RSP_TYPE_R2) {
288                 /* Read data from ping-pong buffer */
289                 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
290                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
291                 stat_idx = 16;
292         } else if (rsp_type != SD_RSP_TYPE_R0) {
293                 /* Read data from SD_CMDx registers */
294                 for (i = SD_CMD0; i <= SD_CMD4; i++)
295                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
296                 stat_idx = 5;
297         }
298 
299         rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
300 
301         err = rtsx_pci_send_cmd(pcr, timeout);
302         if (err < 0) {
303                 sd_print_debug_regs(host);
304                 sd_clear_error(host);
305                 dev_dbg(sdmmc_dev(host),
306                         "rtsx_pci_send_cmd error (err = %d)\n", err);
307                 goto out;
308         }
309 
310         if (rsp_type == SD_RSP_TYPE_R0) {
311                 err = 0;
312                 goto out;
313         }
314 
315         /* Eliminate returned value of CHECK_REG_CMD */
316         ptr = rtsx_pci_get_cmd_data(pcr) + 1;
317 
318         /* Check (Start,Transmission) bit of Response */
319         if ((ptr[0] & 0xC0) != 0) {
320                 err = -EILSEQ;
321                 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
322                 goto out;
323         }
324 
325         /* Check CRC7 */
326         if (!(rsp_type & SD_NO_CHECK_CRC7)) {
327                 if (ptr[stat_idx] & SD_CRC7_ERR) {
328                         err = -EILSEQ;
329                         dev_dbg(sdmmc_dev(host), "CRC7 error\n");
330                         goto out;
331                 }
332         }
333 
334         if (rsp_type == SD_RSP_TYPE_R2) {
335                 for (i = 0; i < 4; i++) {
336                         cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
337                         dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
338                                         i, cmd->resp[i]);
339                 }
340         } else {
341                 cmd->resp[0] = get_unaligned_be32(ptr + 1);
342                 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
343                                 cmd->resp[0]);
344         }
345 
346 out:
347         cmd->error = err;
348 
349         if (err && clock_toggled)
350                 rtsx_pci_write_register(pcr, SD_BUS_STAT,
351                                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
352 }
353 
354 static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
355 {
356         struct rtsx_pcr *pcr = host->pcr;
357         struct mmc_host *mmc = host->mmc;
358         struct mmc_card *card = mmc->card;
359         struct mmc_data *data = mrq->data;
360         int uhs = mmc_card_uhs(card);
361         int read = (data->flags & MMC_DATA_READ) ? 1 : 0;
362         u8 cfg2, trans_mode;
363         int err;
364         size_t data_len = data->blksz * data->blocks;
365 
366         if (read) {
367                 cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
368                         SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0;
369                 trans_mode = SD_TM_AUTO_READ_3;
370         } else {
371                 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
372                         SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
373                 trans_mode = SD_TM_AUTO_WRITE_3;
374         }
375 
376         if (!uhs)
377                 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
378 
379         rtsx_pci_init_cmd(pcr);
380 
381         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00);
382         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02);
383         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L,
384                         0xFF, (u8)data->blocks);
385         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H,
386                         0xFF, (u8)(data->blocks >> 8));
387 
388         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
389                         DMA_DONE_INT, DMA_DONE_INT);
390         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
391                         0xFF, (u8)(data_len >> 24));
392         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
393                         0xFF, (u8)(data_len >> 16));
394         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
395                         0xFF, (u8)(data_len >> 8));
396         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
397         if (read) {
398                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
399                                 0x03 | DMA_PACK_SIZE_MASK,
400                                 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
401         } else {
402                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
403                                 0x03 | DMA_PACK_SIZE_MASK,
404                                 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
405         }
406 
407         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
408                         0x01, RING_BUFFER);
409 
410         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
411         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
412                         trans_mode | SD_TRANSFER_START);
413         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
414                         SD_TRANSFER_END, SD_TRANSFER_END);
415 
416         rtsx_pci_send_cmd_no_wait(pcr);
417 
418         err = rtsx_pci_transfer_data(pcr, data->sg, data->sg_len, read, 10000);
419         if (err < 0) {
420                 sd_clear_error(host);
421                 return err;
422         }
423 
424         return 0;
425 }
426 
427 static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
428 {
429         rtsx_pci_write_register(host->pcr, SD_CFG1,
430                         SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
431 }
432 
433 static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
434 {
435         rtsx_pci_write_register(host->pcr, SD_CFG1,
436                         SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
437 }
438 
439 static void sd_normal_rw(struct realtek_pci_sdmmc *host,
440                 struct mmc_request *mrq)
441 {
442         struct mmc_command *cmd = mrq->cmd;
443         struct mmc_data *data = mrq->data;
444         u8 _cmd[5], *buf;
445 
446         _cmd[0] = 0x40 | (u8)cmd->opcode;
447         put_unaligned_be32(cmd->arg, (u32 *)(&_cmd[1]));
448 
449         buf = kzalloc(data->blksz, GFP_NOIO);
450         if (!buf) {
451                 cmd->error = -ENOMEM;
452                 return;
453         }
454 
455         if (data->flags & MMC_DATA_READ) {
456                 if (host->initial_mode)
457                         sd_disable_initial_mode(host);
458 
459                 cmd->error = sd_read_data(host, _cmd, (u16)data->blksz, buf,
460                                 data->blksz, 200);
461 
462                 if (host->initial_mode)
463                         sd_enable_initial_mode(host);
464 
465                 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
466         } else {
467                 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
468 
469                 cmd->error = sd_write_data(host, _cmd, (u16)data->blksz, buf,
470                                 data->blksz, 200);
471         }
472 
473         kfree(buf);
474 }
475 
476 static int sd_change_phase(struct realtek_pci_sdmmc *host,
477                 u8 sample_point, bool rx)
478 {
479         struct rtsx_pcr *pcr = host->pcr;
480         int err;
481 
482         dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
483                         __func__, rx ? "RX" : "TX", sample_point);
484 
485         rtsx_pci_init_cmd(pcr);
486 
487         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
488         if (rx)
489                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
490                                 SD_VPRX_CTL, 0x1F, sample_point);
491         else
492                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
493                                 SD_VPTX_CTL, 0x1F, sample_point);
494         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
495         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
496                         PHASE_NOT_RESET, PHASE_NOT_RESET);
497         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0);
498         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
499 
500         err = rtsx_pci_send_cmd(pcr, 100);
501         if (err < 0)
502                 return err;
503 
504         return 0;
505 }
506 
507 static inline u32 test_phase_bit(u32 phase_map, unsigned int bit)
508 {
509         bit %= RTSX_PHASE_MAX;
510         return phase_map & (1 << bit);
511 }
512 
513 static int sd_get_phase_len(u32 phase_map, unsigned int start_bit)
514 {
515         int i;
516 
517         for (i = 0; i < RTSX_PHASE_MAX; i++) {
518                 if (test_phase_bit(phase_map, start_bit + i) == 0)
519                         return i;
520         }
521         return RTSX_PHASE_MAX;
522 }
523 
524 static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
525 {
526         int start = 0, len = 0;
527         int start_final = 0, len_final = 0;
528         u8 final_phase = 0xFF;
529 
530         if (phase_map == 0) {
531                 dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map);
532                 return final_phase;
533         }
534 
535         while (start < RTSX_PHASE_MAX) {
536                 len = sd_get_phase_len(phase_map, start);
537                 if (len_final < len) {
538                         start_final = start;
539                         len_final = len;
540                 }
541                 start += len ? len : 1;
542         }
543 
544         final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX;
545         dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n",
546                 phase_map, len_final, final_phase);
547 
548         return final_phase;
549 }
550 
551 static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
552 {
553         int err, i;
554         u8 val = 0;
555 
556         for (i = 0; i < 100; i++) {
557                 err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
558                 if (val & SD_DATA_IDLE)
559                         return;
560 
561                 udelay(100);
562         }
563 }
564 
565 static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
566                 u8 opcode, u8 sample_point)
567 {
568         int err;
569         u8 cmd[5] = {0};
570 
571         err = sd_change_phase(host, sample_point, true);
572         if (err < 0)
573                 return err;
574 
575         cmd[0] = 0x40 | opcode;
576         err = sd_read_data(host, cmd, 0x40, NULL, 0, 100);
577         if (err < 0) {
578                 /* Wait till SD DATA IDLE */
579                 sd_wait_data_idle(host);
580                 sd_clear_error(host);
581                 return err;
582         }
583 
584         return 0;
585 }
586 
587 static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
588                 u8 opcode, u32 *phase_map)
589 {
590         int err, i;
591         u32 raw_phase_map = 0;
592 
593         for (i = 0; i < RTSX_PHASE_MAX; i++) {
594                 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
595                 if (err == 0)
596                         raw_phase_map |= 1 << i;
597         }
598 
599         if (phase_map)
600                 *phase_map = raw_phase_map;
601 
602         return 0;
603 }
604 
605 static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
606 {
607         int err, i;
608         u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
609         u8 final_phase;
610 
611         for (i = 0; i < RX_TUNING_CNT; i++) {
612                 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
613                 if (err < 0)
614                         return err;
615 
616                 if (raw_phase_map[i] == 0)
617                         break;
618         }
619 
620         phase_map = 0xFFFFFFFF;
621         for (i = 0; i < RX_TUNING_CNT; i++) {
622                 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
623                                 i, raw_phase_map[i]);
624                 phase_map &= raw_phase_map[i];
625         }
626         dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
627 
628         if (phase_map) {
629                 final_phase = sd_search_final_phase(host, phase_map);
630                 if (final_phase == 0xFF)
631                         return -EINVAL;
632 
633                 err = sd_change_phase(host, final_phase, true);
634                 if (err < 0)
635                         return err;
636         } else {
637                 return -EINVAL;
638         }
639 
640         return 0;
641 }
642 
643 static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
644 {
645         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
646         struct rtsx_pcr *pcr = host->pcr;
647         struct mmc_command *cmd = mrq->cmd;
648         struct mmc_data *data = mrq->data;
649         unsigned int data_size = 0;
650         int err;
651 
652         if (host->eject) {
653                 cmd->error = -ENOMEDIUM;
654                 goto finish;
655         }
656 
657         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
658         if (err) {
659                 cmd->error = err;
660                 goto finish;
661         }
662 
663         mutex_lock(&pcr->pcr_mutex);
664 
665         rtsx_pci_start_run(pcr);
666 
667         rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
668                         host->initial_mode, host->double_clk, host->vpclk);
669         rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
670         rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
671                         CARD_SHARE_MASK, CARD_SHARE_48_SD);
672 
673         mutex_lock(&host->host_mutex);
674         host->mrq = mrq;
675         mutex_unlock(&host->host_mutex);
676 
677         if (mrq->data)
678                 data_size = data->blocks * data->blksz;
679 
680         if (!data_size || mmc_op_multi(cmd->opcode) ||
681                         (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
682                         (cmd->opcode == MMC_WRITE_BLOCK)) {
683                 sd_send_cmd_get_rsp(host, cmd);
684 
685                 if (!cmd->error && data_size) {
686                         sd_rw_multi(host, mrq);
687 
688                         if (mmc_op_multi(cmd->opcode) && mrq->stop)
689                                 sd_send_cmd_get_rsp(host, mrq->stop);
690                 }
691         } else {
692                 sd_normal_rw(host, mrq);
693         }
694 
695         if (mrq->data) {
696                 if (cmd->error || data->error)
697                         data->bytes_xfered = 0;
698                 else
699                         data->bytes_xfered = data->blocks * data->blksz;
700         }
701 
702         mutex_unlock(&pcr->pcr_mutex);
703 
704 finish:
705         if (cmd->error)
706                 dev_dbg(sdmmc_dev(host), "cmd->error = %d\n", cmd->error);
707 
708         mutex_lock(&host->host_mutex);
709         host->mrq = NULL;
710         mutex_unlock(&host->host_mutex);
711 
712         mmc_request_done(mmc, mrq);
713 }
714 
715 static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
716                 unsigned char bus_width)
717 {
718         int err = 0;
719         u8 width[] = {
720                 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
721                 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
722                 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
723         };
724 
725         if (bus_width <= MMC_BUS_WIDTH_8)
726                 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
727                                 0x03, width[bus_width]);
728 
729         return err;
730 }
731 
732 static int sd_power_on(struct realtek_pci_sdmmc *host)
733 {
734         struct rtsx_pcr *pcr = host->pcr;
735         int err;
736 
737         if (host->power_state == SDMMC_POWER_ON)
738                 return 0;
739 
740         rtsx_pci_init_cmd(pcr);
741         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
742         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
743                         CARD_SHARE_MASK, CARD_SHARE_48_SD);
744         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
745                         SD_CLK_EN, SD_CLK_EN);
746         err = rtsx_pci_send_cmd(pcr, 100);
747         if (err < 0)
748                 return err;
749 
750         err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
751         if (err < 0)
752                 return err;
753 
754         err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
755         if (err < 0)
756                 return err;
757 
758         err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
759         if (err < 0)
760                 return err;
761 
762         host->power_state = SDMMC_POWER_ON;
763         return 0;
764 }
765 
766 static int sd_power_off(struct realtek_pci_sdmmc *host)
767 {
768         struct rtsx_pcr *pcr = host->pcr;
769         int err;
770 
771         host->power_state = SDMMC_POWER_OFF;
772 
773         rtsx_pci_init_cmd(pcr);
774 
775         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
776         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
777 
778         err = rtsx_pci_send_cmd(pcr, 100);
779         if (err < 0)
780                 return err;
781 
782         err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
783         if (err < 0)
784                 return err;
785 
786         return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
787 }
788 
789 static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
790                 unsigned char power_mode)
791 {
792         int err;
793 
794         if (power_mode == MMC_POWER_OFF)
795                 err = sd_power_off(host);
796         else
797                 err = sd_power_on(host);
798 
799         return err;
800 }
801 
802 static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
803 {
804         struct rtsx_pcr *pcr = host->pcr;
805         int err = 0;
806 
807         rtsx_pci_init_cmd(pcr);
808 
809         switch (timing) {
810         case MMC_TIMING_UHS_SDR104:
811         case MMC_TIMING_UHS_SDR50:
812                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
813                                 0x0C | SD_ASYNC_FIFO_NOT_RST,
814                                 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
815                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
816                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
817                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
818                                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
819                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
820                 break;
821 
822         case MMC_TIMING_MMC_DDR52:
823         case MMC_TIMING_UHS_DDR50:
824                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
825                                 0x0C | SD_ASYNC_FIFO_NOT_RST,
826                                 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
827                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
828                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
829                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
830                                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
831                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
832                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
833                                 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
834                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
835                                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
836                                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
837                 break;
838 
839         case MMC_TIMING_MMC_HS:
840         case MMC_TIMING_SD_HS:
841                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
842                                 0x0C, SD_20_MODE);
843                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
844                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
845                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
846                                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
847                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
848                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
849                                 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
850                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
851                                 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
852                 break;
853 
854         default:
855                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
856                                 SD_CFG1, 0x0C, SD_20_MODE);
857                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
858                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
859                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
860                                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
861                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
862                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
863                                 SD_PUSH_POINT_CTL, 0xFF, 0);
864                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
865                                 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
866                 break;
867         }
868 
869         err = rtsx_pci_send_cmd(pcr, 100);
870 
871         return err;
872 }
873 
874 static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
875 {
876         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
877         struct rtsx_pcr *pcr = host->pcr;
878 
879         if (host->eject)
880                 return;
881 
882         if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
883                 return;
884 
885         mutex_lock(&pcr->pcr_mutex);
886 
887         rtsx_pci_start_run(pcr);
888 
889         sd_set_bus_width(host, ios->bus_width);
890         sd_set_power_mode(host, ios->power_mode);
891         sd_set_timing(host, ios->timing);
892 
893         host->vpclk = false;
894         host->double_clk = true;
895 
896         switch (ios->timing) {
897         case MMC_TIMING_UHS_SDR104:
898         case MMC_TIMING_UHS_SDR50:
899                 host->ssc_depth = RTSX_SSC_DEPTH_2M;
900                 host->vpclk = true;
901                 host->double_clk = false;
902                 break;
903         case MMC_TIMING_MMC_DDR52:
904         case MMC_TIMING_UHS_DDR50:
905         case MMC_TIMING_UHS_SDR25:
906                 host->ssc_depth = RTSX_SSC_DEPTH_1M;
907                 break;
908         default:
909                 host->ssc_depth = RTSX_SSC_DEPTH_500K;
910                 break;
911         }
912 
913         host->initial_mode = (ios->clock <= 1000000) ? true : false;
914 
915         host->clock = ios->clock;
916         rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
917                         host->initial_mode, host->double_clk, host->vpclk);
918 
919         mutex_unlock(&pcr->pcr_mutex);
920 }
921 
922 static int sdmmc_get_ro(struct mmc_host *mmc)
923 {
924         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
925         struct rtsx_pcr *pcr = host->pcr;
926         int ro = 0;
927         u32 val;
928 
929         if (host->eject)
930                 return -ENOMEDIUM;
931 
932         mutex_lock(&pcr->pcr_mutex);
933 
934         rtsx_pci_start_run(pcr);
935 
936         /* Check SD mechanical write-protect switch */
937         val = rtsx_pci_readl(pcr, RTSX_BIPR);
938         dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
939         if (val & SD_WRITE_PROTECT)
940                 ro = 1;
941 
942         mutex_unlock(&pcr->pcr_mutex);
943 
944         return ro;
945 }
946 
947 static int sdmmc_get_cd(struct mmc_host *mmc)
948 {
949         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
950         struct rtsx_pcr *pcr = host->pcr;
951         int cd = 0;
952         u32 val;
953 
954         if (host->eject)
955                 return -ENOMEDIUM;
956 
957         mutex_lock(&pcr->pcr_mutex);
958 
959         rtsx_pci_start_run(pcr);
960 
961         /* Check SD card detect */
962         val = rtsx_pci_card_exist(pcr);
963         dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
964         if (val & SD_EXIST)
965                 cd = 1;
966 
967         mutex_unlock(&pcr->pcr_mutex);
968 
969         return cd;
970 }
971 
972 static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
973 {
974         struct rtsx_pcr *pcr = host->pcr;
975         int err;
976         u8 stat;
977 
978         /* Reference to Signal Voltage Switch Sequence in SD spec.
979          * Wait for a period of time so that the card can drive SD_CMD and
980          * SD_DAT[3:0] to low after sending back CMD11 response.
981          */
982         mdelay(1);
983 
984         /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
985          * If either one of SD_CMD,SD_DAT[3:0] is not low,
986          * abort the voltage switch sequence;
987          */
988         err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
989         if (err < 0)
990                 return err;
991 
992         if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
993                                 SD_DAT1_STATUS | SD_DAT0_STATUS))
994                 return -EINVAL;
995 
996         /* Stop toggle SD clock */
997         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
998                         0xFF, SD_CLK_FORCE_STOP);
999         if (err < 0)
1000                 return err;
1001 
1002         return 0;
1003 }
1004 
1005 static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1006 {
1007         struct rtsx_pcr *pcr = host->pcr;
1008         int err;
1009         u8 stat, mask, val;
1010 
1011         /* Wait 1.8V output of voltage regulator in card stable */
1012         msleep(50);
1013 
1014         /* Toggle SD clock again */
1015         err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1016         if (err < 0)
1017                 return err;
1018 
1019         /* Wait for a period of time so that the card can drive
1020          * SD_DAT[3:0] to high at 1.8V
1021          */
1022         msleep(20);
1023 
1024         /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1025         err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1026         if (err < 0)
1027                 return err;
1028 
1029         mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1030                 SD_DAT1_STATUS | SD_DAT0_STATUS;
1031         val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1032                 SD_DAT1_STATUS | SD_DAT0_STATUS;
1033         if ((stat & mask) != val) {
1034                 dev_dbg(sdmmc_dev(host),
1035                         "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1036                 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1037                                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1038                 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1039                 return -EINVAL;
1040         }
1041 
1042         return 0;
1043 }
1044 
1045 static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1046 {
1047         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1048         struct rtsx_pcr *pcr = host->pcr;
1049         int err = 0;
1050         u8 voltage;
1051 
1052         dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1053                         __func__, ios->signal_voltage);
1054 
1055         if (host->eject)
1056                 return -ENOMEDIUM;
1057 
1058         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1059         if (err)
1060                 return err;
1061 
1062         mutex_lock(&pcr->pcr_mutex);
1063 
1064         rtsx_pci_start_run(pcr);
1065 
1066         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1067                 voltage = OUTPUT_3V3;
1068         else
1069                 voltage = OUTPUT_1V8;
1070 
1071         if (voltage == OUTPUT_1V8) {
1072                 err = sd_wait_voltage_stable_1(host);
1073                 if (err < 0)
1074                         goto out;
1075         }
1076 
1077         err = rtsx_pci_switch_output_voltage(pcr, voltage);
1078         if (err < 0)
1079                 goto out;
1080 
1081         if (voltage == OUTPUT_1V8) {
1082                 err = sd_wait_voltage_stable_2(host);
1083                 if (err < 0)
1084                         goto out;
1085         }
1086 
1087 out:
1088         /* Stop toggle SD clock in idle */
1089         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1090                         SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1091 
1092         mutex_unlock(&pcr->pcr_mutex);
1093 
1094         return err;
1095 }
1096 
1097 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1098 {
1099         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1100         struct rtsx_pcr *pcr = host->pcr;
1101         int err = 0;
1102 
1103         if (host->eject)
1104                 return -ENOMEDIUM;
1105 
1106         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1107         if (err)
1108                 return err;
1109 
1110         mutex_lock(&pcr->pcr_mutex);
1111 
1112         rtsx_pci_start_run(pcr);
1113 
1114         /* Set initial TX phase */
1115         switch (mmc->ios.timing) {
1116         case MMC_TIMING_UHS_SDR104:
1117                 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1118                 break;
1119 
1120         case MMC_TIMING_UHS_SDR50:
1121                 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1122                 break;
1123 
1124         case MMC_TIMING_UHS_DDR50:
1125                 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1126                 break;
1127 
1128         default:
1129                 err = 0;
1130         }
1131 
1132         if (err)
1133                 goto out;
1134 
1135         /* Tuning RX phase */
1136         if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1137                         (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
1138                 err = sd_tuning_rx(host, opcode);
1139         else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1140                 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1141 
1142 out:
1143         mutex_unlock(&pcr->pcr_mutex);
1144 
1145         return err;
1146 }
1147 
1148 static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1149         .request = sdmmc_request,
1150         .set_ios = sdmmc_set_ios,
1151         .get_ro = sdmmc_get_ro,
1152         .get_cd = sdmmc_get_cd,
1153         .start_signal_voltage_switch = sdmmc_switch_voltage,
1154         .execute_tuning = sdmmc_execute_tuning,
1155 };
1156 
1157 static void init_extra_caps(struct realtek_pci_sdmmc *host)
1158 {
1159         struct mmc_host *mmc = host->mmc;
1160         struct rtsx_pcr *pcr = host->pcr;
1161 
1162         dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1163 
1164         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1165                 mmc->caps |= MMC_CAP_UHS_SDR50;
1166         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1167                 mmc->caps |= MMC_CAP_UHS_SDR104;
1168         if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1169                 mmc->caps |= MMC_CAP_UHS_DDR50;
1170         if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1171                 mmc->caps |= MMC_CAP_1_8V_DDR;
1172         if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1173                 mmc->caps |= MMC_CAP_8_BIT_DATA;
1174 }
1175 
1176 static void realtek_init_host(struct realtek_pci_sdmmc *host)
1177 {
1178         struct mmc_host *mmc = host->mmc;
1179 
1180         mmc->f_min = 250000;
1181         mmc->f_max = 208000000;
1182         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1183         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1184                 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1185                 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
1186         mmc->max_current_330 = 400;
1187         mmc->max_current_180 = 800;
1188         mmc->ops = &realtek_pci_sdmmc_ops;
1189 
1190         init_extra_caps(host);
1191 
1192         mmc->max_segs = 256;
1193         mmc->max_seg_size = 65536;
1194         mmc->max_blk_size = 512;
1195         mmc->max_blk_count = 65535;
1196         mmc->max_req_size = 524288;
1197 }
1198 
1199 static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1200 {
1201         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1202 
1203         mmc_detect_change(host->mmc, 0);
1204 }
1205 
1206 static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1207 {
1208         struct mmc_host *mmc;
1209         struct realtek_pci_sdmmc *host;
1210         struct rtsx_pcr *pcr;
1211         struct pcr_handle *handle = pdev->dev.platform_data;
1212 
1213         if (!handle)
1214                 return -ENXIO;
1215 
1216         pcr = handle->pcr;
1217         if (!pcr)
1218                 return -ENXIO;
1219 
1220         dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1221 
1222         mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1223         if (!mmc)
1224                 return -ENOMEM;
1225 
1226         host = mmc_priv(mmc);
1227         host->pcr = pcr;
1228         host->mmc = mmc;
1229         host->pdev = pdev;
1230         host->power_state = SDMMC_POWER_OFF;
1231         platform_set_drvdata(pdev, host);
1232         pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1233         pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1234 
1235         mutex_init(&host->host_mutex);
1236 
1237         realtek_init_host(host);
1238 
1239         mmc_add_host(mmc);
1240 
1241         return 0;
1242 }
1243 
1244 static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1245 {
1246         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1247         struct rtsx_pcr *pcr;
1248         struct mmc_host *mmc;
1249 
1250         if (!host)
1251                 return 0;
1252 
1253         pcr = host->pcr;
1254         pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1255         pcr->slots[RTSX_SD_CARD].card_event = NULL;
1256         mmc = host->mmc;
1257 
1258         mutex_lock(&host->host_mutex);
1259         if (host->mrq) {
1260                 dev_dbg(&(pdev->dev),
1261                         "%s: Controller removed during transfer\n",
1262                         mmc_hostname(mmc));
1263 
1264                 rtsx_pci_complete_unfinished_transfer(pcr);
1265 
1266                 host->mrq->cmd->error = -ENOMEDIUM;
1267                 if (host->mrq->stop)
1268                         host->mrq->stop->error = -ENOMEDIUM;
1269                 mmc_request_done(mmc, host->mrq);
1270         }
1271         mutex_unlock(&host->host_mutex);
1272 
1273         mmc_remove_host(mmc);
1274         host->eject = true;
1275 
1276         mmc_free_host(mmc);
1277 
1278         dev_dbg(&(pdev->dev),
1279                 ": Realtek PCI-E SDMMC controller has been removed\n");
1280 
1281         return 0;
1282 }
1283 
1284 static struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1285         {
1286                 .name = DRV_NAME_RTSX_PCI_SDMMC,
1287         }, {
1288                 /* sentinel */
1289         }
1290 };
1291 MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1292 
1293 static struct platform_driver rtsx_pci_sdmmc_driver = {
1294         .probe          = rtsx_pci_sdmmc_drv_probe,
1295         .remove         = rtsx_pci_sdmmc_drv_remove,
1296         .id_table       = rtsx_pci_sdmmc_ids,
1297         .driver         = {
1298                 .owner  = THIS_MODULE,
1299                 .name   = DRV_NAME_RTSX_PCI_SDMMC,
1300         },
1301 };
1302 module_platform_driver(rtsx_pci_sdmmc_driver);
1303 
1304 MODULE_LICENSE("GPL");
1305 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1306 MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");
1307 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us