Version:  2.0.40 2.2.26 2.4.37 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0

Linux/drivers/mmc/host/omap_hsmmc.c

  1 /*
  2  * drivers/mmc/host/omap_hsmmc.c
  3  *
  4  * Driver for OMAP2430/3430 MMC controller.
  5  *
  6  * Copyright (C) 2007 Texas Instruments.
  7  *
  8  * Authors:
  9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
 10  *      Madhusudhan             <madhu.cr@ti.com>
 11  *      Mohit Jalori            <mjalori@ti.com>
 12  *
 13  * This file is licensed under the terms of the GNU General Public License
 14  * version 2. This program is licensed "as is" without any warranty of any
 15  * kind, whether express or implied.
 16  */
 17 
 18 #include <linux/module.h>
 19 #include <linux/init.h>
 20 #include <linux/kernel.h>
 21 #include <linux/debugfs.h>
 22 #include <linux/dmaengine.h>
 23 #include <linux/seq_file.h>
 24 #include <linux/sizes.h>
 25 #include <linux/interrupt.h>
 26 #include <linux/delay.h>
 27 #include <linux/dma-mapping.h>
 28 #include <linux/platform_device.h>
 29 #include <linux/timer.h>
 30 #include <linux/clk.h>
 31 #include <linux/of.h>
 32 #include <linux/of_irq.h>
 33 #include <linux/of_gpio.h>
 34 #include <linux/of_device.h>
 35 #include <linux/omap-dmaengine.h>
 36 #include <linux/mmc/host.h>
 37 #include <linux/mmc/core.h>
 38 #include <linux/mmc/mmc.h>
 39 #include <linux/mmc/slot-gpio.h>
 40 #include <linux/io.h>
 41 #include <linux/irq.h>
 42 #include <linux/gpio.h>
 43 #include <linux/regulator/consumer.h>
 44 #include <linux/pinctrl/consumer.h>
 45 #include <linux/pm_runtime.h>
 46 #include <linux/platform_data/hsmmc-omap.h>
 47 
 48 /* OMAP HSMMC Host Controller Registers */
 49 #define OMAP_HSMMC_SYSSTATUS    0x0014
 50 #define OMAP_HSMMC_CON          0x002C
 51 #define OMAP_HSMMC_SDMASA       0x0100
 52 #define OMAP_HSMMC_BLK          0x0104
 53 #define OMAP_HSMMC_ARG          0x0108
 54 #define OMAP_HSMMC_CMD          0x010C
 55 #define OMAP_HSMMC_RSP10        0x0110
 56 #define OMAP_HSMMC_RSP32        0x0114
 57 #define OMAP_HSMMC_RSP54        0x0118
 58 #define OMAP_HSMMC_RSP76        0x011C
 59 #define OMAP_HSMMC_DATA         0x0120
 60 #define OMAP_HSMMC_PSTATE       0x0124
 61 #define OMAP_HSMMC_HCTL         0x0128
 62 #define OMAP_HSMMC_SYSCTL       0x012C
 63 #define OMAP_HSMMC_STAT         0x0130
 64 #define OMAP_HSMMC_IE           0x0134
 65 #define OMAP_HSMMC_ISE          0x0138
 66 #define OMAP_HSMMC_AC12         0x013C
 67 #define OMAP_HSMMC_CAPA         0x0140
 68 
 69 #define VS18                    (1 << 26)
 70 #define VS30                    (1 << 25)
 71 #define HSS                     (1 << 21)
 72 #define SDVS18                  (0x5 << 9)
 73 #define SDVS30                  (0x6 << 9)
 74 #define SDVS33                  (0x7 << 9)
 75 #define SDVS_MASK               0x00000E00
 76 #define SDVSCLR                 0xFFFFF1FF
 77 #define SDVSDET                 0x00000400
 78 #define AUTOIDLE                0x1
 79 #define SDBP                    (1 << 8)
 80 #define DTO                     0xe
 81 #define ICE                     0x1
 82 #define ICS                     0x2
 83 #define CEN                     (1 << 2)
 84 #define CLKD_MAX                0x3FF           /* max clock divisor: 1023 */
 85 #define CLKD_MASK               0x0000FFC0
 86 #define CLKD_SHIFT              6
 87 #define DTO_MASK                0x000F0000
 88 #define DTO_SHIFT               16
 89 #define INIT_STREAM             (1 << 1)
 90 #define ACEN_ACMD23             (2 << 2)
 91 #define DP_SELECT               (1 << 21)
 92 #define DDIR                    (1 << 4)
 93 #define DMAE                    0x1
 94 #define MSBS                    (1 << 5)
 95 #define BCE                     (1 << 1)
 96 #define FOUR_BIT                (1 << 1)
 97 #define HSPE                    (1 << 2)
 98 #define IWE                     (1 << 24)
 99 #define DDR                     (1 << 19)
100 #define CLKEXTFREE              (1 << 16)
101 #define CTPL                    (1 << 11)
102 #define DW8                     (1 << 5)
103 #define OD                      0x1
104 #define STAT_CLEAR              0xFFFFFFFF
105 #define INIT_STREAM_CMD         0x00000000
106 #define DUAL_VOLT_OCR_BIT       7
107 #define SRC                     (1 << 25)
108 #define SRD                     (1 << 26)
109 #define SOFTRESET               (1 << 1)
110 
111 /* PSTATE */
112 #define DLEV_DAT(x)             (1 << (20 + (x)))
113 
114 /* Interrupt masks for IE and ISE register */
115 #define CC_EN                   (1 << 0)
116 #define TC_EN                   (1 << 1)
117 #define BWR_EN                  (1 << 4)
118 #define BRR_EN                  (1 << 5)
119 #define CIRQ_EN                 (1 << 8)
120 #define ERR_EN                  (1 << 15)
121 #define CTO_EN                  (1 << 16)
122 #define CCRC_EN                 (1 << 17)
123 #define CEB_EN                  (1 << 18)
124 #define CIE_EN                  (1 << 19)
125 #define DTO_EN                  (1 << 20)
126 #define DCRC_EN                 (1 << 21)
127 #define DEB_EN                  (1 << 22)
128 #define ACE_EN                  (1 << 24)
129 #define CERR_EN                 (1 << 28)
130 #define BADA_EN                 (1 << 29)
131 
132 #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
133                 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
134                 BRR_EN | BWR_EN | TC_EN | CC_EN)
135 
136 #define CNI     (1 << 7)
137 #define ACIE    (1 << 4)
138 #define ACEB    (1 << 3)
139 #define ACCE    (1 << 2)
140 #define ACTO    (1 << 1)
141 #define ACNE    (1 << 0)
142 
143 #define MMC_AUTOSUSPEND_DELAY   100
144 #define MMC_TIMEOUT_MS          20              /* 20 mSec */
145 #define MMC_TIMEOUT_US          20000           /* 20000 micro Sec */
146 #define OMAP_MMC_MIN_CLOCK      400000
147 #define OMAP_MMC_MAX_CLOCK      52000000
148 #define DRIVER_NAME             "omap_hsmmc"
149 
150 #define VDD_1V8                 1800000         /* 180000 uV */
151 #define VDD_3V0                 3000000         /* 300000 uV */
152 #define VDD_165_195             (ffs(MMC_VDD_165_195) - 1)
153 
154 /*
155  * One controller can have multiple slots, like on some omap boards using
156  * omap.c controller driver. Luckily this is not currently done on any known
157  * omap_hsmmc.c device.
158  */
159 #define mmc_pdata(host)         host->pdata
160 
161 /*
162  * MMC Host controller read/write API's
163  */
164 #define OMAP_HSMMC_READ(base, reg)      \
165         __raw_readl((base) + OMAP_HSMMC_##reg)
166 
167 #define OMAP_HSMMC_WRITE(base, reg, val) \
168         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
169 
170 struct omap_hsmmc_next {
171         unsigned int    dma_len;
172         s32             cookie;
173 };
174 
175 struct omap_hsmmc_host {
176         struct  device          *dev;
177         struct  mmc_host        *mmc;
178         struct  mmc_request     *mrq;
179         struct  mmc_command     *cmd;
180         struct  mmc_data        *data;
181         struct  clk             *fclk;
182         struct  clk             *dbclk;
183         /*
184          * vcc == configured supply
185          * vcc_aux == optional
186          *   -  MMC1, supply for DAT4..DAT7
187          *   -  MMC2/MMC2, external level shifter voltage supply, for
188          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
189          */
190         struct  regulator       *vcc;
191         struct  regulator       *vcc_aux;
192         struct  regulator       *pbias;
193         bool                    pbias_enabled;
194         void    __iomem         *base;
195         resource_size_t         mapbase;
196         spinlock_t              irq_lock; /* Prevent races with irq handler */
197         unsigned int            dma_len;
198         unsigned int            dma_sg_idx;
199         unsigned char           bus_mode;
200         unsigned char           power_mode;
201         int                     suspended;
202         u32                     con;
203         u32                     hctl;
204         u32                     sysctl;
205         u32                     capa;
206         int                     irq;
207         int                     wake_irq;
208         int                     use_dma, dma_ch;
209         struct dma_chan         *tx_chan;
210         struct dma_chan         *rx_chan;
211         int                     response_busy;
212         int                     context_loss;
213         int                     protect_card;
214         int                     reqs_blocked;
215         int                     use_reg;
216         int                     req_in_progress;
217         unsigned long           clk_rate;
218         unsigned int            flags;
219 #define AUTO_CMD23              (1 << 0)        /* Auto CMD23 support */
220 #define HSMMC_SDIO_IRQ_ENABLED  (1 << 1)        /* SDIO irq enabled */
221 #define HSMMC_WAKE_IRQ_ENABLED  (1 << 2)
222         struct omap_hsmmc_next  next_data;
223         struct  omap_hsmmc_platform_data        *pdata;
224 
225         /* To handle board related suspend/resume functionality for MMC */
226         int (*suspend)(struct device *dev);
227         int (*resume)(struct device *dev);
228 
229         /* return MMC cover switch state, can be NULL if not supported.
230          *
231          * possible return values:
232          *   0 - closed
233          *   1 - open
234          */
235         int (*get_cover_state)(struct device *dev);
236 
237         /* Card detection IRQs */
238         int card_detect_irq;
239 
240         int (*card_detect)(struct device *dev);
241         int (*get_ro)(struct device *dev);
242 
243 };
244 
245 struct omap_mmc_of_data {
246         u32 reg_offset;
247         u8 controller_flags;
248 };
249 
250 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
251 
252 static int omap_hsmmc_card_detect(struct device *dev)
253 {
254         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
255 
256         return mmc_gpio_get_cd(host->mmc);
257 }
258 
259 static int omap_hsmmc_get_wp(struct device *dev)
260 {
261         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
262 
263         return mmc_gpio_get_ro(host->mmc);
264 }
265 
266 static int omap_hsmmc_get_cover_state(struct device *dev)
267 {
268         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
269 
270         return mmc_gpio_get_cd(host->mmc);
271 }
272 
273 #ifdef CONFIG_REGULATOR
274 
275 static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd)
276 {
277         struct omap_hsmmc_host *host =
278                 platform_get_drvdata(to_platform_device(dev));
279         int ret = 0;
280 
281         /*
282          * If we don't see a Vcc regulator, assume it's a fixed
283          * voltage always-on regulator.
284          */
285         if (!host->vcc)
286                 return 0;
287 
288         if (mmc_pdata(host)->before_set_reg)
289                 mmc_pdata(host)->before_set_reg(dev, power_on, vdd);
290 
291         if (host->pbias) {
292                 if (host->pbias_enabled == 1) {
293                         ret = regulator_disable(host->pbias);
294                         if (!ret)
295                                 host->pbias_enabled = 0;
296                 }
297                 regulator_set_voltage(host->pbias, VDD_3V0, VDD_3V0);
298         }
299 
300         /*
301          * Assume Vcc regulator is used only to power the card ... OMAP
302          * VDDS is used to power the pins, optionally with a transceiver to
303          * support cards using voltages other than VDDS (1.8V nominal).  When a
304          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
305          *
306          * In some cases this regulator won't support enable/disable;
307          * e.g. it's a fixed rail for a WLAN chip.
308          *
309          * In other cases vcc_aux switches interface power.  Example, for
310          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
311          * chips/cards need an interface voltage rail too.
312          */
313         if (power_on) {
314                 if (host->vcc)
315                         ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
316                 /* Enable interface voltage rail, if needed */
317                 if (ret == 0 && host->vcc_aux) {
318                         ret = regulator_enable(host->vcc_aux);
319                         if (ret < 0 && host->vcc)
320                                 ret = mmc_regulator_set_ocr(host->mmc,
321                                                         host->vcc, 0);
322                 }
323         } else {
324                 /* Shut down the rail */
325                 if (host->vcc_aux)
326                         ret = regulator_disable(host->vcc_aux);
327                 if (host->vcc) {
328                         /* Then proceed to shut down the local regulator */
329                         ret = mmc_regulator_set_ocr(host->mmc,
330                                                 host->vcc, 0);
331                 }
332         }
333 
334         if (host->pbias) {
335                 if (vdd <= VDD_165_195)
336                         ret = regulator_set_voltage(host->pbias, VDD_1V8,
337                                                                 VDD_1V8);
338                 else
339                         ret = regulator_set_voltage(host->pbias, VDD_3V0,
340                                                                 VDD_3V0);
341                 if (ret < 0)
342                         goto error_set_power;
343 
344                 if (host->pbias_enabled == 0) {
345                         ret = regulator_enable(host->pbias);
346                         if (!ret)
347                                 host->pbias_enabled = 1;
348                 }
349         }
350 
351         if (mmc_pdata(host)->after_set_reg)
352                 mmc_pdata(host)->after_set_reg(dev, power_on, vdd);
353 
354 error_set_power:
355         return ret;
356 }
357 
358 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
359 {
360         struct regulator *reg;
361         int ocr_value = 0;
362 
363         reg = devm_regulator_get(host->dev, "vmmc");
364         if (IS_ERR(reg)) {
365                 dev_err(host->dev, "unable to get vmmc regulator %ld\n",
366                         PTR_ERR(reg));
367                 return PTR_ERR(reg);
368         } else {
369                 host->vcc = reg;
370                 ocr_value = mmc_regulator_get_ocrmask(reg);
371                 if (!mmc_pdata(host)->ocr_mask) {
372                         mmc_pdata(host)->ocr_mask = ocr_value;
373                 } else {
374                         if (!(mmc_pdata(host)->ocr_mask & ocr_value)) {
375                                 dev_err(host->dev, "ocrmask %x is not supported\n",
376                                         mmc_pdata(host)->ocr_mask);
377                                 mmc_pdata(host)->ocr_mask = 0;
378                                 return -EINVAL;
379                         }
380                 }
381         }
382         mmc_pdata(host)->set_power = omap_hsmmc_set_power;
383 
384         /* Allow an aux regulator */
385         reg = devm_regulator_get_optional(host->dev, "vmmc_aux");
386         host->vcc_aux = IS_ERR(reg) ? NULL : reg;
387 
388         reg = devm_regulator_get_optional(host->dev, "pbias");
389         host->pbias = IS_ERR(reg) ? NULL : reg;
390 
391         /* For eMMC do not power off when not in sleep state */
392         if (mmc_pdata(host)->no_regulator_off_init)
393                 return 0;
394         /*
395          * To disable boot_on regulator, enable regulator
396          * to increase usecount and then disable it.
397          */
398         if ((host->vcc && regulator_is_enabled(host->vcc) > 0) ||
399             (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
400                 int vdd = ffs(mmc_pdata(host)->ocr_mask) - 1;
401 
402                 mmc_pdata(host)->set_power(host->dev, 1, vdd);
403                 mmc_pdata(host)->set_power(host->dev, 0, 0);
404         }
405 
406         return 0;
407 }
408 
409 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
410 {
411         mmc_pdata(host)->set_power = NULL;
412 }
413 
414 static inline int omap_hsmmc_have_reg(void)
415 {
416         return 1;
417 }
418 
419 #else
420 
421 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
422 {
423         return -EINVAL;
424 }
425 
426 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
427 {
428 }
429 
430 static inline int omap_hsmmc_have_reg(void)
431 {
432         return 0;
433 }
434 
435 #endif
436 
437 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id);
438 
439 static int omap_hsmmc_gpio_init(struct mmc_host *mmc,
440                                 struct omap_hsmmc_host *host,
441                                 struct omap_hsmmc_platform_data *pdata)
442 {
443         int ret;
444 
445         if (gpio_is_valid(pdata->switch_pin)) {
446                 if (pdata->cover)
447                         host->get_cover_state =
448                                 omap_hsmmc_get_cover_state;
449                 else
450                         host->card_detect = omap_hsmmc_card_detect;
451                 host->card_detect_irq =
452                                 gpio_to_irq(pdata->switch_pin);
453                 mmc_gpio_set_cd_isr(mmc, omap_hsmmc_detect);
454                 ret = mmc_gpio_request_cd(mmc, pdata->switch_pin, 0);
455                 if (ret)
456                         return ret;
457         } else {
458                 pdata->switch_pin = -EINVAL;
459         }
460 
461         if (gpio_is_valid(pdata->gpio_wp)) {
462                 host->get_ro = omap_hsmmc_get_wp;
463                 ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp);
464                 if (ret)
465                         return ret;
466         } else {
467                 pdata->gpio_wp = -EINVAL;
468         }
469 
470         return 0;
471 }
472 
473 /*
474  * Start clock to the card
475  */
476 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
477 {
478         OMAP_HSMMC_WRITE(host->base, SYSCTL,
479                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
480 }
481 
482 /*
483  * Stop clock to the card
484  */
485 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
486 {
487         OMAP_HSMMC_WRITE(host->base, SYSCTL,
488                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
489         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
490                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
491 }
492 
493 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
494                                   struct mmc_command *cmd)
495 {
496         u32 irq_mask = INT_EN_MASK;
497         unsigned long flags;
498 
499         if (host->use_dma)
500                 irq_mask &= ~(BRR_EN | BWR_EN);
501 
502         /* Disable timeout for erases */
503         if (cmd->opcode == MMC_ERASE)
504                 irq_mask &= ~DTO_EN;
505 
506         spin_lock_irqsave(&host->irq_lock, flags);
507         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
508         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
509 
510         /* latch pending CIRQ, but don't signal MMC core */
511         if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
512                 irq_mask |= CIRQ_EN;
513         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
514         spin_unlock_irqrestore(&host->irq_lock, flags);
515 }
516 
517 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
518 {
519         u32 irq_mask = 0;
520         unsigned long flags;
521 
522         spin_lock_irqsave(&host->irq_lock, flags);
523         /* no transfer running but need to keep cirq if enabled */
524         if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
525                 irq_mask |= CIRQ_EN;
526         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
527         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
528         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
529         spin_unlock_irqrestore(&host->irq_lock, flags);
530 }
531 
532 /* Calculate divisor for the given clock frequency */
533 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
534 {
535         u16 dsor = 0;
536 
537         if (ios->clock) {
538                 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
539                 if (dsor > CLKD_MAX)
540                         dsor = CLKD_MAX;
541         }
542 
543         return dsor;
544 }
545 
546 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
547 {
548         struct mmc_ios *ios = &host->mmc->ios;
549         unsigned long regval;
550         unsigned long timeout;
551         unsigned long clkdiv;
552 
553         dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
554 
555         omap_hsmmc_stop_clock(host);
556 
557         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
558         regval = regval & ~(CLKD_MASK | DTO_MASK);
559         clkdiv = calc_divisor(host, ios);
560         regval = regval | (clkdiv << 6) | (DTO << 16);
561         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
562         OMAP_HSMMC_WRITE(host->base, SYSCTL,
563                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
564 
565         /* Wait till the ICS bit is set */
566         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
567         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
568                 && time_before(jiffies, timeout))
569                 cpu_relax();
570 
571         /*
572          * Enable High-Speed Support
573          * Pre-Requisites
574          *      - Controller should support High-Speed-Enable Bit
575          *      - Controller should not be using DDR Mode
576          *      - Controller should advertise that it supports High Speed
577          *        in capabilities register
578          *      - MMC/SD clock coming out of controller > 25MHz
579          */
580         if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
581             (ios->timing != MMC_TIMING_MMC_DDR52) &&
582             (ios->timing != MMC_TIMING_UHS_DDR50) &&
583             ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
584                 regval = OMAP_HSMMC_READ(host->base, HCTL);
585                 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
586                         regval |= HSPE;
587                 else
588                         regval &= ~HSPE;
589 
590                 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
591         }
592 
593         omap_hsmmc_start_clock(host);
594 }
595 
596 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
597 {
598         struct mmc_ios *ios = &host->mmc->ios;
599         u32 con;
600 
601         con = OMAP_HSMMC_READ(host->base, CON);
602         if (ios->timing == MMC_TIMING_MMC_DDR52 ||
603             ios->timing == MMC_TIMING_UHS_DDR50)
604                 con |= DDR;     /* configure in DDR mode */
605         else
606                 con &= ~DDR;
607         switch (ios->bus_width) {
608         case MMC_BUS_WIDTH_8:
609                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
610                 break;
611         case MMC_BUS_WIDTH_4:
612                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
613                 OMAP_HSMMC_WRITE(host->base, HCTL,
614                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
615                 break;
616         case MMC_BUS_WIDTH_1:
617                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
618                 OMAP_HSMMC_WRITE(host->base, HCTL,
619                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
620                 break;
621         }
622 }
623 
624 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
625 {
626         struct mmc_ios *ios = &host->mmc->ios;
627         u32 con;
628 
629         con = OMAP_HSMMC_READ(host->base, CON);
630         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
631                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
632         else
633                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
634 }
635 
636 #ifdef CONFIG_PM
637 
638 /*
639  * Restore the MMC host context, if it was lost as result of a
640  * power state change.
641  */
642 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
643 {
644         struct mmc_ios *ios = &host->mmc->ios;
645         u32 hctl, capa;
646         unsigned long timeout;
647 
648         if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
649             host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
650             host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
651             host->capa == OMAP_HSMMC_READ(host->base, CAPA))
652                 return 0;
653 
654         host->context_loss++;
655 
656         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
657                 if (host->power_mode != MMC_POWER_OFF &&
658                     (1 << ios->vdd) <= MMC_VDD_23_24)
659                         hctl = SDVS18;
660                 else
661                         hctl = SDVS30;
662                 capa = VS30 | VS18;
663         } else {
664                 hctl = SDVS18;
665                 capa = VS18;
666         }
667 
668         if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
669                 hctl |= IWE;
670 
671         OMAP_HSMMC_WRITE(host->base, HCTL,
672                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
673 
674         OMAP_HSMMC_WRITE(host->base, CAPA,
675                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
676 
677         OMAP_HSMMC_WRITE(host->base, HCTL,
678                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
679 
680         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
681         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
682                 && time_before(jiffies, timeout))
683                 ;
684 
685         OMAP_HSMMC_WRITE(host->base, ISE, 0);
686         OMAP_HSMMC_WRITE(host->base, IE, 0);
687         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
688 
689         /* Do not initialize card-specific things if the power is off */
690         if (host->power_mode == MMC_POWER_OFF)
691                 goto out;
692 
693         omap_hsmmc_set_bus_width(host);
694 
695         omap_hsmmc_set_clock(host);
696 
697         omap_hsmmc_set_bus_mode(host);
698 
699 out:
700         dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
701                 host->context_loss);
702         return 0;
703 }
704 
705 /*
706  * Save the MMC host context (store the number of power state changes so far).
707  */
708 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
709 {
710         host->con =  OMAP_HSMMC_READ(host->base, CON);
711         host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
712         host->sysctl =  OMAP_HSMMC_READ(host->base, SYSCTL);
713         host->capa = OMAP_HSMMC_READ(host->base, CAPA);
714 }
715 
716 #else
717 
718 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
719 {
720         return 0;
721 }
722 
723 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
724 {
725 }
726 
727 #endif
728 
729 /*
730  * Send init stream sequence to card
731  * before sending IDLE command
732  */
733 static void send_init_stream(struct omap_hsmmc_host *host)
734 {
735         int reg = 0;
736         unsigned long timeout;
737 
738         if (host->protect_card)
739                 return;
740 
741         disable_irq(host->irq);
742 
743         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
744         OMAP_HSMMC_WRITE(host->base, CON,
745                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
746         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
747 
748         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
749         while ((reg != CC_EN) && time_before(jiffies, timeout))
750                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
751 
752         OMAP_HSMMC_WRITE(host->base, CON,
753                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
754 
755         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
756         OMAP_HSMMC_READ(host->base, STAT);
757 
758         enable_irq(host->irq);
759 }
760 
761 static inline
762 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
763 {
764         int r = 1;
765 
766         if (host->get_cover_state)
767                 r = host->get_cover_state(host->dev);
768         return r;
769 }
770 
771 static ssize_t
772 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
773                            char *buf)
774 {
775         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
776         struct omap_hsmmc_host *host = mmc_priv(mmc);
777 
778         return sprintf(buf, "%s\n",
779                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
780 }
781 
782 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
783 
784 static ssize_t
785 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
786                         char *buf)
787 {
788         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
789         struct omap_hsmmc_host *host = mmc_priv(mmc);
790 
791         return sprintf(buf, "%s\n", mmc_pdata(host)->name);
792 }
793 
794 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
795 
796 /*
797  * Configure the response type and send the cmd.
798  */
799 static void
800 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
801         struct mmc_data *data)
802 {
803         int cmdreg = 0, resptype = 0, cmdtype = 0;
804 
805         dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
806                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
807         host->cmd = cmd;
808 
809         omap_hsmmc_enable_irq(host, cmd);
810 
811         host->response_busy = 0;
812         if (cmd->flags & MMC_RSP_PRESENT) {
813                 if (cmd->flags & MMC_RSP_136)
814                         resptype = 1;
815                 else if (cmd->flags & MMC_RSP_BUSY) {
816                         resptype = 3;
817                         host->response_busy = 1;
818                 } else
819                         resptype = 2;
820         }
821 
822         /*
823          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
824          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
825          * a val of 0x3, rest 0x0.
826          */
827         if (cmd == host->mrq->stop)
828                 cmdtype = 0x3;
829 
830         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
831 
832         if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
833             host->mrq->sbc) {
834                 cmdreg |= ACEN_ACMD23;
835                 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
836         }
837         if (data) {
838                 cmdreg |= DP_SELECT | MSBS | BCE;
839                 if (data->flags & MMC_DATA_READ)
840                         cmdreg |= DDIR;
841                 else
842                         cmdreg &= ~(DDIR);
843         }
844 
845         if (host->use_dma)
846                 cmdreg |= DMAE;
847 
848         host->req_in_progress = 1;
849 
850         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
851         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
852 }
853 
854 static int
855 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
856 {
857         if (data->flags & MMC_DATA_WRITE)
858                 return DMA_TO_DEVICE;
859         else
860                 return DMA_FROM_DEVICE;
861 }
862 
863 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
864         struct mmc_data *data)
865 {
866         return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
867 }
868 
869 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
870 {
871         int dma_ch;
872         unsigned long flags;
873 
874         spin_lock_irqsave(&host->irq_lock, flags);
875         host->req_in_progress = 0;
876         dma_ch = host->dma_ch;
877         spin_unlock_irqrestore(&host->irq_lock, flags);
878 
879         omap_hsmmc_disable_irq(host);
880         /* Do not complete the request if DMA is still in progress */
881         if (mrq->data && host->use_dma && dma_ch != -1)
882                 return;
883         host->mrq = NULL;
884         mmc_request_done(host->mmc, mrq);
885 }
886 
887 /*
888  * Notify the transfer complete to MMC core
889  */
890 static void
891 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
892 {
893         if (!data) {
894                 struct mmc_request *mrq = host->mrq;
895 
896                 /* TC before CC from CMD6 - don't know why, but it happens */
897                 if (host->cmd && host->cmd->opcode == 6 &&
898                     host->response_busy) {
899                         host->response_busy = 0;
900                         return;
901                 }
902 
903                 omap_hsmmc_request_done(host, mrq);
904                 return;
905         }
906 
907         host->data = NULL;
908 
909         if (!data->error)
910                 data->bytes_xfered += data->blocks * (data->blksz);
911         else
912                 data->bytes_xfered = 0;
913 
914         if (data->stop && (data->error || !host->mrq->sbc))
915                 omap_hsmmc_start_command(host, data->stop, NULL);
916         else
917                 omap_hsmmc_request_done(host, data->mrq);
918 }
919 
920 /*
921  * Notify the core about command completion
922  */
923 static void
924 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
925 {
926         if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
927             !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
928                 host->cmd = NULL;
929                 omap_hsmmc_start_dma_transfer(host);
930                 omap_hsmmc_start_command(host, host->mrq->cmd,
931                                                 host->mrq->data);
932                 return;
933         }
934 
935         host->cmd = NULL;
936 
937         if (cmd->flags & MMC_RSP_PRESENT) {
938                 if (cmd->flags & MMC_RSP_136) {
939                         /* response type 2 */
940                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
941                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
942                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
943                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
944                 } else {
945                         /* response types 1, 1b, 3, 4, 5, 6 */
946                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
947                 }
948         }
949         if ((host->data == NULL && !host->response_busy) || cmd->error)
950                 omap_hsmmc_request_done(host, host->mrq);
951 }
952 
953 /*
954  * DMA clean up for command errors
955  */
956 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
957 {
958         int dma_ch;
959         unsigned long flags;
960 
961         host->data->error = errno;
962 
963         spin_lock_irqsave(&host->irq_lock, flags);
964         dma_ch = host->dma_ch;
965         host->dma_ch = -1;
966         spin_unlock_irqrestore(&host->irq_lock, flags);
967 
968         if (host->use_dma && dma_ch != -1) {
969                 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
970 
971                 dmaengine_terminate_all(chan);
972                 dma_unmap_sg(chan->device->dev,
973                         host->data->sg, host->data->sg_len,
974                         omap_hsmmc_get_dma_dir(host, host->data));
975 
976                 host->data->host_cookie = 0;
977         }
978         host->data = NULL;
979 }
980 
981 /*
982  * Readable error output
983  */
984 #ifdef CONFIG_MMC_DEBUG
985 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
986 {
987         /* --- means reserved bit without definition at documentation */
988         static const char *omap_hsmmc_status_bits[] = {
989                 "CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
990                 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
991                 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
992                 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
993         };
994         char res[256];
995         char *buf = res;
996         int len, i;
997 
998         len = sprintf(buf, "MMC IRQ 0x%x :", status);
999         buf += len;
1000 
1001         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1002                 if (status & (1 << i)) {
1003                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1004                         buf += len;
1005                 }
1006 
1007         dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
1008 }
1009 #else
1010 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1011                                              u32 status)
1012 {
1013 }
1014 #endif  /* CONFIG_MMC_DEBUG */
1015 
1016 /*
1017  * MMC controller internal state machines reset
1018  *
1019  * Used to reset command or data internal state machines, using respectively
1020  *  SRC or SRD bit of SYSCTL register
1021  * Can be called from interrupt context
1022  */
1023 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1024                                                    unsigned long bit)
1025 {
1026         unsigned long i = 0;
1027         unsigned long limit = MMC_TIMEOUT_US;
1028 
1029         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1030                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1031 
1032         /*
1033          * OMAP4 ES2 and greater has an updated reset logic.
1034          * Monitor a 0->1 transition first
1035          */
1036         if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
1037                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1038                                         && (i++ < limit))
1039                         udelay(1);
1040         }
1041         i = 0;
1042 
1043         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1044                 (i++ < limit))
1045                 udelay(1);
1046 
1047         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1048                 dev_err(mmc_dev(host->mmc),
1049                         "Timeout waiting on controller reset in %s\n",
1050                         __func__);
1051 }
1052 
1053 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1054                                         int err, int end_cmd)
1055 {
1056         if (end_cmd) {
1057                 omap_hsmmc_reset_controller_fsm(host, SRC);
1058                 if (host->cmd)
1059                         host->cmd->error = err;
1060         }
1061 
1062         if (host->data) {
1063                 omap_hsmmc_reset_controller_fsm(host, SRD);
1064                 omap_hsmmc_dma_cleanup(host, err);
1065         } else if (host->mrq && host->mrq->cmd)
1066                 host->mrq->cmd->error = err;
1067 }
1068 
1069 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1070 {
1071         struct mmc_data *data;
1072         int end_cmd = 0, end_trans = 0;
1073         int error = 0;
1074 
1075         data = host->data;
1076         dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1077 
1078         if (status & ERR_EN) {
1079                 omap_hsmmc_dbg_report_irq(host, status);
1080 
1081                 if (status & (CTO_EN | CCRC_EN))
1082                         end_cmd = 1;
1083                 if (status & (CTO_EN | DTO_EN))
1084                         hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1085                 else if (status & (CCRC_EN | DCRC_EN))
1086                         hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1087 
1088                 if (status & ACE_EN) {
1089                         u32 ac12;
1090                         ac12 = OMAP_HSMMC_READ(host->base, AC12);
1091                         if (!(ac12 & ACNE) && host->mrq->sbc) {
1092                                 end_cmd = 1;
1093                                 if (ac12 & ACTO)
1094                                         error =  -ETIMEDOUT;
1095                                 else if (ac12 & (ACCE | ACEB | ACIE))
1096                                         error = -EILSEQ;
1097                                 host->mrq->sbc->error = error;
1098                                 hsmmc_command_incomplete(host, error, end_cmd);
1099                         }
1100                         dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1101                 }
1102                 if (host->data || host->response_busy) {
1103                         end_trans = !end_cmd;
1104                         host->response_busy = 0;
1105                 }
1106         }
1107 
1108         OMAP_HSMMC_WRITE(host->base, STAT, status);
1109         if (end_cmd || ((status & CC_EN) && host->cmd))
1110                 omap_hsmmc_cmd_done(host, host->cmd);
1111         if ((end_trans || (status & TC_EN)) && host->mrq)
1112                 omap_hsmmc_xfer_done(host, data);
1113 }
1114 
1115 /*
1116  * MMC controller IRQ handler
1117  */
1118 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1119 {
1120         struct omap_hsmmc_host *host = dev_id;
1121         int status;
1122 
1123         status = OMAP_HSMMC_READ(host->base, STAT);
1124         while (status & (INT_EN_MASK | CIRQ_EN)) {
1125                 if (host->req_in_progress)
1126                         omap_hsmmc_do_irq(host, status);
1127 
1128                 if (status & CIRQ_EN)
1129                         mmc_signal_sdio_irq(host->mmc);
1130 
1131                 /* Flush posted write */
1132                 status = OMAP_HSMMC_READ(host->base, STAT);
1133         }
1134 
1135         return IRQ_HANDLED;
1136 }
1137 
1138 static irqreturn_t omap_hsmmc_wake_irq(int irq, void *dev_id)
1139 {
1140         struct omap_hsmmc_host *host = dev_id;
1141 
1142         /* cirq is level triggered, disable to avoid infinite loop */
1143         spin_lock(&host->irq_lock);
1144         if (host->flags & HSMMC_WAKE_IRQ_ENABLED) {
1145                 disable_irq_nosync(host->wake_irq);
1146                 host->flags &= ~HSMMC_WAKE_IRQ_ENABLED;
1147         }
1148         spin_unlock(&host->irq_lock);
1149         pm_request_resume(host->dev); /* no use counter */
1150 
1151         return IRQ_HANDLED;
1152 }
1153 
1154 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1155 {
1156         unsigned long i;
1157 
1158         OMAP_HSMMC_WRITE(host->base, HCTL,
1159                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1160         for (i = 0; i < loops_per_jiffy; i++) {
1161                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1162                         break;
1163                 cpu_relax();
1164         }
1165 }
1166 
1167 /*
1168  * Switch MMC interface voltage ... only relevant for MMC1.
1169  *
1170  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1171  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1172  * Some chips, like eMMC ones, use internal transceivers.
1173  */
1174 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1175 {
1176         u32 reg_val = 0;
1177         int ret;
1178 
1179         /* Disable the clocks */
1180         pm_runtime_put_sync(host->dev);
1181         if (host->dbclk)
1182                 clk_disable_unprepare(host->dbclk);
1183 
1184         /* Turn the power off */
1185         ret = mmc_pdata(host)->set_power(host->dev, 0, 0);
1186 
1187         /* Turn the power ON with given VDD 1.8 or 3.0v */
1188         if (!ret)
1189                 ret = mmc_pdata(host)->set_power(host->dev, 1, vdd);
1190         pm_runtime_get_sync(host->dev);
1191         if (host->dbclk)
1192                 clk_prepare_enable(host->dbclk);
1193 
1194         if (ret != 0)
1195                 goto err;
1196 
1197         OMAP_HSMMC_WRITE(host->base, HCTL,
1198                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1199         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1200 
1201         /*
1202          * If a MMC dual voltage card is detected, the set_ios fn calls
1203          * this fn with VDD bit set for 1.8V. Upon card removal from the
1204          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1205          *
1206          * Cope with a bit of slop in the range ... per data sheets:
1207          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1208          *    but recommended values are 1.71V to 1.89V
1209          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1210          *    but recommended values are 2.7V to 3.3V
1211          *
1212          * Board setup code shouldn't permit anything very out-of-range.
1213          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1214          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1215          */
1216         if ((1 << vdd) <= MMC_VDD_23_24)
1217                 reg_val |= SDVS18;
1218         else
1219                 reg_val |= SDVS30;
1220 
1221         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1222         set_sd_bus_power(host);
1223 
1224         return 0;
1225 err:
1226         dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1227         return ret;
1228 }
1229 
1230 /* Protect the card while the cover is open */
1231 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1232 {
1233         if (!host->get_cover_state)
1234                 return;
1235 
1236         host->reqs_blocked = 0;
1237         if (host->get_cover_state(host->dev)) {
1238                 if (host->protect_card) {
1239                         dev_info(host->dev, "%s: cover is closed, "
1240                                          "card is now accessible\n",
1241                                          mmc_hostname(host->mmc));
1242                         host->protect_card = 0;
1243                 }
1244         } else {
1245                 if (!host->protect_card) {
1246                         dev_info(host->dev, "%s: cover is open, "
1247                                          "card is now inaccessible\n",
1248                                          mmc_hostname(host->mmc));
1249                         host->protect_card = 1;
1250                 }
1251         }
1252 }
1253 
1254 /*
1255  * irq handler to notify the core about card insertion/removal
1256  */
1257 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1258 {
1259         struct omap_hsmmc_host *host = dev_id;
1260         int carddetect;
1261 
1262         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1263 
1264         if (host->card_detect)
1265                 carddetect = host->card_detect(host->dev);
1266         else {
1267                 omap_hsmmc_protect_card(host);
1268                 carddetect = -ENOSYS;
1269         }
1270 
1271         if (carddetect)
1272                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1273         else
1274                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1275         return IRQ_HANDLED;
1276 }
1277 
1278 static void omap_hsmmc_dma_callback(void *param)
1279 {
1280         struct omap_hsmmc_host *host = param;
1281         struct dma_chan *chan;
1282         struct mmc_data *data;
1283         int req_in_progress;
1284 
1285         spin_lock_irq(&host->irq_lock);
1286         if (host->dma_ch < 0) {
1287                 spin_unlock_irq(&host->irq_lock);
1288                 return;
1289         }
1290 
1291         data = host->mrq->data;
1292         chan = omap_hsmmc_get_dma_chan(host, data);
1293         if (!data->host_cookie)
1294                 dma_unmap_sg(chan->device->dev,
1295                              data->sg, data->sg_len,
1296                              omap_hsmmc_get_dma_dir(host, data));
1297 
1298         req_in_progress = host->req_in_progress;
1299         host->dma_ch = -1;
1300         spin_unlock_irq(&host->irq_lock);
1301 
1302         /* If DMA has finished after TC, complete the request */
1303         if (!req_in_progress) {
1304                 struct mmc_request *mrq = host->mrq;
1305 
1306                 host->mrq = NULL;
1307                 mmc_request_done(host->mmc, mrq);
1308         }
1309 }
1310 
1311 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1312                                        struct mmc_data *data,
1313                                        struct omap_hsmmc_next *next,
1314                                        struct dma_chan *chan)
1315 {
1316         int dma_len;
1317 
1318         if (!next && data->host_cookie &&
1319             data->host_cookie != host->next_data.cookie) {
1320                 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1321                        " host->next_data.cookie %d\n",
1322                        __func__, data->host_cookie, host->next_data.cookie);
1323                 data->host_cookie = 0;
1324         }
1325 
1326         /* Check if next job is already prepared */
1327         if (next || data->host_cookie != host->next_data.cookie) {
1328                 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1329                                      omap_hsmmc_get_dma_dir(host, data));
1330 
1331         } else {
1332                 dma_len = host->next_data.dma_len;
1333                 host->next_data.dma_len = 0;
1334         }
1335 
1336 
1337         if (dma_len == 0)
1338                 return -EINVAL;
1339 
1340         if (next) {
1341                 next->dma_len = dma_len;
1342                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1343         } else
1344                 host->dma_len = dma_len;
1345 
1346         return 0;
1347 }
1348 
1349 /*
1350  * Routine to configure and start DMA for the MMC card
1351  */
1352 static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
1353                                         struct mmc_request *req)
1354 {
1355         struct dma_slave_config cfg;
1356         struct dma_async_tx_descriptor *tx;
1357         int ret = 0, i;
1358         struct mmc_data *data = req->data;
1359         struct dma_chan *chan;
1360 
1361         /* Sanity check: all the SG entries must be aligned by block size. */
1362         for (i = 0; i < data->sg_len; i++) {
1363                 struct scatterlist *sgl;
1364 
1365                 sgl = data->sg + i;
1366                 if (sgl->length % data->blksz)
1367                         return -EINVAL;
1368         }
1369         if ((data->blksz % 4) != 0)
1370                 /* REVISIT: The MMC buffer increments only when MSB is written.
1371                  * Return error for blksz which is non multiple of four.
1372                  */
1373                 return -EINVAL;
1374 
1375         BUG_ON(host->dma_ch != -1);
1376 
1377         chan = omap_hsmmc_get_dma_chan(host, data);
1378 
1379         cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1380         cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1381         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1382         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1383         cfg.src_maxburst = data->blksz / 4;
1384         cfg.dst_maxburst = data->blksz / 4;
1385 
1386         ret = dmaengine_slave_config(chan, &cfg);
1387         if (ret)
1388                 return ret;
1389 
1390         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1391         if (ret)
1392                 return ret;
1393 
1394         tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1395                 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1396                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1397         if (!tx) {
1398                 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1399                 /* FIXME: cleanup */
1400                 return -1;
1401         }
1402 
1403         tx->callback = omap_hsmmc_dma_callback;
1404         tx->callback_param = host;
1405 
1406         /* Does not fail */
1407         dmaengine_submit(tx);
1408 
1409         host->dma_ch = 1;
1410 
1411         return 0;
1412 }
1413 
1414 static void set_data_timeout(struct omap_hsmmc_host *host,
1415                              unsigned int timeout_ns,
1416                              unsigned int timeout_clks)
1417 {
1418         unsigned int timeout, cycle_ns;
1419         uint32_t reg, clkd, dto = 0;
1420 
1421         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1422         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1423         if (clkd == 0)
1424                 clkd = 1;
1425 
1426         cycle_ns = 1000000000 / (host->clk_rate / clkd);
1427         timeout = timeout_ns / cycle_ns;
1428         timeout += timeout_clks;
1429         if (timeout) {
1430                 while ((timeout & 0x80000000) == 0) {
1431                         dto += 1;
1432                         timeout <<= 1;
1433                 }
1434                 dto = 31 - dto;
1435                 timeout <<= 1;
1436                 if (timeout && dto)
1437                         dto += 1;
1438                 if (dto >= 13)
1439                         dto -= 13;
1440                 else
1441                         dto = 0;
1442                 if (dto > 14)
1443                         dto = 14;
1444         }
1445 
1446         reg &= ~DTO_MASK;
1447         reg |= dto << DTO_SHIFT;
1448         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1449 }
1450 
1451 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1452 {
1453         struct mmc_request *req = host->mrq;
1454         struct dma_chan *chan;
1455 
1456         if (!req->data)
1457                 return;
1458         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1459                                 | (req->data->blocks << 16));
1460         set_data_timeout(host, req->data->timeout_ns,
1461                                 req->data->timeout_clks);
1462         chan = omap_hsmmc_get_dma_chan(host, req->data);
1463         dma_async_issue_pending(chan);
1464 }
1465 
1466 /*
1467  * Configure block length for MMC/SD cards and initiate the transfer.
1468  */
1469 static int
1470 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1471 {
1472         int ret;
1473         host->data = req->data;
1474 
1475         if (req->data == NULL) {
1476                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1477                 /*
1478                  * Set an arbitrary 100ms data timeout for commands with
1479                  * busy signal.
1480                  */
1481                 if (req->cmd->flags & MMC_RSP_BUSY)
1482                         set_data_timeout(host, 100000000U, 0);
1483                 return 0;
1484         }
1485 
1486         if (host->use_dma) {
1487                 ret = omap_hsmmc_setup_dma_transfer(host, req);
1488                 if (ret != 0) {
1489                         dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1490                         return ret;
1491                 }
1492         }
1493         return 0;
1494 }
1495 
1496 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1497                                 int err)
1498 {
1499         struct omap_hsmmc_host *host = mmc_priv(mmc);
1500         struct mmc_data *data = mrq->data;
1501 
1502         if (host->use_dma && data->host_cookie) {
1503                 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1504 
1505                 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1506                              omap_hsmmc_get_dma_dir(host, data));
1507                 data->host_cookie = 0;
1508         }
1509 }
1510 
1511 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1512                                bool is_first_req)
1513 {
1514         struct omap_hsmmc_host *host = mmc_priv(mmc);
1515 
1516         if (mrq->data->host_cookie) {
1517                 mrq->data->host_cookie = 0;
1518                 return ;
1519         }
1520 
1521         if (host->use_dma) {
1522                 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1523 
1524                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1525                                                 &host->next_data, c))
1526                         mrq->data->host_cookie = 0;
1527         }
1528 }
1529 
1530 /*
1531  * Request function. for read/write operation
1532  */
1533 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1534 {
1535         struct omap_hsmmc_host *host = mmc_priv(mmc);
1536         int err;
1537 
1538         BUG_ON(host->req_in_progress);
1539         BUG_ON(host->dma_ch != -1);
1540         if (host->protect_card) {
1541                 if (host->reqs_blocked < 3) {
1542                         /*
1543                          * Ensure the controller is left in a consistent
1544                          * state by resetting the command and data state
1545                          * machines.
1546                          */
1547                         omap_hsmmc_reset_controller_fsm(host, SRD);
1548                         omap_hsmmc_reset_controller_fsm(host, SRC);
1549                         host->reqs_blocked += 1;
1550                 }
1551                 req->cmd->error = -EBADF;
1552                 if (req->data)
1553                         req->data->error = -EBADF;
1554                 req->cmd->retries = 0;
1555                 mmc_request_done(mmc, req);
1556                 return;
1557         } else if (host->reqs_blocked)
1558                 host->reqs_blocked = 0;
1559         WARN_ON(host->mrq != NULL);
1560         host->mrq = req;
1561         host->clk_rate = clk_get_rate(host->fclk);
1562         err = omap_hsmmc_prepare_data(host, req);
1563         if (err) {
1564                 req->cmd->error = err;
1565                 if (req->data)
1566                         req->data->error = err;
1567                 host->mrq = NULL;
1568                 mmc_request_done(mmc, req);
1569                 return;
1570         }
1571         if (req->sbc && !(host->flags & AUTO_CMD23)) {
1572                 omap_hsmmc_start_command(host, req->sbc, NULL);
1573                 return;
1574         }
1575 
1576         omap_hsmmc_start_dma_transfer(host);
1577         omap_hsmmc_start_command(host, req->cmd, req->data);
1578 }
1579 
1580 /* Routine to configure clock values. Exposed API to core */
1581 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1582 {
1583         struct omap_hsmmc_host *host = mmc_priv(mmc);
1584         int do_send_init_stream = 0;
1585 
1586         pm_runtime_get_sync(host->dev);
1587 
1588         if (ios->power_mode != host->power_mode) {
1589                 switch (ios->power_mode) {
1590                 case MMC_POWER_OFF:
1591                         mmc_pdata(host)->set_power(host->dev, 0, 0);
1592                         break;
1593                 case MMC_POWER_UP:
1594                         mmc_pdata(host)->set_power(host->dev, 1, ios->vdd);
1595                         break;
1596                 case MMC_POWER_ON:
1597                         do_send_init_stream = 1;
1598                         break;
1599                 }
1600                 host->power_mode = ios->power_mode;
1601         }
1602 
1603         /* FIXME: set registers based only on changes to ios */
1604 
1605         omap_hsmmc_set_bus_width(host);
1606 
1607         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1608                 /* Only MMC1 can interface at 3V without some flavor
1609                  * of external transceiver; but they all handle 1.8V.
1610                  */
1611                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1612                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1613                                 /*
1614                                  * The mmc_select_voltage fn of the core does
1615                                  * not seem to set the power_mode to
1616                                  * MMC_POWER_UP upon recalculating the voltage.
1617                                  * vdd 1.8v.
1618                                  */
1619                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1620                                 dev_dbg(mmc_dev(host->mmc),
1621                                                 "Switch operation failed\n");
1622                 }
1623         }
1624 
1625         omap_hsmmc_set_clock(host);
1626 
1627         if (do_send_init_stream)
1628                 send_init_stream(host);
1629 
1630         omap_hsmmc_set_bus_mode(host);
1631 
1632         pm_runtime_put_autosuspend(host->dev);
1633 }
1634 
1635 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1636 {
1637         struct omap_hsmmc_host *host = mmc_priv(mmc);
1638 
1639         if (!host->card_detect)
1640                 return -ENOSYS;
1641         return host->card_detect(host->dev);
1642 }
1643 
1644 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1645 {
1646         struct omap_hsmmc_host *host = mmc_priv(mmc);
1647 
1648         if (!host->get_ro)
1649                 return -ENOSYS;
1650         return host->get_ro(host->dev);
1651 }
1652 
1653 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1654 {
1655         struct omap_hsmmc_host *host = mmc_priv(mmc);
1656 
1657         if (mmc_pdata(host)->init_card)
1658                 mmc_pdata(host)->init_card(card);
1659 }
1660 
1661 static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1662 {
1663         struct omap_hsmmc_host *host = mmc_priv(mmc);
1664         u32 irq_mask, con;
1665         unsigned long flags;
1666 
1667         spin_lock_irqsave(&host->irq_lock, flags);
1668 
1669         con = OMAP_HSMMC_READ(host->base, CON);
1670         irq_mask = OMAP_HSMMC_READ(host->base, ISE);
1671         if (enable) {
1672                 host->flags |= HSMMC_SDIO_IRQ_ENABLED;
1673                 irq_mask |= CIRQ_EN;
1674                 con |= CTPL | CLKEXTFREE;
1675         } else {
1676                 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
1677                 irq_mask &= ~CIRQ_EN;
1678                 con &= ~(CTPL | CLKEXTFREE);
1679         }
1680         OMAP_HSMMC_WRITE(host->base, CON, con);
1681         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
1682 
1683         /*
1684          * if enable, piggy back detection on current request
1685          * but always disable immediately
1686          */
1687         if (!host->req_in_progress || !enable)
1688                 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
1689 
1690         /* flush posted write */
1691         OMAP_HSMMC_READ(host->base, IE);
1692 
1693         spin_unlock_irqrestore(&host->irq_lock, flags);
1694 }
1695 
1696 static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
1697 {
1698         struct mmc_host *mmc = host->mmc;
1699         int ret;
1700 
1701         /*
1702          * For omaps with wake-up path, wakeirq will be irq from pinctrl and
1703          * for other omaps, wakeirq will be from GPIO (dat line remuxed to
1704          * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
1705          * with functional clock disabled.
1706          */
1707         if (!host->dev->of_node || !host->wake_irq)
1708                 return -ENODEV;
1709 
1710         /* Prevent auto-enabling of IRQ */
1711         irq_set_status_flags(host->wake_irq, IRQ_NOAUTOEN);
1712         ret = devm_request_irq(host->dev, host->wake_irq, omap_hsmmc_wake_irq,
1713                                IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1714                                mmc_hostname(mmc), host);
1715         if (ret) {
1716                 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
1717                 goto err;
1718         }
1719 
1720         /*
1721          * Some omaps don't have wake-up path from deeper idle states
1722          * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
1723          */
1724         if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
1725                 struct pinctrl *p = devm_pinctrl_get(host->dev);
1726                 if (!p) {
1727                         ret = -ENODEV;
1728                         goto err_free_irq;
1729                 }
1730                 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) {
1731                         dev_info(host->dev, "missing default pinctrl state\n");
1732                         devm_pinctrl_put(p);
1733                         ret = -EINVAL;
1734                         goto err_free_irq;
1735                 }
1736 
1737                 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
1738                         dev_info(host->dev, "missing idle pinctrl state\n");
1739                         devm_pinctrl_put(p);
1740                         ret = -EINVAL;
1741                         goto err_free_irq;
1742                 }
1743                 devm_pinctrl_put(p);
1744         }
1745 
1746         OMAP_HSMMC_WRITE(host->base, HCTL,
1747                          OMAP_HSMMC_READ(host->base, HCTL) | IWE);
1748         return 0;
1749 
1750 err_free_irq:
1751         devm_free_irq(host->dev, host->wake_irq, host);
1752 err:
1753         dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
1754         host->wake_irq = 0;
1755         return ret;
1756 }
1757 
1758 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1759 {
1760         u32 hctl, capa, value;
1761 
1762         /* Only MMC1 supports 3.0V */
1763         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1764                 hctl = SDVS30;
1765                 capa = VS30 | VS18;
1766         } else {
1767                 hctl = SDVS18;
1768                 capa = VS18;
1769         }
1770 
1771         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1772         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1773 
1774         value = OMAP_HSMMC_READ(host->base, CAPA);
1775         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1776 
1777         /* Set SD bus power bit */
1778         set_sd_bus_power(host);
1779 }
1780 
1781 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1782 {
1783         struct omap_hsmmc_host *host = mmc_priv(mmc);
1784 
1785         pm_runtime_get_sync(host->dev);
1786 
1787         return 0;
1788 }
1789 
1790 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
1791 {
1792         struct omap_hsmmc_host *host = mmc_priv(mmc);
1793 
1794         pm_runtime_mark_last_busy(host->dev);
1795         pm_runtime_put_autosuspend(host->dev);
1796 
1797         return 0;
1798 }
1799 
1800 static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
1801                                      unsigned int direction, int blk_size)
1802 {
1803         /* This controller can't do multiblock reads due to hw bugs */
1804         if (direction == MMC_DATA_READ)
1805                 return 1;
1806 
1807         return blk_size;
1808 }
1809 
1810 static struct mmc_host_ops omap_hsmmc_ops = {
1811         .enable = omap_hsmmc_enable_fclk,
1812         .disable = omap_hsmmc_disable_fclk,
1813         .post_req = omap_hsmmc_post_req,
1814         .pre_req = omap_hsmmc_pre_req,
1815         .request = omap_hsmmc_request,
1816         .set_ios = omap_hsmmc_set_ios,
1817         .get_cd = omap_hsmmc_get_cd,
1818         .get_ro = omap_hsmmc_get_ro,
1819         .init_card = omap_hsmmc_init_card,
1820         .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
1821 };
1822 
1823 #ifdef CONFIG_DEBUG_FS
1824 
1825 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1826 {
1827         struct mmc_host *mmc = s->private;
1828         struct omap_hsmmc_host *host = mmc_priv(mmc);
1829 
1830         seq_printf(s, "mmc%d:\n", mmc->index);
1831         seq_printf(s, "sdio irq mode\t%s\n",
1832                    (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
1833 
1834         if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1835                 seq_printf(s, "sdio irq \t%s\n",
1836                            (host->flags & HSMMC_SDIO_IRQ_ENABLED) ?  "enabled"
1837                            : "disabled");
1838         }
1839         seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
1840 
1841         pm_runtime_get_sync(host->dev);
1842         seq_puts(s, "\nregs:\n");
1843         seq_printf(s, "CON:\t\t0x%08x\n",
1844                         OMAP_HSMMC_READ(host->base, CON));
1845         seq_printf(s, "PSTATE:\t\t0x%08x\n",
1846                    OMAP_HSMMC_READ(host->base, PSTATE));
1847         seq_printf(s, "HCTL:\t\t0x%08x\n",
1848                         OMAP_HSMMC_READ(host->base, HCTL));
1849         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1850                         OMAP_HSMMC_READ(host->base, SYSCTL));
1851         seq_printf(s, "IE:\t\t0x%08x\n",
1852                         OMAP_HSMMC_READ(host->base, IE));
1853         seq_printf(s, "ISE:\t\t0x%08x\n",
1854                         OMAP_HSMMC_READ(host->base, ISE));
1855         seq_printf(s, "CAPA:\t\t0x%08x\n",
1856                         OMAP_HSMMC_READ(host->base, CAPA));
1857 
1858         pm_runtime_mark_last_busy(host->dev);
1859         pm_runtime_put_autosuspend(host->dev);
1860 
1861         return 0;
1862 }
1863 
1864 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1865 {
1866         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1867 }
1868 
1869 static const struct file_operations mmc_regs_fops = {
1870         .open           = omap_hsmmc_regs_open,
1871         .read           = seq_read,
1872         .llseek         = seq_lseek,
1873         .release        = single_release,
1874 };
1875 
1876 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1877 {
1878         if (mmc->debugfs_root)
1879                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1880                         mmc, &mmc_regs_fops);
1881 }
1882 
1883 #else
1884 
1885 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1886 {
1887 }
1888 
1889 #endif
1890 
1891 #ifdef CONFIG_OF
1892 static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1893         /* See 35xx errata 2.1.1.128 in SPRZ278F */
1894         .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1895 };
1896 
1897 static const struct omap_mmc_of_data omap4_mmc_of_data = {
1898         .reg_offset = 0x100,
1899 };
1900 static const struct omap_mmc_of_data am33xx_mmc_of_data = {
1901         .reg_offset = 0x100,
1902         .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
1903 };
1904 
1905 static const struct of_device_id omap_mmc_of_match[] = {
1906         {
1907                 .compatible = "ti,omap2-hsmmc",
1908         },
1909         {
1910                 .compatible = "ti,omap3-pre-es3-hsmmc",
1911                 .data = &omap3_pre_es3_mmc_of_data,
1912         },
1913         {
1914                 .compatible = "ti,omap3-hsmmc",
1915         },
1916         {
1917                 .compatible = "ti,omap4-hsmmc",
1918                 .data = &omap4_mmc_of_data,
1919         },
1920         {
1921                 .compatible = "ti,am33xx-hsmmc",
1922                 .data = &am33xx_mmc_of_data,
1923         },
1924         {},
1925 };
1926 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1927 
1928 static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1929 {
1930         struct omap_hsmmc_platform_data *pdata;
1931         struct device_node *np = dev->of_node;
1932 
1933         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1934         if (!pdata)
1935                 return ERR_PTR(-ENOMEM); /* out of memory */
1936 
1937         if (of_find_property(np, "ti,dual-volt", NULL))
1938                 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1939 
1940         pdata->switch_pin = -EINVAL;
1941         pdata->gpio_wp = -EINVAL;
1942 
1943         if (of_find_property(np, "ti,non-removable", NULL)) {
1944                 pdata->nonremovable = true;
1945                 pdata->no_regulator_off_init = true;
1946         }
1947 
1948         if (of_find_property(np, "ti,needs-special-reset", NULL))
1949                 pdata->features |= HSMMC_HAS_UPDATED_RESET;
1950 
1951         if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
1952                 pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
1953 
1954         return pdata;
1955 }
1956 #else
1957 static inline struct omap_hsmmc_platform_data
1958                         *of_get_hsmmc_pdata(struct device *dev)
1959 {
1960         return ERR_PTR(-EINVAL);
1961 }
1962 #endif
1963 
1964 static int omap_hsmmc_probe(struct platform_device *pdev)
1965 {
1966         struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
1967         struct mmc_host *mmc;
1968         struct omap_hsmmc_host *host = NULL;
1969         struct resource *res;
1970         int ret, irq;
1971         const struct of_device_id *match;
1972         dma_cap_mask_t mask;
1973         unsigned tx_req, rx_req;
1974         const struct omap_mmc_of_data *data;
1975         void __iomem *base;
1976 
1977         match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1978         if (match) {
1979                 pdata = of_get_hsmmc_pdata(&pdev->dev);
1980 
1981                 if (IS_ERR(pdata))
1982                         return PTR_ERR(pdata);
1983 
1984                 if (match->data) {
1985                         data = match->data;
1986                         pdata->reg_offset = data->reg_offset;
1987                         pdata->controller_flags |= data->controller_flags;
1988                 }
1989         }
1990 
1991         if (pdata == NULL) {
1992                 dev_err(&pdev->dev, "Platform Data is missing\n");
1993                 return -ENXIO;
1994         }
1995 
1996         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1997         irq = platform_get_irq(pdev, 0);
1998         if (res == NULL || irq < 0)
1999                 return -ENXIO;
2000 
2001         base = devm_ioremap_resource(&pdev->dev, res);
2002         if (IS_ERR(base))
2003                 return PTR_ERR(base);
2004 
2005         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
2006         if (!mmc) {
2007                 ret = -ENOMEM;
2008                 goto err;
2009         }
2010 
2011         ret = mmc_of_parse(mmc);
2012         if (ret)
2013                 goto err1;
2014 
2015         host            = mmc_priv(mmc);
2016         host->mmc       = mmc;
2017         host->pdata     = pdata;
2018         host->dev       = &pdev->dev;
2019         host->use_dma   = 1;
2020         host->dma_ch    = -1;
2021         host->irq       = irq;
2022         host->mapbase   = res->start + pdata->reg_offset;
2023         host->base      = base + pdata->reg_offset;
2024         host->power_mode = MMC_POWER_OFF;
2025         host->next_data.cookie = 1;
2026         host->pbias_enabled = 0;
2027 
2028         ret = omap_hsmmc_gpio_init(mmc, host, pdata);
2029         if (ret)
2030                 goto err_gpio;
2031 
2032         platform_set_drvdata(pdev, host);
2033 
2034         if (pdev->dev.of_node)
2035                 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
2036 
2037         mmc->ops        = &omap_hsmmc_ops;
2038 
2039         mmc->f_min = OMAP_MMC_MIN_CLOCK;
2040 
2041         if (pdata->max_freq > 0)
2042                 mmc->f_max = pdata->max_freq;
2043         else if (mmc->f_max == 0)
2044                 mmc->f_max = OMAP_MMC_MAX_CLOCK;
2045 
2046         spin_lock_init(&host->irq_lock);
2047 
2048         host->fclk = devm_clk_get(&pdev->dev, "fck");
2049         if (IS_ERR(host->fclk)) {
2050                 ret = PTR_ERR(host->fclk);
2051                 host->fclk = NULL;
2052                 goto err1;
2053         }
2054 
2055         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2056                 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
2057                 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
2058         }
2059 
2060         pm_runtime_enable(host->dev);
2061         pm_runtime_get_sync(host->dev);
2062         pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
2063         pm_runtime_use_autosuspend(host->dev);
2064 
2065         omap_hsmmc_context_save(host);
2066 
2067         host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
2068         /*
2069          * MMC can still work without debounce clock.
2070          */
2071         if (IS_ERR(host->dbclk)) {
2072                 host->dbclk = NULL;
2073         } else if (clk_prepare_enable(host->dbclk) != 0) {
2074                 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
2075                 host->dbclk = NULL;
2076         }
2077 
2078         /* Since we do only SG emulation, we can have as many segs
2079          * as we want. */
2080         mmc->max_segs = 1024;
2081 
2082         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
2083         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
2084         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2085         mmc->max_seg_size = mmc->max_req_size;
2086 
2087         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2088                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2089 
2090         mmc->caps |= mmc_pdata(host)->caps;
2091         if (mmc->caps & MMC_CAP_8_BIT_DATA)
2092                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2093 
2094         if (mmc_pdata(host)->nonremovable)
2095                 mmc->caps |= MMC_CAP_NONREMOVABLE;
2096 
2097         mmc->pm_caps |= mmc_pdata(host)->pm_caps;
2098 
2099         omap_hsmmc_conf_bus_power(host);
2100 
2101         if (!pdev->dev.of_node) {
2102                 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
2103                 if (!res) {
2104                         dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
2105                         ret = -ENXIO;
2106                         goto err_irq;
2107                 }
2108                 tx_req = res->start;
2109 
2110                 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
2111                 if (!res) {
2112                         dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
2113                         ret = -ENXIO;
2114                         goto err_irq;
2115                 }
2116                 rx_req = res->start;
2117         }
2118 
2119         dma_cap_zero(mask);
2120         dma_cap_set(DMA_SLAVE, mask);
2121 
2122         host->rx_chan =
2123                 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2124                                                  &rx_req, &pdev->dev, "rx");
2125 
2126         if (!host->rx_chan) {
2127                 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
2128                 ret = -ENXIO;
2129                 goto err_irq;
2130         }
2131 
2132         host->tx_chan =
2133                 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2134                                                  &tx_req, &pdev->dev, "tx");
2135 
2136         if (!host->tx_chan) {
2137                 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
2138                 ret = -ENXIO;
2139                 goto err_irq;
2140         }
2141 
2142         /* Request IRQ for MMC operations */
2143         ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
2144                         mmc_hostname(mmc), host);
2145         if (ret) {
2146                 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2147                 goto err_irq;
2148         }
2149 
2150         if (omap_hsmmc_have_reg() && !mmc_pdata(host)->set_power) {
2151                 ret = omap_hsmmc_reg_get(host);
2152                 if (ret)
2153                         goto err_irq;
2154                 host->use_reg = 1;
2155         }
2156 
2157         mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
2158 
2159         omap_hsmmc_disable_irq(host);
2160 
2161         /*
2162          * For now, only support SDIO interrupt if we have a separate
2163          * wake-up interrupt configured from device tree. This is because
2164          * the wake-up interrupt is needed for idle state and some
2165          * platforms need special quirks. And we don't want to add new
2166          * legacy mux platform init code callbacks any longer as we
2167          * are moving to DT based booting anyways.
2168          */
2169         ret = omap_hsmmc_configure_wake_irq(host);
2170         if (!ret)
2171                 mmc->caps |= MMC_CAP_SDIO_IRQ;
2172 
2173         omap_hsmmc_protect_card(host);
2174 
2175         mmc_add_host(mmc);
2176 
2177         if (mmc_pdata(host)->name != NULL) {
2178                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2179                 if (ret < 0)
2180                         goto err_slot_name;
2181         }
2182         if (host->card_detect_irq && host->get_cover_state) {
2183                 ret = device_create_file(&mmc->class_dev,
2184                                         &dev_attr_cover_switch);
2185                 if (ret < 0)
2186                         goto err_slot_name;
2187         }
2188 
2189         omap_hsmmc_debugfs(mmc);
2190         pm_runtime_mark_last_busy(host->dev);
2191         pm_runtime_put_autosuspend(host->dev);
2192 
2193         return 0;
2194 
2195 err_slot_name:
2196         mmc_remove_host(mmc);
2197         if (host->use_reg)
2198                 omap_hsmmc_reg_put(host);
2199 err_irq:
2200         if (host->tx_chan)
2201                 dma_release_channel(host->tx_chan);
2202         if (host->rx_chan)
2203                 dma_release_channel(host->rx_chan);
2204         pm_runtime_put_sync(host->dev);
2205         pm_runtime_disable(host->dev);
2206         if (host->dbclk)
2207                 clk_disable_unprepare(host->dbclk);
2208 err1:
2209 err_gpio:
2210         mmc_free_host(mmc);
2211 err:
2212         return ret;
2213 }
2214 
2215 static int omap_hsmmc_remove(struct platform_device *pdev)
2216 {
2217         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2218 
2219         pm_runtime_get_sync(host->dev);
2220         mmc_remove_host(host->mmc);
2221         if (host->use_reg)
2222                 omap_hsmmc_reg_put(host);
2223 
2224         if (host->tx_chan)
2225                 dma_release_channel(host->tx_chan);
2226         if (host->rx_chan)
2227                 dma_release_channel(host->rx_chan);
2228 
2229         pm_runtime_put_sync(host->dev);
2230         pm_runtime_disable(host->dev);
2231         if (host->dbclk)
2232                 clk_disable_unprepare(host->dbclk);
2233 
2234         mmc_free_host(host->mmc);
2235 
2236         return 0;
2237 }
2238 
2239 #ifdef CONFIG_PM
2240 static int omap_hsmmc_suspend(struct device *dev)
2241 {
2242         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2243 
2244         if (!host)
2245                 return 0;
2246 
2247         pm_runtime_get_sync(host->dev);
2248 
2249         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2250                 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2251                 OMAP_HSMMC_WRITE(host->base, IE, 0);
2252                 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2253                 OMAP_HSMMC_WRITE(host->base, HCTL,
2254                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2255         }
2256 
2257         /* do not wake up due to sdio irq */
2258         if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2259             !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ))
2260                 disable_irq(host->wake_irq);
2261 
2262         if (host->dbclk)
2263                 clk_disable_unprepare(host->dbclk);
2264 
2265         pm_runtime_put_sync(host->dev);
2266         return 0;
2267 }
2268 
2269 /* Routine to resume the MMC device */
2270 static int omap_hsmmc_resume(struct device *dev)
2271 {
2272         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2273 
2274         if (!host)
2275                 return 0;
2276 
2277         pm_runtime_get_sync(host->dev);
2278 
2279         if (host->dbclk)
2280                 clk_prepare_enable(host->dbclk);
2281 
2282         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2283                 omap_hsmmc_conf_bus_power(host);
2284 
2285         omap_hsmmc_protect_card(host);
2286 
2287         if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2288             !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ))
2289                 enable_irq(host->wake_irq);
2290 
2291         pm_runtime_mark_last_busy(host->dev);
2292         pm_runtime_put_autosuspend(host->dev);
2293         return 0;
2294 }
2295 
2296 #else
2297 #define omap_hsmmc_suspend      NULL
2298 #define omap_hsmmc_resume       NULL
2299 #endif
2300 
2301 static int omap_hsmmc_runtime_suspend(struct device *dev)
2302 {
2303         struct omap_hsmmc_host *host;
2304         unsigned long flags;
2305         int ret = 0;
2306 
2307         host = platform_get_drvdata(to_platform_device(dev));
2308         omap_hsmmc_context_save(host);
2309         dev_dbg(dev, "disabled\n");
2310 
2311         spin_lock_irqsave(&host->irq_lock, flags);
2312         if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2313             (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2314                 /* disable sdio irq handling to prevent race */
2315                 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2316                 OMAP_HSMMC_WRITE(host->base, IE, 0);
2317 
2318                 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2319                         /*
2320                          * dat1 line low, pending sdio irq
2321                          * race condition: possible irq handler running on
2322                          * multi-core, abort
2323                          */
2324                         dev_dbg(dev, "pending sdio irq, abort suspend\n");
2325                         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2326                         OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2327                         OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2328                         pm_runtime_mark_last_busy(dev);
2329                         ret = -EBUSY;
2330                         goto abort;
2331                 }
2332 
2333                 pinctrl_pm_select_idle_state(dev);
2334 
2335                 WARN_ON(host->flags & HSMMC_WAKE_IRQ_ENABLED);
2336                 enable_irq(host->wake_irq);
2337                 host->flags |= HSMMC_WAKE_IRQ_ENABLED;
2338         } else {
2339                 pinctrl_pm_select_idle_state(dev);
2340         }
2341 
2342 abort:
2343         spin_unlock_irqrestore(&host->irq_lock, flags);
2344         return ret;
2345 }
2346 
2347 static int omap_hsmmc_runtime_resume(struct device *dev)
2348 {
2349         struct omap_hsmmc_host *host;
2350         unsigned long flags;
2351 
2352         host = platform_get_drvdata(to_platform_device(dev));
2353         omap_hsmmc_context_restore(host);
2354         dev_dbg(dev, "enabled\n");
2355 
2356         spin_lock_irqsave(&host->irq_lock, flags);
2357         if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2358             (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2359                 /* sdio irq flag can't change while in runtime suspend */
2360                 if (host->flags & HSMMC_WAKE_IRQ_ENABLED) {
2361                         disable_irq_nosync(host->wake_irq);
2362                         host->flags &= ~HSMMC_WAKE_IRQ_ENABLED;
2363                 }
2364 
2365                 pinctrl_pm_select_default_state(host->dev);
2366 
2367                 /* irq lost, if pinmux incorrect */
2368                 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2369                 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2370                 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2371         } else {
2372                 pinctrl_pm_select_default_state(host->dev);
2373         }
2374         spin_unlock_irqrestore(&host->irq_lock, flags);
2375         return 0;
2376 }
2377 
2378 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2379         .suspend        = omap_hsmmc_suspend,
2380         .resume         = omap_hsmmc_resume,
2381         .runtime_suspend = omap_hsmmc_runtime_suspend,
2382         .runtime_resume = omap_hsmmc_runtime_resume,
2383 };
2384 
2385 static struct platform_driver omap_hsmmc_driver = {
2386         .probe          = omap_hsmmc_probe,
2387         .remove         = omap_hsmmc_remove,
2388         .driver         = {
2389                 .name = DRIVER_NAME,
2390                 .pm = &omap_hsmmc_dev_pm_ops,
2391                 .of_match_table = of_match_ptr(omap_mmc_of_match),
2392         },
2393 };
2394 
2395 module_platform_driver(omap_hsmmc_driver);
2396 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2397 MODULE_LICENSE("GPL");
2398 MODULE_ALIAS("platform:" DRIVER_NAME);
2399 MODULE_AUTHOR("Texas Instruments Inc");
2400 

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