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Linux/drivers/mmc/host/msm_sdcc.c

  1 /*
  2  *  linux/drivers/mmc/host/msm_sdcc.c - Qualcomm MSM 7X00A SDCC Driver
  3  *
  4  *  Copyright (C) 2007 Google Inc,
  5  *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
  6  *  Copyright (C) 2009, Code Aurora Forum. All Rights Reserved.
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License version 2 as
 10  * published by the Free Software Foundation.
 11  *
 12  * Based on mmci.c
 13  *
 14  * Author: San Mehat (san@android.com)
 15  *
 16  */
 17 
 18 #include <linux/module.h>
 19 #include <linux/moduleparam.h>
 20 #include <linux/init.h>
 21 #include <linux/ioport.h>
 22 #include <linux/device.h>
 23 #include <linux/interrupt.h>
 24 #include <linux/delay.h>
 25 #include <linux/err.h>
 26 #include <linux/highmem.h>
 27 #include <linux/log2.h>
 28 #include <linux/mmc/host.h>
 29 #include <linux/mmc/card.h>
 30 #include <linux/mmc/sdio.h>
 31 #include <linux/clk.h>
 32 #include <linux/scatterlist.h>
 33 #include <linux/platform_device.h>
 34 #include <linux/dma-mapping.h>
 35 #include <linux/debugfs.h>
 36 #include <linux/io.h>
 37 #include <linux/memory.h>
 38 #include <linux/gfp.h>
 39 #include <linux/gpio.h>
 40 
 41 #include <asm/cacheflush.h>
 42 #include <asm/div64.h>
 43 #include <asm/sizes.h>
 44 
 45 #include <linux/platform_data/mmc-msm_sdcc.h>
 46 #include <mach/dma.h>
 47 #include <mach/clk.h>
 48 
 49 #include "msm_sdcc.h"
 50 
 51 #define DRIVER_NAME "msm-sdcc"
 52 
 53 #define BUSCLK_PWRSAVE 1
 54 #define BUSCLK_TIMEOUT (HZ)
 55 static unsigned int msmsdcc_fmin = 144000;
 56 static unsigned int msmsdcc_fmax = 50000000;
 57 static unsigned int msmsdcc_4bit = 1;
 58 static unsigned int msmsdcc_pwrsave = 1;
 59 static unsigned int msmsdcc_piopoll = 1;
 60 static unsigned int msmsdcc_sdioirq;
 61 
 62 #define PIO_SPINMAX 30
 63 #define CMD_SPINMAX 20
 64 
 65 
 66 static inline void
 67 msmsdcc_disable_clocks(struct msmsdcc_host *host, int deferr)
 68 {
 69         WARN_ON(!host->clks_on);
 70 
 71         BUG_ON(host->curr.mrq);
 72 
 73         if (deferr) {
 74                 mod_timer(&host->busclk_timer, jiffies + BUSCLK_TIMEOUT);
 75         } else {
 76                 del_timer_sync(&host->busclk_timer);
 77                 /* Need to check clks_on again in case the busclk
 78                  * timer fired
 79                  */
 80                 if (host->clks_on) {
 81                         clk_disable(host->clk);
 82                         clk_disable(host->pclk);
 83                         host->clks_on = 0;
 84                 }
 85         }
 86 }
 87 
 88 static inline int
 89 msmsdcc_enable_clocks(struct msmsdcc_host *host)
 90 {
 91         int rc;
 92 
 93         del_timer_sync(&host->busclk_timer);
 94 
 95         if (!host->clks_on) {
 96                 rc = clk_enable(host->pclk);
 97                 if (rc)
 98                         return rc;
 99                 rc = clk_enable(host->clk);
100                 if (rc) {
101                         clk_disable(host->pclk);
102                         return rc;
103                 }
104                 udelay(1 + ((3 * USEC_PER_SEC) /
105                        (host->clk_rate ? host->clk_rate : msmsdcc_fmin)));
106                 host->clks_on = 1;
107         }
108         return 0;
109 }
110 
111 static inline unsigned int
112 msmsdcc_readl(struct msmsdcc_host *host, unsigned int reg)
113 {
114         return readl(host->base + reg);
115 }
116 
117 static inline void
118 msmsdcc_writel(struct msmsdcc_host *host, u32 data, unsigned int reg)
119 {
120         writel(data, host->base + reg);
121         /* 3 clk delay required! */
122         udelay(1 + ((3 * USEC_PER_SEC) /
123                (host->clk_rate ? host->clk_rate : msmsdcc_fmin)));
124 }
125 
126 static void
127 msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd,
128                       u32 c);
129 
130 static void msmsdcc_reset_and_restore(struct msmsdcc_host *host)
131 {
132         u32     mci_clk = 0;
133         u32     mci_mask0 = 0;
134         int     ret = 0;
135 
136         /* Save the controller state */
137         mci_clk = readl(host->base + MMCICLOCK);
138         mci_mask0 = readl(host->base + MMCIMASK0);
139 
140         /* Reset the controller */
141         ret = clk_reset(host->clk, CLK_RESET_ASSERT);
142         if (ret)
143                 pr_err("%s: Clock assert failed at %u Hz with err %d\n",
144                                 mmc_hostname(host->mmc), host->clk_rate, ret);
145 
146         ret = clk_reset(host->clk, CLK_RESET_DEASSERT);
147         if (ret)
148                 pr_err("%s: Clock deassert failed at %u Hz with err %d\n",
149                                 mmc_hostname(host->mmc), host->clk_rate, ret);
150 
151         pr_info("%s: Controller has been re-initialiazed\n",
152                         mmc_hostname(host->mmc));
153 
154         /* Restore the contoller state */
155         writel(host->pwr, host->base + MMCIPOWER);
156         writel(mci_clk, host->base + MMCICLOCK);
157         writel(mci_mask0, host->base + MMCIMASK0);
158         ret = clk_set_rate(host->clk, host->clk_rate);
159         if (ret)
160                 pr_err("%s: Failed to set clk rate %u Hz (%d)\n",
161                                 mmc_hostname(host->mmc), host->clk_rate, ret);
162 }
163 
164 static void
165 msmsdcc_request_end(struct msmsdcc_host *host, struct mmc_request *mrq)
166 {
167         BUG_ON(host->curr.data);
168 
169         host->curr.mrq = NULL;
170         host->curr.cmd = NULL;
171 
172         if (mrq->data)
173                 mrq->data->bytes_xfered = host->curr.data_xfered;
174         if (mrq->cmd->error == -ETIMEDOUT)
175                 mdelay(5);
176 
177 #if BUSCLK_PWRSAVE
178         msmsdcc_disable_clocks(host, 1);
179 #endif
180         /*
181          * Need to drop the host lock here; mmc_request_done may call
182          * back into the driver...
183          */
184         spin_unlock(&host->lock);
185         mmc_request_done(host->mmc, mrq);
186         spin_lock(&host->lock);
187 }
188 
189 static void
190 msmsdcc_stop_data(struct msmsdcc_host *host)
191 {
192         host->curr.data = NULL;
193         host->curr.got_dataend = 0;
194 }
195 
196 uint32_t msmsdcc_fifo_addr(struct msmsdcc_host *host)
197 {
198         return host->memres->start + MMCIFIFO;
199 }
200 
201 static inline void
202 msmsdcc_start_command_exec(struct msmsdcc_host *host, u32 arg, u32 c) {
203        msmsdcc_writel(host, arg, MMCIARGUMENT);
204        msmsdcc_writel(host, c, MMCICOMMAND);
205 }
206 
207 static void
208 msmsdcc_dma_exec_func(struct msm_dmov_cmd *cmd)
209 {
210         struct msmsdcc_host *host = (struct msmsdcc_host *)cmd->data;
211 
212         msmsdcc_writel(host, host->cmd_timeout, MMCIDATATIMER);
213         msmsdcc_writel(host, (unsigned int)host->curr.xfer_size,
214                        MMCIDATALENGTH);
215         msmsdcc_writel(host, (msmsdcc_readl(host, MMCIMASK0) &
216                         (~MCI_IRQ_PIO)) | host->cmd_pio_irqmask, MMCIMASK0);
217         msmsdcc_writel(host, host->cmd_datactrl, MMCIDATACTRL);
218 
219         if (host->cmd_cmd) {
220                 msmsdcc_start_command_exec(host,
221                                            (u32) host->cmd_cmd->arg,
222                                            (u32) host->cmd_c);
223         }
224         host->dma.active = 1;
225 }
226 
227 static void
228 msmsdcc_dma_complete_tlet(unsigned long data)
229 {
230         struct msmsdcc_host *host = (struct msmsdcc_host *)data;
231         unsigned long           flags;
232         struct mmc_request      *mrq;
233         struct msm_dmov_errdata err;
234 
235         spin_lock_irqsave(&host->lock, flags);
236         host->dma.active = 0;
237 
238         err = host->dma.err;
239         mrq = host->curr.mrq;
240         BUG_ON(!mrq);
241         WARN_ON(!mrq->data);
242 
243         if (!(host->dma.result & DMOV_RSLT_VALID)) {
244                 pr_err("msmsdcc: Invalid DataMover result\n");
245                 goto out;
246         }
247 
248         if (host->dma.result & DMOV_RSLT_DONE) {
249                 host->curr.data_xfered = host->curr.xfer_size;
250         } else {
251                 /* Error or flush  */
252                 if (host->dma.result & DMOV_RSLT_ERROR)
253                         pr_err("%s: DMA error (0x%.8x)\n",
254                                mmc_hostname(host->mmc), host->dma.result);
255                 if (host->dma.result & DMOV_RSLT_FLUSH)
256                         pr_err("%s: DMA channel flushed (0x%.8x)\n",
257                                mmc_hostname(host->mmc), host->dma.result);
258 
259                 pr_err("Flush data: %.8x %.8x %.8x %.8x %.8x %.8x\n",
260                        err.flush[0], err.flush[1], err.flush[2],
261                        err.flush[3], err.flush[4], err.flush[5]);
262 
263                 msmsdcc_reset_and_restore(host);
264                 if (!mrq->data->error)
265                         mrq->data->error = -EIO;
266         }
267         dma_unmap_sg(mmc_dev(host->mmc), host->dma.sg, host->dma.num_ents,
268                      host->dma.dir);
269 
270         host->dma.sg = NULL;
271         host->dma.busy = 0;
272 
273         if (host->curr.got_dataend || mrq->data->error) {
274 
275                 /*
276                  * If we've already gotten our DATAEND / DATABLKEND
277                  * for this request, then complete it through here.
278                  */
279                 msmsdcc_stop_data(host);
280 
281                 if (!mrq->data->error)
282                         host->curr.data_xfered = host->curr.xfer_size;
283                 if (!mrq->data->stop || mrq->cmd->error) {
284                         host->curr.mrq = NULL;
285                         host->curr.cmd = NULL;
286                         mrq->data->bytes_xfered = host->curr.data_xfered;
287 
288                         spin_unlock_irqrestore(&host->lock, flags);
289 #if BUSCLK_PWRSAVE
290                         msmsdcc_disable_clocks(host, 1);
291 #endif
292                         mmc_request_done(host->mmc, mrq);
293                         return;
294                 } else
295                         msmsdcc_start_command(host, mrq->data->stop, 0);
296         }
297 
298 out:
299         spin_unlock_irqrestore(&host->lock, flags);
300         return;
301 }
302 
303 static void
304 msmsdcc_dma_complete_func(struct msm_dmov_cmd *cmd,
305                           unsigned int result,
306                           struct msm_dmov_errdata *err)
307 {
308         struct msmsdcc_dma_data *dma_data =
309                 container_of(cmd, struct msmsdcc_dma_data, hdr);
310         struct msmsdcc_host *host = dma_data->host;
311 
312         dma_data->result = result;
313         if (err)
314                 memcpy(&dma_data->err, err, sizeof(struct msm_dmov_errdata));
315 
316         tasklet_schedule(&host->dma_tlet);
317 }
318 
319 static int validate_dma(struct msmsdcc_host *host, struct mmc_data *data)
320 {
321         if (host->dma.channel == -1)
322                 return -ENOENT;
323 
324         if ((data->blksz * data->blocks) < MCI_FIFOSIZE)
325                 return -EINVAL;
326         if ((data->blksz * data->blocks) % MCI_FIFOSIZE)
327                 return -EINVAL;
328         return 0;
329 }
330 
331 static int msmsdcc_config_dma(struct msmsdcc_host *host, struct mmc_data *data)
332 {
333         struct msmsdcc_nc_dmadata *nc;
334         dmov_box *box;
335         uint32_t rows;
336         uint32_t crci;
337         unsigned int n;
338         int i, rc;
339         struct scatterlist *sg = data->sg;
340 
341         rc = validate_dma(host, data);
342         if (rc)
343                 return rc;
344 
345         host->dma.sg = data->sg;
346         host->dma.num_ents = data->sg_len;
347 
348        BUG_ON(host->dma.num_ents > NR_SG); /* Prevent memory corruption */
349 
350         nc = host->dma.nc;
351 
352         switch (host->pdev_id) {
353         case 1:
354                 crci = MSMSDCC_CRCI_SDC1;
355                 break;
356         case 2:
357                 crci = MSMSDCC_CRCI_SDC2;
358                 break;
359         case 3:
360                 crci = MSMSDCC_CRCI_SDC3;
361                 break;
362         case 4:
363                 crci = MSMSDCC_CRCI_SDC4;
364                 break;
365         default:
366                 host->dma.sg = NULL;
367                 host->dma.num_ents = 0;
368                 return -ENOENT;
369         }
370 
371         if (data->flags & MMC_DATA_READ)
372                 host->dma.dir = DMA_FROM_DEVICE;
373         else
374                 host->dma.dir = DMA_TO_DEVICE;
375 
376         host->curr.user_pages = 0;
377 
378         box = &nc->cmd[0];
379 
380         /* location of command block must be 64 bit aligned */
381         BUG_ON(host->dma.cmd_busaddr & 0x07);
382 
383         nc->cmdptr = (host->dma.cmd_busaddr >> 3) | CMD_PTR_LP;
384         host->dma.hdr.cmdptr = DMOV_CMD_PTR_LIST |
385                                DMOV_CMD_ADDR(host->dma.cmdptr_busaddr);
386         host->dma.hdr.complete_func = msmsdcc_dma_complete_func;
387 
388         n = dma_map_sg(mmc_dev(host->mmc), host->dma.sg,
389                         host->dma.num_ents, host->dma.dir);
390         if (n == 0) {
391                 pr_err("%s: Unable to map in all sg elements\n",
392                         mmc_hostname(host->mmc));
393                 host->dma.sg = NULL;
394                 host->dma.num_ents = 0;
395                 return -ENOMEM;
396         }
397 
398         for_each_sg(host->dma.sg, sg, n, i) {
399 
400                 box->cmd = CMD_MODE_BOX;
401 
402                 if (i == n - 1)
403                         box->cmd |= CMD_LC;
404                 rows = (sg_dma_len(sg) % MCI_FIFOSIZE) ?
405                         (sg_dma_len(sg) / MCI_FIFOSIZE) + 1 :
406                         (sg_dma_len(sg) / MCI_FIFOSIZE) ;
407 
408                 if (data->flags & MMC_DATA_READ) {
409                         box->src_row_addr = msmsdcc_fifo_addr(host);
410                         box->dst_row_addr = sg_dma_address(sg);
411 
412                         box->src_dst_len = (MCI_FIFOSIZE << 16) |
413                                            (MCI_FIFOSIZE);
414                         box->row_offset = MCI_FIFOSIZE;
415 
416                         box->num_rows = rows * ((1 << 16) + 1);
417                         box->cmd |= CMD_SRC_CRCI(crci);
418                 } else {
419                         box->src_row_addr = sg_dma_address(sg);
420                         box->dst_row_addr = msmsdcc_fifo_addr(host);
421 
422                         box->src_dst_len = (MCI_FIFOSIZE << 16) |
423                                            (MCI_FIFOSIZE);
424                         box->row_offset = (MCI_FIFOSIZE << 16);
425 
426                         box->num_rows = rows * ((1 << 16) + 1);
427                         box->cmd |= CMD_DST_CRCI(crci);
428                 }
429                 box++;
430         }
431 
432         return 0;
433 }
434 
435 static int
436 snoop_cccr_abort(struct mmc_command *cmd)
437 {
438         if ((cmd->opcode == 52) &&
439             (cmd->arg & 0x80000000) &&
440             (((cmd->arg >> 9) & 0x1ffff) == SDIO_CCCR_ABORT))
441                 return 1;
442         return 0;
443 }
444 
445 static void
446 msmsdcc_start_command_deferred(struct msmsdcc_host *host,
447                                 struct mmc_command *cmd, u32 *c)
448 {
449         *c |= (cmd->opcode | MCI_CPSM_ENABLE);
450 
451         if (cmd->flags & MMC_RSP_PRESENT) {
452                 if (cmd->flags & MMC_RSP_136)
453                         *c |= MCI_CPSM_LONGRSP;
454                 *c |= MCI_CPSM_RESPONSE;
455         }
456 
457         if (/*interrupt*/0)
458                 *c |= MCI_CPSM_INTERRUPT;
459 
460         if ((((cmd->opcode == 17) || (cmd->opcode == 18))  ||
461              ((cmd->opcode == 24) || (cmd->opcode == 25))) ||
462               (cmd->opcode == 53))
463                 *c |= MCI_CSPM_DATCMD;
464 
465         if (host->prog_scan && (cmd->opcode == 12)) {
466                 *c |= MCI_CPSM_PROGENA;
467                 host->prog_enable = true;
468         }
469 
470         if (cmd == cmd->mrq->stop)
471                 *c |= MCI_CSPM_MCIABORT;
472 
473         if (snoop_cccr_abort(cmd))
474                 *c |= MCI_CSPM_MCIABORT;
475 
476         if (host->curr.cmd != NULL) {
477                 pr_err("%s: Overlapping command requests\n",
478                         mmc_hostname(host->mmc));
479         }
480         host->curr.cmd = cmd;
481 }
482 
483 static void
484 msmsdcc_start_data(struct msmsdcc_host *host, struct mmc_data *data,
485                         struct mmc_command *cmd, u32 c)
486 {
487         unsigned int datactrl, timeout;
488         unsigned long long clks;
489         unsigned int pio_irqmask = 0;
490 
491         host->curr.data = data;
492         host->curr.xfer_size = data->blksz * data->blocks;
493         host->curr.xfer_remain = host->curr.xfer_size;
494         host->curr.data_xfered = 0;
495         host->curr.got_dataend = 0;
496 
497         memset(&host->pio, 0, sizeof(host->pio));
498 
499         datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
500 
501         if (!msmsdcc_config_dma(host, data))
502                 datactrl |= MCI_DPSM_DMAENABLE;
503         else {
504                 host->pio.sg = data->sg;
505                 host->pio.sg_len = data->sg_len;
506                 host->pio.sg_off = 0;
507 
508                 if (data->flags & MMC_DATA_READ) {
509                         pio_irqmask = MCI_RXFIFOHALFFULLMASK;
510                         if (host->curr.xfer_remain < MCI_FIFOSIZE)
511                                 pio_irqmask |= MCI_RXDATAAVLBLMASK;
512                 } else
513                         pio_irqmask = MCI_TXFIFOHALFEMPTYMASK;
514         }
515 
516         if (data->flags & MMC_DATA_READ)
517                 datactrl |= MCI_DPSM_DIRECTION;
518 
519         clks = (unsigned long long)data->timeout_ns * host->clk_rate;
520         do_div(clks, NSEC_PER_SEC);
521         timeout = data->timeout_clks + (unsigned int)clks*2 ;
522 
523         if (datactrl & MCI_DPSM_DMAENABLE) {
524                 /* Save parameters for the exec function */
525                 host->cmd_timeout = timeout;
526                 host->cmd_pio_irqmask = pio_irqmask;
527                 host->cmd_datactrl = datactrl;
528                 host->cmd_cmd = cmd;
529 
530                 host->dma.hdr.execute_func = msmsdcc_dma_exec_func;
531                 host->dma.hdr.data = (void *)host;
532                 host->dma.busy = 1;
533 
534                 if (cmd) {
535                         msmsdcc_start_command_deferred(host, cmd, &c);
536                         host->cmd_c = c;
537                 }
538                 msm_dmov_enqueue_cmd(host->dma.channel, &host->dma.hdr);
539                 if (data->flags & MMC_DATA_WRITE)
540                         host->prog_scan = true;
541         } else {
542                 msmsdcc_writel(host, timeout, MMCIDATATIMER);
543 
544                 msmsdcc_writel(host, host->curr.xfer_size, MMCIDATALENGTH);
545 
546                 msmsdcc_writel(host, (msmsdcc_readl(host, MMCIMASK0) &
547                                 (~MCI_IRQ_PIO)) | pio_irqmask, MMCIMASK0);
548 
549                 msmsdcc_writel(host, datactrl, MMCIDATACTRL);
550 
551                 if (cmd) {
552                         /* Daisy-chain the command if requested */
553                         msmsdcc_start_command(host, cmd, c);
554                 }
555         }
556 }
557 
558 static void
559 msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd, u32 c)
560 {
561         if (cmd == cmd->mrq->stop)
562                 c |= MCI_CSPM_MCIABORT;
563 
564         host->stats.cmds++;
565 
566         msmsdcc_start_command_deferred(host, cmd, &c);
567         msmsdcc_start_command_exec(host, cmd->arg, c);
568 }
569 
570 static void
571 msmsdcc_data_err(struct msmsdcc_host *host, struct mmc_data *data,
572                  unsigned int status)
573 {
574         if (status & MCI_DATACRCFAIL) {
575                 pr_err("%s: Data CRC error\n", mmc_hostname(host->mmc));
576                 pr_err("%s: opcode 0x%.8x\n", __func__,
577                        data->mrq->cmd->opcode);
578                 pr_err("%s: blksz %d, blocks %d\n", __func__,
579                        data->blksz, data->blocks);
580                 data->error = -EILSEQ;
581         } else if (status & MCI_DATATIMEOUT) {
582                 pr_err("%s: Data timeout\n", mmc_hostname(host->mmc));
583                 data->error = -ETIMEDOUT;
584         } else if (status & MCI_RXOVERRUN) {
585                 pr_err("%s: RX overrun\n", mmc_hostname(host->mmc));
586                 data->error = -EIO;
587         } else if (status & MCI_TXUNDERRUN) {
588                 pr_err("%s: TX underrun\n", mmc_hostname(host->mmc));
589                 data->error = -EIO;
590         } else {
591                 pr_err("%s: Unknown error (0x%.8x)\n",
592                        mmc_hostname(host->mmc), status);
593                 data->error = -EIO;
594         }
595 }
596 
597 
598 static int
599 msmsdcc_pio_read(struct msmsdcc_host *host, char *buffer, unsigned int remain)
600 {
601         uint32_t        *ptr = (uint32_t *) buffer;
602         int             count = 0;
603 
604         if (remain % 4)
605                 remain = ((remain >> 2) + 1) << 2;
606 
607         while (msmsdcc_readl(host, MMCISTATUS) & MCI_RXDATAAVLBL) {
608                 *ptr = msmsdcc_readl(host, MMCIFIFO + (count % MCI_FIFOSIZE));
609                 ptr++;
610                 count += sizeof(uint32_t);
611 
612                 remain -=  sizeof(uint32_t);
613                 if (remain == 0)
614                         break;
615         }
616         return count;
617 }
618 
619 static int
620 msmsdcc_pio_write(struct msmsdcc_host *host, char *buffer,
621                   unsigned int remain, u32 status)
622 {
623         void __iomem *base = host->base;
624         char *ptr = buffer;
625 
626         do {
627                 unsigned int count, maxcnt, sz;
628 
629                 maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE :
630                                                     MCI_FIFOHALFSIZE;
631                 count = min(remain, maxcnt);
632 
633                 sz = count % 4 ? (count >> 2) + 1 : (count >> 2);
634                 writesl(base + MMCIFIFO, ptr, sz);
635                 ptr += count;
636                 remain -= count;
637 
638                 if (remain == 0)
639                         break;
640 
641                 status = msmsdcc_readl(host, MMCISTATUS);
642         } while (status & MCI_TXFIFOHALFEMPTY);
643 
644         return ptr - buffer;
645 }
646 
647 static int
648 msmsdcc_spin_on_status(struct msmsdcc_host *host, uint32_t mask, int maxspin)
649 {
650         while (maxspin) {
651                 if ((msmsdcc_readl(host, MMCISTATUS) & mask))
652                         return 0;
653                 udelay(1);
654                 --maxspin;
655         }
656         return -ETIMEDOUT;
657 }
658 
659 static irqreturn_t
660 msmsdcc_pio_irq(int irq, void *dev_id)
661 {
662         struct msmsdcc_host     *host = dev_id;
663         uint32_t                status;
664         u32 mci_mask0;
665 
666         status = msmsdcc_readl(host, MMCISTATUS);
667         mci_mask0 = msmsdcc_readl(host, MMCIMASK0);
668 
669         if (((mci_mask0 & status) & MCI_IRQ_PIO) == 0)
670                 return IRQ_NONE;
671 
672         do {
673                 unsigned long flags;
674                 unsigned int remain, len;
675                 char *buffer;
676 
677                 if (!(status & (MCI_TXFIFOHALFEMPTY | MCI_RXDATAAVLBL))) {
678                         if (host->curr.xfer_remain == 0 || !msmsdcc_piopoll)
679                                 break;
680 
681                         if (msmsdcc_spin_on_status(host,
682                                                    (MCI_TXFIFOHALFEMPTY |
683                                                    MCI_RXDATAAVLBL),
684                                                    PIO_SPINMAX)) {
685                                 break;
686                         }
687                 }
688 
689                 /* Map the current scatter buffer */
690                 local_irq_save(flags);
691                 buffer = kmap_atomic(sg_page(host->pio.sg))
692                                      + host->pio.sg->offset;
693                 buffer += host->pio.sg_off;
694                 remain = host->pio.sg->length - host->pio.sg_off;
695                 len = 0;
696                 if (status & MCI_RXACTIVE)
697                         len = msmsdcc_pio_read(host, buffer, remain);
698                 if (status & MCI_TXACTIVE)
699                         len = msmsdcc_pio_write(host, buffer, remain, status);
700 
701                 /* Unmap the buffer */
702                 kunmap_atomic(buffer);
703                 local_irq_restore(flags);
704 
705                 host->pio.sg_off += len;
706                 host->curr.xfer_remain -= len;
707                 host->curr.data_xfered += len;
708                 remain -= len;
709 
710                 if (remain == 0) {
711                         /* This sg page is full - do some housekeeping */
712                         if (status & MCI_RXACTIVE && host->curr.user_pages)
713                                 flush_dcache_page(sg_page(host->pio.sg));
714 
715                         if (!--host->pio.sg_len) {
716                                 memset(&host->pio, 0, sizeof(host->pio));
717                                 break;
718                         }
719 
720                         /* Advance to next sg */
721                         host->pio.sg++;
722                         host->pio.sg_off = 0;
723                 }
724 
725                 status = msmsdcc_readl(host, MMCISTATUS);
726         } while (1);
727 
728         if (status & MCI_RXACTIVE && host->curr.xfer_remain < MCI_FIFOSIZE)
729                 msmsdcc_writel(host, (mci_mask0 & (~MCI_IRQ_PIO)) |
730                                         MCI_RXDATAAVLBLMASK, MMCIMASK0);
731 
732         if (!host->curr.xfer_remain)
733                 msmsdcc_writel(host, (mci_mask0 & (~MCI_IRQ_PIO)) | 0,
734                                         MMCIMASK0);
735 
736         return IRQ_HANDLED;
737 }
738 
739 static void msmsdcc_do_cmdirq(struct msmsdcc_host *host, uint32_t status)
740 {
741         struct mmc_command *cmd = host->curr.cmd;
742 
743         host->curr.cmd = NULL;
744         cmd->resp[0] = msmsdcc_readl(host, MMCIRESPONSE0);
745         cmd->resp[1] = msmsdcc_readl(host, MMCIRESPONSE1);
746         cmd->resp[2] = msmsdcc_readl(host, MMCIRESPONSE2);
747         cmd->resp[3] = msmsdcc_readl(host, MMCIRESPONSE3);
748 
749         if (status & MCI_CMDTIMEOUT) {
750                 cmd->error = -ETIMEDOUT;
751         } else if (status & MCI_CMDCRCFAIL &&
752                    cmd->flags & MMC_RSP_CRC) {
753                 pr_err("%s: Command CRC error\n", mmc_hostname(host->mmc));
754                 cmd->error = -EILSEQ;
755         }
756 
757         if (!cmd->data || cmd->error) {
758                 if (host->curr.data && host->dma.sg)
759                         msm_dmov_stop_cmd(host->dma.channel,
760                                           &host->dma.hdr, 0);
761                 else if (host->curr.data) { /* Non DMA */
762                         msmsdcc_reset_and_restore(host);
763                         msmsdcc_stop_data(host);
764                         msmsdcc_request_end(host, cmd->mrq);
765                 } else { /* host->data == NULL */
766                         if (!cmd->error && host->prog_enable) {
767                                 if (status & MCI_PROGDONE) {
768                                         host->prog_scan = false;
769                                         host->prog_enable = false;
770                                         msmsdcc_request_end(host, cmd->mrq);
771                                 } else {
772                                         host->curr.cmd = cmd;
773                                 }
774                         } else {
775                                 if (host->prog_enable) {
776                                         host->prog_scan = false;
777                                         host->prog_enable = false;
778                                 }
779                                 msmsdcc_request_end(host, cmd->mrq);
780                         }
781                 }
782         } else if (cmd->data)
783                 if (!(cmd->data->flags & MMC_DATA_READ))
784                         msmsdcc_start_data(host, cmd->data,
785                                                 NULL, 0);
786 }
787 
788 static void
789 msmsdcc_handle_irq_data(struct msmsdcc_host *host, u32 status,
790                         void __iomem *base)
791 {
792         struct mmc_data *data = host->curr.data;
793 
794         if (status & (MCI_CMDSENT | MCI_CMDRESPEND | MCI_CMDCRCFAIL |
795                         MCI_CMDTIMEOUT | MCI_PROGDONE) && host->curr.cmd) {
796                 msmsdcc_do_cmdirq(host, status);
797         }
798 
799         if (!data)
800                 return;
801 
802         /* Check for data errors */
803         if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT |
804                       MCI_TXUNDERRUN | MCI_RXOVERRUN)) {
805                 msmsdcc_data_err(host, data, status);
806                 host->curr.data_xfered = 0;
807                 if (host->dma.sg)
808                         msm_dmov_stop_cmd(host->dma.channel,
809                                           &host->dma.hdr, 0);
810                 else {
811                         msmsdcc_reset_and_restore(host);
812                         if (host->curr.data)
813                                 msmsdcc_stop_data(host);
814                         if (!data->stop)
815                                 msmsdcc_request_end(host, data->mrq);
816                         else
817                                 msmsdcc_start_command(host, data->stop, 0);
818                 }
819         }
820 
821         /* Check for data done */
822         if (!host->curr.got_dataend && (status & MCI_DATAEND))
823                 host->curr.got_dataend = 1;
824 
825         /*
826          * If DMA is still in progress, we complete via the completion handler
827          */
828         if (host->curr.got_dataend && !host->dma.busy) {
829                 /*
830                  * There appears to be an issue in the controller where
831                  * if you request a small block transfer (< fifo size),
832                  * you may get your DATAEND/DATABLKEND irq without the
833                  * PIO data irq.
834                  *
835                  * Check to see if there is still data to be read,
836                  * and simulate a PIO irq.
837                  */
838                 if (readl(base + MMCISTATUS) & MCI_RXDATAAVLBL)
839                         msmsdcc_pio_irq(1, host);
840 
841                 msmsdcc_stop_data(host);
842                 if (!data->error)
843                         host->curr.data_xfered = host->curr.xfer_size;
844 
845                 if (!data->stop)
846                         msmsdcc_request_end(host, data->mrq);
847                 else
848                         msmsdcc_start_command(host, data->stop, 0);
849         }
850 }
851 
852 static irqreturn_t
853 msmsdcc_irq(int irq, void *dev_id)
854 {
855         struct msmsdcc_host     *host = dev_id;
856         void __iomem            *base = host->base;
857         u32                     status;
858         int                     ret = 0;
859         int                     cardint = 0;
860 
861         spin_lock(&host->lock);
862 
863         do {
864                 status = msmsdcc_readl(host, MMCISTATUS);
865                 status &= msmsdcc_readl(host, MMCIMASK0);
866                 if ((status & (~MCI_IRQ_PIO)) == 0)
867                         break;
868                 msmsdcc_writel(host, status, MMCICLEAR);
869 
870                 if (status & MCI_SDIOINTR)
871                         status &= ~MCI_SDIOINTR;
872 
873                 if (!status)
874                         break;
875 
876                 msmsdcc_handle_irq_data(host, status, base);
877 
878                 if (status & MCI_SDIOINTOPER) {
879                         cardint = 1;
880                         status &= ~MCI_SDIOINTOPER;
881                 }
882                 ret = 1;
883         } while (status);
884 
885         spin_unlock(&host->lock);
886 
887         /*
888          * We have to delay handling the card interrupt as it calls
889          * back into the driver.
890          */
891         if (cardint)
892                 mmc_signal_sdio_irq(host->mmc);
893 
894         return IRQ_RETVAL(ret);
895 }
896 
897 static void
898 msmsdcc_request(struct mmc_host *mmc, struct mmc_request *mrq)
899 {
900         struct msmsdcc_host *host = mmc_priv(mmc);
901         unsigned long flags;
902 
903         WARN_ON(host->curr.mrq != NULL);
904         WARN_ON(host->pwr == 0);
905 
906         spin_lock_irqsave(&host->lock, flags);
907 
908         host->stats.reqs++;
909 
910         if (host->eject) {
911                 if (mrq->data && !(mrq->data->flags & MMC_DATA_READ)) {
912                         mrq->cmd->error = 0;
913                         mrq->data->bytes_xfered = mrq->data->blksz *
914                                                   mrq->data->blocks;
915                 } else
916                         mrq->cmd->error = -ENOMEDIUM;
917 
918                 spin_unlock_irqrestore(&host->lock, flags);
919                 mmc_request_done(mmc, mrq);
920                 return;
921         }
922 
923         msmsdcc_enable_clocks(host);
924 
925         host->curr.mrq = mrq;
926 
927         if (mrq->data && mrq->data->flags & MMC_DATA_READ)
928                 /* Queue/read data, daisy-chain command when data starts */
929                 msmsdcc_start_data(host, mrq->data, mrq->cmd, 0);
930         else
931                 msmsdcc_start_command(host, mrq->cmd, 0);
932 
933         if (host->cmdpoll && !msmsdcc_spin_on_status(host,
934                                 MCI_CMDRESPEND|MCI_CMDCRCFAIL|MCI_CMDTIMEOUT,
935                                 CMD_SPINMAX)) {
936                 uint32_t status = msmsdcc_readl(host, MMCISTATUS);
937                 msmsdcc_do_cmdirq(host, status);
938                 msmsdcc_writel(host,
939                                MCI_CMDRESPEND | MCI_CMDCRCFAIL | MCI_CMDTIMEOUT,
940                                MMCICLEAR);
941                 host->stats.cmdpoll_hits++;
942         } else {
943                 host->stats.cmdpoll_misses++;
944         }
945         spin_unlock_irqrestore(&host->lock, flags);
946 }
947 
948 static void msmsdcc_setup_gpio(struct msmsdcc_host *host, bool enable)
949 {
950         struct msm_mmc_gpio_data *curr;
951         int i, rc = 0;
952 
953         if (!host->plat->gpio_data || host->gpio_config_status == enable)
954                 return;
955 
956         curr = host->plat->gpio_data;
957         for (i = 0; i < curr->size; i++) {
958                 if (enable) {
959                         rc = gpio_request(curr->gpio[i].no,
960                                                 curr->gpio[i].name);
961                         if (rc) {
962                                 pr_err("%s: gpio_request(%d, %s) failed %d\n",
963                                         mmc_hostname(host->mmc),
964                                         curr->gpio[i].no,
965                                         curr->gpio[i].name, rc);
966                                 goto free_gpios;
967                         }
968                 } else {
969                         gpio_free(curr->gpio[i].no);
970                 }
971         }
972         host->gpio_config_status = enable;
973         return;
974 
975 free_gpios:
976         for (; i >= 0; i--)
977                 gpio_free(curr->gpio[i].no);
978 }
979 
980 static void
981 msmsdcc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
982 {
983         struct msmsdcc_host *host = mmc_priv(mmc);
984         u32 clk = 0, pwr = 0;
985         int rc;
986         unsigned long flags;
987 
988         spin_lock_irqsave(&host->lock, flags);
989 
990         msmsdcc_enable_clocks(host);
991 
992         spin_unlock_irqrestore(&host->lock, flags);
993 
994         if (ios->clock) {
995                 if (ios->clock != host->clk_rate) {
996                         rc = clk_set_rate(host->clk, ios->clock);
997                         if (rc < 0)
998                                 pr_err("%s: Error setting clock rate (%d)\n",
999                                        mmc_hostname(host->mmc), rc);
1000                         else
1001                                 host->clk_rate = ios->clock;
1002                 }
1003                 clk |= MCI_CLK_ENABLE;
1004         }
1005 
1006         if (ios->bus_width == MMC_BUS_WIDTH_4)
1007                 clk |= (2 << 10); /* Set WIDEBUS */
1008 
1009         if (ios->clock > 400000 && msmsdcc_pwrsave)
1010                 clk |= (1 << 9); /* PWRSAVE */
1011 
1012         clk |= (1 << 12); /* FLOW_ENA */
1013         clk |= (1 << 15); /* feedback clock */
1014 
1015         if (host->plat->translate_vdd)
1016                 pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
1017 
1018         switch (ios->power_mode) {
1019         case MMC_POWER_OFF:
1020                 msmsdcc_setup_gpio(host, false);
1021                 break;
1022         case MMC_POWER_UP:
1023                 pwr |= MCI_PWR_UP;
1024                 msmsdcc_setup_gpio(host, true);
1025                 break;
1026         case MMC_POWER_ON:
1027                 pwr |= MCI_PWR_ON;
1028                 break;
1029         }
1030 
1031         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1032                 pwr |= MCI_OD;
1033 
1034         msmsdcc_writel(host, clk, MMCICLOCK);
1035 
1036         if (host->pwr != pwr) {
1037                 host->pwr = pwr;
1038                 msmsdcc_writel(host, pwr, MMCIPOWER);
1039         }
1040 #if BUSCLK_PWRSAVE
1041         spin_lock_irqsave(&host->lock, flags);
1042         msmsdcc_disable_clocks(host, 1);
1043         spin_unlock_irqrestore(&host->lock, flags);
1044 #endif
1045 }
1046 
1047 static void msmsdcc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1048 {
1049         struct msmsdcc_host *host = mmc_priv(mmc);
1050         unsigned long flags;
1051         u32 status;
1052 
1053         spin_lock_irqsave(&host->lock, flags);
1054         if (msmsdcc_sdioirq == 1) {
1055                 status = msmsdcc_readl(host, MMCIMASK0);
1056                 if (enable)
1057                         status |= MCI_SDIOINTOPERMASK;
1058                 else
1059                         status &= ~MCI_SDIOINTOPERMASK;
1060                 host->saved_irq0mask = status;
1061                 msmsdcc_writel(host, status, MMCIMASK0);
1062         }
1063         spin_unlock_irqrestore(&host->lock, flags);
1064 }
1065 
1066 static void msmsdcc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1067 {
1068         struct msmsdcc_host *host = mmc_priv(mmc);
1069 
1070         if (host->plat->init_card)
1071                 host->plat->init_card(card);
1072 }
1073 
1074 static const struct mmc_host_ops msmsdcc_ops = {
1075         .request        = msmsdcc_request,
1076         .set_ios        = msmsdcc_set_ios,
1077         .enable_sdio_irq = msmsdcc_enable_sdio_irq,
1078         .init_card      = msmsdcc_init_card,
1079 };
1080 
1081 static void
1082 msmsdcc_check_status(unsigned long data)
1083 {
1084         struct msmsdcc_host *host = (struct msmsdcc_host *)data;
1085         unsigned int status;
1086 
1087         if (!host->plat->status) {
1088                 mmc_detect_change(host->mmc, 0);
1089                 goto out;
1090         }
1091 
1092         status = host->plat->status(mmc_dev(host->mmc));
1093         host->eject = !status;
1094         if (status ^ host->oldstat) {
1095                 pr_info("%s: Slot status change detected (%d -> %d)\n",
1096                         mmc_hostname(host->mmc), host->oldstat, status);
1097                 if (status)
1098                         mmc_detect_change(host->mmc, (5 * HZ) / 2);
1099                 else
1100                         mmc_detect_change(host->mmc, 0);
1101         }
1102 
1103         host->oldstat = status;
1104 
1105 out:
1106         if (host->timer.function)
1107                 mod_timer(&host->timer, jiffies + HZ);
1108 }
1109 
1110 static irqreturn_t
1111 msmsdcc_platform_status_irq(int irq, void *dev_id)
1112 {
1113         struct msmsdcc_host *host = dev_id;
1114 
1115         pr_debug("%s: %d\n", __func__, irq);
1116         msmsdcc_check_status((unsigned long) host);
1117         return IRQ_HANDLED;
1118 }
1119 
1120 static void
1121 msmsdcc_status_notify_cb(int card_present, void *dev_id)
1122 {
1123         struct msmsdcc_host *host = dev_id;
1124 
1125         pr_debug("%s: card_present %d\n", mmc_hostname(host->mmc),
1126                card_present);
1127         msmsdcc_check_status((unsigned long) host);
1128 }
1129 
1130 static void
1131 msmsdcc_busclk_expired(unsigned long _data)
1132 {
1133         struct msmsdcc_host     *host = (struct msmsdcc_host *) _data;
1134 
1135         if (host->clks_on)
1136                 msmsdcc_disable_clocks(host, 0);
1137 }
1138 
1139 static int
1140 msmsdcc_init_dma(struct msmsdcc_host *host)
1141 {
1142         memset(&host->dma, 0, sizeof(struct msmsdcc_dma_data));
1143         host->dma.host = host;
1144         host->dma.channel = -1;
1145 
1146         if (!host->dmares)
1147                 return -ENODEV;
1148 
1149         host->dma.nc = dma_alloc_coherent(NULL,
1150                                           sizeof(struct msmsdcc_nc_dmadata),
1151                                           &host->dma.nc_busaddr,
1152                                           GFP_KERNEL);
1153         if (host->dma.nc == NULL) {
1154                 pr_err("Unable to allocate DMA buffer\n");
1155                 return -ENOMEM;
1156         }
1157         memset(host->dma.nc, 0x00, sizeof(struct msmsdcc_nc_dmadata));
1158         host->dma.cmd_busaddr = host->dma.nc_busaddr;
1159         host->dma.cmdptr_busaddr = host->dma.nc_busaddr +
1160                                 offsetof(struct msmsdcc_nc_dmadata, cmdptr);
1161         host->dma.channel = host->dmares->start;
1162 
1163         return 0;
1164 }
1165 
1166 static int
1167 msmsdcc_probe(struct platform_device *pdev)
1168 {
1169         struct msm_mmc_platform_data *plat = pdev->dev.platform_data;
1170         struct msmsdcc_host *host;
1171         struct mmc_host *mmc;
1172         struct resource *cmd_irqres = NULL;
1173         struct resource *stat_irqres = NULL;
1174         struct resource *memres = NULL;
1175         struct resource *dmares = NULL;
1176         int ret;
1177 
1178         /* must have platform data */
1179         if (!plat) {
1180                 pr_err("%s: Platform data not available\n", __func__);
1181                 ret = -EINVAL;
1182                 goto out;
1183         }
1184 
1185         if (pdev->id < 1 || pdev->id > 4)
1186                 return -EINVAL;
1187 
1188         if (pdev->resource == NULL || pdev->num_resources < 2) {
1189                 pr_err("%s: Invalid resource\n", __func__);
1190                 return -ENXIO;
1191         }
1192 
1193         memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1194         dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1195         cmd_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1196                                                   "cmd_irq");
1197         stat_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1198                                                    "status_irq");
1199 
1200         if (!cmd_irqres || !memres) {
1201                 pr_err("%s: Invalid resource\n", __func__);
1202                 return -ENXIO;
1203         }
1204 
1205         /*
1206          * Setup our host structure
1207          */
1208 
1209         mmc = mmc_alloc_host(sizeof(struct msmsdcc_host), &pdev->dev);
1210         if (!mmc) {
1211                 ret = -ENOMEM;
1212                 goto out;
1213         }
1214 
1215         host = mmc_priv(mmc);
1216         host->pdev_id = pdev->id;
1217         host->plat = plat;
1218         host->mmc = mmc;
1219         host->curr.cmd = NULL;
1220         init_timer(&host->busclk_timer);
1221         host->busclk_timer.data = (unsigned long) host;
1222         host->busclk_timer.function = msmsdcc_busclk_expired;
1223 
1224 
1225         host->cmdpoll = 1;
1226 
1227         host->base = ioremap(memres->start, PAGE_SIZE);
1228         if (!host->base) {
1229                 ret = -ENOMEM;
1230                 goto host_free;
1231         }
1232 
1233         host->cmd_irqres = cmd_irqres;
1234         host->memres = memres;
1235         host->dmares = dmares;
1236         spin_lock_init(&host->lock);
1237 
1238         tasklet_init(&host->dma_tlet, msmsdcc_dma_complete_tlet,
1239                         (unsigned long)host);
1240 
1241         /*
1242          * Setup DMA
1243          */
1244         if (host->dmares) {
1245                 ret = msmsdcc_init_dma(host);
1246                 if (ret)
1247                         goto ioremap_free;
1248         } else {
1249                 host->dma.channel = -1;
1250         }
1251 
1252         /* Get our clocks */
1253         host->pclk = clk_get(&pdev->dev, "sdc_pclk");
1254         if (IS_ERR(host->pclk)) {
1255                 ret = PTR_ERR(host->pclk);
1256                 goto dma_free;
1257         }
1258 
1259         host->clk = clk_get(&pdev->dev, "sdc_clk");
1260         if (IS_ERR(host->clk)) {
1261                 ret = PTR_ERR(host->clk);
1262                 goto pclk_put;
1263         }
1264 
1265         ret = clk_set_rate(host->clk, msmsdcc_fmin);
1266         if (ret) {
1267                 pr_err("%s: Clock rate set failed (%d)\n", __func__, ret);
1268                 goto clk_put;
1269         }
1270 
1271         ret = clk_prepare(host->pclk);
1272         if (ret)
1273                 goto clk_put;
1274 
1275         ret = clk_prepare(host->clk);
1276         if (ret)
1277                 goto clk_unprepare_p;
1278 
1279         /* Enable clocks */
1280         ret = msmsdcc_enable_clocks(host);
1281         if (ret)
1282                 goto clk_unprepare;
1283 
1284         host->pclk_rate = clk_get_rate(host->pclk);
1285         host->clk_rate = clk_get_rate(host->clk);
1286 
1287         /*
1288          * Setup MMC host structure
1289          */
1290         mmc->ops = &msmsdcc_ops;
1291         mmc->f_min = msmsdcc_fmin;
1292         mmc->f_max = msmsdcc_fmax;
1293         mmc->ocr_avail = plat->ocr_mask;
1294 
1295         if (msmsdcc_4bit)
1296                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1297         if (msmsdcc_sdioirq)
1298                 mmc->caps |= MMC_CAP_SDIO_IRQ;
1299         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1300 
1301         mmc->max_segs = NR_SG;
1302         mmc->max_blk_size = 4096;       /* MCI_DATA_CTL BLOCKSIZE up to 4096 */
1303         mmc->max_blk_count = 65536;
1304 
1305         mmc->max_req_size = 33554432;   /* MCI_DATA_LENGTH is 25 bits */
1306         mmc->max_seg_size = mmc->max_req_size;
1307 
1308         msmsdcc_writel(host, 0, MMCIMASK0);
1309         msmsdcc_writel(host, 0x5e007ff, MMCICLEAR);
1310 
1311         msmsdcc_writel(host, MCI_IRQENABLE, MMCIMASK0);
1312         host->saved_irq0mask = MCI_IRQENABLE;
1313 
1314         /*
1315          * Setup card detect change
1316          */
1317 
1318         memset(&host->timer, 0, sizeof(host->timer));
1319 
1320         if (stat_irqres && !(stat_irqres->flags & IORESOURCE_DISABLED)) {
1321                 unsigned long irqflags = IRQF_SHARED |
1322                         (stat_irqres->flags & IRQF_TRIGGER_MASK);
1323 
1324                 host->stat_irq = stat_irqres->start;
1325                 ret = request_irq(host->stat_irq,
1326                                   msmsdcc_platform_status_irq,
1327                                   irqflags,
1328                                   DRIVER_NAME " (slot)",
1329                                   host);
1330                 if (ret) {
1331                         pr_err("%s: Unable to get slot IRQ %d (%d)\n",
1332                                mmc_hostname(mmc), host->stat_irq, ret);
1333                         goto clk_disable;
1334                 }
1335         } else if (plat->register_status_notify) {
1336                 plat->register_status_notify(msmsdcc_status_notify_cb, host);
1337         } else if (!plat->status)
1338                 pr_err("%s: No card detect facilities available\n",
1339                        mmc_hostname(mmc));
1340         else {
1341                 init_timer(&host->timer);
1342                 host->timer.data = (unsigned long)host;
1343                 host->timer.function = msmsdcc_check_status;
1344                 host->timer.expires = jiffies + HZ;
1345                 add_timer(&host->timer);
1346         }
1347 
1348         if (plat->status) {
1349                 host->oldstat = host->plat->status(mmc_dev(host->mmc));
1350                 host->eject = !host->oldstat;
1351         }
1352 
1353         ret = request_irq(cmd_irqres->start, msmsdcc_irq, IRQF_SHARED,
1354                           DRIVER_NAME " (cmd)", host);
1355         if (ret)
1356                 goto stat_irq_free;
1357 
1358         ret = request_irq(cmd_irqres->start, msmsdcc_pio_irq, IRQF_SHARED,
1359                           DRIVER_NAME " (pio)", host);
1360         if (ret)
1361                 goto cmd_irq_free;
1362 
1363         mmc_set_drvdata(pdev, mmc);
1364         mmc_add_host(mmc);
1365 
1366         pr_info("%s: Qualcomm MSM SDCC at 0x%016llx irq %d,%d dma %d\n",
1367                 mmc_hostname(mmc), (unsigned long long)memres->start,
1368                 (unsigned int) cmd_irqres->start,
1369                 (unsigned int) host->stat_irq, host->dma.channel);
1370         pr_info("%s: 4 bit data mode %s\n", mmc_hostname(mmc),
1371                 (mmc->caps & MMC_CAP_4_BIT_DATA ? "enabled" : "disabled"));
1372         pr_info("%s: MMC clock %u -> %u Hz, PCLK %u Hz\n",
1373                 mmc_hostname(mmc), msmsdcc_fmin, msmsdcc_fmax, host->pclk_rate);
1374         pr_info("%s: Slot eject status = %d\n", mmc_hostname(mmc), host->eject);
1375         pr_info("%s: Power save feature enable = %d\n",
1376                 mmc_hostname(mmc), msmsdcc_pwrsave);
1377 
1378         if (host->dma.channel != -1) {
1379                 pr_info("%s: DM non-cached buffer at %p, dma_addr 0x%.8x\n",
1380                         mmc_hostname(mmc), host->dma.nc, host->dma.nc_busaddr);
1381                 pr_info("%s: DM cmd busaddr 0x%.8x, cmdptr busaddr 0x%.8x\n",
1382                         mmc_hostname(mmc), host->dma.cmd_busaddr,
1383                         host->dma.cmdptr_busaddr);
1384         } else
1385                 pr_info("%s: PIO transfer enabled\n", mmc_hostname(mmc));
1386         if (host->timer.function)
1387                 pr_info("%s: Polling status mode enabled\n", mmc_hostname(mmc));
1388 
1389         return 0;
1390  cmd_irq_free:
1391         free_irq(cmd_irqres->start, host);
1392  stat_irq_free:
1393         if (host->stat_irq)
1394                 free_irq(host->stat_irq, host);
1395  clk_disable:
1396         msmsdcc_disable_clocks(host, 0);
1397  clk_unprepare:
1398         clk_unprepare(host->clk);
1399  clk_unprepare_p:
1400         clk_unprepare(host->pclk);
1401  clk_put:
1402         clk_put(host->clk);
1403  pclk_put:
1404         clk_put(host->pclk);
1405 dma_free:
1406         if (host->dmares)
1407                 dma_free_coherent(NULL, sizeof(struct msmsdcc_nc_dmadata),
1408                                         host->dma.nc, host->dma.nc_busaddr);
1409 ioremap_free:
1410         tasklet_kill(&host->dma_tlet);
1411         iounmap(host->base);
1412  host_free:
1413         mmc_free_host(mmc);
1414  out:
1415         return ret;
1416 }
1417 
1418 #ifdef CONFIG_PM
1419 static int
1420 msmsdcc_suspend(struct platform_device *dev, pm_message_t state)
1421 {
1422         struct mmc_host *mmc = mmc_get_drvdata(dev);
1423 
1424         if (mmc) {
1425                 struct msmsdcc_host *host = mmc_priv(mmc);
1426 
1427                 if (host->stat_irq)
1428                         disable_irq(host->stat_irq);
1429 
1430                 msmsdcc_writel(host, 0, MMCIMASK0);
1431                 if (host->clks_on)
1432                         msmsdcc_disable_clocks(host, 0);
1433         }
1434         return 0;
1435 }
1436 
1437 static int
1438 msmsdcc_resume(struct platform_device *dev)
1439 {
1440         struct mmc_host *mmc = mmc_get_drvdata(dev);
1441 
1442         if (mmc) {
1443                 struct msmsdcc_host *host = mmc_priv(mmc);
1444 
1445                 msmsdcc_enable_clocks(host);
1446 
1447                 msmsdcc_writel(host, host->saved_irq0mask, MMCIMASK0);
1448 
1449                 if (host->stat_irq)
1450                         enable_irq(host->stat_irq);
1451 #if BUSCLK_PWRSAVE
1452                 msmsdcc_disable_clocks(host, 1);
1453 #endif
1454         }
1455         return 0;
1456 }
1457 #else
1458 #define msmsdcc_suspend 0
1459 #define msmsdcc_resume 0
1460 #endif
1461 
1462 static struct platform_driver msmsdcc_driver = {
1463         .probe          = msmsdcc_probe,
1464         .suspend        = msmsdcc_suspend,
1465         .resume         = msmsdcc_resume,
1466         .driver         = {
1467                 .name   = "msm_sdcc",
1468         },
1469 };
1470 
1471 module_platform_driver(msmsdcc_driver);
1472 
1473 MODULE_DESCRIPTION("Qualcomm MSM 7X00A Multimedia Card Interface driver");
1474 MODULE_LICENSE("GPL");
1475 

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