Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/mmc/host/jz4740_mmc.c

  1 /*
  2  *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
  3  *  JZ4740 SD/MMC controller driver
  4  *
  5  *  This program is free software; you can redistribute  it and/or modify it
  6  *  under  the terms of  the GNU General  Public License as published by the
  7  *  Free Software Foundation;  either version 2 of the  License, or (at your
  8  *  option) any later version.
  9  *
 10  *  You should have received a copy of the  GNU General Public License along
 11  *  with this program; if not, write  to the Free Software Foundation, Inc.,
 12  *  675 Mass Ave, Cambridge, MA 02139, USA.
 13  *
 14  */
 15 
 16 #include <linux/mmc/host.h>
 17 #include <linux/mmc/slot-gpio.h>
 18 #include <linux/err.h>
 19 #include <linux/io.h>
 20 #include <linux/irq.h>
 21 #include <linux/interrupt.h>
 22 #include <linux/module.h>
 23 #include <linux/platform_device.h>
 24 #include <linux/delay.h>
 25 #include <linux/scatterlist.h>
 26 #include <linux/clk.h>
 27 
 28 #include <linux/bitops.h>
 29 #include <linux/gpio.h>
 30 #include <asm/mach-jz4740/gpio.h>
 31 #include <asm/cacheflush.h>
 32 #include <linux/dma-mapping.h>
 33 
 34 #include <asm/mach-jz4740/jz4740_mmc.h>
 35 
 36 #define JZ_REG_MMC_STRPCL       0x00
 37 #define JZ_REG_MMC_STATUS       0x04
 38 #define JZ_REG_MMC_CLKRT        0x08
 39 #define JZ_REG_MMC_CMDAT        0x0C
 40 #define JZ_REG_MMC_RESTO        0x10
 41 #define JZ_REG_MMC_RDTO         0x14
 42 #define JZ_REG_MMC_BLKLEN       0x18
 43 #define JZ_REG_MMC_NOB          0x1C
 44 #define JZ_REG_MMC_SNOB         0x20
 45 #define JZ_REG_MMC_IMASK        0x24
 46 #define JZ_REG_MMC_IREG         0x28
 47 #define JZ_REG_MMC_CMD          0x2C
 48 #define JZ_REG_MMC_ARG          0x30
 49 #define JZ_REG_MMC_RESP_FIFO    0x34
 50 #define JZ_REG_MMC_RXFIFO       0x38
 51 #define JZ_REG_MMC_TXFIFO       0x3C
 52 
 53 #define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7)
 54 #define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6)
 55 #define JZ_MMC_STRPCL_START_READWAIT BIT(5)
 56 #define JZ_MMC_STRPCL_STOP_READWAIT BIT(4)
 57 #define JZ_MMC_STRPCL_RESET BIT(3)
 58 #define JZ_MMC_STRPCL_START_OP BIT(2)
 59 #define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0))
 60 #define JZ_MMC_STRPCL_CLOCK_STOP BIT(0)
 61 #define JZ_MMC_STRPCL_CLOCK_START BIT(1)
 62 
 63 
 64 #define JZ_MMC_STATUS_IS_RESETTING BIT(15)
 65 #define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14)
 66 #define JZ_MMC_STATUS_PRG_DONE BIT(13)
 67 #define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12)
 68 #define JZ_MMC_STATUS_END_CMD_RES BIT(11)
 69 #define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10)
 70 #define JZ_MMC_STATUS_IS_READWAIT BIT(9)
 71 #define JZ_MMC_STATUS_CLK_EN BIT(8)
 72 #define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7)
 73 #define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6)
 74 #define JZ_MMC_STATUS_CRC_RES_ERR BIT(5)
 75 #define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4)
 76 #define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3)
 77 #define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2)
 78 #define JZ_MMC_STATUS_TIMEOUT_RES BIT(1)
 79 #define JZ_MMC_STATUS_TIMEOUT_READ BIT(0)
 80 
 81 #define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0))
 82 #define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2))
 83 
 84 
 85 #define JZ_MMC_CMDAT_IO_ABORT BIT(11)
 86 #define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10)
 87 #define JZ_MMC_CMDAT_DMA_EN BIT(8)
 88 #define JZ_MMC_CMDAT_INIT BIT(7)
 89 #define JZ_MMC_CMDAT_BUSY BIT(6)
 90 #define JZ_MMC_CMDAT_STREAM BIT(5)
 91 #define JZ_MMC_CMDAT_WRITE BIT(4)
 92 #define JZ_MMC_CMDAT_DATA_EN BIT(3)
 93 #define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0))
 94 #define JZ_MMC_CMDAT_RSP_R1 1
 95 #define JZ_MMC_CMDAT_RSP_R2 2
 96 #define JZ_MMC_CMDAT_RSP_R3 3
 97 
 98 #define JZ_MMC_IRQ_SDIO BIT(7)
 99 #define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6)
100 #define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5)
101 #define JZ_MMC_IRQ_END_CMD_RES BIT(2)
102 #define JZ_MMC_IRQ_PRG_DONE BIT(1)
103 #define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0)
104 
105 
106 #define JZ_MMC_CLK_RATE 24000000
107 
108 enum jz4740_mmc_state {
109         JZ4740_MMC_STATE_READ_RESPONSE,
110         JZ4740_MMC_STATE_TRANSFER_DATA,
111         JZ4740_MMC_STATE_SEND_STOP,
112         JZ4740_MMC_STATE_DONE,
113 };
114 
115 struct jz4740_mmc_host {
116         struct mmc_host *mmc;
117         struct platform_device *pdev;
118         struct jz4740_mmc_platform_data *pdata;
119         struct clk *clk;
120 
121         int irq;
122         int card_detect_irq;
123 
124         void __iomem *base;
125         struct mmc_request *req;
126         struct mmc_command *cmd;
127 
128         unsigned long waiting;
129 
130         uint32_t cmdat;
131 
132         uint16_t irq_mask;
133 
134         spinlock_t lock;
135 
136         struct timer_list timeout_timer;
137         struct sg_mapping_iter miter;
138         enum jz4740_mmc_state state;
139 };
140 
141 static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host,
142         unsigned int irq, bool enabled)
143 {
144         unsigned long flags;
145 
146         spin_lock_irqsave(&host->lock, flags);
147         if (enabled)
148                 host->irq_mask &= ~irq;
149         else
150                 host->irq_mask |= irq;
151         spin_unlock_irqrestore(&host->lock, flags);
152 
153         writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
154 }
155 
156 static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host,
157         bool start_transfer)
158 {
159         uint16_t val = JZ_MMC_STRPCL_CLOCK_START;
160 
161         if (start_transfer)
162                 val |= JZ_MMC_STRPCL_START_OP;
163 
164         writew(val, host->base + JZ_REG_MMC_STRPCL);
165 }
166 
167 static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
168 {
169         uint32_t status;
170         unsigned int timeout = 1000;
171 
172         writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
173         do {
174                 status = readl(host->base + JZ_REG_MMC_STATUS);
175         } while (status & JZ_MMC_STATUS_CLK_EN && --timeout);
176 }
177 
178 static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
179 {
180         uint32_t status;
181         unsigned int timeout = 1000;
182 
183         writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
184         udelay(10);
185         do {
186                 status = readl(host->base + JZ_REG_MMC_STATUS);
187         } while (status & JZ_MMC_STATUS_IS_RESETTING && --timeout);
188 }
189 
190 static void jz4740_mmc_request_done(struct jz4740_mmc_host *host)
191 {
192         struct mmc_request *req;
193 
194         req = host->req;
195         host->req = NULL;
196 
197         mmc_request_done(host->mmc, req);
198 }
199 
200 static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host,
201         unsigned int irq)
202 {
203         unsigned int timeout = 0x800;
204         uint16_t status;
205 
206         do {
207                 status = readw(host->base + JZ_REG_MMC_IREG);
208         } while (!(status & irq) && --timeout);
209 
210         if (timeout == 0) {
211                 set_bit(0, &host->waiting);
212                 mod_timer(&host->timeout_timer, jiffies + 5*HZ);
213                 jz4740_mmc_set_irq_enabled(host, irq, true);
214                 return true;
215         }
216 
217         return false;
218 }
219 
220 static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host,
221         struct mmc_data *data)
222 {
223         int status;
224 
225         status = readl(host->base + JZ_REG_MMC_STATUS);
226         if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK) {
227                 if (status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) {
228                         host->req->cmd->error = -ETIMEDOUT;
229                         data->error = -ETIMEDOUT;
230                 } else {
231                         host->req->cmd->error = -EIO;
232                         data->error = -EIO;
233                 }
234         } else if (status & JZ_MMC_STATUS_READ_ERROR_MASK) {
235                 if (status & (JZ_MMC_STATUS_TIMEOUT_READ)) {
236                         host->req->cmd->error = -ETIMEDOUT;
237                         data->error = -ETIMEDOUT;
238                 } else {
239                         host->req->cmd->error = -EIO;
240                         data->error = -EIO;
241                 }
242         }
243 }
244 
245 static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host,
246         struct mmc_data *data)
247 {
248         struct sg_mapping_iter *miter = &host->miter;
249         void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO;
250         uint32_t *buf;
251         bool timeout;
252         size_t i, j;
253 
254         while (sg_miter_next(miter)) {
255                 buf = miter->addr;
256                 i = miter->length / 4;
257                 j = i / 8;
258                 i = i & 0x7;
259                 while (j) {
260                         timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
261                         if (unlikely(timeout))
262                                 goto poll_timeout;
263 
264                         writel(buf[0], fifo_addr);
265                         writel(buf[1], fifo_addr);
266                         writel(buf[2], fifo_addr);
267                         writel(buf[3], fifo_addr);
268                         writel(buf[4], fifo_addr);
269                         writel(buf[5], fifo_addr);
270                         writel(buf[6], fifo_addr);
271                         writel(buf[7], fifo_addr);
272                         buf += 8;
273                         --j;
274                 }
275                 if (unlikely(i)) {
276                         timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
277                         if (unlikely(timeout))
278                                 goto poll_timeout;
279 
280                         while (i) {
281                                 writel(*buf, fifo_addr);
282                                 ++buf;
283                                 --i;
284                         }
285                 }
286                 data->bytes_xfered += miter->length;
287         }
288         sg_miter_stop(miter);
289 
290         return false;
291 
292 poll_timeout:
293         miter->consumed = (void *)buf - miter->addr;
294         data->bytes_xfered += miter->consumed;
295         sg_miter_stop(miter);
296 
297         return true;
298 }
299 
300 static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host,
301                                 struct mmc_data *data)
302 {
303         struct sg_mapping_iter *miter = &host->miter;
304         void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO;
305         uint32_t *buf;
306         uint32_t d;
307         uint16_t status;
308         size_t i, j;
309         unsigned int timeout;
310 
311         while (sg_miter_next(miter)) {
312                 buf = miter->addr;
313                 i = miter->length;
314                 j = i / 32;
315                 i = i & 0x1f;
316                 while (j) {
317                         timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
318                         if (unlikely(timeout))
319                                 goto poll_timeout;
320 
321                         buf[0] = readl(fifo_addr);
322                         buf[1] = readl(fifo_addr);
323                         buf[2] = readl(fifo_addr);
324                         buf[3] = readl(fifo_addr);
325                         buf[4] = readl(fifo_addr);
326                         buf[5] = readl(fifo_addr);
327                         buf[6] = readl(fifo_addr);
328                         buf[7] = readl(fifo_addr);
329 
330                         buf += 8;
331                         --j;
332                 }
333 
334                 if (unlikely(i)) {
335                         timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
336                         if (unlikely(timeout))
337                                 goto poll_timeout;
338 
339                         while (i >= 4) {
340                                 *buf++ = readl(fifo_addr);
341                                 i -= 4;
342                         }
343                         if (unlikely(i > 0)) {
344                                 d = readl(fifo_addr);
345                                 memcpy(buf, &d, i);
346                         }
347                 }
348                 data->bytes_xfered += miter->length;
349 
350                 /* This can go away once MIPS implements
351                  * flush_kernel_dcache_page */
352                 flush_dcache_page(miter->page);
353         }
354         sg_miter_stop(miter);
355 
356         /* For whatever reason there is sometime one word more in the fifo then
357          * requested */
358         timeout = 1000;
359         status = readl(host->base + JZ_REG_MMC_STATUS);
360         while (!(status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout) {
361                 d = readl(fifo_addr);
362                 status = readl(host->base + JZ_REG_MMC_STATUS);
363         }
364 
365         return false;
366 
367 poll_timeout:
368         miter->consumed = (void *)buf - miter->addr;
369         data->bytes_xfered += miter->consumed;
370         sg_miter_stop(miter);
371 
372         return true;
373 }
374 
375 static void jz4740_mmc_timeout(unsigned long data)
376 {
377         struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)data;
378 
379         if (!test_and_clear_bit(0, &host->waiting))
380                 return;
381 
382         jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false);
383 
384         host->req->cmd->error = -ETIMEDOUT;
385         jz4740_mmc_request_done(host);
386 }
387 
388 static void jz4740_mmc_read_response(struct jz4740_mmc_host *host,
389         struct mmc_command *cmd)
390 {
391         int i;
392         uint16_t tmp;
393         void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO;
394 
395         if (cmd->flags & MMC_RSP_136) {
396                 tmp = readw(fifo_addr);
397                 for (i = 0; i < 4; ++i) {
398                         cmd->resp[i] = tmp << 24;
399                         tmp = readw(fifo_addr);
400                         cmd->resp[i] |= tmp << 8;
401                         tmp = readw(fifo_addr);
402                         cmd->resp[i] |= tmp >> 8;
403                 }
404         } else {
405                 cmd->resp[0] = readw(fifo_addr) << 24;
406                 cmd->resp[0] |= readw(fifo_addr) << 8;
407                 cmd->resp[0] |= readw(fifo_addr) & 0xff;
408         }
409 }
410 
411 static void jz4740_mmc_send_command(struct jz4740_mmc_host *host,
412         struct mmc_command *cmd)
413 {
414         uint32_t cmdat = host->cmdat;
415 
416         host->cmdat &= ~JZ_MMC_CMDAT_INIT;
417         jz4740_mmc_clock_disable(host);
418 
419         host->cmd = cmd;
420 
421         if (cmd->flags & MMC_RSP_BUSY)
422                 cmdat |= JZ_MMC_CMDAT_BUSY;
423 
424         switch (mmc_resp_type(cmd)) {
425         case MMC_RSP_R1B:
426         case MMC_RSP_R1:
427                 cmdat |= JZ_MMC_CMDAT_RSP_R1;
428                 break;
429         case MMC_RSP_R2:
430                 cmdat |= JZ_MMC_CMDAT_RSP_R2;
431                 break;
432         case MMC_RSP_R3:
433                 cmdat |= JZ_MMC_CMDAT_RSP_R3;
434                 break;
435         default:
436                 break;
437         }
438 
439         if (cmd->data) {
440                 cmdat |= JZ_MMC_CMDAT_DATA_EN;
441                 if (cmd->data->flags & MMC_DATA_WRITE)
442                         cmdat |= JZ_MMC_CMDAT_WRITE;
443                 if (cmd->data->flags & MMC_DATA_STREAM)
444                         cmdat |= JZ_MMC_CMDAT_STREAM;
445 
446                 writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
447                 writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
448         }
449 
450         writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD);
451         writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
452         writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
453 
454         jz4740_mmc_clock_enable(host, 1);
455 }
456 
457 static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host)
458 {
459         struct mmc_command *cmd = host->req->cmd;
460         struct mmc_data *data = cmd->data;
461         int direction;
462 
463         if (data->flags & MMC_DATA_READ)
464                 direction = SG_MITER_TO_SG;
465         else
466                 direction = SG_MITER_FROM_SG;
467 
468         sg_miter_start(&host->miter, data->sg, data->sg_len, direction);
469 }
470 
471 
472 static irqreturn_t jz_mmc_irq_worker(int irq, void *devid)
473 {
474         struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid;
475         struct mmc_command *cmd = host->req->cmd;
476         struct mmc_request *req = host->req;
477         bool timeout = false;
478 
479         if (cmd->error)
480                 host->state = JZ4740_MMC_STATE_DONE;
481 
482         switch (host->state) {
483         case JZ4740_MMC_STATE_READ_RESPONSE:
484                 if (cmd->flags & MMC_RSP_PRESENT)
485                         jz4740_mmc_read_response(host, cmd);
486 
487                 if (!cmd->data)
488                         break;
489 
490                 jz_mmc_prepare_data_transfer(host);
491 
492         case JZ4740_MMC_STATE_TRANSFER_DATA:
493                 if (cmd->data->flags & MMC_DATA_READ)
494                         timeout = jz4740_mmc_read_data(host, cmd->data);
495                 else
496                         timeout = jz4740_mmc_write_data(host, cmd->data);
497 
498                 if (unlikely(timeout)) {
499                         host->state = JZ4740_MMC_STATE_TRANSFER_DATA;
500                         break;
501                 }
502 
503                 jz4740_mmc_transfer_check_state(host, cmd->data);
504 
505                 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE);
506                 if (unlikely(timeout)) {
507                         host->state = JZ4740_MMC_STATE_SEND_STOP;
508                         break;
509                 }
510                 writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG);
511 
512         case JZ4740_MMC_STATE_SEND_STOP:
513                 if (!req->stop)
514                         break;
515 
516                 jz4740_mmc_send_command(host, req->stop);
517 
518                 if (mmc_resp_type(req->stop) & MMC_RSP_BUSY) {
519                         timeout = jz4740_mmc_poll_irq(host,
520                                                       JZ_MMC_IRQ_PRG_DONE);
521                         if (timeout) {
522                                 host->state = JZ4740_MMC_STATE_DONE;
523                                 break;
524                         }
525                 }
526         case JZ4740_MMC_STATE_DONE:
527                 break;
528         }
529 
530         if (!timeout)
531                 jz4740_mmc_request_done(host);
532 
533         return IRQ_HANDLED;
534 }
535 
536 static irqreturn_t jz_mmc_irq(int irq, void *devid)
537 {
538         struct jz4740_mmc_host *host = devid;
539         struct mmc_command *cmd = host->cmd;
540         uint16_t irq_reg, status, tmp;
541 
542         irq_reg = readw(host->base + JZ_REG_MMC_IREG);
543 
544         tmp = irq_reg;
545         irq_reg &= ~host->irq_mask;
546 
547         tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ |
548                 JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE);
549 
550         if (tmp != irq_reg)
551                 writew(tmp & ~irq_reg, host->base + JZ_REG_MMC_IREG);
552 
553         if (irq_reg & JZ_MMC_IRQ_SDIO) {
554                 writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG);
555                 mmc_signal_sdio_irq(host->mmc);
556                 irq_reg &= ~JZ_MMC_IRQ_SDIO;
557         }
558 
559         if (host->req && cmd && irq_reg) {
560                 if (test_and_clear_bit(0, &host->waiting)) {
561                         del_timer(&host->timeout_timer);
562 
563                         status = readl(host->base + JZ_REG_MMC_STATUS);
564 
565                         if (status & JZ_MMC_STATUS_TIMEOUT_RES) {
566                                         cmd->error = -ETIMEDOUT;
567                         } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) {
568                                         cmd->error = -EIO;
569                         } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR |
570                                     JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
571                                         if (cmd->data)
572                                                         cmd->data->error = -EIO;
573                                         cmd->error = -EIO;
574                         }
575 
576                         jz4740_mmc_set_irq_enabled(host, irq_reg, false);
577                         writew(irq_reg, host->base + JZ_REG_MMC_IREG);
578 
579                         return IRQ_WAKE_THREAD;
580                 }
581         }
582 
583         return IRQ_HANDLED;
584 }
585 
586 static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate)
587 {
588         int div = 0;
589         int real_rate;
590 
591         jz4740_mmc_clock_disable(host);
592         clk_set_rate(host->clk, JZ_MMC_CLK_RATE);
593 
594         real_rate = clk_get_rate(host->clk);
595 
596         while (real_rate > rate && div < 7) {
597                 ++div;
598                 real_rate >>= 1;
599         }
600 
601         writew(div, host->base + JZ_REG_MMC_CLKRT);
602         return real_rate;
603 }
604 
605 static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
606 {
607         struct jz4740_mmc_host *host = mmc_priv(mmc);
608 
609         host->req = req;
610 
611         writew(0xffff, host->base + JZ_REG_MMC_IREG);
612 
613         writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
614         jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true);
615 
616         host->state = JZ4740_MMC_STATE_READ_RESPONSE;
617         set_bit(0, &host->waiting);
618         mod_timer(&host->timeout_timer, jiffies + 5*HZ);
619         jz4740_mmc_send_command(host, req->cmd);
620 }
621 
622 static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
623 {
624         struct jz4740_mmc_host *host = mmc_priv(mmc);
625         if (ios->clock)
626                 jz4740_mmc_set_clock_rate(host, ios->clock);
627 
628         switch (ios->power_mode) {
629         case MMC_POWER_UP:
630                 jz4740_mmc_reset(host);
631                 if (gpio_is_valid(host->pdata->gpio_power))
632                         gpio_set_value(host->pdata->gpio_power,
633                                         !host->pdata->power_active_low);
634                 host->cmdat |= JZ_MMC_CMDAT_INIT;
635                 clk_prepare_enable(host->clk);
636                 break;
637         case MMC_POWER_ON:
638                 break;
639         default:
640                 if (gpio_is_valid(host->pdata->gpio_power))
641                         gpio_set_value(host->pdata->gpio_power,
642                                         host->pdata->power_active_low);
643                 clk_disable_unprepare(host->clk);
644                 break;
645         }
646 
647         switch (ios->bus_width) {
648         case MMC_BUS_WIDTH_1:
649                 host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
650                 break;
651         case MMC_BUS_WIDTH_4:
652                 host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
653                 break;
654         default:
655                 break;
656         }
657 }
658 
659 static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
660 {
661         struct jz4740_mmc_host *host = mmc_priv(mmc);
662         jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable);
663 }
664 
665 static const struct mmc_host_ops jz4740_mmc_ops = {
666         .request        = jz4740_mmc_request,
667         .set_ios        = jz4740_mmc_set_ios,
668         .get_ro         = mmc_gpio_get_ro,
669         .get_cd         = mmc_gpio_get_cd,
670         .enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
671 };
672 
673 static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = {
674         JZ_GPIO_BULK_PIN(MSC_CMD),
675         JZ_GPIO_BULK_PIN(MSC_CLK),
676         JZ_GPIO_BULK_PIN(MSC_DATA0),
677         JZ_GPIO_BULK_PIN(MSC_DATA1),
678         JZ_GPIO_BULK_PIN(MSC_DATA2),
679         JZ_GPIO_BULK_PIN(MSC_DATA3),
680 };
681 
682 static int jz4740_mmc_request_gpio(struct device *dev, int gpio,
683         const char *name, bool output, int value)
684 {
685         int ret;
686 
687         if (!gpio_is_valid(gpio))
688                 return 0;
689 
690         ret = gpio_request(gpio, name);
691         if (ret) {
692                 dev_err(dev, "Failed to request %s gpio: %d\n", name, ret);
693                 return ret;
694         }
695 
696         if (output)
697                 gpio_direction_output(gpio, value);
698         else
699                 gpio_direction_input(gpio);
700 
701         return 0;
702 }
703 
704 static int jz4740_mmc_request_gpios(struct mmc_host *mmc,
705         struct platform_device *pdev)
706 {
707         struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
708         int ret = 0;
709 
710         if (!pdata)
711                 return 0;
712 
713         if (!pdata->card_detect_active_low)
714                 mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
715         if (!pdata->read_only_active_low)
716                 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
717 
718         if (gpio_is_valid(pdata->gpio_card_detect)) {
719                 ret = mmc_gpio_request_cd(mmc, pdata->gpio_card_detect, 0);
720                 if (ret)
721                         return ret;
722         }
723 
724         if (gpio_is_valid(pdata->gpio_read_only)) {
725                 ret = mmc_gpio_request_ro(mmc, pdata->gpio_read_only);
726                 if (ret)
727                         return ret;
728         }
729 
730         return jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_power,
731                         "MMC read only", true, pdata->power_active_low);
732 }
733 
734 static void jz4740_mmc_free_gpios(struct platform_device *pdev)
735 {
736         struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
737 
738         if (!pdata)
739                 return;
740 
741         if (gpio_is_valid(pdata->gpio_power))
742                 gpio_free(pdata->gpio_power);
743 }
744 
745 static inline size_t jz4740_mmc_num_pins(struct jz4740_mmc_host *host)
746 {
747         size_t num_pins = ARRAY_SIZE(jz4740_mmc_pins);
748         if (host->pdata && host->pdata->data_1bit)
749                 num_pins -= 3;
750 
751         return num_pins;
752 }
753 
754 static int jz4740_mmc_probe(struct platform_device* pdev)
755 {
756         int ret;
757         struct mmc_host *mmc;
758         struct jz4740_mmc_host *host;
759         struct jz4740_mmc_platform_data *pdata;
760         struct resource *res;
761 
762         pdata = pdev->dev.platform_data;
763 
764         mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev);
765         if (!mmc) {
766                 dev_err(&pdev->dev, "Failed to alloc mmc host structure\n");
767                 return -ENOMEM;
768         }
769 
770         host = mmc_priv(mmc);
771         host->pdata = pdata;
772 
773         host->irq = platform_get_irq(pdev, 0);
774         if (host->irq < 0) {
775                 ret = host->irq;
776                 dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
777                 goto err_free_host;
778         }
779 
780         host->clk = devm_clk_get(&pdev->dev, "mmc");
781         if (IS_ERR(host->clk)) {
782                 ret = PTR_ERR(host->clk);
783                 dev_err(&pdev->dev, "Failed to get mmc clock\n");
784                 goto err_free_host;
785         }
786 
787         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
788         host->base = devm_ioremap_resource(&pdev->dev, res);
789         if (IS_ERR(host->base)) {
790                 ret = PTR_ERR(host->base);
791                 goto err_free_host;
792         }
793 
794         ret = jz_gpio_bulk_request(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
795         if (ret) {
796                 dev_err(&pdev->dev, "Failed to request mmc pins: %d\n", ret);
797                 goto err_free_host;
798         }
799 
800         ret = jz4740_mmc_request_gpios(mmc, pdev);
801         if (ret)
802                 goto err_gpio_bulk_free;
803 
804         mmc->ops = &jz4740_mmc_ops;
805         mmc->f_min = JZ_MMC_CLK_RATE / 128;
806         mmc->f_max = JZ_MMC_CLK_RATE;
807         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
808         mmc->caps = (pdata && pdata->data_1bit) ? 0 : MMC_CAP_4_BIT_DATA;
809         mmc->caps |= MMC_CAP_SDIO_IRQ;
810 
811         mmc->max_blk_size = (1 << 10) - 1;
812         mmc->max_blk_count = (1 << 15) - 1;
813         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
814 
815         mmc->max_segs = 128;
816         mmc->max_seg_size = mmc->max_req_size;
817 
818         host->mmc = mmc;
819         host->pdev = pdev;
820         spin_lock_init(&host->lock);
821         host->irq_mask = 0xffff;
822 
823         ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0,
824                         dev_name(&pdev->dev), host);
825         if (ret) {
826                 dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
827                 goto err_free_gpios;
828         }
829 
830         jz4740_mmc_reset(host);
831         jz4740_mmc_clock_disable(host);
832         setup_timer(&host->timeout_timer, jz4740_mmc_timeout,
833                         (unsigned long)host);
834         /* It is not important when it times out, it just needs to timeout. */
835         set_timer_slack(&host->timeout_timer, HZ);
836 
837         platform_set_drvdata(pdev, host);
838         ret = mmc_add_host(mmc);
839 
840         if (ret) {
841                 dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret);
842                 goto err_free_irq;
843         }
844         dev_info(&pdev->dev, "JZ SD/MMC card driver registered\n");
845 
846         return 0;
847 
848 err_free_irq:
849         free_irq(host->irq, host);
850 err_free_gpios:
851         jz4740_mmc_free_gpios(pdev);
852 err_gpio_bulk_free:
853         jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
854 err_free_host:
855         mmc_free_host(mmc);
856 
857         return ret;
858 }
859 
860 static int jz4740_mmc_remove(struct platform_device *pdev)
861 {
862         struct jz4740_mmc_host *host = platform_get_drvdata(pdev);
863 
864         del_timer_sync(&host->timeout_timer);
865         jz4740_mmc_set_irq_enabled(host, 0xff, false);
866         jz4740_mmc_reset(host);
867 
868         mmc_remove_host(host->mmc);
869 
870         free_irq(host->irq, host);
871 
872         jz4740_mmc_free_gpios(pdev);
873         jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
874 
875         mmc_free_host(host->mmc);
876 
877         return 0;
878 }
879 
880 #ifdef CONFIG_PM_SLEEP
881 
882 static int jz4740_mmc_suspend(struct device *dev)
883 {
884         struct jz4740_mmc_host *host = dev_get_drvdata(dev);
885 
886         jz_gpio_bulk_suspend(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
887 
888         return 0;
889 }
890 
891 static int jz4740_mmc_resume(struct device *dev)
892 {
893         struct jz4740_mmc_host *host = dev_get_drvdata(dev);
894 
895         jz_gpio_bulk_resume(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
896 
897         return 0;
898 }
899 
900 static SIMPLE_DEV_PM_OPS(jz4740_mmc_pm_ops, jz4740_mmc_suspend,
901         jz4740_mmc_resume);
902 #define JZ4740_MMC_PM_OPS (&jz4740_mmc_pm_ops)
903 #else
904 #define JZ4740_MMC_PM_OPS NULL
905 #endif
906 
907 static struct platform_driver jz4740_mmc_driver = {
908         .probe = jz4740_mmc_probe,
909         .remove = jz4740_mmc_remove,
910         .driver = {
911                 .name = "jz4740-mmc",
912                 .owner = THIS_MODULE,
913                 .pm = JZ4740_MMC_PM_OPS,
914         },
915 };
916 
917 module_platform_driver(jz4740_mmc_driver);
918 
919 MODULE_DESCRIPTION("JZ4740 SD/MMC controller driver");
920 MODULE_LICENSE("GPL");
921 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
922 

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