Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4

Linux/drivers/mmc/host/dw_mmc.c

  1 /*
  2  * Synopsys DesignWare Multimedia Card Interface driver
  3  *  (Based on NXP driver for lpc 31xx)
  4  *
  5  * Copyright (C) 2009 NXP Semiconductors
  6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License, or
 11  * (at your option) any later version.
 12  */
 13 
 14 #include <linux/blkdev.h>
 15 #include <linux/clk.h>
 16 #include <linux/debugfs.h>
 17 #include <linux/device.h>
 18 #include <linux/dma-mapping.h>
 19 #include <linux/err.h>
 20 #include <linux/init.h>
 21 #include <linux/interrupt.h>
 22 #include <linux/ioport.h>
 23 #include <linux/module.h>
 24 #include <linux/platform_device.h>
 25 #include <linux/seq_file.h>
 26 #include <linux/slab.h>
 27 #include <linux/stat.h>
 28 #include <linux/delay.h>
 29 #include <linux/irq.h>
 30 #include <linux/mmc/card.h>
 31 #include <linux/mmc/host.h>
 32 #include <linux/mmc/mmc.h>
 33 #include <linux/mmc/sd.h>
 34 #include <linux/mmc/sdio.h>
 35 #include <linux/mmc/dw_mmc.h>
 36 #include <linux/bitops.h>
 37 #include <linux/regulator/consumer.h>
 38 #include <linux/of.h>
 39 #include <linux/of_gpio.h>
 40 #include <linux/mmc/slot-gpio.h>
 41 
 42 #include "dw_mmc.h"
 43 
 44 /* Common flag combinations */
 45 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
 46                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
 47                                  SDMMC_INT_EBE)
 48 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
 49                                  SDMMC_INT_RESP_ERR)
 50 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
 51                                  DW_MCI_CMD_ERROR_FLAGS  | SDMMC_INT_HLE)
 52 #define DW_MCI_SEND_STATUS      1
 53 #define DW_MCI_RECV_STATUS      2
 54 #define DW_MCI_DMA_THRESHOLD    16
 55 
 56 #define DW_MCI_FREQ_MAX 200000000       /* unit: HZ */
 57 #define DW_MCI_FREQ_MIN 400000          /* unit: HZ */
 58 
 59 #define IDMAC_INT_CLR           (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
 60                                  SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
 61                                  SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
 62                                  SDMMC_IDMAC_INT_TI)
 63 
 64 struct idmac_desc_64addr {
 65         u32             des0;   /* Control Descriptor */
 66 
 67         u32             des1;   /* Reserved */
 68 
 69         u32             des2;   /*Buffer sizes */
 70 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
 71         ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
 72          ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
 73 
 74         u32             des3;   /* Reserved */
 75 
 76         u32             des4;   /* Lower 32-bits of Buffer Address Pointer 1*/
 77         u32             des5;   /* Upper 32-bits of Buffer Address Pointer 1*/
 78 
 79         u32             des6;   /* Lower 32-bits of Next Descriptor Address */
 80         u32             des7;   /* Upper 32-bits of Next Descriptor Address */
 81 };
 82 
 83 struct idmac_desc {
 84         __le32          des0;   /* Control Descriptor */
 85 #define IDMAC_DES0_DIC  BIT(1)
 86 #define IDMAC_DES0_LD   BIT(2)
 87 #define IDMAC_DES0_FD   BIT(3)
 88 #define IDMAC_DES0_CH   BIT(4)
 89 #define IDMAC_DES0_ER   BIT(5)
 90 #define IDMAC_DES0_CES  BIT(30)
 91 #define IDMAC_DES0_OWN  BIT(31)
 92 
 93         __le32          des1;   /* Buffer sizes */
 94 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
 95         ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
 96 
 97         __le32          des2;   /* buffer 1 physical address */
 98 
 99         __le32          des3;   /* buffer 2 physical address */
100 };
101 
102 /* Each descriptor can transfer up to 4KB of data in chained mode */
103 #define DW_MCI_DESC_DATA_LENGTH 0x1000
104 
105 static bool dw_mci_reset(struct dw_mci *host);
106 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
107 static int dw_mci_card_busy(struct mmc_host *mmc);
108 
109 #if defined(CONFIG_DEBUG_FS)
110 static int dw_mci_req_show(struct seq_file *s, void *v)
111 {
112         struct dw_mci_slot *slot = s->private;
113         struct mmc_request *mrq;
114         struct mmc_command *cmd;
115         struct mmc_command *stop;
116         struct mmc_data *data;
117 
118         /* Make sure we get a consistent snapshot */
119         spin_lock_bh(&slot->host->lock);
120         mrq = slot->mrq;
121 
122         if (mrq) {
123                 cmd = mrq->cmd;
124                 data = mrq->data;
125                 stop = mrq->stop;
126 
127                 if (cmd)
128                         seq_printf(s,
129                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
130                                    cmd->opcode, cmd->arg, cmd->flags,
131                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
132                                    cmd->resp[2], cmd->error);
133                 if (data)
134                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
135                                    data->bytes_xfered, data->blocks,
136                                    data->blksz, data->flags, data->error);
137                 if (stop)
138                         seq_printf(s,
139                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
140                                    stop->opcode, stop->arg, stop->flags,
141                                    stop->resp[0], stop->resp[1], stop->resp[2],
142                                    stop->resp[2], stop->error);
143         }
144 
145         spin_unlock_bh(&slot->host->lock);
146 
147         return 0;
148 }
149 
150 static int dw_mci_req_open(struct inode *inode, struct file *file)
151 {
152         return single_open(file, dw_mci_req_show, inode->i_private);
153 }
154 
155 static const struct file_operations dw_mci_req_fops = {
156         .owner          = THIS_MODULE,
157         .open           = dw_mci_req_open,
158         .read           = seq_read,
159         .llseek         = seq_lseek,
160         .release        = single_release,
161 };
162 
163 static int dw_mci_regs_show(struct seq_file *s, void *v)
164 {
165         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
166         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
167         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
168         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
169         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
170         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
171 
172         return 0;
173 }
174 
175 static int dw_mci_regs_open(struct inode *inode, struct file *file)
176 {
177         return single_open(file, dw_mci_regs_show, inode->i_private);
178 }
179 
180 static const struct file_operations dw_mci_regs_fops = {
181         .owner          = THIS_MODULE,
182         .open           = dw_mci_regs_open,
183         .read           = seq_read,
184         .llseek         = seq_lseek,
185         .release        = single_release,
186 };
187 
188 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
189 {
190         struct mmc_host *mmc = slot->mmc;
191         struct dw_mci *host = slot->host;
192         struct dentry *root;
193         struct dentry *node;
194 
195         root = mmc->debugfs_root;
196         if (!root)
197                 return;
198 
199         node = debugfs_create_file("regs", S_IRUSR, root, host,
200                                    &dw_mci_regs_fops);
201         if (!node)
202                 goto err;
203 
204         node = debugfs_create_file("req", S_IRUSR, root, slot,
205                                    &dw_mci_req_fops);
206         if (!node)
207                 goto err;
208 
209         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
210         if (!node)
211                 goto err;
212 
213         node = debugfs_create_x32("pending_events", S_IRUSR, root,
214                                   (u32 *)&host->pending_events);
215         if (!node)
216                 goto err;
217 
218         node = debugfs_create_x32("completed_events", S_IRUSR, root,
219                                   (u32 *)&host->completed_events);
220         if (!node)
221                 goto err;
222 
223         return;
224 
225 err:
226         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
227 }
228 #endif /* defined(CONFIG_DEBUG_FS) */
229 
230 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
231 
232 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
233 {
234         struct mmc_data *data;
235         struct dw_mci_slot *slot = mmc_priv(mmc);
236         struct dw_mci *host = slot->host;
237         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
238         u32 cmdr;
239 
240         cmd->error = -EINPROGRESS;
241         cmdr = cmd->opcode;
242 
243         if (cmd->opcode == MMC_STOP_TRANSMISSION ||
244             cmd->opcode == MMC_GO_IDLE_STATE ||
245             cmd->opcode == MMC_GO_INACTIVE_STATE ||
246             (cmd->opcode == SD_IO_RW_DIRECT &&
247              ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
248                 cmdr |= SDMMC_CMD_STOP;
249         else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
250                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
251 
252         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
253                 u32 clk_en_a;
254 
255                 /* Special bit makes CMD11 not die */
256                 cmdr |= SDMMC_CMD_VOLT_SWITCH;
257 
258                 /* Change state to continue to handle CMD11 weirdness */
259                 WARN_ON(slot->host->state != STATE_SENDING_CMD);
260                 slot->host->state = STATE_SENDING_CMD11;
261 
262                 /*
263                  * We need to disable low power mode (automatic clock stop)
264                  * while doing voltage switch so we don't confuse the card,
265                  * since stopping the clock is a specific part of the UHS
266                  * voltage change dance.
267                  *
268                  * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
269                  * unconditionally turned back on in dw_mci_setup_bus() if it's
270                  * ever called with a non-zero clock.  That shouldn't happen
271                  * until the voltage change is all done.
272                  */
273                 clk_en_a = mci_readl(host, CLKENA);
274                 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
275                 mci_writel(host, CLKENA, clk_en_a);
276                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
277                              SDMMC_CMD_PRV_DAT_WAIT, 0);
278         }
279 
280         if (cmd->flags & MMC_RSP_PRESENT) {
281                 /* We expect a response, so set this bit */
282                 cmdr |= SDMMC_CMD_RESP_EXP;
283                 if (cmd->flags & MMC_RSP_136)
284                         cmdr |= SDMMC_CMD_RESP_LONG;
285         }
286 
287         if (cmd->flags & MMC_RSP_CRC)
288                 cmdr |= SDMMC_CMD_RESP_CRC;
289 
290         data = cmd->data;
291         if (data) {
292                 cmdr |= SDMMC_CMD_DAT_EXP;
293                 if (data->flags & MMC_DATA_STREAM)
294                         cmdr |= SDMMC_CMD_STRM_MODE;
295                 if (data->flags & MMC_DATA_WRITE)
296                         cmdr |= SDMMC_CMD_DAT_WR;
297         }
298 
299         if (drv_data && drv_data->prepare_command)
300                 drv_data->prepare_command(slot->host, &cmdr);
301 
302         return cmdr;
303 }
304 
305 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
306 {
307         struct mmc_command *stop;
308         u32 cmdr;
309 
310         if (!cmd->data)
311                 return 0;
312 
313         stop = &host->stop_abort;
314         cmdr = cmd->opcode;
315         memset(stop, 0, sizeof(struct mmc_command));
316 
317         if (cmdr == MMC_READ_SINGLE_BLOCK ||
318             cmdr == MMC_READ_MULTIPLE_BLOCK ||
319             cmdr == MMC_WRITE_BLOCK ||
320             cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
321             cmdr == MMC_SEND_TUNING_BLOCK ||
322             cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
323                 stop->opcode = MMC_STOP_TRANSMISSION;
324                 stop->arg = 0;
325                 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
326         } else if (cmdr == SD_IO_RW_EXTENDED) {
327                 stop->opcode = SD_IO_RW_DIRECT;
328                 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
329                              ((cmd->arg >> 28) & 0x7);
330                 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
331         } else {
332                 return 0;
333         }
334 
335         cmdr = stop->opcode | SDMMC_CMD_STOP |
336                 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
337 
338         return cmdr;
339 }
340 
341 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
342 {
343         unsigned long timeout = jiffies + msecs_to_jiffies(500);
344 
345         /*
346          * Databook says that before issuing a new data transfer command
347          * we need to check to see if the card is busy.  Data transfer commands
348          * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
349          *
350          * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
351          * expected.
352          */
353         if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
354             !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
355                 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {
356                         if (time_after(jiffies, timeout)) {
357                                 /* Command will fail; we'll pass error then */
358                                 dev_err(host->dev, "Busy; trying anyway\n");
359                                 break;
360                         }
361                         udelay(10);
362                 }
363         }
364 }
365 
366 static void dw_mci_start_command(struct dw_mci *host,
367                                  struct mmc_command *cmd, u32 cmd_flags)
368 {
369         host->cmd = cmd;
370         dev_vdbg(host->dev,
371                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
372                  cmd->arg, cmd_flags);
373 
374         mci_writel(host, CMDARG, cmd->arg);
375         wmb(); /* drain writebuffer */
376         dw_mci_wait_while_busy(host, cmd_flags);
377 
378         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
379 }
380 
381 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
382 {
383         struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
384 
385         dw_mci_start_command(host, stop, host->stop_cmdr);
386 }
387 
388 /* DMA interface functions */
389 static void dw_mci_stop_dma(struct dw_mci *host)
390 {
391         if (host->using_dma) {
392                 host->dma_ops->stop(host);
393                 host->dma_ops->cleanup(host);
394         }
395 
396         /* Data transfer was stopped by the interrupt handler */
397         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
398 }
399 
400 static int dw_mci_get_dma_dir(struct mmc_data *data)
401 {
402         if (data->flags & MMC_DATA_WRITE)
403                 return DMA_TO_DEVICE;
404         else
405                 return DMA_FROM_DEVICE;
406 }
407 
408 static void dw_mci_dma_cleanup(struct dw_mci *host)
409 {
410         struct mmc_data *data = host->data;
411 
412         if (data)
413                 if (!data->host_cookie)
414                         dma_unmap_sg(host->dev,
415                                      data->sg,
416                                      data->sg_len,
417                                      dw_mci_get_dma_dir(data));
418 }
419 
420 static void dw_mci_idmac_reset(struct dw_mci *host)
421 {
422         u32 bmod = mci_readl(host, BMOD);
423         /* Software reset of DMA */
424         bmod |= SDMMC_IDMAC_SWRESET;
425         mci_writel(host, BMOD, bmod);
426 }
427 
428 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
429 {
430         u32 temp;
431 
432         /* Disable and reset the IDMAC interface */
433         temp = mci_readl(host, CTRL);
434         temp &= ~SDMMC_CTRL_USE_IDMAC;
435         temp |= SDMMC_CTRL_DMA_RESET;
436         mci_writel(host, CTRL, temp);
437 
438         /* Stop the IDMAC running */
439         temp = mci_readl(host, BMOD);
440         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
441         temp |= SDMMC_IDMAC_SWRESET;
442         mci_writel(host, BMOD, temp);
443 }
444 
445 static void dw_mci_dmac_complete_dma(void *arg)
446 {
447         struct dw_mci *host = arg;
448         struct mmc_data *data = host->data;
449 
450         dev_vdbg(host->dev, "DMA complete\n");
451 
452         if ((host->use_dma == TRANS_MODE_EDMAC) &&
453             data && (data->flags & MMC_DATA_READ))
454                 /* Invalidate cache after read */
455                 dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc),
456                                     data->sg,
457                                     data->sg_len,
458                                     DMA_FROM_DEVICE);
459 
460         host->dma_ops->cleanup(host);
461 
462         /*
463          * If the card was removed, data will be NULL. No point in trying to
464          * send the stop command or waiting for NBUSY in this case.
465          */
466         if (data) {
467                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
468                 tasklet_schedule(&host->tasklet);
469         }
470 }
471 
472 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
473                                     unsigned int sg_len)
474 {
475         unsigned int desc_len;
476         int i;
477 
478         if (host->dma_64bit_address == 1) {
479                 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
480 
481                 desc_first = desc_last = desc = host->sg_cpu;
482 
483                 for (i = 0; i < sg_len; i++) {
484                         unsigned int length = sg_dma_len(&data->sg[i]);
485 
486                         u64 mem_addr = sg_dma_address(&data->sg[i]);
487 
488                         for ( ; length ; desc++) {
489                                 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
490                                            length : DW_MCI_DESC_DATA_LENGTH;
491 
492                                 length -= desc_len;
493 
494                                 /*
495                                  * Set the OWN bit and disable interrupts
496                                  * for this descriptor
497                                  */
498                                 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
499                                                         IDMAC_DES0_CH;
500 
501                                 /* Buffer length */
502                                 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
503 
504                                 /* Physical address to DMA to/from */
505                                 desc->des4 = mem_addr & 0xffffffff;
506                                 desc->des5 = mem_addr >> 32;
507 
508                                 /* Update physical address for the next desc */
509                                 mem_addr += desc_len;
510 
511                                 /* Save pointer to the last descriptor */
512                                 desc_last = desc;
513                         }
514                 }
515 
516                 /* Set first descriptor */
517                 desc_first->des0 |= IDMAC_DES0_FD;
518 
519                 /* Set last descriptor */
520                 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
521                 desc_last->des0 |= IDMAC_DES0_LD;
522 
523         } else {
524                 struct idmac_desc *desc_first, *desc_last, *desc;
525 
526                 desc_first = desc_last = desc = host->sg_cpu;
527 
528                 for (i = 0; i < sg_len; i++) {
529                         unsigned int length = sg_dma_len(&data->sg[i]);
530 
531                         u32 mem_addr = sg_dma_address(&data->sg[i]);
532 
533                         for ( ; length ; desc++) {
534                                 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
535                                            length : DW_MCI_DESC_DATA_LENGTH;
536 
537                                 length -= desc_len;
538 
539                                 /*
540                                  * Set the OWN bit and disable interrupts
541                                  * for this descriptor
542                                  */
543                                 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
544                                                          IDMAC_DES0_DIC |
545                                                          IDMAC_DES0_CH);
546 
547                                 /* Buffer length */
548                                 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
549 
550                                 /* Physical address to DMA to/from */
551                                 desc->des2 = cpu_to_le32(mem_addr);
552 
553                                 /* Update physical address for the next desc */
554                                 mem_addr += desc_len;
555 
556                                 /* Save pointer to the last descriptor */
557                                 desc_last = desc;
558                         }
559                 }
560 
561                 /* Set first descriptor */
562                 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
563 
564                 /* Set last descriptor */
565                 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
566                                                IDMAC_DES0_DIC));
567                 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
568         }
569 
570         wmb(); /* drain writebuffer */
571 }
572 
573 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
574 {
575         u32 temp;
576 
577         dw_mci_translate_sglist(host, host->data, sg_len);
578 
579         /* Make sure to reset DMA in case we did PIO before this */
580         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
581         dw_mci_idmac_reset(host);
582 
583         /* Select IDMAC interface */
584         temp = mci_readl(host, CTRL);
585         temp |= SDMMC_CTRL_USE_IDMAC;
586         mci_writel(host, CTRL, temp);
587 
588         /* drain writebuffer */
589         wmb();
590 
591         /* Enable the IDMAC */
592         temp = mci_readl(host, BMOD);
593         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
594         mci_writel(host, BMOD, temp);
595 
596         /* Start it running */
597         mci_writel(host, PLDMND, 1);
598 
599         return 0;
600 }
601 
602 static int dw_mci_idmac_init(struct dw_mci *host)
603 {
604         int i;
605 
606         if (host->dma_64bit_address == 1) {
607                 struct idmac_desc_64addr *p;
608                 /* Number of descriptors in the ring buffer */
609                 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr);
610 
611                 /* Forward link the descriptor list */
612                 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
613                                                                 i++, p++) {
614                         p->des6 = (host->sg_dma +
615                                         (sizeof(struct idmac_desc_64addr) *
616                                                         (i + 1))) & 0xffffffff;
617 
618                         p->des7 = (u64)(host->sg_dma +
619                                         (sizeof(struct idmac_desc_64addr) *
620                                                         (i + 1))) >> 32;
621                         /* Initialize reserved and buffer size fields to "" */
622                         p->des1 = 0;
623                         p->des2 = 0;
624                         p->des3 = 0;
625                 }
626 
627                 /* Set the last descriptor as the end-of-ring descriptor */
628                 p->des6 = host->sg_dma & 0xffffffff;
629                 p->des7 = (u64)host->sg_dma >> 32;
630                 p->des0 = IDMAC_DES0_ER;
631 
632         } else {
633                 struct idmac_desc *p;
634                 /* Number of descriptors in the ring buffer */
635                 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
636 
637                 /* Forward link the descriptor list */
638                 for (i = 0, p = host->sg_cpu;
639                      i < host->ring_size - 1;
640                      i++, p++) {
641                         p->des3 = cpu_to_le32(host->sg_dma +
642                                         (sizeof(struct idmac_desc) * (i + 1)));
643                         p->des1 = 0;
644                 }
645 
646                 /* Set the last descriptor as the end-of-ring descriptor */
647                 p->des3 = cpu_to_le32(host->sg_dma);
648                 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
649         }
650 
651         dw_mci_idmac_reset(host);
652 
653         if (host->dma_64bit_address == 1) {
654                 /* Mask out interrupts - get Tx & Rx complete only */
655                 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
656                 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
657                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
658 
659                 /* Set the descriptor base address */
660                 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
661                 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
662 
663         } else {
664                 /* Mask out interrupts - get Tx & Rx complete only */
665                 mci_writel(host, IDSTS, IDMAC_INT_CLR);
666                 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
667                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
668 
669                 /* Set the descriptor base address */
670                 mci_writel(host, DBADDR, host->sg_dma);
671         }
672 
673         return 0;
674 }
675 
676 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
677         .init = dw_mci_idmac_init,
678         .start = dw_mci_idmac_start_dma,
679         .stop = dw_mci_idmac_stop_dma,
680         .complete = dw_mci_dmac_complete_dma,
681         .cleanup = dw_mci_dma_cleanup,
682 };
683 
684 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
685 {
686         dmaengine_terminate_all(host->dms->ch);
687 }
688 
689 static int dw_mci_edmac_start_dma(struct dw_mci *host,
690                                             unsigned int sg_len)
691 {
692         struct dma_slave_config cfg;
693         struct dma_async_tx_descriptor *desc = NULL;
694         struct scatterlist *sgl = host->data->sg;
695         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
696         u32 sg_elems = host->data->sg_len;
697         u32 fifoth_val;
698         u32 fifo_offset = host->fifo_reg - host->regs;
699         int ret = 0;
700 
701         /* Set external dma config: burst size, burst width */
702         cfg.dst_addr = (dma_addr_t)(host->phy_regs + fifo_offset);
703         cfg.src_addr = cfg.dst_addr;
704         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
705         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
706 
707         /* Match burst msize with external dma config */
708         fifoth_val = mci_readl(host, FIFOTH);
709         cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
710         cfg.src_maxburst = cfg.dst_maxburst;
711 
712         if (host->data->flags & MMC_DATA_WRITE)
713                 cfg.direction = DMA_MEM_TO_DEV;
714         else
715                 cfg.direction = DMA_DEV_TO_MEM;
716 
717         ret = dmaengine_slave_config(host->dms->ch, &cfg);
718         if (ret) {
719                 dev_err(host->dev, "Failed to config edmac.\n");
720                 return -EBUSY;
721         }
722 
723         desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
724                                        sg_len, cfg.direction,
725                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
726         if (!desc) {
727                 dev_err(host->dev, "Can't prepare slave sg.\n");
728                 return -EBUSY;
729         }
730 
731         /* Set dw_mci_dmac_complete_dma as callback */
732         desc->callback = dw_mci_dmac_complete_dma;
733         desc->callback_param = (void *)host;
734         dmaengine_submit(desc);
735 
736         /* Flush cache before write */
737         if (host->data->flags & MMC_DATA_WRITE)
738                 dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl,
739                                        sg_elems, DMA_TO_DEVICE);
740 
741         dma_async_issue_pending(host->dms->ch);
742 
743         return 0;
744 }
745 
746 static int dw_mci_edmac_init(struct dw_mci *host)
747 {
748         /* Request external dma channel */
749         host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
750         if (!host->dms)
751                 return -ENOMEM;
752 
753         host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
754         if (!host->dms->ch) {
755                 dev_err(host->dev, "Failed to get external DMA channel.\n");
756                 kfree(host->dms);
757                 host->dms = NULL;
758                 return -ENXIO;
759         }
760 
761         return 0;
762 }
763 
764 static void dw_mci_edmac_exit(struct dw_mci *host)
765 {
766         if (host->dms) {
767                 if (host->dms->ch) {
768                         dma_release_channel(host->dms->ch);
769                         host->dms->ch = NULL;
770                 }
771                 kfree(host->dms);
772                 host->dms = NULL;
773         }
774 }
775 
776 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
777         .init = dw_mci_edmac_init,
778         .exit = dw_mci_edmac_exit,
779         .start = dw_mci_edmac_start_dma,
780         .stop = dw_mci_edmac_stop_dma,
781         .complete = dw_mci_dmac_complete_dma,
782         .cleanup = dw_mci_dma_cleanup,
783 };
784 
785 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
786                                    struct mmc_data *data,
787                                    bool next)
788 {
789         struct scatterlist *sg;
790         unsigned int i, sg_len;
791 
792         if (!next && data->host_cookie)
793                 return data->host_cookie;
794 
795         /*
796          * We don't do DMA on "complex" transfers, i.e. with
797          * non-word-aligned buffers or lengths. Also, we don't bother
798          * with all the DMA setup overhead for short transfers.
799          */
800         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
801                 return -EINVAL;
802 
803         if (data->blksz & 3)
804                 return -EINVAL;
805 
806         for_each_sg(data->sg, sg, data->sg_len, i) {
807                 if (sg->offset & 3 || sg->length & 3)
808                         return -EINVAL;
809         }
810 
811         sg_len = dma_map_sg(host->dev,
812                             data->sg,
813                             data->sg_len,
814                             dw_mci_get_dma_dir(data));
815         if (sg_len == 0)
816                 return -EINVAL;
817 
818         if (next)
819                 data->host_cookie = sg_len;
820 
821         return sg_len;
822 }
823 
824 static void dw_mci_pre_req(struct mmc_host *mmc,
825                            struct mmc_request *mrq,
826                            bool is_first_req)
827 {
828         struct dw_mci_slot *slot = mmc_priv(mmc);
829         struct mmc_data *data = mrq->data;
830 
831         if (!slot->host->use_dma || !data)
832                 return;
833 
834         if (data->host_cookie) {
835                 data->host_cookie = 0;
836                 return;
837         }
838 
839         if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
840                 data->host_cookie = 0;
841 }
842 
843 static void dw_mci_post_req(struct mmc_host *mmc,
844                             struct mmc_request *mrq,
845                             int err)
846 {
847         struct dw_mci_slot *slot = mmc_priv(mmc);
848         struct mmc_data *data = mrq->data;
849 
850         if (!slot->host->use_dma || !data)
851                 return;
852 
853         if (data->host_cookie)
854                 dma_unmap_sg(slot->host->dev,
855                              data->sg,
856                              data->sg_len,
857                              dw_mci_get_dma_dir(data));
858         data->host_cookie = 0;
859 }
860 
861 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
862 {
863         unsigned int blksz = data->blksz;
864         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
865         u32 fifo_width = 1 << host->data_shift;
866         u32 blksz_depth = blksz / fifo_width, fifoth_val;
867         u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
868         int idx = ARRAY_SIZE(mszs) - 1;
869 
870         /* pio should ship this scenario */
871         if (!host->use_dma)
872                 return;
873 
874         tx_wmark = (host->fifo_depth) / 2;
875         tx_wmark_invers = host->fifo_depth - tx_wmark;
876 
877         /*
878          * MSIZE is '1',
879          * if blksz is not a multiple of the FIFO width
880          */
881         if (blksz % fifo_width) {
882                 msize = 0;
883                 rx_wmark = 1;
884                 goto done;
885         }
886 
887         do {
888                 if (!((blksz_depth % mszs[idx]) ||
889                      (tx_wmark_invers % mszs[idx]))) {
890                         msize = idx;
891                         rx_wmark = mszs[idx] - 1;
892                         break;
893                 }
894         } while (--idx > 0);
895         /*
896          * If idx is '', it won't be tried
897          * Thus, initial values are uesed
898          */
899 done:
900         fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
901         mci_writel(host, FIFOTH, fifoth_val);
902 }
903 
904 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
905 {
906         unsigned int blksz = data->blksz;
907         u32 blksz_depth, fifo_depth;
908         u16 thld_size;
909 
910         WARN_ON(!(data->flags & MMC_DATA_READ));
911 
912         /*
913          * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
914          * in the FIFO region, so we really shouldn't access it).
915          */
916         if (host->verid < DW_MMC_240A)
917                 return;
918 
919         if (host->timing != MMC_TIMING_MMC_HS200 &&
920             host->timing != MMC_TIMING_MMC_HS400 &&
921             host->timing != MMC_TIMING_UHS_SDR104)
922                 goto disable;
923 
924         blksz_depth = blksz / (1 << host->data_shift);
925         fifo_depth = host->fifo_depth;
926 
927         if (blksz_depth > fifo_depth)
928                 goto disable;
929 
930         /*
931          * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
932          * If (blksz_depth) <  (fifo_depth >> 1), should be thld_size = blksz
933          * Currently just choose blksz.
934          */
935         thld_size = blksz;
936         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
937         return;
938 
939 disable:
940         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
941 }
942 
943 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
944 {
945         unsigned long irqflags;
946         int sg_len;
947         u32 temp;
948 
949         host->using_dma = 0;
950 
951         /* If we don't have a channel, we can't do DMA */
952         if (!host->use_dma)
953                 return -ENODEV;
954 
955         sg_len = dw_mci_pre_dma_transfer(host, data, 0);
956         if (sg_len < 0) {
957                 host->dma_ops->stop(host);
958                 return sg_len;
959         }
960 
961         host->using_dma = 1;
962 
963         if (host->use_dma == TRANS_MODE_IDMAC)
964                 dev_vdbg(host->dev,
965                          "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
966                          (unsigned long)host->sg_cpu,
967                          (unsigned long)host->sg_dma,
968                          sg_len);
969 
970         /*
971          * Decide the MSIZE and RX/TX Watermark.
972          * If current block size is same with previous size,
973          * no need to update fifoth.
974          */
975         if (host->prev_blksz != data->blksz)
976                 dw_mci_adjust_fifoth(host, data);
977 
978         /* Enable the DMA interface */
979         temp = mci_readl(host, CTRL);
980         temp |= SDMMC_CTRL_DMA_ENABLE;
981         mci_writel(host, CTRL, temp);
982 
983         /* Disable RX/TX IRQs, let DMA handle it */
984         spin_lock_irqsave(&host->irq_lock, irqflags);
985         temp = mci_readl(host, INTMASK);
986         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
987         mci_writel(host, INTMASK, temp);
988         spin_unlock_irqrestore(&host->irq_lock, irqflags);
989 
990         if (host->dma_ops->start(host, sg_len)) {
991                 /* We can't do DMA */
992                 dev_err(host->dev, "%s: failed to start DMA.\n", __func__);
993                 return -ENODEV;
994         }
995 
996         return 0;
997 }
998 
999 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1000 {
1001         unsigned long irqflags;
1002         int flags = SG_MITER_ATOMIC;
1003         u32 temp;
1004 
1005         data->error = -EINPROGRESS;
1006 
1007         WARN_ON(host->data);
1008         host->sg = NULL;
1009         host->data = data;
1010 
1011         if (data->flags & MMC_DATA_READ) {
1012                 host->dir_status = DW_MCI_RECV_STATUS;
1013                 dw_mci_ctrl_rd_thld(host, data);
1014         } else {
1015                 host->dir_status = DW_MCI_SEND_STATUS;
1016         }
1017 
1018         if (dw_mci_submit_data_dma(host, data)) {
1019                 if (host->data->flags & MMC_DATA_READ)
1020                         flags |= SG_MITER_TO_SG;
1021                 else
1022                         flags |= SG_MITER_FROM_SG;
1023 
1024                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1025                 host->sg = data->sg;
1026                 host->part_buf_start = 0;
1027                 host->part_buf_count = 0;
1028 
1029                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1030 
1031                 spin_lock_irqsave(&host->irq_lock, irqflags);
1032                 temp = mci_readl(host, INTMASK);
1033                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1034                 mci_writel(host, INTMASK, temp);
1035                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1036 
1037                 temp = mci_readl(host, CTRL);
1038                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1039                 mci_writel(host, CTRL, temp);
1040 
1041                 /*
1042                  * Use the initial fifoth_val for PIO mode.
1043                  * If next issued data may be transfered by DMA mode,
1044                  * prev_blksz should be invalidated.
1045                  */
1046                 mci_writel(host, FIFOTH, host->fifoth_val);
1047                 host->prev_blksz = 0;
1048         } else {
1049                 /*
1050                  * Keep the current block size.
1051                  * It will be used to decide whether to update
1052                  * fifoth register next time.
1053                  */
1054                 host->prev_blksz = data->blksz;
1055         }
1056 }
1057 
1058 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
1059 {
1060         struct dw_mci *host = slot->host;
1061         unsigned long timeout = jiffies + msecs_to_jiffies(500);
1062         unsigned int cmd_status = 0;
1063 
1064         mci_writel(host, CMDARG, arg);
1065         wmb(); /* drain writebuffer */
1066         dw_mci_wait_while_busy(host, cmd);
1067         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
1068 
1069         while (time_before(jiffies, timeout)) {
1070                 cmd_status = mci_readl(host, CMD);
1071                 if (!(cmd_status & SDMMC_CMD_START))
1072                         return;
1073         }
1074         dev_err(&slot->mmc->class_dev,
1075                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1076                 cmd, arg, cmd_status);
1077 }
1078 
1079 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1080 {
1081         struct dw_mci *host = slot->host;
1082         unsigned int clock = slot->clock;
1083         u32 div;
1084         u32 clk_en_a;
1085         u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1086 
1087         /* We must continue to set bit 28 in CMD until the change is complete */
1088         if (host->state == STATE_WAITING_CMD11_DONE)
1089                 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1090 
1091         if (!clock) {
1092                 mci_writel(host, CLKENA, 0);
1093                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1094         } else if (clock != host->current_speed || force_clkinit) {
1095                 div = host->bus_hz / clock;
1096                 if (host->bus_hz % clock && host->bus_hz > clock)
1097                         /*
1098                          * move the + 1 after the divide to prevent
1099                          * over-clocking the card.
1100                          */
1101                         div += 1;
1102 
1103                 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1104 
1105                 if ((clock << div) != slot->__clk_old || force_clkinit)
1106                         dev_info(&slot->mmc->class_dev,
1107                                  "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1108                                  slot->id, host->bus_hz, clock,
1109                                  div ? ((host->bus_hz / div) >> 1) :
1110                                  host->bus_hz, div);
1111 
1112                 /* disable clock */
1113                 mci_writel(host, CLKENA, 0);
1114                 mci_writel(host, CLKSRC, 0);
1115 
1116                 /* inform CIU */
1117                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1118 
1119                 /* set clock to desired speed */
1120                 mci_writel(host, CLKDIV, div);
1121 
1122                 /* inform CIU */
1123                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1124 
1125                 /* enable clock; only low power if no SDIO */
1126                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1127                 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1128                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1129                 mci_writel(host, CLKENA, clk_en_a);
1130 
1131                 /* inform CIU */
1132                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1133 
1134                 /* keep the clock with reflecting clock dividor */
1135                 slot->__clk_old = clock << div;
1136         }
1137 
1138         host->current_speed = clock;
1139 
1140         /* Set the current slot bus width */
1141         mci_writel(host, CTYPE, (slot->ctype << slot->id));
1142 }
1143 
1144 static void __dw_mci_start_request(struct dw_mci *host,
1145                                    struct dw_mci_slot *slot,
1146                                    struct mmc_command *cmd)
1147 {
1148         struct mmc_request *mrq;
1149         struct mmc_data *data;
1150         u32 cmdflags;
1151 
1152         mrq = slot->mrq;
1153 
1154         host->cur_slot = slot;
1155         host->mrq = mrq;
1156 
1157         host->pending_events = 0;
1158         host->completed_events = 0;
1159         host->cmd_status = 0;
1160         host->data_status = 0;
1161         host->dir_status = 0;
1162 
1163         data = cmd->data;
1164         if (data) {
1165                 mci_writel(host, TMOUT, 0xFFFFFFFF);
1166                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1167                 mci_writel(host, BLKSIZ, data->blksz);
1168         }
1169 
1170         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1171 
1172         /* this is the first command, send the initialization clock */
1173         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1174                 cmdflags |= SDMMC_CMD_INIT;
1175 
1176         if (data) {
1177                 dw_mci_submit_data(host, data);
1178                 wmb(); /* drain writebuffer */
1179         }
1180 
1181         dw_mci_start_command(host, cmd, cmdflags);
1182 
1183         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1184                 unsigned long irqflags;
1185 
1186                 /*
1187                  * Databook says to fail after 2ms w/ no response, but evidence
1188                  * shows that sometimes the cmd11 interrupt takes over 130ms.
1189                  * We'll set to 500ms, plus an extra jiffy just in case jiffies
1190                  * is just about to roll over.
1191                  *
1192                  * We do this whole thing under spinlock and only if the
1193                  * command hasn't already completed (indicating the the irq
1194                  * already ran so we don't want the timeout).
1195                  */
1196                 spin_lock_irqsave(&host->irq_lock, irqflags);
1197                 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1198                         mod_timer(&host->cmd11_timer,
1199                                 jiffies + msecs_to_jiffies(500) + 1);
1200                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1201         }
1202 
1203         if (mrq->stop)
1204                 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
1205         else
1206                 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1207 }
1208 
1209 static void dw_mci_start_request(struct dw_mci *host,
1210                                  struct dw_mci_slot *slot)
1211 {
1212         struct mmc_request *mrq = slot->mrq;
1213         struct mmc_command *cmd;
1214 
1215         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1216         __dw_mci_start_request(host, slot, cmd);
1217 }
1218 
1219 /* must be called with host->lock held */
1220 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1221                                  struct mmc_request *mrq)
1222 {
1223         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1224                  host->state);
1225 
1226         slot->mrq = mrq;
1227 
1228         if (host->state == STATE_WAITING_CMD11_DONE) {
1229                 dev_warn(&slot->mmc->class_dev,
1230                          "Voltage change didn't complete\n");
1231                 /*
1232                  * this case isn't expected to happen, so we can
1233                  * either crash here or just try to continue on
1234                  * in the closest possible state
1235                  */
1236                 host->state = STATE_IDLE;
1237         }
1238 
1239         if (host->state == STATE_IDLE) {
1240                 host->state = STATE_SENDING_CMD;
1241                 dw_mci_start_request(host, slot);
1242         } else {
1243                 list_add_tail(&slot->queue_node, &host->queue);
1244         }
1245 }
1246 
1247 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1248 {
1249         struct dw_mci_slot *slot = mmc_priv(mmc);
1250         struct dw_mci *host = slot->host;
1251 
1252         WARN_ON(slot->mrq);
1253 
1254         /*
1255          * The check for card presence and queueing of the request must be
1256          * atomic, otherwise the card could be removed in between and the
1257          * request wouldn't fail until another card was inserted.
1258          */
1259         spin_lock_bh(&host->lock);
1260 
1261         if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1262                 spin_unlock_bh(&host->lock);
1263                 mrq->cmd->error = -ENOMEDIUM;
1264                 mmc_request_done(mmc, mrq);
1265                 return;
1266         }
1267 
1268         dw_mci_queue_request(host, slot, mrq);
1269 
1270         spin_unlock_bh(&host->lock);
1271 }
1272 
1273 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1274 {
1275         struct dw_mci_slot *slot = mmc_priv(mmc);
1276         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1277         u32 regs;
1278         int ret;
1279 
1280         switch (ios->bus_width) {
1281         case MMC_BUS_WIDTH_4:
1282                 slot->ctype = SDMMC_CTYPE_4BIT;
1283                 break;
1284         case MMC_BUS_WIDTH_8:
1285                 slot->ctype = SDMMC_CTYPE_8BIT;
1286                 break;
1287         default:
1288                 /* set default 1 bit mode */
1289                 slot->ctype = SDMMC_CTYPE_1BIT;
1290         }
1291 
1292         regs = mci_readl(slot->host, UHS_REG);
1293 
1294         /* DDR mode set */
1295         if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1296             ios->timing == MMC_TIMING_UHS_DDR50 ||
1297             ios->timing == MMC_TIMING_MMC_HS400)
1298                 regs |= ((0x1 << slot->id) << 16);
1299         else
1300                 regs &= ~((0x1 << slot->id) << 16);
1301 
1302         mci_writel(slot->host, UHS_REG, regs);
1303         slot->host->timing = ios->timing;
1304 
1305         /*
1306          * Use mirror of ios->clock to prevent race with mmc
1307          * core ios update when finding the minimum.
1308          */
1309         slot->clock = ios->clock;
1310 
1311         if (drv_data && drv_data->set_ios)
1312                 drv_data->set_ios(slot->host, ios);
1313 
1314         switch (ios->power_mode) {
1315         case MMC_POWER_UP:
1316                 if (!IS_ERR(mmc->supply.vmmc)) {
1317                         ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1318                                         ios->vdd);
1319                         if (ret) {
1320                                 dev_err(slot->host->dev,
1321                                         "failed to enable vmmc regulator\n");
1322                                 /*return, if failed turn on vmmc*/
1323                                 return;
1324                         }
1325                 }
1326                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1327                 regs = mci_readl(slot->host, PWREN);
1328                 regs |= (1 << slot->id);
1329                 mci_writel(slot->host, PWREN, regs);
1330                 break;
1331         case MMC_POWER_ON:
1332                 if (!slot->host->vqmmc_enabled) {
1333                         if (!IS_ERR(mmc->supply.vqmmc)) {
1334                                 ret = regulator_enable(mmc->supply.vqmmc);
1335                                 if (ret < 0)
1336                                         dev_err(slot->host->dev,
1337                                                 "failed to enable vqmmc\n");
1338                                 else
1339                                         slot->host->vqmmc_enabled = true;
1340 
1341                         } else {
1342                                 /* Keep track so we don't reset again */
1343                                 slot->host->vqmmc_enabled = true;
1344                         }
1345 
1346                         /* Reset our state machine after powering on */
1347                         dw_mci_ctrl_reset(slot->host,
1348                                           SDMMC_CTRL_ALL_RESET_FLAGS);
1349                 }
1350 
1351                 /* Adjust clock / bus width after power is up */
1352                 dw_mci_setup_bus(slot, false);
1353 
1354                 break;
1355         case MMC_POWER_OFF:
1356                 /* Turn clock off before power goes down */
1357                 dw_mci_setup_bus(slot, false);
1358 
1359                 if (!IS_ERR(mmc->supply.vmmc))
1360                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1361 
1362                 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1363                         regulator_disable(mmc->supply.vqmmc);
1364                 slot->host->vqmmc_enabled = false;
1365 
1366                 regs = mci_readl(slot->host, PWREN);
1367                 regs &= ~(1 << slot->id);
1368                 mci_writel(slot->host, PWREN, regs);
1369                 break;
1370         default:
1371                 break;
1372         }
1373 
1374         if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1375                 slot->host->state = STATE_IDLE;
1376 }
1377 
1378 static int dw_mci_card_busy(struct mmc_host *mmc)
1379 {
1380         struct dw_mci_slot *slot = mmc_priv(mmc);
1381         u32 status;
1382 
1383         /*
1384          * Check the busy bit which is low when DAT[3:0]
1385          * (the data lines) are 0000
1386          */
1387         status = mci_readl(slot->host, STATUS);
1388 
1389         return !!(status & SDMMC_STATUS_BUSY);
1390 }
1391 
1392 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1393 {
1394         struct dw_mci_slot *slot = mmc_priv(mmc);
1395         struct dw_mci *host = slot->host;
1396         const struct dw_mci_drv_data *drv_data = host->drv_data;
1397         u32 uhs;
1398         u32 v18 = SDMMC_UHS_18V << slot->id;
1399         int ret;
1400 
1401         if (drv_data && drv_data->switch_voltage)
1402                 return drv_data->switch_voltage(mmc, ios);
1403 
1404         /*
1405          * Program the voltage.  Note that some instances of dw_mmc may use
1406          * the UHS_REG for this.  For other instances (like exynos) the UHS_REG
1407          * does no harm but you need to set the regulator directly.  Try both.
1408          */
1409         uhs = mci_readl(host, UHS_REG);
1410         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1411                 uhs &= ~v18;
1412         else
1413                 uhs |= v18;
1414 
1415         if (!IS_ERR(mmc->supply.vqmmc)) {
1416                 ret = mmc_regulator_set_vqmmc(mmc, ios);
1417 
1418                 if (ret) {
1419                         dev_dbg(&mmc->class_dev,
1420                                          "Regulator set error %d - %s V\n",
1421                                          ret, uhs & v18 ? "1.8" : "3.3");
1422                         return ret;
1423                 }
1424         }
1425         mci_writel(host, UHS_REG, uhs);
1426 
1427         return 0;
1428 }
1429 
1430 static int dw_mci_get_ro(struct mmc_host *mmc)
1431 {
1432         int read_only;
1433         struct dw_mci_slot *slot = mmc_priv(mmc);
1434         int gpio_ro = mmc_gpio_get_ro(mmc);
1435 
1436         /* Use platform get_ro function, else try on board write protect */
1437         if (!IS_ERR_VALUE(gpio_ro))
1438                 read_only = gpio_ro;
1439         else
1440                 read_only =
1441                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1442 
1443         dev_dbg(&mmc->class_dev, "card is %s\n",
1444                 read_only ? "read-only" : "read-write");
1445 
1446         return read_only;
1447 }
1448 
1449 static int dw_mci_get_cd(struct mmc_host *mmc)
1450 {
1451         int present;
1452         struct dw_mci_slot *slot = mmc_priv(mmc);
1453         struct dw_mci_board *brd = slot->host->pdata;
1454         struct dw_mci *host = slot->host;
1455         int gpio_cd = mmc_gpio_get_cd(mmc);
1456 
1457         /* Use platform get_cd function, else try onboard card detect */
1458         if ((brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) ||
1459             (mmc->caps & MMC_CAP_NONREMOVABLE))
1460                 present = 1;
1461         else if (!IS_ERR_VALUE(gpio_cd))
1462                 present = gpio_cd;
1463         else
1464                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1465                         == 0 ? 1 : 0;
1466 
1467         spin_lock_bh(&host->lock);
1468         if (present) {
1469                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1470                 dev_dbg(&mmc->class_dev, "card is present\n");
1471         } else {
1472                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1473                 dev_dbg(&mmc->class_dev, "card is not present\n");
1474         }
1475         spin_unlock_bh(&host->lock);
1476 
1477         return present;
1478 }
1479 
1480 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1481 {
1482         struct dw_mci_slot *slot = mmc_priv(mmc);
1483         struct dw_mci *host = slot->host;
1484 
1485         /*
1486          * Low power mode will stop the card clock when idle.  According to the
1487          * description of the CLKENA register we should disable low power mode
1488          * for SDIO cards if we need SDIO interrupts to work.
1489          */
1490         if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1491                 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1492                 u32 clk_en_a_old;
1493                 u32 clk_en_a;
1494 
1495                 clk_en_a_old = mci_readl(host, CLKENA);
1496 
1497                 if (card->type == MMC_TYPE_SDIO ||
1498                     card->type == MMC_TYPE_SD_COMBO) {
1499                         set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1500                         clk_en_a = clk_en_a_old & ~clken_low_pwr;
1501                 } else {
1502                         clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1503                         clk_en_a = clk_en_a_old | clken_low_pwr;
1504                 }
1505 
1506                 if (clk_en_a != clk_en_a_old) {
1507                         mci_writel(host, CLKENA, clk_en_a);
1508                         mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1509                                      SDMMC_CMD_PRV_DAT_WAIT, 0);
1510                 }
1511         }
1512 }
1513 
1514 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1515 {
1516         struct dw_mci_slot *slot = mmc_priv(mmc);
1517         struct dw_mci *host = slot->host;
1518         unsigned long irqflags;
1519         u32 int_mask;
1520 
1521         spin_lock_irqsave(&host->irq_lock, irqflags);
1522 
1523         /* Enable/disable Slot Specific SDIO interrupt */
1524         int_mask = mci_readl(host, INTMASK);
1525         if (enb)
1526                 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1527         else
1528                 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1529         mci_writel(host, INTMASK, int_mask);
1530 
1531         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1532 }
1533 
1534 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1535 {
1536         struct dw_mci_slot *slot = mmc_priv(mmc);
1537         struct dw_mci *host = slot->host;
1538         const struct dw_mci_drv_data *drv_data = host->drv_data;
1539         int err = -EINVAL;
1540 
1541         if (drv_data && drv_data->execute_tuning)
1542                 err = drv_data->execute_tuning(slot, opcode);
1543         return err;
1544 }
1545 
1546 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1547                                        struct mmc_ios *ios)
1548 {
1549         struct dw_mci_slot *slot = mmc_priv(mmc);
1550         struct dw_mci *host = slot->host;
1551         const struct dw_mci_drv_data *drv_data = host->drv_data;
1552 
1553         if (drv_data && drv_data->prepare_hs400_tuning)
1554                 return drv_data->prepare_hs400_tuning(host, ios);
1555 
1556         return 0;
1557 }
1558 
1559 static const struct mmc_host_ops dw_mci_ops = {
1560         .request                = dw_mci_request,
1561         .pre_req                = dw_mci_pre_req,
1562         .post_req               = dw_mci_post_req,
1563         .set_ios                = dw_mci_set_ios,
1564         .get_ro                 = dw_mci_get_ro,
1565         .get_cd                 = dw_mci_get_cd,
1566         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
1567         .execute_tuning         = dw_mci_execute_tuning,
1568         .card_busy              = dw_mci_card_busy,
1569         .start_signal_voltage_switch = dw_mci_switch_voltage,
1570         .init_card              = dw_mci_init_card,
1571         .prepare_hs400_tuning   = dw_mci_prepare_hs400_tuning,
1572 };
1573 
1574 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1575         __releases(&host->lock)
1576         __acquires(&host->lock)
1577 {
1578         struct dw_mci_slot *slot;
1579         struct mmc_host *prev_mmc = host->cur_slot->mmc;
1580 
1581         WARN_ON(host->cmd || host->data);
1582 
1583         host->cur_slot->mrq = NULL;
1584         host->mrq = NULL;
1585         if (!list_empty(&host->queue)) {
1586                 slot = list_entry(host->queue.next,
1587                                   struct dw_mci_slot, queue_node);
1588                 list_del(&slot->queue_node);
1589                 dev_vdbg(host->dev, "list not empty: %s is next\n",
1590                          mmc_hostname(slot->mmc));
1591                 host->state = STATE_SENDING_CMD;
1592                 dw_mci_start_request(host, slot);
1593         } else {
1594                 dev_vdbg(host->dev, "list empty\n");
1595 
1596                 if (host->state == STATE_SENDING_CMD11)
1597                         host->state = STATE_WAITING_CMD11_DONE;
1598                 else
1599                         host->state = STATE_IDLE;
1600         }
1601 
1602         spin_unlock(&host->lock);
1603         mmc_request_done(prev_mmc, mrq);
1604         spin_lock(&host->lock);
1605 }
1606 
1607 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1608 {
1609         u32 status = host->cmd_status;
1610 
1611         host->cmd_status = 0;
1612 
1613         /* Read the response from the card (up to 16 bytes) */
1614         if (cmd->flags & MMC_RSP_PRESENT) {
1615                 if (cmd->flags & MMC_RSP_136) {
1616                         cmd->resp[3] = mci_readl(host, RESP0);
1617                         cmd->resp[2] = mci_readl(host, RESP1);
1618                         cmd->resp[1] = mci_readl(host, RESP2);
1619                         cmd->resp[0] = mci_readl(host, RESP3);
1620                 } else {
1621                         cmd->resp[0] = mci_readl(host, RESP0);
1622                         cmd->resp[1] = 0;
1623                         cmd->resp[2] = 0;
1624                         cmd->resp[3] = 0;
1625                 }
1626         }
1627 
1628         if (status & SDMMC_INT_RTO)
1629                 cmd->error = -ETIMEDOUT;
1630         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1631                 cmd->error = -EILSEQ;
1632         else if (status & SDMMC_INT_RESP_ERR)
1633                 cmd->error = -EIO;
1634         else
1635                 cmd->error = 0;
1636 
1637         if (cmd->error) {
1638                 /* newer ip versions need a delay between retries */
1639                 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
1640                         mdelay(20);
1641         }
1642 
1643         return cmd->error;
1644 }
1645 
1646 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1647 {
1648         u32 status = host->data_status;
1649 
1650         if (status & DW_MCI_DATA_ERROR_FLAGS) {
1651                 if (status & SDMMC_INT_DRTO) {
1652                         data->error = -ETIMEDOUT;
1653                 } else if (status & SDMMC_INT_DCRC) {
1654                         data->error = -EILSEQ;
1655                 } else if (status & SDMMC_INT_EBE) {
1656                         if (host->dir_status ==
1657                                 DW_MCI_SEND_STATUS) {
1658                                 /*
1659                                  * No data CRC status was returned.
1660                                  * The number of bytes transferred
1661                                  * will be exaggerated in PIO mode.
1662                                  */
1663                                 data->bytes_xfered = 0;
1664                                 data->error = -ETIMEDOUT;
1665                         } else if (host->dir_status ==
1666                                         DW_MCI_RECV_STATUS) {
1667                                 data->error = -EIO;
1668                         }
1669                 } else {
1670                         /* SDMMC_INT_SBE is included */
1671                         data->error = -EIO;
1672                 }
1673 
1674                 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1675 
1676                 /*
1677                  * After an error, there may be data lingering
1678                  * in the FIFO
1679                  */
1680                 dw_mci_reset(host);
1681         } else {
1682                 data->bytes_xfered = data->blocks * data->blksz;
1683                 data->error = 0;
1684         }
1685 
1686         return data->error;
1687 }
1688 
1689 static void dw_mci_set_drto(struct dw_mci *host)
1690 {
1691         unsigned int drto_clks;
1692         unsigned int drto_ms;
1693 
1694         drto_clks = mci_readl(host, TMOUT) >> 8;
1695         drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000);
1696 
1697         /* add a bit spare time */
1698         drto_ms += 10;
1699 
1700         mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1701 }
1702 
1703 static void dw_mci_tasklet_func(unsigned long priv)
1704 {
1705         struct dw_mci *host = (struct dw_mci *)priv;
1706         struct mmc_data *data;
1707         struct mmc_command *cmd;
1708         struct mmc_request *mrq;
1709         enum dw_mci_state state;
1710         enum dw_mci_state prev_state;
1711         unsigned int err;
1712 
1713         spin_lock(&host->lock);
1714 
1715         state = host->state;
1716         data = host->data;
1717         mrq = host->mrq;
1718 
1719         do {
1720                 prev_state = state;
1721 
1722                 switch (state) {
1723                 case STATE_IDLE:
1724                 case STATE_WAITING_CMD11_DONE:
1725                         break;
1726 
1727                 case STATE_SENDING_CMD11:
1728                 case STATE_SENDING_CMD:
1729                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1730                                                 &host->pending_events))
1731                                 break;
1732 
1733                         cmd = host->cmd;
1734                         host->cmd = NULL;
1735                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1736                         err = dw_mci_command_complete(host, cmd);
1737                         if (cmd == mrq->sbc && !err) {
1738                                 prev_state = state = STATE_SENDING_CMD;
1739                                 __dw_mci_start_request(host, host->cur_slot,
1740                                                        mrq->cmd);
1741                                 goto unlock;
1742                         }
1743 
1744                         if (cmd->data && err) {
1745                                 dw_mci_stop_dma(host);
1746                                 send_stop_abort(host, data);
1747                                 state = STATE_SENDING_STOP;
1748                                 break;
1749                         }
1750 
1751                         if (!cmd->data || err) {
1752                                 dw_mci_request_end(host, mrq);
1753                                 goto unlock;
1754                         }
1755 
1756                         prev_state = state = STATE_SENDING_DATA;
1757                         /* fall through */
1758 
1759                 case STATE_SENDING_DATA:
1760                         /*
1761                          * We could get a data error and never a transfer
1762                          * complete so we'd better check for it here.
1763                          *
1764                          * Note that we don't really care if we also got a
1765                          * transfer complete; stopping the DMA and sending an
1766                          * abort won't hurt.
1767                          */
1768                         if (test_and_clear_bit(EVENT_DATA_ERROR,
1769                                                &host->pending_events)) {
1770                                 dw_mci_stop_dma(host);
1771                                 if (data->stop ||
1772                                     !(host->data_status & (SDMMC_INT_DRTO |
1773                                                            SDMMC_INT_EBE)))
1774                                         send_stop_abort(host, data);
1775                                 state = STATE_DATA_ERROR;
1776                                 break;
1777                         }
1778 
1779                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1780                                                 &host->pending_events)) {
1781                                 /*
1782                                  * If all data-related interrupts don't come
1783                                  * within the given time in reading data state.
1784                                  */
1785                                 if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) &&
1786                                     (host->dir_status == DW_MCI_RECV_STATUS))
1787                                         dw_mci_set_drto(host);
1788                                 break;
1789                         }
1790 
1791                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1792 
1793                         /*
1794                          * Handle an EVENT_DATA_ERROR that might have shown up
1795                          * before the transfer completed.  This might not have
1796                          * been caught by the check above because the interrupt
1797                          * could have gone off between the previous check and
1798                          * the check for transfer complete.
1799                          *
1800                          * Technically this ought not be needed assuming we
1801                          * get a DATA_COMPLETE eventually (we'll notice the
1802                          * error and end the request), but it shouldn't hurt.
1803                          *
1804                          * This has the advantage of sending the stop command.
1805                          */
1806                         if (test_and_clear_bit(EVENT_DATA_ERROR,
1807                                                &host->pending_events)) {
1808                                 dw_mci_stop_dma(host);
1809                                 if (data->stop ||
1810                                     !(host->data_status & (SDMMC_INT_DRTO |
1811                                                            SDMMC_INT_EBE)))
1812                                         send_stop_abort(host, data);
1813                                 state = STATE_DATA_ERROR;
1814                                 break;
1815                         }
1816                         prev_state = state = STATE_DATA_BUSY;
1817 
1818                         /* fall through */
1819 
1820                 case STATE_DATA_BUSY:
1821                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1822                                                 &host->pending_events)) {
1823                                 /*
1824                                  * If data error interrupt comes but data over
1825                                  * interrupt doesn't come within the given time.
1826                                  * in reading data state.
1827                                  */
1828                                 if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) &&
1829                                     (host->dir_status == DW_MCI_RECV_STATUS))
1830                                         dw_mci_set_drto(host);
1831                                 break;
1832                         }
1833 
1834                         host->data = NULL;
1835                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1836                         err = dw_mci_data_complete(host, data);
1837 
1838                         if (!err) {
1839                                 if (!data->stop || mrq->sbc) {
1840                                         if (mrq->sbc && data->stop)
1841                                                 data->stop->error = 0;
1842                                         dw_mci_request_end(host, mrq);
1843                                         goto unlock;
1844                                 }
1845 
1846                                 /* stop command for open-ended transfer*/
1847                                 if (data->stop)
1848                                         send_stop_abort(host, data);
1849                         } else {
1850                                 /*
1851                                  * If we don't have a command complete now we'll
1852                                  * never get one since we just reset everything;
1853                                  * better end the request.
1854                                  *
1855                                  * If we do have a command complete we'll fall
1856                                  * through to the SENDING_STOP command and
1857                                  * everything will be peachy keen.
1858                                  */
1859                                 if (!test_bit(EVENT_CMD_COMPLETE,
1860                                               &host->pending_events)) {
1861                                         host->cmd = NULL;
1862                                         dw_mci_request_end(host, mrq);
1863                                         goto unlock;
1864                                 }
1865                         }
1866 
1867                         /*
1868                          * If err has non-zero,
1869                          * stop-abort command has been already issued.
1870                          */
1871                         prev_state = state = STATE_SENDING_STOP;
1872 
1873                         /* fall through */
1874 
1875                 case STATE_SENDING_STOP:
1876                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1877                                                 &host->pending_events))
1878                                 break;
1879 
1880                         /* CMD error in data command */
1881                         if (mrq->cmd->error && mrq->data)
1882                                 dw_mci_reset(host);
1883 
1884                         host->cmd = NULL;
1885                         host->data = NULL;
1886 
1887                         if (mrq->stop)
1888                                 dw_mci_command_complete(host, mrq->stop);
1889                         else
1890                                 host->cmd_status = 0;
1891 
1892                         dw_mci_request_end(host, mrq);
1893                         goto unlock;
1894 
1895                 case STATE_DATA_ERROR:
1896                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1897                                                 &host->pending_events))
1898                                 break;
1899 
1900                         state = STATE_DATA_BUSY;
1901                         break;
1902                 }
1903         } while (state != prev_state);
1904 
1905         host->state = state;
1906 unlock:
1907         spin_unlock(&host->lock);
1908 
1909 }
1910 
1911 /* push final bytes to part_buf, only use during push */
1912 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
1913 {
1914         memcpy((void *)&host->part_buf, buf, cnt);
1915         host->part_buf_count = cnt;
1916 }
1917 
1918 /* append bytes to part_buf, only use during push */
1919 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1920 {
1921         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1922         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1923         host->part_buf_count += cnt;
1924         return cnt;
1925 }
1926 
1927 /* pull first bytes from part_buf, only use during pull */
1928 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1929 {
1930         cnt = min_t(int, cnt, host->part_buf_count);
1931         if (cnt) {
1932                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1933                        cnt);
1934                 host->part_buf_count -= cnt;
1935                 host->part_buf_start += cnt;
1936         }
1937         return cnt;
1938 }
1939 
1940 /* pull final bytes from the part_buf, assuming it's just been filled */
1941 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
1942 {
1943         memcpy(buf, &host->part_buf, cnt);
1944         host->part_buf_start = cnt;
1945         host->part_buf_count = (1 << host->data_shift) - cnt;
1946 }
1947 
1948 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1949 {
1950         struct mmc_data *data = host->data;
1951         int init_cnt = cnt;
1952 
1953         /* try and push anything in the part_buf */
1954         if (unlikely(host->part_buf_count)) {
1955                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1956 
1957                 buf += len;
1958                 cnt -= len;
1959                 if (host->part_buf_count == 2) {
1960                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
1961                         host->part_buf_count = 0;
1962                 }
1963         }
1964 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1965         if (unlikely((unsigned long)buf & 0x1)) {
1966                 while (cnt >= 2) {
1967                         u16 aligned_buf[64];
1968                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
1969                         int items = len >> 1;
1970                         int i;
1971                         /* memcpy from input buffer into aligned buffer */
1972                         memcpy(aligned_buf, buf, len);
1973                         buf += len;
1974                         cnt -= len;
1975                         /* push data from aligned buffer into fifo */
1976                         for (i = 0; i < items; ++i)
1977                                 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
1978                 }
1979         } else
1980 #endif
1981         {
1982                 u16 *pdata = buf;
1983 
1984                 for (; cnt >= 2; cnt -= 2)
1985                         mci_fifo_writew(host->fifo_reg, *pdata++);
1986                 buf = pdata;
1987         }
1988         /* put anything remaining in the part_buf */
1989         if (cnt) {
1990                 dw_mci_set_part_bytes(host, buf, cnt);
1991                  /* Push data if we have reached the expected data length */
1992                 if ((data->bytes_xfered + init_cnt) ==
1993                     (data->blksz * data->blocks))
1994                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
1995         }
1996 }
1997 
1998 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1999 {
2000 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2001         if (unlikely((unsigned long)buf & 0x1)) {
2002                 while (cnt >= 2) {
2003                         /* pull data from fifo into aligned buffer */
2004                         u16 aligned_buf[64];
2005                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2006                         int items = len >> 1;
2007                         int i;
2008 
2009                         for (i = 0; i < items; ++i)
2010                                 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2011                         /* memcpy from aligned buffer into output buffer */
2012                         memcpy(buf, aligned_buf, len);
2013                         buf += len;
2014                         cnt -= len;
2015                 }
2016         } else
2017 #endif
2018         {
2019                 u16 *pdata = buf;
2020 
2021                 for (; cnt >= 2; cnt -= 2)
2022                         *pdata++ = mci_fifo_readw(host->fifo_reg);
2023                 buf = pdata;
2024         }
2025         if (cnt) {
2026                 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2027                 dw_mci_pull_final_bytes(host, buf, cnt);
2028         }
2029 }
2030 
2031 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2032 {
2033         struct mmc_data *data = host->data;
2034         int init_cnt = cnt;
2035 
2036         /* try and push anything in the part_buf */
2037         if (unlikely(host->part_buf_count)) {
2038                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2039 
2040                 buf += len;
2041                 cnt -= len;
2042                 if (host->part_buf_count == 4) {
2043                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2044                         host->part_buf_count = 0;
2045                 }
2046         }
2047 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2048         if (unlikely((unsigned long)buf & 0x3)) {
2049                 while (cnt >= 4) {
2050                         u32 aligned_buf[32];
2051                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2052                         int items = len >> 2;
2053                         int i;
2054                         /* memcpy from input buffer into aligned buffer */
2055                         memcpy(aligned_buf, buf, len);
2056                         buf += len;
2057                         cnt -= len;
2058                         /* push data from aligned buffer into fifo */
2059                         for (i = 0; i < items; ++i)
2060                                 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2061                 }
2062         } else
2063 #endif
2064         {
2065                 u32 *pdata = buf;
2066 
2067                 for (; cnt >= 4; cnt -= 4)
2068                         mci_fifo_writel(host->fifo_reg, *pdata++);
2069                 buf = pdata;
2070         }
2071         /* put anything remaining in the part_buf */
2072         if (cnt) {
2073                 dw_mci_set_part_bytes(host, buf, cnt);
2074                  /* Push data if we have reached the expected data length */
2075                 if ((data->bytes_xfered + init_cnt) ==
2076                     (data->blksz * data->blocks))
2077                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2078         }
2079 }
2080 
2081 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2082 {
2083 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2084         if (unlikely((unsigned long)buf & 0x3)) {
2085                 while (cnt >= 4) {
2086                         /* pull data from fifo into aligned buffer */
2087                         u32 aligned_buf[32];
2088                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2089                         int items = len >> 2;
2090                         int i;
2091 
2092                         for (i = 0; i < items; ++i)
2093                                 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2094                         /* memcpy from aligned buffer into output buffer */
2095                         memcpy(buf, aligned_buf, len);
2096                         buf += len;
2097                         cnt -= len;
2098                 }
2099         } else
2100 #endif
2101         {
2102                 u32 *pdata = buf;
2103 
2104                 for (; cnt >= 4; cnt -= 4)
2105                         *pdata++ = mci_fifo_readl(host->fifo_reg);
2106                 buf = pdata;
2107         }
2108         if (cnt) {
2109                 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2110                 dw_mci_pull_final_bytes(host, buf, cnt);
2111         }
2112 }
2113 
2114 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2115 {
2116         struct mmc_data *data = host->data;
2117         int init_cnt = cnt;
2118 
2119         /* try and push anything in the part_buf */
2120         if (unlikely(host->part_buf_count)) {
2121                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2122 
2123                 buf += len;
2124                 cnt -= len;
2125 
2126                 if (host->part_buf_count == 8) {
2127                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2128                         host->part_buf_count = 0;
2129                 }
2130         }
2131 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2132         if (unlikely((unsigned long)buf & 0x7)) {
2133                 while (cnt >= 8) {
2134                         u64 aligned_buf[16];
2135                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2136                         int items = len >> 3;
2137                         int i;
2138                         /* memcpy from input buffer into aligned buffer */
2139                         memcpy(aligned_buf, buf, len);
2140                         buf += len;
2141                         cnt -= len;
2142                         /* push data from aligned buffer into fifo */
2143                         for (i = 0; i < items; ++i)
2144                                 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2145                 }
2146         } else
2147 #endif
2148         {
2149                 u64 *pdata = buf;
2150 
2151                 for (; cnt >= 8; cnt -= 8)
2152                         mci_fifo_writeq(host->fifo_reg, *pdata++);
2153                 buf = pdata;
2154         }
2155         /* put anything remaining in the part_buf */
2156         if (cnt) {
2157                 dw_mci_set_part_bytes(host, buf, cnt);
2158                 /* Push data if we have reached the expected data length */
2159                 if ((data->bytes_xfered + init_cnt) ==
2160                     (data->blksz * data->blocks))
2161                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2162         }
2163 }
2164 
2165 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2166 {
2167 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2168         if (unlikely((unsigned long)buf & 0x7)) {
2169                 while (cnt >= 8) {
2170                         /* pull data from fifo into aligned buffer */
2171                         u64 aligned_buf[16];
2172                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2173                         int items = len >> 3;
2174                         int i;
2175 
2176                         for (i = 0; i < items; ++i)
2177                                 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2178 
2179                         /* memcpy from aligned buffer into output buffer */
2180                         memcpy(buf, aligned_buf, len);
2181                         buf += len;
2182                         cnt -= len;
2183                 }
2184         } else
2185 #endif
2186         {
2187                 u64 *pdata = buf;
2188 
2189                 for (; cnt >= 8; cnt -= 8)
2190                         *pdata++ = mci_fifo_readq(host->fifo_reg);
2191                 buf = pdata;
2192         }
2193         if (cnt) {
2194                 host->part_buf = mci_fifo_readq(host->fifo_reg);
2195                 dw_mci_pull_final_bytes(host, buf, cnt);
2196         }
2197 }
2198 
2199 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2200 {
2201         int len;
2202 
2203         /* get remaining partial bytes */
2204         len = dw_mci_pull_part_bytes(host, buf, cnt);
2205         if (unlikely(len == cnt))
2206                 return;
2207         buf += len;
2208         cnt -= len;
2209 
2210         /* get the rest of the data */
2211         host->pull_data(host, buf, cnt);
2212 }
2213 
2214 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2215 {
2216         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2217         void *buf;
2218         unsigned int offset;
2219         struct mmc_data *data = host->data;
2220         int shift = host->data_shift;
2221         u32 status;
2222         unsigned int len;
2223         unsigned int remain, fcnt;
2224 
2225         do {
2226                 if (!sg_miter_next(sg_miter))
2227                         goto done;
2228 
2229                 host->sg = sg_miter->piter.sg;
2230                 buf = sg_miter->addr;
2231                 remain = sg_miter->length;
2232                 offset = 0;
2233 
2234                 do {
2235                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2236                                         << shift) + host->part_buf_count;
2237                         len = min(remain, fcnt);
2238                         if (!len)
2239                                 break;
2240                         dw_mci_pull_data(host, (void *)(buf + offset), len);
2241                         data->bytes_xfered += len;
2242                         offset += len;
2243                         remain -= len;
2244                 } while (remain);
2245 
2246                 sg_miter->consumed = offset;
2247                 status = mci_readl(host, MINTSTS);
2248                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2249         /* if the RXDR is ready read again */
2250         } while ((status & SDMMC_INT_RXDR) ||
2251                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2252 
2253         if (!remain) {
2254                 if (!sg_miter_next(sg_miter))
2255                         goto done;
2256                 sg_miter->consumed = 0;
2257         }
2258         sg_miter_stop(sg_miter);
2259         return;
2260 
2261 done:
2262         sg_miter_stop(sg_miter);
2263         host->sg = NULL;
2264         smp_wmb(); /* drain writebuffer */
2265         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2266 }
2267 
2268 static void dw_mci_write_data_pio(struct dw_mci *host)
2269 {
2270         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2271         void *buf;
2272         unsigned int offset;
2273         struct mmc_data *data = host->data;
2274         int shift = host->data_shift;
2275         u32 status;
2276         unsigned int len;
2277         unsigned int fifo_depth = host->fifo_depth;
2278         unsigned int remain, fcnt;
2279 
2280         do {
2281                 if (!sg_miter_next(sg_miter))
2282                         goto done;
2283 
2284                 host->sg = sg_miter->piter.sg;
2285                 buf = sg_miter->addr;
2286                 remain = sg_miter->length;
2287                 offset = 0;
2288 
2289                 do {
2290                         fcnt = ((fifo_depth -
2291                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2292                                         << shift) - host->part_buf_count;
2293                         len = min(remain, fcnt);
2294                         if (!len)
2295                                 break;
2296                         host->push_data(host, (void *)(buf + offset), len);
2297                         data->bytes_xfered += len;
2298                         offset += len;
2299                         remain -= len;
2300                 } while (remain);
2301 
2302                 sg_miter->consumed = offset;
2303                 status = mci_readl(host, MINTSTS);
2304                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2305         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2306 
2307         if (!remain) {
2308                 if (!sg_miter_next(sg_miter))
2309                         goto done;
2310                 sg_miter->consumed = 0;
2311         }
2312         sg_miter_stop(sg_miter);
2313         return;
2314 
2315 done:
2316         sg_miter_stop(sg_miter);
2317         host->sg = NULL;
2318         smp_wmb(); /* drain writebuffer */
2319         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2320 }
2321 
2322 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2323 {
2324         if (!host->cmd_status)
2325                 host->cmd_status = status;
2326 
2327         smp_wmb(); /* drain writebuffer */
2328 
2329         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2330         tasklet_schedule(&host->tasklet);
2331 }
2332 
2333 static void dw_mci_handle_cd(struct dw_mci *host)
2334 {
2335         int i;
2336 
2337         for (i = 0; i < host->num_slots; i++) {
2338                 struct dw_mci_slot *slot = host->slot[i];
2339 
2340                 if (!slot)
2341                         continue;
2342 
2343                 if (slot->mmc->ops->card_event)
2344                         slot->mmc->ops->card_event(slot->mmc);
2345                 mmc_detect_change(slot->mmc,
2346                         msecs_to_jiffies(host->pdata->detect_delay_ms));
2347         }
2348 }
2349 
2350 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2351 {
2352         struct dw_mci *host = dev_id;
2353         u32 pending;
2354         int i;
2355 
2356         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2357 
2358         /*
2359          * DTO fix - version 2.10a and below, and only if internal DMA
2360          * is configured.
2361          */
2362         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
2363                 if (!pending &&
2364                     ((mci_readl(host, STATUS) >> 17) & 0x1fff))
2365                         pending |= SDMMC_INT_DATA_OVER;
2366         }
2367 
2368         if (pending) {
2369                 /* Check volt switch first, since it can look like an error */
2370                 if ((host->state == STATE_SENDING_CMD11) &&
2371                     (pending & SDMMC_INT_VOLT_SWITCH)) {
2372                         unsigned long irqflags;
2373 
2374                         mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2375                         pending &= ~SDMMC_INT_VOLT_SWITCH;
2376 
2377                         /*
2378                          * Hold the lock; we know cmd11_timer can't be kicked
2379                          * off after the lock is released, so safe to delete.
2380                          */
2381                         spin_lock_irqsave(&host->irq_lock, irqflags);
2382                         dw_mci_cmd_interrupt(host, pending);
2383                         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2384 
2385                         del_timer(&host->cmd11_timer);
2386                 }
2387 
2388                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2389                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2390                         host->cmd_status = pending;
2391                         smp_wmb(); /* drain writebuffer */
2392                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2393                 }
2394 
2395                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2396                         /* if there is an error report DATA_ERROR */
2397                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2398                         host->data_status = pending;
2399                         smp_wmb(); /* drain writebuffer */
2400                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
2401                         tasklet_schedule(&host->tasklet);
2402                 }
2403 
2404                 if (pending & SDMMC_INT_DATA_OVER) {
2405                         if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO)
2406                                 del_timer(&host->dto_timer);
2407 
2408                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2409                         if (!host->data_status)
2410                                 host->data_status = pending;
2411                         smp_wmb(); /* drain writebuffer */
2412                         if (host->dir_status == DW_MCI_RECV_STATUS) {
2413                                 if (host->sg != NULL)
2414                                         dw_mci_read_data_pio(host, true);
2415                         }
2416                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2417                         tasklet_schedule(&host->tasklet);
2418                 }
2419 
2420                 if (pending & SDMMC_INT_RXDR) {
2421                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2422                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2423                                 dw_mci_read_data_pio(host, false);
2424                 }
2425 
2426                 if (pending & SDMMC_INT_TXDR) {
2427                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2428                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2429                                 dw_mci_write_data_pio(host);
2430                 }
2431 
2432                 if (pending & SDMMC_INT_CMD_DONE) {
2433                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2434                         dw_mci_cmd_interrupt(host, pending);
2435                 }
2436 
2437                 if (pending & SDMMC_INT_CD) {
2438                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
2439                         dw_mci_handle_cd(host);
2440                 }
2441 
2442                 /* Handle SDIO Interrupts */
2443                 for (i = 0; i < host->num_slots; i++) {
2444                         struct dw_mci_slot *slot = host->slot[i];
2445 
2446                         if (!slot)
2447                                 continue;
2448 
2449                         if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2450                                 mci_writel(host, RINTSTS,
2451                                            SDMMC_INT_SDIO(slot->sdio_id));
2452                                 mmc_signal_sdio_irq(slot->mmc);
2453                         }
2454                 }
2455 
2456         }
2457 
2458         if (host->use_dma != TRANS_MODE_IDMAC)
2459                 return IRQ_HANDLED;
2460 
2461         /* Handle IDMA interrupts */
2462         if (host->dma_64bit_address == 1) {
2463                 pending = mci_readl(host, IDSTS64);
2464                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2465                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2466                                                         SDMMC_IDMAC_INT_RI);
2467                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2468                         host->dma_ops->complete((void *)host);
2469                 }
2470         } else {
2471                 pending = mci_readl(host, IDSTS);
2472                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2473                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2474                                                         SDMMC_IDMAC_INT_RI);
2475                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2476                         host->dma_ops->complete((void *)host);
2477                 }
2478         }
2479 
2480         return IRQ_HANDLED;
2481 }
2482 
2483 #ifdef CONFIG_OF
2484 /* given a slot, find out the device node representing that slot */
2485 static struct device_node *dw_mci_of_find_slot_node(struct dw_mci_slot *slot)
2486 {
2487         struct device *dev = slot->mmc->parent;
2488         struct device_node *np;
2489         const __be32 *addr;
2490         int len;
2491 
2492         if (!dev || !dev->of_node)
2493                 return NULL;
2494 
2495         for_each_child_of_node(dev->of_node, np) {
2496                 addr = of_get_property(np, "reg", &len);
2497                 if (!addr || (len < sizeof(int)))
2498                         continue;
2499                 if (be32_to_cpup(addr) == slot->id)
2500                         return np;
2501         }
2502         return NULL;
2503 }
2504 
2505 static void dw_mci_slot_of_parse(struct dw_mci_slot *slot)
2506 {
2507         struct device_node *np = dw_mci_of_find_slot_node(slot);
2508 
2509         if (!np)
2510                 return;
2511 
2512         if (of_property_read_bool(np, "disable-wp")) {
2513                 slot->mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
2514                 dev_warn(slot->mmc->parent,
2515                         "Slot quirk 'disable-wp' is deprecated\n");
2516         }
2517 }
2518 #else /* CONFIG_OF */
2519 static void dw_mci_slot_of_parse(struct dw_mci_slot *slot)
2520 {
2521 }
2522 #endif /* CONFIG_OF */
2523 
2524 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2525 {
2526         struct mmc_host *mmc;
2527         struct dw_mci_slot *slot;
2528         const struct dw_mci_drv_data *drv_data = host->drv_data;
2529         int ctrl_id, ret;
2530         u32 freq[2];
2531 
2532         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2533         if (!mmc)
2534                 return -ENOMEM;
2535 
2536         slot = mmc_priv(mmc);
2537         slot->id = id;
2538         slot->sdio_id = host->sdio_id0 + id;
2539         slot->mmc = mmc;
2540         slot->host = host;
2541         host->slot[id] = slot;
2542 
2543         mmc->ops = &dw_mci_ops;
2544         if (of_property_read_u32_array(host->dev->of_node,
2545                                        "clock-freq-min-max", freq, 2)) {
2546                 mmc->f_min = DW_MCI_FREQ_MIN;
2547                 mmc->f_max = DW_MCI_FREQ_MAX;
2548         } else {
2549                 mmc->f_min = freq[0];
2550                 mmc->f_max = freq[1];
2551         }
2552 
2553         /*if there are external regulators, get them*/
2554         ret = mmc_regulator_get_supply(mmc);
2555         if (ret == -EPROBE_DEFER)
2556                 goto err_host_allocated;
2557 
2558         if (!mmc->ocr_avail)
2559                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2560 
2561         if (host->pdata->caps)
2562                 mmc->caps = host->pdata->caps;
2563 
2564         if (host->pdata->pm_caps)
2565                 mmc->pm_caps = host->pdata->pm_caps;
2566 
2567         if (host->dev->of_node) {
2568                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2569                 if (ctrl_id < 0)
2570                         ctrl_id = 0;
2571         } else {
2572                 ctrl_id = to_platform_device(host->dev)->id;
2573         }
2574         if (drv_data && drv_data->caps)
2575                 mmc->caps |= drv_data->caps[ctrl_id];
2576 
2577         if (host->pdata->caps2)
2578                 mmc->caps2 = host->pdata->caps2;
2579 
2580         dw_mci_slot_of_parse(slot);
2581 
2582         ret = mmc_of_parse(mmc);
2583         if (ret)
2584                 goto err_host_allocated;
2585 
2586         /* Useful defaults if platform data is unset. */
2587         if (host->use_dma == TRANS_MODE_IDMAC) {
2588                 mmc->max_segs = host->ring_size;
2589                 mmc->max_blk_size = 65536;
2590                 mmc->max_seg_size = 0x1000;
2591                 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2592                 mmc->max_blk_count = mmc->max_req_size / 512;
2593         } else if (host->use_dma == TRANS_MODE_EDMAC) {
2594                 mmc->max_segs = 64;
2595                 mmc->max_blk_size = 65536;
2596                 mmc->max_blk_count = 65535;
2597                 mmc->max_req_size =
2598                                 mmc->max_blk_size * mmc->max_blk_count;
2599                 mmc->max_seg_size = mmc->max_req_size;
2600         } else {
2601                 /* TRANS_MODE_PIO */
2602                 mmc->max_segs = 64;
2603                 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
2604                 mmc->max_blk_count = 512;
2605                 mmc->max_req_size = mmc->max_blk_size *
2606                                     mmc->max_blk_count;
2607                 mmc->max_seg_size = mmc->max_req_size;
2608         }
2609 
2610         if (dw_mci_get_cd(mmc))
2611                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2612         else
2613                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2614 
2615         ret = mmc_add_host(mmc);
2616         if (ret)
2617                 goto err_host_allocated;
2618 
2619 #if defined(CONFIG_DEBUG_FS)
2620         dw_mci_init_debugfs(slot);
2621 #endif
2622 
2623         return 0;
2624 
2625 err_host_allocated:
2626         mmc_free_host(mmc);
2627         return ret;
2628 }
2629 
2630 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2631 {
2632         /* Debugfs stuff is cleaned up by mmc core */
2633         mmc_remove_host(slot->mmc);
2634         slot->host->slot[id] = NULL;
2635         mmc_free_host(slot->mmc);
2636 }
2637 
2638 static void dw_mci_init_dma(struct dw_mci *host)
2639 {
2640         int addr_config;
2641         struct device *dev = host->dev;
2642         struct device_node *np = dev->of_node;
2643 
2644         /*
2645         * Check tansfer mode from HCON[17:16]
2646         * Clear the ambiguous description of dw_mmc databook:
2647         * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2648         * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2649         * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2650         * 2b'11: Non DW DMA Interface -> pio only
2651         * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2652         * simpler request/acknowledge handshake mechanism and both of them
2653         * are regarded as external dma master for dw_mmc.
2654         */
2655         host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2656         if (host->use_dma == DMA_INTERFACE_IDMA) {
2657                 host->use_dma = TRANS_MODE_IDMAC;
2658         } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2659                    host->use_dma == DMA_INTERFACE_GDMA) {
2660                 host->use_dma = TRANS_MODE_EDMAC;
2661         } else {
2662                 goto no_dma;
2663         }
2664 
2665         /* Determine which DMA interface to use */
2666         if (host->use_dma == TRANS_MODE_IDMAC) {
2667                 /*
2668                 * Check ADDR_CONFIG bit in HCON to find
2669                 * IDMAC address bus width
2670                 */
2671                 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2672 
2673                 if (addr_config == 1) {
2674                         /* host supports IDMAC in 64-bit address mode */
2675                         host->dma_64bit_address = 1;
2676                         dev_info(host->dev,
2677                                  "IDMAC supports 64-bit address mode.\n");
2678                         if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2679                                 dma_set_coherent_mask(host->dev,
2680                                                       DMA_BIT_MASK(64));
2681                 } else {
2682                         /* host supports IDMAC in 32-bit address mode */
2683                         host->dma_64bit_address = 0;
2684                         dev_info(host->dev,
2685                                  "IDMAC supports 32-bit address mode.\n");
2686                 }
2687 
2688                 /* Alloc memory for sg translation */
2689                 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
2690                                                    &host->sg_dma, GFP_KERNEL);
2691                 if (!host->sg_cpu) {
2692                         dev_err(host->dev,
2693                                 "%s: could not alloc DMA memory\n",
2694                                 __func__);
2695                         goto no_dma;
2696                 }
2697 
2698                 host->dma_ops = &dw_mci_idmac_ops;
2699                 dev_info(host->dev, "Using internal DMA controller.\n");
2700         } else {
2701                 /* TRANS_MODE_EDMAC: check dma bindings again */
2702                 if ((of_property_count_strings(np, "dma-names") < 0) ||
2703                     (!of_find_property(np, "dmas", NULL))) {
2704                         goto no_dma;
2705                 }
2706                 host->dma_ops = &dw_mci_edmac_ops;
2707                 dev_info(host->dev, "Using external DMA controller.\n");
2708         }
2709 
2710         if (host->dma_ops->init && host->dma_ops->start &&
2711             host->dma_ops->stop && host->dma_ops->cleanup) {
2712                 if (host->dma_ops->init(host)) {
2713                         dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2714                                 __func__);
2715                         goto no_dma;
2716                 }
2717         } else {
2718                 dev_err(host->dev, "DMA initialization not found.\n");
2719                 goto no_dma;
2720         }
2721 
2722         return;
2723 
2724 no_dma:
2725         dev_info(host->dev, "Using PIO mode.\n");
2726         host->use_dma = TRANS_MODE_PIO;
2727 }
2728 
2729 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
2730 {
2731         unsigned long timeout = jiffies + msecs_to_jiffies(500);
2732         u32 ctrl;
2733 
2734         ctrl = mci_readl(host, CTRL);
2735         ctrl |= reset;
2736         mci_writel(host, CTRL, ctrl);
2737 
2738         /* wait till resets clear */
2739         do {
2740                 ctrl = mci_readl(host, CTRL);
2741                 if (!(ctrl & reset))
2742                         return true;
2743         } while (time_before(jiffies, timeout));
2744 
2745         dev_err(host->dev,
2746                 "Timeout resetting block (ctrl reset %#x)\n",
2747                 ctrl & reset);
2748 
2749         return false;
2750 }
2751 
2752 static bool dw_mci_reset(struct dw_mci *host)
2753 {
2754         u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2755         bool ret = false;
2756 
2757         /*
2758          * Reseting generates a block interrupt, hence setting
2759          * the scatter-gather pointer to NULL.
2760          */
2761         if (host->sg) {
2762                 sg_miter_stop(&host->sg_miter);
2763                 host->sg = NULL;
2764         }
2765 
2766         if (host->use_dma)
2767                 flags |= SDMMC_CTRL_DMA_RESET;
2768 
2769         if (dw_mci_ctrl_reset(host, flags)) {
2770                 /*
2771                  * In all cases we clear the RAWINTS register to clear any
2772                  * interrupts.
2773                  */
2774                 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2775 
2776                 /* if using dma we wait for dma_req to clear */
2777                 if (host->use_dma) {
2778                         unsigned long timeout = jiffies + msecs_to_jiffies(500);
2779                         u32 status;
2780 
2781                         do {
2782                                 status = mci_readl(host, STATUS);
2783                                 if (!(status & SDMMC_STATUS_DMA_REQ))
2784                                         break;
2785                                 cpu_relax();
2786                         } while (time_before(jiffies, timeout));
2787 
2788                         if (status & SDMMC_STATUS_DMA_REQ) {
2789                                 dev_err(host->dev,
2790                                         "%s: Timeout waiting for dma_req to clear during reset\n",
2791                                         __func__);
2792                                 goto ciu_out;
2793                         }
2794 
2795                         /* when using DMA next we reset the fifo again */
2796                         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2797                                 goto ciu_out;
2798                 }
2799         } else {
2800                 /* if the controller reset bit did clear, then set clock regs */
2801                 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
2802                         dev_err(host->dev,
2803                                 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
2804                                 __func__);
2805                         goto ciu_out;
2806                 }
2807         }
2808 
2809         if (host->use_dma == TRANS_MODE_IDMAC)
2810                 /* It is also recommended that we reset and reprogram idmac */
2811                 dw_mci_idmac_reset(host);
2812 
2813         ret = true;
2814 
2815 ciu_out:
2816         /* After a CTRL reset we need to have CIU set clock registers  */
2817         mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2818 
2819         return ret;
2820 }
2821 
2822 static void dw_mci_cmd11_timer(unsigned long arg)
2823 {
2824         struct dw_mci *host = (struct dw_mci *)arg;
2825 
2826         if (host->state != STATE_SENDING_CMD11) {
2827                 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2828                 return;
2829         }
2830 
2831         host->cmd_status = SDMMC_INT_RTO;
2832         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2833         tasklet_schedule(&host->tasklet);
2834 }
2835 
2836 static void dw_mci_dto_timer(unsigned long arg)
2837 {
2838         struct dw_mci *host = (struct dw_mci *)arg;
2839 
2840         switch (host->state) {
2841         case STATE_SENDING_DATA:
2842         case STATE_DATA_BUSY:
2843                 /*
2844                  * If DTO interrupt does NOT come in sending data state,
2845                  * we should notify the driver to terminate current transfer
2846                  * and report a data timeout to the core.
2847                  */
2848                 host->data_status = SDMMC_INT_DRTO;
2849                 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2850                 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2851                 tasklet_schedule(&host->tasklet);
2852                 break;
2853         default:
2854                 break;
2855         }
2856 }
2857 
2858 #ifdef CONFIG_OF
2859 static struct dw_mci_of_quirks {
2860         char *quirk;
2861         int id;
2862 } of_quirks[] = {
2863         {
2864                 .quirk  = "broken-cd",
2865                 .id     = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
2866         },
2867 };
2868 
2869 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2870 {
2871         struct dw_mci_board *pdata;
2872         struct device *dev = host->dev;
2873         struct device_node *np = dev->of_node;
2874         const struct dw_mci_drv_data *drv_data = host->drv_data;
2875         int idx, ret;
2876         u32 clock_frequency;
2877 
2878         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2879         if (!pdata)
2880                 return ERR_PTR(-ENOMEM);
2881 
2882         /* find out number of slots supported */
2883         if (of_property_read_u32(dev->of_node, "num-slots",
2884                                 &pdata->num_slots)) {
2885                 dev_info(dev,
2886                          "num-slots property not found, assuming 1 slot is available\n");
2887                 pdata->num_slots = 1;
2888         }
2889 
2890         /* get quirks */
2891         for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
2892                 if (of_get_property(np, of_quirks[idx].quirk, NULL))
2893                         pdata->quirks |= of_quirks[idx].id;
2894 
2895         if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2896                 dev_info(dev,
2897                          "fifo-depth property not found, using value of FIFOTH register as default\n");
2898 
2899         of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2900 
2901         if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2902                 pdata->bus_hz = clock_frequency;
2903 
2904         if (drv_data && drv_data->parse_dt) {
2905                 ret = drv_data->parse_dt(host);
2906                 if (ret)
2907                         return ERR_PTR(ret);
2908         }
2909 
2910         if (of_find_property(np, "supports-highspeed", NULL)) {
2911                 dev_info(dev, "supports-highspeed property is deprecated.\n");
2912                 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2913         }
2914 
2915         return pdata;
2916 }
2917 
2918 #else /* CONFIG_OF */
2919 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2920 {
2921         return ERR_PTR(-EINVAL);
2922 }
2923 #endif /* CONFIG_OF */
2924 
2925 static void dw_mci_enable_cd(struct dw_mci *host)
2926 {
2927         struct dw_mci_board *brd = host->pdata;
2928         unsigned long irqflags;
2929         u32 temp;
2930         int i;
2931 
2932         /* No need for CD if broken card detection */
2933         if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
2934                 return;
2935 
2936         /* No need for CD if all slots have a non-error GPIO */
2937         for (i = 0; i < host->num_slots; i++) {
2938                 struct dw_mci_slot *slot = host->slot[i];
2939 
2940                 if (IS_ERR_VALUE(mmc_gpio_get_cd(slot->mmc)))
2941                         break;
2942         }
2943         if (i == host->num_slots)
2944                 return;
2945 
2946         spin_lock_irqsave(&host->irq_lock, irqflags);
2947         temp = mci_readl(host, INTMASK);
2948         temp  |= SDMMC_INT_CD;
2949         mci_writel(host, INTMASK, temp);
2950         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2951 }
2952 
2953 int dw_mci_probe(struct dw_mci *host)
2954 {
2955         const struct dw_mci_drv_data *drv_data = host->drv_data;
2956         int width, i, ret = 0;
2957         u32 fifo_size;
2958         int init_slots = 0;
2959 
2960         if (!host->pdata) {
2961                 host->pdata = dw_mci_parse_dt(host);
2962                 if (IS_ERR(host->pdata)) {
2963                         dev_err(host->dev, "platform data not available\n");
2964                         return -EINVAL;
2965                 }
2966         }
2967 
2968         if (host->pdata->num_slots < 1) {
2969                 dev_err(host->dev,
2970                         "Platform data must supply num_slots.\n");
2971                 return -ENODEV;
2972         }
2973 
2974         host->biu_clk = devm_clk_get(host->dev, "biu");
2975         if (IS_ERR(host->biu_clk)) {
2976                 dev_dbg(host->dev, "biu clock not available\n");
2977         } else {
2978                 ret = clk_prepare_enable(host->biu_clk);
2979                 if (ret) {
2980                         dev_err(host->dev, "failed to enable biu clock\n");
2981                         return ret;
2982                 }
2983         }
2984 
2985         host->ciu_clk = devm_clk_get(host->dev, "ciu");
2986         if (IS_ERR(host->ciu_clk)) {
2987                 dev_dbg(host->dev, "ciu clock not available\n");
2988                 host->bus_hz = host->pdata->bus_hz;
2989         } else {
2990                 ret = clk_prepare_enable(host->ciu_clk);
2991                 if (ret) {
2992                         dev_err(host->dev, "failed to enable ciu clock\n");
2993                         goto err_clk_biu;
2994                 }
2995 
2996                 if (host->pdata->bus_hz) {
2997                         ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
2998                         if (ret)
2999                                 dev_warn(host->dev,
3000                                          "Unable to set bus rate to %uHz\n",
3001                                          host->pdata->bus_hz);
3002                 }
3003                 host->bus_hz = clk_get_rate(host->ciu_clk);
3004         }
3005 
3006         if (!host->bus_hz) {
3007                 dev_err(host->dev,
3008                         "Platform data must supply bus speed\n");
3009                 ret = -ENODEV;
3010                 goto err_clk_ciu;
3011         }
3012 
3013         if (drv_data && drv_data->init) {
3014                 ret = drv_data->init(host);
3015                 if (ret) {
3016                         dev_err(host->dev,
3017                                 "implementation specific init failed\n");
3018                         goto err_clk_ciu;
3019                 }
3020         }
3021 
3022         if (drv_data && drv_data->setup_clock) {
3023                 ret = drv_data->setup_clock(host);
3024                 if (ret) {
3025                         dev_err(host->dev,
3026                                 "implementation specific clock setup failed\n");
3027                         goto err_clk_ciu;
3028                 }
3029         }
3030 
3031         setup_timer(&host->cmd11_timer,
3032                     dw_mci_cmd11_timer, (unsigned long)host);
3033 
3034         host->quirks = host->pdata->quirks;
3035 
3036         if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO)
3037                 setup_timer(&host->dto_timer,
3038                             dw_mci_dto_timer, (unsigned long)host);
3039 
3040         spin_lock_init(&host->lock);
3041         spin_lock_init(&host->irq_lock);
3042         INIT_LIST_HEAD(&host->queue);
3043 
3044         /*
3045          * Get the host data width - this assumes that HCON has been set with
3046          * the correct values.
3047          */
3048         i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3049         if (!i) {
3050                 host->push_data = dw_mci_push_data16;
3051                 host->pull_data = dw_mci_pull_data16;
3052                 width = 16;
3053                 host->data_shift = 1;
3054         } else if (i == 2) {
3055                 host->push_data = dw_mci_push_data64;
3056                 host->pull_data = dw_mci_pull_data64;
3057                 width = 64;
3058                 host->data_shift = 3;
3059         } else {
3060                 /* Check for a reserved value, and warn if it is */
3061                 WARN((i != 1),
3062                      "HCON reports a reserved host data width!\n"
3063                      "Defaulting to 32-bit access.\n");
3064                 host->push_data = dw_mci_push_data32;
3065                 host->pull_data = dw_mci_pull_data32;
3066                 width = 32;
3067                 host->data_shift = 2;
3068         }
3069 
3070         /* Reset all blocks */
3071         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS))
3072                 return -ENODEV;
3073 
3074         host->dma_ops = host->pdata->dma_ops;
3075         dw_mci_init_dma(host);
3076 
3077         /* Clear the interrupts for the host controller */
3078         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3079         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3080 
3081         /* Put in max timeout */
3082         mci_writel(host, TMOUT, 0xFFFFFFFF);
3083 
3084         /*
3085          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
3086          *                          Tx Mark = fifo_size / 2 DMA Size = 8
3087          */
3088         if (!host->pdata->fifo_depth) {
3089                 /*
3090                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3091                  * have been overwritten by the bootloader, just like we're
3092                  * about to do, so if you know the value for your hardware, you
3093                  * should put it in the platform data.
3094                  */
3095                 fifo_size = mci_readl(host, FIFOTH);
3096                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3097         } else {
3098                 fifo_size = host->pdata->fifo_depth;
3099         }
3100         host->fifo_depth = fifo_size;
3101         host->fifoth_val =
3102                 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3103         mci_writel(host, FIFOTH, host->fifoth_val);
3104 
3105         /* disable clock to CIU */
3106         mci_writel(host, CLKENA, 0);
3107         mci_writel(host, CLKSRC, 0);
3108 
3109         /*
3110          * In 2.40a spec, Data offset is changed.
3111          * Need to check the version-id and set data-offset for DATA register.
3112          */
3113         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3114         dev_info(host->dev, "Version ID is %04x\n", host->verid);
3115 
3116         if (host->verid < DW_MMC_240A)
3117                 host->fifo_reg = host->regs + DATA_OFFSET;
3118         else
3119                 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3120 
3121         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3122         ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3123                                host->irq_flags, "dw-mci", host);
3124         if (ret)
3125                 goto err_dmaunmap;
3126 
3127         if (host->pdata->num_slots)
3128                 host->num_slots = host->pdata->num_slots;
3129         else
3130                 host->num_slots = SDMMC_GET_SLOT_NUM(mci_readl(host, HCON));
3131 
3132         /*
3133          * Enable interrupts for command done, data over, data empty,
3134          * receive ready and error such as transmit, receive timeout, crc error
3135          */
3136         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3137         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3138                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3139                    DW_MCI_ERROR_FLAGS);
3140         /* Enable mci interrupt */
3141         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3142 
3143         dev_info(host->dev,
3144                  "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3145                  host->irq, width, fifo_size);
3146 
3147         /* We need at least one slot to succeed */
3148         for (i = 0; i < host->num_slots; i++) {
3149                 ret = dw_mci_init_slot(host, i);
3150                 if (ret)
3151                         dev_dbg(host->dev, "slot %d init failed\n", i);
3152                 else
3153                         init_slots++;
3154         }
3155 
3156         if (init_slots) {
3157                 dev_info(host->dev, "%d slots initialized\n", init_slots);
3158         } else {
3159                 dev_dbg(host->dev,
3160                         "attempted to initialize %d slots, but failed on all\n",
3161                         host->num_slots);
3162                 goto err_dmaunmap;
3163         }
3164 
3165         /* Now that slots are all setup, we can enable card detect */
3166         dw_mci_enable_cd(host);
3167 
3168         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
3169                 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
3170 
3171         return 0;
3172 
3173 err_dmaunmap:
3174         if (host->use_dma && host->dma_ops->exit)
3175                 host->dma_ops->exit(host);
3176 
3177 err_clk_ciu:
3178         if (!IS_ERR(host->ciu_clk))
3179                 clk_disable_unprepare(host->ciu_clk);
3180 
3181 err_clk_biu:
3182         if (!IS_ERR(host->biu_clk))
3183                 clk_disable_unprepare(host->biu_clk);
3184 
3185         return ret;
3186 }
3187 EXPORT_SYMBOL(dw_mci_probe);
3188 
3189 void dw_mci_remove(struct dw_mci *host)
3190 {
3191         int i;
3192 
3193         for (i = 0; i < host->num_slots; i++) {
3194                 dev_dbg(host->dev, "remove slot %d\n", i);
3195                 if (host->slot[i])
3196                         dw_mci_cleanup_slot(host->slot[i], i);
3197         }
3198 
3199         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3200         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3201 
3202         /* disable clock to CIU */
3203         mci_writel(host, CLKENA, 0);
3204         mci_writel(host, CLKSRC, 0);
3205 
3206         if (host->use_dma && host->dma_ops->exit)
3207                 host->dma_ops->exit(host);
3208 
3209         if (!IS_ERR(host->ciu_clk))
3210                 clk_disable_unprepare(host->ciu_clk);
3211 
3212         if (!IS_ERR(host->biu_clk))
3213                 clk_disable_unprepare(host->biu_clk);
3214 }
3215 EXPORT_SYMBOL(dw_mci_remove);
3216 
3217 
3218 
3219 #ifdef CONFIG_PM_SLEEP
3220 /*
3221  * TODO: we should probably disable the clock to the card in the suspend path.
3222  */
3223 int dw_mci_suspend(struct dw_mci *host)
3224 {
3225         if (host->use_dma && host->dma_ops->exit)
3226                 host->dma_ops->exit(host);
3227 
3228         return 0;
3229 }
3230 EXPORT_SYMBOL(dw_mci_suspend);
3231 
3232 int dw_mci_resume(struct dw_mci *host)
3233 {
3234         int i, ret;
3235 
3236         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3237                 ret = -ENODEV;
3238                 return ret;
3239         }
3240 
3241         if (host->use_dma && host->dma_ops->init)
3242                 host->dma_ops->init(host);
3243 
3244         /*
3245          * Restore the initial value at FIFOTH register
3246          * And Invalidate the prev_blksz with zero
3247          */
3248         mci_writel(host, FIFOTH, host->fifoth_val);
3249         host->prev_blksz = 0;
3250 
3251         /* Put in max timeout */
3252         mci_writel(host, TMOUT, 0xFFFFFFFF);
3253 
3254         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3255         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3256                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3257                    DW_MCI_ERROR_FLAGS);
3258         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3259 
3260         for (i = 0; i < host->num_slots; i++) {
3261                 struct dw_mci_slot *slot = host->slot[i];
3262 
3263                 if (!slot)
3264                         continue;
3265                 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
3266                         dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
3267                         dw_mci_setup_bus(slot, true);
3268                 }
3269         }
3270 
3271         /* Now that slots are all setup, we can enable card detect */
3272         dw_mci_enable_cd(host);
3273 
3274         return 0;
3275 }
3276 EXPORT_SYMBOL(dw_mci_resume);
3277 #endif /* CONFIG_PM_SLEEP */
3278 
3279 static int __init dw_mci_init(void)
3280 {
3281         pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3282         return 0;
3283 }
3284 
3285 static void __exit dw_mci_exit(void)
3286 {
3287 }
3288 
3289 module_init(dw_mci_init);
3290 module_exit(dw_mci_exit);
3291 
3292 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3293 MODULE_AUTHOR("NXP Semiconductor VietNam");
3294 MODULE_AUTHOR("Imagination Technologies Ltd");
3295 MODULE_LICENSE("GPL v2");
3296 

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