Version:  2.0.40 2.2.26 2.4.37 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0

Linux/drivers/mmc/host/dw_mmc.c

  1 /*
  2  * Synopsys DesignWare Multimedia Card Interface driver
  3  *  (Based on NXP driver for lpc 31xx)
  4  *
  5  * Copyright (C) 2009 NXP Semiconductors
  6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License, or
 11  * (at your option) any later version.
 12  */
 13 
 14 #include <linux/blkdev.h>
 15 #include <linux/clk.h>
 16 #include <linux/debugfs.h>
 17 #include <linux/device.h>
 18 #include <linux/dma-mapping.h>
 19 #include <linux/err.h>
 20 #include <linux/init.h>
 21 #include <linux/interrupt.h>
 22 #include <linux/ioport.h>
 23 #include <linux/module.h>
 24 #include <linux/platform_device.h>
 25 #include <linux/seq_file.h>
 26 #include <linux/slab.h>
 27 #include <linux/stat.h>
 28 #include <linux/delay.h>
 29 #include <linux/irq.h>
 30 #include <linux/mmc/card.h>
 31 #include <linux/mmc/host.h>
 32 #include <linux/mmc/mmc.h>
 33 #include <linux/mmc/sd.h>
 34 #include <linux/mmc/sdio.h>
 35 #include <linux/mmc/dw_mmc.h>
 36 #include <linux/bitops.h>
 37 #include <linux/regulator/consumer.h>
 38 #include <linux/of.h>
 39 #include <linux/of_gpio.h>
 40 #include <linux/mmc/slot-gpio.h>
 41 
 42 #include "dw_mmc.h"
 43 
 44 /* Common flag combinations */
 45 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
 46                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
 47                                  SDMMC_INT_EBE)
 48 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
 49                                  SDMMC_INT_RESP_ERR)
 50 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
 51                                  DW_MCI_CMD_ERROR_FLAGS  | SDMMC_INT_HLE)
 52 #define DW_MCI_SEND_STATUS      1
 53 #define DW_MCI_RECV_STATUS      2
 54 #define DW_MCI_DMA_THRESHOLD    16
 55 
 56 #define DW_MCI_FREQ_MAX 200000000       /* unit: HZ */
 57 #define DW_MCI_FREQ_MIN 400000          /* unit: HZ */
 58 
 59 #ifdef CONFIG_MMC_DW_IDMAC
 60 #define IDMAC_INT_CLR           (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
 61                                  SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
 62                                  SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
 63                                  SDMMC_IDMAC_INT_TI)
 64 
 65 struct idmac_desc_64addr {
 66         u32             des0;   /* Control Descriptor */
 67 
 68         u32             des1;   /* Reserved */
 69 
 70         u32             des2;   /*Buffer sizes */
 71 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
 72         ((d)->des2 = ((d)->des2 & 0x03ffe000) | ((s) & 0x1fff))
 73 
 74         u32             des3;   /* Reserved */
 75 
 76         u32             des4;   /* Lower 32-bits of Buffer Address Pointer 1*/
 77         u32             des5;   /* Upper 32-bits of Buffer Address Pointer 1*/
 78 
 79         u32             des6;   /* Lower 32-bits of Next Descriptor Address */
 80         u32             des7;   /* Upper 32-bits of Next Descriptor Address */
 81 };
 82 
 83 struct idmac_desc {
 84         u32             des0;   /* Control Descriptor */
 85 #define IDMAC_DES0_DIC  BIT(1)
 86 #define IDMAC_DES0_LD   BIT(2)
 87 #define IDMAC_DES0_FD   BIT(3)
 88 #define IDMAC_DES0_CH   BIT(4)
 89 #define IDMAC_DES0_ER   BIT(5)
 90 #define IDMAC_DES0_CES  BIT(30)
 91 #define IDMAC_DES0_OWN  BIT(31)
 92 
 93         u32             des1;   /* Buffer sizes */
 94 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
 95         ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
 96 
 97         u32             des2;   /* buffer 1 physical address */
 98 
 99         u32             des3;   /* buffer 2 physical address */
100 };
101 #endif /* CONFIG_MMC_DW_IDMAC */
102 
103 static bool dw_mci_reset(struct dw_mci *host);
104 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
105 
106 #if defined(CONFIG_DEBUG_FS)
107 static int dw_mci_req_show(struct seq_file *s, void *v)
108 {
109         struct dw_mci_slot *slot = s->private;
110         struct mmc_request *mrq;
111         struct mmc_command *cmd;
112         struct mmc_command *stop;
113         struct mmc_data *data;
114 
115         /* Make sure we get a consistent snapshot */
116         spin_lock_bh(&slot->host->lock);
117         mrq = slot->mrq;
118 
119         if (mrq) {
120                 cmd = mrq->cmd;
121                 data = mrq->data;
122                 stop = mrq->stop;
123 
124                 if (cmd)
125                         seq_printf(s,
126                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
127                                    cmd->opcode, cmd->arg, cmd->flags,
128                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
129                                    cmd->resp[2], cmd->error);
130                 if (data)
131                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
132                                    data->bytes_xfered, data->blocks,
133                                    data->blksz, data->flags, data->error);
134                 if (stop)
135                         seq_printf(s,
136                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
137                                    stop->opcode, stop->arg, stop->flags,
138                                    stop->resp[0], stop->resp[1], stop->resp[2],
139                                    stop->resp[2], stop->error);
140         }
141 
142         spin_unlock_bh(&slot->host->lock);
143 
144         return 0;
145 }
146 
147 static int dw_mci_req_open(struct inode *inode, struct file *file)
148 {
149         return single_open(file, dw_mci_req_show, inode->i_private);
150 }
151 
152 static const struct file_operations dw_mci_req_fops = {
153         .owner          = THIS_MODULE,
154         .open           = dw_mci_req_open,
155         .read           = seq_read,
156         .llseek         = seq_lseek,
157         .release        = single_release,
158 };
159 
160 static int dw_mci_regs_show(struct seq_file *s, void *v)
161 {
162         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
163         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
164         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
165         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
166         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
167         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
168 
169         return 0;
170 }
171 
172 static int dw_mci_regs_open(struct inode *inode, struct file *file)
173 {
174         return single_open(file, dw_mci_regs_show, inode->i_private);
175 }
176 
177 static const struct file_operations dw_mci_regs_fops = {
178         .owner          = THIS_MODULE,
179         .open           = dw_mci_regs_open,
180         .read           = seq_read,
181         .llseek         = seq_lseek,
182         .release        = single_release,
183 };
184 
185 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
186 {
187         struct mmc_host *mmc = slot->mmc;
188         struct dw_mci *host = slot->host;
189         struct dentry *root;
190         struct dentry *node;
191 
192         root = mmc->debugfs_root;
193         if (!root)
194                 return;
195 
196         node = debugfs_create_file("regs", S_IRUSR, root, host,
197                                    &dw_mci_regs_fops);
198         if (!node)
199                 goto err;
200 
201         node = debugfs_create_file("req", S_IRUSR, root, slot,
202                                    &dw_mci_req_fops);
203         if (!node)
204                 goto err;
205 
206         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
207         if (!node)
208                 goto err;
209 
210         node = debugfs_create_x32("pending_events", S_IRUSR, root,
211                                   (u32 *)&host->pending_events);
212         if (!node)
213                 goto err;
214 
215         node = debugfs_create_x32("completed_events", S_IRUSR, root,
216                                   (u32 *)&host->completed_events);
217         if (!node)
218                 goto err;
219 
220         return;
221 
222 err:
223         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
224 }
225 #endif /* defined(CONFIG_DEBUG_FS) */
226 
227 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
228 
229 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
230 {
231         struct mmc_data *data;
232         struct dw_mci_slot *slot = mmc_priv(mmc);
233         struct dw_mci *host = slot->host;
234         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
235         u32 cmdr;
236         cmd->error = -EINPROGRESS;
237 
238         cmdr = cmd->opcode;
239 
240         if (cmd->opcode == MMC_STOP_TRANSMISSION ||
241             cmd->opcode == MMC_GO_IDLE_STATE ||
242             cmd->opcode == MMC_GO_INACTIVE_STATE ||
243             (cmd->opcode == SD_IO_RW_DIRECT &&
244              ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
245                 cmdr |= SDMMC_CMD_STOP;
246         else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
247                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
248 
249         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
250                 u32 clk_en_a;
251 
252                 /* Special bit makes CMD11 not die */
253                 cmdr |= SDMMC_CMD_VOLT_SWITCH;
254 
255                 /* Change state to continue to handle CMD11 weirdness */
256                 WARN_ON(slot->host->state != STATE_SENDING_CMD);
257                 slot->host->state = STATE_SENDING_CMD11;
258 
259                 /*
260                  * We need to disable low power mode (automatic clock stop)
261                  * while doing voltage switch so we don't confuse the card,
262                  * since stopping the clock is a specific part of the UHS
263                  * voltage change dance.
264                  *
265                  * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
266                  * unconditionally turned back on in dw_mci_setup_bus() if it's
267                  * ever called with a non-zero clock.  That shouldn't happen
268                  * until the voltage change is all done.
269                  */
270                 clk_en_a = mci_readl(host, CLKENA);
271                 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
272                 mci_writel(host, CLKENA, clk_en_a);
273                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
274                              SDMMC_CMD_PRV_DAT_WAIT, 0);
275         }
276 
277         if (cmd->flags & MMC_RSP_PRESENT) {
278                 /* We expect a response, so set this bit */
279                 cmdr |= SDMMC_CMD_RESP_EXP;
280                 if (cmd->flags & MMC_RSP_136)
281                         cmdr |= SDMMC_CMD_RESP_LONG;
282         }
283 
284         if (cmd->flags & MMC_RSP_CRC)
285                 cmdr |= SDMMC_CMD_RESP_CRC;
286 
287         data = cmd->data;
288         if (data) {
289                 cmdr |= SDMMC_CMD_DAT_EXP;
290                 if (data->flags & MMC_DATA_STREAM)
291                         cmdr |= SDMMC_CMD_STRM_MODE;
292                 if (data->flags & MMC_DATA_WRITE)
293                         cmdr |= SDMMC_CMD_DAT_WR;
294         }
295 
296         if (drv_data && drv_data->prepare_command)
297                 drv_data->prepare_command(slot->host, &cmdr);
298 
299         return cmdr;
300 }
301 
302 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
303 {
304         struct mmc_command *stop;
305         u32 cmdr;
306 
307         if (!cmd->data)
308                 return 0;
309 
310         stop = &host->stop_abort;
311         cmdr = cmd->opcode;
312         memset(stop, 0, sizeof(struct mmc_command));
313 
314         if (cmdr == MMC_READ_SINGLE_BLOCK ||
315             cmdr == MMC_READ_MULTIPLE_BLOCK ||
316             cmdr == MMC_WRITE_BLOCK ||
317             cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
318             cmdr == MMC_SEND_TUNING_BLOCK ||
319             cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
320                 stop->opcode = MMC_STOP_TRANSMISSION;
321                 stop->arg = 0;
322                 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
323         } else if (cmdr == SD_IO_RW_EXTENDED) {
324                 stop->opcode = SD_IO_RW_DIRECT;
325                 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
326                              ((cmd->arg >> 28) & 0x7);
327                 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
328         } else {
329                 return 0;
330         }
331 
332         cmdr = stop->opcode | SDMMC_CMD_STOP |
333                 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
334 
335         return cmdr;
336 }
337 
338 static void dw_mci_start_command(struct dw_mci *host,
339                                  struct mmc_command *cmd, u32 cmd_flags)
340 {
341         host->cmd = cmd;
342         dev_vdbg(host->dev,
343                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
344                  cmd->arg, cmd_flags);
345 
346         mci_writel(host, CMDARG, cmd->arg);
347         wmb();
348 
349         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
350 }
351 
352 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
353 {
354         struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
355         dw_mci_start_command(host, stop, host->stop_cmdr);
356 }
357 
358 /* DMA interface functions */
359 static void dw_mci_stop_dma(struct dw_mci *host)
360 {
361         if (host->using_dma) {
362                 host->dma_ops->stop(host);
363                 host->dma_ops->cleanup(host);
364         }
365 
366         /* Data transfer was stopped by the interrupt handler */
367         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
368 }
369 
370 static int dw_mci_get_dma_dir(struct mmc_data *data)
371 {
372         if (data->flags & MMC_DATA_WRITE)
373                 return DMA_TO_DEVICE;
374         else
375                 return DMA_FROM_DEVICE;
376 }
377 
378 #ifdef CONFIG_MMC_DW_IDMAC
379 static void dw_mci_dma_cleanup(struct dw_mci *host)
380 {
381         struct mmc_data *data = host->data;
382 
383         if (data)
384                 if (!data->host_cookie)
385                         dma_unmap_sg(host->dev,
386                                      data->sg,
387                                      data->sg_len,
388                                      dw_mci_get_dma_dir(data));
389 }
390 
391 static void dw_mci_idmac_reset(struct dw_mci *host)
392 {
393         u32 bmod = mci_readl(host, BMOD);
394         /* Software reset of DMA */
395         bmod |= SDMMC_IDMAC_SWRESET;
396         mci_writel(host, BMOD, bmod);
397 }
398 
399 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
400 {
401         u32 temp;
402 
403         /* Disable and reset the IDMAC interface */
404         temp = mci_readl(host, CTRL);
405         temp &= ~SDMMC_CTRL_USE_IDMAC;
406         temp |= SDMMC_CTRL_DMA_RESET;
407         mci_writel(host, CTRL, temp);
408 
409         /* Stop the IDMAC running */
410         temp = mci_readl(host, BMOD);
411         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
412         temp |= SDMMC_IDMAC_SWRESET;
413         mci_writel(host, BMOD, temp);
414 }
415 
416 static void dw_mci_idmac_complete_dma(struct dw_mci *host)
417 {
418         struct mmc_data *data = host->data;
419 
420         dev_vdbg(host->dev, "DMA complete\n");
421 
422         host->dma_ops->cleanup(host);
423 
424         /*
425          * If the card was removed, data will be NULL. No point in trying to
426          * send the stop command or waiting for NBUSY in this case.
427          */
428         if (data) {
429                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
430                 tasklet_schedule(&host->tasklet);
431         }
432 }
433 
434 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
435                                     unsigned int sg_len)
436 {
437         int i;
438         if (host->dma_64bit_address == 1) {
439                 struct idmac_desc_64addr *desc = host->sg_cpu;
440 
441                 for (i = 0; i < sg_len; i++, desc++) {
442                         unsigned int length = sg_dma_len(&data->sg[i]);
443                         u64 mem_addr = sg_dma_address(&data->sg[i]);
444 
445                         /*
446                          * Set the OWN bit and disable interrupts for this
447                          * descriptor
448                          */
449                         desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
450                                                 IDMAC_DES0_CH;
451                         /* Buffer length */
452                         IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, length);
453 
454                         /* Physical address to DMA to/from */
455                         desc->des4 = mem_addr & 0xffffffff;
456                         desc->des5 = mem_addr >> 32;
457                 }
458 
459                 /* Set first descriptor */
460                 desc = host->sg_cpu;
461                 desc->des0 |= IDMAC_DES0_FD;
462 
463                 /* Set last descriptor */
464                 desc = host->sg_cpu + (i - 1) *
465                                 sizeof(struct idmac_desc_64addr);
466                 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
467                 desc->des0 |= IDMAC_DES0_LD;
468 
469         } else {
470                 struct idmac_desc *desc = host->sg_cpu;
471 
472                 for (i = 0; i < sg_len; i++, desc++) {
473                         unsigned int length = sg_dma_len(&data->sg[i]);
474                         u32 mem_addr = sg_dma_address(&data->sg[i]);
475 
476                         /*
477                          * Set the OWN bit and disable interrupts for this
478                          * descriptor
479                          */
480                         desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
481                                                 IDMAC_DES0_CH;
482                         /* Buffer length */
483                         IDMAC_SET_BUFFER1_SIZE(desc, length);
484 
485                         /* Physical address to DMA to/from */
486                         desc->des2 = mem_addr;
487                 }
488 
489                 /* Set first descriptor */
490                 desc = host->sg_cpu;
491                 desc->des0 |= IDMAC_DES0_FD;
492 
493                 /* Set last descriptor */
494                 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
495                 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
496                 desc->des0 |= IDMAC_DES0_LD;
497         }
498 
499         wmb();
500 }
501 
502 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
503 {
504         u32 temp;
505 
506         dw_mci_translate_sglist(host, host->data, sg_len);
507 
508         /* Make sure to reset DMA in case we did PIO before this */
509         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
510         dw_mci_idmac_reset(host);
511 
512         /* Select IDMAC interface */
513         temp = mci_readl(host, CTRL);
514         temp |= SDMMC_CTRL_USE_IDMAC;
515         mci_writel(host, CTRL, temp);
516 
517         wmb();
518 
519         /* Enable the IDMAC */
520         temp = mci_readl(host, BMOD);
521         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
522         mci_writel(host, BMOD, temp);
523 
524         /* Start it running */
525         mci_writel(host, PLDMND, 1);
526 }
527 
528 static int dw_mci_idmac_init(struct dw_mci *host)
529 {
530         int i;
531 
532         if (host->dma_64bit_address == 1) {
533                 struct idmac_desc_64addr *p;
534                 /* Number of descriptors in the ring buffer */
535                 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr);
536 
537                 /* Forward link the descriptor list */
538                 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
539                                                                 i++, p++) {
540                         p->des6 = (host->sg_dma +
541                                         (sizeof(struct idmac_desc_64addr) *
542                                                         (i + 1))) & 0xffffffff;
543 
544                         p->des7 = (u64)(host->sg_dma +
545                                         (sizeof(struct idmac_desc_64addr) *
546                                                         (i + 1))) >> 32;
547                         /* Initialize reserved and buffer size fields to "" */
548                         p->des1 = 0;
549                         p->des2 = 0;
550                         p->des3 = 0;
551                 }
552 
553                 /* Set the last descriptor as the end-of-ring descriptor */
554                 p->des6 = host->sg_dma & 0xffffffff;
555                 p->des7 = (u64)host->sg_dma >> 32;
556                 p->des0 = IDMAC_DES0_ER;
557 
558         } else {
559                 struct idmac_desc *p;
560                 /* Number of descriptors in the ring buffer */
561                 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
562 
563                 /* Forward link the descriptor list */
564                 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
565                         p->des3 = host->sg_dma + (sizeof(struct idmac_desc) *
566                                                                 (i + 1));
567 
568                 /* Set the last descriptor as the end-of-ring descriptor */
569                 p->des3 = host->sg_dma;
570                 p->des0 = IDMAC_DES0_ER;
571         }
572 
573         dw_mci_idmac_reset(host);
574 
575         if (host->dma_64bit_address == 1) {
576                 /* Mask out interrupts - get Tx & Rx complete only */
577                 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
578                 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
579                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
580 
581                 /* Set the descriptor base address */
582                 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
583                 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
584 
585         } else {
586                 /* Mask out interrupts - get Tx & Rx complete only */
587                 mci_writel(host, IDSTS, IDMAC_INT_CLR);
588                 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
589                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
590 
591                 /* Set the descriptor base address */
592                 mci_writel(host, DBADDR, host->sg_dma);
593         }
594 
595         return 0;
596 }
597 
598 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
599         .init = dw_mci_idmac_init,
600         .start = dw_mci_idmac_start_dma,
601         .stop = dw_mci_idmac_stop_dma,
602         .complete = dw_mci_idmac_complete_dma,
603         .cleanup = dw_mci_dma_cleanup,
604 };
605 #endif /* CONFIG_MMC_DW_IDMAC */
606 
607 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
608                                    struct mmc_data *data,
609                                    bool next)
610 {
611         struct scatterlist *sg;
612         unsigned int i, sg_len;
613 
614         if (!next && data->host_cookie)
615                 return data->host_cookie;
616 
617         /*
618          * We don't do DMA on "complex" transfers, i.e. with
619          * non-word-aligned buffers or lengths. Also, we don't bother
620          * with all the DMA setup overhead for short transfers.
621          */
622         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
623                 return -EINVAL;
624 
625         if (data->blksz & 3)
626                 return -EINVAL;
627 
628         for_each_sg(data->sg, sg, data->sg_len, i) {
629                 if (sg->offset & 3 || sg->length & 3)
630                         return -EINVAL;
631         }
632 
633         sg_len = dma_map_sg(host->dev,
634                             data->sg,
635                             data->sg_len,
636                             dw_mci_get_dma_dir(data));
637         if (sg_len == 0)
638                 return -EINVAL;
639 
640         if (next)
641                 data->host_cookie = sg_len;
642 
643         return sg_len;
644 }
645 
646 static void dw_mci_pre_req(struct mmc_host *mmc,
647                            struct mmc_request *mrq,
648                            bool is_first_req)
649 {
650         struct dw_mci_slot *slot = mmc_priv(mmc);
651         struct mmc_data *data = mrq->data;
652 
653         if (!slot->host->use_dma || !data)
654                 return;
655 
656         if (data->host_cookie) {
657                 data->host_cookie = 0;
658                 return;
659         }
660 
661         if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
662                 data->host_cookie = 0;
663 }
664 
665 static void dw_mci_post_req(struct mmc_host *mmc,
666                             struct mmc_request *mrq,
667                             int err)
668 {
669         struct dw_mci_slot *slot = mmc_priv(mmc);
670         struct mmc_data *data = mrq->data;
671 
672         if (!slot->host->use_dma || !data)
673                 return;
674 
675         if (data->host_cookie)
676                 dma_unmap_sg(slot->host->dev,
677                              data->sg,
678                              data->sg_len,
679                              dw_mci_get_dma_dir(data));
680         data->host_cookie = 0;
681 }
682 
683 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
684 {
685 #ifdef CONFIG_MMC_DW_IDMAC
686         unsigned int blksz = data->blksz;
687         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
688         u32 fifo_width = 1 << host->data_shift;
689         u32 blksz_depth = blksz / fifo_width, fifoth_val;
690         u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
691         int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
692 
693         tx_wmark = (host->fifo_depth) / 2;
694         tx_wmark_invers = host->fifo_depth - tx_wmark;
695 
696         /*
697          * MSIZE is '1',
698          * if blksz is not a multiple of the FIFO width
699          */
700         if (blksz % fifo_width) {
701                 msize = 0;
702                 rx_wmark = 1;
703                 goto done;
704         }
705 
706         do {
707                 if (!((blksz_depth % mszs[idx]) ||
708                      (tx_wmark_invers % mszs[idx]))) {
709                         msize = idx;
710                         rx_wmark = mszs[idx] - 1;
711                         break;
712                 }
713         } while (--idx > 0);
714         /*
715          * If idx is '', it won't be tried
716          * Thus, initial values are uesed
717          */
718 done:
719         fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
720         mci_writel(host, FIFOTH, fifoth_val);
721 #endif
722 }
723 
724 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
725 {
726         unsigned int blksz = data->blksz;
727         u32 blksz_depth, fifo_depth;
728         u16 thld_size;
729 
730         WARN_ON(!(data->flags & MMC_DATA_READ));
731 
732         /*
733          * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
734          * in the FIFO region, so we really shouldn't access it).
735          */
736         if (host->verid < DW_MMC_240A)
737                 return;
738 
739         if (host->timing != MMC_TIMING_MMC_HS200 &&
740             host->timing != MMC_TIMING_UHS_SDR104)
741                 goto disable;
742 
743         blksz_depth = blksz / (1 << host->data_shift);
744         fifo_depth = host->fifo_depth;
745 
746         if (blksz_depth > fifo_depth)
747                 goto disable;
748 
749         /*
750          * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
751          * If (blksz_depth) <  (fifo_depth >> 1), should be thld_size = blksz
752          * Currently just choose blksz.
753          */
754         thld_size = blksz;
755         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
756         return;
757 
758 disable:
759         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
760 }
761 
762 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
763 {
764         unsigned long irqflags;
765         int sg_len;
766         u32 temp;
767 
768         host->using_dma = 0;
769 
770         /* If we don't have a channel, we can't do DMA */
771         if (!host->use_dma)
772                 return -ENODEV;
773 
774         sg_len = dw_mci_pre_dma_transfer(host, data, 0);
775         if (sg_len < 0) {
776                 host->dma_ops->stop(host);
777                 return sg_len;
778         }
779 
780         host->using_dma = 1;
781 
782         dev_vdbg(host->dev,
783                  "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
784                  (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
785                  sg_len);
786 
787         /*
788          * Decide the MSIZE and RX/TX Watermark.
789          * If current block size is same with previous size,
790          * no need to update fifoth.
791          */
792         if (host->prev_blksz != data->blksz)
793                 dw_mci_adjust_fifoth(host, data);
794 
795         /* Enable the DMA interface */
796         temp = mci_readl(host, CTRL);
797         temp |= SDMMC_CTRL_DMA_ENABLE;
798         mci_writel(host, CTRL, temp);
799 
800         /* Disable RX/TX IRQs, let DMA handle it */
801         spin_lock_irqsave(&host->irq_lock, irqflags);
802         temp = mci_readl(host, INTMASK);
803         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
804         mci_writel(host, INTMASK, temp);
805         spin_unlock_irqrestore(&host->irq_lock, irqflags);
806 
807         host->dma_ops->start(host, sg_len);
808 
809         return 0;
810 }
811 
812 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
813 {
814         unsigned long irqflags;
815         u32 temp;
816 
817         data->error = -EINPROGRESS;
818 
819         WARN_ON(host->data);
820         host->sg = NULL;
821         host->data = data;
822 
823         if (data->flags & MMC_DATA_READ) {
824                 host->dir_status = DW_MCI_RECV_STATUS;
825                 dw_mci_ctrl_rd_thld(host, data);
826         } else {
827                 host->dir_status = DW_MCI_SEND_STATUS;
828         }
829 
830         if (dw_mci_submit_data_dma(host, data)) {
831                 int flags = SG_MITER_ATOMIC;
832                 if (host->data->flags & MMC_DATA_READ)
833                         flags |= SG_MITER_TO_SG;
834                 else
835                         flags |= SG_MITER_FROM_SG;
836 
837                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
838                 host->sg = data->sg;
839                 host->part_buf_start = 0;
840                 host->part_buf_count = 0;
841 
842                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
843 
844                 spin_lock_irqsave(&host->irq_lock, irqflags);
845                 temp = mci_readl(host, INTMASK);
846                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
847                 mci_writel(host, INTMASK, temp);
848                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
849 
850                 temp = mci_readl(host, CTRL);
851                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
852                 mci_writel(host, CTRL, temp);
853 
854                 /*
855                  * Use the initial fifoth_val for PIO mode.
856                  * If next issued data may be transfered by DMA mode,
857                  * prev_blksz should be invalidated.
858                  */
859                 mci_writel(host, FIFOTH, host->fifoth_val);
860                 host->prev_blksz = 0;
861         } else {
862                 /*
863                  * Keep the current block size.
864                  * It will be used to decide whether to update
865                  * fifoth register next time.
866                  */
867                 host->prev_blksz = data->blksz;
868         }
869 }
870 
871 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
872 {
873         struct dw_mci *host = slot->host;
874         unsigned long timeout = jiffies + msecs_to_jiffies(500);
875         unsigned int cmd_status = 0;
876 
877         mci_writel(host, CMDARG, arg);
878         wmb();
879         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
880 
881         while (time_before(jiffies, timeout)) {
882                 cmd_status = mci_readl(host, CMD);
883                 if (!(cmd_status & SDMMC_CMD_START))
884                         return;
885         }
886         dev_err(&slot->mmc->class_dev,
887                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
888                 cmd, arg, cmd_status);
889 }
890 
891 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
892 {
893         struct dw_mci *host = slot->host;
894         unsigned int clock = slot->clock;
895         u32 div;
896         u32 clk_en_a;
897         u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
898 
899         /* We must continue to set bit 28 in CMD until the change is complete */
900         if (host->state == STATE_WAITING_CMD11_DONE)
901                 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
902 
903         if (!clock) {
904                 mci_writel(host, CLKENA, 0);
905                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
906         } else if (clock != host->current_speed || force_clkinit) {
907                 div = host->bus_hz / clock;
908                 if (host->bus_hz % clock && host->bus_hz > clock)
909                         /*
910                          * move the + 1 after the divide to prevent
911                          * over-clocking the card.
912                          */
913                         div += 1;
914 
915                 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
916 
917                 if ((clock << div) != slot->__clk_old || force_clkinit)
918                         dev_info(&slot->mmc->class_dev,
919                                  "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
920                                  slot->id, host->bus_hz, clock,
921                                  div ? ((host->bus_hz / div) >> 1) :
922                                  host->bus_hz, div);
923 
924                 /* disable clock */
925                 mci_writel(host, CLKENA, 0);
926                 mci_writel(host, CLKSRC, 0);
927 
928                 /* inform CIU */
929                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
930 
931                 /* set clock to desired speed */
932                 mci_writel(host, CLKDIV, div);
933 
934                 /* inform CIU */
935                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
936 
937                 /* enable clock; only low power if no SDIO */
938                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
939                 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
940                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
941                 mci_writel(host, CLKENA, clk_en_a);
942 
943                 /* inform CIU */
944                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
945 
946                 /* keep the clock with reflecting clock dividor */
947                 slot->__clk_old = clock << div;
948         }
949 
950         host->current_speed = clock;
951 
952         /* Set the current slot bus width */
953         mci_writel(host, CTYPE, (slot->ctype << slot->id));
954 }
955 
956 static void __dw_mci_start_request(struct dw_mci *host,
957                                    struct dw_mci_slot *slot,
958                                    struct mmc_command *cmd)
959 {
960         struct mmc_request *mrq;
961         struct mmc_data *data;
962         u32 cmdflags;
963 
964         mrq = slot->mrq;
965 
966         host->cur_slot = slot;
967         host->mrq = mrq;
968 
969         host->pending_events = 0;
970         host->completed_events = 0;
971         host->cmd_status = 0;
972         host->data_status = 0;
973         host->dir_status = 0;
974 
975         data = cmd->data;
976         if (data) {
977                 mci_writel(host, TMOUT, 0xFFFFFFFF);
978                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
979                 mci_writel(host, BLKSIZ, data->blksz);
980         }
981 
982         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
983 
984         /* this is the first command, send the initialization clock */
985         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
986                 cmdflags |= SDMMC_CMD_INIT;
987 
988         if (data) {
989                 dw_mci_submit_data(host, data);
990                 wmb();
991         }
992 
993         dw_mci_start_command(host, cmd, cmdflags);
994 
995         if (mrq->stop)
996                 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
997         else
998                 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
999 }
1000 
1001 static void dw_mci_start_request(struct dw_mci *host,
1002                                  struct dw_mci_slot *slot)
1003 {
1004         struct mmc_request *mrq = slot->mrq;
1005         struct mmc_command *cmd;
1006 
1007         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1008         __dw_mci_start_request(host, slot, cmd);
1009 }
1010 
1011 /* must be called with host->lock held */
1012 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1013                                  struct mmc_request *mrq)
1014 {
1015         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1016                  host->state);
1017 
1018         slot->mrq = mrq;
1019 
1020         if (host->state == STATE_WAITING_CMD11_DONE) {
1021                 dev_warn(&slot->mmc->class_dev,
1022                          "Voltage change didn't complete\n");
1023                 /*
1024                  * this case isn't expected to happen, so we can
1025                  * either crash here or just try to continue on
1026                  * in the closest possible state
1027                  */
1028                 host->state = STATE_IDLE;
1029         }
1030 
1031         if (host->state == STATE_IDLE) {
1032                 host->state = STATE_SENDING_CMD;
1033                 dw_mci_start_request(host, slot);
1034         } else {
1035                 list_add_tail(&slot->queue_node, &host->queue);
1036         }
1037 }
1038 
1039 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1040 {
1041         struct dw_mci_slot *slot = mmc_priv(mmc);
1042         struct dw_mci *host = slot->host;
1043 
1044         WARN_ON(slot->mrq);
1045 
1046         /*
1047          * The check for card presence and queueing of the request must be
1048          * atomic, otherwise the card could be removed in between and the
1049          * request wouldn't fail until another card was inserted.
1050          */
1051         spin_lock_bh(&host->lock);
1052 
1053         if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1054                 spin_unlock_bh(&host->lock);
1055                 mrq->cmd->error = -ENOMEDIUM;
1056                 mmc_request_done(mmc, mrq);
1057                 return;
1058         }
1059 
1060         dw_mci_queue_request(host, slot, mrq);
1061 
1062         spin_unlock_bh(&host->lock);
1063 }
1064 
1065 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1066 {
1067         struct dw_mci_slot *slot = mmc_priv(mmc);
1068         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1069         u32 regs;
1070         int ret;
1071 
1072         switch (ios->bus_width) {
1073         case MMC_BUS_WIDTH_4:
1074                 slot->ctype = SDMMC_CTYPE_4BIT;
1075                 break;
1076         case MMC_BUS_WIDTH_8:
1077                 slot->ctype = SDMMC_CTYPE_8BIT;
1078                 break;
1079         default:
1080                 /* set default 1 bit mode */
1081                 slot->ctype = SDMMC_CTYPE_1BIT;
1082         }
1083 
1084         regs = mci_readl(slot->host, UHS_REG);
1085 
1086         /* DDR mode set */
1087         if (ios->timing == MMC_TIMING_MMC_DDR52)
1088                 regs |= ((0x1 << slot->id) << 16);
1089         else
1090                 regs &= ~((0x1 << slot->id) << 16);
1091 
1092         mci_writel(slot->host, UHS_REG, regs);
1093         slot->host->timing = ios->timing;
1094 
1095         /*
1096          * Use mirror of ios->clock to prevent race with mmc
1097          * core ios update when finding the minimum.
1098          */
1099         slot->clock = ios->clock;
1100 
1101         if (drv_data && drv_data->set_ios)
1102                 drv_data->set_ios(slot->host, ios);
1103 
1104         /* Slot specific timing and width adjustment */
1105         dw_mci_setup_bus(slot, false);
1106 
1107         if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1108                 slot->host->state = STATE_IDLE;
1109 
1110         switch (ios->power_mode) {
1111         case MMC_POWER_UP:
1112                 if (!IS_ERR(mmc->supply.vmmc)) {
1113                         ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1114                                         ios->vdd);
1115                         if (ret) {
1116                                 dev_err(slot->host->dev,
1117                                         "failed to enable vmmc regulator\n");
1118                                 /*return, if failed turn on vmmc*/
1119                                 return;
1120                         }
1121                 }
1122                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1123                 regs = mci_readl(slot->host, PWREN);
1124                 regs |= (1 << slot->id);
1125                 mci_writel(slot->host, PWREN, regs);
1126                 break;
1127         case MMC_POWER_ON:
1128                 if (!IS_ERR(mmc->supply.vqmmc) && !slot->host->vqmmc_enabled) {
1129                         ret = regulator_enable(mmc->supply.vqmmc);
1130                         if (ret < 0)
1131                                 dev_err(slot->host->dev,
1132                                         "failed to enable vqmmc regulator\n");
1133                         else
1134                                 slot->host->vqmmc_enabled = true;
1135                 }
1136                 break;
1137         case MMC_POWER_OFF:
1138                 if (!IS_ERR(mmc->supply.vmmc))
1139                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1140 
1141                 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) {
1142                         regulator_disable(mmc->supply.vqmmc);
1143                         slot->host->vqmmc_enabled = false;
1144                 }
1145 
1146                 regs = mci_readl(slot->host, PWREN);
1147                 regs &= ~(1 << slot->id);
1148                 mci_writel(slot->host, PWREN, regs);
1149                 break;
1150         default:
1151                 break;
1152         }
1153 }
1154 
1155 static int dw_mci_card_busy(struct mmc_host *mmc)
1156 {
1157         struct dw_mci_slot *slot = mmc_priv(mmc);
1158         u32 status;
1159 
1160         /*
1161          * Check the busy bit which is low when DAT[3:0]
1162          * (the data lines) are 0000
1163          */
1164         status = mci_readl(slot->host, STATUS);
1165 
1166         return !!(status & SDMMC_STATUS_BUSY);
1167 }
1168 
1169 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1170 {
1171         struct dw_mci_slot *slot = mmc_priv(mmc);
1172         struct dw_mci *host = slot->host;
1173         u32 uhs;
1174         u32 v18 = SDMMC_UHS_18V << slot->id;
1175         int min_uv, max_uv;
1176         int ret;
1177 
1178         /*
1179          * Program the voltage.  Note that some instances of dw_mmc may use
1180          * the UHS_REG for this.  For other instances (like exynos) the UHS_REG
1181          * does no harm but you need to set the regulator directly.  Try both.
1182          */
1183         uhs = mci_readl(host, UHS_REG);
1184         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1185                 min_uv = 2700000;
1186                 max_uv = 3600000;
1187                 uhs &= ~v18;
1188         } else {
1189                 min_uv = 1700000;
1190                 max_uv = 1950000;
1191                 uhs |= v18;
1192         }
1193         if (!IS_ERR(mmc->supply.vqmmc)) {
1194                 ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv);
1195 
1196                 if (ret) {
1197                         dev_dbg(&mmc->class_dev,
1198                                          "Regulator set error %d: %d - %d\n",
1199                                          ret, min_uv, max_uv);
1200                         return ret;
1201                 }
1202         }
1203         mci_writel(host, UHS_REG, uhs);
1204 
1205         return 0;
1206 }
1207 
1208 static int dw_mci_get_ro(struct mmc_host *mmc)
1209 {
1210         int read_only;
1211         struct dw_mci_slot *slot = mmc_priv(mmc);
1212         int gpio_ro = mmc_gpio_get_ro(mmc);
1213 
1214         /* Use platform get_ro function, else try on board write protect */
1215         if ((slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT) ||
1216                         (slot->host->quirks & DW_MCI_QUIRK_NO_WRITE_PROTECT))
1217                 read_only = 0;
1218         else if (!IS_ERR_VALUE(gpio_ro))
1219                 read_only = gpio_ro;
1220         else
1221                 read_only =
1222                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1223 
1224         dev_dbg(&mmc->class_dev, "card is %s\n",
1225                 read_only ? "read-only" : "read-write");
1226 
1227         return read_only;
1228 }
1229 
1230 static int dw_mci_get_cd(struct mmc_host *mmc)
1231 {
1232         int present;
1233         struct dw_mci_slot *slot = mmc_priv(mmc);
1234         struct dw_mci_board *brd = slot->host->pdata;
1235         struct dw_mci *host = slot->host;
1236         int gpio_cd = mmc_gpio_get_cd(mmc);
1237 
1238         /* Use platform get_cd function, else try onboard card detect */
1239         if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
1240                 present = 1;
1241         else if (!IS_ERR_VALUE(gpio_cd))
1242                 present = gpio_cd;
1243         else
1244                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1245                         == 0 ? 1 : 0;
1246 
1247         spin_lock_bh(&host->lock);
1248         if (present) {
1249                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1250                 dev_dbg(&mmc->class_dev, "card is present\n");
1251         } else {
1252                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1253                 dev_dbg(&mmc->class_dev, "card is not present\n");
1254         }
1255         spin_unlock_bh(&host->lock);
1256 
1257         return present;
1258 }
1259 
1260 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1261 {
1262         struct dw_mci_slot *slot = mmc_priv(mmc);
1263         struct dw_mci *host = slot->host;
1264 
1265         /*
1266          * Low power mode will stop the card clock when idle.  According to the
1267          * description of the CLKENA register we should disable low power mode
1268          * for SDIO cards if we need SDIO interrupts to work.
1269          */
1270         if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1271                 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1272                 u32 clk_en_a_old;
1273                 u32 clk_en_a;
1274 
1275                 clk_en_a_old = mci_readl(host, CLKENA);
1276 
1277                 if (card->type == MMC_TYPE_SDIO ||
1278                     card->type == MMC_TYPE_SD_COMBO) {
1279                         set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1280                         clk_en_a = clk_en_a_old & ~clken_low_pwr;
1281                 } else {
1282                         clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1283                         clk_en_a = clk_en_a_old | clken_low_pwr;
1284                 }
1285 
1286                 if (clk_en_a != clk_en_a_old) {
1287                         mci_writel(host, CLKENA, clk_en_a);
1288                         mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1289                                      SDMMC_CMD_PRV_DAT_WAIT, 0);
1290                 }
1291         }
1292 }
1293 
1294 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1295 {
1296         struct dw_mci_slot *slot = mmc_priv(mmc);
1297         struct dw_mci *host = slot->host;
1298         unsigned long irqflags;
1299         u32 int_mask;
1300 
1301         spin_lock_irqsave(&host->irq_lock, irqflags);
1302 
1303         /* Enable/disable Slot Specific SDIO interrupt */
1304         int_mask = mci_readl(host, INTMASK);
1305         if (enb)
1306                 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1307         else
1308                 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1309         mci_writel(host, INTMASK, int_mask);
1310 
1311         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1312 }
1313 
1314 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1315 {
1316         struct dw_mci_slot *slot = mmc_priv(mmc);
1317         struct dw_mci *host = slot->host;
1318         const struct dw_mci_drv_data *drv_data = host->drv_data;
1319         int err = -ENOSYS;
1320 
1321         if (drv_data && drv_data->execute_tuning)
1322                 err = drv_data->execute_tuning(slot);
1323         return err;
1324 }
1325 
1326 static const struct mmc_host_ops dw_mci_ops = {
1327         .request                = dw_mci_request,
1328         .pre_req                = dw_mci_pre_req,
1329         .post_req               = dw_mci_post_req,
1330         .set_ios                = dw_mci_set_ios,
1331         .get_ro                 = dw_mci_get_ro,
1332         .get_cd                 = dw_mci_get_cd,
1333         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
1334         .execute_tuning         = dw_mci_execute_tuning,
1335         .card_busy              = dw_mci_card_busy,
1336         .start_signal_voltage_switch = dw_mci_switch_voltage,
1337         .init_card              = dw_mci_init_card,
1338 };
1339 
1340 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1341         __releases(&host->lock)
1342         __acquires(&host->lock)
1343 {
1344         struct dw_mci_slot *slot;
1345         struct mmc_host *prev_mmc = host->cur_slot->mmc;
1346 
1347         WARN_ON(host->cmd || host->data);
1348 
1349         host->cur_slot->mrq = NULL;
1350         host->mrq = NULL;
1351         if (!list_empty(&host->queue)) {
1352                 slot = list_entry(host->queue.next,
1353                                   struct dw_mci_slot, queue_node);
1354                 list_del(&slot->queue_node);
1355                 dev_vdbg(host->dev, "list not empty: %s is next\n",
1356                          mmc_hostname(slot->mmc));
1357                 host->state = STATE_SENDING_CMD;
1358                 dw_mci_start_request(host, slot);
1359         } else {
1360                 dev_vdbg(host->dev, "list empty\n");
1361 
1362                 if (host->state == STATE_SENDING_CMD11)
1363                         host->state = STATE_WAITING_CMD11_DONE;
1364                 else
1365                         host->state = STATE_IDLE;
1366         }
1367 
1368         spin_unlock(&host->lock);
1369         mmc_request_done(prev_mmc, mrq);
1370         spin_lock(&host->lock);
1371 }
1372 
1373 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1374 {
1375         u32 status = host->cmd_status;
1376 
1377         host->cmd_status = 0;
1378 
1379         /* Read the response from the card (up to 16 bytes) */
1380         if (cmd->flags & MMC_RSP_PRESENT) {
1381                 if (cmd->flags & MMC_RSP_136) {
1382                         cmd->resp[3] = mci_readl(host, RESP0);
1383                         cmd->resp[2] = mci_readl(host, RESP1);
1384                         cmd->resp[1] = mci_readl(host, RESP2);
1385                         cmd->resp[0] = mci_readl(host, RESP3);
1386                 } else {
1387                         cmd->resp[0] = mci_readl(host, RESP0);
1388                         cmd->resp[1] = 0;
1389                         cmd->resp[2] = 0;
1390                         cmd->resp[3] = 0;
1391                 }
1392         }
1393 
1394         if (status & SDMMC_INT_RTO)
1395                 cmd->error = -ETIMEDOUT;
1396         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1397                 cmd->error = -EILSEQ;
1398         else if (status & SDMMC_INT_RESP_ERR)
1399                 cmd->error = -EIO;
1400         else
1401                 cmd->error = 0;
1402 
1403         if (cmd->error) {
1404                 /* newer ip versions need a delay between retries */
1405                 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
1406                         mdelay(20);
1407         }
1408 
1409         return cmd->error;
1410 }
1411 
1412 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1413 {
1414         u32 status = host->data_status;
1415 
1416         if (status & DW_MCI_DATA_ERROR_FLAGS) {
1417                 if (status & SDMMC_INT_DRTO) {
1418                         data->error = -ETIMEDOUT;
1419                 } else if (status & SDMMC_INT_DCRC) {
1420                         data->error = -EILSEQ;
1421                 } else if (status & SDMMC_INT_EBE) {
1422                         if (host->dir_status ==
1423                                 DW_MCI_SEND_STATUS) {
1424                                 /*
1425                                  * No data CRC status was returned.
1426                                  * The number of bytes transferred
1427                                  * will be exaggerated in PIO mode.
1428                                  */
1429                                 data->bytes_xfered = 0;
1430                                 data->error = -ETIMEDOUT;
1431                         } else if (host->dir_status ==
1432                                         DW_MCI_RECV_STATUS) {
1433                                 data->error = -EIO;
1434                         }
1435                 } else {
1436                         /* SDMMC_INT_SBE is included */
1437                         data->error = -EIO;
1438                 }
1439 
1440                 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1441 
1442                 /*
1443                  * After an error, there may be data lingering
1444                  * in the FIFO
1445                  */
1446                 dw_mci_reset(host);
1447         } else {
1448                 data->bytes_xfered = data->blocks * data->blksz;
1449                 data->error = 0;
1450         }
1451 
1452         return data->error;
1453 }
1454 
1455 static void dw_mci_tasklet_func(unsigned long priv)
1456 {
1457         struct dw_mci *host = (struct dw_mci *)priv;
1458         struct mmc_data *data;
1459         struct mmc_command *cmd;
1460         struct mmc_request *mrq;
1461         enum dw_mci_state state;
1462         enum dw_mci_state prev_state;
1463         unsigned int err;
1464 
1465         spin_lock(&host->lock);
1466 
1467         state = host->state;
1468         data = host->data;
1469         mrq = host->mrq;
1470 
1471         do {
1472                 prev_state = state;
1473 
1474                 switch (state) {
1475                 case STATE_IDLE:
1476                 case STATE_WAITING_CMD11_DONE:
1477                         break;
1478 
1479                 case STATE_SENDING_CMD11:
1480                 case STATE_SENDING_CMD:
1481                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1482                                                 &host->pending_events))
1483                                 break;
1484 
1485                         cmd = host->cmd;
1486                         host->cmd = NULL;
1487                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1488                         err = dw_mci_command_complete(host, cmd);
1489                         if (cmd == mrq->sbc && !err) {
1490                                 prev_state = state = STATE_SENDING_CMD;
1491                                 __dw_mci_start_request(host, host->cur_slot,
1492                                                        mrq->cmd);
1493                                 goto unlock;
1494                         }
1495 
1496                         if (cmd->data && err) {
1497                                 dw_mci_stop_dma(host);
1498                                 send_stop_abort(host, data);
1499                                 state = STATE_SENDING_STOP;
1500                                 break;
1501                         }
1502 
1503                         if (!cmd->data || err) {
1504                                 dw_mci_request_end(host, mrq);
1505                                 goto unlock;
1506                         }
1507 
1508                         prev_state = state = STATE_SENDING_DATA;
1509                         /* fall through */
1510 
1511                 case STATE_SENDING_DATA:
1512                         /*
1513                          * We could get a data error and never a transfer
1514                          * complete so we'd better check for it here.
1515                          *
1516                          * Note that we don't really care if we also got a
1517                          * transfer complete; stopping the DMA and sending an
1518                          * abort won't hurt.
1519                          */
1520                         if (test_and_clear_bit(EVENT_DATA_ERROR,
1521                                                &host->pending_events)) {
1522                                 dw_mci_stop_dma(host);
1523                                 send_stop_abort(host, data);
1524                                 state = STATE_DATA_ERROR;
1525                                 break;
1526                         }
1527 
1528                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1529                                                 &host->pending_events))
1530                                 break;
1531 
1532                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1533 
1534                         /*
1535                          * Handle an EVENT_DATA_ERROR that might have shown up
1536                          * before the transfer completed.  This might not have
1537                          * been caught by the check above because the interrupt
1538                          * could have gone off between the previous check and
1539                          * the check for transfer complete.
1540                          *
1541                          * Technically this ought not be needed assuming we
1542                          * get a DATA_COMPLETE eventually (we'll notice the
1543                          * error and end the request), but it shouldn't hurt.
1544                          *
1545                          * This has the advantage of sending the stop command.
1546                          */
1547                         if (test_and_clear_bit(EVENT_DATA_ERROR,
1548                                                &host->pending_events)) {
1549                                 dw_mci_stop_dma(host);
1550                                 send_stop_abort(host, data);
1551                                 state = STATE_DATA_ERROR;
1552                                 break;
1553                         }
1554                         prev_state = state = STATE_DATA_BUSY;
1555 
1556                         /* fall through */
1557 
1558                 case STATE_DATA_BUSY:
1559                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1560                                                 &host->pending_events))
1561                                 break;
1562 
1563                         host->data = NULL;
1564                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1565                         err = dw_mci_data_complete(host, data);
1566 
1567                         if (!err) {
1568                                 if (!data->stop || mrq->sbc) {
1569                                         if (mrq->sbc && data->stop)
1570                                                 data->stop->error = 0;
1571                                         dw_mci_request_end(host, mrq);
1572                                         goto unlock;
1573                                 }
1574 
1575                                 /* stop command for open-ended transfer*/
1576                                 if (data->stop)
1577                                         send_stop_abort(host, data);
1578                         } else {
1579                                 /*
1580                                  * If we don't have a command complete now we'll
1581                                  * never get one since we just reset everything;
1582                                  * better end the request.
1583                                  *
1584                                  * If we do have a command complete we'll fall
1585                                  * through to the SENDING_STOP command and
1586                                  * everything will be peachy keen.
1587                                  */
1588                                 if (!test_bit(EVENT_CMD_COMPLETE,
1589                                               &host->pending_events)) {
1590                                         host->cmd = NULL;
1591                                         dw_mci_request_end(host, mrq);
1592                                         goto unlock;
1593                                 }
1594                         }
1595 
1596                         /*
1597                          * If err has non-zero,
1598                          * stop-abort command has been already issued.
1599                          */
1600                         prev_state = state = STATE_SENDING_STOP;
1601 
1602                         /* fall through */
1603 
1604                 case STATE_SENDING_STOP:
1605                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1606                                                 &host->pending_events))
1607                                 break;
1608 
1609                         /* CMD error in data command */
1610                         if (mrq->cmd->error && mrq->data)
1611                                 dw_mci_reset(host);
1612 
1613                         host->cmd = NULL;
1614                         host->data = NULL;
1615 
1616                         if (mrq->stop)
1617                                 dw_mci_command_complete(host, mrq->stop);
1618                         else
1619                                 host->cmd_status = 0;
1620 
1621                         dw_mci_request_end(host, mrq);
1622                         goto unlock;
1623 
1624                 case STATE_DATA_ERROR:
1625                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1626                                                 &host->pending_events))
1627                                 break;
1628 
1629                         state = STATE_DATA_BUSY;
1630                         break;
1631                 }
1632         } while (state != prev_state);
1633 
1634         host->state = state;
1635 unlock:
1636         spin_unlock(&host->lock);
1637 
1638 }
1639 
1640 /* push final bytes to part_buf, only use during push */
1641 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
1642 {
1643         memcpy((void *)&host->part_buf, buf, cnt);
1644         host->part_buf_count = cnt;
1645 }
1646 
1647 /* append bytes to part_buf, only use during push */
1648 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1649 {
1650         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1651         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1652         host->part_buf_count += cnt;
1653         return cnt;
1654 }
1655 
1656 /* pull first bytes from part_buf, only use during pull */
1657 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1658 {
1659         cnt = min(cnt, (int)host->part_buf_count);
1660         if (cnt) {
1661                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1662                        cnt);
1663                 host->part_buf_count -= cnt;
1664                 host->part_buf_start += cnt;
1665         }
1666         return cnt;
1667 }
1668 
1669 /* pull final bytes from the part_buf, assuming it's just been filled */
1670 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
1671 {
1672         memcpy(buf, &host->part_buf, cnt);
1673         host->part_buf_start = cnt;
1674         host->part_buf_count = (1 << host->data_shift) - cnt;
1675 }
1676 
1677 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1678 {
1679         struct mmc_data *data = host->data;
1680         int init_cnt = cnt;
1681 
1682         /* try and push anything in the part_buf */
1683         if (unlikely(host->part_buf_count)) {
1684                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1685                 buf += len;
1686                 cnt -= len;
1687                 if (host->part_buf_count == 2) {
1688                         mci_writew(host, DATA(host->data_offset),
1689                                         host->part_buf16);
1690                         host->part_buf_count = 0;
1691                 }
1692         }
1693 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1694         if (unlikely((unsigned long)buf & 0x1)) {
1695                 while (cnt >= 2) {
1696                         u16 aligned_buf[64];
1697                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
1698                         int items = len >> 1;
1699                         int i;
1700                         /* memcpy from input buffer into aligned buffer */
1701                         memcpy(aligned_buf, buf, len);
1702                         buf += len;
1703                         cnt -= len;
1704                         /* push data from aligned buffer into fifo */
1705                         for (i = 0; i < items; ++i)
1706                                 mci_writew(host, DATA(host->data_offset),
1707                                                 aligned_buf[i]);
1708                 }
1709         } else
1710 #endif
1711         {
1712                 u16 *pdata = buf;
1713                 for (; cnt >= 2; cnt -= 2)
1714                         mci_writew(host, DATA(host->data_offset), *pdata++);
1715                 buf = pdata;
1716         }
1717         /* put anything remaining in the part_buf */
1718         if (cnt) {
1719                 dw_mci_set_part_bytes(host, buf, cnt);
1720                  /* Push data if we have reached the expected data length */
1721                 if ((data->bytes_xfered + init_cnt) ==
1722                     (data->blksz * data->blocks))
1723                         mci_writew(host, DATA(host->data_offset),
1724                                    host->part_buf16);
1725         }
1726 }
1727 
1728 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1729 {
1730 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1731         if (unlikely((unsigned long)buf & 0x1)) {
1732                 while (cnt >= 2) {
1733                         /* pull data from fifo into aligned buffer */
1734                         u16 aligned_buf[64];
1735                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
1736                         int items = len >> 1;
1737                         int i;
1738                         for (i = 0; i < items; ++i)
1739                                 aligned_buf[i] = mci_readw(host,
1740                                                 DATA(host->data_offset));
1741                         /* memcpy from aligned buffer into output buffer */
1742                         memcpy(buf, aligned_buf, len);
1743                         buf += len;
1744                         cnt -= len;
1745                 }
1746         } else
1747 #endif
1748         {
1749                 u16 *pdata = buf;
1750                 for (; cnt >= 2; cnt -= 2)
1751                         *pdata++ = mci_readw(host, DATA(host->data_offset));
1752                 buf = pdata;
1753         }
1754         if (cnt) {
1755                 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
1756                 dw_mci_pull_final_bytes(host, buf, cnt);
1757         }
1758 }
1759 
1760 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1761 {
1762         struct mmc_data *data = host->data;
1763         int init_cnt = cnt;
1764 
1765         /* try and push anything in the part_buf */
1766         if (unlikely(host->part_buf_count)) {
1767                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1768                 buf += len;
1769                 cnt -= len;
1770                 if (host->part_buf_count == 4) {
1771                         mci_writel(host, DATA(host->data_offset),
1772                                         host->part_buf32);
1773                         host->part_buf_count = 0;
1774                 }
1775         }
1776 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1777         if (unlikely((unsigned long)buf & 0x3)) {
1778                 while (cnt >= 4) {
1779                         u32 aligned_buf[32];
1780                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
1781                         int items = len >> 2;
1782                         int i;
1783                         /* memcpy from input buffer into aligned buffer */
1784                         memcpy(aligned_buf, buf, len);
1785                         buf += len;
1786                         cnt -= len;
1787                         /* push data from aligned buffer into fifo */
1788                         for (i = 0; i < items; ++i)
1789                                 mci_writel(host, DATA(host->data_offset),
1790                                                 aligned_buf[i]);
1791                 }
1792         } else
1793 #endif
1794         {
1795                 u32 *pdata = buf;
1796                 for (; cnt >= 4; cnt -= 4)
1797                         mci_writel(host, DATA(host->data_offset), *pdata++);
1798                 buf = pdata;
1799         }
1800         /* put anything remaining in the part_buf */
1801         if (cnt) {
1802                 dw_mci_set_part_bytes(host, buf, cnt);
1803                  /* Push data if we have reached the expected data length */
1804                 if ((data->bytes_xfered + init_cnt) ==
1805                     (data->blksz * data->blocks))
1806                         mci_writel(host, DATA(host->data_offset),
1807                                    host->part_buf32);
1808         }
1809 }
1810 
1811 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1812 {
1813 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1814         if (unlikely((unsigned long)buf & 0x3)) {
1815                 while (cnt >= 4) {
1816                         /* pull data from fifo into aligned buffer */
1817                         u32 aligned_buf[32];
1818                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
1819                         int items = len >> 2;
1820                         int i;
1821                         for (i = 0; i < items; ++i)
1822                                 aligned_buf[i] = mci_readl(host,
1823                                                 DATA(host->data_offset));
1824                         /* memcpy from aligned buffer into output buffer */
1825                         memcpy(buf, aligned_buf, len);
1826                         buf += len;
1827                         cnt -= len;
1828                 }
1829         } else
1830 #endif
1831         {
1832                 u32 *pdata = buf;
1833                 for (; cnt >= 4; cnt -= 4)
1834                         *pdata++ = mci_readl(host, DATA(host->data_offset));
1835                 buf = pdata;
1836         }
1837         if (cnt) {
1838                 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
1839                 dw_mci_pull_final_bytes(host, buf, cnt);
1840         }
1841 }
1842 
1843 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1844 {
1845         struct mmc_data *data = host->data;
1846         int init_cnt = cnt;
1847 
1848         /* try and push anything in the part_buf */
1849         if (unlikely(host->part_buf_count)) {
1850                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1851                 buf += len;
1852                 cnt -= len;
1853 
1854                 if (host->part_buf_count == 8) {
1855                         mci_writeq(host, DATA(host->data_offset),
1856                                         host->part_buf);
1857                         host->part_buf_count = 0;
1858                 }
1859         }
1860 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1861         if (unlikely((unsigned long)buf & 0x7)) {
1862                 while (cnt >= 8) {
1863                         u64 aligned_buf[16];
1864                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
1865                         int items = len >> 3;
1866                         int i;
1867                         /* memcpy from input buffer into aligned buffer */
1868                         memcpy(aligned_buf, buf, len);
1869                         buf += len;
1870                         cnt -= len;
1871                         /* push data from aligned buffer into fifo */
1872                         for (i = 0; i < items; ++i)
1873                                 mci_writeq(host, DATA(host->data_offset),
1874                                                 aligned_buf[i]);
1875                 }
1876         } else
1877 #endif
1878         {
1879                 u64 *pdata = buf;
1880                 for (; cnt >= 8; cnt -= 8)
1881                         mci_writeq(host, DATA(host->data_offset), *pdata++);
1882                 buf = pdata;
1883         }
1884         /* put anything remaining in the part_buf */
1885         if (cnt) {
1886                 dw_mci_set_part_bytes(host, buf, cnt);
1887                 /* Push data if we have reached the expected data length */
1888                 if ((data->bytes_xfered + init_cnt) ==
1889                     (data->blksz * data->blocks))
1890                         mci_writeq(host, DATA(host->data_offset),
1891                                    host->part_buf);
1892         }
1893 }
1894 
1895 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1896 {
1897 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1898         if (unlikely((unsigned long)buf & 0x7)) {
1899                 while (cnt >= 8) {
1900                         /* pull data from fifo into aligned buffer */
1901                         u64 aligned_buf[16];
1902                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
1903                         int items = len >> 3;
1904                         int i;
1905                         for (i = 0; i < items; ++i)
1906                                 aligned_buf[i] = mci_readq(host,
1907                                                 DATA(host->data_offset));
1908                         /* memcpy from aligned buffer into output buffer */
1909                         memcpy(buf, aligned_buf, len);
1910                         buf += len;
1911                         cnt -= len;
1912                 }
1913         } else
1914 #endif
1915         {
1916                 u64 *pdata = buf;
1917                 for (; cnt >= 8; cnt -= 8)
1918                         *pdata++ = mci_readq(host, DATA(host->data_offset));
1919                 buf = pdata;
1920         }
1921         if (cnt) {
1922                 host->part_buf = mci_readq(host, DATA(host->data_offset));
1923                 dw_mci_pull_final_bytes(host, buf, cnt);
1924         }
1925 }
1926 
1927 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
1928 {
1929         int len;
1930 
1931         /* get remaining partial bytes */
1932         len = dw_mci_pull_part_bytes(host, buf, cnt);
1933         if (unlikely(len == cnt))
1934                 return;
1935         buf += len;
1936         cnt -= len;
1937 
1938         /* get the rest of the data */
1939         host->pull_data(host, buf, cnt);
1940 }
1941 
1942 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
1943 {
1944         struct sg_mapping_iter *sg_miter = &host->sg_miter;
1945         void *buf;
1946         unsigned int offset;
1947         struct mmc_data *data = host->data;
1948         int shift = host->data_shift;
1949         u32 status;
1950         unsigned int len;
1951         unsigned int remain, fcnt;
1952 
1953         do {
1954                 if (!sg_miter_next(sg_miter))
1955                         goto done;
1956 
1957                 host->sg = sg_miter->piter.sg;
1958                 buf = sg_miter->addr;
1959                 remain = sg_miter->length;
1960                 offset = 0;
1961 
1962                 do {
1963                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
1964                                         << shift) + host->part_buf_count;
1965                         len = min(remain, fcnt);
1966                         if (!len)
1967                                 break;
1968                         dw_mci_pull_data(host, (void *)(buf + offset), len);
1969                         data->bytes_xfered += len;
1970                         offset += len;
1971                         remain -= len;
1972                 } while (remain);
1973 
1974                 sg_miter->consumed = offset;
1975                 status = mci_readl(host, MINTSTS);
1976                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1977         /* if the RXDR is ready read again */
1978         } while ((status & SDMMC_INT_RXDR) ||
1979                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
1980 
1981         if (!remain) {
1982                 if (!sg_miter_next(sg_miter))
1983                         goto done;
1984                 sg_miter->consumed = 0;
1985         }
1986         sg_miter_stop(sg_miter);
1987         return;
1988 
1989 done:
1990         sg_miter_stop(sg_miter);
1991         host->sg = NULL;
1992         smp_wmb();
1993         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1994 }
1995 
1996 static void dw_mci_write_data_pio(struct dw_mci *host)
1997 {
1998         struct sg_mapping_iter *sg_miter = &host->sg_miter;
1999         void *buf;
2000         unsigned int offset;
2001         struct mmc_data *data = host->data;
2002         int shift = host->data_shift;
2003         u32 status;
2004         unsigned int len;
2005         unsigned int fifo_depth = host->fifo_depth;
2006         unsigned int remain, fcnt;
2007 
2008         do {
2009                 if (!sg_miter_next(sg_miter))
2010                         goto done;
2011 
2012                 host->sg = sg_miter->piter.sg;
2013                 buf = sg_miter->addr;
2014                 remain = sg_miter->length;
2015                 offset = 0;
2016 
2017                 do {
2018                         fcnt = ((fifo_depth -
2019                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2020                                         << shift) - host->part_buf_count;
2021                         len = min(remain, fcnt);
2022                         if (!len)
2023                                 break;
2024                         host->push_data(host, (void *)(buf + offset), len);
2025                         data->bytes_xfered += len;
2026                         offset += len;
2027                         remain -= len;
2028                 } while (remain);
2029 
2030                 sg_miter->consumed = offset;
2031                 status = mci_readl(host, MINTSTS);
2032                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2033         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2034 
2035         if (!remain) {
2036                 if (!sg_miter_next(sg_miter))
2037                         goto done;
2038                 sg_miter->consumed = 0;
2039         }
2040         sg_miter_stop(sg_miter);
2041         return;
2042 
2043 done:
2044         sg_miter_stop(sg_miter);
2045         host->sg = NULL;
2046         smp_wmb();
2047         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2048 }
2049 
2050 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2051 {
2052         if (!host->cmd_status)
2053                 host->cmd_status = status;
2054 
2055         smp_wmb();
2056 
2057         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2058         tasklet_schedule(&host->tasklet);
2059 }
2060 
2061 static void dw_mci_handle_cd(struct dw_mci *host)
2062 {
2063         int i;
2064 
2065         for (i = 0; i < host->num_slots; i++) {
2066                 struct dw_mci_slot *slot = host->slot[i];
2067 
2068                 if (!slot)
2069                         continue;
2070 
2071                 if (slot->mmc->ops->card_event)
2072                         slot->mmc->ops->card_event(slot->mmc);
2073                 mmc_detect_change(slot->mmc,
2074                         msecs_to_jiffies(host->pdata->detect_delay_ms));
2075         }
2076 }
2077 
2078 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2079 {
2080         struct dw_mci *host = dev_id;
2081         u32 pending;
2082         int i;
2083 
2084         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2085 
2086         /*
2087          * DTO fix - version 2.10a and below, and only if internal DMA
2088          * is configured.
2089          */
2090         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
2091                 if (!pending &&
2092                     ((mci_readl(host, STATUS) >> 17) & 0x1fff))
2093                         pending |= SDMMC_INT_DATA_OVER;
2094         }
2095 
2096         if (pending) {
2097                 /* Check volt switch first, since it can look like an error */
2098                 if ((host->state == STATE_SENDING_CMD11) &&
2099                     (pending & SDMMC_INT_VOLT_SWITCH)) {
2100                         mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2101                         pending &= ~SDMMC_INT_VOLT_SWITCH;
2102                         dw_mci_cmd_interrupt(host, pending);
2103                 }
2104 
2105                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2106                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2107                         host->cmd_status = pending;
2108                         smp_wmb();
2109                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2110                 }
2111 
2112                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2113                         /* if there is an error report DATA_ERROR */
2114                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2115                         host->data_status = pending;
2116                         smp_wmb();
2117                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
2118                         tasklet_schedule(&host->tasklet);
2119                 }
2120 
2121                 if (pending & SDMMC_INT_DATA_OVER) {
2122                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2123                         if (!host->data_status)
2124                                 host->data_status = pending;
2125                         smp_wmb();
2126                         if (host->dir_status == DW_MCI_RECV_STATUS) {
2127                                 if (host->sg != NULL)
2128                                         dw_mci_read_data_pio(host, true);
2129                         }
2130                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2131                         tasklet_schedule(&host->tasklet);
2132                 }
2133 
2134                 if (pending & SDMMC_INT_RXDR) {
2135                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2136                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2137                                 dw_mci_read_data_pio(host, false);
2138                 }
2139 
2140                 if (pending & SDMMC_INT_TXDR) {
2141                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2142                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2143                                 dw_mci_write_data_pio(host);
2144                 }
2145 
2146                 if (pending & SDMMC_INT_CMD_DONE) {
2147                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2148                         dw_mci_cmd_interrupt(host, pending);
2149                 }
2150 
2151                 if (pending & SDMMC_INT_CD) {
2152                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
2153                         dw_mci_handle_cd(host);
2154                 }
2155 
2156                 /* Handle SDIO Interrupts */
2157                 for (i = 0; i < host->num_slots; i++) {
2158                         struct dw_mci_slot *slot = host->slot[i];
2159                         if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2160                                 mci_writel(host, RINTSTS,
2161                                            SDMMC_INT_SDIO(slot->sdio_id));
2162                                 mmc_signal_sdio_irq(slot->mmc);
2163                         }
2164                 }
2165 
2166         }
2167 
2168 #ifdef CONFIG_MMC_DW_IDMAC
2169         /* Handle DMA interrupts */
2170         if (host->dma_64bit_address == 1) {
2171                 pending = mci_readl(host, IDSTS64);
2172                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2173                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2174                                                         SDMMC_IDMAC_INT_RI);
2175                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2176                         host->dma_ops->complete(host);
2177                 }
2178         } else {
2179                 pending = mci_readl(host, IDSTS);
2180                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2181                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2182                                                         SDMMC_IDMAC_INT_RI);
2183                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2184                         host->dma_ops->complete(host);
2185                 }
2186         }
2187 #endif
2188 
2189         return IRQ_HANDLED;
2190 }
2191 
2192 #ifdef CONFIG_OF
2193 /* given a slot id, find out the device node representing that slot */
2194 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
2195 {
2196         struct device_node *np;
2197         const __be32 *addr;
2198         int len;
2199 
2200         if (!dev || !dev->of_node)
2201                 return NULL;
2202 
2203         for_each_child_of_node(dev->of_node, np) {
2204                 addr = of_get_property(np, "reg", &len);
2205                 if (!addr || (len < sizeof(int)))
2206                         continue;
2207                 if (be32_to_cpup(addr) == slot)
2208                         return np;
2209         }
2210         return NULL;
2211 }
2212 
2213 static struct dw_mci_of_slot_quirks {
2214         char *quirk;
2215         int id;
2216 } of_slot_quirks[] = {
2217         {
2218                 .quirk  = "disable-wp",
2219                 .id     = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
2220         },
2221 };
2222 
2223 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
2224 {
2225         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
2226         int quirks = 0;
2227         int idx;
2228 
2229         /* get quirks */
2230         for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++)
2231                 if (of_get_property(np, of_slot_quirks[idx].quirk, NULL)) {
2232                         dev_warn(dev, "Slot quirk %s is deprecated\n",
2233                                         of_slot_quirks[idx].quirk);
2234                         quirks |= of_slot_quirks[idx].id;
2235                 }
2236 
2237         return quirks;
2238 }
2239 #else /* CONFIG_OF */
2240 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
2241 {
2242         return 0;
2243 }
2244 #endif /* CONFIG_OF */
2245 
2246 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2247 {
2248         struct mmc_host *mmc;
2249         struct dw_mci_slot *slot;
2250         const struct dw_mci_drv_data *drv_data = host->drv_data;
2251         int ctrl_id, ret;
2252         u32 freq[2];
2253 
2254         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2255         if (!mmc)
2256                 return -ENOMEM;
2257 
2258         slot = mmc_priv(mmc);
2259         slot->id = id;
2260         slot->sdio_id = host->sdio_id0 + id;
2261         slot->mmc = mmc;
2262         slot->host = host;
2263         host->slot[id] = slot;
2264 
2265         slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
2266 
2267         mmc->ops = &dw_mci_ops;
2268         if (of_property_read_u32_array(host->dev->of_node,
2269                                        "clock-freq-min-max", freq, 2)) {
2270                 mmc->f_min = DW_MCI_FREQ_MIN;
2271                 mmc->f_max = DW_MCI_FREQ_MAX;
2272         } else {
2273                 mmc->f_min = freq[0];
2274                 mmc->f_max = freq[1];
2275         }
2276 
2277         /*if there are external regulators, get them*/
2278         ret = mmc_regulator_get_supply(mmc);
2279         if (ret == -EPROBE_DEFER)
2280                 goto err_host_allocated;
2281 
2282         if (!mmc->ocr_avail)
2283                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2284 
2285         if (host->pdata->caps)
2286                 mmc->caps = host->pdata->caps;
2287 
2288         if (host->pdata->pm_caps)
2289                 mmc->pm_caps = host->pdata->pm_caps;
2290 
2291         if (host->dev->of_node) {
2292                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2293                 if (ctrl_id < 0)
2294                         ctrl_id = 0;
2295         } else {
2296                 ctrl_id = to_platform_device(host->dev)->id;
2297         }
2298         if (drv_data && drv_data->caps)
2299                 mmc->caps |= drv_data->caps[ctrl_id];
2300 
2301         if (host->pdata->caps2)
2302                 mmc->caps2 = host->pdata->caps2;
2303 
2304         ret = mmc_of_parse(mmc);
2305         if (ret)
2306                 goto err_host_allocated;
2307 
2308         if (host->pdata->blk_settings) {
2309                 mmc->max_segs = host->pdata->blk_settings->max_segs;
2310                 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
2311                 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
2312                 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
2313                 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
2314         } else {
2315                 /* Useful defaults if platform data is unset. */
2316 #ifdef CONFIG_MMC_DW_IDMAC
2317                 mmc->max_segs = host->ring_size;
2318                 mmc->max_blk_size = 65536;
2319                 mmc->max_seg_size = 0x1000;
2320                 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2321                 mmc->max_blk_count = mmc->max_req_size / 512;
2322 #else
2323                 mmc->max_segs = 64;
2324                 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
2325                 mmc->max_blk_count = 512;
2326                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2327                 mmc->max_seg_size = mmc->max_req_size;
2328 #endif /* CONFIG_MMC_DW_IDMAC */
2329         }
2330 
2331         if (dw_mci_get_cd(mmc))
2332                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2333         else
2334                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2335 
2336         ret = mmc_add_host(mmc);
2337         if (ret)
2338                 goto err_host_allocated;
2339 
2340 #if defined(CONFIG_DEBUG_FS)
2341         dw_mci_init_debugfs(slot);
2342 #endif
2343 
2344         return 0;
2345 
2346 err_host_allocated:
2347         mmc_free_host(mmc);
2348         return ret;
2349 }
2350 
2351 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2352 {
2353         /* Debugfs stuff is cleaned up by mmc core */
2354         mmc_remove_host(slot->mmc);
2355         slot->host->slot[id] = NULL;
2356         mmc_free_host(slot->mmc);
2357 }
2358 
2359 static void dw_mci_init_dma(struct dw_mci *host)
2360 {
2361         int addr_config;
2362         /* Check ADDR_CONFIG bit in HCON to find IDMAC address bus width */
2363         addr_config = (mci_readl(host, HCON) >> 27) & 0x01;
2364 
2365         if (addr_config == 1) {
2366                 /* host supports IDMAC in 64-bit address mode */
2367                 host->dma_64bit_address = 1;
2368                 dev_info(host->dev, "IDMAC supports 64-bit address mode.\n");
2369                 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2370                         dma_set_coherent_mask(host->dev, DMA_BIT_MASK(64));
2371         } else {
2372                 /* host supports IDMAC in 32-bit address mode */
2373                 host->dma_64bit_address = 0;
2374                 dev_info(host->dev, "IDMAC supports 32-bit address mode.\n");
2375         }
2376 
2377         /* Alloc memory for sg translation */
2378         host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
2379                                           &host->sg_dma, GFP_KERNEL);
2380         if (!host->sg_cpu) {
2381                 dev_err(host->dev, "%s: could not alloc DMA memory\n",
2382                         __func__);
2383                 goto no_dma;
2384         }
2385 
2386         /* Determine which DMA interface to use */
2387 #ifdef CONFIG_MMC_DW_IDMAC
2388         host->dma_ops = &dw_mci_idmac_ops;
2389         dev_info(host->dev, "Using internal DMA controller.\n");
2390 #endif
2391 
2392         if (!host->dma_ops)
2393                 goto no_dma;
2394 
2395         if (host->dma_ops->init && host->dma_ops->start &&
2396             host->dma_ops->stop && host->dma_ops->cleanup) {
2397                 if (host->dma_ops->init(host)) {
2398                         dev_err(host->dev, "%s: Unable to initialize "
2399                                 "DMA Controller.\n", __func__);
2400                         goto no_dma;
2401                 }
2402         } else {
2403                 dev_err(host->dev, "DMA initialization not found.\n");
2404                 goto no_dma;
2405         }
2406 
2407         host->use_dma = 1;
2408         return;
2409 
2410 no_dma:
2411         dev_info(host->dev, "Using PIO mode.\n");
2412         host->use_dma = 0;
2413         return;
2414 }
2415 
2416 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
2417 {
2418         unsigned long timeout = jiffies + msecs_to_jiffies(500);
2419         u32 ctrl;
2420 
2421         ctrl = mci_readl(host, CTRL);
2422         ctrl |= reset;
2423         mci_writel(host, CTRL, ctrl);
2424 
2425         /* wait till resets clear */
2426         do {
2427                 ctrl = mci_readl(host, CTRL);
2428                 if (!(ctrl & reset))
2429                         return true;
2430         } while (time_before(jiffies, timeout));
2431 
2432         dev_err(host->dev,
2433                 "Timeout resetting block (ctrl reset %#x)\n",
2434                 ctrl & reset);
2435 
2436         return false;
2437 }
2438 
2439 static bool dw_mci_reset(struct dw_mci *host)
2440 {
2441         u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2442         bool ret = false;
2443 
2444         /*
2445          * Reseting generates a block interrupt, hence setting
2446          * the scatter-gather pointer to NULL.
2447          */
2448         if (host->sg) {
2449                 sg_miter_stop(&host->sg_miter);
2450                 host->sg = NULL;
2451         }
2452 
2453         if (host->use_dma)
2454                 flags |= SDMMC_CTRL_DMA_RESET;
2455 
2456         if (dw_mci_ctrl_reset(host, flags)) {
2457                 /*
2458                  * In all cases we clear the RAWINTS register to clear any
2459                  * interrupts.
2460                  */
2461                 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2462 
2463                 /* if using dma we wait for dma_req to clear */
2464                 if (host->use_dma) {
2465                         unsigned long timeout = jiffies + msecs_to_jiffies(500);
2466                         u32 status;
2467                         do {
2468                                 status = mci_readl(host, STATUS);
2469                                 if (!(status & SDMMC_STATUS_DMA_REQ))
2470                                         break;
2471                                 cpu_relax();
2472                         } while (time_before(jiffies, timeout));
2473 
2474                         if (status & SDMMC_STATUS_DMA_REQ) {
2475                                 dev_err(host->dev,
2476                                         "%s: Timeout waiting for dma_req to "
2477                                         "clear during reset\n", __func__);
2478                                 goto ciu_out;
2479                         }
2480 
2481                         /* when using DMA next we reset the fifo again */
2482                         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2483                                 goto ciu_out;
2484                 }
2485         } else {
2486                 /* if the controller reset bit did clear, then set clock regs */
2487                 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
2488                         dev_err(host->dev, "%s: fifo/dma reset bits didn't "
2489                                 "clear but ciu was reset, doing clock update\n",
2490                                 __func__);
2491                         goto ciu_out;
2492                 }
2493         }
2494 
2495 #if IS_ENABLED(CONFIG_MMC_DW_IDMAC)
2496         /* It is also recommended that we reset and reprogram idmac */
2497         dw_mci_idmac_reset(host);
2498 #endif
2499 
2500         ret = true;
2501 
2502 ciu_out:
2503         /* After a CTRL reset we need to have CIU set clock registers  */
2504         mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2505 
2506         return ret;
2507 }
2508 
2509 #ifdef CONFIG_OF
2510 static struct dw_mci_of_quirks {
2511         char *quirk;
2512         int id;
2513 } of_quirks[] = {
2514         {
2515                 .quirk  = "broken-cd",
2516                 .id     = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
2517         }, {
2518                 .quirk  = "disable-wp",
2519                 .id     = DW_MCI_QUIRK_NO_WRITE_PROTECT,
2520         },
2521 };
2522 
2523 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2524 {
2525         struct dw_mci_board *pdata;
2526         struct device *dev = host->dev;
2527         struct device_node *np = dev->of_node;
2528         const struct dw_mci_drv_data *drv_data = host->drv_data;
2529         int idx, ret;
2530         u32 clock_frequency;
2531 
2532         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2533         if (!pdata)
2534                 return ERR_PTR(-ENOMEM);
2535 
2536         /* find out number of slots supported */
2537         if (of_property_read_u32(dev->of_node, "num-slots",
2538                                 &pdata->num_slots)) {
2539                 dev_info(dev, "num-slots property not found, "
2540                                 "assuming 1 slot is available\n");
2541                 pdata->num_slots = 1;
2542         }
2543 
2544         /* get quirks */
2545         for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
2546                 if (of_get_property(np, of_quirks[idx].quirk, NULL))
2547                         pdata->quirks |= of_quirks[idx].id;
2548 
2549         if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2550                 dev_info(dev, "fifo-depth property not found, using "
2551                                 "value of FIFOTH register as default\n");
2552 
2553         of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2554 
2555         if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2556                 pdata->bus_hz = clock_frequency;
2557 
2558         if (drv_data && drv_data->parse_dt) {
2559                 ret = drv_data->parse_dt(host);
2560                 if (ret)
2561                         return ERR_PTR(ret);
2562         }
2563 
2564         if (of_find_property(np, "supports-highspeed", NULL))
2565                 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2566 
2567         return pdata;
2568 }
2569 
2570 #else /* CONFIG_OF */
2571 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2572 {
2573         return ERR_PTR(-EINVAL);
2574 }
2575 #endif /* CONFIG_OF */
2576 
2577 int dw_mci_probe(struct dw_mci *host)
2578 {
2579         const struct dw_mci_drv_data *drv_data = host->drv_data;
2580         int width, i, ret = 0;
2581         u32 fifo_size;
2582         int init_slots = 0;
2583 
2584         if (!host->pdata) {
2585                 host->pdata = dw_mci_parse_dt(host);
2586                 if (IS_ERR(host->pdata)) {
2587                         dev_err(host->dev, "platform data not available\n");
2588                         return -EINVAL;
2589                 }
2590         }
2591 
2592         if (host->pdata->num_slots > 1) {
2593                 dev_err(host->dev,
2594                         "Platform data must supply num_slots.\n");
2595                 return -ENODEV;
2596         }
2597 
2598         host->biu_clk = devm_clk_get(host->dev, "biu");
2599         if (IS_ERR(host->biu_clk)) {
2600                 dev_dbg(host->dev, "biu clock not available\n");
2601         } else {
2602                 ret = clk_prepare_enable(host->biu_clk);
2603                 if (ret) {
2604                         dev_err(host->dev, "failed to enable biu clock\n");
2605                         return ret;
2606                 }
2607         }
2608 
2609         host->ciu_clk = devm_clk_get(host->dev, "ciu");
2610         if (IS_ERR(host->ciu_clk)) {
2611                 dev_dbg(host->dev, "ciu clock not available\n");
2612                 host->bus_hz = host->pdata->bus_hz;
2613         } else {
2614                 ret = clk_prepare_enable(host->ciu_clk);
2615                 if (ret) {
2616                         dev_err(host->dev, "failed to enable ciu clock\n");
2617                         goto err_clk_biu;
2618                 }
2619 
2620                 if (host->pdata->bus_hz) {
2621                         ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
2622                         if (ret)
2623                                 dev_warn(host->dev,
2624                                          "Unable to set bus rate to %uHz\n",
2625                                          host->pdata->bus_hz);
2626                 }
2627                 host->bus_hz = clk_get_rate(host->ciu_clk);
2628         }
2629 
2630         if (!host->bus_hz) {
2631                 dev_err(host->dev,
2632                         "Platform data must supply bus speed\n");
2633                 ret = -ENODEV;
2634                 goto err_clk_ciu;
2635         }
2636 
2637         if (drv_data && drv_data->init) {
2638                 ret = drv_data->init(host);
2639                 if (ret) {
2640                         dev_err(host->dev,
2641                                 "implementation specific init failed\n");
2642                         goto err_clk_ciu;
2643                 }
2644         }
2645 
2646         if (drv_data && drv_data->setup_clock) {
2647                 ret = drv_data->setup_clock(host);
2648                 if (ret) {
2649                         dev_err(host->dev,
2650                                 "implementation specific clock setup failed\n");
2651                         goto err_clk_ciu;
2652                 }
2653         }
2654 
2655         host->quirks = host->pdata->quirks;
2656 
2657         spin_lock_init(&host->lock);
2658         spin_lock_init(&host->irq_lock);
2659         INIT_LIST_HEAD(&host->queue);
2660 
2661         /*
2662          * Get the host data width - this assumes that HCON has been set with
2663          * the correct values.
2664          */
2665         i = (mci_readl(host, HCON) >> 7) & 0x7;
2666         if (!i) {
2667                 host->push_data = dw_mci_push_data16;
2668                 host->pull_data = dw_mci_pull_data16;
2669                 width = 16;
2670                 host->data_shift = 1;
2671         } else if (i == 2) {
2672                 host->push_data = dw_mci_push_data64;
2673                 host->pull_data = dw_mci_pull_data64;
2674                 width = 64;
2675                 host->data_shift = 3;
2676         } else {
2677                 /* Check for a reserved value, and warn if it is */
2678                 WARN((i != 1),
2679                      "HCON reports a reserved host data width!\n"
2680                      "Defaulting to 32-bit access.\n");
2681                 host->push_data = dw_mci_push_data32;
2682                 host->pull_data = dw_mci_pull_data32;
2683                 width = 32;
2684                 host->data_shift = 2;
2685         }
2686 
2687         /* Reset all blocks */
2688         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS))
2689                 return -ENODEV;
2690 
2691         host->dma_ops = host->pdata->dma_ops;
2692         dw_mci_init_dma(host);
2693 
2694         /* Clear the interrupts for the host controller */
2695         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2696         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2697 
2698         /* Put in max timeout */
2699         mci_writel(host, TMOUT, 0xFFFFFFFF);
2700 
2701         /*
2702          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
2703          *                          Tx Mark = fifo_size / 2 DMA Size = 8
2704          */
2705         if (!host->pdata->fifo_depth) {
2706                 /*
2707                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
2708                  * have been overwritten by the bootloader, just like we're
2709                  * about to do, so if you know the value for your hardware, you
2710                  * should put it in the platform data.
2711                  */
2712                 fifo_size = mci_readl(host, FIFOTH);
2713                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
2714         } else {
2715                 fifo_size = host->pdata->fifo_depth;
2716         }
2717         host->fifo_depth = fifo_size;
2718         host->fifoth_val =
2719                 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
2720         mci_writel(host, FIFOTH, host->fifoth_val);
2721 
2722         /* disable clock to CIU */
2723         mci_writel(host, CLKENA, 0);
2724         mci_writel(host, CLKSRC, 0);
2725 
2726         /*
2727          * In 2.40a spec, Data offset is changed.
2728          * Need to check the version-id and set data-offset for DATA register.
2729          */
2730         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
2731         dev_info(host->dev, "Version ID is %04x\n", host->verid);
2732 
2733         if (host->verid < DW_MMC_240A)
2734                 host->data_offset = DATA_OFFSET;
2735         else
2736                 host->data_offset = DATA_240A_OFFSET;
2737 
2738         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
2739         ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
2740                                host->irq_flags, "dw-mci", host);
2741         if (ret)
2742                 goto err_dmaunmap;
2743 
2744         if (host->pdata->num_slots)
2745                 host->num_slots = host->pdata->num_slots;
2746         else
2747                 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
2748 
2749         /*
2750          * Enable interrupts for command done, data over, data empty, card det,
2751          * receive ready and error such as transmit, receive timeout, crc error
2752          */
2753         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2754         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2755                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2756                    DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2757         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
2758 
2759         dev_info(host->dev, "DW MMC controller at irq %d, "
2760                  "%d bit host data width, "
2761                  "%u deep fifo\n",
2762                  host->irq, width, fifo_size);
2763 
2764         /* We need at least one slot to succeed */
2765         for (i = 0; i < host->num_slots; i++) {
2766                 ret = dw_mci_init_slot(host, i);
2767                 if (ret)
2768                         dev_dbg(host->dev, "slot %d init failed\n", i);
2769                 else
2770                         init_slots++;
2771         }
2772 
2773         if (init_slots) {
2774                 dev_info(host->dev, "%d slots initialized\n", init_slots);
2775         } else {
2776                 dev_dbg(host->dev, "attempted to initialize %d slots, "
2777                                         "but failed on all\n", host->num_slots);
2778                 goto err_dmaunmap;
2779         }
2780 
2781         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
2782                 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
2783 
2784         return 0;
2785 
2786 err_dmaunmap:
2787         if (host->use_dma && host->dma_ops->exit)
2788                 host->dma_ops->exit(host);
2789 
2790 err_clk_ciu:
2791         if (!IS_ERR(host->ciu_clk))
2792                 clk_disable_unprepare(host->ciu_clk);
2793 
2794 err_clk_biu:
2795         if (!IS_ERR(host->biu_clk))
2796                 clk_disable_unprepare(host->biu_clk);
2797 
2798         return ret;
2799 }
2800 EXPORT_SYMBOL(dw_mci_probe);
2801 
2802 void dw_mci_remove(struct dw_mci *host)
2803 {
2804         int i;
2805 
2806         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2807         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2808 
2809         for (i = 0; i < host->num_slots; i++) {
2810                 dev_dbg(host->dev, "remove slot %d\n", i);
2811                 if (host->slot[i])
2812                         dw_mci_cleanup_slot(host->slot[i], i);
2813         }
2814 
2815         /* disable clock to CIU */
2816         mci_writel(host, CLKENA, 0);
2817         mci_writel(host, CLKSRC, 0);
2818 
2819         if (host->use_dma && host->dma_ops->exit)
2820                 host->dma_ops->exit(host);
2821 
2822         if (!IS_ERR(host->ciu_clk))
2823                 clk_disable_unprepare(host->ciu_clk);
2824 
2825         if (!IS_ERR(host->biu_clk))
2826                 clk_disable_unprepare(host->biu_clk);
2827 }
2828 EXPORT_SYMBOL(dw_mci_remove);
2829 
2830 
2831 
2832 #ifdef CONFIG_PM_SLEEP
2833 /*
2834  * TODO: we should probably disable the clock to the card in the suspend path.
2835  */
2836 int dw_mci_suspend(struct dw_mci *host)
2837 {
2838         return 0;
2839 }
2840 EXPORT_SYMBOL(dw_mci_suspend);
2841 
2842 int dw_mci_resume(struct dw_mci *host)
2843 {
2844         int i, ret;
2845 
2846         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
2847                 ret = -ENODEV;
2848                 return ret;
2849         }
2850 
2851         if (host->use_dma && host->dma_ops->init)
2852                 host->dma_ops->init(host);
2853 
2854         /*
2855          * Restore the initial value at FIFOTH register
2856          * And Invalidate the prev_blksz with zero
2857          */
2858         mci_writel(host, FIFOTH, host->fifoth_val);
2859         host->prev_blksz = 0;
2860 
2861         /* Put in max timeout */
2862         mci_writel(host, TMOUT, 0xFFFFFFFF);
2863 
2864         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2865         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2866                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2867                    DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2868         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2869 
2870         for (i = 0; i < host->num_slots; i++) {
2871                 struct dw_mci_slot *slot = host->slot[i];
2872                 if (!slot)
2873                         continue;
2874                 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
2875                         dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
2876                         dw_mci_setup_bus(slot, true);
2877                 }
2878         }
2879         return 0;
2880 }
2881 EXPORT_SYMBOL(dw_mci_resume);
2882 #endif /* CONFIG_PM_SLEEP */
2883 
2884 static int __init dw_mci_init(void)
2885 {
2886         pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
2887         return 0;
2888 }
2889 
2890 static void __exit dw_mci_exit(void)
2891 {
2892 }
2893 
2894 module_init(dw_mci_init);
2895 module_exit(dw_mci_exit);
2896 
2897 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
2898 MODULE_AUTHOR("NXP Semiconductor VietNam");
2899 MODULE_AUTHOR("Imagination Technologies Ltd");
2900 MODULE_LICENSE("GPL v2");
2901 

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