Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/mmc/host/au1xmmc.c

  1 /*
  2  * linux/drivers/mmc/host/au1xmmc.c - AU1XX0 MMC driver
  3  *
  4  *  Copyright (c) 2005, Advanced Micro Devices, Inc.
  5  *
  6  *  Developed with help from the 2.4.30 MMC AU1XXX controller including
  7  *  the following copyright notices:
  8  *     Copyright (c) 2003-2004 Embedded Edge, LLC.
  9  *     Portions Copyright (C) 2002 Embedix, Inc
 10  *     Copyright 2002 Hewlett-Packard Company
 11 
 12  *  2.6 version of this driver inspired by:
 13  *     (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
 14  *     All Rights Reserved.
 15  *     (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
 16  *     All Rights Reserved.
 17  *
 18 
 19  * This program is free software; you can redistribute it and/or modify
 20  * it under the terms of the GNU General Public License version 2 as
 21  * published by the Free Software Foundation.
 22  */
 23 
 24 /* Why don't we use the SD controllers' carddetect feature?
 25  *
 26  * From the AU1100 MMC application guide:
 27  * If the Au1100-based design is intended to support both MultiMediaCards
 28  * and 1- or 4-data bit SecureDigital cards, then the solution is to
 29  * connect a weak (560KOhm) pull-up resistor to connector pin 1.
 30  * In doing so, a MMC card never enters SPI-mode communications,
 31  * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
 32  * (the low to high transition will not occur).
 33  */
 34 
 35 #include <linux/clk.h>
 36 #include <linux/module.h>
 37 #include <linux/init.h>
 38 #include <linux/platform_device.h>
 39 #include <linux/mm.h>
 40 #include <linux/interrupt.h>
 41 #include <linux/dma-mapping.h>
 42 #include <linux/scatterlist.h>
 43 #include <linux/leds.h>
 44 #include <linux/mmc/host.h>
 45 #include <linux/slab.h>
 46 
 47 #include <asm/io.h>
 48 #include <asm/mach-au1x00/au1000.h>
 49 #include <asm/mach-au1x00/au1xxx_dbdma.h>
 50 #include <asm/mach-au1x00/au1100_mmc.h>
 51 
 52 #define DRIVER_NAME "au1xxx-mmc"
 53 
 54 /* Set this to enable special debugging macros */
 55 /* #define DEBUG */
 56 
 57 #ifdef DEBUG
 58 #define DBG(fmt, idx, args...)  \
 59         pr_debug("au1xmmc(%d): DEBUG: " fmt, idx, ##args)
 60 #else
 61 #define DBG(fmt, idx, args...) do {} while (0)
 62 #endif
 63 
 64 /* Hardware definitions */
 65 #define AU1XMMC_DESCRIPTOR_COUNT 1
 66 
 67 /* max DMA seg size: 64KB on Au1100, 4MB on Au1200 */
 68 #define AU1100_MMC_DESCRIPTOR_SIZE 0x0000ffff
 69 #define AU1200_MMC_DESCRIPTOR_SIZE 0x003fffff
 70 
 71 #define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \
 72                      MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \
 73                      MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36)
 74 
 75 /* This gives us a hard value for the stop command that we can write directly
 76  * to the command register.
 77  */
 78 #define STOP_CMD        \
 79         (SD_CMD_RT_1B | SD_CMD_CT_7 | (0xC << SD_CMD_CI_SHIFT) | SD_CMD_GO)
 80 
 81 /* This is the set of interrupts that we configure by default. */
 82 #define AU1XMMC_INTERRUPTS                              \
 83         (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_RAT |  \
 84          SD_CONFIG_CR | SD_CONFIG_I)
 85 
 86 /* The poll event (looking for insert/remove events runs twice a second. */
 87 #define AU1XMMC_DETECT_TIMEOUT (HZ/2)
 88 
 89 struct au1xmmc_host {
 90         struct mmc_host *mmc;
 91         struct mmc_request *mrq;
 92 
 93         u32 flags;
 94         void __iomem *iobase;
 95         u32 clock;
 96         u32 bus_width;
 97         u32 power_mode;
 98 
 99         int status;
100 
101         struct {
102                 int len;
103                 int dir;
104         } dma;
105 
106         struct {
107                 int index;
108                 int offset;
109                 int len;
110         } pio;
111 
112         u32 tx_chan;
113         u32 rx_chan;
114 
115         int irq;
116 
117         struct tasklet_struct finish_task;
118         struct tasklet_struct data_task;
119         struct au1xmmc_platform_data *platdata;
120         struct platform_device *pdev;
121         struct resource *ioarea;
122         struct clk *clk;
123 };
124 
125 /* Status flags used by the host structure */
126 #define HOST_F_XMIT     0x0001
127 #define HOST_F_RECV     0x0002
128 #define HOST_F_DMA      0x0010
129 #define HOST_F_DBDMA    0x0020
130 #define HOST_F_ACTIVE   0x0100
131 #define HOST_F_STOP     0x1000
132 
133 #define HOST_S_IDLE     0x0001
134 #define HOST_S_CMD      0x0002
135 #define HOST_S_DATA     0x0003
136 #define HOST_S_STOP     0x0004
137 
138 /* Easy access macros */
139 #define HOST_STATUS(h)  ((h)->iobase + SD_STATUS)
140 #define HOST_CONFIG(h)  ((h)->iobase + SD_CONFIG)
141 #define HOST_ENABLE(h)  ((h)->iobase + SD_ENABLE)
142 #define HOST_TXPORT(h)  ((h)->iobase + SD_TXPORT)
143 #define HOST_RXPORT(h)  ((h)->iobase + SD_RXPORT)
144 #define HOST_CMDARG(h)  ((h)->iobase + SD_CMDARG)
145 #define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE)
146 #define HOST_CMD(h)     ((h)->iobase + SD_CMD)
147 #define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2)
148 #define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT)
149 #define HOST_DEBUG(h)   ((h)->iobase + SD_DEBUG)
150 
151 #define DMA_CHANNEL(h)  \
152         (((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan)
153 
154 static inline int has_dbdma(void)
155 {
156         switch (alchemy_get_cputype()) {
157         case ALCHEMY_CPU_AU1200:
158         case ALCHEMY_CPU_AU1300:
159                 return 1;
160         default:
161                 return 0;
162         }
163 }
164 
165 static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
166 {
167         u32 val = __raw_readl(HOST_CONFIG(host));
168         val |= mask;
169         __raw_writel(val, HOST_CONFIG(host));
170         wmb(); /* drain writebuffer */
171 }
172 
173 static inline void FLUSH_FIFO(struct au1xmmc_host *host)
174 {
175         u32 val = __raw_readl(HOST_CONFIG2(host));
176 
177         __raw_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
178         wmb(); /* drain writebuffer */
179         mdelay(1);
180 
181         /* SEND_STOP will turn off clock control - this re-enables it */
182         val &= ~SD_CONFIG2_DF;
183 
184         __raw_writel(val, HOST_CONFIG2(host));
185         wmb(); /* drain writebuffer */
186 }
187 
188 static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
189 {
190         u32 val = __raw_readl(HOST_CONFIG(host));
191         val &= ~mask;
192         __raw_writel(val, HOST_CONFIG(host));
193         wmb(); /* drain writebuffer */
194 }
195 
196 static inline void SEND_STOP(struct au1xmmc_host *host)
197 {
198         u32 config2;
199 
200         WARN_ON(host->status != HOST_S_DATA);
201         host->status = HOST_S_STOP;
202 
203         config2 = __raw_readl(HOST_CONFIG2(host));
204         __raw_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host));
205         wmb(); /* drain writebuffer */
206 
207         /* Send the stop command */
208         __raw_writel(STOP_CMD, HOST_CMD(host));
209         wmb(); /* drain writebuffer */
210 }
211 
212 static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
213 {
214         if (host->platdata && host->platdata->set_power)
215                 host->platdata->set_power(host->mmc, state);
216 }
217 
218 static int au1xmmc_card_inserted(struct mmc_host *mmc)
219 {
220         struct au1xmmc_host *host = mmc_priv(mmc);
221 
222         if (host->platdata && host->platdata->card_inserted)
223                 return !!host->platdata->card_inserted(host->mmc);
224 
225         return -ENOSYS;
226 }
227 
228 static int au1xmmc_card_readonly(struct mmc_host *mmc)
229 {
230         struct au1xmmc_host *host = mmc_priv(mmc);
231 
232         if (host->platdata && host->platdata->card_readonly)
233                 return !!host->platdata->card_readonly(mmc);
234 
235         return -ENOSYS;
236 }
237 
238 static void au1xmmc_finish_request(struct au1xmmc_host *host)
239 {
240         struct mmc_request *mrq = host->mrq;
241 
242         host->mrq = NULL;
243         host->flags &= HOST_F_ACTIVE | HOST_F_DMA;
244 
245         host->dma.len = 0;
246         host->dma.dir = 0;
247 
248         host->pio.index  = 0;
249         host->pio.offset = 0;
250         host->pio.len = 0;
251 
252         host->status = HOST_S_IDLE;
253 
254         mmc_request_done(host->mmc, mrq);
255 }
256 
257 static void au1xmmc_tasklet_finish(unsigned long param)
258 {
259         struct au1xmmc_host *host = (struct au1xmmc_host *) param;
260         au1xmmc_finish_request(host);
261 }
262 
263 static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
264                                 struct mmc_command *cmd, struct mmc_data *data)
265 {
266         u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
267 
268         switch (mmc_resp_type(cmd)) {
269         case MMC_RSP_NONE:
270                 break;
271         case MMC_RSP_R1:
272                 mmccmd |= SD_CMD_RT_1;
273                 break;
274         case MMC_RSP_R1B:
275                 mmccmd |= SD_CMD_RT_1B;
276                 break;
277         case MMC_RSP_R2:
278                 mmccmd |= SD_CMD_RT_2;
279                 break;
280         case MMC_RSP_R3:
281                 mmccmd |= SD_CMD_RT_3;
282                 break;
283         default:
284                 pr_info("au1xmmc: unhandled response type %02x\n",
285                         mmc_resp_type(cmd));
286                 return -EINVAL;
287         }
288 
289         if (data) {
290                 if (data->flags & MMC_DATA_READ) {
291                         if (data->blocks > 1)
292                                 mmccmd |= SD_CMD_CT_4;
293                         else
294                                 mmccmd |= SD_CMD_CT_2;
295                 } else if (data->flags & MMC_DATA_WRITE) {
296                         if (data->blocks > 1)
297                                 mmccmd |= SD_CMD_CT_3;
298                         else
299                                 mmccmd |= SD_CMD_CT_1;
300                 }
301         }
302 
303         __raw_writel(cmd->arg, HOST_CMDARG(host));
304         wmb(); /* drain writebuffer */
305 
306         if (wait)
307                 IRQ_OFF(host, SD_CONFIG_CR);
308 
309         __raw_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
310         wmb(); /* drain writebuffer */
311 
312         /* Wait for the command to go on the line */
313         while (__raw_readl(HOST_CMD(host)) & SD_CMD_GO)
314                 /* nop */;
315 
316         /* Wait for the command to come back */
317         if (wait) {
318                 u32 status = __raw_readl(HOST_STATUS(host));
319 
320                 while (!(status & SD_STATUS_CR))
321                         status = __raw_readl(HOST_STATUS(host));
322 
323                 /* Clear the CR status */
324                 __raw_writel(SD_STATUS_CR, HOST_STATUS(host));
325 
326                 IRQ_ON(host, SD_CONFIG_CR);
327         }
328 
329         return 0;
330 }
331 
332 static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
333 {
334         struct mmc_request *mrq = host->mrq;
335         struct mmc_data *data;
336         u32 crc;
337 
338         WARN_ON((host->status != HOST_S_DATA) && (host->status != HOST_S_STOP));
339 
340         if (host->mrq == NULL)
341                 return;
342 
343         data = mrq->cmd->data;
344 
345         if (status == 0)
346                 status = __raw_readl(HOST_STATUS(host));
347 
348         /* The transaction is really over when the SD_STATUS_DB bit is clear */
349         while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
350                 status = __raw_readl(HOST_STATUS(host));
351 
352         data->error = 0;
353         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
354 
355         /* Process any errors */
356         crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
357         if (host->flags & HOST_F_XMIT)
358                 crc |= ((status & 0x07) == 0x02) ? 0 : 1;
359 
360         if (crc)
361                 data->error = -EILSEQ;
362 
363         /* Clear the CRC bits */
364         __raw_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
365 
366         data->bytes_xfered = 0;
367 
368         if (!data->error) {
369                 if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) {
370                         u32 chan = DMA_CHANNEL(host);
371 
372                         chan_tab_t *c = *((chan_tab_t **)chan);
373                         au1x_dma_chan_t *cp = c->chan_ptr;
374                         data->bytes_xfered = cp->ddma_bytecnt;
375                 } else
376                         data->bytes_xfered =
377                                 (data->blocks * data->blksz) - host->pio.len;
378         }
379 
380         au1xmmc_finish_request(host);
381 }
382 
383 static void au1xmmc_tasklet_data(unsigned long param)
384 {
385         struct au1xmmc_host *host = (struct au1xmmc_host *)param;
386 
387         u32 status = __raw_readl(HOST_STATUS(host));
388         au1xmmc_data_complete(host, status);
389 }
390 
391 #define AU1XMMC_MAX_TRANSFER 8
392 
393 static void au1xmmc_send_pio(struct au1xmmc_host *host)
394 {
395         struct mmc_data *data;
396         int sg_len, max, count;
397         unsigned char *sg_ptr, val;
398         u32 status;
399         struct scatterlist *sg;
400 
401         data = host->mrq->data;
402 
403         if (!(host->flags & HOST_F_XMIT))
404                 return;
405 
406         /* This is the pointer to the data buffer */
407         sg = &data->sg[host->pio.index];
408         sg_ptr = sg_virt(sg) + host->pio.offset;
409 
410         /* This is the space left inside the buffer */
411         sg_len = data->sg[host->pio.index].length - host->pio.offset;
412 
413         /* Check if we need less than the size of the sg_buffer */
414         max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
415         if (max > AU1XMMC_MAX_TRANSFER)
416                 max = AU1XMMC_MAX_TRANSFER;
417 
418         for (count = 0; count < max; count++) {
419                 status = __raw_readl(HOST_STATUS(host));
420 
421                 if (!(status & SD_STATUS_TH))
422                         break;
423 
424                 val = *sg_ptr++;
425 
426                 __raw_writel((unsigned long)val, HOST_TXPORT(host));
427                 wmb(); /* drain writebuffer */
428         }
429 
430         host->pio.len -= count;
431         host->pio.offset += count;
432 
433         if (count == sg_len) {
434                 host->pio.index++;
435                 host->pio.offset = 0;
436         }
437 
438         if (host->pio.len == 0) {
439                 IRQ_OFF(host, SD_CONFIG_TH);
440 
441                 if (host->flags & HOST_F_STOP)
442                         SEND_STOP(host);
443 
444                 tasklet_schedule(&host->data_task);
445         }
446 }
447 
448 static void au1xmmc_receive_pio(struct au1xmmc_host *host)
449 {
450         struct mmc_data *data;
451         int max, count, sg_len = 0;
452         unsigned char *sg_ptr = NULL;
453         u32 status, val;
454         struct scatterlist *sg;
455 
456         data = host->mrq->data;
457 
458         if (!(host->flags & HOST_F_RECV))
459                 return;
460 
461         max = host->pio.len;
462 
463         if (host->pio.index < host->dma.len) {
464                 sg = &data->sg[host->pio.index];
465                 sg_ptr = sg_virt(sg) + host->pio.offset;
466 
467                 /* This is the space left inside the buffer */
468                 sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
469 
470                 /* Check if we need less than the size of the sg_buffer */
471                 if (sg_len < max)
472                         max = sg_len;
473         }
474 
475         if (max > AU1XMMC_MAX_TRANSFER)
476                 max = AU1XMMC_MAX_TRANSFER;
477 
478         for (count = 0; count < max; count++) {
479                 status = __raw_readl(HOST_STATUS(host));
480 
481                 if (!(status & SD_STATUS_NE))
482                         break;
483 
484                 if (status & SD_STATUS_RC) {
485                         DBG("RX CRC Error [%d + %d].\n", host->pdev->id,
486                                         host->pio.len, count);
487                         break;
488                 }
489 
490                 if (status & SD_STATUS_RO) {
491                         DBG("RX Overrun [%d + %d]\n", host->pdev->id,
492                                         host->pio.len, count);
493                         break;
494                 }
495                 else if (status & SD_STATUS_RU) {
496                         DBG("RX Underrun [%d + %d]\n", host->pdev->id,
497                                         host->pio.len,  count);
498                         break;
499                 }
500 
501                 val = __raw_readl(HOST_RXPORT(host));
502 
503                 if (sg_ptr)
504                         *sg_ptr++ = (unsigned char)(val & 0xFF);
505         }
506 
507         host->pio.len -= count;
508         host->pio.offset += count;
509 
510         if (sg_len && count == sg_len) {
511                 host->pio.index++;
512                 host->pio.offset = 0;
513         }
514 
515         if (host->pio.len == 0) {
516                 /* IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); */
517                 IRQ_OFF(host, SD_CONFIG_NE);
518 
519                 if (host->flags & HOST_F_STOP)
520                         SEND_STOP(host);
521 
522                 tasklet_schedule(&host->data_task);
523         }
524 }
525 
526 /* This is called when a command has been completed - grab the response
527  * and check for errors.  Then start the data transfer if it is indicated.
528  */
529 static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
530 {
531         struct mmc_request *mrq = host->mrq;
532         struct mmc_command *cmd;
533         u32 r[4];
534         int i, trans;
535 
536         if (!host->mrq)
537                 return;
538 
539         cmd = mrq->cmd;
540         cmd->error = 0;
541 
542         if (cmd->flags & MMC_RSP_PRESENT) {
543                 if (cmd->flags & MMC_RSP_136) {
544                         r[0] = __raw_readl(host->iobase + SD_RESP3);
545                         r[1] = __raw_readl(host->iobase + SD_RESP2);
546                         r[2] = __raw_readl(host->iobase + SD_RESP1);
547                         r[3] = __raw_readl(host->iobase + SD_RESP0);
548 
549                         /* The CRC is omitted from the response, so really
550                          * we only got 120 bytes, but the engine expects
551                          * 128 bits, so we have to shift things up.
552                          */
553                         for (i = 0; i < 4; i++) {
554                                 cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
555                                 if (i != 3)
556                                         cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
557                         }
558                 } else {
559                         /* Techincally, we should be getting all 48 bits of
560                          * the response (SD_RESP1 + SD_RESP2), but because
561                          * our response omits the CRC, our data ends up
562                          * being shifted 8 bits to the right.  In this case,
563                          * that means that the OSR data starts at bit 31,
564                          * so we can just read RESP0 and return that.
565                          */
566                         cmd->resp[0] = __raw_readl(host->iobase + SD_RESP0);
567                 }
568         }
569 
570         /* Figure out errors */
571         if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
572                 cmd->error = -EILSEQ;
573 
574         trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
575 
576         if (!trans || cmd->error) {
577                 IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF);
578                 tasklet_schedule(&host->finish_task);
579                 return;
580         }
581 
582         host->status = HOST_S_DATA;
583 
584         if ((host->flags & (HOST_F_DMA | HOST_F_DBDMA))) {
585                 u32 channel = DMA_CHANNEL(host);
586 
587                 /* Start the DBDMA as soon as the buffer gets something in it */
588 
589                 if (host->flags & HOST_F_RECV) {
590                         u32 mask = SD_STATUS_DB | SD_STATUS_NE;
591 
592                         while((status & mask) != mask)
593                                 status = __raw_readl(HOST_STATUS(host));
594                 }
595 
596                 au1xxx_dbdma_start(channel);
597         }
598 }
599 
600 static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
601 {
602         unsigned int pbus = clk_get_rate(host->clk);
603         unsigned int divisor = ((pbus / rate) / 2) - 1;
604         u32 config;
605 
606         config = __raw_readl(HOST_CONFIG(host));
607 
608         config &= ~(SD_CONFIG_DIV);
609         config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
610 
611         __raw_writel(config, HOST_CONFIG(host));
612         wmb(); /* drain writebuffer */
613 }
614 
615 static int au1xmmc_prepare_data(struct au1xmmc_host *host,
616                                 struct mmc_data *data)
617 {
618         int datalen = data->blocks * data->blksz;
619 
620         if (data->flags & MMC_DATA_READ)
621                 host->flags |= HOST_F_RECV;
622         else
623                 host->flags |= HOST_F_XMIT;
624 
625         if (host->mrq->stop)
626                 host->flags |= HOST_F_STOP;
627 
628         host->dma.dir = DMA_BIDIRECTIONAL;
629 
630         host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
631                                    data->sg_len, host->dma.dir);
632 
633         if (host->dma.len == 0)
634                 return -ETIMEDOUT;
635 
636         __raw_writel(data->blksz - 1, HOST_BLKSIZE(host));
637 
638         if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) {
639                 int i;
640                 u32 channel = DMA_CHANNEL(host);
641 
642                 au1xxx_dbdma_stop(channel);
643 
644                 for (i = 0; i < host->dma.len; i++) {
645                         u32 ret = 0, flags = DDMA_FLAGS_NOIE;
646                         struct scatterlist *sg = &data->sg[i];
647                         int sg_len = sg->length;
648 
649                         int len = (datalen > sg_len) ? sg_len : datalen;
650 
651                         if (i == host->dma.len - 1)
652                                 flags = DDMA_FLAGS_IE;
653 
654                         if (host->flags & HOST_F_XMIT) {
655                                 ret = au1xxx_dbdma_put_source(channel,
656                                         sg_phys(sg), len, flags);
657                         } else {
658                                 ret = au1xxx_dbdma_put_dest(channel,
659                                         sg_phys(sg), len, flags);
660                         }
661 
662                         if (!ret)
663                                 goto dataerr;
664 
665                         datalen -= len;
666                 }
667         } else {
668                 host->pio.index = 0;
669                 host->pio.offset = 0;
670                 host->pio.len = datalen;
671 
672                 if (host->flags & HOST_F_XMIT)
673                         IRQ_ON(host, SD_CONFIG_TH);
674                 else
675                         IRQ_ON(host, SD_CONFIG_NE);
676                         /* IRQ_ON(host, SD_CONFIG_RA | SD_CONFIG_RF); */
677         }
678 
679         return 0;
680 
681 dataerr:
682         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
683                         host->dma.dir);
684         return -ETIMEDOUT;
685 }
686 
687 /* This actually starts a command or data transaction */
688 static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
689 {
690         struct au1xmmc_host *host = mmc_priv(mmc);
691         int ret = 0;
692 
693         WARN_ON(irqs_disabled());
694         WARN_ON(host->status != HOST_S_IDLE);
695 
696         host->mrq = mrq;
697         host->status = HOST_S_CMD;
698 
699         /* fail request immediately if no card is present */
700         if (0 == au1xmmc_card_inserted(mmc)) {
701                 mrq->cmd->error = -ENOMEDIUM;
702                 au1xmmc_finish_request(host);
703                 return;
704         }
705 
706         if (mrq->data) {
707                 FLUSH_FIFO(host);
708                 ret = au1xmmc_prepare_data(host, mrq->data);
709         }
710 
711         if (!ret)
712                 ret = au1xmmc_send_command(host, 0, mrq->cmd, mrq->data);
713 
714         if (ret) {
715                 mrq->cmd->error = ret;
716                 au1xmmc_finish_request(host);
717         }
718 }
719 
720 static void au1xmmc_reset_controller(struct au1xmmc_host *host)
721 {
722         /* Apply the clock */
723         __raw_writel(SD_ENABLE_CE, HOST_ENABLE(host));
724         wmb(); /* drain writebuffer */
725         mdelay(1);
726 
727         __raw_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
728         wmb(); /* drain writebuffer */
729         mdelay(5);
730 
731         __raw_writel(~0, HOST_STATUS(host));
732         wmb(); /* drain writebuffer */
733 
734         __raw_writel(0, HOST_BLKSIZE(host));
735         __raw_writel(0x001fffff, HOST_TIMEOUT(host));
736         wmb(); /* drain writebuffer */
737 
738         __raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
739         wmb(); /* drain writebuffer */
740 
741         __raw_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
742         wmb(); /* drain writebuffer */
743         mdelay(1);
744 
745         __raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
746         wmb(); /* drain writebuffer */
747 
748         /* Configure interrupts */
749         __raw_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
750         wmb(); /* drain writebuffer */
751 }
752 
753 
754 static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
755 {
756         struct au1xmmc_host *host = mmc_priv(mmc);
757         u32 config2;
758 
759         if (ios->power_mode == MMC_POWER_OFF)
760                 au1xmmc_set_power(host, 0);
761         else if (ios->power_mode == MMC_POWER_ON) {
762                 au1xmmc_set_power(host, 1);
763         }
764 
765         if (ios->clock && ios->clock != host->clock) {
766                 au1xmmc_set_clock(host, ios->clock);
767                 host->clock = ios->clock;
768         }
769 
770         config2 = __raw_readl(HOST_CONFIG2(host));
771         switch (ios->bus_width) {
772         case MMC_BUS_WIDTH_8:
773                 config2 |= SD_CONFIG2_BB;
774                 break;
775         case MMC_BUS_WIDTH_4:
776                 config2 &= ~SD_CONFIG2_BB;
777                 config2 |= SD_CONFIG2_WB;
778                 break;
779         case MMC_BUS_WIDTH_1:
780                 config2 &= ~(SD_CONFIG2_WB | SD_CONFIG2_BB);
781                 break;
782         }
783         __raw_writel(config2, HOST_CONFIG2(host));
784         wmb(); /* drain writebuffer */
785 }
786 
787 #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
788 #define STATUS_DATA_IN  (SD_STATUS_NE)
789 #define STATUS_DATA_OUT (SD_STATUS_TH)
790 
791 static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
792 {
793         struct au1xmmc_host *host = dev_id;
794         u32 status;
795 
796         status = __raw_readl(HOST_STATUS(host));
797 
798         if (!(status & SD_STATUS_I))
799                 return IRQ_NONE;        /* not ours */
800 
801         if (status & SD_STATUS_SI)      /* SDIO */
802                 mmc_signal_sdio_irq(host->mmc);
803 
804         if (host->mrq && (status & STATUS_TIMEOUT)) {
805                 if (status & SD_STATUS_RAT)
806                         host->mrq->cmd->error = -ETIMEDOUT;
807                 else if (status & SD_STATUS_DT)
808                         host->mrq->data->error = -ETIMEDOUT;
809 
810                 /* In PIO mode, interrupts might still be enabled */
811                 IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
812 
813                 /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */
814                 tasklet_schedule(&host->finish_task);
815         }
816 #if 0
817         else if (status & SD_STATUS_DD) {
818                 /* Sometimes we get a DD before a NE in PIO mode */
819                 if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE))
820                         au1xmmc_receive_pio(host);
821                 else {
822                         au1xmmc_data_complete(host, status);
823                         /* tasklet_schedule(&host->data_task); */
824                 }
825         }
826 #endif
827         else if (status & SD_STATUS_CR) {
828                 if (host->status == HOST_S_CMD)
829                         au1xmmc_cmd_complete(host, status);
830 
831         } else if (!(host->flags & HOST_F_DMA)) {
832                 if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT))
833                         au1xmmc_send_pio(host);
834                 else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN))
835                         au1xmmc_receive_pio(host);
836 
837         } else if (status & 0x203F3C70) {
838                         DBG("Unhandled status %8.8x\n", host->pdev->id,
839                                 status);
840         }
841 
842         __raw_writel(status, HOST_STATUS(host));
843         wmb(); /* drain writebuffer */
844 
845         return IRQ_HANDLED;
846 }
847 
848 /* 8bit memory DMA device */
849 static dbdev_tab_t au1xmmc_mem_dbdev = {
850         .dev_id         = DSCR_CMD0_ALWAYS,
851         .dev_flags      = DEV_FLAGS_ANYUSE,
852         .dev_tsize      = 0,
853         .dev_devwidth   = 8,
854         .dev_physaddr   = 0x00000000,
855         .dev_intlevel   = 0,
856         .dev_intpolarity = 0,
857 };
858 static int memid;
859 
860 static void au1xmmc_dbdma_callback(int irq, void *dev_id)
861 {
862         struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id;
863 
864         /* Avoid spurious interrupts */
865         if (!host->mrq)
866                 return;
867 
868         if (host->flags & HOST_F_STOP)
869                 SEND_STOP(host);
870 
871         tasklet_schedule(&host->data_task);
872 }
873 
874 static int au1xmmc_dbdma_init(struct au1xmmc_host *host)
875 {
876         struct resource *res;
877         int txid, rxid;
878 
879         res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0);
880         if (!res)
881                 return -ENODEV;
882         txid = res->start;
883 
884         res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1);
885         if (!res)
886                 return -ENODEV;
887         rxid = res->start;
888 
889         if (!memid)
890                 return -ENODEV;
891 
892         host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid,
893                                 au1xmmc_dbdma_callback, (void *)host);
894         if (!host->tx_chan) {
895                 dev_err(&host->pdev->dev, "cannot allocate TX DMA\n");
896                 return -ENODEV;
897         }
898 
899         host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid,
900                                 au1xmmc_dbdma_callback, (void *)host);
901         if (!host->rx_chan) {
902                 dev_err(&host->pdev->dev, "cannot allocate RX DMA\n");
903                 au1xxx_dbdma_chan_free(host->tx_chan);
904                 return -ENODEV;
905         }
906 
907         au1xxx_dbdma_set_devwidth(host->tx_chan, 8);
908         au1xxx_dbdma_set_devwidth(host->rx_chan, 8);
909 
910         au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT);
911         au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT);
912 
913         /* DBDMA is good to go */
914         host->flags |= HOST_F_DMA | HOST_F_DBDMA;
915 
916         return 0;
917 }
918 
919 static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host)
920 {
921         if (host->flags & HOST_F_DMA) {
922                 host->flags &= ~HOST_F_DMA;
923                 au1xxx_dbdma_chan_free(host->tx_chan);
924                 au1xxx_dbdma_chan_free(host->rx_chan);
925         }
926 }
927 
928 static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en)
929 {
930         struct au1xmmc_host *host = mmc_priv(mmc);
931 
932         if (en)
933                 IRQ_ON(host, SD_CONFIG_SI);
934         else
935                 IRQ_OFF(host, SD_CONFIG_SI);
936 }
937 
938 static const struct mmc_host_ops au1xmmc_ops = {
939         .request        = au1xmmc_request,
940         .set_ios        = au1xmmc_set_ios,
941         .get_ro         = au1xmmc_card_readonly,
942         .get_cd         = au1xmmc_card_inserted,
943         .enable_sdio_irq = au1xmmc_enable_sdio_irq,
944 };
945 
946 static int au1xmmc_probe(struct platform_device *pdev)
947 {
948         struct mmc_host *mmc;
949         struct au1xmmc_host *host;
950         struct resource *r;
951         int ret, iflag;
952 
953         mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
954         if (!mmc) {
955                 dev_err(&pdev->dev, "no memory for mmc_host\n");
956                 ret = -ENOMEM;
957                 goto out0;
958         }
959 
960         host = mmc_priv(mmc);
961         host->mmc = mmc;
962         host->platdata = pdev->dev.platform_data;
963         host->pdev = pdev;
964 
965         ret = -ENODEV;
966         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
967         if (!r) {
968                 dev_err(&pdev->dev, "no mmio defined\n");
969                 goto out1;
970         }
971 
972         host->ioarea = request_mem_region(r->start, resource_size(r),
973                                            pdev->name);
974         if (!host->ioarea) {
975                 dev_err(&pdev->dev, "mmio already in use\n");
976                 goto out1;
977         }
978 
979         host->iobase = ioremap(r->start, 0x3c);
980         if (!host->iobase) {
981                 dev_err(&pdev->dev, "cannot remap mmio\n");
982                 goto out2;
983         }
984 
985         r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
986         if (!r) {
987                 dev_err(&pdev->dev, "no IRQ defined\n");
988                 goto out3;
989         }
990         host->irq = r->start;
991 
992         mmc->ops = &au1xmmc_ops;
993 
994         mmc->f_min =   450000;
995         mmc->f_max = 24000000;
996 
997         mmc->max_blk_size = 2048;
998         mmc->max_blk_count = 512;
999 
1000         mmc->ocr_avail = AU1XMMC_OCR;
1001         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1002         mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT;
1003 
1004         iflag = IRQF_SHARED;    /* Au1100/Au1200: one int for both ctrls */
1005 
1006         switch (alchemy_get_cputype()) {
1007         case ALCHEMY_CPU_AU1100:
1008                 mmc->max_seg_size = AU1100_MMC_DESCRIPTOR_SIZE;
1009                 break;
1010         case ALCHEMY_CPU_AU1200:
1011                 mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
1012                 break;
1013         case ALCHEMY_CPU_AU1300:
1014                 iflag = 0;      /* nothing is shared */
1015                 mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
1016                 mmc->f_max = 52000000;
1017                 if (host->ioarea->start == AU1100_SD0_PHYS_ADDR)
1018                         mmc->caps |= MMC_CAP_8_BIT_DATA;
1019                 break;
1020         }
1021 
1022         ret = request_irq(host->irq, au1xmmc_irq, iflag, DRIVER_NAME, host);
1023         if (ret) {
1024                 dev_err(&pdev->dev, "cannot grab IRQ\n");
1025                 goto out3;
1026         }
1027 
1028         host->clk = clk_get(&pdev->dev, ALCHEMY_PERIPH_CLK);
1029         if (IS_ERR(host->clk)) {
1030                 dev_err(&pdev->dev, "cannot find clock\n");
1031                 goto out_irq;
1032         }
1033         if (clk_prepare_enable(host->clk)) {
1034                 dev_err(&pdev->dev, "cannot enable clock\n");
1035                 goto out_clk;
1036         }
1037 
1038         host->status = HOST_S_IDLE;
1039 
1040         /* board-specific carddetect setup, if any */
1041         if (host->platdata && host->platdata->cd_setup) {
1042                 ret = host->platdata->cd_setup(mmc, 1);
1043                 if (ret) {
1044                         dev_warn(&pdev->dev, "board CD setup failed\n");
1045                         mmc->caps |= MMC_CAP_NEEDS_POLL;
1046                 }
1047         } else
1048                 mmc->caps |= MMC_CAP_NEEDS_POLL;
1049 
1050         /* platform may not be able to use all advertised caps */
1051         if (host->platdata)
1052                 mmc->caps &= ~(host->platdata->mask_host_caps);
1053 
1054         tasklet_init(&host->data_task, au1xmmc_tasklet_data,
1055                         (unsigned long)host);
1056 
1057         tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
1058                         (unsigned long)host);
1059 
1060         if (has_dbdma()) {
1061                 ret = au1xmmc_dbdma_init(host);
1062                 if (ret)
1063                         pr_info(DRIVER_NAME ": DBDMA init failed; using PIO\n");
1064         }
1065 
1066 #ifdef CONFIG_LEDS_CLASS
1067         if (host->platdata && host->platdata->led) {
1068                 struct led_classdev *led = host->platdata->led;
1069                 led->name = mmc_hostname(mmc);
1070                 led->brightness = LED_OFF;
1071                 led->default_trigger = mmc_hostname(mmc);
1072                 ret = led_classdev_register(mmc_dev(mmc), led);
1073                 if (ret)
1074                         goto out5;
1075         }
1076 #endif
1077 
1078         au1xmmc_reset_controller(host);
1079 
1080         ret = mmc_add_host(mmc);
1081         if (ret) {
1082                 dev_err(&pdev->dev, "cannot add mmc host\n");
1083                 goto out6;
1084         }
1085 
1086         platform_set_drvdata(pdev, host);
1087 
1088         pr_info(DRIVER_NAME ": MMC Controller %d set up at %p"
1089                 " (mode=%s)\n", pdev->id, host->iobase,
1090                 host->flags & HOST_F_DMA ? "dma" : "pio");
1091 
1092         return 0;       /* all ok */
1093 
1094 out6:
1095 #ifdef CONFIG_LEDS_CLASS
1096         if (host->platdata && host->platdata->led)
1097                 led_classdev_unregister(host->platdata->led);
1098 out5:
1099 #endif
1100         __raw_writel(0, HOST_ENABLE(host));
1101         __raw_writel(0, HOST_CONFIG(host));
1102         __raw_writel(0, HOST_CONFIG2(host));
1103         wmb(); /* drain writebuffer */
1104 
1105         if (host->flags & HOST_F_DBDMA)
1106                 au1xmmc_dbdma_shutdown(host);
1107 
1108         tasklet_kill(&host->data_task);
1109         tasklet_kill(&host->finish_task);
1110 
1111         if (host->platdata && host->platdata->cd_setup &&
1112             !(mmc->caps & MMC_CAP_NEEDS_POLL))
1113                 host->platdata->cd_setup(mmc, 0);
1114 out_clk:
1115         clk_disable_unprepare(host->clk);
1116         clk_put(host->clk);
1117 out_irq:
1118         free_irq(host->irq, host);
1119 out3:
1120         iounmap((void *)host->iobase);
1121 out2:
1122         release_resource(host->ioarea);
1123         kfree(host->ioarea);
1124 out1:
1125         mmc_free_host(mmc);
1126 out0:
1127         return ret;
1128 }
1129 
1130 static int au1xmmc_remove(struct platform_device *pdev)
1131 {
1132         struct au1xmmc_host *host = platform_get_drvdata(pdev);
1133 
1134         if (host) {
1135                 mmc_remove_host(host->mmc);
1136 
1137 #ifdef CONFIG_LEDS_CLASS
1138                 if (host->platdata && host->platdata->led)
1139                         led_classdev_unregister(host->platdata->led);
1140 #endif
1141 
1142                 if (host->platdata && host->platdata->cd_setup &&
1143                     !(host->mmc->caps & MMC_CAP_NEEDS_POLL))
1144                         host->platdata->cd_setup(host->mmc, 0);
1145 
1146                 __raw_writel(0, HOST_ENABLE(host));
1147                 __raw_writel(0, HOST_CONFIG(host));
1148                 __raw_writel(0, HOST_CONFIG2(host));
1149                 wmb(); /* drain writebuffer */
1150 
1151                 tasklet_kill(&host->data_task);
1152                 tasklet_kill(&host->finish_task);
1153 
1154                 if (host->flags & HOST_F_DBDMA)
1155                         au1xmmc_dbdma_shutdown(host);
1156 
1157                 au1xmmc_set_power(host, 0);
1158 
1159                 clk_disable_unprepare(host->clk);
1160                 clk_put(host->clk);
1161 
1162                 free_irq(host->irq, host);
1163                 iounmap((void *)host->iobase);
1164                 release_resource(host->ioarea);
1165                 kfree(host->ioarea);
1166 
1167                 mmc_free_host(host->mmc);
1168         }
1169         return 0;
1170 }
1171 
1172 #ifdef CONFIG_PM
1173 static int au1xmmc_suspend(struct platform_device *pdev, pm_message_t state)
1174 {
1175         struct au1xmmc_host *host = platform_get_drvdata(pdev);
1176 
1177         __raw_writel(0, HOST_CONFIG2(host));
1178         __raw_writel(0, HOST_CONFIG(host));
1179         __raw_writel(0xffffffff, HOST_STATUS(host));
1180         __raw_writel(0, HOST_ENABLE(host));
1181         wmb(); /* drain writebuffer */
1182 
1183         return 0;
1184 }
1185 
1186 static int au1xmmc_resume(struct platform_device *pdev)
1187 {
1188         struct au1xmmc_host *host = platform_get_drvdata(pdev);
1189 
1190         au1xmmc_reset_controller(host);
1191 
1192         return 0;
1193 }
1194 #else
1195 #define au1xmmc_suspend NULL
1196 #define au1xmmc_resume NULL
1197 #endif
1198 
1199 static struct platform_driver au1xmmc_driver = {
1200         .probe         = au1xmmc_probe,
1201         .remove        = au1xmmc_remove,
1202         .suspend       = au1xmmc_suspend,
1203         .resume        = au1xmmc_resume,
1204         .driver        = {
1205                 .name  = DRIVER_NAME,
1206                 .owner = THIS_MODULE,
1207         },
1208 };
1209 
1210 static int __init au1xmmc_init(void)
1211 {
1212         if (has_dbdma()) {
1213                 /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
1214                 * of 8 bits.  And since devices are shared, we need to create
1215                 * our own to avoid freaking out other devices.
1216                 */
1217                 memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
1218                 if (!memid)
1219                         pr_err("au1xmmc: cannot add memory dbdma\n");
1220         }
1221         return platform_driver_register(&au1xmmc_driver);
1222 }
1223 
1224 static void __exit au1xmmc_exit(void)
1225 {
1226         if (has_dbdma() && memid)
1227                 au1xxx_ddma_del_device(memid);
1228 
1229         platform_driver_unregister(&au1xmmc_driver);
1230 }
1231 
1232 module_init(au1xmmc_init);
1233 module_exit(au1xmmc_exit);
1234 
1235 MODULE_AUTHOR("Advanced Micro Devices, Inc");
1236 MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
1237 MODULE_LICENSE("GPL");
1238 MODULE_ALIAS("platform:au1xxx-mmc");
1239 

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