Version:  2.0.40 2.2.26 2.4.37 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7

Linux/drivers/mmc/host/atmel-mci.c

  1 /*
  2  * Atmel MultiMedia Card Interface driver
  3  *
  4  * Copyright (C) 2004-2008 Atmel Corporation
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License version 2 as
  8  * published by the Free Software Foundation.
  9  */
 10 #include <linux/blkdev.h>
 11 #include <linux/clk.h>
 12 #include <linux/debugfs.h>
 13 #include <linux/device.h>
 14 #include <linux/dmaengine.h>
 15 #include <linux/dma-mapping.h>
 16 #include <linux/err.h>
 17 #include <linux/gpio.h>
 18 #include <linux/init.h>
 19 #include <linux/interrupt.h>
 20 #include <linux/io.h>
 21 #include <linux/ioport.h>
 22 #include <linux/module.h>
 23 #include <linux/of.h>
 24 #include <linux/of_device.h>
 25 #include <linux/of_gpio.h>
 26 #include <linux/platform_device.h>
 27 #include <linux/scatterlist.h>
 28 #include <linux/seq_file.h>
 29 #include <linux/slab.h>
 30 #include <linux/stat.h>
 31 #include <linux/types.h>
 32 
 33 #include <linux/mmc/host.h>
 34 #include <linux/mmc/sdio.h>
 35 
 36 #include <linux/atmel-mci.h>
 37 #include <linux/atmel_pdc.h>
 38 #include <linux/pm.h>
 39 #include <linux/pm_runtime.h>
 40 #include <linux/pinctrl/consumer.h>
 41 
 42 #include <asm/cacheflush.h>
 43 #include <asm/io.h>
 44 #include <asm/unaligned.h>
 45 
 46 /*
 47  * Superset of MCI IP registers integrated in Atmel AVR32 and AT91 Processors
 48  * Registers and bitfields marked with [2] are only available in MCI2
 49  */
 50 
 51 /* MCI Register Definitions */
 52 #define ATMCI_CR                        0x0000  /* Control */
 53 #define         ATMCI_CR_MCIEN                  BIT(0)          /* MCI Enable */
 54 #define         ATMCI_CR_MCIDIS                 BIT(1)          /* MCI Disable */
 55 #define         ATMCI_CR_PWSEN                  BIT(2)          /* Power Save Enable */
 56 #define         ATMCI_CR_PWSDIS                 BIT(3)          /* Power Save Disable */
 57 #define         ATMCI_CR_SWRST                  BIT(7)          /* Software Reset */
 58 #define ATMCI_MR                        0x0004  /* Mode */
 59 #define         ATMCI_MR_CLKDIV(x)              ((x) <<  0)     /* Clock Divider */
 60 #define         ATMCI_MR_PWSDIV(x)              ((x) <<  8)     /* Power Saving Divider */
 61 #define         ATMCI_MR_RDPROOF                BIT(11)         /* Read Proof */
 62 #define         ATMCI_MR_WRPROOF                BIT(12)         /* Write Proof */
 63 #define         ATMCI_MR_PDCFBYTE               BIT(13)         /* Force Byte Transfer */
 64 #define         ATMCI_MR_PDCPADV                BIT(14)         /* Padding Value */
 65 #define         ATMCI_MR_PDCMODE                BIT(15)         /* PDC-oriented Mode */
 66 #define         ATMCI_MR_CLKODD(x)              ((x) << 16)     /* LSB of Clock Divider */
 67 #define ATMCI_DTOR                      0x0008  /* Data Timeout */
 68 #define         ATMCI_DTOCYC(x)                 ((x) <<  0)     /* Data Timeout Cycles */
 69 #define         ATMCI_DTOMUL(x)                 ((x) <<  4)     /* Data Timeout Multiplier */
 70 #define ATMCI_SDCR                      0x000c  /* SD Card / SDIO */
 71 #define         ATMCI_SDCSEL_SLOT_A             (0 <<  0)       /* Select SD slot A */
 72 #define         ATMCI_SDCSEL_SLOT_B             (1 <<  0)       /* Select SD slot A */
 73 #define         ATMCI_SDCSEL_MASK               (3 <<  0)
 74 #define         ATMCI_SDCBUS_1BIT               (0 <<  6)       /* 1-bit data bus */
 75 #define         ATMCI_SDCBUS_4BIT               (2 <<  6)       /* 4-bit data bus */
 76 #define         ATMCI_SDCBUS_8BIT               (3 <<  6)       /* 8-bit data bus[2] */
 77 #define         ATMCI_SDCBUS_MASK               (3 <<  6)
 78 #define ATMCI_ARGR                      0x0010  /* Command Argument */
 79 #define ATMCI_CMDR                      0x0014  /* Command */
 80 #define         ATMCI_CMDR_CMDNB(x)             ((x) <<  0)     /* Command Opcode */
 81 #define         ATMCI_CMDR_RSPTYP_NONE          (0 <<  6)       /* No response */
 82 #define         ATMCI_CMDR_RSPTYP_48BIT         (1 <<  6)       /* 48-bit response */
 83 #define         ATMCI_CMDR_RSPTYP_136BIT        (2 <<  6)       /* 136-bit response */
 84 #define         ATMCI_CMDR_SPCMD_INIT           (1 <<  8)       /* Initialization command */
 85 #define         ATMCI_CMDR_SPCMD_SYNC           (2 <<  8)       /* Synchronized command */
 86 #define         ATMCI_CMDR_SPCMD_INT            (4 <<  8)       /* Interrupt command */
 87 #define         ATMCI_CMDR_SPCMD_INTRESP        (5 <<  8)       /* Interrupt response */
 88 #define         ATMCI_CMDR_OPDCMD               (1 << 11)       /* Open Drain */
 89 #define         ATMCI_CMDR_MAXLAT_5CYC          (0 << 12)       /* Max latency 5 cycles */
 90 #define         ATMCI_CMDR_MAXLAT_64CYC         (1 << 12)       /* Max latency 64 cycles */
 91 #define         ATMCI_CMDR_START_XFER           (1 << 16)       /* Start data transfer */
 92 #define         ATMCI_CMDR_STOP_XFER            (2 << 16)       /* Stop data transfer */
 93 #define         ATMCI_CMDR_TRDIR_WRITE          (0 << 18)       /* Write data */
 94 #define         ATMCI_CMDR_TRDIR_READ           (1 << 18)       /* Read data */
 95 #define         ATMCI_CMDR_BLOCK                (0 << 19)       /* Single-block transfer */
 96 #define         ATMCI_CMDR_MULTI_BLOCK          (1 << 19)       /* Multi-block transfer */
 97 #define         ATMCI_CMDR_STREAM               (2 << 19)       /* MMC Stream transfer */
 98 #define         ATMCI_CMDR_SDIO_BYTE            (4 << 19)       /* SDIO Byte transfer */
 99 #define         ATMCI_CMDR_SDIO_BLOCK           (5 << 19)       /* SDIO Block transfer */
100 #define         ATMCI_CMDR_SDIO_SUSPEND         (1 << 24)       /* SDIO Suspend Command */
101 #define         ATMCI_CMDR_SDIO_RESUME          (2 << 24)       /* SDIO Resume Command */
102 #define ATMCI_BLKR                      0x0018  /* Block */
103 #define         ATMCI_BCNT(x)                   ((x) <<  0)     /* Data Block Count */
104 #define         ATMCI_BLKLEN(x)                 ((x) << 16)     /* Data Block Length */
105 #define ATMCI_CSTOR                     0x001c  /* Completion Signal Timeout[2] */
106 #define         ATMCI_CSTOCYC(x)                ((x) <<  0)     /* CST cycles */
107 #define         ATMCI_CSTOMUL(x)                ((x) <<  4)     /* CST multiplier */
108 #define ATMCI_RSPR                      0x0020  /* Response 0 */
109 #define ATMCI_RSPR1                     0x0024  /* Response 1 */
110 #define ATMCI_RSPR2                     0x0028  /* Response 2 */
111 #define ATMCI_RSPR3                     0x002c  /* Response 3 */
112 #define ATMCI_RDR                       0x0030  /* Receive Data */
113 #define ATMCI_TDR                       0x0034  /* Transmit Data */
114 #define ATMCI_SR                        0x0040  /* Status */
115 #define ATMCI_IER                       0x0044  /* Interrupt Enable */
116 #define ATMCI_IDR                       0x0048  /* Interrupt Disable */
117 #define ATMCI_IMR                       0x004c  /* Interrupt Mask */
118 #define         ATMCI_CMDRDY                    BIT(0)          /* Command Ready */
119 #define         ATMCI_RXRDY                     BIT(1)          /* Receiver Ready */
120 #define         ATMCI_TXRDY                     BIT(2)          /* Transmitter Ready */
121 #define         ATMCI_BLKE                      BIT(3)          /* Data Block Ended */
122 #define         ATMCI_DTIP                      BIT(4)          /* Data Transfer In Progress */
123 #define         ATMCI_NOTBUSY                   BIT(5)          /* Data Not Busy */
124 #define         ATMCI_ENDRX                     BIT(6)          /* End of RX Buffer */
125 #define         ATMCI_ENDTX                     BIT(7)          /* End of TX Buffer */
126 #define         ATMCI_SDIOIRQA                  BIT(8)          /* SDIO IRQ in slot A */
127 #define         ATMCI_SDIOIRQB                  BIT(9)          /* SDIO IRQ in slot B */
128 #define         ATMCI_SDIOWAIT                  BIT(12)         /* SDIO Read Wait Operation Status */
129 #define         ATMCI_CSRCV                     BIT(13)         /* CE-ATA Completion Signal Received */
130 #define         ATMCI_RXBUFF                    BIT(14)         /* RX Buffer Full */
131 #define         ATMCI_TXBUFE                    BIT(15)         /* TX Buffer Empty */
132 #define         ATMCI_RINDE                     BIT(16)         /* Response Index Error */
133 #define         ATMCI_RDIRE                     BIT(17)         /* Response Direction Error */
134 #define         ATMCI_RCRCE                     BIT(18)         /* Response CRC Error */
135 #define         ATMCI_RENDE                     BIT(19)         /* Response End Bit Error */
136 #define         ATMCI_RTOE                      BIT(20)         /* Response Time-Out Error */
137 #define         ATMCI_DCRCE                     BIT(21)         /* Data CRC Error */
138 #define         ATMCI_DTOE                      BIT(22)         /* Data Time-Out Error */
139 #define         ATMCI_CSTOE                     BIT(23)         /* Completion Signal Time-out Error */
140 #define         ATMCI_BLKOVRE                   BIT(24)         /* DMA Block Overrun Error */
141 #define         ATMCI_DMADONE                   BIT(25)         /* DMA Transfer Done */
142 #define         ATMCI_FIFOEMPTY                 BIT(26)         /* FIFO Empty Flag */
143 #define         ATMCI_XFRDONE                   BIT(27)         /* Transfer Done Flag */
144 #define         ATMCI_ACKRCV                    BIT(28)         /* Boot Operation Acknowledge Received */
145 #define         ATMCI_ACKRCVE                   BIT(29)         /* Boot Operation Acknowledge Error */
146 #define         ATMCI_OVRE                      BIT(30)         /* RX Overrun Error */
147 #define         ATMCI_UNRE                      BIT(31)         /* TX Underrun Error */
148 #define ATMCI_DMA                       0x0050  /* DMA Configuration[2] */
149 #define         ATMCI_DMA_OFFSET(x)             ((x) <<  0)     /* DMA Write Buffer Offset */
150 #define         ATMCI_DMA_CHKSIZE(x)            ((x) <<  4)     /* DMA Channel Read and Write Chunk Size */
151 #define         ATMCI_DMAEN                     BIT(8)  /* DMA Hardware Handshaking Enable */
152 #define ATMCI_CFG                       0x0054  /* Configuration[2] */
153 #define         ATMCI_CFG_FIFOMODE_1DATA        BIT(0)          /* MCI Internal FIFO control mode */
154 #define         ATMCI_CFG_FERRCTRL_COR          BIT(4)          /* Flow Error flag reset control mode */
155 #define         ATMCI_CFG_HSMODE                BIT(8)          /* High Speed Mode */
156 #define         ATMCI_CFG_LSYNC                 BIT(12)         /* Synchronize on the last block */
157 #define ATMCI_WPMR                      0x00e4  /* Write Protection Mode[2] */
158 #define         ATMCI_WP_EN                     BIT(0)          /* WP Enable */
159 #define         ATMCI_WP_KEY                    (0x4d4349 << 8) /* WP Key */
160 #define ATMCI_WPSR                      0x00e8  /* Write Protection Status[2] */
161 #define         ATMCI_GET_WP_VS(x)              ((x) & 0x0f)
162 #define         ATMCI_GET_WP_VSRC(x)            (((x) >> 8) & 0xffff)
163 #define ATMCI_VERSION                   0x00FC  /* Version */
164 #define ATMCI_FIFO_APERTURE             0x0200  /* FIFO Aperture[2] */
165 
166 /* This is not including the FIFO Aperture on MCI2 */
167 #define ATMCI_REGS_SIZE         0x100
168 
169 /* Register access macros */
170 #define atmci_readl(port, reg)                          \
171         __raw_readl((port)->regs + reg)
172 #define atmci_writel(port, reg, value)                  \
173         __raw_writel((value), (port)->regs + reg)
174 
175 /* On AVR chips the Peripheral DMA Controller is not connected to MCI. */
176 #ifdef CONFIG_AVR32
177 #       define ATMCI_PDC_CONNECTED      0
178 #else
179 #       define ATMCI_PDC_CONNECTED      1
180 #endif
181 
182 #define AUTOSUSPEND_DELAY       50
183 
184 #define ATMCI_DATA_ERROR_FLAGS  (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
185 #define ATMCI_DMA_THRESHOLD     16
186 
187 enum {
188         EVENT_CMD_RDY = 0,
189         EVENT_XFER_COMPLETE,
190         EVENT_NOTBUSY,
191         EVENT_DATA_ERROR,
192 };
193 
194 enum atmel_mci_state {
195         STATE_IDLE = 0,
196         STATE_SENDING_CMD,
197         STATE_DATA_XFER,
198         STATE_WAITING_NOTBUSY,
199         STATE_SENDING_STOP,
200         STATE_END_REQUEST,
201 };
202 
203 enum atmci_xfer_dir {
204         XFER_RECEIVE = 0,
205         XFER_TRANSMIT,
206 };
207 
208 enum atmci_pdc_buf {
209         PDC_FIRST_BUF = 0,
210         PDC_SECOND_BUF,
211 };
212 
213 struct atmel_mci_caps {
214         bool    has_dma_conf_reg;
215         bool    has_pdc;
216         bool    has_cfg_reg;
217         bool    has_cstor_reg;
218         bool    has_highspeed;
219         bool    has_rwproof;
220         bool    has_odd_clk_div;
221         bool    has_bad_data_ordering;
222         bool    need_reset_after_xfer;
223         bool    need_blksz_mul_4;
224         bool    need_notbusy_for_read_ops;
225 };
226 
227 struct atmel_mci_dma {
228         struct dma_chan                 *chan;
229         struct dma_async_tx_descriptor  *data_desc;
230 };
231 
232 /**
233  * struct atmel_mci - MMC controller state shared between all slots
234  * @lock: Spinlock protecting the queue and associated data.
235  * @regs: Pointer to MMIO registers.
236  * @sg: Scatterlist entry currently being processed by PIO or PDC code.
237  * @pio_offset: Offset into the current scatterlist entry.
238  * @buffer: Buffer used if we don't have the r/w proof capability. We
239  *      don't have the time to switch pdc buffers so we have to use only
240  *      one buffer for the full transaction.
241  * @buf_size: size of the buffer.
242  * @phys_buf_addr: buffer address needed for pdc.
243  * @cur_slot: The slot which is currently using the controller.
244  * @mrq: The request currently being processed on @cur_slot,
245  *      or NULL if the controller is idle.
246  * @cmd: The command currently being sent to the card, or NULL.
247  * @data: The data currently being transferred, or NULL if no data
248  *      transfer is in progress.
249  * @data_size: just data->blocks * data->blksz.
250  * @dma: DMA client state.
251  * @data_chan: DMA channel being used for the current data transfer.
252  * @cmd_status: Snapshot of SR taken upon completion of the current
253  *      command. Only valid when EVENT_CMD_COMPLETE is pending.
254  * @data_status: Snapshot of SR taken upon completion of the current
255  *      data transfer. Only valid when EVENT_DATA_COMPLETE or
256  *      EVENT_DATA_ERROR is pending.
257  * @stop_cmdr: Value to be loaded into CMDR when the stop command is
258  *      to be sent.
259  * @tasklet: Tasklet running the request state machine.
260  * @pending_events: Bitmask of events flagged by the interrupt handler
261  *      to be processed by the tasklet.
262  * @completed_events: Bitmask of events which the state machine has
263  *      processed.
264  * @state: Tasklet state.
265  * @queue: List of slots waiting for access to the controller.
266  * @need_clock_update: Update the clock rate before the next request.
267  * @need_reset: Reset controller before next request.
268  * @timer: Timer to balance the data timeout error flag which cannot rise.
269  * @mode_reg: Value of the MR register.
270  * @cfg_reg: Value of the CFG register.
271  * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
272  *      rate and timeout calculations.
273  * @mapbase: Physical address of the MMIO registers.
274  * @mck: The peripheral bus clock hooked up to the MMC controller.
275  * @pdev: Platform device associated with the MMC controller.
276  * @slot: Slots sharing this MMC controller.
277  * @caps: MCI capabilities depending on MCI version.
278  * @prepare_data: function to setup MCI before data transfer which
279  * depends on MCI capabilities.
280  * @submit_data: function to start data transfer which depends on MCI
281  * capabilities.
282  * @stop_transfer: function to stop data transfer which depends on MCI
283  * capabilities.
284  *
285  * Locking
286  * =======
287  *
288  * @lock is a softirq-safe spinlock protecting @queue as well as
289  * @cur_slot, @mrq and @state. These must always be updated
290  * at the same time while holding @lock.
291  *
292  * @lock also protects mode_reg and need_clock_update since these are
293  * used to synchronize mode register updates with the queue
294  * processing.
295  *
296  * The @mrq field of struct atmel_mci_slot is also protected by @lock,
297  * and must always be written at the same time as the slot is added to
298  * @queue.
299  *
300  * @pending_events and @completed_events are accessed using atomic bit
301  * operations, so they don't need any locking.
302  *
303  * None of the fields touched by the interrupt handler need any
304  * locking. However, ordering is important: Before EVENT_DATA_ERROR or
305  * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
306  * interrupts must be disabled and @data_status updated with a
307  * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
308  * CMDRDY interrupt must be disabled and @cmd_status updated with a
309  * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
310  * bytes_xfered field of @data must be written. This is ensured by
311  * using barriers.
312  */
313 struct atmel_mci {
314         spinlock_t              lock;
315         void __iomem            *regs;
316 
317         struct scatterlist      *sg;
318         unsigned int            sg_len;
319         unsigned int            pio_offset;
320         unsigned int            *buffer;
321         unsigned int            buf_size;
322         dma_addr_t              buf_phys_addr;
323 
324         struct atmel_mci_slot   *cur_slot;
325         struct mmc_request      *mrq;
326         struct mmc_command      *cmd;
327         struct mmc_data         *data;
328         unsigned int            data_size;
329 
330         struct atmel_mci_dma    dma;
331         struct dma_chan         *data_chan;
332         struct dma_slave_config dma_conf;
333 
334         u32                     cmd_status;
335         u32                     data_status;
336         u32                     stop_cmdr;
337 
338         struct tasklet_struct   tasklet;
339         unsigned long           pending_events;
340         unsigned long           completed_events;
341         enum atmel_mci_state    state;
342         struct list_head        queue;
343 
344         bool                    need_clock_update;
345         bool                    need_reset;
346         struct timer_list       timer;
347         u32                     mode_reg;
348         u32                     cfg_reg;
349         unsigned long           bus_hz;
350         unsigned long           mapbase;
351         struct clk              *mck;
352         struct platform_device  *pdev;
353 
354         struct atmel_mci_slot   *slot[ATMCI_MAX_NR_SLOTS];
355 
356         struct atmel_mci_caps   caps;
357 
358         u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
359         void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
360         void (*stop_transfer)(struct atmel_mci *host);
361 };
362 
363 /**
364  * struct atmel_mci_slot - MMC slot state
365  * @mmc: The mmc_host representing this slot.
366  * @host: The MMC controller this slot is using.
367  * @sdc_reg: Value of SDCR to be written before using this slot.
368  * @sdio_irq: SDIO irq mask for this slot.
369  * @mrq: mmc_request currently being processed or waiting to be
370  *      processed, or NULL when the slot is idle.
371  * @queue_node: List node for placing this node in the @queue list of
372  *      &struct atmel_mci.
373  * @clock: Clock rate configured by set_ios(). Protected by host->lock.
374  * @flags: Random state bits associated with the slot.
375  * @detect_pin: GPIO pin used for card detection, or negative if not
376  *      available.
377  * @wp_pin: GPIO pin used for card write protect sending, or negative
378  *      if not available.
379  * @detect_is_active_high: The state of the detect pin when it is active.
380  * @detect_timer: Timer used for debouncing @detect_pin interrupts.
381  */
382 struct atmel_mci_slot {
383         struct mmc_host         *mmc;
384         struct atmel_mci        *host;
385 
386         u32                     sdc_reg;
387         u32                     sdio_irq;
388 
389         struct mmc_request      *mrq;
390         struct list_head        queue_node;
391 
392         unsigned int            clock;
393         unsigned long           flags;
394 #define ATMCI_CARD_PRESENT      0
395 #define ATMCI_CARD_NEED_INIT    1
396 #define ATMCI_SHUTDOWN          2
397 
398         int                     detect_pin;
399         int                     wp_pin;
400         bool                    detect_is_active_high;
401 
402         struct timer_list       detect_timer;
403 };
404 
405 #define atmci_test_and_clear_pending(host, event)               \
406         test_and_clear_bit(event, &host->pending_events)
407 #define atmci_set_completed(host, event)                        \
408         set_bit(event, &host->completed_events)
409 #define atmci_set_pending(host, event)                          \
410         set_bit(event, &host->pending_events)
411 
412 /*
413  * The debugfs stuff below is mostly optimized away when
414  * CONFIG_DEBUG_FS is not set.
415  */
416 static int atmci_req_show(struct seq_file *s, void *v)
417 {
418         struct atmel_mci_slot   *slot = s->private;
419         struct mmc_request      *mrq;
420         struct mmc_command      *cmd;
421         struct mmc_command      *stop;
422         struct mmc_data         *data;
423 
424         /* Make sure we get a consistent snapshot */
425         spin_lock_bh(&slot->host->lock);
426         mrq = slot->mrq;
427 
428         if (mrq) {
429                 cmd = mrq->cmd;
430                 data = mrq->data;
431                 stop = mrq->stop;
432 
433                 if (cmd)
434                         seq_printf(s,
435                                 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
436                                 cmd->opcode, cmd->arg, cmd->flags,
437                                 cmd->resp[0], cmd->resp[1], cmd->resp[2],
438                                 cmd->resp[3], cmd->error);
439                 if (data)
440                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
441                                 data->bytes_xfered, data->blocks,
442                                 data->blksz, data->flags, data->error);
443                 if (stop)
444                         seq_printf(s,
445                                 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
446                                 stop->opcode, stop->arg, stop->flags,
447                                 stop->resp[0], stop->resp[1], stop->resp[2],
448                                 stop->resp[3], stop->error);
449         }
450 
451         spin_unlock_bh(&slot->host->lock);
452 
453         return 0;
454 }
455 
456 static int atmci_req_open(struct inode *inode, struct file *file)
457 {
458         return single_open(file, atmci_req_show, inode->i_private);
459 }
460 
461 static const struct file_operations atmci_req_fops = {
462         .owner          = THIS_MODULE,
463         .open           = atmci_req_open,
464         .read           = seq_read,
465         .llseek         = seq_lseek,
466         .release        = single_release,
467 };
468 
469 static void atmci_show_status_reg(struct seq_file *s,
470                 const char *regname, u32 value)
471 {
472         static const char       *sr_bit[] = {
473                 [0]     = "CMDRDY",
474                 [1]     = "RXRDY",
475                 [2]     = "TXRDY",
476                 [3]     = "BLKE",
477                 [4]     = "DTIP",
478                 [5]     = "NOTBUSY",
479                 [6]     = "ENDRX",
480                 [7]     = "ENDTX",
481                 [8]     = "SDIOIRQA",
482                 [9]     = "SDIOIRQB",
483                 [12]    = "SDIOWAIT",
484                 [14]    = "RXBUFF",
485                 [15]    = "TXBUFE",
486                 [16]    = "RINDE",
487                 [17]    = "RDIRE",
488                 [18]    = "RCRCE",
489                 [19]    = "RENDE",
490                 [20]    = "RTOE",
491                 [21]    = "DCRCE",
492                 [22]    = "DTOE",
493                 [23]    = "CSTOE",
494                 [24]    = "BLKOVRE",
495                 [25]    = "DMADONE",
496                 [26]    = "FIFOEMPTY",
497                 [27]    = "XFRDONE",
498                 [30]    = "OVRE",
499                 [31]    = "UNRE",
500         };
501         unsigned int            i;
502 
503         seq_printf(s, "%s:\t0x%08x", regname, value);
504         for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
505                 if (value & (1 << i)) {
506                         if (sr_bit[i])
507                                 seq_printf(s, " %s", sr_bit[i]);
508                         else
509                                 seq_puts(s, " UNKNOWN");
510                 }
511         }
512         seq_putc(s, '\n');
513 }
514 
515 static int atmci_regs_show(struct seq_file *s, void *v)
516 {
517         struct atmel_mci        *host = s->private;
518         u32                     *buf;
519         int                     ret = 0;
520 
521 
522         buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
523         if (!buf)
524                 return -ENOMEM;
525 
526         pm_runtime_get_sync(&host->pdev->dev);
527 
528         /*
529          * Grab a more or less consistent snapshot. Note that we're
530          * not disabling interrupts, so IMR and SR may not be
531          * consistent.
532          */
533         spin_lock_bh(&host->lock);
534         memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
535         spin_unlock_bh(&host->lock);
536 
537         pm_runtime_mark_last_busy(&host->pdev->dev);
538         pm_runtime_put_autosuspend(&host->pdev->dev);
539 
540         seq_printf(s, "MR:\t0x%08x%s%s ",
541                         buf[ATMCI_MR / 4],
542                         buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
543                         buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "");
544         if (host->caps.has_odd_clk_div)
545                 seq_printf(s, "{CLKDIV,CLKODD}=%u\n",
546                                 ((buf[ATMCI_MR / 4] & 0xff) << 1)
547                                 | ((buf[ATMCI_MR / 4] >> 16) & 1));
548         else
549                 seq_printf(s, "CLKDIV=%u\n",
550                                 (buf[ATMCI_MR / 4] & 0xff));
551         seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
552         seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
553         seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
554         seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
555                         buf[ATMCI_BLKR / 4],
556                         buf[ATMCI_BLKR / 4] & 0xffff,
557                         (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
558         if (host->caps.has_cstor_reg)
559                 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
560 
561         /* Don't read RSPR and RDR; it will consume the data there */
562 
563         atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
564         atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
565 
566         if (host->caps.has_dma_conf_reg) {
567                 u32 val;
568 
569                 val = buf[ATMCI_DMA / 4];
570                 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
571                                 val, val & 3,
572                                 ((val >> 4) & 3) ?
573                                         1 << (((val >> 4) & 3) + 1) : 1,
574                                 val & ATMCI_DMAEN ? " DMAEN" : "");
575         }
576         if (host->caps.has_cfg_reg) {
577                 u32 val;
578 
579                 val = buf[ATMCI_CFG / 4];
580                 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
581                                 val,
582                                 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
583                                 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
584                                 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
585                                 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
586         }
587 
588         kfree(buf);
589 
590         return ret;
591 }
592 
593 static int atmci_regs_open(struct inode *inode, struct file *file)
594 {
595         return single_open(file, atmci_regs_show, inode->i_private);
596 }
597 
598 static const struct file_operations atmci_regs_fops = {
599         .owner          = THIS_MODULE,
600         .open           = atmci_regs_open,
601         .read           = seq_read,
602         .llseek         = seq_lseek,
603         .release        = single_release,
604 };
605 
606 static void atmci_init_debugfs(struct atmel_mci_slot *slot)
607 {
608         struct mmc_host         *mmc = slot->mmc;
609         struct atmel_mci        *host = slot->host;
610         struct dentry           *root;
611         struct dentry           *node;
612 
613         root = mmc->debugfs_root;
614         if (!root)
615                 return;
616 
617         node = debugfs_create_file("regs", S_IRUSR, root, host,
618                         &atmci_regs_fops);
619         if (IS_ERR(node))
620                 return;
621         if (!node)
622                 goto err;
623 
624         node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
625         if (!node)
626                 goto err;
627 
628         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
629         if (!node)
630                 goto err;
631 
632         node = debugfs_create_x32("pending_events", S_IRUSR, root,
633                                      (u32 *)&host->pending_events);
634         if (!node)
635                 goto err;
636 
637         node = debugfs_create_x32("completed_events", S_IRUSR, root,
638                                      (u32 *)&host->completed_events);
639         if (!node)
640                 goto err;
641 
642         return;
643 
644 err:
645         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
646 }
647 
648 #if defined(CONFIG_OF)
649 static const struct of_device_id atmci_dt_ids[] = {
650         { .compatible = "atmel,hsmci" },
651         { /* sentinel */ }
652 };
653 
654 MODULE_DEVICE_TABLE(of, atmci_dt_ids);
655 
656 static struct mci_platform_data*
657 atmci_of_init(struct platform_device *pdev)
658 {
659         struct device_node *np = pdev->dev.of_node;
660         struct device_node *cnp;
661         struct mci_platform_data *pdata;
662         u32 slot_id;
663 
664         if (!np) {
665                 dev_err(&pdev->dev, "device node not found\n");
666                 return ERR_PTR(-EINVAL);
667         }
668 
669         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
670         if (!pdata) {
671                 dev_err(&pdev->dev, "could not allocate memory for pdata\n");
672                 return ERR_PTR(-ENOMEM);
673         }
674 
675         for_each_child_of_node(np, cnp) {
676                 if (of_property_read_u32(cnp, "reg", &slot_id)) {
677                         dev_warn(&pdev->dev, "reg property is missing for %s\n",
678                                  cnp->full_name);
679                         continue;
680                 }
681 
682                 if (slot_id >= ATMCI_MAX_NR_SLOTS) {
683                         dev_warn(&pdev->dev, "can't have more than %d slots\n",
684                                  ATMCI_MAX_NR_SLOTS);
685                         break;
686                 }
687 
688                 if (of_property_read_u32(cnp, "bus-width",
689                                          &pdata->slot[slot_id].bus_width))
690                         pdata->slot[slot_id].bus_width = 1;
691 
692                 pdata->slot[slot_id].detect_pin =
693                         of_get_named_gpio(cnp, "cd-gpios", 0);
694 
695                 pdata->slot[slot_id].detect_is_active_high =
696                         of_property_read_bool(cnp, "cd-inverted");
697 
698                 pdata->slot[slot_id].non_removable =
699                         of_property_read_bool(cnp, "non-removable");
700 
701                 pdata->slot[slot_id].wp_pin =
702                         of_get_named_gpio(cnp, "wp-gpios", 0);
703         }
704 
705         return pdata;
706 }
707 #else /* CONFIG_OF */
708 static inline struct mci_platform_data*
709 atmci_of_init(struct platform_device *dev)
710 {
711         return ERR_PTR(-EINVAL);
712 }
713 #endif
714 
715 static inline unsigned int atmci_get_version(struct atmel_mci *host)
716 {
717         return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
718 }
719 
720 /*
721  * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
722  * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
723  * With version 0x600, we need to convert them as: 1 -> 0, 2 -> 1, 4 -> 2,
724  * 8 -> 3, 16 -> 4.
725  *
726  * This can be done by finding most significant bit set.
727  */
728 static inline unsigned int atmci_convert_chksize(struct atmel_mci *host,
729                                                  unsigned int maxburst)
730 {
731         unsigned int version = atmci_get_version(host);
732         unsigned int offset = 2;
733 
734         if (version >= 0x600)
735                 offset = 1;
736 
737         if (maxburst > 1)
738                 return fls(maxburst) - offset;
739         else
740                 return 0;
741 }
742 
743 static void atmci_timeout_timer(unsigned long data)
744 {
745         struct atmel_mci *host;
746 
747         host = (struct atmel_mci *)data;
748 
749         dev_dbg(&host->pdev->dev, "software timeout\n");
750 
751         if (host->mrq->cmd->data) {
752                 host->mrq->cmd->data->error = -ETIMEDOUT;
753                 host->data = NULL;
754                 /*
755                  * With some SDIO modules, sometimes DMA transfer hangs. If
756                  * stop_transfer() is not called then the DMA request is not
757                  * removed, following ones are queued and never computed.
758                  */
759                 if (host->state == STATE_DATA_XFER)
760                         host->stop_transfer(host);
761         } else {
762                 host->mrq->cmd->error = -ETIMEDOUT;
763                 host->cmd = NULL;
764         }
765         host->need_reset = 1;
766         host->state = STATE_END_REQUEST;
767         smp_wmb();
768         tasklet_schedule(&host->tasklet);
769 }
770 
771 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
772                                         unsigned int ns)
773 {
774         /*
775          * It is easier here to use us instead of ns for the timeout,
776          * it prevents from overflows during calculation.
777          */
778         unsigned int us = DIV_ROUND_UP(ns, 1000);
779 
780         /* Maximum clock frequency is host->bus_hz/2 */
781         return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
782 }
783 
784 static void atmci_set_timeout(struct atmel_mci *host,
785                 struct atmel_mci_slot *slot, struct mmc_data *data)
786 {
787         static unsigned dtomul_to_shift[] = {
788                 0, 4, 7, 8, 10, 12, 16, 20
789         };
790         unsigned        timeout;
791         unsigned        dtocyc;
792         unsigned        dtomul;
793 
794         timeout = atmci_ns_to_clocks(host, data->timeout_ns)
795                 + data->timeout_clks;
796 
797         for (dtomul = 0; dtomul < 8; dtomul++) {
798                 unsigned shift = dtomul_to_shift[dtomul];
799                 dtocyc = (timeout + (1 << shift) - 1) >> shift;
800                 if (dtocyc < 15)
801                         break;
802         }
803 
804         if (dtomul >= 8) {
805                 dtomul = 7;
806                 dtocyc = 15;
807         }
808 
809         dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
810                         dtocyc << dtomul_to_shift[dtomul]);
811         atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
812 }
813 
814 /*
815  * Return mask with command flags to be enabled for this command.
816  */
817 static u32 atmci_prepare_command(struct mmc_host *mmc,
818                                  struct mmc_command *cmd)
819 {
820         struct mmc_data *data;
821         u32             cmdr;
822 
823         cmd->error = -EINPROGRESS;
824 
825         cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
826 
827         if (cmd->flags & MMC_RSP_PRESENT) {
828                 if (cmd->flags & MMC_RSP_136)
829                         cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
830                 else
831                         cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
832         }
833 
834         /*
835          * This should really be MAXLAT_5 for CMD2 and ACMD41, but
836          * it's too difficult to determine whether this is an ACMD or
837          * not. Better make it 64.
838          */
839         cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
840 
841         if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
842                 cmdr |= ATMCI_CMDR_OPDCMD;
843 
844         data = cmd->data;
845         if (data) {
846                 cmdr |= ATMCI_CMDR_START_XFER;
847 
848                 if (cmd->opcode == SD_IO_RW_EXTENDED) {
849                         cmdr |= ATMCI_CMDR_SDIO_BLOCK;
850                 } else {
851                         if (data->blocks > 1)
852                                 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
853                         else
854                                 cmdr |= ATMCI_CMDR_BLOCK;
855                 }
856 
857                 if (data->flags & MMC_DATA_READ)
858                         cmdr |= ATMCI_CMDR_TRDIR_READ;
859         }
860 
861         return cmdr;
862 }
863 
864 static void atmci_send_command(struct atmel_mci *host,
865                 struct mmc_command *cmd, u32 cmd_flags)
866 {
867         WARN_ON(host->cmd);
868         host->cmd = cmd;
869 
870         dev_vdbg(&host->pdev->dev,
871                         "start command: ARGR=0x%08x CMDR=0x%08x\n",
872                         cmd->arg, cmd_flags);
873 
874         atmci_writel(host, ATMCI_ARGR, cmd->arg);
875         atmci_writel(host, ATMCI_CMDR, cmd_flags);
876 }
877 
878 static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
879 {
880         dev_dbg(&host->pdev->dev, "send stop command\n");
881         atmci_send_command(host, data->stop, host->stop_cmdr);
882         atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
883 }
884 
885 /*
886  * Configure given PDC buffer taking care of alignement issues.
887  * Update host->data_size and host->sg.
888  */
889 static void atmci_pdc_set_single_buf(struct atmel_mci *host,
890         enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
891 {
892         u32 pointer_reg, counter_reg;
893         unsigned int buf_size;
894 
895         if (dir == XFER_RECEIVE) {
896                 pointer_reg = ATMEL_PDC_RPR;
897                 counter_reg = ATMEL_PDC_RCR;
898         } else {
899                 pointer_reg = ATMEL_PDC_TPR;
900                 counter_reg = ATMEL_PDC_TCR;
901         }
902 
903         if (buf_nb == PDC_SECOND_BUF) {
904                 pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
905                 counter_reg += ATMEL_PDC_SCND_BUF_OFF;
906         }
907 
908         if (!host->caps.has_rwproof) {
909                 buf_size = host->buf_size;
910                 atmci_writel(host, pointer_reg, host->buf_phys_addr);
911         } else {
912                 buf_size = sg_dma_len(host->sg);
913                 atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
914         }
915 
916         if (host->data_size <= buf_size) {
917                 if (host->data_size & 0x3) {
918                         /* If size is different from modulo 4, transfer bytes */
919                         atmci_writel(host, counter_reg, host->data_size);
920                         atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
921                 } else {
922                         /* Else transfer 32-bits words */
923                         atmci_writel(host, counter_reg, host->data_size / 4);
924                 }
925                 host->data_size = 0;
926         } else {
927                 /* We assume the size of a page is 32-bits aligned */
928                 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
929                 host->data_size -= sg_dma_len(host->sg);
930                 if (host->data_size)
931                         host->sg = sg_next(host->sg);
932         }
933 }
934 
935 /*
936  * Configure PDC buffer according to the data size ie configuring one or two
937  * buffers. Don't use this function if you want to configure only the second
938  * buffer. In this case, use atmci_pdc_set_single_buf.
939  */
940 static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
941 {
942         atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
943         if (host->data_size)
944                 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
945 }
946 
947 /*
948  * Unmap sg lists, called when transfer is finished.
949  */
950 static void atmci_pdc_cleanup(struct atmel_mci *host)
951 {
952         struct mmc_data         *data = host->data;
953 
954         if (data)
955                 dma_unmap_sg(&host->pdev->dev,
956                                 data->sg, data->sg_len,
957                                 ((data->flags & MMC_DATA_WRITE)
958                                  ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
959 }
960 
961 /*
962  * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
963  * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
964  * interrupt needed for both transfer directions.
965  */
966 static void atmci_pdc_complete(struct atmel_mci *host)
967 {
968         int transfer_size = host->data->blocks * host->data->blksz;
969         int i;
970 
971         atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
972 
973         if ((!host->caps.has_rwproof)
974             && (host->data->flags & MMC_DATA_READ)) {
975                 if (host->caps.has_bad_data_ordering)
976                         for (i = 0; i < transfer_size; i++)
977                                 host->buffer[i] = swab32(host->buffer[i]);
978                 sg_copy_from_buffer(host->data->sg, host->data->sg_len,
979                                     host->buffer, transfer_size);
980         }
981 
982         atmci_pdc_cleanup(host);
983 
984         dev_dbg(&host->pdev->dev, "(%s) set pending xfer complete\n", __func__);
985         atmci_set_pending(host, EVENT_XFER_COMPLETE);
986         tasklet_schedule(&host->tasklet);
987 }
988 
989 static void atmci_dma_cleanup(struct atmel_mci *host)
990 {
991         struct mmc_data                 *data = host->data;
992 
993         if (data)
994                 dma_unmap_sg(host->dma.chan->device->dev,
995                                 data->sg, data->sg_len,
996                                 ((data->flags & MMC_DATA_WRITE)
997                                  ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
998 }
999 
1000 /*
1001  * This function is called by the DMA driver from tasklet context.
1002  */
1003 static void atmci_dma_complete(void *arg)
1004 {
1005         struct atmel_mci        *host = arg;
1006         struct mmc_data         *data = host->data;
1007 
1008         dev_vdbg(&host->pdev->dev, "DMA complete\n");
1009 
1010         if (host->caps.has_dma_conf_reg)
1011                 /* Disable DMA hardware handshaking on MCI */
1012                 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
1013 
1014         atmci_dma_cleanup(host);
1015 
1016         /*
1017          * If the card was removed, data will be NULL. No point trying
1018          * to send the stop command or waiting for NBUSY in this case.
1019          */
1020         if (data) {
1021                 dev_dbg(&host->pdev->dev,
1022                         "(%s) set pending xfer complete\n", __func__);
1023                 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1024                 tasklet_schedule(&host->tasklet);
1025 
1026                 /*
1027                  * Regardless of what the documentation says, we have
1028                  * to wait for NOTBUSY even after block read
1029                  * operations.
1030                  *
1031                  * When the DMA transfer is complete, the controller
1032                  * may still be reading the CRC from the card, i.e.
1033                  * the data transfer is still in progress and we
1034                  * haven't seen all the potential error bits yet.
1035                  *
1036                  * The interrupt handler will schedule a different
1037                  * tasklet to finish things up when the data transfer
1038                  * is completely done.
1039                  *
1040                  * We may not complete the mmc request here anyway
1041                  * because the mmc layer may call back and cause us to
1042                  * violate the "don't submit new operations from the
1043                  * completion callback" rule of the dma engine
1044                  * framework.
1045                  */
1046                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1047         }
1048 }
1049 
1050 /*
1051  * Returns a mask of interrupt flags to be enabled after the whole
1052  * request has been prepared.
1053  */
1054 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
1055 {
1056         u32 iflags;
1057 
1058         data->error = -EINPROGRESS;
1059 
1060         host->sg = data->sg;
1061         host->sg_len = data->sg_len;
1062         host->data = data;
1063         host->data_chan = NULL;
1064 
1065         iflags = ATMCI_DATA_ERROR_FLAGS;
1066 
1067         /*
1068          * Errata: MMC data write operation with less than 12
1069          * bytes is impossible.
1070          *
1071          * Errata: MCI Transmit Data Register (TDR) FIFO
1072          * corruption when length is not multiple of 4.
1073          */
1074         if (data->blocks * data->blksz < 12
1075                         || (data->blocks * data->blksz) & 3)
1076                 host->need_reset = true;
1077 
1078         host->pio_offset = 0;
1079         if (data->flags & MMC_DATA_READ)
1080                 iflags |= ATMCI_RXRDY;
1081         else
1082                 iflags |= ATMCI_TXRDY;
1083 
1084         return iflags;
1085 }
1086 
1087 /*
1088  * Set interrupt flags and set block length into the MCI mode register even
1089  * if this value is also accessible in the MCI block register. It seems to be
1090  * necessary before the High Speed MCI version. It also map sg and configure
1091  * PDC registers.
1092  */
1093 static u32
1094 atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1095 {
1096         u32 iflags, tmp;
1097         unsigned int sg_len;
1098         enum dma_data_direction dir;
1099         int i;
1100 
1101         data->error = -EINPROGRESS;
1102 
1103         host->data = data;
1104         host->sg = data->sg;
1105         iflags = ATMCI_DATA_ERROR_FLAGS;
1106 
1107         /* Enable pdc mode */
1108         atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
1109 
1110         if (data->flags & MMC_DATA_READ) {
1111                 dir = DMA_FROM_DEVICE;
1112                 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
1113         } else {
1114                 dir = DMA_TO_DEVICE;
1115                 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
1116         }
1117 
1118         /* Set BLKLEN */
1119         tmp = atmci_readl(host, ATMCI_MR);
1120         tmp &= 0x0000ffff;
1121         tmp |= ATMCI_BLKLEN(data->blksz);
1122         atmci_writel(host, ATMCI_MR, tmp);
1123 
1124         /* Configure PDC */
1125         host->data_size = data->blocks * data->blksz;
1126         sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir);
1127 
1128         if ((!host->caps.has_rwproof)
1129             && (host->data->flags & MMC_DATA_WRITE)) {
1130                 sg_copy_to_buffer(host->data->sg, host->data->sg_len,
1131                                   host->buffer, host->data_size);
1132                 if (host->caps.has_bad_data_ordering)
1133                         for (i = 0; i < host->data_size; i++)
1134                                 host->buffer[i] = swab32(host->buffer[i]);
1135         }
1136 
1137         if (host->data_size)
1138                 atmci_pdc_set_both_buf(host,
1139                         ((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT));
1140 
1141         return iflags;
1142 }
1143 
1144 static u32
1145 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
1146 {
1147         struct dma_chan                 *chan;
1148         struct dma_async_tx_descriptor  *desc;
1149         struct scatterlist              *sg;
1150         unsigned int                    i;
1151         enum dma_data_direction         direction;
1152         enum dma_transfer_direction     slave_dirn;
1153         unsigned int                    sglen;
1154         u32                             maxburst;
1155         u32 iflags;
1156 
1157         data->error = -EINPROGRESS;
1158 
1159         WARN_ON(host->data);
1160         host->sg = NULL;
1161         host->data = data;
1162 
1163         iflags = ATMCI_DATA_ERROR_FLAGS;
1164 
1165         /*
1166          * We don't do DMA on "complex" transfers, i.e. with
1167          * non-word-aligned buffers or lengths. Also, we don't bother
1168          * with all the DMA setup overhead for short transfers.
1169          */
1170         if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
1171                 return atmci_prepare_data(host, data);
1172         if (data->blksz & 3)
1173                 return atmci_prepare_data(host, data);
1174 
1175         for_each_sg(data->sg, sg, data->sg_len, i) {
1176                 if (sg->offset & 3 || sg->length & 3)
1177                         return atmci_prepare_data(host, data);
1178         }
1179 
1180         /* If we don't have a channel, we can't do DMA */
1181         chan = host->dma.chan;
1182         if (chan)
1183                 host->data_chan = chan;
1184 
1185         if (!chan)
1186                 return -ENODEV;
1187 
1188         if (data->flags & MMC_DATA_READ) {
1189                 direction = DMA_FROM_DEVICE;
1190                 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
1191                 maxburst = atmci_convert_chksize(host,
1192                                                  host->dma_conf.src_maxburst);
1193         } else {
1194                 direction = DMA_TO_DEVICE;
1195                 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
1196                 maxburst = atmci_convert_chksize(host,
1197                                                  host->dma_conf.dst_maxburst);
1198         }
1199 
1200         if (host->caps.has_dma_conf_reg)
1201                 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) |
1202                         ATMCI_DMAEN);
1203 
1204         sglen = dma_map_sg(chan->device->dev, data->sg,
1205                         data->sg_len, direction);
1206 
1207         dmaengine_slave_config(chan, &host->dma_conf);
1208         desc = dmaengine_prep_slave_sg(chan,
1209                         data->sg, sglen, slave_dirn,
1210                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1211         if (!desc)
1212                 goto unmap_exit;
1213 
1214         host->dma.data_desc = desc;
1215         desc->callback = atmci_dma_complete;
1216         desc->callback_param = host;
1217 
1218         return iflags;
1219 unmap_exit:
1220         dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction);
1221         return -ENOMEM;
1222 }
1223 
1224 static void
1225 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
1226 {
1227         return;
1228 }
1229 
1230 /*
1231  * Start PDC according to transfer direction.
1232  */
1233 static void
1234 atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1235 {
1236         if (data->flags & MMC_DATA_READ)
1237                 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1238         else
1239                 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1240 }
1241 
1242 static void
1243 atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
1244 {
1245         struct dma_chan                 *chan = host->data_chan;
1246         struct dma_async_tx_descriptor  *desc = host->dma.data_desc;
1247 
1248         if (chan) {
1249                 dmaengine_submit(desc);
1250                 dma_async_issue_pending(chan);
1251         }
1252 }
1253 
1254 static void atmci_stop_transfer(struct atmel_mci *host)
1255 {
1256         dev_dbg(&host->pdev->dev,
1257                 "(%s) set pending xfer complete\n", __func__);
1258         atmci_set_pending(host, EVENT_XFER_COMPLETE);
1259         atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1260 }
1261 
1262 /*
1263  * Stop data transfer because error(s) occurred.
1264  */
1265 static void atmci_stop_transfer_pdc(struct atmel_mci *host)
1266 {
1267         atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
1268 }
1269 
1270 static void atmci_stop_transfer_dma(struct atmel_mci *host)
1271 {
1272         struct dma_chan *chan = host->data_chan;
1273 
1274         if (chan) {
1275                 dmaengine_terminate_all(chan);
1276                 atmci_dma_cleanup(host);
1277         } else {
1278                 /* Data transfer was stopped by the interrupt handler */
1279                 dev_dbg(&host->pdev->dev,
1280                         "(%s) set pending xfer complete\n", __func__);
1281                 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1282                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1283         }
1284 }
1285 
1286 /*
1287  * Start a request: prepare data if needed, prepare the command and activate
1288  * interrupts.
1289  */
1290 static void atmci_start_request(struct atmel_mci *host,
1291                 struct atmel_mci_slot *slot)
1292 {
1293         struct mmc_request      *mrq;
1294         struct mmc_command      *cmd;
1295         struct mmc_data         *data;
1296         u32                     iflags;
1297         u32                     cmdflags;
1298 
1299         mrq = slot->mrq;
1300         host->cur_slot = slot;
1301         host->mrq = mrq;
1302 
1303         host->pending_events = 0;
1304         host->completed_events = 0;
1305         host->cmd_status = 0;
1306         host->data_status = 0;
1307 
1308         dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode);
1309 
1310         if (host->need_reset || host->caps.need_reset_after_xfer) {
1311                 iflags = atmci_readl(host, ATMCI_IMR);
1312                 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
1313                 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1314                 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1315                 atmci_writel(host, ATMCI_MR, host->mode_reg);
1316                 if (host->caps.has_cfg_reg)
1317                         atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1318                 atmci_writel(host, ATMCI_IER, iflags);
1319                 host->need_reset = false;
1320         }
1321         atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
1322 
1323         iflags = atmci_readl(host, ATMCI_IMR);
1324         if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1325                 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
1326                                 iflags);
1327 
1328         if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
1329                 /* Send init sequence (74 clock cycles) */
1330                 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
1331                 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
1332                         cpu_relax();
1333         }
1334         iflags = 0;
1335         data = mrq->data;
1336         if (data) {
1337                 atmci_set_timeout(host, slot, data);
1338 
1339                 /* Must set block count/size before sending command */
1340                 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
1341                                 | ATMCI_BLKLEN(data->blksz));
1342                 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
1343                         ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
1344 
1345                 iflags |= host->prepare_data(host, data);
1346         }
1347 
1348         iflags |= ATMCI_CMDRDY;
1349         cmd = mrq->cmd;
1350         cmdflags = atmci_prepare_command(slot->mmc, cmd);
1351 
1352         /*
1353          * DMA transfer should be started before sending the command to avoid
1354          * unexpected errors especially for read operations in SDIO mode.
1355          * Unfortunately, in PDC mode, command has to be sent before starting
1356          * the transfer.
1357          */
1358         if (host->submit_data != &atmci_submit_data_dma)
1359                 atmci_send_command(host, cmd, cmdflags);
1360 
1361         if (data)
1362                 host->submit_data(host, data);
1363 
1364         if (host->submit_data == &atmci_submit_data_dma)
1365                 atmci_send_command(host, cmd, cmdflags);
1366 
1367         if (mrq->stop) {
1368                 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
1369                 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
1370                 if (!(data->flags & MMC_DATA_WRITE))
1371                         host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
1372                 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
1373         }
1374 
1375         /*
1376          * We could have enabled interrupts earlier, but I suspect
1377          * that would open up a nice can of interesting race
1378          * conditions (e.g. command and data complete, but stop not
1379          * prepared yet.)
1380          */
1381         atmci_writel(host, ATMCI_IER, iflags);
1382 
1383         mod_timer(&host->timer, jiffies +  msecs_to_jiffies(2000));
1384 }
1385 
1386 static void atmci_queue_request(struct atmel_mci *host,
1387                 struct atmel_mci_slot *slot, struct mmc_request *mrq)
1388 {
1389         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1390                         host->state);
1391 
1392         spin_lock_bh(&host->lock);
1393         slot->mrq = mrq;
1394         if (host->state == STATE_IDLE) {
1395                 host->state = STATE_SENDING_CMD;
1396                 atmci_start_request(host, slot);
1397         } else {
1398                 dev_dbg(&host->pdev->dev, "queue request\n");
1399                 list_add_tail(&slot->queue_node, &host->queue);
1400         }
1401         spin_unlock_bh(&host->lock);
1402 }
1403 
1404 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1405 {
1406         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1407         struct atmel_mci        *host = slot->host;
1408         struct mmc_data         *data;
1409 
1410         WARN_ON(slot->mrq);
1411         dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode);
1412 
1413         /*
1414          * We may "know" the card is gone even though there's still an
1415          * electrical connection. If so, we really need to communicate
1416          * this to the MMC core since there won't be any more
1417          * interrupts as the card is completely removed. Otherwise,
1418          * the MMC core might believe the card is still there even
1419          * though the card was just removed very slowly.
1420          */
1421         if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1422                 mrq->cmd->error = -ENOMEDIUM;
1423                 mmc_request_done(mmc, mrq);
1424                 return;
1425         }
1426 
1427         /* We don't support multiple blocks of weird lengths. */
1428         data = mrq->data;
1429         if (data && data->blocks > 1 && data->blksz & 3) {
1430                 mrq->cmd->error = -EINVAL;
1431                 mmc_request_done(mmc, mrq);
1432         }
1433 
1434         atmci_queue_request(host, slot, mrq);
1435 }
1436 
1437 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1438 {
1439         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1440         struct atmel_mci        *host = slot->host;
1441         unsigned int            i;
1442 
1443         slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
1444         switch (ios->bus_width) {
1445         case MMC_BUS_WIDTH_1:
1446                 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
1447                 break;
1448         case MMC_BUS_WIDTH_4:
1449                 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
1450                 break;
1451         }
1452 
1453         if (ios->clock) {
1454                 unsigned int clock_min = ~0U;
1455                 int clkdiv;
1456 
1457                 spin_lock_bh(&host->lock);
1458                 if (!host->mode_reg) {
1459                         atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1460                         atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1461                         if (host->caps.has_cfg_reg)
1462                                 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1463                 }
1464 
1465                 /*
1466                  * Use mirror of ios->clock to prevent race with mmc
1467                  * core ios update when finding the minimum.
1468                  */
1469                 slot->clock = ios->clock;
1470                 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1471                         if (host->slot[i] && host->slot[i]->clock
1472                                         && host->slot[i]->clock < clock_min)
1473                                 clock_min = host->slot[i]->clock;
1474                 }
1475 
1476                 /* Calculate clock divider */
1477                 if (host->caps.has_odd_clk_div) {
1478                         clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
1479                         if (clkdiv < 0) {
1480                                 dev_warn(&mmc->class_dev,
1481                                          "clock %u too fast; using %lu\n",
1482                                          clock_min, host->bus_hz / 2);
1483                                 clkdiv = 0;
1484                         } else if (clkdiv > 511) {
1485                                 dev_warn(&mmc->class_dev,
1486                                          "clock %u too slow; using %lu\n",
1487                                          clock_min, host->bus_hz / (511 + 2));
1488                                 clkdiv = 511;
1489                         }
1490                         host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
1491                                          | ATMCI_MR_CLKODD(clkdiv & 1);
1492                 } else {
1493                         clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
1494                         if (clkdiv > 255) {
1495                                 dev_warn(&mmc->class_dev,
1496                                          "clock %u too slow; using %lu\n",
1497                                          clock_min, host->bus_hz / (2 * 256));
1498                                 clkdiv = 255;
1499                         }
1500                         host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
1501                 }
1502 
1503                 /*
1504                  * WRPROOF and RDPROOF prevent overruns/underruns by
1505                  * stopping the clock when the FIFO is full/empty.
1506                  * This state is not expected to last for long.
1507                  */
1508                 if (host->caps.has_rwproof)
1509                         host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
1510 
1511                 if (host->caps.has_cfg_reg) {
1512                         /* setup High Speed mode in relation with card capacity */
1513                         if (ios->timing == MMC_TIMING_SD_HS)
1514                                 host->cfg_reg |= ATMCI_CFG_HSMODE;
1515                         else
1516                                 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
1517                 }
1518 
1519                 if (list_empty(&host->queue)) {
1520                         atmci_writel(host, ATMCI_MR, host->mode_reg);
1521                         if (host->caps.has_cfg_reg)
1522                                 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1523                 } else {
1524                         host->need_clock_update = true;
1525                 }
1526 
1527                 spin_unlock_bh(&host->lock);
1528         } else {
1529                 bool any_slot_active = false;
1530 
1531                 spin_lock_bh(&host->lock);
1532                 slot->clock = 0;
1533                 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1534                         if (host->slot[i] && host->slot[i]->clock) {
1535                                 any_slot_active = true;
1536                                 break;
1537                         }
1538                 }
1539                 if (!any_slot_active) {
1540                         atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
1541                         if (host->mode_reg) {
1542                                 atmci_readl(host, ATMCI_MR);
1543                         }
1544                         host->mode_reg = 0;
1545                 }
1546                 spin_unlock_bh(&host->lock);
1547         }
1548 
1549         switch (ios->power_mode) {
1550         case MMC_POWER_OFF:
1551                 if (!IS_ERR(mmc->supply.vmmc))
1552                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1553                 break;
1554         case MMC_POWER_UP:
1555                 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1556                 if (!IS_ERR(mmc->supply.vmmc))
1557                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1558                 break;
1559         default:
1560                 /*
1561                  * TODO: None of the currently available AVR32-based
1562                  * boards allow MMC power to be turned off. Implement
1563                  * power control when this can be tested properly.
1564                  *
1565                  * We also need to hook this into the clock management
1566                  * somehow so that newly inserted cards aren't
1567                  * subjected to a fast clock before we have a chance
1568                  * to figure out what the maximum rate is. Currently,
1569                  * there's no way to avoid this, and there never will
1570                  * be for boards that don't support power control.
1571                  */
1572                 break;
1573         }
1574 
1575 }
1576 
1577 static int atmci_get_ro(struct mmc_host *mmc)
1578 {
1579         int                     read_only = -ENOSYS;
1580         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1581 
1582         if (gpio_is_valid(slot->wp_pin)) {
1583                 read_only = gpio_get_value(slot->wp_pin);
1584                 dev_dbg(&mmc->class_dev, "card is %s\n",
1585                                 read_only ? "read-only" : "read-write");
1586         }
1587 
1588         return read_only;
1589 }
1590 
1591 static int atmci_get_cd(struct mmc_host *mmc)
1592 {
1593         int                     present = -ENOSYS;
1594         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1595 
1596         if (gpio_is_valid(slot->detect_pin)) {
1597                 present = !(gpio_get_value(slot->detect_pin) ^
1598                             slot->detect_is_active_high);
1599                 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1600                                 present ? "" : "not ");
1601         }
1602 
1603         return present;
1604 }
1605 
1606 static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1607 {
1608         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1609         struct atmel_mci        *host = slot->host;
1610 
1611         if (enable)
1612                 atmci_writel(host, ATMCI_IER, slot->sdio_irq);
1613         else
1614                 atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
1615 }
1616 
1617 static const struct mmc_host_ops atmci_ops = {
1618         .request        = atmci_request,
1619         .set_ios        = atmci_set_ios,
1620         .get_ro         = atmci_get_ro,
1621         .get_cd         = atmci_get_cd,
1622         .enable_sdio_irq = atmci_enable_sdio_irq,
1623 };
1624 
1625 /* Called with host->lock held */
1626 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1627         __releases(&host->lock)
1628         __acquires(&host->lock)
1629 {
1630         struct atmel_mci_slot   *slot = NULL;
1631         struct mmc_host         *prev_mmc = host->cur_slot->mmc;
1632 
1633         WARN_ON(host->cmd || host->data);
1634 
1635         /*
1636          * Update the MMC clock rate if necessary. This may be
1637          * necessary if set_ios() is called when a different slot is
1638          * busy transferring data.
1639          */
1640         if (host->need_clock_update) {
1641                 atmci_writel(host, ATMCI_MR, host->mode_reg);
1642                 if (host->caps.has_cfg_reg)
1643                         atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1644         }
1645 
1646         host->cur_slot->mrq = NULL;
1647         host->mrq = NULL;
1648         if (!list_empty(&host->queue)) {
1649                 slot = list_entry(host->queue.next,
1650                                 struct atmel_mci_slot, queue_node);
1651                 list_del(&slot->queue_node);
1652                 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1653                                 mmc_hostname(slot->mmc));
1654                 host->state = STATE_SENDING_CMD;
1655                 atmci_start_request(host, slot);
1656         } else {
1657                 dev_vdbg(&host->pdev->dev, "list empty\n");
1658                 host->state = STATE_IDLE;
1659         }
1660 
1661         del_timer(&host->timer);
1662 
1663         spin_unlock(&host->lock);
1664         mmc_request_done(prev_mmc, mrq);
1665         spin_lock(&host->lock);
1666 }
1667 
1668 static void atmci_command_complete(struct atmel_mci *host,
1669                         struct mmc_command *cmd)
1670 {
1671         u32             status = host->cmd_status;
1672 
1673         /* Read the response from the card (up to 16 bytes) */
1674         cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1675         cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1676         cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1677         cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
1678 
1679         if (status & ATMCI_RTOE)
1680                 cmd->error = -ETIMEDOUT;
1681         else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
1682                 cmd->error = -EILSEQ;
1683         else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
1684                 cmd->error = -EIO;
1685         else if (host->mrq->data && (host->mrq->data->blksz & 3)) {
1686                 if (host->caps.need_blksz_mul_4) {
1687                         cmd->error = -EINVAL;
1688                         host->need_reset = 1;
1689                 }
1690         } else
1691                 cmd->error = 0;
1692 }
1693 
1694 static void atmci_detect_change(unsigned long data)
1695 {
1696         struct atmel_mci_slot   *slot = (struct atmel_mci_slot *)data;
1697         bool                    present;
1698         bool                    present_old;
1699 
1700         /*
1701          * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1702          * freeing the interrupt. We must not re-enable the interrupt
1703          * if it has been freed, and if we're shutting down, it
1704          * doesn't really matter whether the card is present or not.
1705          */
1706         smp_rmb();
1707         if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1708                 return;
1709 
1710         enable_irq(gpio_to_irq(slot->detect_pin));
1711         present = !(gpio_get_value(slot->detect_pin) ^
1712                     slot->detect_is_active_high);
1713         present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1714 
1715         dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1716                         present, present_old);
1717 
1718         if (present != present_old) {
1719                 struct atmel_mci        *host = slot->host;
1720                 struct mmc_request      *mrq;
1721 
1722                 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1723                         present ? "inserted" : "removed");
1724 
1725                 spin_lock(&host->lock);
1726 
1727                 if (!present)
1728                         clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1729                 else
1730                         set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1731 
1732                 /* Clean up queue if present */
1733                 mrq = slot->mrq;
1734                 if (mrq) {
1735                         if (mrq == host->mrq) {
1736                                 /*
1737                                  * Reset controller to terminate any ongoing
1738                                  * commands or data transfers.
1739                                  */
1740                                 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1741                                 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1742                                 atmci_writel(host, ATMCI_MR, host->mode_reg);
1743                                 if (host->caps.has_cfg_reg)
1744                                         atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1745 
1746                                 host->data = NULL;
1747                                 host->cmd = NULL;
1748 
1749                                 switch (host->state) {
1750                                 case STATE_IDLE:
1751                                         break;
1752                                 case STATE_SENDING_CMD:
1753                                         mrq->cmd->error = -ENOMEDIUM;
1754                                         if (mrq->data)
1755                                                 host->stop_transfer(host);
1756                                         break;
1757                                 case STATE_DATA_XFER:
1758                                         mrq->data->error = -ENOMEDIUM;
1759                                         host->stop_transfer(host);
1760                                         break;
1761                                 case STATE_WAITING_NOTBUSY:
1762                                         mrq->data->error = -ENOMEDIUM;
1763                                         break;
1764                                 case STATE_SENDING_STOP:
1765                                         mrq->stop->error = -ENOMEDIUM;
1766                                         break;
1767                                 case STATE_END_REQUEST:
1768                                         break;
1769                                 }
1770 
1771                                 atmci_request_end(host, mrq);
1772                         } else {
1773                                 list_del(&slot->queue_node);
1774                                 mrq->cmd->error = -ENOMEDIUM;
1775                                 if (mrq->data)
1776                                         mrq->data->error = -ENOMEDIUM;
1777                                 if (mrq->stop)
1778                                         mrq->stop->error = -ENOMEDIUM;
1779 
1780                                 spin_unlock(&host->lock);
1781                                 mmc_request_done(slot->mmc, mrq);
1782                                 spin_lock(&host->lock);
1783                         }
1784                 }
1785                 spin_unlock(&host->lock);
1786 
1787                 mmc_detect_change(slot->mmc, 0);
1788         }
1789 }
1790 
1791 static void atmci_tasklet_func(unsigned long priv)
1792 {
1793         struct atmel_mci        *host = (struct atmel_mci *)priv;
1794         struct mmc_request      *mrq = host->mrq;
1795         struct mmc_data         *data = host->data;
1796         enum atmel_mci_state    state = host->state;
1797         enum atmel_mci_state    prev_state;
1798         u32                     status;
1799 
1800         spin_lock(&host->lock);
1801 
1802         state = host->state;
1803 
1804         dev_vdbg(&host->pdev->dev,
1805                 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1806                 state, host->pending_events, host->completed_events,
1807                 atmci_readl(host, ATMCI_IMR));
1808 
1809         do {
1810                 prev_state = state;
1811                 dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state);
1812 
1813                 switch (state) {
1814                 case STATE_IDLE:
1815                         break;
1816 
1817                 case STATE_SENDING_CMD:
1818                         /*
1819                          * Command has been sent, we are waiting for command
1820                          * ready. Then we have three next states possible:
1821                          * END_REQUEST by default, WAITING_NOTBUSY if it's a
1822                          * command needing it or DATA_XFER if there is data.
1823                          */
1824                         dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1825                         if (!atmci_test_and_clear_pending(host,
1826                                                 EVENT_CMD_RDY))
1827                                 break;
1828 
1829                         dev_dbg(&host->pdev->dev, "set completed cmd ready\n");
1830                         host->cmd = NULL;
1831                         atmci_set_completed(host, EVENT_CMD_RDY);
1832                         atmci_command_complete(host, mrq->cmd);
1833                         if (mrq->data) {
1834                                 dev_dbg(&host->pdev->dev,
1835                                         "command with data transfer");
1836                                 /*
1837                                  * If there is a command error don't start
1838                                  * data transfer.
1839                                  */
1840                                 if (mrq->cmd->error) {
1841                                         host->stop_transfer(host);
1842                                         host->data = NULL;
1843                                         atmci_writel(host, ATMCI_IDR,
1844                                                      ATMCI_TXRDY | ATMCI_RXRDY
1845                                                      | ATMCI_DATA_ERROR_FLAGS);
1846                                         state = STATE_END_REQUEST;
1847                                 } else
1848                                         state = STATE_DATA_XFER;
1849                         } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) {
1850                                 dev_dbg(&host->pdev->dev,
1851                                         "command response need waiting notbusy");
1852                                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1853                                 state = STATE_WAITING_NOTBUSY;
1854                         } else
1855                                 state = STATE_END_REQUEST;
1856 
1857                         break;
1858 
1859                 case STATE_DATA_XFER:
1860                         if (atmci_test_and_clear_pending(host,
1861                                                 EVENT_DATA_ERROR)) {
1862                                 dev_dbg(&host->pdev->dev, "set completed data error\n");
1863                                 atmci_set_completed(host, EVENT_DATA_ERROR);
1864                                 state = STATE_END_REQUEST;
1865                                 break;
1866                         }
1867 
1868                         /*
1869                          * A data transfer is in progress. The event expected
1870                          * to move to the next state depends of data transfer
1871                          * type (PDC or DMA). Once transfer done we can move
1872                          * to the next step which is WAITING_NOTBUSY in write
1873                          * case and directly SENDING_STOP in read case.
1874                          */
1875                         dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n");
1876                         if (!atmci_test_and_clear_pending(host,
1877                                                 EVENT_XFER_COMPLETE))
1878                                 break;
1879 
1880                         dev_dbg(&host->pdev->dev,
1881                                 "(%s) set completed xfer complete\n",
1882                                 __func__);
1883                         atmci_set_completed(host, EVENT_XFER_COMPLETE);
1884 
1885                         if (host->caps.need_notbusy_for_read_ops ||
1886                            (host->data->flags & MMC_DATA_WRITE)) {
1887                                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1888                                 state = STATE_WAITING_NOTBUSY;
1889                         } else if (host->mrq->stop) {
1890                                 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
1891                                 atmci_send_stop_cmd(host, data);
1892                                 state = STATE_SENDING_STOP;
1893                         } else {
1894                                 host->data = NULL;
1895                                 data->bytes_xfered = data->blocks * data->blksz;
1896                                 data->error = 0;
1897                                 state = STATE_END_REQUEST;
1898                         }
1899                         break;
1900 
1901                 case STATE_WAITING_NOTBUSY:
1902                         /*
1903                          * We can be in the state for two reasons: a command
1904                          * requiring waiting not busy signal (stop command
1905                          * included) or a write operation. In the latest case,
1906                          * we need to send a stop command.
1907                          */
1908                         dev_dbg(&host->pdev->dev, "FSM: not busy?\n");
1909                         if (!atmci_test_and_clear_pending(host,
1910                                                 EVENT_NOTBUSY))
1911                                 break;
1912 
1913                         dev_dbg(&host->pdev->dev, "set completed not busy\n");
1914                         atmci_set_completed(host, EVENT_NOTBUSY);
1915 
1916                         if (host->data) {
1917                                 /*
1918                                  * For some commands such as CMD53, even if
1919                                  * there is data transfer, there is no stop
1920                                  * command to send.
1921                                  */
1922                                 if (host->mrq->stop) {
1923                                         atmci_writel(host, ATMCI_IER,
1924                                                      ATMCI_CMDRDY);
1925                                         atmci_send_stop_cmd(host, data);
1926                                         state = STATE_SENDING_STOP;
1927                                 } else {
1928                                         host->data = NULL;
1929                                         data->bytes_xfered = data->blocks
1930                                                              * data->blksz;
1931                                         data->error = 0;
1932                                         state = STATE_END_REQUEST;
1933                                 }
1934                         } else
1935                                 state = STATE_END_REQUEST;
1936                         break;
1937 
1938                 case STATE_SENDING_STOP:
1939                         /*
1940                          * In this state, it is important to set host->data to
1941                          * NULL (which is tested in the waiting notbusy state)
1942                          * in order to go to the end request state instead of
1943                          * sending stop again.
1944                          */
1945                         dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1946                         if (!atmci_test_and_clear_pending(host,
1947                                                 EVENT_CMD_RDY))
1948                                 break;
1949 
1950                         dev_dbg(&host->pdev->dev, "FSM: cmd ready\n");
1951                         host->cmd = NULL;
1952                         data->bytes_xfered = data->blocks * data->blksz;
1953                         data->error = 0;
1954                         atmci_command_complete(host, mrq->stop);
1955                         if (mrq->stop->error) {
1956                                 host->stop_transfer(host);
1957                                 atmci_writel(host, ATMCI_IDR,
1958                                              ATMCI_TXRDY | ATMCI_RXRDY
1959                                              | ATMCI_DATA_ERROR_FLAGS);
1960                                 state = STATE_END_REQUEST;
1961                         } else {
1962                                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1963                                 state = STATE_WAITING_NOTBUSY;
1964                         }
1965                         host->data = NULL;
1966                         break;
1967 
1968                 case STATE_END_REQUEST:
1969                         atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY
1970                                            | ATMCI_DATA_ERROR_FLAGS);
1971                         status = host->data_status;
1972                         if (unlikely(status)) {
1973                                 host->stop_transfer(host);
1974                                 host->data = NULL;
1975                                 if (data) {
1976                                         if (status & ATMCI_DTOE) {
1977                                                 data->error = -ETIMEDOUT;
1978                                         } else if (status & ATMCI_DCRCE) {
1979                                                 data->error = -EILSEQ;
1980                                         } else {
1981                                                 data->error = -EIO;
1982                                         }
1983                                 }
1984                         }
1985 
1986                         atmci_request_end(host, host->mrq);
1987                         state = STATE_IDLE;
1988                         break;
1989                 }
1990         } while (state != prev_state);
1991 
1992         host->state = state;
1993 
1994         spin_unlock(&host->lock);
1995 }
1996 
1997 static void atmci_read_data_pio(struct atmel_mci *host)
1998 {
1999         struct scatterlist      *sg = host->sg;
2000         void                    *buf = sg_virt(sg);
2001         unsigned int            offset = host->pio_offset;
2002         struct mmc_data         *data = host->data;
2003         u32                     value;
2004         u32                     status;
2005         unsigned int            nbytes = 0;
2006 
2007         do {
2008                 value = atmci_readl(host, ATMCI_RDR);
2009                 if (likely(offset + 4 <= sg->length)) {
2010                         put_unaligned(value, (u32 *)(buf + offset));
2011 
2012                         offset += 4;
2013                         nbytes += 4;
2014 
2015                         if (offset == sg->length) {
2016                                 flush_dcache_page(sg_page(sg));
2017                                 host->sg = sg = sg_next(sg);
2018                                 host->sg_len--;
2019                                 if (!sg || !host->sg_len)
2020                                         goto done;
2021 
2022                                 offset = 0;
2023                                 buf = sg_virt(sg);
2024                         }
2025                 } else {
2026                         unsigned int remaining = sg->length - offset;
2027                         memcpy(buf + offset, &value, remaining);
2028                         nbytes += remaining;
2029 
2030                         flush_dcache_page(sg_page(sg));
2031                         host->sg = sg = sg_next(sg);
2032                         host->sg_len--;
2033                         if (!sg || !host->sg_len)
2034                                 goto done;
2035 
2036                         offset = 4 - remaining;
2037                         buf = sg_virt(sg);
2038                         memcpy(buf, (u8 *)&value + remaining, offset);
2039                         nbytes += offset;
2040                 }
2041 
2042                 status = atmci_readl(host, ATMCI_SR);
2043                 if (status & ATMCI_DATA_ERROR_FLAGS) {
2044                         atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
2045                                                 | ATMCI_DATA_ERROR_FLAGS));
2046                         host->data_status = status;
2047                         data->bytes_xfered += nbytes;
2048                         return;
2049                 }
2050         } while (status & ATMCI_RXRDY);
2051 
2052         host->pio_offset = offset;
2053         data->bytes_xfered += nbytes;
2054 
2055         return;
2056 
2057 done:
2058         atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
2059         atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
2060         data->bytes_xfered += nbytes;
2061         smp_wmb();
2062         atmci_set_pending(host, EVENT_XFER_COMPLETE);
2063 }
2064 
2065 static void atmci_write_data_pio(struct atmel_mci *host)
2066 {
2067         struct scatterlist      *sg = host->sg;
2068         void                    *buf = sg_virt(sg);
2069         unsigned int            offset = host->pio_offset;
2070         struct mmc_data         *data = host->data;
2071         u32                     value;
2072         u32                     status;
2073         unsigned int            nbytes = 0;
2074 
2075         do {
2076                 if (likely(offset + 4 <= sg->length)) {
2077                         value = get_unaligned((u32 *)(buf + offset));
2078                         atmci_writel(host, ATMCI_TDR, value);
2079 
2080                         offset += 4;
2081                         nbytes += 4;
2082                         if (offset == sg->length) {
2083                                 host->sg = sg = sg_next(sg);
2084                                 host->sg_len--;
2085                                 if (!sg || !host->sg_len)
2086                                         goto done;
2087 
2088                                 offset = 0;
2089                                 buf = sg_virt(sg);
2090                         }
2091                 } else {
2092                         unsigned int remaining = sg->length - offset;
2093 
2094                         value = 0;
2095                         memcpy(&value, buf + offset, remaining);
2096                         nbytes += remaining;
2097 
2098                         host->sg = sg = sg_next(sg);
2099                         host->sg_len--;
2100                         if (!sg || !host->sg_len) {
2101                                 atmci_writel(host, ATMCI_TDR, value);
2102                                 goto done;
2103                         }
2104 
2105                         offset = 4 - remaining;
2106                         buf = sg_virt(sg);
2107                         memcpy((u8 *)&value + remaining, buf, offset);
2108                         atmci_writel(host, ATMCI_TDR, value);
2109                         nbytes += offset;
2110                 }
2111 
2112                 status = atmci_readl(host, ATMCI_SR);
2113                 if (status & ATMCI_DATA_ERROR_FLAGS) {
2114                         atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
2115                                                 | ATMCI_DATA_ERROR_FLAGS));
2116                         host->data_status = status;
2117                         data->bytes_xfered += nbytes;
2118                         return;
2119                 }
2120         } while (status & ATMCI_TXRDY);
2121 
2122         host->pio_offset = offset;
2123         data->bytes_xfered += nbytes;
2124 
2125         return;
2126 
2127 done:
2128         atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
2129         atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
2130         data->bytes_xfered += nbytes;
2131         smp_wmb();
2132         atmci_set_pending(host, EVENT_XFER_COMPLETE);
2133 }
2134 
2135 static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
2136 {
2137         int     i;
2138 
2139         for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2140                 struct atmel_mci_slot *slot = host->slot[i];
2141                 if (slot && (status & slot->sdio_irq)) {
2142                         mmc_signal_sdio_irq(slot->mmc);
2143                 }
2144         }
2145 }
2146 
2147 
2148 static irqreturn_t atmci_interrupt(int irq, void *dev_id)
2149 {
2150         struct atmel_mci        *host = dev_id;
2151         u32                     status, mask, pending;
2152         unsigned int            pass_count = 0;
2153 
2154         do {
2155                 status = atmci_readl(host, ATMCI_SR);
2156                 mask = atmci_readl(host, ATMCI_IMR);
2157                 pending = status & mask;
2158                 if (!pending)
2159                         break;
2160 
2161                 if (pending & ATMCI_DATA_ERROR_FLAGS) {
2162                         dev_dbg(&host->pdev->dev, "IRQ: data error\n");
2163                         atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
2164                                         | ATMCI_RXRDY | ATMCI_TXRDY
2165                                         | ATMCI_ENDRX | ATMCI_ENDTX
2166                                         | ATMCI_RXBUFF | ATMCI_TXBUFE);
2167 
2168                         host->data_status = status;
2169                         dev_dbg(&host->pdev->dev, "set pending data error\n");
2170                         smp_wmb();
2171                         atmci_set_pending(host, EVENT_DATA_ERROR);
2172                         tasklet_schedule(&host->tasklet);
2173                 }
2174 
2175                 if (pending & ATMCI_TXBUFE) {
2176                         dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n");
2177                         atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
2178                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2179                         /*
2180                          * We can receive this interruption before having configured
2181                          * the second pdc buffer, so we need to reconfigure first and
2182                          * second buffers again
2183                          */
2184                         if (host->data_size) {
2185                                 atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
2186                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2187                                 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
2188                         } else {
2189                                 atmci_pdc_complete(host);
2190                         }
2191                 } else if (pending & ATMCI_ENDTX) {
2192                         dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n");
2193                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2194 
2195                         if (host->data_size) {
2196                                 atmci_pdc_set_single_buf(host,
2197                                                 XFER_TRANSMIT, PDC_SECOND_BUF);
2198                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2199                         }
2200                 }
2201 
2202                 if (pending & ATMCI_RXBUFF) {
2203                         dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n");
2204                         atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
2205                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2206                         /*
2207                          * We can receive this interruption before having configured
2208                          * the second pdc buffer, so we need to reconfigure first and
2209                          * second buffers again
2210                          */
2211                         if (host->data_size) {
2212                                 atmci_pdc_set_both_buf(host, XFER_RECEIVE);
2213                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2214                                 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
2215                         } else {
2216                                 atmci_pdc_complete(host);
2217                         }
2218                 } else if (pending & ATMCI_ENDRX) {
2219                         dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n");
2220                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2221 
2222                         if (host->data_size) {
2223                                 atmci_pdc_set_single_buf(host,
2224                                                 XFER_RECEIVE, PDC_SECOND_BUF);
2225                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2226                         }
2227                 }
2228 
2229                 /*
2230                  * First mci IPs, so mainly the ones having pdc, have some
2231                  * issues with the notbusy signal. You can't get it after
2232                  * data transmission if you have not sent a stop command.
2233                  * The appropriate workaround is to use the BLKE signal.
2234                  */
2235                 if (pending & ATMCI_BLKE) {
2236                         dev_dbg(&host->pdev->dev, "IRQ: blke\n");
2237                         atmci_writel(host, ATMCI_IDR, ATMCI_BLKE);
2238                         smp_wmb();
2239                         dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2240                         atmci_set_pending(host, EVENT_NOTBUSY);
2241                         tasklet_schedule(&host->tasklet);
2242                 }
2243 
2244                 if (pending & ATMCI_NOTBUSY) {
2245                         dev_dbg(&host->pdev->dev, "IRQ: not_busy\n");
2246                         atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY);
2247                         smp_wmb();
2248                         dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2249                         atmci_set_pending(host, EVENT_NOTBUSY);
2250                         tasklet_schedule(&host->tasklet);
2251                 }
2252 
2253                 if (pending & ATMCI_RXRDY)
2254                         atmci_read_data_pio(host);
2255                 if (pending & ATMCI_TXRDY)
2256                         atmci_write_data_pio(host);
2257 
2258                 if (pending & ATMCI_CMDRDY) {
2259                         dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n");
2260                         atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
2261                         host->cmd_status = status;
2262                         smp_wmb();
2263                         dev_dbg(&host->pdev->dev, "set pending cmd rdy\n");
2264                         atmci_set_pending(host, EVENT_CMD_RDY);
2265                         tasklet_schedule(&host->tasklet);
2266                 }
2267 
2268                 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
2269                         atmci_sdio_interrupt(host, status);
2270 
2271         } while (pass_count++ < 5);
2272 
2273         return pass_count ? IRQ_HANDLED : IRQ_NONE;
2274 }
2275 
2276 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
2277 {
2278         struct atmel_mci_slot   *slot = dev_id;
2279 
2280         /*
2281          * Disable interrupts until the pin has stabilized and check
2282          * the state then. Use mod_timer() since we may be in the
2283          * middle of the timer routine when this interrupt triggers.
2284          */
2285         disable_irq_nosync(irq);
2286         mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
2287 
2288         return IRQ_HANDLED;
2289 }
2290 
2291 static int atmci_init_slot(struct atmel_mci *host,
2292                 struct mci_slot_pdata *slot_data, unsigned int id,
2293                 u32 sdc_reg, u32 sdio_irq)
2294 {
2295         struct mmc_host                 *mmc;
2296         struct atmel_mci_slot           *slot;
2297 
2298         mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
2299         if (!mmc)
2300                 return -ENOMEM;
2301 
2302         slot = mmc_priv(mmc);
2303         slot->mmc = mmc;
2304         slot->host = host;
2305         slot->detect_pin = slot_data->detect_pin;
2306         slot->wp_pin = slot_data->wp_pin;
2307         slot->detect_is_active_high = slot_data->detect_is_active_high;
2308         slot->sdc_reg = sdc_reg;
2309         slot->sdio_irq = sdio_irq;
2310 
2311         dev_dbg(&mmc->class_dev,
2312                 "slot[%u]: bus_width=%u, detect_pin=%d, "
2313                 "detect_is_active_high=%s, wp_pin=%d\n",
2314                 id, slot_data->bus_width, slot_data->detect_pin,
2315                 slot_data->detect_is_active_high ? "true" : "false",
2316                 slot_data->wp_pin);
2317 
2318         mmc->ops = &atmci_ops;
2319         mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
2320         mmc->f_max = host->bus_hz / 2;
2321         mmc->ocr_avail  = MMC_VDD_32_33 | MMC_VDD_33_34;
2322         if (sdio_irq)
2323                 mmc->caps |= MMC_CAP_SDIO_IRQ;
2324         if (host->caps.has_highspeed)
2325                 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
2326         /*
2327          * Without the read/write proof capability, it is strongly suggested to
2328          * use only one bit for data to prevent fifo underruns and overruns
2329          * which will corrupt data.
2330          */
2331         if ((slot_data->bus_width >= 4) && host->caps.has_rwproof)
2332                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2333 
2334         if (atmci_get_version(host) < 0x200) {
2335                 mmc->max_segs = 256;
2336                 mmc->max_blk_size = 4095;
2337                 mmc->max_blk_count = 256;
2338                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2339                 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs;
2340         } else {
2341                 mmc->max_segs = 64;
2342                 mmc->max_req_size = 32768 * 512;
2343                 mmc->max_blk_size = 32768;
2344                 mmc->max_blk_count = 512;
2345         }
2346 
2347         /* Assume card is present initially */
2348         set_bit(ATMCI_CARD_PRESENT, &slot->flags);
2349         if (gpio_is_valid(slot->detect_pin)) {
2350                 if (devm_gpio_request(&host->pdev->dev, slot->detect_pin,
2351                                       "mmc_detect")) {
2352                         dev_dbg(&mmc->class_dev, "no detect pin available\n");
2353                         slot->detect_pin = -EBUSY;
2354                 } else if (gpio_get_value(slot->detect_pin) ^
2355                                 slot->detect_is_active_high) {
2356                         clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
2357                 }
2358         }
2359 
2360         if (!gpio_is_valid(slot->detect_pin)) {
2361                 if (slot_data->non_removable)
2362                         mmc->caps |= MMC_CAP_NONREMOVABLE;
2363                 else
2364                         mmc->caps |= MMC_CAP_NEEDS_POLL;
2365         }
2366 
2367         if (gpio_is_valid(slot->wp_pin)) {
2368                 if (devm_gpio_request(&host->pdev->dev, slot->wp_pin,
2369                                       "mmc_wp")) {
2370                         dev_dbg(&mmc->class_dev, "no WP pin available\n");
2371                         slot->wp_pin = -EBUSY;
2372                 }
2373         }
2374 
2375         host->slot[id] = slot;
2376         mmc_regulator_get_supply(mmc);
2377         mmc_add_host(mmc);
2378 
2379         if (gpio_is_valid(slot->detect_pin)) {
2380                 int ret;
2381 
2382                 setup_timer(&slot->detect_timer, atmci_detect_change,
2383                                 (unsigned long)slot);
2384 
2385                 ret = request_irq(gpio_to_irq(slot->detect_pin),
2386                                 atmci_detect_interrupt,
2387                                 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2388                                 "mmc-detect", slot);
2389                 if (ret) {
2390                         dev_dbg(&mmc->class_dev,
2391                                 "could not request IRQ %d for detect pin\n",
2392                                 gpio_to_irq(slot->detect_pin));
2393                         slot->detect_pin = -EBUSY;
2394                 }
2395         }
2396 
2397         atmci_init_debugfs(slot);
2398 
2399         return 0;
2400 }
2401 
2402 static void atmci_cleanup_slot(struct atmel_mci_slot *slot,
2403                 unsigned int id)
2404 {
2405         /* Debugfs stuff is cleaned up by mmc core */
2406 
2407         set_bit(ATMCI_SHUTDOWN, &slot->flags);
2408         smp_wmb();
2409 
2410         mmc_remove_host(slot->mmc);
2411 
2412         if (gpio_is_valid(slot->detect_pin)) {
2413                 int pin = slot->detect_pin;
2414 
2415                 free_irq(gpio_to_irq(pin), slot);
2416                 del_timer_sync(&slot->detect_timer);
2417         }
2418 
2419         slot->host->slot[id] = NULL;
2420         mmc_free_host(slot->mmc);
2421 }
2422 
2423 static int atmci_configure_dma(struct atmel_mci *host)
2424 {
2425         host->dma.chan = dma_request_slave_channel_reason(&host->pdev->dev,
2426                                                         "rxtx");
2427 
2428         if (PTR_ERR(host->dma.chan) == -ENODEV) {
2429                 struct mci_platform_data *pdata = host->pdev->dev.platform_data;
2430                 dma_cap_mask_t mask;
2431 
2432                 if (!pdata || !pdata->dma_filter)
2433                         return -ENODEV;
2434 
2435                 dma_cap_zero(mask);
2436                 dma_cap_set(DMA_SLAVE, mask);
2437 
2438                 host->dma.chan = dma_request_channel(mask, pdata->dma_filter,
2439                                                      pdata->dma_slave);
2440                 if (!host->dma.chan)
2441                         host->dma.chan = ERR_PTR(-ENODEV);
2442         }
2443 
2444         if (IS_ERR(host->dma.chan))
2445                 return PTR_ERR(host->dma.chan);
2446 
2447         dev_info(&host->pdev->dev, "using %s for DMA transfers\n",
2448                  dma_chan_name(host->dma.chan));
2449 
2450         host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
2451         host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2452         host->dma_conf.src_maxburst = 1;
2453         host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
2454         host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2455         host->dma_conf.dst_maxburst = 1;
2456         host->dma_conf.device_fc = false;
2457 
2458         return 0;
2459 }
2460 
2461 /*
2462  * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2463  * HSMCI provides DMA support and a new config register but no more supports
2464  * PDC.
2465  */
2466 static void atmci_get_cap(struct atmel_mci *host)
2467 {
2468         unsigned int version;
2469 
2470         version = atmci_get_version(host);
2471         dev_info(&host->pdev->dev,
2472                         "version: 0x%x\n", version);
2473 
2474         host->caps.has_dma_conf_reg = 0;
2475         host->caps.has_pdc = ATMCI_PDC_CONNECTED;
2476         host->caps.has_cfg_reg = 0;
2477         host->caps.has_cstor_reg = 0;
2478         host->caps.has_highspeed = 0;
2479         host->caps.has_rwproof = 0;
2480         host->caps.has_odd_clk_div = 0;
2481         host->caps.has_bad_data_ordering = 1;
2482         host->caps.need_reset_after_xfer = 1;
2483         host->caps.need_blksz_mul_4 = 1;
2484         host->caps.need_notbusy_for_read_ops = 0;
2485 
2486         /* keep only major version number */
2487         switch (version & 0xf00) {
2488         case 0x600:
2489         case 0x500:
2490                 host->caps.has_odd_clk_div = 1;
2491         case 0x400:
2492         case 0x300:
2493                 host->caps.has_dma_conf_reg = 1;
2494                 host->caps.has_pdc = 0;
2495                 host->caps.has_cfg_reg = 1;
2496                 host->caps.has_cstor_reg = 1;
2497                 host->caps.has_highspeed = 1;
2498         case 0x200:
2499                 host->caps.has_rwproof = 1;
2500                 host->caps.need_blksz_mul_4 = 0;
2501                 host->caps.need_notbusy_for_read_ops = 1;
2502         case 0x100:
2503                 host->caps.has_bad_data_ordering = 0;
2504                 host->caps.need_reset_after_xfer = 0;
2505         case 0x0:
2506                 break;
2507         default:
2508                 host->caps.has_pdc = 0;
2509                 dev_warn(&host->pdev->dev,
2510                                 "Unmanaged mci version, set minimum capabilities\n");
2511                 break;
2512         }
2513 }
2514 
2515 static int atmci_probe(struct platform_device *pdev)
2516 {
2517         struct mci_platform_data        *pdata;
2518         struct atmel_mci                *host;
2519         struct resource                 *regs;
2520         unsigned int                    nr_slots;
2521         int                             irq;
2522         int                             ret, i;
2523 
2524         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2525         if (!regs)
2526                 return -ENXIO;
2527         pdata = pdev->dev.platform_data;
2528         if (!pdata) {
2529                 pdata = atmci_of_init(pdev);
2530                 if (IS_ERR(pdata)) {
2531                         dev_err(&pdev->dev, "platform data not available\n");
2532                         return PTR_ERR(pdata);
2533                 }
2534         }
2535 
2536         irq = platform_get_irq(pdev, 0);
2537         if (irq < 0)
2538                 return irq;
2539 
2540         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
2541         if (!host)
2542                 return -ENOMEM;
2543 
2544         host->pdev = pdev;
2545         spin_lock_init(&host->lock);
2546         INIT_LIST_HEAD(&host->queue);
2547 
2548         host->mck = devm_clk_get(&pdev->dev, "mci_clk");
2549         if (IS_ERR(host->mck))
2550                 return PTR_ERR(host->mck);
2551 
2552         host->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
2553         if (!host->regs)
2554                 return -ENOMEM;
2555 
2556         ret = clk_prepare_enable(host->mck);
2557         if (ret)
2558                 return ret;
2559 
2560         atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
2561         host->bus_hz = clk_get_rate(host->mck);
2562 
2563         host->mapbase = regs->start;
2564 
2565         tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
2566 
2567         ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
2568         if (ret) {
2569                 clk_disable_unprepare(host->mck);
2570                 return ret;
2571         }
2572 
2573         /* Get MCI capabilities and set operations according to it */
2574         atmci_get_cap(host);
2575         ret = atmci_configure_dma(host);
2576         if (ret == -EPROBE_DEFER)
2577                 goto err_dma_probe_defer;
2578         if (ret == 0) {
2579                 host->prepare_data = &atmci_prepare_data_dma;
2580                 host->submit_data = &atmci_submit_data_dma;
2581                 host->stop_transfer = &atmci_stop_transfer_dma;
2582         } else if (host->caps.has_pdc) {
2583                 dev_info(&pdev->dev, "using PDC\n");
2584                 host->prepare_data = &atmci_prepare_data_pdc;
2585                 host->submit_data = &atmci_submit_data_pdc;
2586                 host->stop_transfer = &atmci_stop_transfer_pdc;
2587         } else {
2588                 dev_info(&pdev->dev, "using PIO\n");
2589                 host->prepare_data = &atmci_prepare_data;
2590                 host->submit_data = &atmci_submit_data;
2591                 host->stop_transfer = &atmci_stop_transfer;
2592         }
2593 
2594         platform_set_drvdata(pdev, host);
2595 
2596         setup_timer(&host->timer, atmci_timeout_timer, (unsigned long)host);
2597 
2598         pm_runtime_get_noresume(&pdev->dev);
2599         pm_runtime_set_active(&pdev->dev);
2600         pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_DELAY);
2601         pm_runtime_use_autosuspend(&pdev->dev);
2602         pm_runtime_enable(&pdev->dev);
2603 
2604         /* We need at least one slot to succeed */
2605         nr_slots = 0;
2606         ret = -ENODEV;
2607         if (pdata->slot[0].bus_width) {
2608                 ret = atmci_init_slot(host, &pdata->slot[0],
2609                                 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
2610                 if (!ret) {
2611                         nr_slots++;
2612                         host->buf_size = host->slot[0]->mmc->max_req_size;
2613                 }
2614         }
2615         if (pdata->slot[1].bus_width) {
2616                 ret = atmci_init_slot(host, &pdata->slot[1],
2617                                 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
2618                 if (!ret) {
2619                         nr_slots++;
2620                         if (host->slot[1]->mmc->max_req_size > host->buf_size)
2621                                 host->buf_size =
2622                                         host->slot[1]->mmc->max_req_size;
2623                 }
2624         }
2625 
2626         if (!nr_slots) {
2627                 dev_err(&pdev->dev, "init failed: no slot defined\n");
2628                 goto err_init_slot;
2629         }
2630 
2631         if (!host->caps.has_rwproof) {
2632                 host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size,
2633                                                   &host->buf_phys_addr,
2634                                                   GFP_KERNEL);
2635                 if (!host->buffer) {
2636                         ret = -ENOMEM;
2637                         dev_err(&pdev->dev, "buffer allocation failed\n");
2638                         goto err_dma_alloc;
2639                 }
2640         }
2641 
2642         dev_info(&pdev->dev,
2643                         "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2644                         host->mapbase, irq, nr_slots);
2645 
2646         pm_runtime_mark_last_busy(&host->pdev->dev);
2647         pm_runtime_put_autosuspend(&pdev->dev);
2648 
2649         return 0;
2650 
2651 err_dma_alloc:
2652         for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2653                 if (host->slot[i])
2654                         atmci_cleanup_slot(host->slot[i], i);
2655         }
2656 err_init_slot:
2657         clk_disable_unprepare(host->mck);
2658 
2659         pm_runtime_disable(&pdev->dev);
2660         pm_runtime_put_noidle(&pdev->dev);
2661 
2662         del_timer_sync(&host->timer);
2663         if (!IS_ERR(host->dma.chan))
2664                 dma_release_channel(host->dma.chan);
2665 err_dma_probe_defer:
2666         free_irq(irq, host);
2667         return ret;
2668 }
2669 
2670 static int atmci_remove(struct platform_device *pdev)
2671 {
2672         struct atmel_mci        *host = platform_get_drvdata(pdev);
2673         unsigned int            i;
2674 
2675         pm_runtime_get_sync(&pdev->dev);
2676 
2677         if (host->buffer)
2678                 dma_free_coherent(&pdev->dev, host->buf_size,
2679                                   host->buffer, host->buf_phys_addr);
2680 
2681         for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2682                 if (host->slot[i])
2683                         atmci_cleanup_slot(host->slot[i], i);
2684         }
2685 
2686         atmci_writel(host, ATMCI_IDR, ~0UL);
2687         atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2688         atmci_readl(host, ATMCI_SR);
2689 
2690         del_timer_sync(&host->timer);
2691         if (!IS_ERR(host->dma.chan))
2692                 dma_release_channel(host->dma.chan);
2693 
2694         free_irq(platform_get_irq(pdev, 0), host);
2695 
2696         clk_disable_unprepare(host->mck);
2697 
2698         pm_runtime_disable(&pdev->dev);
2699         pm_runtime_put_noidle(&pdev->dev);
2700 
2701         return 0;
2702 }
2703 
2704 #ifdef CONFIG_PM
2705 static int atmci_runtime_suspend(struct device *dev)
2706 {
2707         struct atmel_mci *host = dev_get_drvdata(dev);
2708 
2709         clk_disable_unprepare(host->mck);
2710 
2711         pinctrl_pm_select_sleep_state(dev);
2712 
2713         return 0;
2714 }
2715 
2716 static int atmci_runtime_resume(struct device *dev)
2717 {
2718         struct atmel_mci *host = dev_get_drvdata(dev);
2719 
2720         pinctrl_pm_select_default_state(dev);
2721 
2722         return clk_prepare_enable(host->mck);
2723 }
2724 #endif
2725 
2726 static const struct dev_pm_ops atmci_dev_pm_ops = {
2727         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2728                                 pm_runtime_force_resume)
2729         SET_RUNTIME_PM_OPS(atmci_runtime_suspend, atmci_runtime_resume, NULL)
2730 };
2731 
2732 static struct platform_driver atmci_driver = {
2733         .probe          = atmci_probe,
2734         .remove         = atmci_remove,
2735         .driver         = {
2736                 .name           = "atmel_mci",
2737                 .of_match_table = of_match_ptr(atmci_dt_ids),
2738                 .pm             = &atmci_dev_pm_ops,
2739         },
2740 };
2741 module_platform_driver(atmci_driver);
2742 
2743 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2744 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2745 MODULE_LICENSE("GPL v2");
2746 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us