Version:  2.0.40 2.2.26 2.4.37 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0

Linux/drivers/mmc/host/atmel-mci.c

  1 /*
  2  * Atmel MultiMedia Card Interface driver
  3  *
  4  * Copyright (C) 2004-2008 Atmel Corporation
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License version 2 as
  8  * published by the Free Software Foundation.
  9  */
 10 #include <linux/blkdev.h>
 11 #include <linux/clk.h>
 12 #include <linux/debugfs.h>
 13 #include <linux/device.h>
 14 #include <linux/dmaengine.h>
 15 #include <linux/dma-mapping.h>
 16 #include <linux/err.h>
 17 #include <linux/gpio.h>
 18 #include <linux/init.h>
 19 #include <linux/interrupt.h>
 20 #include <linux/io.h>
 21 #include <linux/ioport.h>
 22 #include <linux/module.h>
 23 #include <linux/of.h>
 24 #include <linux/of_device.h>
 25 #include <linux/of_gpio.h>
 26 #include <linux/platform_device.h>
 27 #include <linux/scatterlist.h>
 28 #include <linux/seq_file.h>
 29 #include <linux/slab.h>
 30 #include <linux/stat.h>
 31 #include <linux/types.h>
 32 #include <linux/platform_data/atmel.h>
 33 #include <linux/platform_data/mmc-atmel-mci.h>
 34 
 35 #include <linux/mmc/host.h>
 36 #include <linux/mmc/sdio.h>
 37 
 38 #include <linux/atmel-mci.h>
 39 #include <linux/atmel_pdc.h>
 40 #include <linux/pm.h>
 41 #include <linux/pm_runtime.h>
 42 #include <linux/pinctrl/consumer.h>
 43 
 44 #include <asm/cacheflush.h>
 45 #include <asm/io.h>
 46 #include <asm/unaligned.h>
 47 
 48 #include "atmel-mci-regs.h"
 49 
 50 #define AUTOSUSPEND_DELAY       50
 51 
 52 #define ATMCI_DATA_ERROR_FLAGS  (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
 53 #define ATMCI_DMA_THRESHOLD     16
 54 
 55 enum {
 56         EVENT_CMD_RDY = 0,
 57         EVENT_XFER_COMPLETE,
 58         EVENT_NOTBUSY,
 59         EVENT_DATA_ERROR,
 60 };
 61 
 62 enum atmel_mci_state {
 63         STATE_IDLE = 0,
 64         STATE_SENDING_CMD,
 65         STATE_DATA_XFER,
 66         STATE_WAITING_NOTBUSY,
 67         STATE_SENDING_STOP,
 68         STATE_END_REQUEST,
 69 };
 70 
 71 enum atmci_xfer_dir {
 72         XFER_RECEIVE = 0,
 73         XFER_TRANSMIT,
 74 };
 75 
 76 enum atmci_pdc_buf {
 77         PDC_FIRST_BUF = 0,
 78         PDC_SECOND_BUF,
 79 };
 80 
 81 struct atmel_mci_caps {
 82         bool    has_dma_conf_reg;
 83         bool    has_pdc;
 84         bool    has_cfg_reg;
 85         bool    has_cstor_reg;
 86         bool    has_highspeed;
 87         bool    has_rwproof;
 88         bool    has_odd_clk_div;
 89         bool    has_bad_data_ordering;
 90         bool    need_reset_after_xfer;
 91         bool    need_blksz_mul_4;
 92         bool    need_notbusy_for_read_ops;
 93 };
 94 
 95 struct atmel_mci_dma {
 96         struct dma_chan                 *chan;
 97         struct dma_async_tx_descriptor  *data_desc;
 98 };
 99 
100 /**
101  * struct atmel_mci - MMC controller state shared between all slots
102  * @lock: Spinlock protecting the queue and associated data.
103  * @regs: Pointer to MMIO registers.
104  * @sg: Scatterlist entry currently being processed by PIO or PDC code.
105  * @pio_offset: Offset into the current scatterlist entry.
106  * @buffer: Buffer used if we don't have the r/w proof capability. We
107  *      don't have the time to switch pdc buffers so we have to use only
108  *      one buffer for the full transaction.
109  * @buf_size: size of the buffer.
110  * @phys_buf_addr: buffer address needed for pdc.
111  * @cur_slot: The slot which is currently using the controller.
112  * @mrq: The request currently being processed on @cur_slot,
113  *      or NULL if the controller is idle.
114  * @cmd: The command currently being sent to the card, or NULL.
115  * @data: The data currently being transferred, or NULL if no data
116  *      transfer is in progress.
117  * @data_size: just data->blocks * data->blksz.
118  * @dma: DMA client state.
119  * @data_chan: DMA channel being used for the current data transfer.
120  * @cmd_status: Snapshot of SR taken upon completion of the current
121  *      command. Only valid when EVENT_CMD_COMPLETE is pending.
122  * @data_status: Snapshot of SR taken upon completion of the current
123  *      data transfer. Only valid when EVENT_DATA_COMPLETE or
124  *      EVENT_DATA_ERROR is pending.
125  * @stop_cmdr: Value to be loaded into CMDR when the stop command is
126  *      to be sent.
127  * @tasklet: Tasklet running the request state machine.
128  * @pending_events: Bitmask of events flagged by the interrupt handler
129  *      to be processed by the tasklet.
130  * @completed_events: Bitmask of events which the state machine has
131  *      processed.
132  * @state: Tasklet state.
133  * @queue: List of slots waiting for access to the controller.
134  * @need_clock_update: Update the clock rate before the next request.
135  * @need_reset: Reset controller before next request.
136  * @timer: Timer to balance the data timeout error flag which cannot rise.
137  * @mode_reg: Value of the MR register.
138  * @cfg_reg: Value of the CFG register.
139  * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
140  *      rate and timeout calculations.
141  * @mapbase: Physical address of the MMIO registers.
142  * @mck: The peripheral bus clock hooked up to the MMC controller.
143  * @pdev: Platform device associated with the MMC controller.
144  * @slot: Slots sharing this MMC controller.
145  * @caps: MCI capabilities depending on MCI version.
146  * @prepare_data: function to setup MCI before data transfer which
147  * depends on MCI capabilities.
148  * @submit_data: function to start data transfer which depends on MCI
149  * capabilities.
150  * @stop_transfer: function to stop data transfer which depends on MCI
151  * capabilities.
152  *
153  * Locking
154  * =======
155  *
156  * @lock is a softirq-safe spinlock protecting @queue as well as
157  * @cur_slot, @mrq and @state. These must always be updated
158  * at the same time while holding @lock.
159  *
160  * @lock also protects mode_reg and need_clock_update since these are
161  * used to synchronize mode register updates with the queue
162  * processing.
163  *
164  * The @mrq field of struct atmel_mci_slot is also protected by @lock,
165  * and must always be written at the same time as the slot is added to
166  * @queue.
167  *
168  * @pending_events and @completed_events are accessed using atomic bit
169  * operations, so they don't need any locking.
170  *
171  * None of the fields touched by the interrupt handler need any
172  * locking. However, ordering is important: Before EVENT_DATA_ERROR or
173  * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
174  * interrupts must be disabled and @data_status updated with a
175  * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
176  * CMDRDY interrupt must be disabled and @cmd_status updated with a
177  * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
178  * bytes_xfered field of @data must be written. This is ensured by
179  * using barriers.
180  */
181 struct atmel_mci {
182         spinlock_t              lock;
183         void __iomem            *regs;
184 
185         struct scatterlist      *sg;
186         unsigned int            sg_len;
187         unsigned int            pio_offset;
188         unsigned int            *buffer;
189         unsigned int            buf_size;
190         dma_addr_t              buf_phys_addr;
191 
192         struct atmel_mci_slot   *cur_slot;
193         struct mmc_request      *mrq;
194         struct mmc_command      *cmd;
195         struct mmc_data         *data;
196         unsigned int            data_size;
197 
198         struct atmel_mci_dma    dma;
199         struct dma_chan         *data_chan;
200         struct dma_slave_config dma_conf;
201 
202         u32                     cmd_status;
203         u32                     data_status;
204         u32                     stop_cmdr;
205 
206         struct tasklet_struct   tasklet;
207         unsigned long           pending_events;
208         unsigned long           completed_events;
209         enum atmel_mci_state    state;
210         struct list_head        queue;
211 
212         bool                    need_clock_update;
213         bool                    need_reset;
214         struct timer_list       timer;
215         u32                     mode_reg;
216         u32                     cfg_reg;
217         unsigned long           bus_hz;
218         unsigned long           mapbase;
219         struct clk              *mck;
220         struct platform_device  *pdev;
221 
222         struct atmel_mci_slot   *slot[ATMCI_MAX_NR_SLOTS];
223 
224         struct atmel_mci_caps   caps;
225 
226         u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
227         void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
228         void (*stop_transfer)(struct atmel_mci *host);
229 };
230 
231 /**
232  * struct atmel_mci_slot - MMC slot state
233  * @mmc: The mmc_host representing this slot.
234  * @host: The MMC controller this slot is using.
235  * @sdc_reg: Value of SDCR to be written before using this slot.
236  * @sdio_irq: SDIO irq mask for this slot.
237  * @mrq: mmc_request currently being processed or waiting to be
238  *      processed, or NULL when the slot is idle.
239  * @queue_node: List node for placing this node in the @queue list of
240  *      &struct atmel_mci.
241  * @clock: Clock rate configured by set_ios(). Protected by host->lock.
242  * @flags: Random state bits associated with the slot.
243  * @detect_pin: GPIO pin used for card detection, or negative if not
244  *      available.
245  * @wp_pin: GPIO pin used for card write protect sending, or negative
246  *      if not available.
247  * @detect_is_active_high: The state of the detect pin when it is active.
248  * @detect_timer: Timer used for debouncing @detect_pin interrupts.
249  */
250 struct atmel_mci_slot {
251         struct mmc_host         *mmc;
252         struct atmel_mci        *host;
253 
254         u32                     sdc_reg;
255         u32                     sdio_irq;
256 
257         struct mmc_request      *mrq;
258         struct list_head        queue_node;
259 
260         unsigned int            clock;
261         unsigned long           flags;
262 #define ATMCI_CARD_PRESENT      0
263 #define ATMCI_CARD_NEED_INIT    1
264 #define ATMCI_SHUTDOWN          2
265 
266         int                     detect_pin;
267         int                     wp_pin;
268         bool                    detect_is_active_high;
269 
270         struct timer_list       detect_timer;
271 };
272 
273 #define atmci_test_and_clear_pending(host, event)               \
274         test_and_clear_bit(event, &host->pending_events)
275 #define atmci_set_completed(host, event)                        \
276         set_bit(event, &host->completed_events)
277 #define atmci_set_pending(host, event)                          \
278         set_bit(event, &host->pending_events)
279 
280 /*
281  * The debugfs stuff below is mostly optimized away when
282  * CONFIG_DEBUG_FS is not set.
283  */
284 static int atmci_req_show(struct seq_file *s, void *v)
285 {
286         struct atmel_mci_slot   *slot = s->private;
287         struct mmc_request      *mrq;
288         struct mmc_command      *cmd;
289         struct mmc_command      *stop;
290         struct mmc_data         *data;
291 
292         /* Make sure we get a consistent snapshot */
293         spin_lock_bh(&slot->host->lock);
294         mrq = slot->mrq;
295 
296         if (mrq) {
297                 cmd = mrq->cmd;
298                 data = mrq->data;
299                 stop = mrq->stop;
300 
301                 if (cmd)
302                         seq_printf(s,
303                                 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
304                                 cmd->opcode, cmd->arg, cmd->flags,
305                                 cmd->resp[0], cmd->resp[1], cmd->resp[2],
306                                 cmd->resp[3], cmd->error);
307                 if (data)
308                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
309                                 data->bytes_xfered, data->blocks,
310                                 data->blksz, data->flags, data->error);
311                 if (stop)
312                         seq_printf(s,
313                                 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
314                                 stop->opcode, stop->arg, stop->flags,
315                                 stop->resp[0], stop->resp[1], stop->resp[2],
316                                 stop->resp[3], stop->error);
317         }
318 
319         spin_unlock_bh(&slot->host->lock);
320 
321         return 0;
322 }
323 
324 static int atmci_req_open(struct inode *inode, struct file *file)
325 {
326         return single_open(file, atmci_req_show, inode->i_private);
327 }
328 
329 static const struct file_operations atmci_req_fops = {
330         .owner          = THIS_MODULE,
331         .open           = atmci_req_open,
332         .read           = seq_read,
333         .llseek         = seq_lseek,
334         .release        = single_release,
335 };
336 
337 static void atmci_show_status_reg(struct seq_file *s,
338                 const char *regname, u32 value)
339 {
340         static const char       *sr_bit[] = {
341                 [0]     = "CMDRDY",
342                 [1]     = "RXRDY",
343                 [2]     = "TXRDY",
344                 [3]     = "BLKE",
345                 [4]     = "DTIP",
346                 [5]     = "NOTBUSY",
347                 [6]     = "ENDRX",
348                 [7]     = "ENDTX",
349                 [8]     = "SDIOIRQA",
350                 [9]     = "SDIOIRQB",
351                 [12]    = "SDIOWAIT",
352                 [14]    = "RXBUFF",
353                 [15]    = "TXBUFE",
354                 [16]    = "RINDE",
355                 [17]    = "RDIRE",
356                 [18]    = "RCRCE",
357                 [19]    = "RENDE",
358                 [20]    = "RTOE",
359                 [21]    = "DCRCE",
360                 [22]    = "DTOE",
361                 [23]    = "CSTOE",
362                 [24]    = "BLKOVRE",
363                 [25]    = "DMADONE",
364                 [26]    = "FIFOEMPTY",
365                 [27]    = "XFRDONE",
366                 [30]    = "OVRE",
367                 [31]    = "UNRE",
368         };
369         unsigned int            i;
370 
371         seq_printf(s, "%s:\t0x%08x", regname, value);
372         for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
373                 if (value & (1 << i)) {
374                         if (sr_bit[i])
375                                 seq_printf(s, " %s", sr_bit[i]);
376                         else
377                                 seq_puts(s, " UNKNOWN");
378                 }
379         }
380         seq_putc(s, '\n');
381 }
382 
383 static int atmci_regs_show(struct seq_file *s, void *v)
384 {
385         struct atmel_mci        *host = s->private;
386         u32                     *buf;
387         int                     ret = 0;
388 
389 
390         buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
391         if (!buf)
392                 return -ENOMEM;
393 
394         pm_runtime_get_sync(&host->pdev->dev);
395 
396         /*
397          * Grab a more or less consistent snapshot. Note that we're
398          * not disabling interrupts, so IMR and SR may not be
399          * consistent.
400          */
401         spin_lock_bh(&host->lock);
402         memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
403         spin_unlock_bh(&host->lock);
404 
405         pm_runtime_mark_last_busy(&host->pdev->dev);
406         pm_runtime_put_autosuspend(&host->pdev->dev);
407 
408         seq_printf(s, "MR:\t0x%08x%s%s ",
409                         buf[ATMCI_MR / 4],
410                         buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
411                         buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "");
412         if (host->caps.has_odd_clk_div)
413                 seq_printf(s, "{CLKDIV,CLKODD}=%u\n",
414                                 ((buf[ATMCI_MR / 4] & 0xff) << 1)
415                                 | ((buf[ATMCI_MR / 4] >> 16) & 1));
416         else
417                 seq_printf(s, "CLKDIV=%u\n",
418                                 (buf[ATMCI_MR / 4] & 0xff));
419         seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
420         seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
421         seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
422         seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
423                         buf[ATMCI_BLKR / 4],
424                         buf[ATMCI_BLKR / 4] & 0xffff,
425                         (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
426         if (host->caps.has_cstor_reg)
427                 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
428 
429         /* Don't read RSPR and RDR; it will consume the data there */
430 
431         atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
432         atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
433 
434         if (host->caps.has_dma_conf_reg) {
435                 u32 val;
436 
437                 val = buf[ATMCI_DMA / 4];
438                 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
439                                 val, val & 3,
440                                 ((val >> 4) & 3) ?
441                                         1 << (((val >> 4) & 3) + 1) : 1,
442                                 val & ATMCI_DMAEN ? " DMAEN" : "");
443         }
444         if (host->caps.has_cfg_reg) {
445                 u32 val;
446 
447                 val = buf[ATMCI_CFG / 4];
448                 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
449                                 val,
450                                 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
451                                 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
452                                 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
453                                 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
454         }
455 
456         kfree(buf);
457 
458         return ret;
459 }
460 
461 static int atmci_regs_open(struct inode *inode, struct file *file)
462 {
463         return single_open(file, atmci_regs_show, inode->i_private);
464 }
465 
466 static const struct file_operations atmci_regs_fops = {
467         .owner          = THIS_MODULE,
468         .open           = atmci_regs_open,
469         .read           = seq_read,
470         .llseek         = seq_lseek,
471         .release        = single_release,
472 };
473 
474 static void atmci_init_debugfs(struct atmel_mci_slot *slot)
475 {
476         struct mmc_host         *mmc = slot->mmc;
477         struct atmel_mci        *host = slot->host;
478         struct dentry           *root;
479         struct dentry           *node;
480 
481         root = mmc->debugfs_root;
482         if (!root)
483                 return;
484 
485         node = debugfs_create_file("regs", S_IRUSR, root, host,
486                         &atmci_regs_fops);
487         if (IS_ERR(node))
488                 return;
489         if (!node)
490                 goto err;
491 
492         node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
493         if (!node)
494                 goto err;
495 
496         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
497         if (!node)
498                 goto err;
499 
500         node = debugfs_create_x32("pending_events", S_IRUSR, root,
501                                      (u32 *)&host->pending_events);
502         if (!node)
503                 goto err;
504 
505         node = debugfs_create_x32("completed_events", S_IRUSR, root,
506                                      (u32 *)&host->completed_events);
507         if (!node)
508                 goto err;
509 
510         return;
511 
512 err:
513         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
514 }
515 
516 #if defined(CONFIG_OF)
517 static const struct of_device_id atmci_dt_ids[] = {
518         { .compatible = "atmel,hsmci" },
519         { /* sentinel */ }
520 };
521 
522 MODULE_DEVICE_TABLE(of, atmci_dt_ids);
523 
524 static struct mci_platform_data*
525 atmci_of_init(struct platform_device *pdev)
526 {
527         struct device_node *np = pdev->dev.of_node;
528         struct device_node *cnp;
529         struct mci_platform_data *pdata;
530         u32 slot_id;
531 
532         if (!np) {
533                 dev_err(&pdev->dev, "device node not found\n");
534                 return ERR_PTR(-EINVAL);
535         }
536 
537         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
538         if (!pdata) {
539                 dev_err(&pdev->dev, "could not allocate memory for pdata\n");
540                 return ERR_PTR(-ENOMEM);
541         }
542 
543         for_each_child_of_node(np, cnp) {
544                 if (of_property_read_u32(cnp, "reg", &slot_id)) {
545                         dev_warn(&pdev->dev, "reg property is missing for %s\n",
546                                  cnp->full_name);
547                         continue;
548                 }
549 
550                 if (slot_id >= ATMCI_MAX_NR_SLOTS) {
551                         dev_warn(&pdev->dev, "can't have more than %d slots\n",
552                                  ATMCI_MAX_NR_SLOTS);
553                         break;
554                 }
555 
556                 if (of_property_read_u32(cnp, "bus-width",
557                                          &pdata->slot[slot_id].bus_width))
558                         pdata->slot[slot_id].bus_width = 1;
559 
560                 pdata->slot[slot_id].detect_pin =
561                         of_get_named_gpio(cnp, "cd-gpios", 0);
562 
563                 pdata->slot[slot_id].detect_is_active_high =
564                         of_property_read_bool(cnp, "cd-inverted");
565 
566                 pdata->slot[slot_id].non_removable =
567                         of_property_read_bool(cnp, "non-removable");
568 
569                 pdata->slot[slot_id].wp_pin =
570                         of_get_named_gpio(cnp, "wp-gpios", 0);
571         }
572 
573         return pdata;
574 }
575 #else /* CONFIG_OF */
576 static inline struct mci_platform_data*
577 atmci_of_init(struct platform_device *dev)
578 {
579         return ERR_PTR(-EINVAL);
580 }
581 #endif
582 
583 static inline unsigned int atmci_get_version(struct atmel_mci *host)
584 {
585         return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
586 }
587 
588 static void atmci_timeout_timer(unsigned long data)
589 {
590         struct atmel_mci *host;
591 
592         host = (struct atmel_mci *)data;
593 
594         dev_dbg(&host->pdev->dev, "software timeout\n");
595 
596         if (host->mrq->cmd->data) {
597                 host->mrq->cmd->data->error = -ETIMEDOUT;
598                 host->data = NULL;
599                 /*
600                  * With some SDIO modules, sometimes DMA transfer hangs. If
601                  * stop_transfer() is not called then the DMA request is not
602                  * removed, following ones are queued and never computed.
603                  */
604                 if (host->state == STATE_DATA_XFER)
605                         host->stop_transfer(host);
606         } else {
607                 host->mrq->cmd->error = -ETIMEDOUT;
608                 host->cmd = NULL;
609         }
610         host->need_reset = 1;
611         host->state = STATE_END_REQUEST;
612         smp_wmb();
613         tasklet_schedule(&host->tasklet);
614 }
615 
616 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
617                                         unsigned int ns)
618 {
619         /*
620          * It is easier here to use us instead of ns for the timeout,
621          * it prevents from overflows during calculation.
622          */
623         unsigned int us = DIV_ROUND_UP(ns, 1000);
624 
625         /* Maximum clock frequency is host->bus_hz/2 */
626         return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
627 }
628 
629 static void atmci_set_timeout(struct atmel_mci *host,
630                 struct atmel_mci_slot *slot, struct mmc_data *data)
631 {
632         static unsigned dtomul_to_shift[] = {
633                 0, 4, 7, 8, 10, 12, 16, 20
634         };
635         unsigned        timeout;
636         unsigned        dtocyc;
637         unsigned        dtomul;
638 
639         timeout = atmci_ns_to_clocks(host, data->timeout_ns)
640                 + data->timeout_clks;
641 
642         for (dtomul = 0; dtomul < 8; dtomul++) {
643                 unsigned shift = dtomul_to_shift[dtomul];
644                 dtocyc = (timeout + (1 << shift) - 1) >> shift;
645                 if (dtocyc < 15)
646                         break;
647         }
648 
649         if (dtomul >= 8) {
650                 dtomul = 7;
651                 dtocyc = 15;
652         }
653 
654         dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
655                         dtocyc << dtomul_to_shift[dtomul]);
656         atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
657 }
658 
659 /*
660  * Return mask with command flags to be enabled for this command.
661  */
662 static u32 atmci_prepare_command(struct mmc_host *mmc,
663                                  struct mmc_command *cmd)
664 {
665         struct mmc_data *data;
666         u32             cmdr;
667 
668         cmd->error = -EINPROGRESS;
669 
670         cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
671 
672         if (cmd->flags & MMC_RSP_PRESENT) {
673                 if (cmd->flags & MMC_RSP_136)
674                         cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
675                 else
676                         cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
677         }
678 
679         /*
680          * This should really be MAXLAT_5 for CMD2 and ACMD41, but
681          * it's too difficult to determine whether this is an ACMD or
682          * not. Better make it 64.
683          */
684         cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
685 
686         if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
687                 cmdr |= ATMCI_CMDR_OPDCMD;
688 
689         data = cmd->data;
690         if (data) {
691                 cmdr |= ATMCI_CMDR_START_XFER;
692 
693                 if (cmd->opcode == SD_IO_RW_EXTENDED) {
694                         cmdr |= ATMCI_CMDR_SDIO_BLOCK;
695                 } else {
696                         if (data->flags & MMC_DATA_STREAM)
697                                 cmdr |= ATMCI_CMDR_STREAM;
698                         else if (data->blocks > 1)
699                                 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
700                         else
701                                 cmdr |= ATMCI_CMDR_BLOCK;
702                 }
703 
704                 if (data->flags & MMC_DATA_READ)
705                         cmdr |= ATMCI_CMDR_TRDIR_READ;
706         }
707 
708         return cmdr;
709 }
710 
711 static void atmci_send_command(struct atmel_mci *host,
712                 struct mmc_command *cmd, u32 cmd_flags)
713 {
714         WARN_ON(host->cmd);
715         host->cmd = cmd;
716 
717         dev_vdbg(&host->pdev->dev,
718                         "start command: ARGR=0x%08x CMDR=0x%08x\n",
719                         cmd->arg, cmd_flags);
720 
721         atmci_writel(host, ATMCI_ARGR, cmd->arg);
722         atmci_writel(host, ATMCI_CMDR, cmd_flags);
723 }
724 
725 static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
726 {
727         dev_dbg(&host->pdev->dev, "send stop command\n");
728         atmci_send_command(host, data->stop, host->stop_cmdr);
729         atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
730 }
731 
732 /*
733  * Configure given PDC buffer taking care of alignement issues.
734  * Update host->data_size and host->sg.
735  */
736 static void atmci_pdc_set_single_buf(struct atmel_mci *host,
737         enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
738 {
739         u32 pointer_reg, counter_reg;
740         unsigned int buf_size;
741 
742         if (dir == XFER_RECEIVE) {
743                 pointer_reg = ATMEL_PDC_RPR;
744                 counter_reg = ATMEL_PDC_RCR;
745         } else {
746                 pointer_reg = ATMEL_PDC_TPR;
747                 counter_reg = ATMEL_PDC_TCR;
748         }
749 
750         if (buf_nb == PDC_SECOND_BUF) {
751                 pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
752                 counter_reg += ATMEL_PDC_SCND_BUF_OFF;
753         }
754 
755         if (!host->caps.has_rwproof) {
756                 buf_size = host->buf_size;
757                 atmci_writel(host, pointer_reg, host->buf_phys_addr);
758         } else {
759                 buf_size = sg_dma_len(host->sg);
760                 atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
761         }
762 
763         if (host->data_size <= buf_size) {
764                 if (host->data_size & 0x3) {
765                         /* If size is different from modulo 4, transfer bytes */
766                         atmci_writel(host, counter_reg, host->data_size);
767                         atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
768                 } else {
769                         /* Else transfer 32-bits words */
770                         atmci_writel(host, counter_reg, host->data_size / 4);
771                 }
772                 host->data_size = 0;
773         } else {
774                 /* We assume the size of a page is 32-bits aligned */
775                 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
776                 host->data_size -= sg_dma_len(host->sg);
777                 if (host->data_size)
778                         host->sg = sg_next(host->sg);
779         }
780 }
781 
782 /*
783  * Configure PDC buffer according to the data size ie configuring one or two
784  * buffers. Don't use this function if you want to configure only the second
785  * buffer. In this case, use atmci_pdc_set_single_buf.
786  */
787 static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
788 {
789         atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
790         if (host->data_size)
791                 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
792 }
793 
794 /*
795  * Unmap sg lists, called when transfer is finished.
796  */
797 static void atmci_pdc_cleanup(struct atmel_mci *host)
798 {
799         struct mmc_data         *data = host->data;
800 
801         if (data)
802                 dma_unmap_sg(&host->pdev->dev,
803                                 data->sg, data->sg_len,
804                                 ((data->flags & MMC_DATA_WRITE)
805                                  ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
806 }
807 
808 /*
809  * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
810  * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
811  * interrupt needed for both transfer directions.
812  */
813 static void atmci_pdc_complete(struct atmel_mci *host)
814 {
815         int transfer_size = host->data->blocks * host->data->blksz;
816         int i;
817 
818         atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
819 
820         if ((!host->caps.has_rwproof)
821             && (host->data->flags & MMC_DATA_READ)) {
822                 if (host->caps.has_bad_data_ordering)
823                         for (i = 0; i < transfer_size; i++)
824                                 host->buffer[i] = swab32(host->buffer[i]);
825                 sg_copy_from_buffer(host->data->sg, host->data->sg_len,
826                                     host->buffer, transfer_size);
827         }
828 
829         atmci_pdc_cleanup(host);
830 
831         dev_dbg(&host->pdev->dev, "(%s) set pending xfer complete\n", __func__);
832         atmci_set_pending(host, EVENT_XFER_COMPLETE);
833         tasklet_schedule(&host->tasklet);
834 }
835 
836 static void atmci_dma_cleanup(struct atmel_mci *host)
837 {
838         struct mmc_data                 *data = host->data;
839 
840         if (data)
841                 dma_unmap_sg(host->dma.chan->device->dev,
842                                 data->sg, data->sg_len,
843                                 ((data->flags & MMC_DATA_WRITE)
844                                  ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
845 }
846 
847 /*
848  * This function is called by the DMA driver from tasklet context.
849  */
850 static void atmci_dma_complete(void *arg)
851 {
852         struct atmel_mci        *host = arg;
853         struct mmc_data         *data = host->data;
854 
855         dev_vdbg(&host->pdev->dev, "DMA complete\n");
856 
857         if (host->caps.has_dma_conf_reg)
858                 /* Disable DMA hardware handshaking on MCI */
859                 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
860 
861         atmci_dma_cleanup(host);
862 
863         /*
864          * If the card was removed, data will be NULL. No point trying
865          * to send the stop command or waiting for NBUSY in this case.
866          */
867         if (data) {
868                 dev_dbg(&host->pdev->dev,
869                         "(%s) set pending xfer complete\n", __func__);
870                 atmci_set_pending(host, EVENT_XFER_COMPLETE);
871                 tasklet_schedule(&host->tasklet);
872 
873                 /*
874                  * Regardless of what the documentation says, we have
875                  * to wait for NOTBUSY even after block read
876                  * operations.
877                  *
878                  * When the DMA transfer is complete, the controller
879                  * may still be reading the CRC from the card, i.e.
880                  * the data transfer is still in progress and we
881                  * haven't seen all the potential error bits yet.
882                  *
883                  * The interrupt handler will schedule a different
884                  * tasklet to finish things up when the data transfer
885                  * is completely done.
886                  *
887                  * We may not complete the mmc request here anyway
888                  * because the mmc layer may call back and cause us to
889                  * violate the "don't submit new operations from the
890                  * completion callback" rule of the dma engine
891                  * framework.
892                  */
893                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
894         }
895 }
896 
897 /*
898  * Returns a mask of interrupt flags to be enabled after the whole
899  * request has been prepared.
900  */
901 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
902 {
903         u32 iflags;
904 
905         data->error = -EINPROGRESS;
906 
907         host->sg = data->sg;
908         host->sg_len = data->sg_len;
909         host->data = data;
910         host->data_chan = NULL;
911 
912         iflags = ATMCI_DATA_ERROR_FLAGS;
913 
914         /*
915          * Errata: MMC data write operation with less than 12
916          * bytes is impossible.
917          *
918          * Errata: MCI Transmit Data Register (TDR) FIFO
919          * corruption when length is not multiple of 4.
920          */
921         if (data->blocks * data->blksz < 12
922                         || (data->blocks * data->blksz) & 3)
923                 host->need_reset = true;
924 
925         host->pio_offset = 0;
926         if (data->flags & MMC_DATA_READ)
927                 iflags |= ATMCI_RXRDY;
928         else
929                 iflags |= ATMCI_TXRDY;
930 
931         return iflags;
932 }
933 
934 /*
935  * Set interrupt flags and set block length into the MCI mode register even
936  * if this value is also accessible in the MCI block register. It seems to be
937  * necessary before the High Speed MCI version. It also map sg and configure
938  * PDC registers.
939  */
940 static u32
941 atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
942 {
943         u32 iflags, tmp;
944         unsigned int sg_len;
945         enum dma_data_direction dir;
946         int i;
947 
948         data->error = -EINPROGRESS;
949 
950         host->data = data;
951         host->sg = data->sg;
952         iflags = ATMCI_DATA_ERROR_FLAGS;
953 
954         /* Enable pdc mode */
955         atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
956 
957         if (data->flags & MMC_DATA_READ) {
958                 dir = DMA_FROM_DEVICE;
959                 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
960         } else {
961                 dir = DMA_TO_DEVICE;
962                 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
963         }
964 
965         /* Set BLKLEN */
966         tmp = atmci_readl(host, ATMCI_MR);
967         tmp &= 0x0000ffff;
968         tmp |= ATMCI_BLKLEN(data->blksz);
969         atmci_writel(host, ATMCI_MR, tmp);
970 
971         /* Configure PDC */
972         host->data_size = data->blocks * data->blksz;
973         sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir);
974 
975         if ((!host->caps.has_rwproof)
976             && (host->data->flags & MMC_DATA_WRITE)) {
977                 sg_copy_to_buffer(host->data->sg, host->data->sg_len,
978                                   host->buffer, host->data_size);
979                 if (host->caps.has_bad_data_ordering)
980                         for (i = 0; i < host->data_size; i++)
981                                 host->buffer[i] = swab32(host->buffer[i]);
982         }
983 
984         if (host->data_size)
985                 atmci_pdc_set_both_buf(host,
986                         ((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT));
987 
988         return iflags;
989 }
990 
991 static u32
992 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
993 {
994         struct dma_chan                 *chan;
995         struct dma_async_tx_descriptor  *desc;
996         struct scatterlist              *sg;
997         unsigned int                    i;
998         enum dma_data_direction         direction;
999         enum dma_transfer_direction     slave_dirn;
1000         unsigned int                    sglen;
1001         u32                             maxburst;
1002         u32 iflags;
1003 
1004         data->error = -EINPROGRESS;
1005 
1006         WARN_ON(host->data);
1007         host->sg = NULL;
1008         host->data = data;
1009 
1010         iflags = ATMCI_DATA_ERROR_FLAGS;
1011 
1012         /*
1013          * We don't do DMA on "complex" transfers, i.e. with
1014          * non-word-aligned buffers or lengths. Also, we don't bother
1015          * with all the DMA setup overhead for short transfers.
1016          */
1017         if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
1018                 return atmci_prepare_data(host, data);
1019         if (data->blksz & 3)
1020                 return atmci_prepare_data(host, data);
1021 
1022         for_each_sg(data->sg, sg, data->sg_len, i) {
1023                 if (sg->offset & 3 || sg->length & 3)
1024                         return atmci_prepare_data(host, data);
1025         }
1026 
1027         /* If we don't have a channel, we can't do DMA */
1028         chan = host->dma.chan;
1029         if (chan)
1030                 host->data_chan = chan;
1031 
1032         if (!chan)
1033                 return -ENODEV;
1034 
1035         if (data->flags & MMC_DATA_READ) {
1036                 direction = DMA_FROM_DEVICE;
1037                 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
1038                 maxburst = atmci_convert_chksize(host->dma_conf.src_maxburst);
1039         } else {
1040                 direction = DMA_TO_DEVICE;
1041                 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
1042                 maxburst = atmci_convert_chksize(host->dma_conf.dst_maxburst);
1043         }
1044 
1045         if (host->caps.has_dma_conf_reg)
1046                 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) |
1047                         ATMCI_DMAEN);
1048 
1049         sglen = dma_map_sg(chan->device->dev, data->sg,
1050                         data->sg_len, direction);
1051 
1052         dmaengine_slave_config(chan, &host->dma_conf);
1053         desc = dmaengine_prep_slave_sg(chan,
1054                         data->sg, sglen, slave_dirn,
1055                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1056         if (!desc)
1057                 goto unmap_exit;
1058 
1059         host->dma.data_desc = desc;
1060         desc->callback = atmci_dma_complete;
1061         desc->callback_param = host;
1062 
1063         return iflags;
1064 unmap_exit:
1065         dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction);
1066         return -ENOMEM;
1067 }
1068 
1069 static void
1070 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
1071 {
1072         return;
1073 }
1074 
1075 /*
1076  * Start PDC according to transfer direction.
1077  */
1078 static void
1079 atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1080 {
1081         if (data->flags & MMC_DATA_READ)
1082                 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1083         else
1084                 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1085 }
1086 
1087 static void
1088 atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
1089 {
1090         struct dma_chan                 *chan = host->data_chan;
1091         struct dma_async_tx_descriptor  *desc = host->dma.data_desc;
1092 
1093         if (chan) {
1094                 dmaengine_submit(desc);
1095                 dma_async_issue_pending(chan);
1096         }
1097 }
1098 
1099 static void atmci_stop_transfer(struct atmel_mci *host)
1100 {
1101         dev_dbg(&host->pdev->dev,
1102                 "(%s) set pending xfer complete\n", __func__);
1103         atmci_set_pending(host, EVENT_XFER_COMPLETE);
1104         atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1105 }
1106 
1107 /*
1108  * Stop data transfer because error(s) occurred.
1109  */
1110 static void atmci_stop_transfer_pdc(struct atmel_mci *host)
1111 {
1112         atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
1113 }
1114 
1115 static void atmci_stop_transfer_dma(struct atmel_mci *host)
1116 {
1117         struct dma_chan *chan = host->data_chan;
1118 
1119         if (chan) {
1120                 dmaengine_terminate_all(chan);
1121                 atmci_dma_cleanup(host);
1122         } else {
1123                 /* Data transfer was stopped by the interrupt handler */
1124                 dev_dbg(&host->pdev->dev,
1125                         "(%s) set pending xfer complete\n", __func__);
1126                 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1127                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1128         }
1129 }
1130 
1131 /*
1132  * Start a request: prepare data if needed, prepare the command and activate
1133  * interrupts.
1134  */
1135 static void atmci_start_request(struct atmel_mci *host,
1136                 struct atmel_mci_slot *slot)
1137 {
1138         struct mmc_request      *mrq;
1139         struct mmc_command      *cmd;
1140         struct mmc_data         *data;
1141         u32                     iflags;
1142         u32                     cmdflags;
1143 
1144         mrq = slot->mrq;
1145         host->cur_slot = slot;
1146         host->mrq = mrq;
1147 
1148         host->pending_events = 0;
1149         host->completed_events = 0;
1150         host->cmd_status = 0;
1151         host->data_status = 0;
1152 
1153         dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode);
1154 
1155         if (host->need_reset || host->caps.need_reset_after_xfer) {
1156                 iflags = atmci_readl(host, ATMCI_IMR);
1157                 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
1158                 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1159                 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1160                 atmci_writel(host, ATMCI_MR, host->mode_reg);
1161                 if (host->caps.has_cfg_reg)
1162                         atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1163                 atmci_writel(host, ATMCI_IER, iflags);
1164                 host->need_reset = false;
1165         }
1166         atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
1167 
1168         iflags = atmci_readl(host, ATMCI_IMR);
1169         if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1170                 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
1171                                 iflags);
1172 
1173         if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
1174                 /* Send init sequence (74 clock cycles) */
1175                 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
1176                 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
1177                         cpu_relax();
1178         }
1179         iflags = 0;
1180         data = mrq->data;
1181         if (data) {
1182                 atmci_set_timeout(host, slot, data);
1183 
1184                 /* Must set block count/size before sending command */
1185                 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
1186                                 | ATMCI_BLKLEN(data->blksz));
1187                 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
1188                         ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
1189 
1190                 iflags |= host->prepare_data(host, data);
1191         }
1192 
1193         iflags |= ATMCI_CMDRDY;
1194         cmd = mrq->cmd;
1195         cmdflags = atmci_prepare_command(slot->mmc, cmd);
1196 
1197         /*
1198          * DMA transfer should be started before sending the command to avoid
1199          * unexpected errors especially for read operations in SDIO mode.
1200          * Unfortunately, in PDC mode, command has to be sent before starting
1201          * the transfer.
1202          */
1203         if (host->submit_data != &atmci_submit_data_dma)
1204                 atmci_send_command(host, cmd, cmdflags);
1205 
1206         if (data)
1207                 host->submit_data(host, data);
1208 
1209         if (host->submit_data == &atmci_submit_data_dma)
1210                 atmci_send_command(host, cmd, cmdflags);
1211 
1212         if (mrq->stop) {
1213                 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
1214                 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
1215                 if (!(data->flags & MMC_DATA_WRITE))
1216                         host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
1217                 if (data->flags & MMC_DATA_STREAM)
1218                         host->stop_cmdr |= ATMCI_CMDR_STREAM;
1219                 else
1220                         host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
1221         }
1222 
1223         /*
1224          * We could have enabled interrupts earlier, but I suspect
1225          * that would open up a nice can of interesting race
1226          * conditions (e.g. command and data complete, but stop not
1227          * prepared yet.)
1228          */
1229         atmci_writel(host, ATMCI_IER, iflags);
1230 
1231         mod_timer(&host->timer, jiffies +  msecs_to_jiffies(2000));
1232 }
1233 
1234 static void atmci_queue_request(struct atmel_mci *host,
1235                 struct atmel_mci_slot *slot, struct mmc_request *mrq)
1236 {
1237         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1238                         host->state);
1239 
1240         spin_lock_bh(&host->lock);
1241         slot->mrq = mrq;
1242         if (host->state == STATE_IDLE) {
1243                 host->state = STATE_SENDING_CMD;
1244                 atmci_start_request(host, slot);
1245         } else {
1246                 dev_dbg(&host->pdev->dev, "queue request\n");
1247                 list_add_tail(&slot->queue_node, &host->queue);
1248         }
1249         spin_unlock_bh(&host->lock);
1250 }
1251 
1252 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1253 {
1254         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1255         struct atmel_mci        *host = slot->host;
1256         struct mmc_data         *data;
1257 
1258         WARN_ON(slot->mrq);
1259         dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode);
1260 
1261         pm_runtime_get_sync(&host->pdev->dev);
1262 
1263         /*
1264          * We may "know" the card is gone even though there's still an
1265          * electrical connection. If so, we really need to communicate
1266          * this to the MMC core since there won't be any more
1267          * interrupts as the card is completely removed. Otherwise,
1268          * the MMC core might believe the card is still there even
1269          * though the card was just removed very slowly.
1270          */
1271         if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1272                 mrq->cmd->error = -ENOMEDIUM;
1273                 mmc_request_done(mmc, mrq);
1274                 return;
1275         }
1276 
1277         /* We don't support multiple blocks of weird lengths. */
1278         data = mrq->data;
1279         if (data && data->blocks > 1 && data->blksz & 3) {
1280                 mrq->cmd->error = -EINVAL;
1281                 mmc_request_done(mmc, mrq);
1282         }
1283 
1284         atmci_queue_request(host, slot, mrq);
1285 }
1286 
1287 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1288 {
1289         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1290         struct atmel_mci        *host = slot->host;
1291         unsigned int            i;
1292 
1293         pm_runtime_get_sync(&host->pdev->dev);
1294 
1295         slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
1296         switch (ios->bus_width) {
1297         case MMC_BUS_WIDTH_1:
1298                 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
1299                 break;
1300         case MMC_BUS_WIDTH_4:
1301                 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
1302                 break;
1303         }
1304 
1305         if (ios->clock) {
1306                 unsigned int clock_min = ~0U;
1307                 u32 clkdiv;
1308 
1309                 spin_lock_bh(&host->lock);
1310                 if (!host->mode_reg) {
1311                         atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1312                         atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1313                         if (host->caps.has_cfg_reg)
1314                                 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1315                 }
1316 
1317                 /*
1318                  * Use mirror of ios->clock to prevent race with mmc
1319                  * core ios update when finding the minimum.
1320                  */
1321                 slot->clock = ios->clock;
1322                 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1323                         if (host->slot[i] && host->slot[i]->clock
1324                                         && host->slot[i]->clock < clock_min)
1325                                 clock_min = host->slot[i]->clock;
1326                 }
1327 
1328                 /* Calculate clock divider */
1329                 if (host->caps.has_odd_clk_div) {
1330                         clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
1331                         if (clkdiv > 511) {
1332                                 dev_warn(&mmc->class_dev,
1333                                          "clock %u too slow; using %lu\n",
1334                                          clock_min, host->bus_hz / (511 + 2));
1335                                 clkdiv = 511;
1336                         }
1337                         host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
1338                                          | ATMCI_MR_CLKODD(clkdiv & 1);
1339                 } else {
1340                         clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
1341                         if (clkdiv > 255) {
1342                                 dev_warn(&mmc->class_dev,
1343                                          "clock %u too slow; using %lu\n",
1344                                          clock_min, host->bus_hz / (2 * 256));
1345                                 clkdiv = 255;
1346                         }
1347                         host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
1348                 }
1349 
1350                 /*
1351                  * WRPROOF and RDPROOF prevent overruns/underruns by
1352                  * stopping the clock when the FIFO is full/empty.
1353                  * This state is not expected to last for long.
1354                  */
1355                 if (host->caps.has_rwproof)
1356                         host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
1357 
1358                 if (host->caps.has_cfg_reg) {
1359                         /* setup High Speed mode in relation with card capacity */
1360                         if (ios->timing == MMC_TIMING_SD_HS)
1361                                 host->cfg_reg |= ATMCI_CFG_HSMODE;
1362                         else
1363                                 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
1364                 }
1365 
1366                 if (list_empty(&host->queue)) {
1367                         atmci_writel(host, ATMCI_MR, host->mode_reg);
1368                         if (host->caps.has_cfg_reg)
1369                                 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1370                 } else {
1371                         host->need_clock_update = true;
1372                 }
1373 
1374                 spin_unlock_bh(&host->lock);
1375         } else {
1376                 bool any_slot_active = false;
1377 
1378                 spin_lock_bh(&host->lock);
1379                 slot->clock = 0;
1380                 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1381                         if (host->slot[i] && host->slot[i]->clock) {
1382                                 any_slot_active = true;
1383                                 break;
1384                         }
1385                 }
1386                 if (!any_slot_active) {
1387                         atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
1388                         if (host->mode_reg) {
1389                                 atmci_readl(host, ATMCI_MR);
1390                         }
1391                         host->mode_reg = 0;
1392                 }
1393                 spin_unlock_bh(&host->lock);
1394         }
1395 
1396         switch (ios->power_mode) {
1397         case MMC_POWER_OFF:
1398                 if (!IS_ERR(mmc->supply.vmmc))
1399                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1400                 break;
1401         case MMC_POWER_UP:
1402                 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1403                 if (!IS_ERR(mmc->supply.vmmc))
1404                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1405                 break;
1406         default:
1407                 /*
1408                  * TODO: None of the currently available AVR32-based
1409                  * boards allow MMC power to be turned off. Implement
1410                  * power control when this can be tested properly.
1411                  *
1412                  * We also need to hook this into the clock management
1413                  * somehow so that newly inserted cards aren't
1414                  * subjected to a fast clock before we have a chance
1415                  * to figure out what the maximum rate is. Currently,
1416                  * there's no way to avoid this, and there never will
1417                  * be for boards that don't support power control.
1418                  */
1419                 break;
1420         }
1421 
1422         pm_runtime_mark_last_busy(&host->pdev->dev);
1423         pm_runtime_put_autosuspend(&host->pdev->dev);
1424 }
1425 
1426 static int atmci_get_ro(struct mmc_host *mmc)
1427 {
1428         int                     read_only = -ENOSYS;
1429         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1430 
1431         if (gpio_is_valid(slot->wp_pin)) {
1432                 read_only = gpio_get_value(slot->wp_pin);
1433                 dev_dbg(&mmc->class_dev, "card is %s\n",
1434                                 read_only ? "read-only" : "read-write");
1435         }
1436 
1437         return read_only;
1438 }
1439 
1440 static int atmci_get_cd(struct mmc_host *mmc)
1441 {
1442         int                     present = -ENOSYS;
1443         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1444 
1445         if (gpio_is_valid(slot->detect_pin)) {
1446                 present = !(gpio_get_value(slot->detect_pin) ^
1447                             slot->detect_is_active_high);
1448                 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1449                                 present ? "" : "not ");
1450         }
1451 
1452         return present;
1453 }
1454 
1455 static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1456 {
1457         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1458         struct atmel_mci        *host = slot->host;
1459 
1460         if (enable)
1461                 atmci_writel(host, ATMCI_IER, slot->sdio_irq);
1462         else
1463                 atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
1464 }
1465 
1466 static const struct mmc_host_ops atmci_ops = {
1467         .request        = atmci_request,
1468         .set_ios        = atmci_set_ios,
1469         .get_ro         = atmci_get_ro,
1470         .get_cd         = atmci_get_cd,
1471         .enable_sdio_irq = atmci_enable_sdio_irq,
1472 };
1473 
1474 /* Called with host->lock held */
1475 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1476         __releases(&host->lock)
1477         __acquires(&host->lock)
1478 {
1479         struct atmel_mci_slot   *slot = NULL;
1480         struct mmc_host         *prev_mmc = host->cur_slot->mmc;
1481 
1482         WARN_ON(host->cmd || host->data);
1483 
1484         /*
1485          * Update the MMC clock rate if necessary. This may be
1486          * necessary if set_ios() is called when a different slot is
1487          * busy transferring data.
1488          */
1489         if (host->need_clock_update) {
1490                 atmci_writel(host, ATMCI_MR, host->mode_reg);
1491                 if (host->caps.has_cfg_reg)
1492                         atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1493         }
1494 
1495         host->cur_slot->mrq = NULL;
1496         host->mrq = NULL;
1497         if (!list_empty(&host->queue)) {
1498                 slot = list_entry(host->queue.next,
1499                                 struct atmel_mci_slot, queue_node);
1500                 list_del(&slot->queue_node);
1501                 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1502                                 mmc_hostname(slot->mmc));
1503                 host->state = STATE_SENDING_CMD;
1504                 atmci_start_request(host, slot);
1505         } else {
1506                 dev_vdbg(&host->pdev->dev, "list empty\n");
1507                 host->state = STATE_IDLE;
1508         }
1509 
1510         del_timer(&host->timer);
1511 
1512         spin_unlock(&host->lock);
1513         mmc_request_done(prev_mmc, mrq);
1514         spin_lock(&host->lock);
1515 
1516         pm_runtime_mark_last_busy(&host->pdev->dev);
1517         pm_runtime_put_autosuspend(&host->pdev->dev);
1518 }
1519 
1520 static void atmci_command_complete(struct atmel_mci *host,
1521                         struct mmc_command *cmd)
1522 {
1523         u32             status = host->cmd_status;
1524 
1525         /* Read the response from the card (up to 16 bytes) */
1526         cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1527         cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1528         cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1529         cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
1530 
1531         if (status & ATMCI_RTOE)
1532                 cmd->error = -ETIMEDOUT;
1533         else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
1534                 cmd->error = -EILSEQ;
1535         else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
1536                 cmd->error = -EIO;
1537         else if (host->mrq->data && (host->mrq->data->blksz & 3)) {
1538                 if (host->caps.need_blksz_mul_4) {
1539                         cmd->error = -EINVAL;
1540                         host->need_reset = 1;
1541                 }
1542         } else
1543                 cmd->error = 0;
1544 }
1545 
1546 static void atmci_detect_change(unsigned long data)
1547 {
1548         struct atmel_mci_slot   *slot = (struct atmel_mci_slot *)data;
1549         bool                    present;
1550         bool                    present_old;
1551 
1552         /*
1553          * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1554          * freeing the interrupt. We must not re-enable the interrupt
1555          * if it has been freed, and if we're shutting down, it
1556          * doesn't really matter whether the card is present or not.
1557          */
1558         smp_rmb();
1559         if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1560                 return;
1561 
1562         enable_irq(gpio_to_irq(slot->detect_pin));
1563         present = !(gpio_get_value(slot->detect_pin) ^
1564                     slot->detect_is_active_high);
1565         present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1566 
1567         dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1568                         present, present_old);
1569 
1570         if (present != present_old) {
1571                 struct atmel_mci        *host = slot->host;
1572                 struct mmc_request      *mrq;
1573 
1574                 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1575                         present ? "inserted" : "removed");
1576 
1577                 spin_lock(&host->lock);
1578 
1579                 if (!present)
1580                         clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1581                 else
1582                         set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1583 
1584                 /* Clean up queue if present */
1585                 mrq = slot->mrq;
1586                 if (mrq) {
1587                         if (mrq == host->mrq) {
1588                                 /*
1589                                  * Reset controller to terminate any ongoing
1590                                  * commands or data transfers.
1591                                  */
1592                                 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1593                                 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1594                                 atmci_writel(host, ATMCI_MR, host->mode_reg);
1595                                 if (host->caps.has_cfg_reg)
1596                                         atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1597 
1598                                 host->data = NULL;
1599                                 host->cmd = NULL;
1600 
1601                                 switch (host->state) {
1602                                 case STATE_IDLE:
1603                                         break;
1604                                 case STATE_SENDING_CMD:
1605                                         mrq->cmd->error = -ENOMEDIUM;
1606                                         if (mrq->data)
1607                                                 host->stop_transfer(host);
1608                                         break;
1609                                 case STATE_DATA_XFER:
1610                                         mrq->data->error = -ENOMEDIUM;
1611                                         host->stop_transfer(host);
1612                                         break;
1613                                 case STATE_WAITING_NOTBUSY:
1614                                         mrq->data->error = -ENOMEDIUM;
1615                                         break;
1616                                 case STATE_SENDING_STOP:
1617                                         mrq->stop->error = -ENOMEDIUM;
1618                                         break;
1619                                 case STATE_END_REQUEST:
1620                                         break;
1621                                 }
1622 
1623                                 atmci_request_end(host, mrq);
1624                         } else {
1625                                 list_del(&slot->queue_node);
1626                                 mrq->cmd->error = -ENOMEDIUM;
1627                                 if (mrq->data)
1628                                         mrq->data->error = -ENOMEDIUM;
1629                                 if (mrq->stop)
1630                                         mrq->stop->error = -ENOMEDIUM;
1631 
1632                                 spin_unlock(&host->lock);
1633                                 mmc_request_done(slot->mmc, mrq);
1634                                 spin_lock(&host->lock);
1635                         }
1636                 }
1637                 spin_unlock(&host->lock);
1638 
1639                 mmc_detect_change(slot->mmc, 0);
1640         }
1641 }
1642 
1643 static void atmci_tasklet_func(unsigned long priv)
1644 {
1645         struct atmel_mci        *host = (struct atmel_mci *)priv;
1646         struct mmc_request      *mrq = host->mrq;
1647         struct mmc_data         *data = host->data;
1648         enum atmel_mci_state    state = host->state;
1649         enum atmel_mci_state    prev_state;
1650         u32                     status;
1651 
1652         spin_lock(&host->lock);
1653 
1654         state = host->state;
1655 
1656         dev_vdbg(&host->pdev->dev,
1657                 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1658                 state, host->pending_events, host->completed_events,
1659                 atmci_readl(host, ATMCI_IMR));
1660 
1661         do {
1662                 prev_state = state;
1663                 dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state);
1664 
1665                 switch (state) {
1666                 case STATE_IDLE:
1667                         break;
1668 
1669                 case STATE_SENDING_CMD:
1670                         /*
1671                          * Command has been sent, we are waiting for command
1672                          * ready. Then we have three next states possible:
1673                          * END_REQUEST by default, WAITING_NOTBUSY if it's a
1674                          * command needing it or DATA_XFER if there is data.
1675                          */
1676                         dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1677                         if (!atmci_test_and_clear_pending(host,
1678                                                 EVENT_CMD_RDY))
1679                                 break;
1680 
1681                         dev_dbg(&host->pdev->dev, "set completed cmd ready\n");
1682                         host->cmd = NULL;
1683                         atmci_set_completed(host, EVENT_CMD_RDY);
1684                         atmci_command_complete(host, mrq->cmd);
1685                         if (mrq->data) {
1686                                 dev_dbg(&host->pdev->dev,
1687                                         "command with data transfer");
1688                                 /*
1689                                  * If there is a command error don't start
1690                                  * data transfer.
1691                                  */
1692                                 if (mrq->cmd->error) {
1693                                         host->stop_transfer(host);
1694                                         host->data = NULL;
1695                                         atmci_writel(host, ATMCI_IDR,
1696                                                      ATMCI_TXRDY | ATMCI_RXRDY
1697                                                      | ATMCI_DATA_ERROR_FLAGS);
1698                                         state = STATE_END_REQUEST;
1699                                 } else
1700                                         state = STATE_DATA_XFER;
1701                         } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) {
1702                                 dev_dbg(&host->pdev->dev,
1703                                         "command response need waiting notbusy");
1704                                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1705                                 state = STATE_WAITING_NOTBUSY;
1706                         } else
1707                                 state = STATE_END_REQUEST;
1708 
1709                         break;
1710 
1711                 case STATE_DATA_XFER:
1712                         if (atmci_test_and_clear_pending(host,
1713                                                 EVENT_DATA_ERROR)) {
1714                                 dev_dbg(&host->pdev->dev, "set completed data error\n");
1715                                 atmci_set_completed(host, EVENT_DATA_ERROR);
1716                                 state = STATE_END_REQUEST;
1717                                 break;
1718                         }
1719 
1720                         /*
1721                          * A data transfer is in progress. The event expected
1722                          * to move to the next state depends of data transfer
1723                          * type (PDC or DMA). Once transfer done we can move
1724                          * to the next step which is WAITING_NOTBUSY in write
1725                          * case and directly SENDING_STOP in read case.
1726                          */
1727                         dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n");
1728                         if (!atmci_test_and_clear_pending(host,
1729                                                 EVENT_XFER_COMPLETE))
1730                                 break;
1731 
1732                         dev_dbg(&host->pdev->dev,
1733                                 "(%s) set completed xfer complete\n",
1734                                 __func__);
1735                         atmci_set_completed(host, EVENT_XFER_COMPLETE);
1736 
1737                         if (host->caps.need_notbusy_for_read_ops ||
1738                            (host->data->flags & MMC_DATA_WRITE)) {
1739                                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1740                                 state = STATE_WAITING_NOTBUSY;
1741                         } else if (host->mrq->stop) {
1742                                 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
1743                                 atmci_send_stop_cmd(host, data);
1744                                 state = STATE_SENDING_STOP;
1745                         } else {
1746                                 host->data = NULL;
1747                                 data->bytes_xfered = data->blocks * data->blksz;
1748                                 data->error = 0;
1749                                 state = STATE_END_REQUEST;
1750                         }
1751                         break;
1752 
1753                 case STATE_WAITING_NOTBUSY:
1754                         /*
1755                          * We can be in the state for two reasons: a command
1756                          * requiring waiting not busy signal (stop command
1757                          * included) or a write operation. In the latest case,
1758                          * we need to send a stop command.
1759                          */
1760                         dev_dbg(&host->pdev->dev, "FSM: not busy?\n");
1761                         if (!atmci_test_and_clear_pending(host,
1762                                                 EVENT_NOTBUSY))
1763                                 break;
1764 
1765                         dev_dbg(&host->pdev->dev, "set completed not busy\n");
1766                         atmci_set_completed(host, EVENT_NOTBUSY);
1767 
1768                         if (host->data) {
1769                                 /*
1770                                  * For some commands such as CMD53, even if
1771                                  * there is data transfer, there is no stop
1772                                  * command to send.
1773                                  */
1774                                 if (host->mrq->stop) {
1775                                         atmci_writel(host, ATMCI_IER,
1776                                                      ATMCI_CMDRDY);
1777                                         atmci_send_stop_cmd(host, data);
1778                                         state = STATE_SENDING_STOP;
1779                                 } else {
1780                                         host->data = NULL;
1781                                         data->bytes_xfered = data->blocks
1782                                                              * data->blksz;
1783                                         data->error = 0;
1784                                         state = STATE_END_REQUEST;
1785                                 }
1786                         } else
1787                                 state = STATE_END_REQUEST;
1788                         break;
1789 
1790                 case STATE_SENDING_STOP:
1791                         /*
1792                          * In this state, it is important to set host->data to
1793                          * NULL (which is tested in the waiting notbusy state)
1794                          * in order to go to the end request state instead of
1795                          * sending stop again.
1796                          */
1797                         dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1798                         if (!atmci_test_and_clear_pending(host,
1799                                                 EVENT_CMD_RDY))
1800                                 break;
1801 
1802                         dev_dbg(&host->pdev->dev, "FSM: cmd ready\n");
1803                         host->cmd = NULL;
1804                         data->bytes_xfered = data->blocks * data->blksz;
1805                         data->error = 0;
1806                         atmci_command_complete(host, mrq->stop);
1807                         if (mrq->stop->error) {
1808                                 host->stop_transfer(host);
1809                                 atmci_writel(host, ATMCI_IDR,
1810                                              ATMCI_TXRDY | ATMCI_RXRDY
1811                                              | ATMCI_DATA_ERROR_FLAGS);
1812                                 state = STATE_END_REQUEST;
1813                         } else {
1814                                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1815                                 state = STATE_WAITING_NOTBUSY;
1816                         }
1817                         host->data = NULL;
1818                         break;
1819 
1820                 case STATE_END_REQUEST:
1821                         atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY
1822                                            | ATMCI_DATA_ERROR_FLAGS);
1823                         status = host->data_status;
1824                         if (unlikely(status)) {
1825                                 host->stop_transfer(host);
1826                                 host->data = NULL;
1827                                 if (data) {
1828                                         if (status & ATMCI_DTOE) {
1829                                                 data->error = -ETIMEDOUT;
1830                                         } else if (status & ATMCI_DCRCE) {
1831                                                 data->error = -EILSEQ;
1832                                         } else {
1833                                                 data->error = -EIO;
1834                                         }
1835                                 }
1836                         }
1837 
1838                         atmci_request_end(host, host->mrq);
1839                         state = STATE_IDLE;
1840                         break;
1841                 }
1842         } while (state != prev_state);
1843 
1844         host->state = state;
1845 
1846         spin_unlock(&host->lock);
1847 }
1848 
1849 static void atmci_read_data_pio(struct atmel_mci *host)
1850 {
1851         struct scatterlist      *sg = host->sg;
1852         void                    *buf = sg_virt(sg);
1853         unsigned int            offset = host->pio_offset;
1854         struct mmc_data         *data = host->data;
1855         u32                     value;
1856         u32                     status;
1857         unsigned int            nbytes = 0;
1858 
1859         do {
1860                 value = atmci_readl(host, ATMCI_RDR);
1861                 if (likely(offset + 4 <= sg->length)) {
1862                         put_unaligned(value, (u32 *)(buf + offset));
1863 
1864                         offset += 4;
1865                         nbytes += 4;
1866 
1867                         if (offset == sg->length) {
1868                                 flush_dcache_page(sg_page(sg));
1869                                 host->sg = sg = sg_next(sg);
1870                                 host->sg_len--;
1871                                 if (!sg || !host->sg_len)
1872                                         goto done;
1873 
1874                                 offset = 0;
1875                                 buf = sg_virt(sg);
1876                         }
1877                 } else {
1878                         unsigned int remaining = sg->length - offset;
1879                         memcpy(buf + offset, &value, remaining);
1880                         nbytes += remaining;
1881 
1882                         flush_dcache_page(sg_page(sg));
1883                         host->sg = sg = sg_next(sg);
1884                         host->sg_len--;
1885                         if (!sg || !host->sg_len)
1886                                 goto done;
1887 
1888                         offset = 4 - remaining;
1889                         buf = sg_virt(sg);
1890                         memcpy(buf, (u8 *)&value + remaining, offset);
1891                         nbytes += offset;
1892                 }
1893 
1894                 status = atmci_readl(host, ATMCI_SR);
1895                 if (status & ATMCI_DATA_ERROR_FLAGS) {
1896                         atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
1897                                                 | ATMCI_DATA_ERROR_FLAGS));
1898                         host->data_status = status;
1899                         data->bytes_xfered += nbytes;
1900                         return;
1901                 }
1902         } while (status & ATMCI_RXRDY);
1903 
1904         host->pio_offset = offset;
1905         data->bytes_xfered += nbytes;
1906 
1907         return;
1908 
1909 done:
1910         atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
1911         atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1912         data->bytes_xfered += nbytes;
1913         smp_wmb();
1914         atmci_set_pending(host, EVENT_XFER_COMPLETE);
1915 }
1916 
1917 static void atmci_write_data_pio(struct atmel_mci *host)
1918 {
1919         struct scatterlist      *sg = host->sg;
1920         void                    *buf = sg_virt(sg);
1921         unsigned int            offset = host->pio_offset;
1922         struct mmc_data         *data = host->data;
1923         u32                     value;
1924         u32                     status;
1925         unsigned int            nbytes = 0;
1926 
1927         do {
1928                 if (likely(offset + 4 <= sg->length)) {
1929                         value = get_unaligned((u32 *)(buf + offset));
1930                         atmci_writel(host, ATMCI_TDR, value);
1931 
1932                         offset += 4;
1933                         nbytes += 4;
1934                         if (offset == sg->length) {
1935                                 host->sg = sg = sg_next(sg);
1936                                 host->sg_len--;
1937                                 if (!sg || !host->sg_len)
1938                                         goto done;
1939 
1940                                 offset = 0;
1941                                 buf = sg_virt(sg);
1942                         }
1943                 } else {
1944                         unsigned int remaining = sg->length - offset;
1945 
1946                         value = 0;
1947                         memcpy(&value, buf + offset, remaining);
1948                         nbytes += remaining;
1949 
1950                         host->sg = sg = sg_next(sg);
1951                         host->sg_len--;
1952                         if (!sg || !host->sg_len) {
1953                                 atmci_writel(host, ATMCI_TDR, value);
1954                                 goto done;
1955                         }
1956 
1957                         offset = 4 - remaining;
1958                         buf = sg_virt(sg);
1959                         memcpy((u8 *)&value + remaining, buf, offset);
1960                         atmci_writel(host, ATMCI_TDR, value);
1961                         nbytes += offset;
1962                 }
1963 
1964                 status = atmci_readl(host, ATMCI_SR);
1965                 if (status & ATMCI_DATA_ERROR_FLAGS) {
1966                         atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
1967                                                 | ATMCI_DATA_ERROR_FLAGS));
1968                         host->data_status = status;
1969                         data->bytes_xfered += nbytes;
1970                         return;
1971                 }
1972         } while (status & ATMCI_TXRDY);
1973 
1974         host->pio_offset = offset;
1975         data->bytes_xfered += nbytes;
1976 
1977         return;
1978 
1979 done:
1980         atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
1981         atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1982         data->bytes_xfered += nbytes;
1983         smp_wmb();
1984         atmci_set_pending(host, EVENT_XFER_COMPLETE);
1985 }
1986 
1987 static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
1988 {
1989         int     i;
1990 
1991         for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1992                 struct atmel_mci_slot *slot = host->slot[i];
1993                 if (slot && (status & slot->sdio_irq)) {
1994                         mmc_signal_sdio_irq(slot->mmc);
1995                 }
1996         }
1997 }
1998 
1999 
2000 static irqreturn_t atmci_interrupt(int irq, void *dev_id)
2001 {
2002         struct atmel_mci        *host = dev_id;
2003         u32                     status, mask, pending;
2004         unsigned int            pass_count = 0;
2005 
2006         do {
2007                 status = atmci_readl(host, ATMCI_SR);
2008                 mask = atmci_readl(host, ATMCI_IMR);
2009                 pending = status & mask;
2010                 if (!pending)
2011                         break;
2012 
2013                 if (pending & ATMCI_DATA_ERROR_FLAGS) {
2014                         dev_dbg(&host->pdev->dev, "IRQ: data error\n");
2015                         atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
2016                                         | ATMCI_RXRDY | ATMCI_TXRDY
2017                                         | ATMCI_ENDRX | ATMCI_ENDTX
2018                                         | ATMCI_RXBUFF | ATMCI_TXBUFE);
2019 
2020                         host->data_status = status;
2021                         dev_dbg(&host->pdev->dev, "set pending data error\n");
2022                         smp_wmb();
2023                         atmci_set_pending(host, EVENT_DATA_ERROR);
2024                         tasklet_schedule(&host->tasklet);
2025                 }
2026 
2027                 if (pending & ATMCI_TXBUFE) {
2028                         dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n");
2029                         atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
2030                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2031                         /*
2032                          * We can receive this interruption before having configured
2033                          * the second pdc buffer, so we need to reconfigure first and
2034                          * second buffers again
2035                          */
2036                         if (host->data_size) {
2037                                 atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
2038                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2039                                 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
2040                         } else {
2041                                 atmci_pdc_complete(host);
2042                         }
2043                 } else if (pending & ATMCI_ENDTX) {
2044                         dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n");
2045                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2046 
2047                         if (host->data_size) {
2048                                 atmci_pdc_set_single_buf(host,
2049                                                 XFER_TRANSMIT, PDC_SECOND_BUF);
2050                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2051                         }
2052                 }
2053 
2054                 if (pending & ATMCI_RXBUFF) {
2055                         dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n");
2056                         atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
2057                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2058                         /*
2059                          * We can receive this interruption before having configured
2060                          * the second pdc buffer, so we need to reconfigure first and
2061                          * second buffers again
2062                          */
2063                         if (host->data_size) {
2064                                 atmci_pdc_set_both_buf(host, XFER_RECEIVE);
2065                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2066                                 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
2067                         } else {
2068                                 atmci_pdc_complete(host);
2069                         }
2070                 } else if (pending & ATMCI_ENDRX) {
2071                         dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n");
2072                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2073 
2074                         if (host->data_size) {
2075                                 atmci_pdc_set_single_buf(host,
2076                                                 XFER_RECEIVE, PDC_SECOND_BUF);
2077                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2078                         }
2079                 }
2080 
2081                 /*
2082                  * First mci IPs, so mainly the ones having pdc, have some
2083                  * issues with the notbusy signal. You can't get it after
2084                  * data transmission if you have not sent a stop command.
2085                  * The appropriate workaround is to use the BLKE signal.
2086                  */
2087                 if (pending & ATMCI_BLKE) {
2088                         dev_dbg(&host->pdev->dev, "IRQ: blke\n");
2089                         atmci_writel(host, ATMCI_IDR, ATMCI_BLKE);
2090                         smp_wmb();
2091                         dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2092                         atmci_set_pending(host, EVENT_NOTBUSY);
2093                         tasklet_schedule(&host->tasklet);
2094                 }
2095 
2096                 if (pending & ATMCI_NOTBUSY) {
2097                         dev_dbg(&host->pdev->dev, "IRQ: not_busy\n");
2098                         atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY);
2099                         smp_wmb();
2100                         dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2101                         atmci_set_pending(host, EVENT_NOTBUSY);
2102                         tasklet_schedule(&host->tasklet);
2103                 }
2104 
2105                 if (pending & ATMCI_RXRDY)
2106                         atmci_read_data_pio(host);
2107                 if (pending & ATMCI_TXRDY)
2108                         atmci_write_data_pio(host);
2109 
2110                 if (pending & ATMCI_CMDRDY) {
2111                         dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n");
2112                         atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
2113                         host->cmd_status = status;
2114                         smp_wmb();
2115                         dev_dbg(&host->pdev->dev, "set pending cmd rdy\n");
2116                         atmci_set_pending(host, EVENT_CMD_RDY);
2117                         tasklet_schedule(&host->tasklet);
2118                 }
2119 
2120                 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
2121                         atmci_sdio_interrupt(host, status);
2122 
2123         } while (pass_count++ < 5);
2124 
2125         return pass_count ? IRQ_HANDLED : IRQ_NONE;
2126 }
2127 
2128 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
2129 {
2130         struct atmel_mci_slot   *slot = dev_id;
2131 
2132         /*
2133          * Disable interrupts until the pin has stabilized and check
2134          * the state then. Use mod_timer() since we may be in the
2135          * middle of the timer routine when this interrupt triggers.
2136          */
2137         disable_irq_nosync(irq);
2138         mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
2139 
2140         return IRQ_HANDLED;
2141 }
2142 
2143 static int atmci_init_slot(struct atmel_mci *host,
2144                 struct mci_slot_pdata *slot_data, unsigned int id,
2145                 u32 sdc_reg, u32 sdio_irq)
2146 {
2147         struct mmc_host                 *mmc;
2148         struct atmel_mci_slot           *slot;
2149 
2150         mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
2151         if (!mmc)
2152                 return -ENOMEM;
2153 
2154         slot = mmc_priv(mmc);
2155         slot->mmc = mmc;
2156         slot->host = host;
2157         slot->detect_pin = slot_data->detect_pin;
2158         slot->wp_pin = slot_data->wp_pin;
2159         slot->detect_is_active_high = slot_data->detect_is_active_high;
2160         slot->sdc_reg = sdc_reg;
2161         slot->sdio_irq = sdio_irq;
2162 
2163         dev_dbg(&mmc->class_dev,
2164                 "slot[%u]: bus_width=%u, detect_pin=%d, "
2165                 "detect_is_active_high=%s, wp_pin=%d\n",
2166                 id, slot_data->bus_width, slot_data->detect_pin,
2167                 slot_data->detect_is_active_high ? "true" : "false",
2168                 slot_data->wp_pin);
2169 
2170         mmc->ops = &atmci_ops;
2171         mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
2172         mmc->f_max = host->bus_hz / 2;
2173         mmc->ocr_avail  = MMC_VDD_32_33 | MMC_VDD_33_34;
2174         if (sdio_irq)
2175                 mmc->caps |= MMC_CAP_SDIO_IRQ;
2176         if (host->caps.has_highspeed)
2177                 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
2178         /*
2179          * Without the read/write proof capability, it is strongly suggested to
2180          * use only one bit for data to prevent fifo underruns and overruns
2181          * which will corrupt data.
2182          */
2183         if ((slot_data->bus_width >= 4) && host->caps.has_rwproof)
2184                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2185 
2186         if (atmci_get_version(host) < 0x200) {
2187                 mmc->max_segs = 256;
2188                 mmc->max_blk_size = 4095;
2189                 mmc->max_blk_count = 256;
2190                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2191                 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs;
2192         } else {
2193                 mmc->max_segs = 64;
2194                 mmc->max_req_size = 32768 * 512;
2195                 mmc->max_blk_size = 32768;
2196                 mmc->max_blk_count = 512;
2197         }
2198 
2199         /* Assume card is present initially */
2200         set_bit(ATMCI_CARD_PRESENT, &slot->flags);
2201         if (gpio_is_valid(slot->detect_pin)) {
2202                 if (devm_gpio_request(&host->pdev->dev, slot->detect_pin,
2203                                       "mmc_detect")) {
2204                         dev_dbg(&mmc->class_dev, "no detect pin available\n");
2205                         slot->detect_pin = -EBUSY;
2206                 } else if (gpio_get_value(slot->detect_pin) ^
2207                                 slot->detect_is_active_high) {
2208                         clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
2209                 }
2210         }
2211 
2212         if (!gpio_is_valid(slot->detect_pin)) {
2213                 if (slot_data->non_removable)
2214                         mmc->caps |= MMC_CAP_NONREMOVABLE;
2215                 else
2216                         mmc->caps |= MMC_CAP_NEEDS_POLL;
2217         }
2218 
2219         if (gpio_is_valid(slot->wp_pin)) {
2220                 if (devm_gpio_request(&host->pdev->dev, slot->wp_pin,
2221                                       "mmc_wp")) {
2222                         dev_dbg(&mmc->class_dev, "no WP pin available\n");
2223                         slot->wp_pin = -EBUSY;
2224                 }
2225         }
2226 
2227         host->slot[id] = slot;
2228         mmc_regulator_get_supply(mmc);
2229         mmc_add_host(mmc);
2230 
2231         if (gpio_is_valid(slot->detect_pin)) {
2232                 int ret;
2233 
2234                 setup_timer(&slot->detect_timer, atmci_detect_change,
2235                                 (unsigned long)slot);
2236 
2237                 ret = request_irq(gpio_to_irq(slot->detect_pin),
2238                                 atmci_detect_interrupt,
2239                                 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2240                                 "mmc-detect", slot);
2241                 if (ret) {
2242                         dev_dbg(&mmc->class_dev,
2243                                 "could not request IRQ %d for detect pin\n",
2244                                 gpio_to_irq(slot->detect_pin));
2245                         slot->detect_pin = -EBUSY;
2246                 }
2247         }
2248 
2249         atmci_init_debugfs(slot);
2250 
2251         return 0;
2252 }
2253 
2254 static void atmci_cleanup_slot(struct atmel_mci_slot *slot,
2255                 unsigned int id)
2256 {
2257         /* Debugfs stuff is cleaned up by mmc core */
2258 
2259         set_bit(ATMCI_SHUTDOWN, &slot->flags);
2260         smp_wmb();
2261 
2262         mmc_remove_host(slot->mmc);
2263 
2264         if (gpio_is_valid(slot->detect_pin)) {
2265                 int pin = slot->detect_pin;
2266 
2267                 free_irq(gpio_to_irq(pin), slot);
2268                 del_timer_sync(&slot->detect_timer);
2269         }
2270 
2271         slot->host->slot[id] = NULL;
2272         mmc_free_host(slot->mmc);
2273 }
2274 
2275 static int atmci_configure_dma(struct atmel_mci *host)
2276 {
2277         host->dma.chan = dma_request_slave_channel_reason(&host->pdev->dev,
2278                                                         "rxtx");
2279         if (IS_ERR(host->dma.chan))
2280                 return PTR_ERR(host->dma.chan);
2281 
2282         dev_info(&host->pdev->dev, "using %s for DMA transfers\n",
2283                  dma_chan_name(host->dma.chan));
2284 
2285         host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
2286         host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2287         host->dma_conf.src_maxburst = 1;
2288         host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
2289         host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2290         host->dma_conf.dst_maxburst = 1;
2291         host->dma_conf.device_fc = false;
2292 
2293         return 0;
2294 }
2295 
2296 /*
2297  * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2298  * HSMCI provides DMA support and a new config register but no more supports
2299  * PDC.
2300  */
2301 static void atmci_get_cap(struct atmel_mci *host)
2302 {
2303         unsigned int version;
2304 
2305         version = atmci_get_version(host);
2306         dev_info(&host->pdev->dev,
2307                         "version: 0x%x\n", version);
2308 
2309         host->caps.has_dma_conf_reg = 0;
2310         host->caps.has_pdc = ATMCI_PDC_CONNECTED;
2311         host->caps.has_cfg_reg = 0;
2312         host->caps.has_cstor_reg = 0;
2313         host->caps.has_highspeed = 0;
2314         host->caps.has_rwproof = 0;
2315         host->caps.has_odd_clk_div = 0;
2316         host->caps.has_bad_data_ordering = 1;
2317         host->caps.need_reset_after_xfer = 1;
2318         host->caps.need_blksz_mul_4 = 1;
2319         host->caps.need_notbusy_for_read_ops = 0;
2320 
2321         /* keep only major version number */
2322         switch (version & 0xf00) {
2323         case 0x600:
2324         case 0x500:
2325                 host->caps.has_odd_clk_div = 1;
2326         case 0x400:
2327         case 0x300:
2328                 host->caps.has_dma_conf_reg = 1;
2329                 host->caps.has_pdc = 0;
2330                 host->caps.has_cfg_reg = 1;
2331                 host->caps.has_cstor_reg = 1;
2332                 host->caps.has_highspeed = 1;
2333         case 0x200:
2334                 host->caps.has_rwproof = 1;
2335                 host->caps.need_blksz_mul_4 = 0;
2336                 host->caps.need_notbusy_for_read_ops = 1;
2337         case 0x100:
2338                 host->caps.has_bad_data_ordering = 0;
2339                 host->caps.need_reset_after_xfer = 0;
2340         case 0x0:
2341                 break;
2342         default:
2343                 host->caps.has_pdc = 0;
2344                 dev_warn(&host->pdev->dev,
2345                                 "Unmanaged mci version, set minimum capabilities\n");
2346                 break;
2347         }
2348 }
2349 
2350 static int atmci_probe(struct platform_device *pdev)
2351 {
2352         struct mci_platform_data        *pdata;
2353         struct atmel_mci                *host;
2354         struct resource                 *regs;
2355         unsigned int                    nr_slots;
2356         int                             irq;
2357         int                             ret, i;
2358 
2359         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2360         if (!regs)
2361                 return -ENXIO;
2362         pdata = pdev->dev.platform_data;
2363         if (!pdata) {
2364                 pdata = atmci_of_init(pdev);
2365                 if (IS_ERR(pdata)) {
2366                         dev_err(&pdev->dev, "platform data not available\n");
2367                         return PTR_ERR(pdata);
2368                 }
2369         }
2370 
2371         irq = platform_get_irq(pdev, 0);
2372         if (irq < 0)
2373                 return irq;
2374 
2375         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
2376         if (!host)
2377                 return -ENOMEM;
2378 
2379         host->pdev = pdev;
2380         spin_lock_init(&host->lock);
2381         INIT_LIST_HEAD(&host->queue);
2382 
2383         host->mck = devm_clk_get(&pdev->dev, "mci_clk");
2384         if (IS_ERR(host->mck))
2385                 return PTR_ERR(host->mck);
2386 
2387         host->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
2388         if (!host->regs)
2389                 return -ENOMEM;
2390 
2391         ret = clk_prepare_enable(host->mck);
2392         if (ret)
2393                 return ret;
2394 
2395         atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
2396         host->bus_hz = clk_get_rate(host->mck);
2397 
2398         host->mapbase = regs->start;
2399 
2400         tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
2401 
2402         ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
2403         if (ret) {
2404                 clk_disable_unprepare(host->mck);
2405                 return ret;
2406         }
2407 
2408         /* Get MCI capabilities and set operations according to it */
2409         atmci_get_cap(host);
2410         ret = atmci_configure_dma(host);
2411         if (ret == -EPROBE_DEFER)
2412                 goto err_dma_probe_defer;
2413         if (ret == 0) {
2414                 host->prepare_data = &atmci_prepare_data_dma;
2415                 host->submit_data = &atmci_submit_data_dma;
2416                 host->stop_transfer = &atmci_stop_transfer_dma;
2417         } else if (host->caps.has_pdc) {
2418                 dev_info(&pdev->dev, "using PDC\n");
2419                 host->prepare_data = &atmci_prepare_data_pdc;
2420                 host->submit_data = &atmci_submit_data_pdc;
2421                 host->stop_transfer = &atmci_stop_transfer_pdc;
2422         } else {
2423                 dev_info(&pdev->dev, "using PIO\n");
2424                 host->prepare_data = &atmci_prepare_data;
2425                 host->submit_data = &atmci_submit_data;
2426                 host->stop_transfer = &atmci_stop_transfer;
2427         }
2428 
2429         platform_set_drvdata(pdev, host);
2430 
2431         setup_timer(&host->timer, atmci_timeout_timer, (unsigned long)host);
2432 
2433         pm_runtime_get_noresume(&pdev->dev);
2434         pm_runtime_set_active(&pdev->dev);
2435         pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_DELAY);
2436         pm_runtime_use_autosuspend(&pdev->dev);
2437         pm_runtime_enable(&pdev->dev);
2438 
2439         /* We need at least one slot to succeed */
2440         nr_slots = 0;
2441         ret = -ENODEV;
2442         if (pdata->slot[0].bus_width) {
2443                 ret = atmci_init_slot(host, &pdata->slot[0],
2444                                 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
2445                 if (!ret) {
2446                         nr_slots++;
2447                         host->buf_size = host->slot[0]->mmc->max_req_size;
2448                 }
2449         }
2450         if (pdata->slot[1].bus_width) {
2451                 ret = atmci_init_slot(host, &pdata->slot[1],
2452                                 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
2453                 if (!ret) {
2454                         nr_slots++;
2455                         if (host->slot[1]->mmc->max_req_size > host->buf_size)
2456                                 host->buf_size =
2457                                         host->slot[1]->mmc->max_req_size;
2458                 }
2459         }
2460 
2461         if (!nr_slots) {
2462                 dev_err(&pdev->dev, "init failed: no slot defined\n");
2463                 goto err_init_slot;
2464         }
2465 
2466         if (!host->caps.has_rwproof) {
2467                 host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size,
2468                                                   &host->buf_phys_addr,
2469                                                   GFP_KERNEL);
2470                 if (!host->buffer) {
2471                         ret = -ENOMEM;
2472                         dev_err(&pdev->dev, "buffer allocation failed\n");
2473                         goto err_dma_alloc;
2474                 }
2475         }
2476 
2477         dev_info(&pdev->dev,
2478                         "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2479                         host->mapbase, irq, nr_slots);
2480 
2481         pm_runtime_mark_last_busy(&host->pdev->dev);
2482         pm_runtime_put_autosuspend(&pdev->dev);
2483 
2484         return 0;
2485 
2486 err_dma_alloc:
2487         for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2488                 if (host->slot[i])
2489                         atmci_cleanup_slot(host->slot[i], i);
2490         }
2491 err_init_slot:
2492         clk_disable_unprepare(host->mck);
2493 
2494         pm_runtime_disable(&pdev->dev);
2495         pm_runtime_put_noidle(&pdev->dev);
2496 
2497         del_timer_sync(&host->timer);
2498         if (!IS_ERR(host->dma.chan))
2499                 dma_release_channel(host->dma.chan);
2500 err_dma_probe_defer:
2501         free_irq(irq, host);
2502         return ret;
2503 }
2504 
2505 static int atmci_remove(struct platform_device *pdev)
2506 {
2507         struct atmel_mci        *host = platform_get_drvdata(pdev);
2508         unsigned int            i;
2509 
2510         pm_runtime_get_sync(&pdev->dev);
2511 
2512         if (host->buffer)
2513                 dma_free_coherent(&pdev->dev, host->buf_size,
2514                                   host->buffer, host->buf_phys_addr);
2515 
2516         for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2517                 if (host->slot[i])
2518                         atmci_cleanup_slot(host->slot[i], i);
2519         }
2520 
2521         atmci_writel(host, ATMCI_IDR, ~0UL);
2522         atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2523         atmci_readl(host, ATMCI_SR);
2524 
2525         del_timer_sync(&host->timer);
2526         if (!IS_ERR(host->dma.chan))
2527                 dma_release_channel(host->dma.chan);
2528 
2529         free_irq(platform_get_irq(pdev, 0), host);
2530 
2531         clk_disable_unprepare(host->mck);
2532 
2533         pm_runtime_disable(&pdev->dev);
2534         pm_runtime_put_noidle(&pdev->dev);
2535 
2536         return 0;
2537 }
2538 
2539 #ifdef CONFIG_PM
2540 static int atmci_runtime_suspend(struct device *dev)
2541 {
2542         struct atmel_mci *host = dev_get_drvdata(dev);
2543 
2544         clk_disable_unprepare(host->mck);
2545 
2546         pinctrl_pm_select_sleep_state(dev);
2547 
2548         return 0;
2549 }
2550 
2551 static int atmci_runtime_resume(struct device *dev)
2552 {
2553         struct atmel_mci *host = dev_get_drvdata(dev);
2554 
2555         pinctrl_pm_select_default_state(dev);
2556 
2557         return clk_prepare_enable(host->mck);
2558 }
2559 #endif
2560 
2561 static const struct dev_pm_ops atmci_dev_pm_ops = {
2562         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2563                                 pm_runtime_force_resume)
2564         SET_RUNTIME_PM_OPS(atmci_runtime_suspend, atmci_runtime_resume, NULL)
2565 };
2566 
2567 static struct platform_driver atmci_driver = {
2568         .probe          = atmci_probe,
2569         .remove         = atmci_remove,
2570         .driver         = {
2571                 .name           = "atmel_mci",
2572                 .of_match_table = of_match_ptr(atmci_dt_ids),
2573                 .pm             = &atmci_dev_pm_ops,
2574         },
2575 };
2576 module_platform_driver(atmci_driver);
2577 
2578 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2579 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2580 MODULE_LICENSE("GPL v2");
2581 

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