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Linux/drivers/misc/mei/pci-me.c

  1 /*
  2  *
  3  * Intel Management Engine Interface (Intel MEI) Linux driver
  4  * Copyright (c) 2003-2012, Intel Corporation.
  5  *
  6  * This program is free software; you can redistribute it and/or modify it
  7  * under the terms and conditions of the GNU General Public License,
  8  * version 2, as published by the Free Software Foundation.
  9  *
 10  * This program is distributed in the hope it will be useful, but WITHOUT
 11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 13  * more details.
 14  *
 15  */
 16 #include <linux/module.h>
 17 #include <linux/moduleparam.h>
 18 #include <linux/kernel.h>
 19 #include <linux/device.h>
 20 #include <linux/fs.h>
 21 #include <linux/errno.h>
 22 #include <linux/types.h>
 23 #include <linux/fcntl.h>
 24 #include <linux/pci.h>
 25 #include <linux/poll.h>
 26 #include <linux/ioctl.h>
 27 #include <linux/cdev.h>
 28 #include <linux/sched.h>
 29 #include <linux/uuid.h>
 30 #include <linux/compat.h>
 31 #include <linux/jiffies.h>
 32 #include <linux/interrupt.h>
 33 
 34 #include <linux/pm_runtime.h>
 35 
 36 #include <linux/mei.h>
 37 
 38 #include "mei_dev.h"
 39 #include "client.h"
 40 #include "hw-me-regs.h"
 41 #include "hw-me.h"
 42 
 43 /* mei_pci_tbl - PCI Device ID Table */
 44 static const struct pci_device_id mei_me_pci_tbl[] = {
 45         {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, mei_me_legacy_cfg)},
 46         {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, mei_me_legacy_cfg)},
 47         {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, mei_me_legacy_cfg)},
 48         {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, mei_me_legacy_cfg)},
 49         {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, mei_me_legacy_cfg)},
 50         {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, mei_me_legacy_cfg)},
 51         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, mei_me_legacy_cfg)},
 52         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, mei_me_legacy_cfg)},
 53         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, mei_me_legacy_cfg)},
 54         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, mei_me_legacy_cfg)},
 55         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, mei_me_legacy_cfg)},
 56 
 57         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, mei_me_legacy_cfg)},
 58         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, mei_me_legacy_cfg)},
 59         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, mei_me_legacy_cfg)},
 60         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, mei_me_legacy_cfg)},
 61         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, mei_me_legacy_cfg)},
 62         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, mei_me_legacy_cfg)},
 63         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, mei_me_legacy_cfg)},
 64         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, mei_me_legacy_cfg)},
 65         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, mei_me_legacy_cfg)},
 66         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, mei_me_ich_cfg)},
 67         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, mei_me_ich_cfg)},
 68         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, mei_me_ich_cfg)},
 69         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, mei_me_ich_cfg)},
 70 
 71         {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, mei_me_pch_cfg)},
 72         {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, mei_me_pch_cfg)},
 73         {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, mei_me_pch_cpt_pbg_cfg)},
 74         {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, mei_me_pch_cpt_pbg_cfg)},
 75         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, mei_me_pch_cfg)},
 76         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, mei_me_pch_cfg)},
 77         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, mei_me_pch_cfg)},
 78         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, mei_me_pch8_sps_cfg)},
 79         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, mei_me_pch8_sps_cfg)},
 80         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, mei_me_pch8_cfg)},
 81         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, mei_me_pch8_sps_cfg)},
 82         {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, mei_me_pch8_cfg)},
 83         {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, mei_me_pch8_cfg)},
 84 
 85         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, mei_me_pch8_cfg)},
 86         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, mei_me_pch8_cfg)},
 87         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, mei_me_pch8_cfg)},
 88         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, mei_me_pch8_cfg)},
 89 
 90         /* required last entry */
 91         {0, }
 92 };
 93 
 94 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
 95 
 96 #ifdef CONFIG_PM
 97 static inline void mei_me_set_pm_domain(struct mei_device *dev);
 98 static inline void mei_me_unset_pm_domain(struct mei_device *dev);
 99 #else
100 static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
101 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
102 #endif /* CONFIG_PM */
103 
104 /**
105  * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
106  *
107  * @pdev: PCI device structure
108  * @cfg: per generation config
109  *
110  * Return: true if ME Interface is valid, false otherwise
111  */
112 static bool mei_me_quirk_probe(struct pci_dev *pdev,
113                                 const struct mei_cfg *cfg)
114 {
115         if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
116                 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
117                 return false;
118         }
119 
120         return true;
121 }
122 
123 /**
124  * mei_me_probe - Device Initialization Routine
125  *
126  * @pdev: PCI device structure
127  * @ent: entry in kcs_pci_tbl
128  *
129  * Return: 0 on success, <0 on failure.
130  */
131 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
132 {
133         const struct mei_cfg *cfg = (struct mei_cfg *)(ent->driver_data);
134         struct mei_device *dev;
135         struct mei_me_hw *hw;
136         unsigned int irqflags;
137         int err;
138 
139 
140         if (!mei_me_quirk_probe(pdev, cfg))
141                 return -ENODEV;
142 
143         /* enable pci dev */
144         err = pci_enable_device(pdev);
145         if (err) {
146                 dev_err(&pdev->dev, "failed to enable pci device.\n");
147                 goto end;
148         }
149         /* set PCI host mastering  */
150         pci_set_master(pdev);
151         /* pci request regions for mei driver */
152         err = pci_request_regions(pdev, KBUILD_MODNAME);
153         if (err) {
154                 dev_err(&pdev->dev, "failed to get pci regions.\n");
155                 goto disable_device;
156         }
157 
158         if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
159             dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
160 
161                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
162                 if (err)
163                         err = dma_set_coherent_mask(&pdev->dev,
164                                                     DMA_BIT_MASK(32));
165         }
166         if (err) {
167                 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
168                 goto release_regions;
169         }
170 
171 
172         /* allocates and initializes the mei dev structure */
173         dev = mei_me_dev_init(pdev, cfg);
174         if (!dev) {
175                 err = -ENOMEM;
176                 goto release_regions;
177         }
178         hw = to_me_hw(dev);
179         /* mapping  IO device memory */
180         hw->mem_addr = pci_iomap(pdev, 0, 0);
181         if (!hw->mem_addr) {
182                 dev_err(&pdev->dev, "mapping I/O device memory failure.\n");
183                 err = -ENOMEM;
184                 goto free_device;
185         }
186         pci_enable_msi(pdev);
187 
188          /* request and enable interrupt */
189         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
190 
191         err = request_threaded_irq(pdev->irq,
192                         mei_me_irq_quick_handler,
193                         mei_me_irq_thread_handler,
194                         irqflags, KBUILD_MODNAME, dev);
195         if (err) {
196                 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
197                        pdev->irq);
198                 goto disable_msi;
199         }
200 
201         if (mei_start(dev)) {
202                 dev_err(&pdev->dev, "init hw failure.\n");
203                 err = -ENODEV;
204                 goto release_irq;
205         }
206 
207         pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
208         pm_runtime_use_autosuspend(&pdev->dev);
209 
210         err = mei_register(dev, &pdev->dev);
211         if (err)
212                 goto release_irq;
213 
214         pci_set_drvdata(pdev, dev);
215 
216         schedule_delayed_work(&dev->timer_work, HZ);
217 
218         /*
219         * For not wake-able HW runtime pm framework
220         * can't be used on pci device level.
221         * Use domain runtime pm callbacks instead.
222         */
223         if (!pci_dev_run_wake(pdev))
224                 mei_me_set_pm_domain(dev);
225 
226         if (mei_pg_is_enabled(dev))
227                 pm_runtime_put_noidle(&pdev->dev);
228 
229         dev_dbg(&pdev->dev, "initialization successful.\n");
230 
231         return 0;
232 
233 release_irq:
234         mei_cancel_work(dev);
235         mei_disable_interrupts(dev);
236         free_irq(pdev->irq, dev);
237 disable_msi:
238         pci_disable_msi(pdev);
239         pci_iounmap(pdev, hw->mem_addr);
240 free_device:
241         kfree(dev);
242 release_regions:
243         pci_release_regions(pdev);
244 disable_device:
245         pci_disable_device(pdev);
246 end:
247         dev_err(&pdev->dev, "initialization failed.\n");
248         return err;
249 }
250 
251 /**
252  * mei_me_remove - Device Removal Routine
253  *
254  * @pdev: PCI device structure
255  *
256  * mei_remove is called by the PCI subsystem to alert the driver
257  * that it should release a PCI device.
258  */
259 static void mei_me_remove(struct pci_dev *pdev)
260 {
261         struct mei_device *dev;
262         struct mei_me_hw *hw;
263 
264         dev = pci_get_drvdata(pdev);
265         if (!dev)
266                 return;
267 
268         if (mei_pg_is_enabled(dev))
269                 pm_runtime_get_noresume(&pdev->dev);
270 
271         hw = to_me_hw(dev);
272 
273 
274         dev_dbg(&pdev->dev, "stop\n");
275         mei_stop(dev);
276 
277         if (!pci_dev_run_wake(pdev))
278                 mei_me_unset_pm_domain(dev);
279 
280         /* disable interrupts */
281         mei_disable_interrupts(dev);
282 
283         free_irq(pdev->irq, dev);
284         pci_disable_msi(pdev);
285 
286         if (hw->mem_addr)
287                 pci_iounmap(pdev, hw->mem_addr);
288 
289         mei_deregister(dev);
290 
291         kfree(dev);
292 
293         pci_release_regions(pdev);
294         pci_disable_device(pdev);
295 
296 
297 }
298 #ifdef CONFIG_PM_SLEEP
299 static int mei_me_pci_suspend(struct device *device)
300 {
301         struct pci_dev *pdev = to_pci_dev(device);
302         struct mei_device *dev = pci_get_drvdata(pdev);
303 
304         if (!dev)
305                 return -ENODEV;
306 
307         dev_dbg(&pdev->dev, "suspend\n");
308 
309         mei_stop(dev);
310 
311         mei_disable_interrupts(dev);
312 
313         free_irq(pdev->irq, dev);
314         pci_disable_msi(pdev);
315 
316         return 0;
317 }
318 
319 static int mei_me_pci_resume(struct device *device)
320 {
321         struct pci_dev *pdev = to_pci_dev(device);
322         struct mei_device *dev;
323         unsigned int irqflags;
324         int err;
325 
326         dev = pci_get_drvdata(pdev);
327         if (!dev)
328                 return -ENODEV;
329 
330         pci_enable_msi(pdev);
331 
332         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
333 
334         /* request and enable interrupt */
335         err = request_threaded_irq(pdev->irq,
336                         mei_me_irq_quick_handler,
337                         mei_me_irq_thread_handler,
338                         irqflags, KBUILD_MODNAME, dev);
339 
340         if (err) {
341                 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
342                                 pdev->irq);
343                 return err;
344         }
345 
346         err = mei_restart(dev);
347         if (err)
348                 return err;
349 
350         /* Start timer if stopped in suspend */
351         schedule_delayed_work(&dev->timer_work, HZ);
352 
353         return 0;
354 }
355 #endif /* CONFIG_PM_SLEEP */
356 
357 #ifdef CONFIG_PM
358 static int mei_me_pm_runtime_idle(struct device *device)
359 {
360         struct pci_dev *pdev = to_pci_dev(device);
361         struct mei_device *dev;
362 
363         dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n");
364 
365         dev = pci_get_drvdata(pdev);
366         if (!dev)
367                 return -ENODEV;
368         if (mei_write_is_idle(dev))
369                 pm_runtime_autosuspend(device);
370 
371         return -EBUSY;
372 }
373 
374 static int mei_me_pm_runtime_suspend(struct device *device)
375 {
376         struct pci_dev *pdev = to_pci_dev(device);
377         struct mei_device *dev;
378         int ret;
379 
380         dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n");
381 
382         dev = pci_get_drvdata(pdev);
383         if (!dev)
384                 return -ENODEV;
385 
386         mutex_lock(&dev->device_lock);
387 
388         if (mei_write_is_idle(dev))
389                 ret = mei_me_pg_enter_sync(dev);
390         else
391                 ret = -EAGAIN;
392 
393         mutex_unlock(&dev->device_lock);
394 
395         dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret);
396 
397         return ret;
398 }
399 
400 static int mei_me_pm_runtime_resume(struct device *device)
401 {
402         struct pci_dev *pdev = to_pci_dev(device);
403         struct mei_device *dev;
404         int ret;
405 
406         dev_dbg(&pdev->dev, "rpm: me: runtime resume\n");
407 
408         dev = pci_get_drvdata(pdev);
409         if (!dev)
410                 return -ENODEV;
411 
412         mutex_lock(&dev->device_lock);
413 
414         ret = mei_me_pg_exit_sync(dev);
415 
416         mutex_unlock(&dev->device_lock);
417 
418         dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret);
419 
420         return ret;
421 }
422 
423 /**
424  * mei_me_set_pm_domain - fill and set pm domain structure for device
425  *
426  * @dev: mei_device
427  */
428 static inline void mei_me_set_pm_domain(struct mei_device *dev)
429 {
430         struct pci_dev *pdev  = to_pci_dev(dev->dev);
431 
432         if (pdev->dev.bus && pdev->dev.bus->pm) {
433                 dev->pg_domain.ops = *pdev->dev.bus->pm;
434 
435                 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
436                 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
437                 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
438 
439                 pdev->dev.pm_domain = &dev->pg_domain;
440         }
441 }
442 
443 /**
444  * mei_me_unset_pm_domain - clean pm domain structure for device
445  *
446  * @dev: mei_device
447  */
448 static inline void mei_me_unset_pm_domain(struct mei_device *dev)
449 {
450         /* stop using pm callbacks if any */
451         dev->dev->pm_domain = NULL;
452 }
453 
454 static const struct dev_pm_ops mei_me_pm_ops = {
455         SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
456                                 mei_me_pci_resume)
457         SET_RUNTIME_PM_OPS(
458                 mei_me_pm_runtime_suspend,
459                 mei_me_pm_runtime_resume,
460                 mei_me_pm_runtime_idle)
461 };
462 
463 #define MEI_ME_PM_OPS   (&mei_me_pm_ops)
464 #else
465 #define MEI_ME_PM_OPS   NULL
466 #endif /* CONFIG_PM */
467 /*
468  *  PCI driver structure
469  */
470 static struct pci_driver mei_me_driver = {
471         .name = KBUILD_MODNAME,
472         .id_table = mei_me_pci_tbl,
473         .probe = mei_me_probe,
474         .remove = mei_me_remove,
475         .shutdown = mei_me_remove,
476         .driver.pm = MEI_ME_PM_OPS,
477 };
478 
479 module_pci_driver(mei_me_driver);
480 
481 MODULE_AUTHOR("Intel Corporation");
482 MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
483 MODULE_LICENSE("GPL v2");
484 

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