Version:  2.0.40 2.2.26 2.4.37 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7

Linux/drivers/mfd/lpc_ich.c

  1 /*
  2  *  lpc_ich.c - LPC interface for Intel ICH
  3  *
  4  *  LPC bridge function of the Intel ICH contains many other
  5  *  functional units, such as Interrupt controllers, Timers,
  6  *  Power Management, System Management, GPIO, RTC, and LPC
  7  *  Configuration Registers.
  8  *
  9  *  This driver is derived from lpc_sch.
 10 
 11  *  Copyright (c) 2011 Extreme Engineering Solution, Inc.
 12  *  Author: Aaron Sierra <asierra@xes-inc.com>
 13  *
 14  *  This program is free software; you can redistribute it and/or modify
 15  *  it under the terms of the GNU General Public License 2 as published
 16  *  by the Free Software Foundation.
 17  *
 18  *  This program is distributed in the hope that it will be useful,
 19  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 20  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 21  *  GNU General Public License for more details.
 22  *
 23  *  You should have received a copy of the GNU General Public License
 24  *  along with this program; see the file COPYING.  If not, write to
 25  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 26  *
 27  *  This driver supports the following I/O Controller hubs:
 28  *      (See the intel documentation on http://developer.intel.com.)
 29  *      document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
 30  *      document number 290687-002, 298242-027: 82801BA (ICH2)
 31  *      document number 290733-003, 290739-013: 82801CA (ICH3-S)
 32  *      document number 290716-001, 290718-007: 82801CAM (ICH3-M)
 33  *      document number 290744-001, 290745-025: 82801DB (ICH4)
 34  *      document number 252337-001, 252663-008: 82801DBM (ICH4-M)
 35  *      document number 273599-001, 273645-002: 82801E (C-ICH)
 36  *      document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
 37  *      document number 300641-004, 300884-013: 6300ESB
 38  *      document number 301473-002, 301474-026: 82801F (ICH6)
 39  *      document number 313082-001, 313075-006: 631xESB, 632xESB
 40  *      document number 307013-003, 307014-024: 82801G (ICH7)
 41  *      document number 322896-001, 322897-001: NM10
 42  *      document number 313056-003, 313057-017: 82801H (ICH8)
 43  *      document number 316972-004, 316973-012: 82801I (ICH9)
 44  *      document number 319973-002, 319974-002: 82801J (ICH10)
 45  *      document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
 46  *      document number 320066-003, 320257-008: EP80597 (IICH)
 47  *      document number 324645-001, 324646-001: Cougar Point (CPT)
 48  *      document number TBD : Patsburg (PBG)
 49  *      document number TBD : DH89xxCC
 50  *      document number TBD : Panther Point
 51  *      document number TBD : Lynx Point
 52  *      document number TBD : Lynx Point-LP
 53  *      document number TBD : Wellsburg
 54  *      document number TBD : Avoton SoC
 55  *      document number TBD : Coleto Creek
 56  *      document number TBD : Wildcat Point-LP
 57  *      document number TBD : 9 Series
 58  *      document number TBD : Lewisburg
 59  */
 60 
 61 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 62 
 63 #include <linux/kernel.h>
 64 #include <linux/module.h>
 65 #include <linux/errno.h>
 66 #include <linux/acpi.h>
 67 #include <linux/pci.h>
 68 #include <linux/mfd/core.h>
 69 #include <linux/mfd/lpc_ich.h>
 70 #include <linux/platform_data/itco_wdt.h>
 71 
 72 #define ACPIBASE                0x40
 73 #define ACPIBASE_GPE_OFF        0x28
 74 #define ACPIBASE_GPE_END        0x2f
 75 #define ACPIBASE_SMI_OFF        0x30
 76 #define ACPIBASE_SMI_END        0x33
 77 #define ACPIBASE_PMC_OFF        0x08
 78 #define ACPIBASE_PMC_END        0x0c
 79 #define ACPIBASE_TCO_OFF        0x60
 80 #define ACPIBASE_TCO_END        0x7f
 81 #define ACPICTRL_PMCBASE        0x44
 82 
 83 #define ACPIBASE_GCS_OFF        0x3410
 84 #define ACPIBASE_GCS_END        0x3414
 85 
 86 #define GPIOBASE_ICH0           0x58
 87 #define GPIOCTRL_ICH0           0x5C
 88 #define GPIOBASE_ICH6           0x48
 89 #define GPIOCTRL_ICH6           0x4C
 90 
 91 #define RCBABASE                0xf0
 92 
 93 #define wdt_io_res(i) wdt_res(0, i)
 94 #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i)
 95 #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)])
 96 
 97 struct lpc_ich_priv {
 98         int chipset;
 99 
100         int abase;              /* ACPI base */
101         int actrl_pbase;        /* ACPI control or PMC base */
102         int gbase;              /* GPIO base */
103         int gctrl;              /* GPIO control */
104 
105         int abase_save;         /* Cached ACPI base value */
106         int actrl_pbase_save;           /* Cached ACPI control or PMC base value */
107         int gctrl_save;         /* Cached GPIO control value */
108 };
109 
110 static struct resource wdt_ich_res[] = {
111         /* ACPI - TCO */
112         {
113                 .flags = IORESOURCE_IO,
114         },
115         /* ACPI - SMI */
116         {
117                 .flags = IORESOURCE_IO,
118         },
119         /* GCS or PMC */
120         {
121                 .flags = IORESOURCE_MEM,
122         },
123 };
124 
125 static struct resource gpio_ich_res[] = {
126         /* GPIO */
127         {
128                 .flags = IORESOURCE_IO,
129         },
130         /* ACPI - GPE0 */
131         {
132                 .flags = IORESOURCE_IO,
133         },
134 };
135 
136 static struct mfd_cell lpc_ich_wdt_cell = {
137         .name = "iTCO_wdt",
138         .num_resources = ARRAY_SIZE(wdt_ich_res),
139         .resources = wdt_ich_res,
140         .ignore_resource_conflicts = true,
141 };
142 
143 static struct mfd_cell lpc_ich_gpio_cell = {
144         .name = "gpio_ich",
145         .num_resources = ARRAY_SIZE(gpio_ich_res),
146         .resources = gpio_ich_res,
147         .ignore_resource_conflicts = true,
148 };
149 
150 /* chipset related info */
151 enum lpc_chipsets {
152         LPC_ICH = 0,    /* ICH */
153         LPC_ICH0,       /* ICH0 */
154         LPC_ICH2,       /* ICH2 */
155         LPC_ICH2M,      /* ICH2-M */
156         LPC_ICH3,       /* ICH3-S */
157         LPC_ICH3M,      /* ICH3-M */
158         LPC_ICH4,       /* ICH4 */
159         LPC_ICH4M,      /* ICH4-M */
160         LPC_CICH,       /* C-ICH */
161         LPC_ICH5,       /* ICH5 & ICH5R */
162         LPC_6300ESB,    /* 6300ESB */
163         LPC_ICH6,       /* ICH6 & ICH6R */
164         LPC_ICH6M,      /* ICH6-M */
165         LPC_ICH6W,      /* ICH6W & ICH6RW */
166         LPC_631XESB,    /* 631xESB/632xESB */
167         LPC_ICH7,       /* ICH7 & ICH7R */
168         LPC_ICH7DH,     /* ICH7DH */
169         LPC_ICH7M,      /* ICH7-M & ICH7-U */
170         LPC_ICH7MDH,    /* ICH7-M DH */
171         LPC_NM10,       /* NM10 */
172         LPC_ICH8,       /* ICH8 & ICH8R */
173         LPC_ICH8DH,     /* ICH8DH */
174         LPC_ICH8DO,     /* ICH8DO */
175         LPC_ICH8M,      /* ICH8M */
176         LPC_ICH8ME,     /* ICH8M-E */
177         LPC_ICH9,       /* ICH9 */
178         LPC_ICH9R,      /* ICH9R */
179         LPC_ICH9DH,     /* ICH9DH */
180         LPC_ICH9DO,     /* ICH9DO */
181         LPC_ICH9M,      /* ICH9M */
182         LPC_ICH9ME,     /* ICH9M-E */
183         LPC_ICH10,      /* ICH10 */
184         LPC_ICH10R,     /* ICH10R */
185         LPC_ICH10D,     /* ICH10D */
186         LPC_ICH10DO,    /* ICH10DO */
187         LPC_PCH,        /* PCH Desktop Full Featured */
188         LPC_PCHM,       /* PCH Mobile Full Featured */
189         LPC_P55,        /* P55 */
190         LPC_PM55,       /* PM55 */
191         LPC_H55,        /* H55 */
192         LPC_QM57,       /* QM57 */
193         LPC_H57,        /* H57 */
194         LPC_HM55,       /* HM55 */
195         LPC_Q57,        /* Q57 */
196         LPC_HM57,       /* HM57 */
197         LPC_PCHMSFF,    /* PCH Mobile SFF Full Featured */
198         LPC_QS57,       /* QS57 */
199         LPC_3400,       /* 3400 */
200         LPC_3420,       /* 3420 */
201         LPC_3450,       /* 3450 */
202         LPC_EP80579,    /* EP80579 */
203         LPC_CPT,        /* Cougar Point */
204         LPC_CPTD,       /* Cougar Point Desktop */
205         LPC_CPTM,       /* Cougar Point Mobile */
206         LPC_PBG,        /* Patsburg */
207         LPC_DH89XXCC,   /* DH89xxCC */
208         LPC_PPT,        /* Panther Point */
209         LPC_LPT,        /* Lynx Point */
210         LPC_LPT_LP,     /* Lynx Point-LP */
211         LPC_WBG,        /* Wellsburg */
212         LPC_AVN,        /* Avoton SoC */
213         LPC_BAYTRAIL,   /* Bay Trail SoC */
214         LPC_COLETO,     /* Coleto Creek */
215         LPC_WPT_LP,     /* Wildcat Point-LP */
216         LPC_BRASWELL,   /* Braswell SoC */
217         LPC_LEWISBURG,  /* Lewisburg */
218         LPC_9S,         /* 9 Series */
219 };
220 
221 static struct lpc_ich_info lpc_chipset_info[] = {
222         [LPC_ICH] = {
223                 .name = "ICH",
224                 .iTCO_version = 1,
225         },
226         [LPC_ICH0] = {
227                 .name = "ICH0",
228                 .iTCO_version = 1,
229         },
230         [LPC_ICH2] = {
231                 .name = "ICH2",
232                 .iTCO_version = 1,
233         },
234         [LPC_ICH2M] = {
235                 .name = "ICH2-M",
236                 .iTCO_version = 1,
237         },
238         [LPC_ICH3] = {
239                 .name = "ICH3-S",
240                 .iTCO_version = 1,
241         },
242         [LPC_ICH3M] = {
243                 .name = "ICH3-M",
244                 .iTCO_version = 1,
245         },
246         [LPC_ICH4] = {
247                 .name = "ICH4",
248                 .iTCO_version = 1,
249         },
250         [LPC_ICH4M] = {
251                 .name = "ICH4-M",
252                 .iTCO_version = 1,
253         },
254         [LPC_CICH] = {
255                 .name = "C-ICH",
256                 .iTCO_version = 1,
257         },
258         [LPC_ICH5] = {
259                 .name = "ICH5 or ICH5R",
260                 .iTCO_version = 1,
261         },
262         [LPC_6300ESB] = {
263                 .name = "6300ESB",
264                 .iTCO_version = 1,
265         },
266         [LPC_ICH6] = {
267                 .name = "ICH6 or ICH6R",
268                 .iTCO_version = 2,
269                 .gpio_version = ICH_V6_GPIO,
270         },
271         [LPC_ICH6M] = {
272                 .name = "ICH6-M",
273                 .iTCO_version = 2,
274                 .gpio_version = ICH_V6_GPIO,
275         },
276         [LPC_ICH6W] = {
277                 .name = "ICH6W or ICH6RW",
278                 .iTCO_version = 2,
279                 .gpio_version = ICH_V6_GPIO,
280         },
281         [LPC_631XESB] = {
282                 .name = "631xESB/632xESB",
283                 .iTCO_version = 2,
284                 .gpio_version = ICH_V6_GPIO,
285         },
286         [LPC_ICH7] = {
287                 .name = "ICH7 or ICH7R",
288                 .iTCO_version = 2,
289                 .gpio_version = ICH_V7_GPIO,
290         },
291         [LPC_ICH7DH] = {
292                 .name = "ICH7DH",
293                 .iTCO_version = 2,
294                 .gpio_version = ICH_V7_GPIO,
295         },
296         [LPC_ICH7M] = {
297                 .name = "ICH7-M or ICH7-U",
298                 .iTCO_version = 2,
299                 .gpio_version = ICH_V7_GPIO,
300         },
301         [LPC_ICH7MDH] = {
302                 .name = "ICH7-M DH",
303                 .iTCO_version = 2,
304                 .gpio_version = ICH_V7_GPIO,
305         },
306         [LPC_NM10] = {
307                 .name = "NM10",
308                 .iTCO_version = 2,
309                 .gpio_version = ICH_V7_GPIO,
310         },
311         [LPC_ICH8] = {
312                 .name = "ICH8 or ICH8R",
313                 .iTCO_version = 2,
314                 .gpio_version = ICH_V7_GPIO,
315         },
316         [LPC_ICH8DH] = {
317                 .name = "ICH8DH",
318                 .iTCO_version = 2,
319                 .gpio_version = ICH_V7_GPIO,
320         },
321         [LPC_ICH8DO] = {
322                 .name = "ICH8DO",
323                 .iTCO_version = 2,
324                 .gpio_version = ICH_V7_GPIO,
325         },
326         [LPC_ICH8M] = {
327                 .name = "ICH8M",
328                 .iTCO_version = 2,
329                 .gpio_version = ICH_V7_GPIO,
330         },
331         [LPC_ICH8ME] = {
332                 .name = "ICH8M-E",
333                 .iTCO_version = 2,
334                 .gpio_version = ICH_V7_GPIO,
335         },
336         [LPC_ICH9] = {
337                 .name = "ICH9",
338                 .iTCO_version = 2,
339                 .gpio_version = ICH_V9_GPIO,
340         },
341         [LPC_ICH9R] = {
342                 .name = "ICH9R",
343                 .iTCO_version = 2,
344                 .gpio_version = ICH_V9_GPIO,
345         },
346         [LPC_ICH9DH] = {
347                 .name = "ICH9DH",
348                 .iTCO_version = 2,
349                 .gpio_version = ICH_V9_GPIO,
350         },
351         [LPC_ICH9DO] = {
352                 .name = "ICH9DO",
353                 .iTCO_version = 2,
354                 .gpio_version = ICH_V9_GPIO,
355         },
356         [LPC_ICH9M] = {
357                 .name = "ICH9M",
358                 .iTCO_version = 2,
359                 .gpio_version = ICH_V9_GPIO,
360         },
361         [LPC_ICH9ME] = {
362                 .name = "ICH9M-E",
363                 .iTCO_version = 2,
364                 .gpio_version = ICH_V9_GPIO,
365         },
366         [LPC_ICH10] = {
367                 .name = "ICH10",
368                 .iTCO_version = 2,
369                 .gpio_version = ICH_V10CONS_GPIO,
370         },
371         [LPC_ICH10R] = {
372                 .name = "ICH10R",
373                 .iTCO_version = 2,
374                 .gpio_version = ICH_V10CONS_GPIO,
375         },
376         [LPC_ICH10D] = {
377                 .name = "ICH10D",
378                 .iTCO_version = 2,
379                 .gpio_version = ICH_V10CORP_GPIO,
380         },
381         [LPC_ICH10DO] = {
382                 .name = "ICH10DO",
383                 .iTCO_version = 2,
384                 .gpio_version = ICH_V10CORP_GPIO,
385         },
386         [LPC_PCH] = {
387                 .name = "PCH Desktop Full Featured",
388                 .iTCO_version = 2,
389                 .gpio_version = ICH_V5_GPIO,
390         },
391         [LPC_PCHM] = {
392                 .name = "PCH Mobile Full Featured",
393                 .iTCO_version = 2,
394                 .gpio_version = ICH_V5_GPIO,
395         },
396         [LPC_P55] = {
397                 .name = "P55",
398                 .iTCO_version = 2,
399                 .gpio_version = ICH_V5_GPIO,
400         },
401         [LPC_PM55] = {
402                 .name = "PM55",
403                 .iTCO_version = 2,
404                 .gpio_version = ICH_V5_GPIO,
405         },
406         [LPC_H55] = {
407                 .name = "H55",
408                 .iTCO_version = 2,
409                 .gpio_version = ICH_V5_GPIO,
410         },
411         [LPC_QM57] = {
412                 .name = "QM57",
413                 .iTCO_version = 2,
414                 .gpio_version = ICH_V5_GPIO,
415         },
416         [LPC_H57] = {
417                 .name = "H57",
418                 .iTCO_version = 2,
419                 .gpio_version = ICH_V5_GPIO,
420         },
421         [LPC_HM55] = {
422                 .name = "HM55",
423                 .iTCO_version = 2,
424                 .gpio_version = ICH_V5_GPIO,
425         },
426         [LPC_Q57] = {
427                 .name = "Q57",
428                 .iTCO_version = 2,
429                 .gpio_version = ICH_V5_GPIO,
430         },
431         [LPC_HM57] = {
432                 .name = "HM57",
433                 .iTCO_version = 2,
434                 .gpio_version = ICH_V5_GPIO,
435         },
436         [LPC_PCHMSFF] = {
437                 .name = "PCH Mobile SFF Full Featured",
438                 .iTCO_version = 2,
439                 .gpio_version = ICH_V5_GPIO,
440         },
441         [LPC_QS57] = {
442                 .name = "QS57",
443                 .iTCO_version = 2,
444                 .gpio_version = ICH_V5_GPIO,
445         },
446         [LPC_3400] = {
447                 .name = "3400",
448                 .iTCO_version = 2,
449                 .gpio_version = ICH_V5_GPIO,
450         },
451         [LPC_3420] = {
452                 .name = "3420",
453                 .iTCO_version = 2,
454                 .gpio_version = ICH_V5_GPIO,
455         },
456         [LPC_3450] = {
457                 .name = "3450",
458                 .iTCO_version = 2,
459                 .gpio_version = ICH_V5_GPIO,
460         },
461         [LPC_EP80579] = {
462                 .name = "EP80579",
463                 .iTCO_version = 2,
464         },
465         [LPC_CPT] = {
466                 .name = "Cougar Point",
467                 .iTCO_version = 2,
468                 .gpio_version = ICH_V5_GPIO,
469         },
470         [LPC_CPTD] = {
471                 .name = "Cougar Point Desktop",
472                 .iTCO_version = 2,
473                 .gpio_version = ICH_V5_GPIO,
474         },
475         [LPC_CPTM] = {
476                 .name = "Cougar Point Mobile",
477                 .iTCO_version = 2,
478                 .gpio_version = ICH_V5_GPIO,
479         },
480         [LPC_PBG] = {
481                 .name = "Patsburg",
482                 .iTCO_version = 2,
483         },
484         [LPC_DH89XXCC] = {
485                 .name = "DH89xxCC",
486                 .iTCO_version = 2,
487         },
488         [LPC_PPT] = {
489                 .name = "Panther Point",
490                 .iTCO_version = 2,
491                 .gpio_version = ICH_V5_GPIO,
492         },
493         [LPC_LPT] = {
494                 .name = "Lynx Point",
495                 .iTCO_version = 2,
496         },
497         [LPC_LPT_LP] = {
498                 .name = "Lynx Point_LP",
499                 .iTCO_version = 2,
500         },
501         [LPC_WBG] = {
502                 .name = "Wellsburg",
503                 .iTCO_version = 2,
504         },
505         [LPC_AVN] = {
506                 .name = "Avoton SoC",
507                 .iTCO_version = 3,
508                 .gpio_version = AVOTON_GPIO,
509         },
510         [LPC_BAYTRAIL] = {
511                 .name = "Bay Trail SoC",
512                 .iTCO_version = 3,
513         },
514         [LPC_COLETO] = {
515                 .name = "Coleto Creek",
516                 .iTCO_version = 2,
517         },
518         [LPC_WPT_LP] = {
519                 .name = "Wildcat Point_LP",
520                 .iTCO_version = 2,
521         },
522         [LPC_BRASWELL] = {
523                 .name = "Braswell SoC",
524                 .iTCO_version = 3,
525         },
526         [LPC_LEWISBURG] = {
527                 .name = "Lewisburg",
528                 .iTCO_version = 2,
529         },
530         [LPC_9S] = {
531                 .name = "9 Series",
532                 .iTCO_version = 2,
533         },
534 };
535 
536 /*
537  * This data only exists for exporting the supported PCI ids
538  * via MODULE_DEVICE_TABLE.  We do not actually register a
539  * pci_driver, because the I/O Controller Hub has also other
540  * functions that probably will be registered by other drivers.
541  */
542 static const struct pci_device_id lpc_ich_ids[] = {
543         { PCI_VDEVICE(INTEL, 0x0f1c), LPC_BAYTRAIL},
544         { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT},
545         { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD},
546         { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM},
547         { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT},
548         { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT},
549         { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT},
550         { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT},
551         { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT},
552         { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT},
553         { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT},
554         { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT},
555         { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT},
556         { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT},
557         { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT},
558         { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT},
559         { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT},
560         { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT},
561         { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT},
562         { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT},
563         { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT},
564         { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT},
565         { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT},
566         { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT},
567         { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT},
568         { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT},
569         { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT},
570         { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT},
571         { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT},
572         { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT},
573         { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT},
574         { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT},
575         { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG},
576         { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG},
577         { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT},
578         { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT},
579         { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT},
580         { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT},
581         { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT},
582         { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT},
583         { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT},
584         { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT},
585         { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT},
586         { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT},
587         { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT},
588         { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT},
589         { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT},
590         { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT},
591         { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT},
592         { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT},
593         { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT},
594         { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT},
595         { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT},
596         { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT},
597         { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT},
598         { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT},
599         { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT},
600         { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT},
601         { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT},
602         { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT},
603         { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT},
604         { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT},
605         { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT},
606         { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT},
607         { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT},
608         { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT},
609         { PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN},
610         { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN},
611         { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN},
612         { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN},
613         { PCI_VDEVICE(INTEL, 0x229c), LPC_BRASWELL},
614         { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC},
615         { PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO},
616         { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH},
617         { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0},
618         { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2},
619         { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M},
620         { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH},
621         { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3},
622         { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M},
623         { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4},
624         { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M},
625         { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5},
626         { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB},
627         { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6},
628         { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M},
629         { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W},
630         { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB},
631         { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB},
632         { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB},
633         { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB},
634         { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB},
635         { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB},
636         { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB},
637         { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB},
638         { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB},
639         { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB},
640         { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB},
641         { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB},
642         { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB},
643         { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB},
644         { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB},
645         { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB},
646         { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH},
647         { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7},
648         { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M},
649         { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10},
650         { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH},
651         { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8},
652         { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME},
653         { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH},
654         { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO},
655         { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M},
656         { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH},
657         { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO},
658         { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R},
659         { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME},
660         { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9},
661         { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M},
662         { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO},
663         { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R},
664         { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10},
665         { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D},
666         { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH},
667         { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM},
668         { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55},
669         { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55},
670         { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55},
671         { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57},
672         { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57},
673         { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55},
674         { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57},
675         { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57},
676         { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF},
677         { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57},
678         { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400},
679         { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
680         { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
681         { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
682         { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
683         { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
684         { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
685         { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT},
686         { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT},
687         { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT},
688         { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT},
689         { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT},
690         { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT},
691         { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT},
692         { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT},
693         { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT},
694         { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT},
695         { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT},
696         { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT},
697         { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT},
698         { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT},
699         { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT},
700         { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT},
701         { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT},
702         { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT},
703         { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT},
704         { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT},
705         { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT},
706         { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT},
707         { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT},
708         { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT},
709         { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT},
710         { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT},
711         { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT},
712         { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT},
713         { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT},
714         { PCI_VDEVICE(INTEL, 0x8cc1), LPC_9S},
715         { PCI_VDEVICE(INTEL, 0x8cc2), LPC_9S},
716         { PCI_VDEVICE(INTEL, 0x8cc3), LPC_9S},
717         { PCI_VDEVICE(INTEL, 0x8cc4), LPC_9S},
718         { PCI_VDEVICE(INTEL, 0x8cc6), LPC_9S},
719         { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG},
720         { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG},
721         { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG},
722         { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG},
723         { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG},
724         { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG},
725         { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG},
726         { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG},
727         { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG},
728         { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG},
729         { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG},
730         { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG},
731         { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG},
732         { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG},
733         { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG},
734         { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG},
735         { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG},
736         { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG},
737         { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG},
738         { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG},
739         { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG},
740         { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG},
741         { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG},
742         { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG},
743         { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG},
744         { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG},
745         { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG},
746         { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG},
747         { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG},
748         { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG},
749         { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG},
750         { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG},
751         { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP},
752         { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP},
753         { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP},
754         { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP},
755         { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP},
756         { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP},
757         { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP},
758         { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP},
759         { PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP},
760         { PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP},
761         { PCI_VDEVICE(INTEL, 0x9cc3), LPC_WPT_LP},
762         { PCI_VDEVICE(INTEL, 0x9cc5), LPC_WPT_LP},
763         { PCI_VDEVICE(INTEL, 0x9cc6), LPC_WPT_LP},
764         { PCI_VDEVICE(INTEL, 0x9cc7), LPC_WPT_LP},
765         { PCI_VDEVICE(INTEL, 0x9cc9), LPC_WPT_LP},
766         { PCI_VDEVICE(INTEL, 0xa1c1), LPC_LEWISBURG},
767         { PCI_VDEVICE(INTEL, 0xa1c2), LPC_LEWISBURG},
768         { PCI_VDEVICE(INTEL, 0xa1c3), LPC_LEWISBURG},
769         { PCI_VDEVICE(INTEL, 0xa1c4), LPC_LEWISBURG},
770         { PCI_VDEVICE(INTEL, 0xa1c5), LPC_LEWISBURG},
771         { PCI_VDEVICE(INTEL, 0xa1c6), LPC_LEWISBURG},
772         { PCI_VDEVICE(INTEL, 0xa1c7), LPC_LEWISBURG},
773         { PCI_VDEVICE(INTEL, 0xa242), LPC_LEWISBURG},
774         { PCI_VDEVICE(INTEL, 0xa243), LPC_LEWISBURG},
775         { 0, },                 /* End of list */
776 };
777 MODULE_DEVICE_TABLE(pci, lpc_ich_ids);
778 
779 static void lpc_ich_restore_config_space(struct pci_dev *dev)
780 {
781         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
782 
783         if (priv->abase_save >= 0) {
784                 pci_write_config_byte(dev, priv->abase, priv->abase_save);
785                 priv->abase_save = -1;
786         }
787 
788         if (priv->actrl_pbase_save >= 0) {
789                 pci_write_config_byte(dev, priv->actrl_pbase,
790                         priv->actrl_pbase_save);
791                 priv->actrl_pbase_save = -1;
792         }
793 
794         if (priv->gctrl_save >= 0) {
795                 pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save);
796                 priv->gctrl_save = -1;
797         }
798 }
799 
800 static void lpc_ich_enable_acpi_space(struct pci_dev *dev)
801 {
802         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
803         u8 reg_save;
804 
805         switch (lpc_chipset_info[priv->chipset].iTCO_version) {
806         case 3:
807                 /*
808                  * Some chipsets (eg Avoton) enable the ACPI space in the
809                  * ACPI BASE register.
810                  */
811                 pci_read_config_byte(dev, priv->abase, &reg_save);
812                 pci_write_config_byte(dev, priv->abase, reg_save | 0x2);
813                 priv->abase_save = reg_save;
814                 break;
815         default:
816                 /*
817                  * Most chipsets enable the ACPI space in the ACPI control
818                  * register.
819                  */
820                 pci_read_config_byte(dev, priv->actrl_pbase, &reg_save);
821                 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80);
822                 priv->actrl_pbase_save = reg_save;
823                 break;
824         }
825 }
826 
827 static void lpc_ich_enable_gpio_space(struct pci_dev *dev)
828 {
829         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
830         u8 reg_save;
831 
832         pci_read_config_byte(dev, priv->gctrl, &reg_save);
833         pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10);
834         priv->gctrl_save = reg_save;
835 }
836 
837 static void lpc_ich_enable_pmc_space(struct pci_dev *dev)
838 {
839         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
840         u8 reg_save;
841 
842         pci_read_config_byte(dev, priv->actrl_pbase, &reg_save);
843         pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2);
844 
845         priv->actrl_pbase_save = reg_save;
846 }
847 
848 static int lpc_ich_finalize_wdt_cell(struct pci_dev *dev)
849 {
850         struct itco_wdt_platform_data *pdata;
851         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
852         struct lpc_ich_info *info;
853         struct mfd_cell *cell = &lpc_ich_wdt_cell;
854 
855         pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
856         if (!pdata)
857                 return -ENOMEM;
858 
859         info = &lpc_chipset_info[priv->chipset];
860 
861         pdata->version = info->iTCO_version;
862         strlcpy(pdata->name, info->name, sizeof(pdata->name));
863 
864         cell->platform_data = pdata;
865         cell->pdata_size = sizeof(*pdata);
866         return 0;
867 }
868 
869 static void lpc_ich_finalize_gpio_cell(struct pci_dev *dev)
870 {
871         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
872         struct mfd_cell *cell = &lpc_ich_gpio_cell;
873 
874         cell->platform_data = &lpc_chipset_info[priv->chipset];
875         cell->pdata_size = sizeof(struct lpc_ich_info);
876 }
877 
878 /*
879  * We don't check for resource conflict globally. There are 2 or 3 independent
880  * GPIO groups and it's enough to have access to one of these to instantiate
881  * the device.
882  */
883 static int lpc_ich_check_conflict_gpio(struct resource *res)
884 {
885         int ret;
886         u8 use_gpio = 0;
887 
888         if (resource_size(res) >= 0x50 &&
889             !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3"))
890                 use_gpio |= 1 << 2;
891 
892         if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2"))
893                 use_gpio |= 1 << 1;
894 
895         ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1");
896         if (!ret)
897                 use_gpio |= 1 << 0;
898 
899         return use_gpio ? use_gpio : ret;
900 }
901 
902 static int lpc_ich_init_gpio(struct pci_dev *dev)
903 {
904         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
905         u32 base_addr_cfg;
906         u32 base_addr;
907         int ret;
908         bool acpi_conflict = false;
909         struct resource *res;
910 
911         /* Setup power management base register */
912         pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
913         base_addr = base_addr_cfg & 0x0000ff80;
914         if (!base_addr) {
915                 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
916                 lpc_ich_gpio_cell.num_resources--;
917                 goto gpe0_done;
918         }
919 
920         res = &gpio_ich_res[ICH_RES_GPE0];
921         res->start = base_addr + ACPIBASE_GPE_OFF;
922         res->end = base_addr + ACPIBASE_GPE_END;
923         ret = acpi_check_resource_conflict(res);
924         if (ret) {
925                 /*
926                  * This isn't fatal for the GPIO, but we have to make sure that
927                  * the platform_device subsystem doesn't see this resource
928                  * or it will register an invalid region.
929                  */
930                 lpc_ich_gpio_cell.num_resources--;
931                 acpi_conflict = true;
932         } else {
933                 lpc_ich_enable_acpi_space(dev);
934         }
935 
936 gpe0_done:
937         /* Setup GPIO base register */
938         pci_read_config_dword(dev, priv->gbase, &base_addr_cfg);
939         base_addr = base_addr_cfg & 0x0000ff80;
940         if (!base_addr) {
941                 dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n");
942                 ret = -ENODEV;
943                 goto gpio_done;
944         }
945 
946         /* Older devices provide fewer GPIO and have a smaller resource size. */
947         res = &gpio_ich_res[ICH_RES_GPIO];
948         res->start = base_addr;
949         switch (lpc_chipset_info[priv->chipset].gpio_version) {
950         case ICH_V5_GPIO:
951         case ICH_V10CORP_GPIO:
952                 res->end = res->start + 128 - 1;
953                 break;
954         default:
955                 res->end = res->start + 64 - 1;
956                 break;
957         }
958 
959         ret = lpc_ich_check_conflict_gpio(res);
960         if (ret < 0) {
961                 /* this isn't necessarily fatal for the GPIO */
962                 acpi_conflict = true;
963                 goto gpio_done;
964         }
965         lpc_chipset_info[priv->chipset].use_gpio = ret;
966         lpc_ich_enable_gpio_space(dev);
967 
968         lpc_ich_finalize_gpio_cell(dev);
969         ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
970                               &lpc_ich_gpio_cell, 1, NULL, 0, NULL);
971 
972 gpio_done:
973         if (acpi_conflict)
974                 pr_warn("Resource conflict(s) found affecting %s\n",
975                                 lpc_ich_gpio_cell.name);
976         return ret;
977 }
978 
979 static int lpc_ich_init_wdt(struct pci_dev *dev)
980 {
981         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
982         u32 base_addr_cfg;
983         u32 base_addr;
984         int ret;
985         struct resource *res;
986 
987         /* Setup power management base register */
988         pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
989         base_addr = base_addr_cfg & 0x0000ff80;
990         if (!base_addr) {
991                 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
992                 ret = -ENODEV;
993                 goto wdt_done;
994         }
995 
996         res = wdt_io_res(ICH_RES_IO_TCO);
997         res->start = base_addr + ACPIBASE_TCO_OFF;
998         res->end = base_addr + ACPIBASE_TCO_END;
999 
1000         res = wdt_io_res(ICH_RES_IO_SMI);
1001         res->start = base_addr + ACPIBASE_SMI_OFF;
1002         res->end = base_addr + ACPIBASE_SMI_END;
1003 
1004         lpc_ich_enable_acpi_space(dev);
1005 
1006         /*
1007          * iTCO v2:
1008          * Get the Memory-Mapped GCS register. To get access to it
1009          * we have to read RCBA from PCI Config space 0xf0 and use
1010          * it as base. GCS = RCBA + ICH6_GCS(0x3410).
1011          *
1012          * iTCO v3:
1013          * Get the Power Management Configuration register.  To get access
1014          * to it we have to read the PMC BASE from config space and address
1015          * the register at offset 0x8.
1016          */
1017         if (lpc_chipset_info[priv->chipset].iTCO_version == 1) {
1018                 /* Don't register iomem for TCO ver 1 */
1019                 lpc_ich_wdt_cell.num_resources--;
1020         } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) {
1021                 pci_read_config_dword(dev, RCBABASE, &base_addr_cfg);
1022                 base_addr = base_addr_cfg & 0xffffc000;
1023                 if (!(base_addr_cfg & 1)) {
1024                         dev_notice(&dev->dev, "RCBA is disabled by "
1025                                         "hardware/BIOS, device disabled\n");
1026                         ret = -ENODEV;
1027                         goto wdt_done;
1028                 }
1029                 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
1030                 res->start = base_addr + ACPIBASE_GCS_OFF;
1031                 res->end = base_addr + ACPIBASE_GCS_END;
1032         } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) {
1033                 lpc_ich_enable_pmc_space(dev);
1034                 pci_read_config_dword(dev, ACPICTRL_PMCBASE, &base_addr_cfg);
1035                 base_addr = base_addr_cfg & 0xfffffe00;
1036 
1037                 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
1038                 res->start = base_addr + ACPIBASE_PMC_OFF;
1039                 res->end = base_addr + ACPIBASE_PMC_END;
1040         }
1041 
1042         ret = lpc_ich_finalize_wdt_cell(dev);
1043         if (ret)
1044                 goto wdt_done;
1045 
1046         ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
1047                               &lpc_ich_wdt_cell, 1, NULL, 0, NULL);
1048 
1049 wdt_done:
1050         return ret;
1051 }
1052 
1053 static int lpc_ich_probe(struct pci_dev *dev,
1054                                 const struct pci_device_id *id)
1055 {
1056         struct lpc_ich_priv *priv;
1057         int ret;
1058         bool cell_added = false;
1059 
1060         priv = devm_kzalloc(&dev->dev,
1061                             sizeof(struct lpc_ich_priv), GFP_KERNEL);
1062         if (!priv)
1063                 return -ENOMEM;
1064 
1065         priv->chipset = id->driver_data;
1066 
1067         priv->actrl_pbase_save = -1;
1068         priv->abase_save = -1;
1069 
1070         priv->abase = ACPIBASE;
1071         priv->actrl_pbase = ACPICTRL_PMCBASE;
1072 
1073         priv->gctrl_save = -1;
1074         if (priv->chipset <= LPC_ICH5) {
1075                 priv->gbase = GPIOBASE_ICH0;
1076                 priv->gctrl = GPIOCTRL_ICH0;
1077         } else {
1078                 priv->gbase = GPIOBASE_ICH6;
1079                 priv->gctrl = GPIOCTRL_ICH6;
1080         }
1081 
1082         pci_set_drvdata(dev, priv);
1083 
1084         if (lpc_chipset_info[priv->chipset].iTCO_version) {
1085                 ret = lpc_ich_init_wdt(dev);
1086                 if (!ret)
1087                         cell_added = true;
1088         }
1089 
1090         if (lpc_chipset_info[priv->chipset].gpio_version) {
1091                 ret = lpc_ich_init_gpio(dev);
1092                 if (!ret)
1093                         cell_added = true;
1094         }
1095 
1096         /*
1097          * We only care if at least one or none of the cells registered
1098          * successfully.
1099          */
1100         if (!cell_added) {
1101                 dev_warn(&dev->dev, "No MFD cells added\n");
1102                 lpc_ich_restore_config_space(dev);
1103                 return -ENODEV;
1104         }
1105 
1106         return 0;
1107 }
1108 
1109 static void lpc_ich_remove(struct pci_dev *dev)
1110 {
1111         mfd_remove_devices(&dev->dev);
1112         lpc_ich_restore_config_space(dev);
1113 }
1114 
1115 static struct pci_driver lpc_ich_driver = {
1116         .name           = "lpc_ich",
1117         .id_table       = lpc_ich_ids,
1118         .probe          = lpc_ich_probe,
1119         .remove         = lpc_ich_remove,
1120 };
1121 
1122 module_pci_driver(lpc_ich_driver);
1123 
1124 MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>");
1125 MODULE_DESCRIPTION("LPC interface for Intel ICH");
1126 MODULE_LICENSE("GPL");
1127 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us