Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/mfd/lpc_ich.c

  1 /*
  2  *  lpc_ich.c - LPC interface for Intel ICH
  3  *
  4  *  LPC bridge function of the Intel ICH contains many other
  5  *  functional units, such as Interrupt controllers, Timers,
  6  *  Power Management, System Management, GPIO, RTC, and LPC
  7  *  Configuration Registers.
  8  *
  9  *  This driver is derived from lpc_sch.
 10 
 11  *  Copyright (c) 2011 Extreme Engineering Solution, Inc.
 12  *  Author: Aaron Sierra <asierra@xes-inc.com>
 13  *
 14  *  This program is free software; you can redistribute it and/or modify
 15  *  it under the terms of the GNU General Public License 2 as published
 16  *  by the Free Software Foundation.
 17  *
 18  *  This program is distributed in the hope that it will be useful,
 19  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 20  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 21  *  GNU General Public License for more details.
 22  *
 23  *  You should have received a copy of the GNU General Public License
 24  *  along with this program; see the file COPYING.  If not, write to
 25  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 26  *
 27  *  This driver supports the following I/O Controller hubs:
 28  *      (See the intel documentation on http://developer.intel.com.)
 29  *      document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
 30  *      document number 290687-002, 298242-027: 82801BA (ICH2)
 31  *      document number 290733-003, 290739-013: 82801CA (ICH3-S)
 32  *      document number 290716-001, 290718-007: 82801CAM (ICH3-M)
 33  *      document number 290744-001, 290745-025: 82801DB (ICH4)
 34  *      document number 252337-001, 252663-008: 82801DBM (ICH4-M)
 35  *      document number 273599-001, 273645-002: 82801E (C-ICH)
 36  *      document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
 37  *      document number 300641-004, 300884-013: 6300ESB
 38  *      document number 301473-002, 301474-026: 82801F (ICH6)
 39  *      document number 313082-001, 313075-006: 631xESB, 632xESB
 40  *      document number 307013-003, 307014-024: 82801G (ICH7)
 41  *      document number 322896-001, 322897-001: NM10
 42  *      document number 313056-003, 313057-017: 82801H (ICH8)
 43  *      document number 316972-004, 316973-012: 82801I (ICH9)
 44  *      document number 319973-002, 319974-002: 82801J (ICH10)
 45  *      document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
 46  *      document number 320066-003, 320257-008: EP80597 (IICH)
 47  *      document number 324645-001, 324646-001: Cougar Point (CPT)
 48  *      document number TBD : Patsburg (PBG)
 49  *      document number TBD : DH89xxCC
 50  *      document number TBD : Panther Point
 51  *      document number TBD : Lynx Point
 52  *      document number TBD : Lynx Point-LP
 53  *      document number TBD : Wellsburg
 54  *      document number TBD : Avoton SoC
 55  *      document number TBD : Coleto Creek
 56  *      document number TBD : Wildcat Point-LP
 57  */
 58 
 59 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 60 
 61 #include <linux/kernel.h>
 62 #include <linux/module.h>
 63 #include <linux/errno.h>
 64 #include <linux/acpi.h>
 65 #include <linux/pci.h>
 66 #include <linux/mfd/core.h>
 67 #include <linux/mfd/lpc_ich.h>
 68 
 69 #define ACPIBASE                0x40
 70 #define ACPIBASE_GPE_OFF        0x28
 71 #define ACPIBASE_GPE_END        0x2f
 72 #define ACPIBASE_SMI_OFF        0x30
 73 #define ACPIBASE_SMI_END        0x33
 74 #define ACPIBASE_PMC_OFF        0x08
 75 #define ACPIBASE_PMC_END        0x0c
 76 #define ACPIBASE_TCO_OFF        0x60
 77 #define ACPIBASE_TCO_END        0x7f
 78 #define ACPICTRL_PMCBASE        0x44
 79 
 80 #define ACPIBASE_GCS_OFF        0x3410
 81 #define ACPIBASE_GCS_END        0x3414
 82 
 83 #define GPIOBASE_ICH0           0x58
 84 #define GPIOCTRL_ICH0           0x5C
 85 #define GPIOBASE_ICH6           0x48
 86 #define GPIOCTRL_ICH6           0x4C
 87 
 88 #define RCBABASE                0xf0
 89 
 90 #define wdt_io_res(i) wdt_res(0, i)
 91 #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i)
 92 #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)])
 93 
 94 struct lpc_ich_priv {
 95         int chipset;
 96 
 97         int abase;              /* ACPI base */
 98         int actrl_pbase;        /* ACPI control or PMC base */
 99         int gbase;              /* GPIO base */
100         int gctrl;              /* GPIO control */
101 
102         int abase_save;         /* Cached ACPI base value */
103         int actrl_pbase_save;           /* Cached ACPI control or PMC base value */
104         int gctrl_save;         /* Cached GPIO control value */
105 };
106 
107 static struct resource wdt_ich_res[] = {
108         /* ACPI - TCO */
109         {
110                 .flags = IORESOURCE_IO,
111         },
112         /* ACPI - SMI */
113         {
114                 .flags = IORESOURCE_IO,
115         },
116         /* GCS or PMC */
117         {
118                 .flags = IORESOURCE_MEM,
119         },
120 };
121 
122 static struct resource gpio_ich_res[] = {
123         /* GPIO */
124         {
125                 .flags = IORESOURCE_IO,
126         },
127         /* ACPI - GPE0 */
128         {
129                 .flags = IORESOURCE_IO,
130         },
131 };
132 
133 enum lpc_cells {
134         LPC_WDT = 0,
135         LPC_GPIO,
136 };
137 
138 static struct mfd_cell lpc_ich_cells[] = {
139         [LPC_WDT] = {
140                 .name = "iTCO_wdt",
141                 .num_resources = ARRAY_SIZE(wdt_ich_res),
142                 .resources = wdt_ich_res,
143                 .ignore_resource_conflicts = true,
144         },
145         [LPC_GPIO] = {
146                 .name = "gpio_ich",
147                 .num_resources = ARRAY_SIZE(gpio_ich_res),
148                 .resources = gpio_ich_res,
149                 .ignore_resource_conflicts = true,
150         },
151 };
152 
153 /* chipset related info */
154 enum lpc_chipsets {
155         LPC_ICH = 0,    /* ICH */
156         LPC_ICH0,       /* ICH0 */
157         LPC_ICH2,       /* ICH2 */
158         LPC_ICH2M,      /* ICH2-M */
159         LPC_ICH3,       /* ICH3-S */
160         LPC_ICH3M,      /* ICH3-M */
161         LPC_ICH4,       /* ICH4 */
162         LPC_ICH4M,      /* ICH4-M */
163         LPC_CICH,       /* C-ICH */
164         LPC_ICH5,       /* ICH5 & ICH5R */
165         LPC_6300ESB,    /* 6300ESB */
166         LPC_ICH6,       /* ICH6 & ICH6R */
167         LPC_ICH6M,      /* ICH6-M */
168         LPC_ICH6W,      /* ICH6W & ICH6RW */
169         LPC_631XESB,    /* 631xESB/632xESB */
170         LPC_ICH7,       /* ICH7 & ICH7R */
171         LPC_ICH7DH,     /* ICH7DH */
172         LPC_ICH7M,      /* ICH7-M & ICH7-U */
173         LPC_ICH7MDH,    /* ICH7-M DH */
174         LPC_NM10,       /* NM10 */
175         LPC_ICH8,       /* ICH8 & ICH8R */
176         LPC_ICH8DH,     /* ICH8DH */
177         LPC_ICH8DO,     /* ICH8DO */
178         LPC_ICH8M,      /* ICH8M */
179         LPC_ICH8ME,     /* ICH8M-E */
180         LPC_ICH9,       /* ICH9 */
181         LPC_ICH9R,      /* ICH9R */
182         LPC_ICH9DH,     /* ICH9DH */
183         LPC_ICH9DO,     /* ICH9DO */
184         LPC_ICH9M,      /* ICH9M */
185         LPC_ICH9ME,     /* ICH9M-E */
186         LPC_ICH10,      /* ICH10 */
187         LPC_ICH10R,     /* ICH10R */
188         LPC_ICH10D,     /* ICH10D */
189         LPC_ICH10DO,    /* ICH10DO */
190         LPC_PCH,        /* PCH Desktop Full Featured */
191         LPC_PCHM,       /* PCH Mobile Full Featured */
192         LPC_P55,        /* P55 */
193         LPC_PM55,       /* PM55 */
194         LPC_H55,        /* H55 */
195         LPC_QM57,       /* QM57 */
196         LPC_H57,        /* H57 */
197         LPC_HM55,       /* HM55 */
198         LPC_Q57,        /* Q57 */
199         LPC_HM57,       /* HM57 */
200         LPC_PCHMSFF,    /* PCH Mobile SFF Full Featured */
201         LPC_QS57,       /* QS57 */
202         LPC_3400,       /* 3400 */
203         LPC_3420,       /* 3420 */
204         LPC_3450,       /* 3450 */
205         LPC_EP80579,    /* EP80579 */
206         LPC_CPT,        /* Cougar Point */
207         LPC_CPTD,       /* Cougar Point Desktop */
208         LPC_CPTM,       /* Cougar Point Mobile */
209         LPC_PBG,        /* Patsburg */
210         LPC_DH89XXCC,   /* DH89xxCC */
211         LPC_PPT,        /* Panther Point */
212         LPC_LPT,        /* Lynx Point */
213         LPC_LPT_LP,     /* Lynx Point-LP */
214         LPC_WBG,        /* Wellsburg */
215         LPC_AVN,        /* Avoton SoC */
216         LPC_BAYTRAIL,   /* Bay Trail SoC */
217         LPC_COLETO,     /* Coleto Creek */
218         LPC_WPT_LP,     /* Wildcat Point-LP */
219 };
220 
221 static struct lpc_ich_info lpc_chipset_info[] = {
222         [LPC_ICH] = {
223                 .name = "ICH",
224                 .iTCO_version = 1,
225         },
226         [LPC_ICH0] = {
227                 .name = "ICH0",
228                 .iTCO_version = 1,
229         },
230         [LPC_ICH2] = {
231                 .name = "ICH2",
232                 .iTCO_version = 1,
233         },
234         [LPC_ICH2M] = {
235                 .name = "ICH2-M",
236                 .iTCO_version = 1,
237         },
238         [LPC_ICH3] = {
239                 .name = "ICH3-S",
240                 .iTCO_version = 1,
241         },
242         [LPC_ICH3M] = {
243                 .name = "ICH3-M",
244                 .iTCO_version = 1,
245         },
246         [LPC_ICH4] = {
247                 .name = "ICH4",
248                 .iTCO_version = 1,
249         },
250         [LPC_ICH4M] = {
251                 .name = "ICH4-M",
252                 .iTCO_version = 1,
253         },
254         [LPC_CICH] = {
255                 .name = "C-ICH",
256                 .iTCO_version = 1,
257         },
258         [LPC_ICH5] = {
259                 .name = "ICH5 or ICH5R",
260                 .iTCO_version = 1,
261         },
262         [LPC_6300ESB] = {
263                 .name = "6300ESB",
264                 .iTCO_version = 1,
265         },
266         [LPC_ICH6] = {
267                 .name = "ICH6 or ICH6R",
268                 .iTCO_version = 2,
269                 .gpio_version = ICH_V6_GPIO,
270         },
271         [LPC_ICH6M] = {
272                 .name = "ICH6-M",
273                 .iTCO_version = 2,
274                 .gpio_version = ICH_V6_GPIO,
275         },
276         [LPC_ICH6W] = {
277                 .name = "ICH6W or ICH6RW",
278                 .iTCO_version = 2,
279                 .gpio_version = ICH_V6_GPIO,
280         },
281         [LPC_631XESB] = {
282                 .name = "631xESB/632xESB",
283                 .iTCO_version = 2,
284                 .gpio_version = ICH_V6_GPIO,
285         },
286         [LPC_ICH7] = {
287                 .name = "ICH7 or ICH7R",
288                 .iTCO_version = 2,
289                 .gpio_version = ICH_V7_GPIO,
290         },
291         [LPC_ICH7DH] = {
292                 .name = "ICH7DH",
293                 .iTCO_version = 2,
294                 .gpio_version = ICH_V7_GPIO,
295         },
296         [LPC_ICH7M] = {
297                 .name = "ICH7-M or ICH7-U",
298                 .iTCO_version = 2,
299                 .gpio_version = ICH_V7_GPIO,
300         },
301         [LPC_ICH7MDH] = {
302                 .name = "ICH7-M DH",
303                 .iTCO_version = 2,
304                 .gpio_version = ICH_V7_GPIO,
305         },
306         [LPC_NM10] = {
307                 .name = "NM10",
308                 .iTCO_version = 2,
309                 .gpio_version = ICH_V7_GPIO,
310         },
311         [LPC_ICH8] = {
312                 .name = "ICH8 or ICH8R",
313                 .iTCO_version = 2,
314                 .gpio_version = ICH_V7_GPIO,
315         },
316         [LPC_ICH8DH] = {
317                 .name = "ICH8DH",
318                 .iTCO_version = 2,
319                 .gpio_version = ICH_V7_GPIO,
320         },
321         [LPC_ICH8DO] = {
322                 .name = "ICH8DO",
323                 .iTCO_version = 2,
324                 .gpio_version = ICH_V7_GPIO,
325         },
326         [LPC_ICH8M] = {
327                 .name = "ICH8M",
328                 .iTCO_version = 2,
329                 .gpio_version = ICH_V7_GPIO,
330         },
331         [LPC_ICH8ME] = {
332                 .name = "ICH8M-E",
333                 .iTCO_version = 2,
334                 .gpio_version = ICH_V7_GPIO,
335         },
336         [LPC_ICH9] = {
337                 .name = "ICH9",
338                 .iTCO_version = 2,
339                 .gpio_version = ICH_V9_GPIO,
340         },
341         [LPC_ICH9R] = {
342                 .name = "ICH9R",
343                 .iTCO_version = 2,
344                 .gpio_version = ICH_V9_GPIO,
345         },
346         [LPC_ICH9DH] = {
347                 .name = "ICH9DH",
348                 .iTCO_version = 2,
349                 .gpio_version = ICH_V9_GPIO,
350         },
351         [LPC_ICH9DO] = {
352                 .name = "ICH9DO",
353                 .iTCO_version = 2,
354                 .gpio_version = ICH_V9_GPIO,
355         },
356         [LPC_ICH9M] = {
357                 .name = "ICH9M",
358                 .iTCO_version = 2,
359                 .gpio_version = ICH_V9_GPIO,
360         },
361         [LPC_ICH9ME] = {
362                 .name = "ICH9M-E",
363                 .iTCO_version = 2,
364                 .gpio_version = ICH_V9_GPIO,
365         },
366         [LPC_ICH10] = {
367                 .name = "ICH10",
368                 .iTCO_version = 2,
369                 .gpio_version = ICH_V10CONS_GPIO,
370         },
371         [LPC_ICH10R] = {
372                 .name = "ICH10R",
373                 .iTCO_version = 2,
374                 .gpio_version = ICH_V10CONS_GPIO,
375         },
376         [LPC_ICH10D] = {
377                 .name = "ICH10D",
378                 .iTCO_version = 2,
379                 .gpio_version = ICH_V10CORP_GPIO,
380         },
381         [LPC_ICH10DO] = {
382                 .name = "ICH10DO",
383                 .iTCO_version = 2,
384                 .gpio_version = ICH_V10CORP_GPIO,
385         },
386         [LPC_PCH] = {
387                 .name = "PCH Desktop Full Featured",
388                 .iTCO_version = 2,
389                 .gpio_version = ICH_V5_GPIO,
390         },
391         [LPC_PCHM] = {
392                 .name = "PCH Mobile Full Featured",
393                 .iTCO_version = 2,
394                 .gpio_version = ICH_V5_GPIO,
395         },
396         [LPC_P55] = {
397                 .name = "P55",
398                 .iTCO_version = 2,
399                 .gpio_version = ICH_V5_GPIO,
400         },
401         [LPC_PM55] = {
402                 .name = "PM55",
403                 .iTCO_version = 2,
404                 .gpio_version = ICH_V5_GPIO,
405         },
406         [LPC_H55] = {
407                 .name = "H55",
408                 .iTCO_version = 2,
409                 .gpio_version = ICH_V5_GPIO,
410         },
411         [LPC_QM57] = {
412                 .name = "QM57",
413                 .iTCO_version = 2,
414                 .gpio_version = ICH_V5_GPIO,
415         },
416         [LPC_H57] = {
417                 .name = "H57",
418                 .iTCO_version = 2,
419                 .gpio_version = ICH_V5_GPIO,
420         },
421         [LPC_HM55] = {
422                 .name = "HM55",
423                 .iTCO_version = 2,
424                 .gpio_version = ICH_V5_GPIO,
425         },
426         [LPC_Q57] = {
427                 .name = "Q57",
428                 .iTCO_version = 2,
429                 .gpio_version = ICH_V5_GPIO,
430         },
431         [LPC_HM57] = {
432                 .name = "HM57",
433                 .iTCO_version = 2,
434                 .gpio_version = ICH_V5_GPIO,
435         },
436         [LPC_PCHMSFF] = {
437                 .name = "PCH Mobile SFF Full Featured",
438                 .iTCO_version = 2,
439                 .gpio_version = ICH_V5_GPIO,
440         },
441         [LPC_QS57] = {
442                 .name = "QS57",
443                 .iTCO_version = 2,
444                 .gpio_version = ICH_V5_GPIO,
445         },
446         [LPC_3400] = {
447                 .name = "3400",
448                 .iTCO_version = 2,
449                 .gpio_version = ICH_V5_GPIO,
450         },
451         [LPC_3420] = {
452                 .name = "3420",
453                 .iTCO_version = 2,
454                 .gpio_version = ICH_V5_GPIO,
455         },
456         [LPC_3450] = {
457                 .name = "3450",
458                 .iTCO_version = 2,
459                 .gpio_version = ICH_V5_GPIO,
460         },
461         [LPC_EP80579] = {
462                 .name = "EP80579",
463                 .iTCO_version = 2,
464         },
465         [LPC_CPT] = {
466                 .name = "Cougar Point",
467                 .iTCO_version = 2,
468                 .gpio_version = ICH_V5_GPIO,
469         },
470         [LPC_CPTD] = {
471                 .name = "Cougar Point Desktop",
472                 .iTCO_version = 2,
473                 .gpio_version = ICH_V5_GPIO,
474         },
475         [LPC_CPTM] = {
476                 .name = "Cougar Point Mobile",
477                 .iTCO_version = 2,
478                 .gpio_version = ICH_V5_GPIO,
479         },
480         [LPC_PBG] = {
481                 .name = "Patsburg",
482                 .iTCO_version = 2,
483         },
484         [LPC_DH89XXCC] = {
485                 .name = "DH89xxCC",
486                 .iTCO_version = 2,
487         },
488         [LPC_PPT] = {
489                 .name = "Panther Point",
490                 .iTCO_version = 2,
491                 .gpio_version = ICH_V5_GPIO,
492         },
493         [LPC_LPT] = {
494                 .name = "Lynx Point",
495                 .iTCO_version = 2,
496         },
497         [LPC_LPT_LP] = {
498                 .name = "Lynx Point_LP",
499                 .iTCO_version = 2,
500         },
501         [LPC_WBG] = {
502                 .name = "Wellsburg",
503                 .iTCO_version = 2,
504         },
505         [LPC_AVN] = {
506                 .name = "Avoton SoC",
507                 .iTCO_version = 3,
508                 .gpio_version = AVOTON_GPIO,
509         },
510         [LPC_BAYTRAIL] = {
511                 .name = "Bay Trail SoC",
512                 .iTCO_version = 3,
513         },
514         [LPC_COLETO] = {
515                 .name = "Coleto Creek",
516                 .iTCO_version = 2,
517         },
518         [LPC_WPT_LP] = {
519                 .name = "Wildcat Point_LP",
520                 .iTCO_version = 2,
521         },
522 };
523 
524 /*
525  * This data only exists for exporting the supported PCI ids
526  * via MODULE_DEVICE_TABLE.  We do not actually register a
527  * pci_driver, because the I/O Controller Hub has also other
528  * functions that probably will be registered by other drivers.
529  */
530 static const struct pci_device_id lpc_ich_ids[] = {
531         { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH},
532         { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0},
533         { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2},
534         { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M},
535         { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3},
536         { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M},
537         { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4},
538         { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M},
539         { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH},
540         { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5},
541         { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB},
542         { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6},
543         { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M},
544         { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W},
545         { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB},
546         { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB},
547         { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB},
548         { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB},
549         { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB},
550         { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB},
551         { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB},
552         { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB},
553         { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB},
554         { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB},
555         { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB},
556         { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB},
557         { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB},
558         { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB},
559         { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB},
560         { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB},
561         { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7},
562         { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH},
563         { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M},
564         { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH},
565         { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10},
566         { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8},
567         { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH},
568         { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO},
569         { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M},
570         { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME},
571         { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9},
572         { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R},
573         { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH},
574         { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO},
575         { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M},
576         { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME},
577         { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10},
578         { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R},
579         { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D},
580         { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO},
581         { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH},
582         { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM},
583         { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55},
584         { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55},
585         { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55},
586         { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57},
587         { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57},
588         { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55},
589         { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57},
590         { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57},
591         { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF},
592         { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57},
593         { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400},
594         { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
595         { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
596         { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
597         { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT},
598         { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD},
599         { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM},
600         { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT},
601         { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT},
602         { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT},
603         { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT},
604         { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT},
605         { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT},
606         { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT},
607         { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT},
608         { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT},
609         { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT},
610         { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT},
611         { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT},
612         { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT},
613         { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT},
614         { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT},
615         { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT},
616         { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT},
617         { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT},
618         { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT},
619         { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT},
620         { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT},
621         { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT},
622         { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT},
623         { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT},
624         { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT},
625         { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT},
626         { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT},
627         { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT},
628         { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG},
629         { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG},
630         { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC},
631         { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT},
632         { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT},
633         { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT},
634         { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT},
635         { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT},
636         { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT},
637         { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT},
638         { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT},
639         { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT},
640         { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT},
641         { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT},
642         { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT},
643         { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT},
644         { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT},
645         { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT},
646         { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT},
647         { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT},
648         { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT},
649         { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT},
650         { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT},
651         { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT},
652         { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT},
653         { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT},
654         { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT},
655         { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT},
656         { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT},
657         { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT},
658         { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT},
659         { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT},
660         { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT},
661         { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT},
662         { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT},
663         { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
664         { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
665         { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
666         { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT},
667         { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT},
668         { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT},
669         { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT},
670         { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT},
671         { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT},
672         { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT},
673         { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT},
674         { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT},
675         { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT},
676         { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT},
677         { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT},
678         { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT},
679         { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT},
680         { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT},
681         { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT},
682         { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT},
683         { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT},
684         { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT},
685         { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT},
686         { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT},
687         { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT},
688         { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT},
689         { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT},
690         { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT},
691         { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT},
692         { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT},
693         { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT},
694         { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT},
695         { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP},
696         { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP},
697         { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP},
698         { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP},
699         { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP},
700         { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP},
701         { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP},
702         { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP},
703         { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG},
704         { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG},
705         { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG},
706         { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG},
707         { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG},
708         { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG},
709         { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG},
710         { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG},
711         { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG},
712         { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG},
713         { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG},
714         { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG},
715         { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG},
716         { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG},
717         { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG},
718         { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG},
719         { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG},
720         { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG},
721         { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG},
722         { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG},
723         { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG},
724         { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG},
725         { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG},
726         { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG},
727         { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG},
728         { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG},
729         { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG},
730         { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG},
731         { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG},
732         { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG},
733         { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG},
734         { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG},
735         { PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN},
736         { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN},
737         { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN},
738         { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN},
739         { PCI_VDEVICE(INTEL, 0x0f1c), LPC_BAYTRAIL},
740         { PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO},
741         { PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP},
742         { PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP},
743         { PCI_VDEVICE(INTEL, 0x9cc3), LPC_WPT_LP},
744         { PCI_VDEVICE(INTEL, 0x9cc5), LPC_WPT_LP},
745         { PCI_VDEVICE(INTEL, 0x9cc6), LPC_WPT_LP},
746         { PCI_VDEVICE(INTEL, 0x9cc7), LPC_WPT_LP},
747         { PCI_VDEVICE(INTEL, 0x9cc9), LPC_WPT_LP},
748         { 0, },                 /* End of list */
749 };
750 MODULE_DEVICE_TABLE(pci, lpc_ich_ids);
751 
752 static void lpc_ich_restore_config_space(struct pci_dev *dev)
753 {
754         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
755 
756         if (priv->abase_save >= 0) {
757                 pci_write_config_byte(dev, priv->abase, priv->abase_save);
758                 priv->abase_save = -1;
759         }
760 
761         if (priv->actrl_pbase_save >= 0) {
762                 pci_write_config_byte(dev, priv->actrl_pbase,
763                         priv->actrl_pbase_save);
764                 priv->actrl_pbase_save = -1;
765         }
766 
767         if (priv->gctrl_save >= 0) {
768                 pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save);
769                 priv->gctrl_save = -1;
770         }
771 }
772 
773 static void lpc_ich_enable_acpi_space(struct pci_dev *dev)
774 {
775         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
776         u8 reg_save;
777 
778         switch (lpc_chipset_info[priv->chipset].iTCO_version) {
779         case 3:
780                 /*
781                  * Some chipsets (eg Avoton) enable the ACPI space in the
782                  * ACPI BASE register.
783                  */
784                 pci_read_config_byte(dev, priv->abase, &reg_save);
785                 pci_write_config_byte(dev, priv->abase, reg_save | 0x2);
786                 priv->abase_save = reg_save;
787                 break;
788         default:
789                 /*
790                  * Most chipsets enable the ACPI space in the ACPI control
791                  * register.
792                  */
793                 pci_read_config_byte(dev, priv->actrl_pbase, &reg_save);
794                 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80);
795                 priv->actrl_pbase_save = reg_save;
796                 break;
797         }
798 }
799 
800 static void lpc_ich_enable_gpio_space(struct pci_dev *dev)
801 {
802         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
803         u8 reg_save;
804 
805         pci_read_config_byte(dev, priv->gctrl, &reg_save);
806         pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10);
807         priv->gctrl_save = reg_save;
808 }
809 
810 static void lpc_ich_enable_pmc_space(struct pci_dev *dev)
811 {
812         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
813         u8 reg_save;
814 
815         pci_read_config_byte(dev, priv->actrl_pbase, &reg_save);
816         pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2);
817 
818         priv->actrl_pbase_save = reg_save;
819 }
820 
821 static void lpc_ich_finalize_cell(struct pci_dev *dev, struct mfd_cell *cell)
822 {
823         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
824 
825         cell->platform_data = &lpc_chipset_info[priv->chipset];
826         cell->pdata_size = sizeof(struct lpc_ich_info);
827 }
828 
829 /*
830  * We don't check for resource conflict globally. There are 2 or 3 independent
831  * GPIO groups and it's enough to have access to one of these to instantiate
832  * the device.
833  */
834 static int lpc_ich_check_conflict_gpio(struct resource *res)
835 {
836         int ret;
837         u8 use_gpio = 0;
838 
839         if (resource_size(res) >= 0x50 &&
840             !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3"))
841                 use_gpio |= 1 << 2;
842 
843         if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2"))
844                 use_gpio |= 1 << 1;
845 
846         ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1");
847         if (!ret)
848                 use_gpio |= 1 << 0;
849 
850         return use_gpio ? use_gpio : ret;
851 }
852 
853 static int lpc_ich_init_gpio(struct pci_dev *dev)
854 {
855         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
856         u32 base_addr_cfg;
857         u32 base_addr;
858         int ret;
859         bool acpi_conflict = false;
860         struct resource *res;
861 
862         /* Setup power management base register */
863         pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
864         base_addr = base_addr_cfg & 0x0000ff80;
865         if (!base_addr) {
866                 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
867                 lpc_ich_cells[LPC_GPIO].num_resources--;
868                 goto gpe0_done;
869         }
870 
871         res = &gpio_ich_res[ICH_RES_GPE0];
872         res->start = base_addr + ACPIBASE_GPE_OFF;
873         res->end = base_addr + ACPIBASE_GPE_END;
874         ret = acpi_check_resource_conflict(res);
875         if (ret) {
876                 /*
877                  * This isn't fatal for the GPIO, but we have to make sure that
878                  * the platform_device subsystem doesn't see this resource
879                  * or it will register an invalid region.
880                  */
881                 lpc_ich_cells[LPC_GPIO].num_resources--;
882                 acpi_conflict = true;
883         } else {
884                 lpc_ich_enable_acpi_space(dev);
885         }
886 
887 gpe0_done:
888         /* Setup GPIO base register */
889         pci_read_config_dword(dev, priv->gbase, &base_addr_cfg);
890         base_addr = base_addr_cfg & 0x0000ff80;
891         if (!base_addr) {
892                 dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n");
893                 ret = -ENODEV;
894                 goto gpio_done;
895         }
896 
897         /* Older devices provide fewer GPIO and have a smaller resource size. */
898         res = &gpio_ich_res[ICH_RES_GPIO];
899         res->start = base_addr;
900         switch (lpc_chipset_info[priv->chipset].gpio_version) {
901         case ICH_V5_GPIO:
902         case ICH_V10CORP_GPIO:
903                 res->end = res->start + 128 - 1;
904                 break;
905         default:
906                 res->end = res->start + 64 - 1;
907                 break;
908         }
909 
910         ret = lpc_ich_check_conflict_gpio(res);
911         if (ret < 0) {
912                 /* this isn't necessarily fatal for the GPIO */
913                 acpi_conflict = true;
914                 goto gpio_done;
915         }
916         lpc_chipset_info[priv->chipset].use_gpio = ret;
917         lpc_ich_enable_gpio_space(dev);
918 
919         lpc_ich_finalize_cell(dev, &lpc_ich_cells[LPC_GPIO]);
920         ret = mfd_add_devices(&dev->dev, -1, &lpc_ich_cells[LPC_GPIO],
921                               1, NULL, 0, NULL);
922 
923 gpio_done:
924         if (acpi_conflict)
925                 pr_warn("Resource conflict(s) found affecting %s\n",
926                                 lpc_ich_cells[LPC_GPIO].name);
927         return ret;
928 }
929 
930 static int lpc_ich_init_wdt(struct pci_dev *dev)
931 {
932         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
933         u32 base_addr_cfg;
934         u32 base_addr;
935         int ret;
936         struct resource *res;
937 
938         /* Setup power management base register */
939         pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
940         base_addr = base_addr_cfg & 0x0000ff80;
941         if (!base_addr) {
942                 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
943                 ret = -ENODEV;
944                 goto wdt_done;
945         }
946 
947         res = wdt_io_res(ICH_RES_IO_TCO);
948         res->start = base_addr + ACPIBASE_TCO_OFF;
949         res->end = base_addr + ACPIBASE_TCO_END;
950 
951         res = wdt_io_res(ICH_RES_IO_SMI);
952         res->start = base_addr + ACPIBASE_SMI_OFF;
953         res->end = base_addr + ACPIBASE_SMI_END;
954 
955         lpc_ich_enable_acpi_space(dev);
956 
957         /*
958          * iTCO v2:
959          * Get the Memory-Mapped GCS register. To get access to it
960          * we have to read RCBA from PCI Config space 0xf0 and use
961          * it as base. GCS = RCBA + ICH6_GCS(0x3410).
962          *
963          * iTCO v3:
964          * Get the Power Management Configuration register.  To get access
965          * to it we have to read the PMC BASE from config space and address
966          * the register at offset 0x8.
967          */
968         if (lpc_chipset_info[priv->chipset].iTCO_version == 1) {
969                 /* Don't register iomem for TCO ver 1 */
970                 lpc_ich_cells[LPC_WDT].num_resources--;
971         } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) {
972                 pci_read_config_dword(dev, RCBABASE, &base_addr_cfg);
973                 base_addr = base_addr_cfg & 0xffffc000;
974                 if (!(base_addr_cfg & 1)) {
975                         dev_notice(&dev->dev, "RCBA is disabled by "
976                                         "hardware/BIOS, device disabled\n");
977                         ret = -ENODEV;
978                         goto wdt_done;
979                 }
980                 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
981                 res->start = base_addr + ACPIBASE_GCS_OFF;
982                 res->end = base_addr + ACPIBASE_GCS_END;
983         } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) {
984                 lpc_ich_enable_pmc_space(dev);
985                 pci_read_config_dword(dev, ACPICTRL_PMCBASE, &base_addr_cfg);
986                 base_addr = base_addr_cfg & 0xfffffe00;
987 
988                 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
989                 res->start = base_addr + ACPIBASE_PMC_OFF;
990                 res->end = base_addr + ACPIBASE_PMC_END;
991         }
992 
993         lpc_ich_finalize_cell(dev, &lpc_ich_cells[LPC_WDT]);
994         ret = mfd_add_devices(&dev->dev, -1, &lpc_ich_cells[LPC_WDT],
995                               1, NULL, 0, NULL);
996 
997 wdt_done:
998         return ret;
999 }
1000 
1001 static int lpc_ich_probe(struct pci_dev *dev,
1002                                 const struct pci_device_id *id)
1003 {
1004         struct lpc_ich_priv *priv;
1005         int ret;
1006         bool cell_added = false;
1007 
1008         priv = devm_kzalloc(&dev->dev,
1009                             sizeof(struct lpc_ich_priv), GFP_KERNEL);
1010         if (!priv)
1011                 return -ENOMEM;
1012 
1013         priv->chipset = id->driver_data;
1014 
1015         priv->actrl_pbase_save = -1;
1016         priv->abase_save = -1;
1017 
1018         priv->abase = ACPIBASE;
1019         priv->actrl_pbase = ACPICTRL_PMCBASE;
1020 
1021         priv->gctrl_save = -1;
1022         if (priv->chipset <= LPC_ICH5) {
1023                 priv->gbase = GPIOBASE_ICH0;
1024                 priv->gctrl = GPIOCTRL_ICH0;
1025         } else {
1026                 priv->gbase = GPIOBASE_ICH6;
1027                 priv->gctrl = GPIOCTRL_ICH6;
1028         }
1029 
1030         pci_set_drvdata(dev, priv);
1031 
1032         if (lpc_chipset_info[priv->chipset].iTCO_version) {
1033                 ret = lpc_ich_init_wdt(dev);
1034                 if (!ret)
1035                         cell_added = true;
1036         }
1037 
1038         if (lpc_chipset_info[priv->chipset].gpio_version) {
1039                 ret = lpc_ich_init_gpio(dev);
1040                 if (!ret)
1041                         cell_added = true;
1042         }
1043 
1044         /*
1045          * We only care if at least one or none of the cells registered
1046          * successfully.
1047          */
1048         if (!cell_added) {
1049                 dev_warn(&dev->dev, "No MFD cells added\n");
1050                 lpc_ich_restore_config_space(dev);
1051                 return -ENODEV;
1052         }
1053 
1054         return 0;
1055 }
1056 
1057 static void lpc_ich_remove(struct pci_dev *dev)
1058 {
1059         mfd_remove_devices(&dev->dev);
1060         lpc_ich_restore_config_space(dev);
1061 }
1062 
1063 static struct pci_driver lpc_ich_driver = {
1064         .name           = "lpc_ich",
1065         .id_table       = lpc_ich_ids,
1066         .probe          = lpc_ich_probe,
1067         .remove         = lpc_ich_remove,
1068 };
1069 
1070 module_pci_driver(lpc_ich_driver);
1071 
1072 MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>");
1073 MODULE_DESCRIPTION("LPC interface for Intel ICH");
1074 MODULE_LICENSE("GPL");
1075 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us