Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/mfd/asic3.c

  1 /*
  2  * driver/mfd/asic3.c
  3  *
  4  * Compaq ASIC3 support.
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License version 2 as
  8  * published by the Free Software Foundation.
  9  *
 10  * Copyright 2001 Compaq Computer Corporation.
 11  * Copyright 2004-2005 Phil Blundell
 12  * Copyright 2007-2008 OpenedHand Ltd.
 13  *
 14  * Authors: Phil Blundell <pb@handhelds.org>,
 15  *          Samuel Ortiz <sameo@openedhand.com>
 16  *
 17  */
 18 
 19 #include <linux/kernel.h>
 20 #include <linux/delay.h>
 21 #include <linux/irq.h>
 22 #include <linux/gpio.h>
 23 #include <linux/export.h>
 24 #include <linux/io.h>
 25 #include <linux/slab.h>
 26 #include <linux/spinlock.h>
 27 #include <linux/platform_device.h>
 28 
 29 #include <linux/mfd/asic3.h>
 30 #include <linux/mfd/core.h>
 31 #include <linux/mfd/ds1wm.h>
 32 #include <linux/mfd/tmio.h>
 33 
 34 enum {
 35         ASIC3_CLOCK_SPI,
 36         ASIC3_CLOCK_OWM,
 37         ASIC3_CLOCK_PWM0,
 38         ASIC3_CLOCK_PWM1,
 39         ASIC3_CLOCK_LED0,
 40         ASIC3_CLOCK_LED1,
 41         ASIC3_CLOCK_LED2,
 42         ASIC3_CLOCK_SD_HOST,
 43         ASIC3_CLOCK_SD_BUS,
 44         ASIC3_CLOCK_SMBUS,
 45         ASIC3_CLOCK_EX0,
 46         ASIC3_CLOCK_EX1,
 47 };
 48 
 49 struct asic3_clk {
 50         int enabled;
 51         unsigned int cdex;
 52         unsigned long rate;
 53 };
 54 
 55 #define INIT_CDEX(_name, _rate) \
 56         [ASIC3_CLOCK_##_name] = {               \
 57                 .cdex = CLOCK_CDEX_##_name,     \
 58                 .rate = _rate,                  \
 59         }
 60 
 61 static struct asic3_clk asic3_clk_init[] __initdata = {
 62         INIT_CDEX(SPI, 0),
 63         INIT_CDEX(OWM, 5000000),
 64         INIT_CDEX(PWM0, 0),
 65         INIT_CDEX(PWM1, 0),
 66         INIT_CDEX(LED0, 0),
 67         INIT_CDEX(LED1, 0),
 68         INIT_CDEX(LED2, 0),
 69         INIT_CDEX(SD_HOST, 24576000),
 70         INIT_CDEX(SD_BUS, 12288000),
 71         INIT_CDEX(SMBUS, 0),
 72         INIT_CDEX(EX0, 32768),
 73         INIT_CDEX(EX1, 24576000),
 74 };
 75 
 76 struct asic3 {
 77         void __iomem *mapping;
 78         unsigned int bus_shift;
 79         unsigned int irq_nr;
 80         unsigned int irq_base;
 81         spinlock_t lock;
 82         u16 irq_bothedge[4];
 83         struct gpio_chip gpio;
 84         struct device *dev;
 85         void __iomem *tmio_cnf;
 86 
 87         struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)];
 88 };
 89 
 90 static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
 91 
 92 void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 value)
 93 {
 94         iowrite16(value, asic->mapping +
 95                   (reg >> asic->bus_shift));
 96 }
 97 EXPORT_SYMBOL_GPL(asic3_write_register);
 98 
 99 u32 asic3_read_register(struct asic3 *asic, unsigned int reg)
100 {
101         return ioread16(asic->mapping +
102                         (reg >> asic->bus_shift));
103 }
104 EXPORT_SYMBOL_GPL(asic3_read_register);
105 
106 static void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
107 {
108         unsigned long flags;
109         u32 val;
110 
111         spin_lock_irqsave(&asic->lock, flags);
112         val = asic3_read_register(asic, reg);
113         if (set)
114                 val |= bits;
115         else
116                 val &= ~bits;
117         asic3_write_register(asic, reg, val);
118         spin_unlock_irqrestore(&asic->lock, flags);
119 }
120 
121 /* IRQs */
122 #define MAX_ASIC_ISR_LOOPS    20
123 #define ASIC3_GPIO_BASE_INCR \
124         (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
125 
126 static void asic3_irq_flip_edge(struct asic3 *asic,
127                                 u32 base, int bit)
128 {
129         u16 edge;
130         unsigned long flags;
131 
132         spin_lock_irqsave(&asic->lock, flags);
133         edge = asic3_read_register(asic,
134                                    base + ASIC3_GPIO_EDGE_TRIGGER);
135         edge ^= bit;
136         asic3_write_register(asic,
137                              base + ASIC3_GPIO_EDGE_TRIGGER, edge);
138         spin_unlock_irqrestore(&asic->lock, flags);
139 }
140 
141 static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
142 {
143         struct asic3 *asic = irq_desc_get_handler_data(desc);
144         struct irq_data *data = irq_desc_get_irq_data(desc);
145         int iter, i;
146         unsigned long flags;
147 
148         data->chip->irq_ack(data);
149 
150         for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
151                 u32 status;
152                 int bank;
153 
154                 spin_lock_irqsave(&asic->lock, flags);
155                 status = asic3_read_register(asic,
156                                              ASIC3_OFFSET(INTR, P_INT_STAT));
157                 spin_unlock_irqrestore(&asic->lock, flags);
158 
159                 /* Check all ten register bits */
160                 if ((status & 0x3ff) == 0)
161                         break;
162 
163                 /* Handle GPIO IRQs */
164                 for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
165                         if (status & (1 << bank)) {
166                                 unsigned long base, istat;
167 
168                                 base = ASIC3_GPIO_A_BASE
169                                        + bank * ASIC3_GPIO_BASE_INCR;
170 
171                                 spin_lock_irqsave(&asic->lock, flags);
172                                 istat = asic3_read_register(asic,
173                                                             base +
174                                                             ASIC3_GPIO_INT_STATUS);
175                                 /* Clearing IntStatus */
176                                 asic3_write_register(asic,
177                                                      base +
178                                                      ASIC3_GPIO_INT_STATUS, 0);
179                                 spin_unlock_irqrestore(&asic->lock, flags);
180 
181                                 for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
182                                         int bit = (1 << i);
183                                         unsigned int irqnr;
184 
185                                         if (!(istat & bit))
186                                                 continue;
187 
188                                         irqnr = asic->irq_base +
189                                                 (ASIC3_GPIOS_PER_BANK * bank)
190                                                 + i;
191                                         generic_handle_irq(irqnr);
192                                         if (asic->irq_bothedge[bank] & bit)
193                                                 asic3_irq_flip_edge(asic, base,
194                                                                     bit);
195                                 }
196                         }
197                 }
198 
199                 /* Handle remaining IRQs in the status register */
200                 for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
201                         /* They start at bit 4 and go up */
202                         if (status & (1 << (i - ASIC3_NUM_GPIOS + 4)))
203                                 generic_handle_irq(asic->irq_base + i);
204                 }
205         }
206 
207         if (iter >= MAX_ASIC_ISR_LOOPS)
208                 dev_err(asic->dev, "interrupt processing overrun\n");
209 }
210 
211 static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
212 {
213         int n;
214 
215         n = (irq - asic->irq_base) >> 4;
216 
217         return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
218 }
219 
220 static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
221 {
222         return (irq - asic->irq_base) & 0xf;
223 }
224 
225 static void asic3_mask_gpio_irq(struct irq_data *data)
226 {
227         struct asic3 *asic = irq_data_get_irq_chip_data(data);
228         u32 val, bank, index;
229         unsigned long flags;
230 
231         bank = asic3_irq_to_bank(asic, data->irq);
232         index = asic3_irq_to_index(asic, data->irq);
233 
234         spin_lock_irqsave(&asic->lock, flags);
235         val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
236         val |= 1 << index;
237         asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
238         spin_unlock_irqrestore(&asic->lock, flags);
239 }
240 
241 static void asic3_mask_irq(struct irq_data *data)
242 {
243         struct asic3 *asic = irq_data_get_irq_chip_data(data);
244         int regval;
245         unsigned long flags;
246 
247         spin_lock_irqsave(&asic->lock, flags);
248         regval = asic3_read_register(asic,
249                                      ASIC3_INTR_BASE +
250                                      ASIC3_INTR_INT_MASK);
251 
252         regval &= ~(ASIC3_INTMASK_MASK0 <<
253                     (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
254 
255         asic3_write_register(asic,
256                              ASIC3_INTR_BASE +
257                              ASIC3_INTR_INT_MASK,
258                              regval);
259         spin_unlock_irqrestore(&asic->lock, flags);
260 }
261 
262 static void asic3_unmask_gpio_irq(struct irq_data *data)
263 {
264         struct asic3 *asic = irq_data_get_irq_chip_data(data);
265         u32 val, bank, index;
266         unsigned long flags;
267 
268         bank = asic3_irq_to_bank(asic, data->irq);
269         index = asic3_irq_to_index(asic, data->irq);
270 
271         spin_lock_irqsave(&asic->lock, flags);
272         val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
273         val &= ~(1 << index);
274         asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
275         spin_unlock_irqrestore(&asic->lock, flags);
276 }
277 
278 static void asic3_unmask_irq(struct irq_data *data)
279 {
280         struct asic3 *asic = irq_data_get_irq_chip_data(data);
281         int regval;
282         unsigned long flags;
283 
284         spin_lock_irqsave(&asic->lock, flags);
285         regval = asic3_read_register(asic,
286                                      ASIC3_INTR_BASE +
287                                      ASIC3_INTR_INT_MASK);
288 
289         regval |= (ASIC3_INTMASK_MASK0 <<
290                    (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
291 
292         asic3_write_register(asic,
293                              ASIC3_INTR_BASE +
294                              ASIC3_INTR_INT_MASK,
295                              regval);
296         spin_unlock_irqrestore(&asic->lock, flags);
297 }
298 
299 static int asic3_gpio_irq_type(struct irq_data *data, unsigned int type)
300 {
301         struct asic3 *asic = irq_data_get_irq_chip_data(data);
302         u32 bank, index;
303         u16 trigger, level, edge, bit;
304         unsigned long flags;
305 
306         bank = asic3_irq_to_bank(asic, data->irq);
307         index = asic3_irq_to_index(asic, data->irq);
308         bit = 1<<index;
309 
310         spin_lock_irqsave(&asic->lock, flags);
311         level = asic3_read_register(asic,
312                                     bank + ASIC3_GPIO_LEVEL_TRIGGER);
313         edge = asic3_read_register(asic,
314                                    bank + ASIC3_GPIO_EDGE_TRIGGER);
315         trigger = asic3_read_register(asic,
316                                       bank + ASIC3_GPIO_TRIGGER_TYPE);
317         asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] &= ~bit;
318 
319         if (type == IRQ_TYPE_EDGE_RISING) {
320                 trigger |= bit;
321                 edge |= bit;
322         } else if (type == IRQ_TYPE_EDGE_FALLING) {
323                 trigger |= bit;
324                 edge &= ~bit;
325         } else if (type == IRQ_TYPE_EDGE_BOTH) {
326                 trigger |= bit;
327                 if (asic3_gpio_get(&asic->gpio, data->irq - asic->irq_base))
328                         edge &= ~bit;
329                 else
330                         edge |= bit;
331                 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] |= bit;
332         } else if (type == IRQ_TYPE_LEVEL_LOW) {
333                 trigger &= ~bit;
334                 level &= ~bit;
335         } else if (type == IRQ_TYPE_LEVEL_HIGH) {
336                 trigger &= ~bit;
337                 level |= bit;
338         } else {
339                 /*
340                  * if type == IRQ_TYPE_NONE, we should mask interrupts, but
341                  * be careful to not unmask them if mask was also called.
342                  * Probably need internal state for mask.
343                  */
344                 dev_notice(asic->dev, "irq type not changed\n");
345         }
346         asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
347                              level);
348         asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
349                              edge);
350         asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
351                              trigger);
352         spin_unlock_irqrestore(&asic->lock, flags);
353         return 0;
354 }
355 
356 static int asic3_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
357 {
358         struct asic3 *asic = irq_data_get_irq_chip_data(data);
359         u32 bank, index;
360         u16 bit;
361 
362         bank = asic3_irq_to_bank(asic, data->irq);
363         index = asic3_irq_to_index(asic, data->irq);
364         bit = 1<<index;
365 
366         asic3_set_register(asic, bank + ASIC3_GPIO_SLEEP_MASK, bit, !on);
367 
368         return 0;
369 }
370 
371 static struct irq_chip asic3_gpio_irq_chip = {
372         .name           = "ASIC3-GPIO",
373         .irq_ack        = asic3_mask_gpio_irq,
374         .irq_mask       = asic3_mask_gpio_irq,
375         .irq_unmask     = asic3_unmask_gpio_irq,
376         .irq_set_type   = asic3_gpio_irq_type,
377         .irq_set_wake   = asic3_gpio_irq_set_wake,
378 };
379 
380 static struct irq_chip asic3_irq_chip = {
381         .name           = "ASIC3",
382         .irq_ack        = asic3_mask_irq,
383         .irq_mask       = asic3_mask_irq,
384         .irq_unmask     = asic3_unmask_irq,
385 };
386 
387 static int __init asic3_irq_probe(struct platform_device *pdev)
388 {
389         struct asic3 *asic = platform_get_drvdata(pdev);
390         unsigned long clksel = 0;
391         unsigned int irq, irq_base;
392         int ret;
393 
394         ret = platform_get_irq(pdev, 0);
395         if (ret < 0)
396                 return ret;
397         asic->irq_nr = ret;
398 
399         /* turn on clock to IRQ controller */
400         clksel |= CLOCK_SEL_CX;
401         asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
402                              clksel);
403 
404         irq_base = asic->irq_base;
405 
406         for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
407                 if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
408                         irq_set_chip(irq, &asic3_gpio_irq_chip);
409                 else
410                         irq_set_chip(irq, &asic3_irq_chip);
411 
412                 irq_set_chip_data(irq, asic);
413                 irq_set_handler(irq, handle_level_irq);
414                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
415         }
416 
417         asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
418                              ASIC3_INTMASK_GINTMASK);
419 
420         irq_set_chained_handler(asic->irq_nr, asic3_irq_demux);
421         irq_set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
422         irq_set_handler_data(asic->irq_nr, asic);
423 
424         return 0;
425 }
426 
427 static void asic3_irq_remove(struct platform_device *pdev)
428 {
429         struct asic3 *asic = platform_get_drvdata(pdev);
430         unsigned int irq, irq_base;
431 
432         irq_base = asic->irq_base;
433 
434         for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
435                 set_irq_flags(irq, 0);
436                 irq_set_chip_and_handler(irq, NULL, NULL);
437                 irq_set_chip_data(irq, NULL);
438         }
439         irq_set_chained_handler(asic->irq_nr, NULL);
440 }
441 
442 /* GPIOs */
443 static int asic3_gpio_direction(struct gpio_chip *chip,
444                                 unsigned offset, int out)
445 {
446         u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
447         unsigned int gpio_base;
448         unsigned long flags;
449         struct asic3 *asic;
450 
451         asic = container_of(chip, struct asic3, gpio);
452         gpio_base = ASIC3_GPIO_TO_BASE(offset);
453 
454         if (gpio_base > ASIC3_GPIO_D_BASE) {
455                 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
456                         gpio_base, offset);
457                 return -EINVAL;
458         }
459 
460         spin_lock_irqsave(&asic->lock, flags);
461 
462         out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
463 
464         /* Input is 0, Output is 1 */
465         if (out)
466                 out_reg |= mask;
467         else
468                 out_reg &= ~mask;
469 
470         asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
471 
472         spin_unlock_irqrestore(&asic->lock, flags);
473 
474         return 0;
475 
476 }
477 
478 static int asic3_gpio_direction_input(struct gpio_chip *chip,
479                                       unsigned offset)
480 {
481         return asic3_gpio_direction(chip, offset, 0);
482 }
483 
484 static int asic3_gpio_direction_output(struct gpio_chip *chip,
485                                        unsigned offset, int value)
486 {
487         return asic3_gpio_direction(chip, offset, 1);
488 }
489 
490 static int asic3_gpio_get(struct gpio_chip *chip,
491                           unsigned offset)
492 {
493         unsigned int gpio_base;
494         u32 mask = ASIC3_GPIO_TO_MASK(offset);
495         struct asic3 *asic;
496 
497         asic = container_of(chip, struct asic3, gpio);
498         gpio_base = ASIC3_GPIO_TO_BASE(offset);
499 
500         if (gpio_base > ASIC3_GPIO_D_BASE) {
501                 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
502                         gpio_base, offset);
503                 return -EINVAL;
504         }
505 
506         return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask;
507 }
508 
509 static void asic3_gpio_set(struct gpio_chip *chip,
510                            unsigned offset, int value)
511 {
512         u32 mask, out_reg;
513         unsigned int gpio_base;
514         unsigned long flags;
515         struct asic3 *asic;
516 
517         asic = container_of(chip, struct asic3, gpio);
518         gpio_base = ASIC3_GPIO_TO_BASE(offset);
519 
520         if (gpio_base > ASIC3_GPIO_D_BASE) {
521                 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
522                         gpio_base, offset);
523                 return;
524         }
525 
526         mask = ASIC3_GPIO_TO_MASK(offset);
527 
528         spin_lock_irqsave(&asic->lock, flags);
529 
530         out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
531 
532         if (value)
533                 out_reg |= mask;
534         else
535                 out_reg &= ~mask;
536 
537         asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
538 
539         spin_unlock_irqrestore(&asic->lock, flags);
540 
541         return;
542 }
543 
544 static int asic3_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
545 {
546         struct asic3 *asic = container_of(chip, struct asic3, gpio);
547 
548         return asic->irq_base + offset;
549 }
550 
551 static __init int asic3_gpio_probe(struct platform_device *pdev,
552                                    u16 *gpio_config, int num)
553 {
554         struct asic3 *asic = platform_get_drvdata(pdev);
555         u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
556         u16 out_reg[ASIC3_NUM_GPIO_BANKS];
557         u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
558         int i;
559 
560         memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
561         memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
562         memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
563 
564         /* Enable all GPIOs */
565         asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
566         asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
567         asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
568         asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
569 
570         for (i = 0; i < num; i++) {
571                 u8 alt, pin, dir, init, bank_num, bit_num;
572                 u16 config = gpio_config[i];
573 
574                 pin = ASIC3_CONFIG_GPIO_PIN(config);
575                 alt = ASIC3_CONFIG_GPIO_ALT(config);
576                 dir = ASIC3_CONFIG_GPIO_DIR(config);
577                 init = ASIC3_CONFIG_GPIO_INIT(config);
578 
579                 bank_num = ASIC3_GPIO_TO_BANK(pin);
580                 bit_num = ASIC3_GPIO_TO_BIT(pin);
581 
582                 alt_reg[bank_num] |= (alt << bit_num);
583                 out_reg[bank_num] |= (init << bit_num);
584                 dir_reg[bank_num] |= (dir << bit_num);
585         }
586 
587         for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
588                 asic3_write_register(asic,
589                                      ASIC3_BANK_TO_BASE(i) +
590                                      ASIC3_GPIO_DIRECTION,
591                                      dir_reg[i]);
592                 asic3_write_register(asic,
593                                      ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
594                                      out_reg[i]);
595                 asic3_write_register(asic,
596                                      ASIC3_BANK_TO_BASE(i) +
597                                      ASIC3_GPIO_ALT_FUNCTION,
598                                      alt_reg[i]);
599         }
600 
601         return gpiochip_add(&asic->gpio);
602 }
603 
604 static int asic3_gpio_remove(struct platform_device *pdev)
605 {
606         struct asic3 *asic = platform_get_drvdata(pdev);
607 
608         return gpiochip_remove(&asic->gpio);
609 }
610 
611 static void asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk)
612 {
613         unsigned long flags;
614         u32 cdex;
615 
616         spin_lock_irqsave(&asic->lock, flags);
617         if (clk->enabled++ == 0) {
618                 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
619                 cdex |= clk->cdex;
620                 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
621         }
622         spin_unlock_irqrestore(&asic->lock, flags);
623 }
624 
625 static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk)
626 {
627         unsigned long flags;
628         u32 cdex;
629 
630         WARN_ON(clk->enabled == 0);
631 
632         spin_lock_irqsave(&asic->lock, flags);
633         if (--clk->enabled == 0) {
634                 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
635                 cdex &= ~clk->cdex;
636                 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
637         }
638         spin_unlock_irqrestore(&asic->lock, flags);
639 }
640 
641 /* MFD cells (SPI, PWM, LED, DS1WM, MMC) */
642 static struct ds1wm_driver_data ds1wm_pdata = {
643         .active_high = 1,
644         .reset_recover_delay = 1,
645 };
646 
647 static struct resource ds1wm_resources[] = {
648         {
649                 .start = ASIC3_OWM_BASE,
650                 .end   = ASIC3_OWM_BASE + 0x13,
651                 .flags = IORESOURCE_MEM,
652         },
653         {
654                 .start = ASIC3_IRQ_OWM,
655                 .end   = ASIC3_IRQ_OWM,
656                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
657         },
658 };
659 
660 static int ds1wm_enable(struct platform_device *pdev)
661 {
662         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
663 
664         /* Turn on external clocks and the OWM clock */
665         asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
666         asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
667         asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
668         msleep(1);
669 
670         /* Reset and enable DS1WM */
671         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
672                            ASIC3_EXTCF_OWM_RESET, 1);
673         msleep(1);
674         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
675                            ASIC3_EXTCF_OWM_RESET, 0);
676         msleep(1);
677         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
678                            ASIC3_EXTCF_OWM_EN, 1);
679         msleep(1);
680 
681         return 0;
682 }
683 
684 static int ds1wm_disable(struct platform_device *pdev)
685 {
686         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
687 
688         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
689                            ASIC3_EXTCF_OWM_EN, 0);
690 
691         asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
692         asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
693         asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
694 
695         return 0;
696 }
697 
698 static const struct mfd_cell asic3_cell_ds1wm = {
699         .name          = "ds1wm",
700         .enable        = ds1wm_enable,
701         .disable       = ds1wm_disable,
702         .platform_data = &ds1wm_pdata,
703         .pdata_size    = sizeof(ds1wm_pdata),
704         .num_resources = ARRAY_SIZE(ds1wm_resources),
705         .resources     = ds1wm_resources,
706 };
707 
708 static void asic3_mmc_pwr(struct platform_device *pdev, int state)
709 {
710         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
711 
712         tmio_core_mmc_pwr(asic->tmio_cnf, 1 - asic->bus_shift, state);
713 }
714 
715 static void asic3_mmc_clk_div(struct platform_device *pdev, int state)
716 {
717         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
718 
719         tmio_core_mmc_clk_div(asic->tmio_cnf, 1 - asic->bus_shift, state);
720 }
721 
722 static struct tmio_mmc_data asic3_mmc_data = {
723         .hclk           = 24576000,
724         .set_pwr        = asic3_mmc_pwr,
725         .set_clk_div    = asic3_mmc_clk_div,
726 };
727 
728 static struct resource asic3_mmc_resources[] = {
729         {
730                 .start = ASIC3_SD_CTRL_BASE,
731                 .end   = ASIC3_SD_CTRL_BASE + 0x3ff,
732                 .flags = IORESOURCE_MEM,
733         },
734         {
735                 .start = 0,
736                 .end   = 0,
737                 .flags = IORESOURCE_IRQ,
738         },
739 };
740 
741 static int asic3_mmc_enable(struct platform_device *pdev)
742 {
743         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
744 
745         /* Not sure if it must be done bit by bit, but leaving as-is */
746         asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
747                            ASIC3_SDHWCTRL_LEVCD, 1);
748         asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
749                            ASIC3_SDHWCTRL_LEVWP, 1);
750         asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
751                            ASIC3_SDHWCTRL_SUSPEND, 0);
752         asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
753                            ASIC3_SDHWCTRL_PCLR, 0);
754 
755         asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
756         /* CLK32 used for card detection and for interruption detection
757          * when HCLK is stopped.
758          */
759         asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
760         msleep(1);
761 
762         /* HCLK 24.576 MHz, BCLK 12.288 MHz: */
763         asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
764                 CLOCK_SEL_CX | CLOCK_SEL_SD_HCLK_SEL);
765 
766         asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
767         asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
768         msleep(1);
769 
770         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
771                            ASIC3_EXTCF_SD_MEM_ENABLE, 1);
772 
773         /* Enable SD card slot 3.3V power supply */
774         asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
775                            ASIC3_SDHWCTRL_SDPWR, 1);
776 
777         /* ASIC3_SD_CTRL_BASE assumes 32-bit addressing, TMIO is 16-bit */
778         tmio_core_mmc_enable(asic->tmio_cnf, 1 - asic->bus_shift,
779                              ASIC3_SD_CTRL_BASE >> 1);
780 
781         return 0;
782 }
783 
784 static int asic3_mmc_disable(struct platform_device *pdev)
785 {
786         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
787 
788         /* Put in suspend mode */
789         asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
790                            ASIC3_SDHWCTRL_SUSPEND, 1);
791 
792         /* Disable clocks */
793         asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
794         asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
795         asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
796         asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
797         return 0;
798 }
799 
800 static const struct mfd_cell asic3_cell_mmc = {
801         .name          = "tmio-mmc",
802         .enable        = asic3_mmc_enable,
803         .disable       = asic3_mmc_disable,
804         .suspend       = asic3_mmc_disable,
805         .resume        = asic3_mmc_enable,
806         .platform_data = &asic3_mmc_data,
807         .pdata_size    = sizeof(asic3_mmc_data),
808         .num_resources = ARRAY_SIZE(asic3_mmc_resources),
809         .resources     = asic3_mmc_resources,
810 };
811 
812 static const int clock_ledn[ASIC3_NUM_LEDS] = {
813         [0] = ASIC3_CLOCK_LED0,
814         [1] = ASIC3_CLOCK_LED1,
815         [2] = ASIC3_CLOCK_LED2,
816 };
817 
818 static int asic3_leds_enable(struct platform_device *pdev)
819 {
820         const struct mfd_cell *cell = mfd_get_cell(pdev);
821         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
822 
823         asic3_clk_enable(asic, &asic->clocks[clock_ledn[cell->id]]);
824 
825         return 0;
826 }
827 
828 static int asic3_leds_disable(struct platform_device *pdev)
829 {
830         const struct mfd_cell *cell = mfd_get_cell(pdev);
831         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
832 
833         asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]);
834 
835         return 0;
836 }
837 
838 static int asic3_leds_suspend(struct platform_device *pdev)
839 {
840         const struct mfd_cell *cell = mfd_get_cell(pdev);
841         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
842 
843         while (asic3_gpio_get(&asic->gpio, ASIC3_GPIO(C, cell->id)) != 0)
844                 msleep(1);
845 
846         asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]);
847 
848         return 0;
849 }
850 
851 static struct mfd_cell asic3_cell_leds[ASIC3_NUM_LEDS] = {
852         [0] = {
853                 .name          = "leds-asic3",
854                 .id            = 0,
855                 .enable        = asic3_leds_enable,
856                 .disable       = asic3_leds_disable,
857                 .suspend       = asic3_leds_suspend,
858                 .resume        = asic3_leds_enable,
859         },
860         [1] = {
861                 .name          = "leds-asic3",
862                 .id            = 1,
863                 .enable        = asic3_leds_enable,
864                 .disable       = asic3_leds_disable,
865                 .suspend       = asic3_leds_suspend,
866                 .resume        = asic3_leds_enable,
867         },
868         [2] = {
869                 .name          = "leds-asic3",
870                 .id            = 2,
871                 .enable        = asic3_leds_enable,
872                 .disable       = asic3_leds_disable,
873                 .suspend       = asic3_leds_suspend,
874                 .resume        = asic3_leds_enable,
875         },
876 };
877 
878 static int __init asic3_mfd_probe(struct platform_device *pdev,
879                                   struct asic3_platform_data *pdata,
880                                   struct resource *mem)
881 {
882         struct asic3 *asic = platform_get_drvdata(pdev);
883         struct resource *mem_sdio;
884         int irq, ret;
885 
886         mem_sdio = platform_get_resource(pdev, IORESOURCE_MEM, 1);
887         if (!mem_sdio)
888                 dev_dbg(asic->dev, "no SDIO MEM resource\n");
889 
890         irq = platform_get_irq(pdev, 1);
891         if (irq < 0)
892                 dev_dbg(asic->dev, "no SDIO IRQ resource\n");
893 
894         /* DS1WM */
895         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
896                            ASIC3_EXTCF_OWM_SMB, 0);
897 
898         ds1wm_resources[0].start >>= asic->bus_shift;
899         ds1wm_resources[0].end   >>= asic->bus_shift;
900 
901         /* MMC */
902         if (mem_sdio) {
903                 asic->tmio_cnf = ioremap((ASIC3_SD_CONFIG_BASE >> asic->bus_shift) +
904                                  mem_sdio->start,
905                                  ASIC3_SD_CONFIG_SIZE >> asic->bus_shift);
906                 if (!asic->tmio_cnf) {
907                         ret = -ENOMEM;
908                         dev_dbg(asic->dev, "Couldn't ioremap SD_CONFIG\n");
909                         goto out;
910                 }
911         }
912         asic3_mmc_resources[0].start >>= asic->bus_shift;
913         asic3_mmc_resources[0].end   >>= asic->bus_shift;
914 
915         if (pdata->clock_rate) {
916                 ds1wm_pdata.clock_rate = pdata->clock_rate;
917                 ret = mfd_add_devices(&pdev->dev, pdev->id,
918                         &asic3_cell_ds1wm, 1, mem, asic->irq_base, NULL);
919                 if (ret < 0)
920                         goto out;
921         }
922 
923         if (mem_sdio && (irq >= 0)) {
924                 ret = mfd_add_devices(&pdev->dev, pdev->id,
925                         &asic3_cell_mmc, 1, mem_sdio, irq, NULL);
926                 if (ret < 0)
927                         goto out;
928         }
929 
930         ret = 0;
931         if (pdata->leds) {
932                 int i;
933 
934                 for (i = 0; i < ASIC3_NUM_LEDS; ++i) {
935                         asic3_cell_leds[i].platform_data = &pdata->leds[i];
936                         asic3_cell_leds[i].pdata_size = sizeof(pdata->leds[i]);
937                 }
938                 ret = mfd_add_devices(&pdev->dev, 0,
939                         asic3_cell_leds, ASIC3_NUM_LEDS, NULL, 0, NULL);
940         }
941 
942  out:
943         return ret;
944 }
945 
946 static void asic3_mfd_remove(struct platform_device *pdev)
947 {
948         struct asic3 *asic = platform_get_drvdata(pdev);
949 
950         mfd_remove_devices(&pdev->dev);
951         iounmap(asic->tmio_cnf);
952 }
953 
954 /* Core */
955 static int __init asic3_probe(struct platform_device *pdev)
956 {
957         struct asic3_platform_data *pdata = dev_get_platdata(&pdev->dev);
958         struct asic3 *asic;
959         struct resource *mem;
960         unsigned long clksel;
961         int ret = 0;
962 
963         asic = devm_kzalloc(&pdev->dev,
964                             sizeof(struct asic3), GFP_KERNEL);
965         if (asic == NULL) {
966                 printk(KERN_ERR "kzalloc failed\n");
967                 return -ENOMEM;
968         }
969 
970         spin_lock_init(&asic->lock);
971         platform_set_drvdata(pdev, asic);
972         asic->dev = &pdev->dev;
973 
974         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
975         if (!mem) {
976                 dev_err(asic->dev, "no MEM resource\n");
977                 return -ENOMEM;
978         }
979 
980         asic->mapping = ioremap(mem->start, resource_size(mem));
981         if (!asic->mapping) {
982                 dev_err(asic->dev, "Couldn't ioremap\n");
983                 return -ENOMEM;
984         }
985 
986         asic->irq_base = pdata->irq_base;
987 
988         /* calculate bus shift from mem resource */
989         asic->bus_shift = 2 - (resource_size(mem) >> 12);
990 
991         clksel = 0;
992         asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
993 
994         ret = asic3_irq_probe(pdev);
995         if (ret < 0) {
996                 dev_err(asic->dev, "Couldn't probe IRQs\n");
997                 goto out_unmap;
998         }
999 
1000         asic->gpio.label = "asic3";
1001         asic->gpio.base = pdata->gpio_base;
1002         asic->gpio.ngpio = ASIC3_NUM_GPIOS;
1003         asic->gpio.get = asic3_gpio_get;
1004         asic->gpio.set = asic3_gpio_set;
1005         asic->gpio.direction_input = asic3_gpio_direction_input;
1006         asic->gpio.direction_output = asic3_gpio_direction_output;
1007         asic->gpio.to_irq = asic3_gpio_to_irq;
1008 
1009         ret = asic3_gpio_probe(pdev,
1010                                pdata->gpio_config,
1011                                pdata->gpio_config_num);
1012         if (ret < 0) {
1013                 dev_err(asic->dev, "GPIO probe failed\n");
1014                 goto out_irq;
1015         }
1016 
1017         /* Making a per-device copy is only needed for the
1018          * theoretical case of multiple ASIC3s on one board:
1019          */
1020         memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init));
1021 
1022         asic3_mfd_probe(pdev, pdata, mem);
1023 
1024         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
1025                 (ASIC3_EXTCF_CF0_BUF_EN|ASIC3_EXTCF_CF0_PWAIT_EN), 1);
1026 
1027         dev_info(asic->dev, "ASIC3 Core driver\n");
1028 
1029         return 0;
1030 
1031  out_irq:
1032         asic3_irq_remove(pdev);
1033 
1034  out_unmap:
1035         iounmap(asic->mapping);
1036 
1037         return ret;
1038 }
1039 
1040 static int asic3_remove(struct platform_device *pdev)
1041 {
1042         int ret;
1043         struct asic3 *asic = platform_get_drvdata(pdev);
1044 
1045         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
1046                 (ASIC3_EXTCF_CF0_BUF_EN|ASIC3_EXTCF_CF0_PWAIT_EN), 0);
1047 
1048         asic3_mfd_remove(pdev);
1049 
1050         ret = asic3_gpio_remove(pdev);
1051         if (ret < 0)
1052                 return ret;
1053         asic3_irq_remove(pdev);
1054 
1055         asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
1056 
1057         iounmap(asic->mapping);
1058 
1059         return 0;
1060 }
1061 
1062 static void asic3_shutdown(struct platform_device *pdev)
1063 {
1064 }
1065 
1066 static struct platform_driver asic3_device_driver = {
1067         .driver         = {
1068                 .name   = "asic3",
1069         },
1070         .remove         = asic3_remove,
1071         .shutdown       = asic3_shutdown,
1072 };
1073 
1074 static int __init asic3_init(void)
1075 {
1076         int retval = 0;
1077         retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
1078         return retval;
1079 }
1080 
1081 subsys_initcall(asic3_init);
1082 

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