Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/media/rc/fintek-cir.c

  1 /*
  2  * Driver for Feature Integration Technology Inc. (aka Fintek) LPC CIR
  3  *
  4  * Copyright (C) 2011 Jarod Wilson <jarod@redhat.com>
  5  *
  6  * Special thanks to Fintek for providing hardware and spec sheets.
  7  * This driver is based upon the nuvoton, ite and ene drivers for
  8  * similar hardware.
  9  *
 10  * This program is free software; you can redistribute it and/or
 11  * modify it under the terms of the GNU General Public License as
 12  * published by the Free Software Foundation; either version 2 of the
 13  * License, or (at your option) any later version.
 14  *
 15  * This program is distributed in the hope that it will be useful, but
 16  * WITHOUT ANY WARRANTY; without even the implied warranty of
 17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 18  * General Public License for more details.
 19  *
 20  * You should have received a copy of the GNU General Public License
 21  * along with this program; if not, write to the Free Software
 22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
 23  * USA
 24  */
 25 
 26 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 27 
 28 #include <linux/kernel.h>
 29 #include <linux/module.h>
 30 #include <linux/pnp.h>
 31 #include <linux/io.h>
 32 #include <linux/interrupt.h>
 33 #include <linux/sched.h>
 34 #include <linux/slab.h>
 35 #include <media/rc-core.h>
 36 #include <linux/pci_ids.h>
 37 
 38 #include "fintek-cir.h"
 39 
 40 /* write val to config reg */
 41 static inline void fintek_cr_write(struct fintek_dev *fintek, u8 val, u8 reg)
 42 {
 43         fit_dbg("%s: reg 0x%02x, val 0x%02x  (ip/dp: %02x/%02x)",
 44                 __func__, reg, val, fintek->cr_ip, fintek->cr_dp);
 45         outb(reg, fintek->cr_ip);
 46         outb(val, fintek->cr_dp);
 47 }
 48 
 49 /* read val from config reg */
 50 static inline u8 fintek_cr_read(struct fintek_dev *fintek, u8 reg)
 51 {
 52         u8 val;
 53 
 54         outb(reg, fintek->cr_ip);
 55         val = inb(fintek->cr_dp);
 56 
 57         fit_dbg("%s: reg 0x%02x, val 0x%02x  (ip/dp: %02x/%02x)",
 58                 __func__, reg, val, fintek->cr_ip, fintek->cr_dp);
 59         return val;
 60 }
 61 
 62 /* update config register bit without changing other bits */
 63 static inline void fintek_set_reg_bit(struct fintek_dev *fintek, u8 val, u8 reg)
 64 {
 65         u8 tmp = fintek_cr_read(fintek, reg) | val;
 66         fintek_cr_write(fintek, tmp, reg);
 67 }
 68 
 69 /* clear config register bit without changing other bits */
 70 static inline void fintek_clear_reg_bit(struct fintek_dev *fintek, u8 val, u8 reg)
 71 {
 72         u8 tmp = fintek_cr_read(fintek, reg) & ~val;
 73         fintek_cr_write(fintek, tmp, reg);
 74 }
 75 
 76 /* enter config mode */
 77 static inline void fintek_config_mode_enable(struct fintek_dev *fintek)
 78 {
 79         /* Enabling Config Mode explicitly requires writing 2x */
 80         outb(CONFIG_REG_ENABLE, fintek->cr_ip);
 81         outb(CONFIG_REG_ENABLE, fintek->cr_ip);
 82 }
 83 
 84 /* exit config mode */
 85 static inline void fintek_config_mode_disable(struct fintek_dev *fintek)
 86 {
 87         outb(CONFIG_REG_DISABLE, fintek->cr_ip);
 88 }
 89 
 90 /*
 91  * When you want to address a specific logical device, write its logical
 92  * device number to GCR_LOGICAL_DEV_NO
 93  */
 94 static inline void fintek_select_logical_dev(struct fintek_dev *fintek, u8 ldev)
 95 {
 96         fintek_cr_write(fintek, ldev, GCR_LOGICAL_DEV_NO);
 97 }
 98 
 99 /* write val to cir config register */
100 static inline void fintek_cir_reg_write(struct fintek_dev *fintek, u8 val, u8 offset)
101 {
102         outb(val, fintek->cir_addr + offset);
103 }
104 
105 /* read val from cir config register */
106 static u8 fintek_cir_reg_read(struct fintek_dev *fintek, u8 offset)
107 {
108         u8 val;
109 
110         val = inb(fintek->cir_addr + offset);
111 
112         return val;
113 }
114 
115 /* dump current cir register contents */
116 static void cir_dump_regs(struct fintek_dev *fintek)
117 {
118         fintek_config_mode_enable(fintek);
119         fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
120 
121         pr_info("%s: Dump CIR logical device registers:\n", FINTEK_DRIVER_NAME);
122         pr_info(" * CR CIR BASE ADDR: 0x%x\n",
123                 (fintek_cr_read(fintek, CIR_CR_BASE_ADDR_HI) << 8) |
124                 fintek_cr_read(fintek, CIR_CR_BASE_ADDR_LO));
125         pr_info(" * CR CIR IRQ NUM:   0x%x\n",
126                 fintek_cr_read(fintek, CIR_CR_IRQ_SEL));
127 
128         fintek_config_mode_disable(fintek);
129 
130         pr_info("%s: Dump CIR registers:\n", FINTEK_DRIVER_NAME);
131         pr_info(" * STATUS:     0x%x\n",
132                 fintek_cir_reg_read(fintek, CIR_STATUS));
133         pr_info(" * CONTROL:    0x%x\n",
134                 fintek_cir_reg_read(fintek, CIR_CONTROL));
135         pr_info(" * RX_DATA:    0x%x\n",
136                 fintek_cir_reg_read(fintek, CIR_RX_DATA));
137         pr_info(" * TX_CONTROL: 0x%x\n",
138                 fintek_cir_reg_read(fintek, CIR_TX_CONTROL));
139         pr_info(" * TX_DATA:    0x%x\n",
140                 fintek_cir_reg_read(fintek, CIR_TX_DATA));
141 }
142 
143 /* detect hardware features */
144 static int fintek_hw_detect(struct fintek_dev *fintek)
145 {
146         unsigned long flags;
147         u8 chip_major, chip_minor;
148         u8 vendor_major, vendor_minor;
149         u8 portsel, ir_class;
150         u16 vendor, chip;
151         int ret = 0;
152 
153         fintek_config_mode_enable(fintek);
154 
155         /* Check if we're using config port 0x4e or 0x2e */
156         portsel = fintek_cr_read(fintek, GCR_CONFIG_PORT_SEL);
157         if (portsel == 0xff) {
158                 fit_pr(KERN_INFO, "first portsel read was bunk, trying alt");
159                 fintek_config_mode_disable(fintek);
160                 fintek->cr_ip = CR_INDEX_PORT2;
161                 fintek->cr_dp = CR_DATA_PORT2;
162                 fintek_config_mode_enable(fintek);
163                 portsel = fintek_cr_read(fintek, GCR_CONFIG_PORT_SEL);
164         }
165         fit_dbg("portsel reg: 0x%02x", portsel);
166 
167         ir_class = fintek_cir_reg_read(fintek, CIR_CR_CLASS);
168         fit_dbg("ir_class reg: 0x%02x", ir_class);
169 
170         switch (ir_class) {
171         case CLASS_RX_2TX:
172         case CLASS_RX_1TX:
173                 fintek->hw_tx_capable = true;
174                 break;
175         case CLASS_RX_ONLY:
176         default:
177                 fintek->hw_tx_capable = false;
178                 break;
179         }
180 
181         chip_major = fintek_cr_read(fintek, GCR_CHIP_ID_HI);
182         chip_minor = fintek_cr_read(fintek, GCR_CHIP_ID_LO);
183         chip  = chip_major << 8 | chip_minor;
184 
185         vendor_major = fintek_cr_read(fintek, GCR_VENDOR_ID_HI);
186         vendor_minor = fintek_cr_read(fintek, GCR_VENDOR_ID_LO);
187         vendor = vendor_major << 8 | vendor_minor;
188 
189         if (vendor != VENDOR_ID_FINTEK)
190                 fit_pr(KERN_WARNING, "Unknown vendor ID: 0x%04x", vendor);
191         else
192                 fit_dbg("Read Fintek vendor ID from chip");
193 
194         fintek_config_mode_disable(fintek);
195 
196         spin_lock_irqsave(&fintek->fintek_lock, flags);
197         fintek->chip_major  = chip_major;
198         fintek->chip_minor  = chip_minor;
199         fintek->chip_vendor = vendor;
200 
201         /*
202          * Newer reviews of this chipset uses port 8 instead of 5
203          */
204         if ((chip != 0x0408) && (chip != 0x0804))
205                 fintek->logical_dev_cir = LOGICAL_DEV_CIR_REV2;
206         else
207                 fintek->logical_dev_cir = LOGICAL_DEV_CIR_REV1;
208 
209         spin_unlock_irqrestore(&fintek->fintek_lock, flags);
210 
211         return ret;
212 }
213 
214 static void fintek_cir_ldev_init(struct fintek_dev *fintek)
215 {
216         /* Select CIR logical device and enable */
217         fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
218         fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN);
219 
220         /* Write allocated CIR address and IRQ information to hardware */
221         fintek_cr_write(fintek, fintek->cir_addr >> 8, CIR_CR_BASE_ADDR_HI);
222         fintek_cr_write(fintek, fintek->cir_addr & 0xff, CIR_CR_BASE_ADDR_LO);
223 
224         fintek_cr_write(fintek, fintek->cir_irq, CIR_CR_IRQ_SEL);
225 
226         fit_dbg("CIR initialized, base io address: 0x%lx, irq: %d (len: %d)",
227                 fintek->cir_addr, fintek->cir_irq, fintek->cir_port_len);
228 }
229 
230 /* enable CIR interrupts */
231 static void fintek_enable_cir_irq(struct fintek_dev *fintek)
232 {
233         fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_EN, CIR_STATUS);
234 }
235 
236 static void fintek_cir_regs_init(struct fintek_dev *fintek)
237 {
238         /* clear any and all stray interrupts */
239         fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
240 
241         /* and finally, enable interrupts */
242         fintek_enable_cir_irq(fintek);
243 }
244 
245 static void fintek_enable_wake(struct fintek_dev *fintek)
246 {
247         fintek_config_mode_enable(fintek);
248         fintek_select_logical_dev(fintek, LOGICAL_DEV_ACPI);
249 
250         /* Allow CIR PME's to wake system */
251         fintek_set_reg_bit(fintek, ACPI_WAKE_EN_CIR_BIT, LDEV_ACPI_WAKE_EN_REG);
252         /* Enable CIR PME's */
253         fintek_set_reg_bit(fintek, ACPI_PME_CIR_BIT, LDEV_ACPI_PME_EN_REG);
254         /* Clear CIR PME status register */
255         fintek_set_reg_bit(fintek, ACPI_PME_CIR_BIT, LDEV_ACPI_PME_CLR_REG);
256         /* Save state */
257         fintek_set_reg_bit(fintek, ACPI_STATE_CIR_BIT, LDEV_ACPI_STATE_REG);
258 
259         fintek_config_mode_disable(fintek);
260 }
261 
262 static int fintek_cmdsize(u8 cmd, u8 subcmd)
263 {
264         int datasize = 0;
265 
266         switch (cmd) {
267         case BUF_COMMAND_NULL:
268                 if (subcmd == BUF_HW_CMD_HEADER)
269                         datasize = 1;
270                 break;
271         case BUF_HW_CMD_HEADER:
272                 if (subcmd == BUF_CMD_G_REVISION)
273                         datasize = 2;
274                 break;
275         case BUF_COMMAND_HEADER:
276                 switch (subcmd) {
277                 case BUF_CMD_S_CARRIER:
278                 case BUF_CMD_S_TIMEOUT:
279                 case BUF_RSP_PULSE_COUNT:
280                         datasize = 2;
281                         break;
282                 case BUF_CMD_SIG_END:
283                 case BUF_CMD_S_TXMASK:
284                 case BUF_CMD_S_RXSENSOR:
285                         datasize = 1;
286                         break;
287                 }
288         }
289 
290         return datasize;
291 }
292 
293 /* process ir data stored in driver buffer */
294 static void fintek_process_rx_ir_data(struct fintek_dev *fintek)
295 {
296         DEFINE_IR_RAW_EVENT(rawir);
297         u8 sample;
298         bool event = false;
299         int i;
300 
301         for (i = 0; i < fintek->pkts; i++) {
302                 sample = fintek->buf[i];
303                 switch (fintek->parser_state) {
304                 case CMD_HEADER:
305                         fintek->cmd = sample;
306                         if ((fintek->cmd == BUF_COMMAND_HEADER) ||
307                             ((fintek->cmd & BUF_COMMAND_MASK) !=
308                              BUF_PULSE_BIT)) {
309                                 fintek->parser_state = SUBCMD;
310                                 continue;
311                         }
312                         fintek->rem = (fintek->cmd & BUF_LEN_MASK);
313                         fit_dbg("%s: rem: 0x%02x", __func__, fintek->rem);
314                         if (fintek->rem)
315                                 fintek->parser_state = PARSE_IRDATA;
316                         else
317                                 ir_raw_event_reset(fintek->rdev);
318                         break;
319                 case SUBCMD:
320                         fintek->rem = fintek_cmdsize(fintek->cmd, sample);
321                         fintek->parser_state = CMD_DATA;
322                         break;
323                 case CMD_DATA:
324                         fintek->rem--;
325                         break;
326                 case PARSE_IRDATA:
327                         fintek->rem--;
328                         init_ir_raw_event(&rawir);
329                         rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
330                         rawir.duration = US_TO_NS((sample & BUF_SAMPLE_MASK)
331                                           * CIR_SAMPLE_PERIOD);
332 
333                         fit_dbg("Storing %s with duration %d",
334                                 rawir.pulse ? "pulse" : "space",
335                                 rawir.duration);
336                         if (ir_raw_event_store_with_filter(fintek->rdev,
337                                                                         &rawir))
338                                 event = true;
339                         break;
340                 }
341 
342                 if ((fintek->parser_state != CMD_HEADER) && !fintek->rem)
343                         fintek->parser_state = CMD_HEADER;
344         }
345 
346         fintek->pkts = 0;
347 
348         if (event) {
349                 fit_dbg("Calling ir_raw_event_handle");
350                 ir_raw_event_handle(fintek->rdev);
351         }
352 }
353 
354 /* copy data from hardware rx register into driver buffer */
355 static void fintek_get_rx_ir_data(struct fintek_dev *fintek, u8 rx_irqs)
356 {
357         unsigned long flags;
358         u8 sample, status;
359 
360         spin_lock_irqsave(&fintek->fintek_lock, flags);
361 
362         /*
363          * We must read data from CIR_RX_DATA until the hardware IR buffer
364          * is empty and clears the RX_TIMEOUT and/or RX_RECEIVE flags in
365          * the CIR_STATUS register
366          */
367         do {
368                 sample = fintek_cir_reg_read(fintek, CIR_RX_DATA);
369                 fit_dbg("%s: sample: 0x%02x", __func__, sample);
370 
371                 fintek->buf[fintek->pkts] = sample;
372                 fintek->pkts++;
373 
374                 status = fintek_cir_reg_read(fintek, CIR_STATUS);
375                 if (!(status & CIR_STATUS_IRQ_EN))
376                         break;
377         } while (status & rx_irqs);
378 
379         fintek_process_rx_ir_data(fintek);
380 
381         spin_unlock_irqrestore(&fintek->fintek_lock, flags);
382 }
383 
384 static void fintek_cir_log_irqs(u8 status)
385 {
386         fit_pr(KERN_INFO, "IRQ 0x%02x:%s%s%s%s%s", status,
387                 status & CIR_STATUS_IRQ_EN      ? " IRQEN"      : "",
388                 status & CIR_STATUS_TX_FINISH   ? " TXF"        : "",
389                 status & CIR_STATUS_TX_UNDERRUN ? " TXU"        : "",
390                 status & CIR_STATUS_RX_TIMEOUT  ? " RXTO"       : "",
391                 status & CIR_STATUS_RX_RECEIVE  ? " RXOK"       : "");
392 }
393 
394 /* interrupt service routine for incoming and outgoing CIR data */
395 static irqreturn_t fintek_cir_isr(int irq, void *data)
396 {
397         struct fintek_dev *fintek = data;
398         u8 status, rx_irqs;
399 
400         fit_dbg_verbose("%s firing", __func__);
401 
402         fintek_config_mode_enable(fintek);
403         fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
404         fintek_config_mode_disable(fintek);
405 
406         /*
407          * Get IR Status register contents. Write 1 to ack/clear
408          *
409          * bit: reg name    - description
410          *   3: TX_FINISH   - TX is finished
411          *   2: TX_UNDERRUN - TX underrun
412          *   1: RX_TIMEOUT  - RX data timeout
413          *   0: RX_RECEIVE  - RX data received
414          */
415         status = fintek_cir_reg_read(fintek, CIR_STATUS);
416         if (!(status & CIR_STATUS_IRQ_MASK) || status == 0xff) {
417                 fit_dbg_verbose("%s exiting, IRSTS 0x%02x", __func__, status);
418                 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
419                 return IRQ_RETVAL(IRQ_NONE);
420         }
421 
422         if (debug)
423                 fintek_cir_log_irqs(status);
424 
425         rx_irqs = status & (CIR_STATUS_RX_RECEIVE | CIR_STATUS_RX_TIMEOUT);
426         if (rx_irqs)
427                 fintek_get_rx_ir_data(fintek, rx_irqs);
428 
429         /* ack/clear all irq flags we've got */
430         fintek_cir_reg_write(fintek, status, CIR_STATUS);
431 
432         fit_dbg_verbose("%s done", __func__);
433         return IRQ_RETVAL(IRQ_HANDLED);
434 }
435 
436 static void fintek_enable_cir(struct fintek_dev *fintek)
437 {
438         /* set IRQ enabled */
439         fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_EN, CIR_STATUS);
440 
441         fintek_config_mode_enable(fintek);
442 
443         /* enable the CIR logical device */
444         fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
445         fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN);
446 
447         fintek_config_mode_disable(fintek);
448 
449         /* clear all pending interrupts */
450         fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
451 
452         /* enable interrupts */
453         fintek_enable_cir_irq(fintek);
454 }
455 
456 static void fintek_disable_cir(struct fintek_dev *fintek)
457 {
458         fintek_config_mode_enable(fintek);
459 
460         /* disable the CIR logical device */
461         fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
462         fintek_cr_write(fintek, LOGICAL_DEV_DISABLE, CIR_CR_DEV_EN);
463 
464         fintek_config_mode_disable(fintek);
465 }
466 
467 static int fintek_open(struct rc_dev *dev)
468 {
469         struct fintek_dev *fintek = dev->priv;
470         unsigned long flags;
471 
472         spin_lock_irqsave(&fintek->fintek_lock, flags);
473         fintek_enable_cir(fintek);
474         spin_unlock_irqrestore(&fintek->fintek_lock, flags);
475 
476         return 0;
477 }
478 
479 static void fintek_close(struct rc_dev *dev)
480 {
481         struct fintek_dev *fintek = dev->priv;
482         unsigned long flags;
483 
484         spin_lock_irqsave(&fintek->fintek_lock, flags);
485         fintek_disable_cir(fintek);
486         spin_unlock_irqrestore(&fintek->fintek_lock, flags);
487 }
488 
489 /* Allocate memory, probe hardware, and initialize everything */
490 static int fintek_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
491 {
492         struct fintek_dev *fintek;
493         struct rc_dev *rdev;
494         int ret = -ENOMEM;
495 
496         fintek = kzalloc(sizeof(struct fintek_dev), GFP_KERNEL);
497         if (!fintek)
498                 return ret;
499 
500         /* input device for IR remote (and tx) */
501         rdev = rc_allocate_device();
502         if (!rdev)
503                 goto exit_free_dev_rdev;
504 
505         ret = -ENODEV;
506         /* validate pnp resources */
507         if (!pnp_port_valid(pdev, 0)) {
508                 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
509                 goto exit_free_dev_rdev;
510         }
511 
512         if (!pnp_irq_valid(pdev, 0)) {
513                 dev_err(&pdev->dev, "IR PNP IRQ not valid!\n");
514                 goto exit_free_dev_rdev;
515         }
516 
517         fintek->cir_addr = pnp_port_start(pdev, 0);
518         fintek->cir_irq  = pnp_irq(pdev, 0);
519         fintek->cir_port_len = pnp_port_len(pdev, 0);
520 
521         fintek->cr_ip = CR_INDEX_PORT;
522         fintek->cr_dp = CR_DATA_PORT;
523 
524         spin_lock_init(&fintek->fintek_lock);
525 
526         pnp_set_drvdata(pdev, fintek);
527         fintek->pdev = pdev;
528 
529         ret = fintek_hw_detect(fintek);
530         if (ret)
531                 goto exit_free_dev_rdev;
532 
533         /* Initialize CIR & CIR Wake Logical Devices */
534         fintek_config_mode_enable(fintek);
535         fintek_cir_ldev_init(fintek);
536         fintek_config_mode_disable(fintek);
537 
538         /* Initialize CIR & CIR Wake Config Registers */
539         fintek_cir_regs_init(fintek);
540 
541         /* Set up the rc device */
542         rdev->priv = fintek;
543         rdev->driver_type = RC_DRIVER_IR_RAW;
544         rdev->allowed_protocols = RC_BIT_ALL;
545         rdev->open = fintek_open;
546         rdev->close = fintek_close;
547         rdev->input_name = FINTEK_DESCRIPTION;
548         rdev->input_phys = "fintek/cir0";
549         rdev->input_id.bustype = BUS_HOST;
550         rdev->input_id.vendor = VENDOR_ID_FINTEK;
551         rdev->input_id.product = fintek->chip_major;
552         rdev->input_id.version = fintek->chip_minor;
553         rdev->dev.parent = &pdev->dev;
554         rdev->driver_name = FINTEK_DRIVER_NAME;
555         rdev->map_name = RC_MAP_RC6_MCE;
556         rdev->timeout = US_TO_NS(1000);
557         /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
558         rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD);
559 
560         fintek->rdev = rdev;
561 
562         ret = -EBUSY;
563         /* now claim resources */
564         if (!request_region(fintek->cir_addr,
565                             fintek->cir_port_len, FINTEK_DRIVER_NAME))
566                 goto exit_free_dev_rdev;
567 
568         if (request_irq(fintek->cir_irq, fintek_cir_isr, IRQF_SHARED,
569                         FINTEK_DRIVER_NAME, (void *)fintek))
570                 goto exit_free_cir_addr;
571 
572         ret = rc_register_device(rdev);
573         if (ret)
574                 goto exit_free_irq;
575 
576         device_init_wakeup(&pdev->dev, true);
577 
578         fit_pr(KERN_NOTICE, "driver has been successfully loaded\n");
579         if (debug)
580                 cir_dump_regs(fintek);
581 
582         return 0;
583 
584 exit_free_irq:
585         free_irq(fintek->cir_irq, fintek);
586 exit_free_cir_addr:
587         release_region(fintek->cir_addr, fintek->cir_port_len);
588 exit_free_dev_rdev:
589         rc_free_device(rdev);
590         kfree(fintek);
591 
592         return ret;
593 }
594 
595 static void fintek_remove(struct pnp_dev *pdev)
596 {
597         struct fintek_dev *fintek = pnp_get_drvdata(pdev);
598         unsigned long flags;
599 
600         spin_lock_irqsave(&fintek->fintek_lock, flags);
601         /* disable CIR */
602         fintek_disable_cir(fintek);
603         fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
604         /* enable CIR Wake (for IR power-on) */
605         fintek_enable_wake(fintek);
606         spin_unlock_irqrestore(&fintek->fintek_lock, flags);
607 
608         /* free resources */
609         free_irq(fintek->cir_irq, fintek);
610         release_region(fintek->cir_addr, fintek->cir_port_len);
611 
612         rc_unregister_device(fintek->rdev);
613 
614         kfree(fintek);
615 }
616 
617 static int fintek_suspend(struct pnp_dev *pdev, pm_message_t state)
618 {
619         struct fintek_dev *fintek = pnp_get_drvdata(pdev);
620         unsigned long flags;
621 
622         fit_dbg("%s called", __func__);
623 
624         spin_lock_irqsave(&fintek->fintek_lock, flags);
625 
626         /* disable all CIR interrupts */
627         fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
628 
629         spin_unlock_irqrestore(&fintek->fintek_lock, flags);
630 
631         fintek_config_mode_enable(fintek);
632 
633         /* disable cir logical dev */
634         fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
635         fintek_cr_write(fintek, LOGICAL_DEV_DISABLE, CIR_CR_DEV_EN);
636 
637         fintek_config_mode_disable(fintek);
638 
639         /* make sure wake is enabled */
640         fintek_enable_wake(fintek);
641 
642         return 0;
643 }
644 
645 static int fintek_resume(struct pnp_dev *pdev)
646 {
647         int ret = 0;
648         struct fintek_dev *fintek = pnp_get_drvdata(pdev);
649 
650         fit_dbg("%s called", __func__);
651 
652         /* open interrupt */
653         fintek_enable_cir_irq(fintek);
654 
655         /* Enable CIR logical device */
656         fintek_config_mode_enable(fintek);
657         fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
658         fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN);
659 
660         fintek_config_mode_disable(fintek);
661 
662         fintek_cir_regs_init(fintek);
663 
664         return ret;
665 }
666 
667 static void fintek_shutdown(struct pnp_dev *pdev)
668 {
669         struct fintek_dev *fintek = pnp_get_drvdata(pdev);
670         fintek_enable_wake(fintek);
671 }
672 
673 static const struct pnp_device_id fintek_ids[] = {
674         { "FIT0002", 0 },   /* CIR */
675         { "", 0 },
676 };
677 
678 static struct pnp_driver fintek_driver = {
679         .name           = FINTEK_DRIVER_NAME,
680         .id_table       = fintek_ids,
681         .flags          = PNP_DRIVER_RES_DO_NOT_CHANGE,
682         .probe          = fintek_probe,
683         .remove         = fintek_remove,
684         .suspend        = fintek_suspend,
685         .resume         = fintek_resume,
686         .shutdown       = fintek_shutdown,
687 };
688 
689 static int __init fintek_init(void)
690 {
691         return pnp_register_driver(&fintek_driver);
692 }
693 
694 static void __exit fintek_exit(void)
695 {
696         pnp_unregister_driver(&fintek_driver);
697 }
698 
699 module_param(debug, int, S_IRUGO | S_IWUSR);
700 MODULE_PARM_DESC(debug, "Enable debugging output");
701 
702 MODULE_DEVICE_TABLE(pnp, fintek_ids);
703 MODULE_DESCRIPTION(FINTEK_DESCRIPTION " driver");
704 
705 MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
706 MODULE_LICENSE("GPL");
707 
708 module_init(fintek_init);
709 module_exit(fintek_exit);
710 

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