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Linux/drivers/media/platform/ti-vpe/vpe.c

  1 /*
  2  * TI VPE mem2mem driver, based on the virtual v4l2-mem2mem example driver
  3  *
  4  * Copyright (c) 2013 Texas Instruments Inc.
  5  * David Griego, <dagriego@biglakesoftware.com>
  6  * Dale Farnsworth, <dale@farnsworth.org>
  7  * Archit Taneja, <archit@ti.com>
  8  *
  9  * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
 10  * Pawel Osciak, <pawel@osciak.com>
 11  * Marek Szyprowski, <m.szyprowski@samsung.com>
 12  *
 13  * Based on the virtual v4l2-mem2mem example device
 14  *
 15  * This program is free software; you can redistribute it and/or modify it
 16  * under the terms of the GNU General Public License version 2 as published by
 17  * the Free Software Foundation
 18  */
 19 
 20 #include <linux/delay.h>
 21 #include <linux/dma-mapping.h>
 22 #include <linux/err.h>
 23 #include <linux/fs.h>
 24 #include <linux/interrupt.h>
 25 #include <linux/io.h>
 26 #include <linux/ioctl.h>
 27 #include <linux/module.h>
 28 #include <linux/of.h>
 29 #include <linux/platform_device.h>
 30 #include <linux/pm_runtime.h>
 31 #include <linux/sched.h>
 32 #include <linux/slab.h>
 33 #include <linux/videodev2.h>
 34 #include <linux/log2.h>
 35 #include <linux/sizes.h>
 36 
 37 #include <media/v4l2-common.h>
 38 #include <media/v4l2-ctrls.h>
 39 #include <media/v4l2-device.h>
 40 #include <media/v4l2-event.h>
 41 #include <media/v4l2-ioctl.h>
 42 #include <media/v4l2-mem2mem.h>
 43 #include <media/videobuf2-v4l2.h>
 44 #include <media/videobuf2-dma-contig.h>
 45 
 46 #include "vpdma.h"
 47 #include "vpe_regs.h"
 48 #include "sc.h"
 49 #include "csc.h"
 50 
 51 #define VPE_MODULE_NAME "vpe"
 52 
 53 /* minimum and maximum frame sizes */
 54 #define MIN_W           32
 55 #define MIN_H           32
 56 #define MAX_W           1920
 57 #define MAX_H           1080
 58 
 59 /* required alignments */
 60 #define S_ALIGN         0       /* multiple of 1 */
 61 #define H_ALIGN         1       /* multiple of 2 */
 62 
 63 /* flags that indicate a format can be used for capture/output */
 64 #define VPE_FMT_TYPE_CAPTURE    (1 << 0)
 65 #define VPE_FMT_TYPE_OUTPUT     (1 << 1)
 66 
 67 /* used as plane indices */
 68 #define VPE_MAX_PLANES  2
 69 #define VPE_LUMA        0
 70 #define VPE_CHROMA      1
 71 
 72 /* per m2m context info */
 73 #define VPE_MAX_SRC_BUFS        3       /* need 3 src fields to de-interlace */
 74 
 75 #define VPE_DEF_BUFS_PER_JOB    1       /* default one buffer per batch job */
 76 
 77 /*
 78  * each VPE context can need up to 3 config descriptors, 7 input descriptors,
 79  * 3 output descriptors, and 10 control descriptors
 80  */
 81 #define VPE_DESC_LIST_SIZE      (10 * VPDMA_DTD_DESC_SIZE +     \
 82                                         13 * VPDMA_CFD_CTD_DESC_SIZE)
 83 
 84 #define vpe_dbg(vpedev, fmt, arg...)    \
 85                 dev_dbg((vpedev)->v4l2_dev.dev, fmt, ##arg)
 86 #define vpe_err(vpedev, fmt, arg...)    \
 87                 dev_err((vpedev)->v4l2_dev.dev, fmt, ##arg)
 88 
 89 struct vpe_us_coeffs {
 90         unsigned short  anchor_fid0_c0;
 91         unsigned short  anchor_fid0_c1;
 92         unsigned short  anchor_fid0_c2;
 93         unsigned short  anchor_fid0_c3;
 94         unsigned short  interp_fid0_c0;
 95         unsigned short  interp_fid0_c1;
 96         unsigned short  interp_fid0_c2;
 97         unsigned short  interp_fid0_c3;
 98         unsigned short  anchor_fid1_c0;
 99         unsigned short  anchor_fid1_c1;
100         unsigned short  anchor_fid1_c2;
101         unsigned short  anchor_fid1_c3;
102         unsigned short  interp_fid1_c0;
103         unsigned short  interp_fid1_c1;
104         unsigned short  interp_fid1_c2;
105         unsigned short  interp_fid1_c3;
106 };
107 
108 /*
109  * Default upsampler coefficients
110  */
111 static const struct vpe_us_coeffs us_coeffs[] = {
112         {
113                 /* Coefficients for progressive input */
114                 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8,
115                 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8,
116         },
117         {
118                 /* Coefficients for Top Field Interlaced input */
119                 0x0051, 0x03D5, 0x3FE3, 0x3FF7, 0x3FB5, 0x02E9, 0x018F, 0x3FD3,
120                 /* Coefficients for Bottom Field Interlaced input */
121                 0x016B, 0x0247, 0x00B1, 0x3F9D, 0x3FCF, 0x03DB, 0x005D, 0x3FF9,
122         },
123 };
124 
125 /*
126  * the following registers are for configuring some of the parameters of the
127  * motion and edge detection blocks inside DEI, these generally remain the same,
128  * these could be passed later via userspace if some one needs to tweak these.
129  */
130 struct vpe_dei_regs {
131         unsigned long mdt_spacial_freq_thr_reg;         /* VPE_DEI_REG2 */
132         unsigned long edi_config_reg;                   /* VPE_DEI_REG3 */
133         unsigned long edi_lut_reg0;                     /* VPE_DEI_REG4 */
134         unsigned long edi_lut_reg1;                     /* VPE_DEI_REG5 */
135         unsigned long edi_lut_reg2;                     /* VPE_DEI_REG6 */
136         unsigned long edi_lut_reg3;                     /* VPE_DEI_REG7 */
137 };
138 
139 /*
140  * default expert DEI register values, unlikely to be modified.
141  */
142 static const struct vpe_dei_regs dei_regs = {
143         .mdt_spacial_freq_thr_reg = 0x020C0804u,
144         .edi_config_reg = 0x0118100Fu,
145         .edi_lut_reg0 = 0x08040200u,
146         .edi_lut_reg1 = 0x1010100Cu,
147         .edi_lut_reg2 = 0x10101010u,
148         .edi_lut_reg3 = 0x10101010u,
149 };
150 
151 /*
152  * The port_data structure contains per-port data.
153  */
154 struct vpe_port_data {
155         enum vpdma_channel channel;     /* VPDMA channel */
156         u8      vb_index;               /* input frame f, f-1, f-2 index */
157         u8      vb_part;                /* plane index for co-panar formats */
158 };
159 
160 /*
161  * Define indices into the port_data tables
162  */
163 #define VPE_PORT_LUMA1_IN       0
164 #define VPE_PORT_CHROMA1_IN     1
165 #define VPE_PORT_LUMA2_IN       2
166 #define VPE_PORT_CHROMA2_IN     3
167 #define VPE_PORT_LUMA3_IN       4
168 #define VPE_PORT_CHROMA3_IN     5
169 #define VPE_PORT_MV_IN          6
170 #define VPE_PORT_MV_OUT         7
171 #define VPE_PORT_LUMA_OUT       8
172 #define VPE_PORT_CHROMA_OUT     9
173 #define VPE_PORT_RGB_OUT        10
174 
175 static const struct vpe_port_data port_data[11] = {
176         [VPE_PORT_LUMA1_IN] = {
177                 .channel        = VPE_CHAN_LUMA1_IN,
178                 .vb_index       = 0,
179                 .vb_part        = VPE_LUMA,
180         },
181         [VPE_PORT_CHROMA1_IN] = {
182                 .channel        = VPE_CHAN_CHROMA1_IN,
183                 .vb_index       = 0,
184                 .vb_part        = VPE_CHROMA,
185         },
186         [VPE_PORT_LUMA2_IN] = {
187                 .channel        = VPE_CHAN_LUMA2_IN,
188                 .vb_index       = 1,
189                 .vb_part        = VPE_LUMA,
190         },
191         [VPE_PORT_CHROMA2_IN] = {
192                 .channel        = VPE_CHAN_CHROMA2_IN,
193                 .vb_index       = 1,
194                 .vb_part        = VPE_CHROMA,
195         },
196         [VPE_PORT_LUMA3_IN] = {
197                 .channel        = VPE_CHAN_LUMA3_IN,
198                 .vb_index       = 2,
199                 .vb_part        = VPE_LUMA,
200         },
201         [VPE_PORT_CHROMA3_IN] = {
202                 .channel        = VPE_CHAN_CHROMA3_IN,
203                 .vb_index       = 2,
204                 .vb_part        = VPE_CHROMA,
205         },
206         [VPE_PORT_MV_IN] = {
207                 .channel        = VPE_CHAN_MV_IN,
208         },
209         [VPE_PORT_MV_OUT] = {
210                 .channel        = VPE_CHAN_MV_OUT,
211         },
212         [VPE_PORT_LUMA_OUT] = {
213                 .channel        = VPE_CHAN_LUMA_OUT,
214                 .vb_part        = VPE_LUMA,
215         },
216         [VPE_PORT_CHROMA_OUT] = {
217                 .channel        = VPE_CHAN_CHROMA_OUT,
218                 .vb_part        = VPE_CHROMA,
219         },
220         [VPE_PORT_RGB_OUT] = {
221                 .channel        = VPE_CHAN_RGB_OUT,
222                 .vb_part        = VPE_LUMA,
223         },
224 };
225 
226 
227 /* driver info for each of the supported video formats */
228 struct vpe_fmt {
229         char    *name;                  /* human-readable name */
230         u32     fourcc;                 /* standard format identifier */
231         u8      types;                  /* CAPTURE and/or OUTPUT */
232         u8      coplanar;               /* set for unpacked Luma and Chroma */
233         /* vpdma format info for each plane */
234         struct vpdma_data_format const *vpdma_fmt[VPE_MAX_PLANES];
235 };
236 
237 static struct vpe_fmt vpe_formats[] = {
238         {
239                 .name           = "YUV 422 co-planar",
240                 .fourcc         = V4L2_PIX_FMT_NV16,
241                 .types          = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
242                 .coplanar       = 1,
243                 .vpdma_fmt      = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y444],
244                                     &vpdma_yuv_fmts[VPDMA_DATA_FMT_C444],
245                                   },
246         },
247         {
248                 .name           = "YUV 420 co-planar",
249                 .fourcc         = V4L2_PIX_FMT_NV12,
250                 .types          = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
251                 .coplanar       = 1,
252                 .vpdma_fmt      = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y420],
253                                     &vpdma_yuv_fmts[VPDMA_DATA_FMT_C420],
254                                   },
255         },
256         {
257                 .name           = "YUYV 422 packed",
258                 .fourcc         = V4L2_PIX_FMT_YUYV,
259                 .types          = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
260                 .coplanar       = 0,
261                 .vpdma_fmt      = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_YC422],
262                                   },
263         },
264         {
265                 .name           = "UYVY 422 packed",
266                 .fourcc         = V4L2_PIX_FMT_UYVY,
267                 .types          = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
268                 .coplanar       = 0,
269                 .vpdma_fmt      = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_CY422],
270                                   },
271         },
272         {
273                 .name           = "RGB888 packed",
274                 .fourcc         = V4L2_PIX_FMT_RGB24,
275                 .types          = VPE_FMT_TYPE_CAPTURE,
276                 .coplanar       = 0,
277                 .vpdma_fmt      = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGB24],
278                                   },
279         },
280         {
281                 .name           = "ARGB32",
282                 .fourcc         = V4L2_PIX_FMT_RGB32,
283                 .types          = VPE_FMT_TYPE_CAPTURE,
284                 .coplanar       = 0,
285                 .vpdma_fmt      = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ARGB32],
286                                   },
287         },
288         {
289                 .name           = "BGR888 packed",
290                 .fourcc         = V4L2_PIX_FMT_BGR24,
291                 .types          = VPE_FMT_TYPE_CAPTURE,
292                 .coplanar       = 0,
293                 .vpdma_fmt      = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_BGR24],
294                                   },
295         },
296         {
297                 .name           = "ABGR32",
298                 .fourcc         = V4L2_PIX_FMT_BGR32,
299                 .types          = VPE_FMT_TYPE_CAPTURE,
300                 .coplanar       = 0,
301                 .vpdma_fmt      = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ABGR32],
302                                   },
303         },
304 };
305 
306 /*
307  * per-queue, driver-specific private data.
308  * there is one source queue and one destination queue for each m2m context.
309  */
310 struct vpe_q_data {
311         unsigned int            width;                          /* frame width */
312         unsigned int            height;                         /* frame height */
313         unsigned int            bytesperline[VPE_MAX_PLANES];   /* bytes per line in memory */
314         enum v4l2_colorspace    colorspace;
315         enum v4l2_field         field;                          /* supported field value */
316         unsigned int            flags;
317         unsigned int            sizeimage[VPE_MAX_PLANES];      /* image size in memory */
318         struct v4l2_rect        c_rect;                         /* crop/compose rectangle */
319         struct vpe_fmt          *fmt;                           /* format info */
320 };
321 
322 /* vpe_q_data flag bits */
323 #define Q_DATA_FRAME_1D         (1 << 0)
324 #define Q_DATA_MODE_TILED       (1 << 1)
325 #define Q_DATA_INTERLACED       (1 << 2)
326 
327 enum {
328         Q_DATA_SRC = 0,
329         Q_DATA_DST = 1,
330 };
331 
332 /* find our format description corresponding to the passed v4l2_format */
333 static struct vpe_fmt *find_format(struct v4l2_format *f)
334 {
335         struct vpe_fmt *fmt;
336         unsigned int k;
337 
338         for (k = 0; k < ARRAY_SIZE(vpe_formats); k++) {
339                 fmt = &vpe_formats[k];
340                 if (fmt->fourcc == f->fmt.pix.pixelformat)
341                         return fmt;
342         }
343 
344         return NULL;
345 }
346 
347 /*
348  * there is one vpe_dev structure in the driver, it is shared by
349  * all instances.
350  */
351 struct vpe_dev {
352         struct v4l2_device      v4l2_dev;
353         struct video_device     vfd;
354         struct v4l2_m2m_dev     *m2m_dev;
355 
356         atomic_t                num_instances;  /* count of driver instances */
357         dma_addr_t              loaded_mmrs;    /* shadow mmrs in device */
358         struct mutex            dev_mutex;
359         spinlock_t              lock;
360 
361         int                     irq;
362         void __iomem            *base;
363         struct resource         *res;
364 
365         struct vb2_alloc_ctx    *alloc_ctx;
366         struct vpdma_data       *vpdma;         /* vpdma data handle */
367         struct sc_data          *sc;            /* scaler data handle */
368         struct csc_data         *csc;           /* csc data handle */
369 };
370 
371 /*
372  * There is one vpe_ctx structure for each m2m context.
373  */
374 struct vpe_ctx {
375         struct v4l2_fh          fh;
376         struct vpe_dev          *dev;
377         struct v4l2_ctrl_handler hdl;
378 
379         unsigned int            field;                  /* current field */
380         unsigned int            sequence;               /* current frame/field seq */
381         unsigned int            aborting;               /* abort after next irq */
382 
383         unsigned int            bufs_per_job;           /* input buffers per batch */
384         unsigned int            bufs_completed;         /* bufs done in this batch */
385 
386         struct vpe_q_data       q_data[2];              /* src & dst queue data */
387         struct vb2_v4l2_buffer  *src_vbs[VPE_MAX_SRC_BUFS];
388         struct vb2_v4l2_buffer  *dst_vb;
389 
390         dma_addr_t              mv_buf_dma[2];          /* dma addrs of motion vector in/out bufs */
391         void                    *mv_buf[2];             /* virtual addrs of motion vector bufs */
392         size_t                  mv_buf_size;            /* current motion vector buffer size */
393         struct vpdma_buf        mmr_adb;                /* shadow reg addr/data block */
394         struct vpdma_buf        sc_coeff_h;             /* h coeff buffer */
395         struct vpdma_buf        sc_coeff_v;             /* v coeff buffer */
396         struct vpdma_desc_list  desc_list;              /* DMA descriptor list */
397 
398         bool                    deinterlacing;          /* using de-interlacer */
399         bool                    load_mmrs;              /* have new shadow reg values */
400 
401         unsigned int            src_mv_buf_selector;
402 };
403 
404 
405 /*
406  * M2M devices get 2 queues.
407  * Return the queue given the type.
408  */
409 static struct vpe_q_data *get_q_data(struct vpe_ctx *ctx,
410                                      enum v4l2_buf_type type)
411 {
412         switch (type) {
413         case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE:
414         case V4L2_BUF_TYPE_VIDEO_OUTPUT:
415                 return &ctx->q_data[Q_DATA_SRC];
416         case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE:
417         case V4L2_BUF_TYPE_VIDEO_CAPTURE:
418                 return &ctx->q_data[Q_DATA_DST];
419         default:
420                 BUG();
421         }
422         return NULL;
423 }
424 
425 static u32 read_reg(struct vpe_dev *dev, int offset)
426 {
427         return ioread32(dev->base + offset);
428 }
429 
430 static void write_reg(struct vpe_dev *dev, int offset, u32 value)
431 {
432         iowrite32(value, dev->base + offset);
433 }
434 
435 /* register field read/write helpers */
436 static int get_field(u32 value, u32 mask, int shift)
437 {
438         return (value & (mask << shift)) >> shift;
439 }
440 
441 static int read_field_reg(struct vpe_dev *dev, int offset, u32 mask, int shift)
442 {
443         return get_field(read_reg(dev, offset), mask, shift);
444 }
445 
446 static void write_field(u32 *valp, u32 field, u32 mask, int shift)
447 {
448         u32 val = *valp;
449 
450         val &= ~(mask << shift);
451         val |= (field & mask) << shift;
452         *valp = val;
453 }
454 
455 static void write_field_reg(struct vpe_dev *dev, int offset, u32 field,
456                 u32 mask, int shift)
457 {
458         u32 val = read_reg(dev, offset);
459 
460         write_field(&val, field, mask, shift);
461 
462         write_reg(dev, offset, val);
463 }
464 
465 /*
466  * DMA address/data block for the shadow registers
467  */
468 struct vpe_mmr_adb {
469         struct vpdma_adb_hdr    out_fmt_hdr;
470         u32                     out_fmt_reg[1];
471         u32                     out_fmt_pad[3];
472         struct vpdma_adb_hdr    us1_hdr;
473         u32                     us1_regs[8];
474         struct vpdma_adb_hdr    us2_hdr;
475         u32                     us2_regs[8];
476         struct vpdma_adb_hdr    us3_hdr;
477         u32                     us3_regs[8];
478         struct vpdma_adb_hdr    dei_hdr;
479         u32                     dei_regs[8];
480         struct vpdma_adb_hdr    sc_hdr0;
481         u32                     sc_regs0[7];
482         u32                     sc_pad0[1];
483         struct vpdma_adb_hdr    sc_hdr8;
484         u32                     sc_regs8[6];
485         u32                     sc_pad8[2];
486         struct vpdma_adb_hdr    sc_hdr17;
487         u32                     sc_regs17[9];
488         u32                     sc_pad17[3];
489         struct vpdma_adb_hdr    csc_hdr;
490         u32                     csc_regs[6];
491         u32                     csc_pad[2];
492 };
493 
494 #define GET_OFFSET_TOP(ctx, obj, reg)   \
495         ((obj)->res->start - ctx->dev->res->start + reg)
496 
497 #define VPE_SET_MMR_ADB_HDR(ctx, hdr, regs, offset_a)   \
498         VPDMA_SET_MMR_ADB_HDR(ctx->mmr_adb, vpe_mmr_adb, hdr, regs, offset_a)
499 /*
500  * Set the headers for all of the address/data block structures.
501  */
502 static void init_adb_hdrs(struct vpe_ctx *ctx)
503 {
504         VPE_SET_MMR_ADB_HDR(ctx, out_fmt_hdr, out_fmt_reg, VPE_CLK_FORMAT_SELECT);
505         VPE_SET_MMR_ADB_HDR(ctx, us1_hdr, us1_regs, VPE_US1_R0);
506         VPE_SET_MMR_ADB_HDR(ctx, us2_hdr, us2_regs, VPE_US2_R0);
507         VPE_SET_MMR_ADB_HDR(ctx, us3_hdr, us3_regs, VPE_US3_R0);
508         VPE_SET_MMR_ADB_HDR(ctx, dei_hdr, dei_regs, VPE_DEI_FRAME_SIZE);
509         VPE_SET_MMR_ADB_HDR(ctx, sc_hdr0, sc_regs0,
510                 GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC0));
511         VPE_SET_MMR_ADB_HDR(ctx, sc_hdr8, sc_regs8,
512                 GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC8));
513         VPE_SET_MMR_ADB_HDR(ctx, sc_hdr17, sc_regs17,
514                 GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC17));
515         VPE_SET_MMR_ADB_HDR(ctx, csc_hdr, csc_regs,
516                 GET_OFFSET_TOP(ctx, ctx->dev->csc, CSC_CSC00));
517 };
518 
519 /*
520  * Allocate or re-allocate the motion vector DMA buffers
521  * There are two buffers, one for input and one for output.
522  * However, the roles are reversed after each field is processed.
523  * In other words, after each field is processed, the previous
524  * output (dst) MV buffer becomes the new input (src) MV buffer.
525  */
526 static int realloc_mv_buffers(struct vpe_ctx *ctx, size_t size)
527 {
528         struct device *dev = ctx->dev->v4l2_dev.dev;
529 
530         if (ctx->mv_buf_size == size)
531                 return 0;
532 
533         if (ctx->mv_buf[0])
534                 dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[0],
535                         ctx->mv_buf_dma[0]);
536 
537         if (ctx->mv_buf[1])
538                 dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[1],
539                         ctx->mv_buf_dma[1]);
540 
541         if (size == 0)
542                 return 0;
543 
544         ctx->mv_buf[0] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[0],
545                                 GFP_KERNEL);
546         if (!ctx->mv_buf[0]) {
547                 vpe_err(ctx->dev, "failed to allocate motion vector buffer\n");
548                 return -ENOMEM;
549         }
550 
551         ctx->mv_buf[1] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[1],
552                                 GFP_KERNEL);
553         if (!ctx->mv_buf[1]) {
554                 vpe_err(ctx->dev, "failed to allocate motion vector buffer\n");
555                 dma_free_coherent(dev, size, ctx->mv_buf[0],
556                         ctx->mv_buf_dma[0]);
557 
558                 return -ENOMEM;
559         }
560 
561         ctx->mv_buf_size = size;
562         ctx->src_mv_buf_selector = 0;
563 
564         return 0;
565 }
566 
567 static void free_mv_buffers(struct vpe_ctx *ctx)
568 {
569         realloc_mv_buffers(ctx, 0);
570 }
571 
572 /*
573  * While de-interlacing, we keep the two most recent input buffers
574  * around.  This function frees those two buffers when we have
575  * finished processing the current stream.
576  */
577 static void free_vbs(struct vpe_ctx *ctx)
578 {
579         struct vpe_dev *dev = ctx->dev;
580         unsigned long flags;
581 
582         if (ctx->src_vbs[2] == NULL)
583                 return;
584 
585         spin_lock_irqsave(&dev->lock, flags);
586         if (ctx->src_vbs[2]) {
587                 v4l2_m2m_buf_done(ctx->src_vbs[2], VB2_BUF_STATE_DONE);
588                 v4l2_m2m_buf_done(ctx->src_vbs[1], VB2_BUF_STATE_DONE);
589         }
590         spin_unlock_irqrestore(&dev->lock, flags);
591 }
592 
593 /*
594  * Enable or disable the VPE clocks
595  */
596 static void vpe_set_clock_enable(struct vpe_dev *dev, bool on)
597 {
598         u32 val = 0;
599 
600         if (on)
601                 val = VPE_DATA_PATH_CLK_ENABLE | VPE_VPEDMA_CLK_ENABLE;
602         write_reg(dev, VPE_CLK_ENABLE, val);
603 }
604 
605 static void vpe_top_reset(struct vpe_dev *dev)
606 {
607 
608         write_field_reg(dev, VPE_CLK_RESET, 1, VPE_DATA_PATH_CLK_RESET_MASK,
609                 VPE_DATA_PATH_CLK_RESET_SHIFT);
610 
611         usleep_range(100, 150);
612 
613         write_field_reg(dev, VPE_CLK_RESET, 0, VPE_DATA_PATH_CLK_RESET_MASK,
614                 VPE_DATA_PATH_CLK_RESET_SHIFT);
615 }
616 
617 static void vpe_top_vpdma_reset(struct vpe_dev *dev)
618 {
619         write_field_reg(dev, VPE_CLK_RESET, 1, VPE_VPDMA_CLK_RESET_MASK,
620                 VPE_VPDMA_CLK_RESET_SHIFT);
621 
622         usleep_range(100, 150);
623 
624         write_field_reg(dev, VPE_CLK_RESET, 0, VPE_VPDMA_CLK_RESET_MASK,
625                 VPE_VPDMA_CLK_RESET_SHIFT);
626 }
627 
628 /*
629  * Load the correct of upsampler coefficients into the shadow MMRs
630  */
631 static void set_us_coefficients(struct vpe_ctx *ctx)
632 {
633         struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
634         struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
635         u32 *us1_reg = &mmr_adb->us1_regs[0];
636         u32 *us2_reg = &mmr_adb->us2_regs[0];
637         u32 *us3_reg = &mmr_adb->us3_regs[0];
638         const unsigned short *cp, *end_cp;
639 
640         cp = &us_coeffs[0].anchor_fid0_c0;
641 
642         if (s_q_data->flags & Q_DATA_INTERLACED)        /* interlaced */
643                 cp += sizeof(us_coeffs[0]) / sizeof(*cp);
644 
645         end_cp = cp + sizeof(us_coeffs[0]) / sizeof(*cp);
646 
647         while (cp < end_cp) {
648                 write_field(us1_reg, *cp++, VPE_US_C0_MASK, VPE_US_C0_SHIFT);
649                 write_field(us1_reg, *cp++, VPE_US_C1_MASK, VPE_US_C1_SHIFT);
650                 *us2_reg++ = *us1_reg;
651                 *us3_reg++ = *us1_reg++;
652         }
653         ctx->load_mmrs = true;
654 }
655 
656 /*
657  * Set the upsampler config mode and the VPDMA line mode in the shadow MMRs.
658  */
659 static void set_cfg_and_line_modes(struct vpe_ctx *ctx)
660 {
661         struct vpe_fmt *fmt = ctx->q_data[Q_DATA_SRC].fmt;
662         struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
663         u32 *us1_reg0 = &mmr_adb->us1_regs[0];
664         u32 *us2_reg0 = &mmr_adb->us2_regs[0];
665         u32 *us3_reg0 = &mmr_adb->us3_regs[0];
666         int line_mode = 1;
667         int cfg_mode = 1;
668 
669         /*
670          * Cfg Mode 0: YUV420 source, enable upsampler, DEI is de-interlacing.
671          * Cfg Mode 1: YUV422 source, disable upsampler, DEI is de-interlacing.
672          */
673 
674         if (fmt->fourcc == V4L2_PIX_FMT_NV12) {
675                 cfg_mode = 0;
676                 line_mode = 0;          /* double lines to line buffer */
677         }
678 
679         write_field(us1_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
680         write_field(us2_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
681         write_field(us3_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
682 
683         /* regs for now */
684         vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA1_IN);
685         vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA2_IN);
686         vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA3_IN);
687 
688         /* frame start for input luma */
689         vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
690                 VPE_CHAN_LUMA1_IN);
691         vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
692                 VPE_CHAN_LUMA2_IN);
693         vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
694                 VPE_CHAN_LUMA3_IN);
695 
696         /* frame start for input chroma */
697         vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
698                 VPE_CHAN_CHROMA1_IN);
699         vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
700                 VPE_CHAN_CHROMA2_IN);
701         vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
702                 VPE_CHAN_CHROMA3_IN);
703 
704         /* frame start for MV in client */
705         vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
706                 VPE_CHAN_MV_IN);
707 
708         ctx->load_mmrs = true;
709 }
710 
711 /*
712  * Set the shadow registers that are modified when the source
713  * format changes.
714  */
715 static void set_src_registers(struct vpe_ctx *ctx)
716 {
717         set_us_coefficients(ctx);
718 }
719 
720 /*
721  * Set the shadow registers that are modified when the destination
722  * format changes.
723  */
724 static void set_dst_registers(struct vpe_ctx *ctx)
725 {
726         struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
727         enum v4l2_colorspace clrspc = ctx->q_data[Q_DATA_DST].colorspace;
728         struct vpe_fmt *fmt = ctx->q_data[Q_DATA_DST].fmt;
729         u32 val = 0;
730 
731         if (clrspc == V4L2_COLORSPACE_SRGB)
732                 val |= VPE_RGB_OUT_SELECT;
733         else if (fmt->fourcc == V4L2_PIX_FMT_NV16)
734                 val |= VPE_COLOR_SEPARATE_422;
735 
736         /*
737          * the source of CHR_DS and CSC is always the scaler, irrespective of
738          * whether it's used or not
739          */
740         val |= VPE_DS_SRC_DEI_SCALER | VPE_CSC_SRC_DEI_SCALER;
741 
742         if (fmt->fourcc != V4L2_PIX_FMT_NV12)
743                 val |= VPE_DS_BYPASS;
744 
745         mmr_adb->out_fmt_reg[0] = val;
746 
747         ctx->load_mmrs = true;
748 }
749 
750 /*
751  * Set the de-interlacer shadow register values
752  */
753 static void set_dei_regs(struct vpe_ctx *ctx)
754 {
755         struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
756         struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
757         unsigned int src_h = s_q_data->c_rect.height;
758         unsigned int src_w = s_q_data->c_rect.width;
759         u32 *dei_mmr0 = &mmr_adb->dei_regs[0];
760         bool deinterlace = true;
761         u32 val = 0;
762 
763         /*
764          * according to TRM, we should set DEI in progressive bypass mode when
765          * the input content is progressive, however, DEI is bypassed correctly
766          * for both progressive and interlace content in interlace bypass mode.
767          * It has been recommended not to use progressive bypass mode.
768          */
769         if ((!ctx->deinterlacing && (s_q_data->flags & Q_DATA_INTERLACED)) ||
770                         !(s_q_data->flags & Q_DATA_INTERLACED)) {
771                 deinterlace = false;
772                 val = VPE_DEI_INTERLACE_BYPASS;
773         }
774 
775         src_h = deinterlace ? src_h * 2 : src_h;
776 
777         val |= (src_h << VPE_DEI_HEIGHT_SHIFT) |
778                 (src_w << VPE_DEI_WIDTH_SHIFT) |
779                 VPE_DEI_FIELD_FLUSH;
780 
781         *dei_mmr0 = val;
782 
783         ctx->load_mmrs = true;
784 }
785 
786 static void set_dei_shadow_registers(struct vpe_ctx *ctx)
787 {
788         struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
789         u32 *dei_mmr = &mmr_adb->dei_regs[0];
790         const struct vpe_dei_regs *cur = &dei_regs;
791 
792         dei_mmr[2]  = cur->mdt_spacial_freq_thr_reg;
793         dei_mmr[3]  = cur->edi_config_reg;
794         dei_mmr[4]  = cur->edi_lut_reg0;
795         dei_mmr[5]  = cur->edi_lut_reg1;
796         dei_mmr[6]  = cur->edi_lut_reg2;
797         dei_mmr[7]  = cur->edi_lut_reg3;
798 
799         ctx->load_mmrs = true;
800 }
801 
802 /*
803  * Set the shadow registers whose values are modified when either the
804  * source or destination format is changed.
805  */
806 static int set_srcdst_params(struct vpe_ctx *ctx)
807 {
808         struct vpe_q_data *s_q_data =  &ctx->q_data[Q_DATA_SRC];
809         struct vpe_q_data *d_q_data =  &ctx->q_data[Q_DATA_DST];
810         struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
811         unsigned int src_w = s_q_data->c_rect.width;
812         unsigned int src_h = s_q_data->c_rect.height;
813         unsigned int dst_w = d_q_data->c_rect.width;
814         unsigned int dst_h = d_q_data->c_rect.height;
815         size_t mv_buf_size;
816         int ret;
817 
818         ctx->sequence = 0;
819         ctx->field = V4L2_FIELD_TOP;
820 
821         if ((s_q_data->flags & Q_DATA_INTERLACED) &&
822                         !(d_q_data->flags & Q_DATA_INTERLACED)) {
823                 int bytes_per_line;
824                 const struct vpdma_data_format *mv =
825                         &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
826 
827                 /*
828                  * we make sure that the source image has a 16 byte aligned
829                  * stride, we need to do the same for the motion vector buffer
830                  * by aligning it's stride to the next 16 byte boundry. this
831                  * extra space will not be used by the de-interlacer, but will
832                  * ensure that vpdma operates correctly
833                  */
834                 bytes_per_line = ALIGN((s_q_data->width * mv->depth) >> 3,
835                                         VPDMA_STRIDE_ALIGN);
836                 mv_buf_size = bytes_per_line * s_q_data->height;
837 
838                 ctx->deinterlacing = true;
839                 src_h <<= 1;
840         } else {
841                 ctx->deinterlacing = false;
842                 mv_buf_size = 0;
843         }
844 
845         free_vbs(ctx);
846 
847         ret = realloc_mv_buffers(ctx, mv_buf_size);
848         if (ret)
849                 return ret;
850 
851         set_cfg_and_line_modes(ctx);
852         set_dei_regs(ctx);
853 
854         csc_set_coeff(ctx->dev->csc, &mmr_adb->csc_regs[0],
855                 s_q_data->colorspace, d_q_data->colorspace);
856 
857         sc_set_hs_coeffs(ctx->dev->sc, ctx->sc_coeff_h.addr, src_w, dst_w);
858         sc_set_vs_coeffs(ctx->dev->sc, ctx->sc_coeff_v.addr, src_h, dst_h);
859 
860         sc_config_scaler(ctx->dev->sc, &mmr_adb->sc_regs0[0],
861                 &mmr_adb->sc_regs8[0], &mmr_adb->sc_regs17[0],
862                 src_w, src_h, dst_w, dst_h);
863 
864         return 0;
865 }
866 
867 /*
868  * Return the vpe_ctx structure for a given struct file
869  */
870 static struct vpe_ctx *file2ctx(struct file *file)
871 {
872         return container_of(file->private_data, struct vpe_ctx, fh);
873 }
874 
875 /*
876  * mem2mem callbacks
877  */
878 
879 /**
880  * job_ready() - check whether an instance is ready to be scheduled to run
881  */
882 static int job_ready(void *priv)
883 {
884         struct vpe_ctx *ctx = priv;
885         int needed = ctx->bufs_per_job;
886 
887         if (ctx->deinterlacing && ctx->src_vbs[2] == NULL)
888                 needed += 2;    /* need additional two most recent fields */
889 
890         if (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) < needed)
891                 return 0;
892 
893         if (v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) < needed)
894                 return 0;
895 
896         return 1;
897 }
898 
899 static void job_abort(void *priv)
900 {
901         struct vpe_ctx *ctx = priv;
902 
903         /* Will cancel the transaction in the next interrupt handler */
904         ctx->aborting = 1;
905 }
906 
907 /*
908  * Lock access to the device
909  */
910 static void vpe_lock(void *priv)
911 {
912         struct vpe_ctx *ctx = priv;
913         struct vpe_dev *dev = ctx->dev;
914         mutex_lock(&dev->dev_mutex);
915 }
916 
917 static void vpe_unlock(void *priv)
918 {
919         struct vpe_ctx *ctx = priv;
920         struct vpe_dev *dev = ctx->dev;
921         mutex_unlock(&dev->dev_mutex);
922 }
923 
924 static void vpe_dump_regs(struct vpe_dev *dev)
925 {
926 #define DUMPREG(r) vpe_dbg(dev, "%-35s %08x\n", #r, read_reg(dev, VPE_##r))
927 
928         vpe_dbg(dev, "VPE Registers:\n");
929 
930         DUMPREG(PID);
931         DUMPREG(SYSCONFIG);
932         DUMPREG(INT0_STATUS0_RAW);
933         DUMPREG(INT0_STATUS0);
934         DUMPREG(INT0_ENABLE0);
935         DUMPREG(INT0_STATUS1_RAW);
936         DUMPREG(INT0_STATUS1);
937         DUMPREG(INT0_ENABLE1);
938         DUMPREG(CLK_ENABLE);
939         DUMPREG(CLK_RESET);
940         DUMPREG(CLK_FORMAT_SELECT);
941         DUMPREG(CLK_RANGE_MAP);
942         DUMPREG(US1_R0);
943         DUMPREG(US1_R1);
944         DUMPREG(US1_R2);
945         DUMPREG(US1_R3);
946         DUMPREG(US1_R4);
947         DUMPREG(US1_R5);
948         DUMPREG(US1_R6);
949         DUMPREG(US1_R7);
950         DUMPREG(US2_R0);
951         DUMPREG(US2_R1);
952         DUMPREG(US2_R2);
953         DUMPREG(US2_R3);
954         DUMPREG(US2_R4);
955         DUMPREG(US2_R5);
956         DUMPREG(US2_R6);
957         DUMPREG(US2_R7);
958         DUMPREG(US3_R0);
959         DUMPREG(US3_R1);
960         DUMPREG(US3_R2);
961         DUMPREG(US3_R3);
962         DUMPREG(US3_R4);
963         DUMPREG(US3_R5);
964         DUMPREG(US3_R6);
965         DUMPREG(US3_R7);
966         DUMPREG(DEI_FRAME_SIZE);
967         DUMPREG(MDT_BYPASS);
968         DUMPREG(MDT_SF_THRESHOLD);
969         DUMPREG(EDI_CONFIG);
970         DUMPREG(DEI_EDI_LUT_R0);
971         DUMPREG(DEI_EDI_LUT_R1);
972         DUMPREG(DEI_EDI_LUT_R2);
973         DUMPREG(DEI_EDI_LUT_R3);
974         DUMPREG(DEI_FMD_WINDOW_R0);
975         DUMPREG(DEI_FMD_WINDOW_R1);
976         DUMPREG(DEI_FMD_CONTROL_R0);
977         DUMPREG(DEI_FMD_CONTROL_R1);
978         DUMPREG(DEI_FMD_STATUS_R0);
979         DUMPREG(DEI_FMD_STATUS_R1);
980         DUMPREG(DEI_FMD_STATUS_R2);
981 #undef DUMPREG
982 
983         sc_dump_regs(dev->sc);
984         csc_dump_regs(dev->csc);
985 }
986 
987 static void add_out_dtd(struct vpe_ctx *ctx, int port)
988 {
989         struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_DST];
990         const struct vpe_port_data *p_data = &port_data[port];
991         struct vb2_buffer *vb = &ctx->dst_vb->vb2_buf;
992         struct vpe_fmt *fmt = q_data->fmt;
993         const struct vpdma_data_format *vpdma_fmt;
994         int mv_buf_selector = !ctx->src_mv_buf_selector;
995         dma_addr_t dma_addr;
996         u32 flags = 0;
997 
998         if (port == VPE_PORT_MV_OUT) {
999                 vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
1000                 dma_addr = ctx->mv_buf_dma[mv_buf_selector];
1001         } else {
1002                 /* to incorporate interleaved formats */
1003                 int plane = fmt->coplanar ? p_data->vb_part : 0;
1004 
1005                 vpdma_fmt = fmt->vpdma_fmt[plane];
1006                 dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane);
1007                 if (!dma_addr) {
1008                         vpe_err(ctx->dev,
1009                                 "acquiring output buffer(%d) dma_addr failed\n",
1010                                 port);
1011                         return;
1012                 }
1013         }
1014 
1015         if (q_data->flags & Q_DATA_FRAME_1D)
1016                 flags |= VPDMA_DATA_FRAME_1D;
1017         if (q_data->flags & Q_DATA_MODE_TILED)
1018                 flags |= VPDMA_DATA_MODE_TILED;
1019 
1020         vpdma_add_out_dtd(&ctx->desc_list, q_data->width, &q_data->c_rect,
1021                 vpdma_fmt, dma_addr, p_data->channel, flags);
1022 }
1023 
1024 static void add_in_dtd(struct vpe_ctx *ctx, int port)
1025 {
1026         struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_SRC];
1027         const struct vpe_port_data *p_data = &port_data[port];
1028         struct vb2_buffer *vb = &ctx->src_vbs[p_data->vb_index]->vb2_buf;
1029         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1030         struct vpe_fmt *fmt = q_data->fmt;
1031         const struct vpdma_data_format *vpdma_fmt;
1032         int mv_buf_selector = ctx->src_mv_buf_selector;
1033         int field = vbuf->field == V4L2_FIELD_BOTTOM;
1034         int frame_width, frame_height;
1035         dma_addr_t dma_addr;
1036         u32 flags = 0;
1037 
1038         if (port == VPE_PORT_MV_IN) {
1039                 vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
1040                 dma_addr = ctx->mv_buf_dma[mv_buf_selector];
1041         } else {
1042                 /* to incorporate interleaved formats */
1043                 int plane = fmt->coplanar ? p_data->vb_part : 0;
1044 
1045                 vpdma_fmt = fmt->vpdma_fmt[plane];
1046 
1047                 dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane);
1048                 if (!dma_addr) {
1049                         vpe_err(ctx->dev,
1050                                 "acquiring input buffer(%d) dma_addr failed\n",
1051                                 port);
1052                         return;
1053                 }
1054         }
1055 
1056         if (q_data->flags & Q_DATA_FRAME_1D)
1057                 flags |= VPDMA_DATA_FRAME_1D;
1058         if (q_data->flags & Q_DATA_MODE_TILED)
1059                 flags |= VPDMA_DATA_MODE_TILED;
1060 
1061         frame_width = q_data->c_rect.width;
1062         frame_height = q_data->c_rect.height;
1063 
1064         if (p_data->vb_part && fmt->fourcc == V4L2_PIX_FMT_NV12)
1065                 frame_height /= 2;
1066 
1067         vpdma_add_in_dtd(&ctx->desc_list, q_data->width, &q_data->c_rect,
1068                 vpdma_fmt, dma_addr, p_data->channel, field, flags, frame_width,
1069                 frame_height, 0, 0);
1070 }
1071 
1072 /*
1073  * Enable the expected IRQ sources
1074  */
1075 static void enable_irqs(struct vpe_ctx *ctx)
1076 {
1077         write_reg(ctx->dev, VPE_INT0_ENABLE0_SET, VPE_INT0_LIST0_COMPLETE);
1078         write_reg(ctx->dev, VPE_INT0_ENABLE1_SET, VPE_DEI_ERROR_INT |
1079                                 VPE_DS1_UV_ERROR_INT);
1080 
1081         vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, true);
1082 }
1083 
1084 static void disable_irqs(struct vpe_ctx *ctx)
1085 {
1086         write_reg(ctx->dev, VPE_INT0_ENABLE0_CLR, 0xffffffff);
1087         write_reg(ctx->dev, VPE_INT0_ENABLE1_CLR, 0xffffffff);
1088 
1089         vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, false);
1090 }
1091 
1092 /* device_run() - prepares and starts the device
1093  *
1094  * This function is only called when both the source and destination
1095  * buffers are in place.
1096  */
1097 static void device_run(void *priv)
1098 {
1099         struct vpe_ctx *ctx = priv;
1100         struct sc_data *sc = ctx->dev->sc;
1101         struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
1102 
1103         if (ctx->deinterlacing && ctx->src_vbs[2] == NULL) {
1104                 ctx->src_vbs[2] = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1105                 WARN_ON(ctx->src_vbs[2] == NULL);
1106                 ctx->src_vbs[1] = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1107                 WARN_ON(ctx->src_vbs[1] == NULL);
1108         }
1109 
1110         ctx->src_vbs[0] = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1111         WARN_ON(ctx->src_vbs[0] == NULL);
1112         ctx->dst_vb = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1113         WARN_ON(ctx->dst_vb == NULL);
1114 
1115         /* config descriptors */
1116         if (ctx->dev->loaded_mmrs != ctx->mmr_adb.dma_addr || ctx->load_mmrs) {
1117                 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->mmr_adb);
1118                 vpdma_add_cfd_adb(&ctx->desc_list, CFD_MMR_CLIENT, &ctx->mmr_adb);
1119                 ctx->dev->loaded_mmrs = ctx->mmr_adb.dma_addr;
1120                 ctx->load_mmrs = false;
1121         }
1122 
1123         if (sc->loaded_coeff_h != ctx->sc_coeff_h.dma_addr ||
1124                         sc->load_coeff_h) {
1125                 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->sc_coeff_h);
1126                 vpdma_add_cfd_block(&ctx->desc_list, CFD_SC_CLIENT,
1127                         &ctx->sc_coeff_h, 0);
1128 
1129                 sc->loaded_coeff_h = ctx->sc_coeff_h.dma_addr;
1130                 sc->load_coeff_h = false;
1131         }
1132 
1133         if (sc->loaded_coeff_v != ctx->sc_coeff_v.dma_addr ||
1134                         sc->load_coeff_v) {
1135                 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->sc_coeff_v);
1136                 vpdma_add_cfd_block(&ctx->desc_list, CFD_SC_CLIENT,
1137                         &ctx->sc_coeff_v, SC_COEF_SRAM_SIZE >> 4);
1138 
1139                 sc->loaded_coeff_v = ctx->sc_coeff_v.dma_addr;
1140                 sc->load_coeff_v = false;
1141         }
1142 
1143         /* output data descriptors */
1144         if (ctx->deinterlacing)
1145                 add_out_dtd(ctx, VPE_PORT_MV_OUT);
1146 
1147         if (d_q_data->colorspace == V4L2_COLORSPACE_SRGB) {
1148                 add_out_dtd(ctx, VPE_PORT_RGB_OUT);
1149         } else {
1150                 add_out_dtd(ctx, VPE_PORT_LUMA_OUT);
1151                 if (d_q_data->fmt->coplanar)
1152                         add_out_dtd(ctx, VPE_PORT_CHROMA_OUT);
1153         }
1154 
1155         /* input data descriptors */
1156         if (ctx->deinterlacing) {
1157                 add_in_dtd(ctx, VPE_PORT_LUMA3_IN);
1158                 add_in_dtd(ctx, VPE_PORT_CHROMA3_IN);
1159 
1160                 add_in_dtd(ctx, VPE_PORT_LUMA2_IN);
1161                 add_in_dtd(ctx, VPE_PORT_CHROMA2_IN);
1162         }
1163 
1164         add_in_dtd(ctx, VPE_PORT_LUMA1_IN);
1165         add_in_dtd(ctx, VPE_PORT_CHROMA1_IN);
1166 
1167         if (ctx->deinterlacing)
1168                 add_in_dtd(ctx, VPE_PORT_MV_IN);
1169 
1170         /* sync on channel control descriptors for input ports */
1171         vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_LUMA1_IN);
1172         vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_CHROMA1_IN);
1173 
1174         if (ctx->deinterlacing) {
1175                 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1176                         VPE_CHAN_LUMA2_IN);
1177                 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1178                         VPE_CHAN_CHROMA2_IN);
1179 
1180                 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1181                         VPE_CHAN_LUMA3_IN);
1182                 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1183                         VPE_CHAN_CHROMA3_IN);
1184 
1185                 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_IN);
1186         }
1187 
1188         /* sync on channel control descriptors for output ports */
1189         if (d_q_data->colorspace == V4L2_COLORSPACE_SRGB) {
1190                 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1191                         VPE_CHAN_RGB_OUT);
1192         } else {
1193                 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1194                         VPE_CHAN_LUMA_OUT);
1195                 if (d_q_data->fmt->coplanar)
1196                         vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1197                                 VPE_CHAN_CHROMA_OUT);
1198         }
1199 
1200         if (ctx->deinterlacing)
1201                 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_OUT);
1202 
1203         enable_irqs(ctx);
1204 
1205         vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->desc_list.buf);
1206         vpdma_submit_descs(ctx->dev->vpdma, &ctx->desc_list);
1207 }
1208 
1209 static void dei_error(struct vpe_ctx *ctx)
1210 {
1211         dev_warn(ctx->dev->v4l2_dev.dev,
1212                 "received DEI error interrupt\n");
1213 }
1214 
1215 static void ds1_uv_error(struct vpe_ctx *ctx)
1216 {
1217         dev_warn(ctx->dev->v4l2_dev.dev,
1218                 "received downsampler error interrupt\n");
1219 }
1220 
1221 static irqreturn_t vpe_irq(int irq_vpe, void *data)
1222 {
1223         struct vpe_dev *dev = (struct vpe_dev *)data;
1224         struct vpe_ctx *ctx;
1225         struct vpe_q_data *d_q_data;
1226         struct vb2_v4l2_buffer *s_vb, *d_vb;
1227         unsigned long flags;
1228         u32 irqst0, irqst1;
1229 
1230         irqst0 = read_reg(dev, VPE_INT0_STATUS0);
1231         if (irqst0) {
1232                 write_reg(dev, VPE_INT0_STATUS0_CLR, irqst0);
1233                 vpe_dbg(dev, "INT0_STATUS0 = 0x%08x\n", irqst0);
1234         }
1235 
1236         irqst1 = read_reg(dev, VPE_INT0_STATUS1);
1237         if (irqst1) {
1238                 write_reg(dev, VPE_INT0_STATUS1_CLR, irqst1);
1239                 vpe_dbg(dev, "INT0_STATUS1 = 0x%08x\n", irqst1);
1240         }
1241 
1242         ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
1243         if (!ctx) {
1244                 vpe_err(dev, "instance released before end of transaction\n");
1245                 goto handled;
1246         }
1247 
1248         if (irqst1) {
1249                 if (irqst1 & VPE_DEI_ERROR_INT) {
1250                         irqst1 &= ~VPE_DEI_ERROR_INT;
1251                         dei_error(ctx);
1252                 }
1253                 if (irqst1 & VPE_DS1_UV_ERROR_INT) {
1254                         irqst1 &= ~VPE_DS1_UV_ERROR_INT;
1255                         ds1_uv_error(ctx);
1256                 }
1257         }
1258 
1259         if (irqst0) {
1260                 if (irqst0 & VPE_INT0_LIST0_COMPLETE)
1261                         vpdma_clear_list_stat(ctx->dev->vpdma);
1262 
1263                 irqst0 &= ~(VPE_INT0_LIST0_COMPLETE);
1264         }
1265 
1266         if (irqst0 | irqst1) {
1267                 dev_warn(dev->v4l2_dev.dev, "Unexpected interrupt: "
1268                         "INT0_STATUS0 = 0x%08x, INT0_STATUS1 = 0x%08x\n",
1269                         irqst0, irqst1);
1270         }
1271 
1272         disable_irqs(ctx);
1273 
1274         vpdma_unmap_desc_buf(dev->vpdma, &ctx->desc_list.buf);
1275         vpdma_unmap_desc_buf(dev->vpdma, &ctx->mmr_adb);
1276         vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_h);
1277         vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_v);
1278 
1279         vpdma_reset_desc_list(&ctx->desc_list);
1280 
1281          /* the previous dst mv buffer becomes the next src mv buffer */
1282         ctx->src_mv_buf_selector = !ctx->src_mv_buf_selector;
1283 
1284         if (ctx->aborting)
1285                 goto finished;
1286 
1287         s_vb = ctx->src_vbs[0];
1288         d_vb = ctx->dst_vb;
1289 
1290         d_vb->flags = s_vb->flags;
1291         d_vb->vb2_buf.timestamp = s_vb->vb2_buf.timestamp;
1292 
1293         if (s_vb->flags & V4L2_BUF_FLAG_TIMECODE)
1294                 d_vb->timecode = s_vb->timecode;
1295 
1296         d_vb->sequence = ctx->sequence;
1297 
1298         d_q_data = &ctx->q_data[Q_DATA_DST];
1299         if (d_q_data->flags & Q_DATA_INTERLACED) {
1300                 d_vb->field = ctx->field;
1301                 if (ctx->field == V4L2_FIELD_BOTTOM) {
1302                         ctx->sequence++;
1303                         ctx->field = V4L2_FIELD_TOP;
1304                 } else {
1305                         WARN_ON(ctx->field != V4L2_FIELD_TOP);
1306                         ctx->field = V4L2_FIELD_BOTTOM;
1307                 }
1308         } else {
1309                 d_vb->field = V4L2_FIELD_NONE;
1310                 ctx->sequence++;
1311         }
1312 
1313         if (ctx->deinterlacing)
1314                 s_vb = ctx->src_vbs[2];
1315 
1316         spin_lock_irqsave(&dev->lock, flags);
1317         v4l2_m2m_buf_done(s_vb, VB2_BUF_STATE_DONE);
1318         v4l2_m2m_buf_done(d_vb, VB2_BUF_STATE_DONE);
1319         spin_unlock_irqrestore(&dev->lock, flags);
1320 
1321         if (ctx->deinterlacing) {
1322                 ctx->src_vbs[2] = ctx->src_vbs[1];
1323                 ctx->src_vbs[1] = ctx->src_vbs[0];
1324         }
1325 
1326         ctx->bufs_completed++;
1327         if (ctx->bufs_completed < ctx->bufs_per_job) {
1328                 device_run(ctx);
1329                 goto handled;
1330         }
1331 
1332 finished:
1333         vpe_dbg(ctx->dev, "finishing transaction\n");
1334         ctx->bufs_completed = 0;
1335         v4l2_m2m_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx);
1336 handled:
1337         return IRQ_HANDLED;
1338 }
1339 
1340 /*
1341  * video ioctls
1342  */
1343 static int vpe_querycap(struct file *file, void *priv,
1344                         struct v4l2_capability *cap)
1345 {
1346         strncpy(cap->driver, VPE_MODULE_NAME, sizeof(cap->driver) - 1);
1347         strncpy(cap->card, VPE_MODULE_NAME, sizeof(cap->card) - 1);
1348         snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
1349                 VPE_MODULE_NAME);
1350         cap->device_caps  = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING;
1351         cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
1352         return 0;
1353 }
1354 
1355 static int __enum_fmt(struct v4l2_fmtdesc *f, u32 type)
1356 {
1357         int i, index;
1358         struct vpe_fmt *fmt = NULL;
1359 
1360         index = 0;
1361         for (i = 0; i < ARRAY_SIZE(vpe_formats); ++i) {
1362                 if (vpe_formats[i].types & type) {
1363                         if (index == f->index) {
1364                                 fmt = &vpe_formats[i];
1365                                 break;
1366                         }
1367                         index++;
1368                 }
1369         }
1370 
1371         if (!fmt)
1372                 return -EINVAL;
1373 
1374         strncpy(f->description, fmt->name, sizeof(f->description) - 1);
1375         f->pixelformat = fmt->fourcc;
1376         return 0;
1377 }
1378 
1379 static int vpe_enum_fmt(struct file *file, void *priv,
1380                                 struct v4l2_fmtdesc *f)
1381 {
1382         if (V4L2_TYPE_IS_OUTPUT(f->type))
1383                 return __enum_fmt(f, VPE_FMT_TYPE_OUTPUT);
1384 
1385         return __enum_fmt(f, VPE_FMT_TYPE_CAPTURE);
1386 }
1387 
1388 static int vpe_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
1389 {
1390         struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1391         struct vpe_ctx *ctx = file2ctx(file);
1392         struct vb2_queue *vq;
1393         struct vpe_q_data *q_data;
1394         int i;
1395 
1396         vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
1397         if (!vq)
1398                 return -EINVAL;
1399 
1400         q_data = get_q_data(ctx, f->type);
1401 
1402         pix->width = q_data->width;
1403         pix->height = q_data->height;
1404         pix->pixelformat = q_data->fmt->fourcc;
1405         pix->field = q_data->field;
1406 
1407         if (V4L2_TYPE_IS_OUTPUT(f->type)) {
1408                 pix->colorspace = q_data->colorspace;
1409         } else {
1410                 struct vpe_q_data *s_q_data;
1411 
1412                 /* get colorspace from the source queue */
1413                 s_q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
1414 
1415                 pix->colorspace = s_q_data->colorspace;
1416         }
1417 
1418         pix->num_planes = q_data->fmt->coplanar ? 2 : 1;
1419 
1420         for (i = 0; i < pix->num_planes; i++) {
1421                 pix->plane_fmt[i].bytesperline = q_data->bytesperline[i];
1422                 pix->plane_fmt[i].sizeimage = q_data->sizeimage[i];
1423         }
1424 
1425         return 0;
1426 }
1427 
1428 static int __vpe_try_fmt(struct vpe_ctx *ctx, struct v4l2_format *f,
1429                        struct vpe_fmt *fmt, int type)
1430 {
1431         struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1432         struct v4l2_plane_pix_format *plane_fmt;
1433         unsigned int w_align;
1434         int i, depth, depth_bytes;
1435 
1436         if (!fmt || !(fmt->types & type)) {
1437                 vpe_err(ctx->dev, "Fourcc format (0x%08x) invalid.\n",
1438                         pix->pixelformat);
1439                 return -EINVAL;
1440         }
1441 
1442         if (pix->field != V4L2_FIELD_NONE && pix->field != V4L2_FIELD_ALTERNATE)
1443                 pix->field = V4L2_FIELD_NONE;
1444 
1445         depth = fmt->vpdma_fmt[VPE_LUMA]->depth;
1446 
1447         /*
1448          * the line stride should 16 byte aligned for VPDMA to work, based on
1449          * the bytes per pixel, figure out how much the width should be aligned
1450          * to make sure line stride is 16 byte aligned
1451          */
1452         depth_bytes = depth >> 3;
1453 
1454         if (depth_bytes == 3)
1455                 /*
1456                  * if bpp is 3(as in some RGB formats), the pixel width doesn't
1457                  * really help in ensuring line stride is 16 byte aligned
1458                  */
1459                 w_align = 4;
1460         else
1461                 /*
1462                  * for the remainder bpp(4, 2 and 1), the pixel width alignment
1463                  * can ensure a line stride alignment of 16 bytes. For example,
1464                  * if bpp is 2, then the line stride can be 16 byte aligned if
1465                  * the width is 8 byte aligned
1466                  */
1467                 w_align = order_base_2(VPDMA_DESC_ALIGN / depth_bytes);
1468 
1469         v4l_bound_align_image(&pix->width, MIN_W, MAX_W, w_align,
1470                               &pix->height, MIN_H, MAX_H, H_ALIGN,
1471                               S_ALIGN);
1472 
1473         pix->num_planes = fmt->coplanar ? 2 : 1;
1474         pix->pixelformat = fmt->fourcc;
1475 
1476         if (!pix->colorspace) {
1477                 if (fmt->fourcc == V4L2_PIX_FMT_RGB24 ||
1478                                 fmt->fourcc == V4L2_PIX_FMT_BGR24 ||
1479                                 fmt->fourcc == V4L2_PIX_FMT_RGB32 ||
1480                                 fmt->fourcc == V4L2_PIX_FMT_BGR32) {
1481                         pix->colorspace = V4L2_COLORSPACE_SRGB;
1482                 } else {
1483                         if (pix->height > 1280) /* HD */
1484                                 pix->colorspace = V4L2_COLORSPACE_REC709;
1485                         else                    /* SD */
1486                                 pix->colorspace = V4L2_COLORSPACE_SMPTE170M;
1487                 }
1488         }
1489 
1490         memset(pix->reserved, 0, sizeof(pix->reserved));
1491         for (i = 0; i < pix->num_planes; i++) {
1492                 plane_fmt = &pix->plane_fmt[i];
1493                 depth = fmt->vpdma_fmt[i]->depth;
1494 
1495                 if (i == VPE_LUMA)
1496                         plane_fmt->bytesperline = (pix->width * depth) >> 3;
1497                 else
1498                         plane_fmt->bytesperline = pix->width;
1499 
1500                 plane_fmt->sizeimage =
1501                                 (pix->height * pix->width * depth) >> 3;
1502 
1503                 memset(plane_fmt->reserved, 0, sizeof(plane_fmt->reserved));
1504         }
1505 
1506         return 0;
1507 }
1508 
1509 static int vpe_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
1510 {
1511         struct vpe_ctx *ctx = file2ctx(file);
1512         struct vpe_fmt *fmt = find_format(f);
1513 
1514         if (V4L2_TYPE_IS_OUTPUT(f->type))
1515                 return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_OUTPUT);
1516         else
1517                 return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_CAPTURE);
1518 }
1519 
1520 static int __vpe_s_fmt(struct vpe_ctx *ctx, struct v4l2_format *f)
1521 {
1522         struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1523         struct v4l2_plane_pix_format *plane_fmt;
1524         struct vpe_q_data *q_data;
1525         struct vb2_queue *vq;
1526         int i;
1527 
1528         vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
1529         if (!vq)
1530                 return -EINVAL;
1531 
1532         if (vb2_is_busy(vq)) {
1533                 vpe_err(ctx->dev, "queue busy\n");
1534                 return -EBUSY;
1535         }
1536 
1537         q_data = get_q_data(ctx, f->type);
1538         if (!q_data)
1539                 return -EINVAL;
1540 
1541         q_data->fmt             = find_format(f);
1542         q_data->width           = pix->width;
1543         q_data->height          = pix->height;
1544         q_data->colorspace      = pix->colorspace;
1545         q_data->field           = pix->field;
1546 
1547         for (i = 0; i < pix->num_planes; i++) {
1548                 plane_fmt = &pix->plane_fmt[i];
1549 
1550                 q_data->bytesperline[i] = plane_fmt->bytesperline;
1551                 q_data->sizeimage[i]    = plane_fmt->sizeimage;
1552         }
1553 
1554         q_data->c_rect.left     = 0;
1555         q_data->c_rect.top      = 0;
1556         q_data->c_rect.width    = q_data->width;
1557         q_data->c_rect.height   = q_data->height;
1558 
1559         if (q_data->field == V4L2_FIELD_ALTERNATE)
1560                 q_data->flags |= Q_DATA_INTERLACED;
1561         else
1562                 q_data->flags &= ~Q_DATA_INTERLACED;
1563 
1564         vpe_dbg(ctx->dev, "Setting format for type %d, wxh: %dx%d, fmt: %d bpl_y %d",
1565                 f->type, q_data->width, q_data->height, q_data->fmt->fourcc,
1566                 q_data->bytesperline[VPE_LUMA]);
1567         if (q_data->fmt->coplanar)
1568                 vpe_dbg(ctx->dev, " bpl_uv %d\n",
1569                         q_data->bytesperline[VPE_CHROMA]);
1570 
1571         return 0;
1572 }
1573 
1574 static int vpe_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
1575 {
1576         int ret;
1577         struct vpe_ctx *ctx = file2ctx(file);
1578 
1579         ret = vpe_try_fmt(file, priv, f);
1580         if (ret)
1581                 return ret;
1582 
1583         ret = __vpe_s_fmt(ctx, f);
1584         if (ret)
1585                 return ret;
1586 
1587         if (V4L2_TYPE_IS_OUTPUT(f->type))
1588                 set_src_registers(ctx);
1589         else
1590                 set_dst_registers(ctx);
1591 
1592         return set_srcdst_params(ctx);
1593 }
1594 
1595 static int __vpe_try_selection(struct vpe_ctx *ctx, struct v4l2_selection *s)
1596 {
1597         struct vpe_q_data *q_data;
1598 
1599         if ((s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
1600             (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT))
1601                 return -EINVAL;
1602 
1603         q_data = get_q_data(ctx, s->type);
1604         if (!q_data)
1605                 return -EINVAL;
1606 
1607         switch (s->target) {
1608         case V4L2_SEL_TGT_COMPOSE:
1609                 /*
1610                  * COMPOSE target is only valid for capture buffer type, return
1611                  * error for output buffer type
1612                  */
1613                 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1614                         return -EINVAL;
1615                 break;
1616         case V4L2_SEL_TGT_CROP:
1617                 /*
1618                  * CROP target is only valid for output buffer type, return
1619                  * error for capture buffer type
1620                  */
1621                 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1622                         return -EINVAL;
1623                 break;
1624         /*
1625          * bound and default crop/compose targets are invalid targets to
1626          * try/set
1627          */
1628         default:
1629                 return -EINVAL;
1630         }
1631 
1632         if (s->r.top < 0 || s->r.left < 0) {
1633                 vpe_err(ctx->dev, "negative values for top and left\n");
1634                 s->r.top = s->r.left = 0;
1635         }
1636 
1637         v4l_bound_align_image(&s->r.width, MIN_W, q_data->width, 1,
1638                 &s->r.height, MIN_H, q_data->height, H_ALIGN, S_ALIGN);
1639 
1640         /* adjust left/top if cropping rectangle is out of bounds */
1641         if (s->r.left + s->r.width > q_data->width)
1642                 s->r.left = q_data->width - s->r.width;
1643         if (s->r.top + s->r.height > q_data->height)
1644                 s->r.top = q_data->height - s->r.height;
1645 
1646         return 0;
1647 }
1648 
1649 static int vpe_g_selection(struct file *file, void *fh,
1650                 struct v4l2_selection *s)
1651 {
1652         struct vpe_ctx *ctx = file2ctx(file);
1653         struct vpe_q_data *q_data;
1654         bool use_c_rect = false;
1655 
1656         if ((s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
1657             (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT))
1658                 return -EINVAL;
1659 
1660         q_data = get_q_data(ctx, s->type);
1661         if (!q_data)
1662                 return -EINVAL;
1663 
1664         switch (s->target) {
1665         case V4L2_SEL_TGT_COMPOSE_DEFAULT:
1666         case V4L2_SEL_TGT_COMPOSE_BOUNDS:
1667                 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1668                         return -EINVAL;
1669                 break;
1670         case V4L2_SEL_TGT_CROP_BOUNDS:
1671         case V4L2_SEL_TGT_CROP_DEFAULT:
1672                 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1673                         return -EINVAL;
1674                 break;
1675         case V4L2_SEL_TGT_COMPOSE:
1676                 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1677                         return -EINVAL;
1678                 use_c_rect = true;
1679                 break;
1680         case V4L2_SEL_TGT_CROP:
1681                 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1682                         return -EINVAL;
1683                 use_c_rect = true;
1684                 break;
1685         default:
1686                 return -EINVAL;
1687         }
1688 
1689         if (use_c_rect) {
1690                 /*
1691                  * for CROP/COMPOSE target type, return c_rect params from the
1692                  * respective buffer type
1693                  */
1694                 s->r = q_data->c_rect;
1695         } else {
1696                 /*
1697                  * for DEFAULT/BOUNDS target type, return width and height from
1698                  * S_FMT of the respective buffer type
1699                  */
1700                 s->r.left = 0;
1701                 s->r.top = 0;
1702                 s->r.width = q_data->width;
1703                 s->r.height = q_data->height;
1704         }
1705 
1706         return 0;
1707 }
1708 
1709 
1710 static int vpe_s_selection(struct file *file, void *fh,
1711                 struct v4l2_selection *s)
1712 {
1713         struct vpe_ctx *ctx = file2ctx(file);
1714         struct vpe_q_data *q_data;
1715         struct v4l2_selection sel = *s;
1716         int ret;
1717 
1718         ret = __vpe_try_selection(ctx, &sel);
1719         if (ret)
1720                 return ret;
1721 
1722         q_data = get_q_data(ctx, sel.type);
1723         if (!q_data)
1724                 return -EINVAL;
1725 
1726         if ((q_data->c_rect.left == sel.r.left) &&
1727                         (q_data->c_rect.top == sel.r.top) &&
1728                         (q_data->c_rect.width == sel.r.width) &&
1729                         (q_data->c_rect.height == sel.r.height)) {
1730                 vpe_dbg(ctx->dev,
1731                         "requested crop/compose values are already set\n");
1732                 return 0;
1733         }
1734 
1735         q_data->c_rect = sel.r;
1736 
1737         return set_srcdst_params(ctx);
1738 }
1739 
1740 /*
1741  * defines number of buffers/frames a context can process with VPE before
1742  * switching to a different context. default value is 1 buffer per context
1743  */
1744 #define V4L2_CID_VPE_BUFS_PER_JOB               (V4L2_CID_USER_TI_VPE_BASE + 0)
1745 
1746 static int vpe_s_ctrl(struct v4l2_ctrl *ctrl)
1747 {
1748         struct vpe_ctx *ctx =
1749                 container_of(ctrl->handler, struct vpe_ctx, hdl);
1750 
1751         switch (ctrl->id) {
1752         case V4L2_CID_VPE_BUFS_PER_JOB:
1753                 ctx->bufs_per_job = ctrl->val;
1754                 break;
1755 
1756         default:
1757                 vpe_err(ctx->dev, "Invalid control\n");
1758                 return -EINVAL;
1759         }
1760 
1761         return 0;
1762 }
1763 
1764 static const struct v4l2_ctrl_ops vpe_ctrl_ops = {
1765         .s_ctrl = vpe_s_ctrl,
1766 };
1767 
1768 static const struct v4l2_ioctl_ops vpe_ioctl_ops = {
1769         .vidioc_querycap                = vpe_querycap,
1770 
1771         .vidioc_enum_fmt_vid_cap_mplane = vpe_enum_fmt,
1772         .vidioc_g_fmt_vid_cap_mplane    = vpe_g_fmt,
1773         .vidioc_try_fmt_vid_cap_mplane  = vpe_try_fmt,
1774         .vidioc_s_fmt_vid_cap_mplane    = vpe_s_fmt,
1775 
1776         .vidioc_enum_fmt_vid_out_mplane = vpe_enum_fmt,
1777         .vidioc_g_fmt_vid_out_mplane    = vpe_g_fmt,
1778         .vidioc_try_fmt_vid_out_mplane  = vpe_try_fmt,
1779         .vidioc_s_fmt_vid_out_mplane    = vpe_s_fmt,
1780 
1781         .vidioc_g_selection             = vpe_g_selection,
1782         .vidioc_s_selection             = vpe_s_selection,
1783 
1784         .vidioc_reqbufs                 = v4l2_m2m_ioctl_reqbufs,
1785         .vidioc_querybuf                = v4l2_m2m_ioctl_querybuf,
1786         .vidioc_qbuf                    = v4l2_m2m_ioctl_qbuf,
1787         .vidioc_dqbuf                   = v4l2_m2m_ioctl_dqbuf,
1788         .vidioc_streamon                = v4l2_m2m_ioctl_streamon,
1789         .vidioc_streamoff               = v4l2_m2m_ioctl_streamoff,
1790 
1791         .vidioc_subscribe_event         = v4l2_ctrl_subscribe_event,
1792         .vidioc_unsubscribe_event       = v4l2_event_unsubscribe,
1793 };
1794 
1795 /*
1796  * Queue operations
1797  */
1798 static int vpe_queue_setup(struct vb2_queue *vq,
1799                            unsigned int *nbuffers, unsigned int *nplanes,
1800                            unsigned int sizes[], void *alloc_ctxs[])
1801 {
1802         int i;
1803         struct vpe_ctx *ctx = vb2_get_drv_priv(vq);
1804         struct vpe_q_data *q_data;
1805 
1806         q_data = get_q_data(ctx, vq->type);
1807 
1808         *nplanes = q_data->fmt->coplanar ? 2 : 1;
1809 
1810         for (i = 0; i < *nplanes; i++) {
1811                 sizes[i] = q_data->sizeimage[i];
1812                 alloc_ctxs[i] = ctx->dev->alloc_ctx;
1813         }
1814 
1815         vpe_dbg(ctx->dev, "get %d buffer(s) of size %d", *nbuffers,
1816                 sizes[VPE_LUMA]);
1817         if (q_data->fmt->coplanar)
1818                 vpe_dbg(ctx->dev, " and %d\n", sizes[VPE_CHROMA]);
1819 
1820         return 0;
1821 }
1822 
1823 static int vpe_buf_prepare(struct vb2_buffer *vb)
1824 {
1825         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1826         struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1827         struct vpe_q_data *q_data;
1828         int i, num_planes;
1829 
1830         vpe_dbg(ctx->dev, "type: %d\n", vb->vb2_queue->type);
1831 
1832         q_data = get_q_data(ctx, vb->vb2_queue->type);
1833         num_planes = q_data->fmt->coplanar ? 2 : 1;
1834 
1835         if (vb->vb2_queue->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1836                 if (!(q_data->flags & Q_DATA_INTERLACED)) {
1837                         vbuf->field = V4L2_FIELD_NONE;
1838                 } else {
1839                         if (vbuf->field != V4L2_FIELD_TOP &&
1840                                         vbuf->field != V4L2_FIELD_BOTTOM)
1841                                 return -EINVAL;
1842                 }
1843         }
1844 
1845         for (i = 0; i < num_planes; i++) {
1846                 if (vb2_plane_size(vb, i) < q_data->sizeimage[i]) {
1847                         vpe_err(ctx->dev,
1848                                 "data will not fit into plane (%lu < %lu)\n",
1849                                 vb2_plane_size(vb, i),
1850                                 (long) q_data->sizeimage[i]);
1851                         return -EINVAL;
1852                 }
1853         }
1854 
1855         for (i = 0; i < num_planes; i++)
1856                 vb2_set_plane_payload(vb, i, q_data->sizeimage[i]);
1857 
1858         return 0;
1859 }
1860 
1861 static void vpe_buf_queue(struct vb2_buffer *vb)
1862 {
1863         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1864         struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1865 
1866         v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
1867 }
1868 
1869 static int vpe_start_streaming(struct vb2_queue *q, unsigned int count)
1870 {
1871         /* currently we do nothing here */
1872 
1873         return 0;
1874 }
1875 
1876 static void vpe_stop_streaming(struct vb2_queue *q)
1877 {
1878         struct vpe_ctx *ctx = vb2_get_drv_priv(q);
1879 
1880         vpe_dump_regs(ctx->dev);
1881         vpdma_dump_regs(ctx->dev->vpdma);
1882 }
1883 
1884 static struct vb2_ops vpe_qops = {
1885         .queue_setup     = vpe_queue_setup,
1886         .buf_prepare     = vpe_buf_prepare,
1887         .buf_queue       = vpe_buf_queue,
1888         .wait_prepare    = vb2_ops_wait_prepare,
1889         .wait_finish     = vb2_ops_wait_finish,
1890         .start_streaming = vpe_start_streaming,
1891         .stop_streaming  = vpe_stop_streaming,
1892 };
1893 
1894 static int queue_init(void *priv, struct vb2_queue *src_vq,
1895                       struct vb2_queue *dst_vq)
1896 {
1897         struct vpe_ctx *ctx = priv;
1898         struct vpe_dev *dev = ctx->dev;
1899         int ret;
1900 
1901         memset(src_vq, 0, sizeof(*src_vq));
1902         src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
1903         src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
1904         src_vq->drv_priv = ctx;
1905         src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1906         src_vq->ops = &vpe_qops;
1907         src_vq->mem_ops = &vb2_dma_contig_memops;
1908         src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
1909         src_vq->lock = &dev->dev_mutex;
1910 
1911         ret = vb2_queue_init(src_vq);
1912         if (ret)
1913                 return ret;
1914 
1915         memset(dst_vq, 0, sizeof(*dst_vq));
1916         dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1917         dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
1918         dst_vq->drv_priv = ctx;
1919         dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1920         dst_vq->ops = &vpe_qops;
1921         dst_vq->mem_ops = &vb2_dma_contig_memops;
1922         dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
1923         dst_vq->lock = &dev->dev_mutex;
1924 
1925         return vb2_queue_init(dst_vq);
1926 }
1927 
1928 static const struct v4l2_ctrl_config vpe_bufs_per_job = {
1929         .ops = &vpe_ctrl_ops,
1930         .id = V4L2_CID_VPE_BUFS_PER_JOB,
1931         .name = "Buffers Per Transaction",
1932         .type = V4L2_CTRL_TYPE_INTEGER,
1933         .def = VPE_DEF_BUFS_PER_JOB,
1934         .min = 1,
1935         .max = VIDEO_MAX_FRAME,
1936         .step = 1,
1937 };
1938 
1939 /*
1940  * File operations
1941  */
1942 static int vpe_open(struct file *file)
1943 {
1944         struct vpe_dev *dev = video_drvdata(file);
1945         struct vpe_q_data *s_q_data;
1946         struct v4l2_ctrl_handler *hdl;
1947         struct vpe_ctx *ctx;
1948         int ret;
1949 
1950         vpe_dbg(dev, "vpe_open\n");
1951 
1952         ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
1953         if (!ctx)
1954                 return -ENOMEM;
1955 
1956         ctx->dev = dev;
1957 
1958         if (mutex_lock_interruptible(&dev->dev_mutex)) {
1959                 ret = -ERESTARTSYS;
1960                 goto free_ctx;
1961         }
1962 
1963         ret = vpdma_create_desc_list(&ctx->desc_list, VPE_DESC_LIST_SIZE,
1964                         VPDMA_LIST_TYPE_NORMAL);
1965         if (ret != 0)
1966                 goto unlock;
1967 
1968         ret = vpdma_alloc_desc_buf(&ctx->mmr_adb, sizeof(struct vpe_mmr_adb));
1969         if (ret != 0)
1970                 goto free_desc_list;
1971 
1972         ret = vpdma_alloc_desc_buf(&ctx->sc_coeff_h, SC_COEF_SRAM_SIZE);
1973         if (ret != 0)
1974                 goto free_mmr_adb;
1975 
1976         ret = vpdma_alloc_desc_buf(&ctx->sc_coeff_v, SC_COEF_SRAM_SIZE);
1977         if (ret != 0)
1978                 goto free_sc_h;
1979 
1980         init_adb_hdrs(ctx);
1981 
1982         v4l2_fh_init(&ctx->fh, video_devdata(file));
1983         file->private_data = &ctx->fh;
1984 
1985         hdl = &ctx->hdl;
1986         v4l2_ctrl_handler_init(hdl, 1);
1987         v4l2_ctrl_new_custom(hdl, &vpe_bufs_per_job, NULL);
1988         if (hdl->error) {
1989                 ret = hdl->error;
1990                 goto exit_fh;
1991         }
1992         ctx->fh.ctrl_handler = hdl;
1993         v4l2_ctrl_handler_setup(hdl);
1994 
1995         s_q_data = &ctx->q_data[Q_DATA_SRC];
1996         s_q_data->fmt = &vpe_formats[2];
1997         s_q_data->width = 1920;
1998         s_q_data->height = 1080;
1999         s_q_data->bytesperline[VPE_LUMA] = (s_q_data->width *
2000                         s_q_data->fmt->vpdma_fmt[VPE_LUMA]->depth) >> 3;
2001         s_q_data->sizeimage[VPE_LUMA] = (s_q_data->bytesperline[VPE_LUMA] *
2002                         s_q_data->height);
2003         s_q_data->colorspace = V4L2_COLORSPACE_REC709;
2004         s_q_data->field = V4L2_FIELD_NONE;
2005         s_q_data->c_rect.left = 0;
2006         s_q_data->c_rect.top = 0;
2007         s_q_data->c_rect.width = s_q_data->width;
2008         s_q_data->c_rect.height = s_q_data->height;
2009         s_q_data->flags = 0;
2010 
2011         ctx->q_data[Q_DATA_DST] = *s_q_data;
2012 
2013         set_dei_shadow_registers(ctx);
2014         set_src_registers(ctx);
2015         set_dst_registers(ctx);
2016         ret = set_srcdst_params(ctx);
2017         if (ret)
2018                 goto exit_fh;
2019 
2020         ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init);
2021 
2022         if (IS_ERR(ctx->fh.m2m_ctx)) {
2023                 ret = PTR_ERR(ctx->fh.m2m_ctx);
2024                 goto exit_fh;
2025         }
2026 
2027         v4l2_fh_add(&ctx->fh);
2028 
2029         /*
2030          * for now, just report the creation of the first instance, we can later
2031          * optimize the driver to enable or disable clocks when the first
2032          * instance is created or the last instance released
2033          */
2034         if (atomic_inc_return(&dev->num_instances) == 1)
2035                 vpe_dbg(dev, "first instance created\n");
2036 
2037         ctx->bufs_per_job = VPE_DEF_BUFS_PER_JOB;
2038 
2039         ctx->load_mmrs = true;
2040 
2041         vpe_dbg(dev, "created instance %p, m2m_ctx: %p\n",
2042                 ctx, ctx->fh.m2m_ctx);
2043 
2044         mutex_unlock(&dev->dev_mutex);
2045 
2046         return 0;
2047 exit_fh:
2048         v4l2_ctrl_handler_free(hdl);
2049         v4l2_fh_exit(&ctx->fh);
2050         vpdma_free_desc_buf(&ctx->sc_coeff_v);
2051 free_sc_h:
2052         vpdma_free_desc_buf(&ctx->sc_coeff_h);
2053 free_mmr_adb:
2054         vpdma_free_desc_buf(&ctx->mmr_adb);
2055 free_desc_list:
2056         vpdma_free_desc_list(&ctx->desc_list);
2057 unlock:
2058         mutex_unlock(&dev->dev_mutex);
2059 free_ctx:
2060         kfree(ctx);
2061         return ret;
2062 }
2063 
2064 static int vpe_release(struct file *file)
2065 {
2066         struct vpe_dev *dev = video_drvdata(file);
2067         struct vpe_ctx *ctx = file2ctx(file);
2068 
2069         vpe_dbg(dev, "releasing instance %p\n", ctx);
2070 
2071         mutex_lock(&dev->dev_mutex);
2072         free_vbs(ctx);
2073         free_mv_buffers(ctx);
2074         vpdma_free_desc_list(&ctx->desc_list);
2075         vpdma_free_desc_buf(&ctx->mmr_adb);
2076 
2077         v4l2_fh_del(&ctx->fh);
2078         v4l2_fh_exit(&ctx->fh);
2079         v4l2_ctrl_handler_free(&ctx->hdl);
2080         v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
2081 
2082         kfree(ctx);
2083 
2084         /*
2085          * for now, just report the release of the last instance, we can later
2086          * optimize the driver to enable or disable clocks when the first
2087          * instance is created or the last instance released
2088          */
2089         if (atomic_dec_return(&dev->num_instances) == 0)
2090                 vpe_dbg(dev, "last instance released\n");
2091 
2092         mutex_unlock(&dev->dev_mutex);
2093 
2094         return 0;
2095 }
2096 
2097 static const struct v4l2_file_operations vpe_fops = {
2098         .owner          = THIS_MODULE,
2099         .open           = vpe_open,
2100         .release        = vpe_release,
2101         .poll           = v4l2_m2m_fop_poll,
2102         .unlocked_ioctl = video_ioctl2,
2103         .mmap           = v4l2_m2m_fop_mmap,
2104 };
2105 
2106 static struct video_device vpe_videodev = {
2107         .name           = VPE_MODULE_NAME,
2108         .fops           = &vpe_fops,
2109         .ioctl_ops      = &vpe_ioctl_ops,
2110         .minor          = -1,
2111         .release        = video_device_release_empty,
2112         .vfl_dir        = VFL_DIR_M2M,
2113 };
2114 
2115 static struct v4l2_m2m_ops m2m_ops = {
2116         .device_run     = device_run,
2117         .job_ready      = job_ready,
2118         .job_abort      = job_abort,
2119         .lock           = vpe_lock,
2120         .unlock         = vpe_unlock,
2121 };
2122 
2123 static int vpe_runtime_get(struct platform_device *pdev)
2124 {
2125         int r;
2126 
2127         dev_dbg(&pdev->dev, "vpe_runtime_get\n");
2128 
2129         r = pm_runtime_get_sync(&pdev->dev);
2130         WARN_ON(r < 0);
2131         return r < 0 ? r : 0;
2132 }
2133 
2134 static void vpe_runtime_put(struct platform_device *pdev)
2135 {
2136 
2137         int r;
2138 
2139         dev_dbg(&pdev->dev, "vpe_runtime_put\n");
2140 
2141         r = pm_runtime_put_sync(&pdev->dev);
2142         WARN_ON(r < 0 && r != -ENOSYS);
2143 }
2144 
2145 static void vpe_fw_cb(struct platform_device *pdev)
2146 {
2147         struct vpe_dev *dev = platform_get_drvdata(pdev);
2148         struct video_device *vfd;
2149         int ret;
2150 
2151         vfd = &dev->vfd;
2152         *vfd = vpe_videodev;
2153         vfd->lock = &dev->dev_mutex;
2154         vfd->v4l2_dev = &dev->v4l2_dev;
2155 
2156         ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
2157         if (ret) {
2158                 vpe_err(dev, "Failed to register video device\n");
2159 
2160                 vpe_set_clock_enable(dev, 0);
2161                 vpe_runtime_put(pdev);
2162                 pm_runtime_disable(&pdev->dev);
2163                 v4l2_m2m_release(dev->m2m_dev);
2164                 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
2165                 v4l2_device_unregister(&dev->v4l2_dev);
2166 
2167                 return;
2168         }
2169 
2170         video_set_drvdata(vfd, dev);
2171         snprintf(vfd->name, sizeof(vfd->name), "%s", vpe_videodev.name);
2172         dev_info(dev->v4l2_dev.dev, "Device registered as /dev/video%d\n",
2173                 vfd->num);
2174 }
2175 
2176 static int vpe_probe(struct platform_device *pdev)
2177 {
2178         struct vpe_dev *dev;
2179         int ret, irq, func;
2180 
2181         dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
2182         if (!dev)
2183                 return -ENOMEM;
2184 
2185         spin_lock_init(&dev->lock);
2186 
2187         ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
2188         if (ret)
2189                 return ret;
2190 
2191         atomic_set(&dev->num_instances, 0);
2192         mutex_init(&dev->dev_mutex);
2193 
2194         dev->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2195                         "vpe_top");
2196         /*
2197          * HACK: we get resource info from device tree in the form of a list of
2198          * VPE sub blocks, the driver currently uses only the base of vpe_top
2199          * for register access, the driver should be changed later to access
2200          * registers based on the sub block base addresses
2201          */
2202         dev->base = devm_ioremap(&pdev->dev, dev->res->start, SZ_32K);
2203         if (!dev->base) {
2204                 ret = -ENOMEM;
2205                 goto v4l2_dev_unreg;
2206         }
2207 
2208         irq = platform_get_irq(pdev, 0);
2209         ret = devm_request_irq(&pdev->dev, irq, vpe_irq, 0, VPE_MODULE_NAME,
2210                         dev);
2211         if (ret)
2212                 goto v4l2_dev_unreg;
2213 
2214         platform_set_drvdata(pdev, dev);
2215 
2216         dev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
2217         if (IS_ERR(dev->alloc_ctx)) {
2218                 vpe_err(dev, "Failed to alloc vb2 context\n");
2219                 ret = PTR_ERR(dev->alloc_ctx);
2220                 goto v4l2_dev_unreg;
2221         }
2222 
2223         dev->m2m_dev = v4l2_m2m_init(&m2m_ops);
2224         if (IS_ERR(dev->m2m_dev)) {
2225                 vpe_err(dev, "Failed to init mem2mem device\n");
2226                 ret = PTR_ERR(dev->m2m_dev);
2227                 goto rel_ctx;
2228         }
2229 
2230         pm_runtime_enable(&pdev->dev);
2231 
2232         ret = vpe_runtime_get(pdev);
2233         if (ret)
2234                 goto rel_m2m;
2235 
2236         /* Perform clk enable followed by reset */
2237         vpe_set_clock_enable(dev, 1);
2238 
2239         vpe_top_reset(dev);
2240 
2241         func = read_field_reg(dev, VPE_PID, VPE_PID_FUNC_MASK,
2242                 VPE_PID_FUNC_SHIFT);
2243         vpe_dbg(dev, "VPE PID function %x\n", func);
2244 
2245         vpe_top_vpdma_reset(dev);
2246 
2247         dev->sc = sc_create(pdev);
2248         if (IS_ERR(dev->sc)) {
2249                 ret = PTR_ERR(dev->sc);
2250                 goto runtime_put;
2251         }
2252 
2253         dev->csc = csc_create(pdev);
2254         if (IS_ERR(dev->csc)) {
2255                 ret = PTR_ERR(dev->csc);
2256                 goto runtime_put;
2257         }
2258 
2259         dev->vpdma = vpdma_create(pdev, vpe_fw_cb);
2260         if (IS_ERR(dev->vpdma)) {
2261                 ret = PTR_ERR(dev->vpdma);
2262                 goto runtime_put;
2263         }
2264 
2265         return 0;
2266 
2267 runtime_put:
2268         vpe_runtime_put(pdev);
2269 rel_m2m:
2270         pm_runtime_disable(&pdev->dev);
2271         v4l2_m2m_release(dev->m2m_dev);
2272 rel_ctx:
2273         vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
2274 v4l2_dev_unreg:
2275         v4l2_device_unregister(&dev->v4l2_dev);
2276 
2277         return ret;
2278 }
2279 
2280 static int vpe_remove(struct platform_device *pdev)
2281 {
2282         struct vpe_dev *dev = platform_get_drvdata(pdev);
2283 
2284         v4l2_info(&dev->v4l2_dev, "Removing " VPE_MODULE_NAME);
2285 
2286         v4l2_m2m_release(dev->m2m_dev);
2287         video_unregister_device(&dev->vfd);
2288         v4l2_device_unregister(&dev->v4l2_dev);
2289         vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
2290 
2291         vpe_set_clock_enable(dev, 0);
2292         vpe_runtime_put(pdev);
2293         pm_runtime_disable(&pdev->dev);
2294 
2295         return 0;
2296 }
2297 
2298 #if defined(CONFIG_OF)
2299 static const struct of_device_id vpe_of_match[] = {
2300         {
2301                 .compatible = "ti,vpe",
2302         },
2303         {},
2304 };
2305 #endif
2306 
2307 static struct platform_driver vpe_pdrv = {
2308         .probe          = vpe_probe,
2309         .remove         = vpe_remove,
2310         .driver         = {
2311                 .name   = VPE_MODULE_NAME,
2312                 .of_match_table = of_match_ptr(vpe_of_match),
2313         },
2314 };
2315 
2316 module_platform_driver(vpe_pdrv);
2317 
2318 MODULE_DESCRIPTION("TI VPE driver");
2319 MODULE_AUTHOR("Dale Farnsworth, <dale@farnsworth.org>");
2320 MODULE_LICENSE("GPL");
2321 

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