Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/media/platform/ti-vpe/vpe.c

  1 /*
  2  * TI VPE mem2mem driver, based on the virtual v4l2-mem2mem example driver
  3  *
  4  * Copyright (c) 2013 Texas Instruments Inc.
  5  * David Griego, <dagriego@biglakesoftware.com>
  6  * Dale Farnsworth, <dale@farnsworth.org>
  7  * Archit Taneja, <archit@ti.com>
  8  *
  9  * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
 10  * Pawel Osciak, <pawel@osciak.com>
 11  * Marek Szyprowski, <m.szyprowski@samsung.com>
 12  *
 13  * Based on the virtual v4l2-mem2mem example device
 14  *
 15  * This program is free software; you can redistribute it and/or modify it
 16  * under the terms of the GNU General Public License version 2 as published by
 17  * the Free Software Foundation
 18  */
 19 
 20 #include <linux/delay.h>
 21 #include <linux/dma-mapping.h>
 22 #include <linux/err.h>
 23 #include <linux/fs.h>
 24 #include <linux/interrupt.h>
 25 #include <linux/io.h>
 26 #include <linux/ioctl.h>
 27 #include <linux/module.h>
 28 #include <linux/platform_device.h>
 29 #include <linux/pm_runtime.h>
 30 #include <linux/sched.h>
 31 #include <linux/slab.h>
 32 #include <linux/videodev2.h>
 33 #include <linux/log2.h>
 34 
 35 #include <media/v4l2-common.h>
 36 #include <media/v4l2-ctrls.h>
 37 #include <media/v4l2-device.h>
 38 #include <media/v4l2-event.h>
 39 #include <media/v4l2-ioctl.h>
 40 #include <media/v4l2-mem2mem.h>
 41 #include <media/videobuf2-core.h>
 42 #include <media/videobuf2-dma-contig.h>
 43 
 44 #include "vpdma.h"
 45 #include "vpe_regs.h"
 46 #include "sc.h"
 47 #include "csc.h"
 48 
 49 #define VPE_MODULE_NAME "vpe"
 50 
 51 /* minimum and maximum frame sizes */
 52 #define MIN_W           32
 53 #define MIN_H           32
 54 #define MAX_W           1920
 55 #define MAX_H           1080
 56 
 57 /* required alignments */
 58 #define S_ALIGN         0       /* multiple of 1 */
 59 #define H_ALIGN         1       /* multiple of 2 */
 60 
 61 /* flags that indicate a format can be used for capture/output */
 62 #define VPE_FMT_TYPE_CAPTURE    (1 << 0)
 63 #define VPE_FMT_TYPE_OUTPUT     (1 << 1)
 64 
 65 /* used as plane indices */
 66 #define VPE_MAX_PLANES  2
 67 #define VPE_LUMA        0
 68 #define VPE_CHROMA      1
 69 
 70 /* per m2m context info */
 71 #define VPE_MAX_SRC_BUFS        3       /* need 3 src fields to de-interlace */
 72 
 73 #define VPE_DEF_BUFS_PER_JOB    1       /* default one buffer per batch job */
 74 
 75 /*
 76  * each VPE context can need up to 3 config desciptors, 7 input descriptors,
 77  * 3 output descriptors, and 10 control descriptors
 78  */
 79 #define VPE_DESC_LIST_SIZE      (10 * VPDMA_DTD_DESC_SIZE +     \
 80                                         13 * VPDMA_CFD_CTD_DESC_SIZE)
 81 
 82 #define vpe_dbg(vpedev, fmt, arg...)    \
 83                 dev_dbg((vpedev)->v4l2_dev.dev, fmt, ##arg)
 84 #define vpe_err(vpedev, fmt, arg...)    \
 85                 dev_err((vpedev)->v4l2_dev.dev, fmt, ##arg)
 86 
 87 struct vpe_us_coeffs {
 88         unsigned short  anchor_fid0_c0;
 89         unsigned short  anchor_fid0_c1;
 90         unsigned short  anchor_fid0_c2;
 91         unsigned short  anchor_fid0_c3;
 92         unsigned short  interp_fid0_c0;
 93         unsigned short  interp_fid0_c1;
 94         unsigned short  interp_fid0_c2;
 95         unsigned short  interp_fid0_c3;
 96         unsigned short  anchor_fid1_c0;
 97         unsigned short  anchor_fid1_c1;
 98         unsigned short  anchor_fid1_c2;
 99         unsigned short  anchor_fid1_c3;
100         unsigned short  interp_fid1_c0;
101         unsigned short  interp_fid1_c1;
102         unsigned short  interp_fid1_c2;
103         unsigned short  interp_fid1_c3;
104 };
105 
106 /*
107  * Default upsampler coefficients
108  */
109 static const struct vpe_us_coeffs us_coeffs[] = {
110         {
111                 /* Coefficients for progressive input */
112                 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8,
113                 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8,
114         },
115         {
116                 /* Coefficients for Top Field Interlaced input */
117                 0x0051, 0x03D5, 0x3FE3, 0x3FF7, 0x3FB5, 0x02E9, 0x018F, 0x3FD3,
118                 /* Coefficients for Bottom Field Interlaced input */
119                 0x016B, 0x0247, 0x00B1, 0x3F9D, 0x3FCF, 0x03DB, 0x005D, 0x3FF9,
120         },
121 };
122 
123 /*
124  * the following registers are for configuring some of the parameters of the
125  * motion and edge detection blocks inside DEI, these generally remain the same,
126  * these could be passed later via userspace if some one needs to tweak these.
127  */
128 struct vpe_dei_regs {
129         unsigned long mdt_spacial_freq_thr_reg;         /* VPE_DEI_REG2 */
130         unsigned long edi_config_reg;                   /* VPE_DEI_REG3 */
131         unsigned long edi_lut_reg0;                     /* VPE_DEI_REG4 */
132         unsigned long edi_lut_reg1;                     /* VPE_DEI_REG5 */
133         unsigned long edi_lut_reg2;                     /* VPE_DEI_REG6 */
134         unsigned long edi_lut_reg3;                     /* VPE_DEI_REG7 */
135 };
136 
137 /*
138  * default expert DEI register values, unlikely to be modified.
139  */
140 static const struct vpe_dei_regs dei_regs = {
141         0x020C0804u,
142         0x0118100Fu,
143         0x08040200u,
144         0x1010100Cu,
145         0x10101010u,
146         0x10101010u,
147 };
148 
149 /*
150  * The port_data structure contains per-port data.
151  */
152 struct vpe_port_data {
153         enum vpdma_channel channel;     /* VPDMA channel */
154         u8      vb_index;               /* input frame f, f-1, f-2 index */
155         u8      vb_part;                /* plane index for co-panar formats */
156 };
157 
158 /*
159  * Define indices into the port_data tables
160  */
161 #define VPE_PORT_LUMA1_IN       0
162 #define VPE_PORT_CHROMA1_IN     1
163 #define VPE_PORT_LUMA2_IN       2
164 #define VPE_PORT_CHROMA2_IN     3
165 #define VPE_PORT_LUMA3_IN       4
166 #define VPE_PORT_CHROMA3_IN     5
167 #define VPE_PORT_MV_IN          6
168 #define VPE_PORT_MV_OUT         7
169 #define VPE_PORT_LUMA_OUT       8
170 #define VPE_PORT_CHROMA_OUT     9
171 #define VPE_PORT_RGB_OUT        10
172 
173 static const struct vpe_port_data port_data[11] = {
174         [VPE_PORT_LUMA1_IN] = {
175                 .channel        = VPE_CHAN_LUMA1_IN,
176                 .vb_index       = 0,
177                 .vb_part        = VPE_LUMA,
178         },
179         [VPE_PORT_CHROMA1_IN] = {
180                 .channel        = VPE_CHAN_CHROMA1_IN,
181                 .vb_index       = 0,
182                 .vb_part        = VPE_CHROMA,
183         },
184         [VPE_PORT_LUMA2_IN] = {
185                 .channel        = VPE_CHAN_LUMA2_IN,
186                 .vb_index       = 1,
187                 .vb_part        = VPE_LUMA,
188         },
189         [VPE_PORT_CHROMA2_IN] = {
190                 .channel        = VPE_CHAN_CHROMA2_IN,
191                 .vb_index       = 1,
192                 .vb_part        = VPE_CHROMA,
193         },
194         [VPE_PORT_LUMA3_IN] = {
195                 .channel        = VPE_CHAN_LUMA3_IN,
196                 .vb_index       = 2,
197                 .vb_part        = VPE_LUMA,
198         },
199         [VPE_PORT_CHROMA3_IN] = {
200                 .channel        = VPE_CHAN_CHROMA3_IN,
201                 .vb_index       = 2,
202                 .vb_part        = VPE_CHROMA,
203         },
204         [VPE_PORT_MV_IN] = {
205                 .channel        = VPE_CHAN_MV_IN,
206         },
207         [VPE_PORT_MV_OUT] = {
208                 .channel        = VPE_CHAN_MV_OUT,
209         },
210         [VPE_PORT_LUMA_OUT] = {
211                 .channel        = VPE_CHAN_LUMA_OUT,
212                 .vb_part        = VPE_LUMA,
213         },
214         [VPE_PORT_CHROMA_OUT] = {
215                 .channel        = VPE_CHAN_CHROMA_OUT,
216                 .vb_part        = VPE_CHROMA,
217         },
218         [VPE_PORT_RGB_OUT] = {
219                 .channel        = VPE_CHAN_RGB_OUT,
220                 .vb_part        = VPE_LUMA,
221         },
222 };
223 
224 
225 /* driver info for each of the supported video formats */
226 struct vpe_fmt {
227         char    *name;                  /* human-readable name */
228         u32     fourcc;                 /* standard format identifier */
229         u8      types;                  /* CAPTURE and/or OUTPUT */
230         u8      coplanar;               /* set for unpacked Luma and Chroma */
231         /* vpdma format info for each plane */
232         struct vpdma_data_format const *vpdma_fmt[VPE_MAX_PLANES];
233 };
234 
235 static struct vpe_fmt vpe_formats[] = {
236         {
237                 .name           = "YUV 422 co-planar",
238                 .fourcc         = V4L2_PIX_FMT_NV16,
239                 .types          = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
240                 .coplanar       = 1,
241                 .vpdma_fmt      = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y444],
242                                     &vpdma_yuv_fmts[VPDMA_DATA_FMT_C444],
243                                   },
244         },
245         {
246                 .name           = "YUV 420 co-planar",
247                 .fourcc         = V4L2_PIX_FMT_NV12,
248                 .types          = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
249                 .coplanar       = 1,
250                 .vpdma_fmt      = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y420],
251                                     &vpdma_yuv_fmts[VPDMA_DATA_FMT_C420],
252                                   },
253         },
254         {
255                 .name           = "YUYV 422 packed",
256                 .fourcc         = V4L2_PIX_FMT_YUYV,
257                 .types          = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
258                 .coplanar       = 0,
259                 .vpdma_fmt      = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_YC422],
260                                   },
261         },
262         {
263                 .name           = "UYVY 422 packed",
264                 .fourcc         = V4L2_PIX_FMT_UYVY,
265                 .types          = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
266                 .coplanar       = 0,
267                 .vpdma_fmt      = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_CY422],
268                                   },
269         },
270         {
271                 .name           = "RGB888 packed",
272                 .fourcc         = V4L2_PIX_FMT_RGB24,
273                 .types          = VPE_FMT_TYPE_CAPTURE,
274                 .coplanar       = 0,
275                 .vpdma_fmt      = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGB24],
276                                   },
277         },
278         {
279                 .name           = "ARGB32",
280                 .fourcc         = V4L2_PIX_FMT_RGB32,
281                 .types          = VPE_FMT_TYPE_CAPTURE,
282                 .coplanar       = 0,
283                 .vpdma_fmt      = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ARGB32],
284                                   },
285         },
286         {
287                 .name           = "BGR888 packed",
288                 .fourcc         = V4L2_PIX_FMT_BGR24,
289                 .types          = VPE_FMT_TYPE_CAPTURE,
290                 .coplanar       = 0,
291                 .vpdma_fmt      = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_BGR24],
292                                   },
293         },
294         {
295                 .name           = "ABGR32",
296                 .fourcc         = V4L2_PIX_FMT_BGR32,
297                 .types          = VPE_FMT_TYPE_CAPTURE,
298                 .coplanar       = 0,
299                 .vpdma_fmt      = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ABGR32],
300                                   },
301         },
302 };
303 
304 /*
305  * per-queue, driver-specific private data.
306  * there is one source queue and one destination queue for each m2m context.
307  */
308 struct vpe_q_data {
309         unsigned int            width;                          /* frame width */
310         unsigned int            height;                         /* frame height */
311         unsigned int            bytesperline[VPE_MAX_PLANES];   /* bytes per line in memory */
312         enum v4l2_colorspace    colorspace;
313         enum v4l2_field         field;                          /* supported field value */
314         unsigned int            flags;
315         unsigned int            sizeimage[VPE_MAX_PLANES];      /* image size in memory */
316         struct v4l2_rect        c_rect;                         /* crop/compose rectangle */
317         struct vpe_fmt          *fmt;                           /* format info */
318 };
319 
320 /* vpe_q_data flag bits */
321 #define Q_DATA_FRAME_1D         (1 << 0)
322 #define Q_DATA_MODE_TILED       (1 << 1)
323 #define Q_DATA_INTERLACED       (1 << 2)
324 
325 enum {
326         Q_DATA_SRC = 0,
327         Q_DATA_DST = 1,
328 };
329 
330 /* find our format description corresponding to the passed v4l2_format */
331 static struct vpe_fmt *find_format(struct v4l2_format *f)
332 {
333         struct vpe_fmt *fmt;
334         unsigned int k;
335 
336         for (k = 0; k < ARRAY_SIZE(vpe_formats); k++) {
337                 fmt = &vpe_formats[k];
338                 if (fmt->fourcc == f->fmt.pix.pixelformat)
339                         return fmt;
340         }
341 
342         return NULL;
343 }
344 
345 /*
346  * there is one vpe_dev structure in the driver, it is shared by
347  * all instances.
348  */
349 struct vpe_dev {
350         struct v4l2_device      v4l2_dev;
351         struct video_device     vfd;
352         struct v4l2_m2m_dev     *m2m_dev;
353 
354         atomic_t                num_instances;  /* count of driver instances */
355         dma_addr_t              loaded_mmrs;    /* shadow mmrs in device */
356         struct mutex            dev_mutex;
357         spinlock_t              lock;
358 
359         int                     irq;
360         void __iomem            *base;
361         struct resource         *res;
362 
363         struct vb2_alloc_ctx    *alloc_ctx;
364         struct vpdma_data       *vpdma;         /* vpdma data handle */
365         struct sc_data          *sc;            /* scaler data handle */
366         struct csc_data         *csc;           /* csc data handle */
367 };
368 
369 /*
370  * There is one vpe_ctx structure for each m2m context.
371  */
372 struct vpe_ctx {
373         struct v4l2_fh          fh;
374         struct vpe_dev          *dev;
375         struct v4l2_m2m_ctx     *m2m_ctx;
376         struct v4l2_ctrl_handler hdl;
377 
378         unsigned int            field;                  /* current field */
379         unsigned int            sequence;               /* current frame/field seq */
380         unsigned int            aborting;               /* abort after next irq */
381 
382         unsigned int            bufs_per_job;           /* input buffers per batch */
383         unsigned int            bufs_completed;         /* bufs done in this batch */
384 
385         struct vpe_q_data       q_data[2];              /* src & dst queue data */
386         struct vb2_buffer       *src_vbs[VPE_MAX_SRC_BUFS];
387         struct vb2_buffer       *dst_vb;
388 
389         dma_addr_t              mv_buf_dma[2];          /* dma addrs of motion vector in/out bufs */
390         void                    *mv_buf[2];             /* virtual addrs of motion vector bufs */
391         size_t                  mv_buf_size;            /* current motion vector buffer size */
392         struct vpdma_buf        mmr_adb;                /* shadow reg addr/data block */
393         struct vpdma_buf        sc_coeff_h;             /* h coeff buffer */
394         struct vpdma_buf        sc_coeff_v;             /* v coeff buffer */
395         struct vpdma_desc_list  desc_list;              /* DMA descriptor list */
396 
397         bool                    deinterlacing;          /* using de-interlacer */
398         bool                    load_mmrs;              /* have new shadow reg values */
399 
400         unsigned int            src_mv_buf_selector;
401 };
402 
403 
404 /*
405  * M2M devices get 2 queues.
406  * Return the queue given the type.
407  */
408 static struct vpe_q_data *get_q_data(struct vpe_ctx *ctx,
409                                      enum v4l2_buf_type type)
410 {
411         switch (type) {
412         case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE:
413         case V4L2_BUF_TYPE_VIDEO_OUTPUT:
414                 return &ctx->q_data[Q_DATA_SRC];
415         case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE:
416         case V4L2_BUF_TYPE_VIDEO_CAPTURE:
417                 return &ctx->q_data[Q_DATA_DST];
418         default:
419                 BUG();
420         }
421         return NULL;
422 }
423 
424 static u32 read_reg(struct vpe_dev *dev, int offset)
425 {
426         return ioread32(dev->base + offset);
427 }
428 
429 static void write_reg(struct vpe_dev *dev, int offset, u32 value)
430 {
431         iowrite32(value, dev->base + offset);
432 }
433 
434 /* register field read/write helpers */
435 static int get_field(u32 value, u32 mask, int shift)
436 {
437         return (value & (mask << shift)) >> shift;
438 }
439 
440 static int read_field_reg(struct vpe_dev *dev, int offset, u32 mask, int shift)
441 {
442         return get_field(read_reg(dev, offset), mask, shift);
443 }
444 
445 static void write_field(u32 *valp, u32 field, u32 mask, int shift)
446 {
447         u32 val = *valp;
448 
449         val &= ~(mask << shift);
450         val |= (field & mask) << shift;
451         *valp = val;
452 }
453 
454 static void write_field_reg(struct vpe_dev *dev, int offset, u32 field,
455                 u32 mask, int shift)
456 {
457         u32 val = read_reg(dev, offset);
458 
459         write_field(&val, field, mask, shift);
460 
461         write_reg(dev, offset, val);
462 }
463 
464 /*
465  * DMA address/data block for the shadow registers
466  */
467 struct vpe_mmr_adb {
468         struct vpdma_adb_hdr    out_fmt_hdr;
469         u32                     out_fmt_reg[1];
470         u32                     out_fmt_pad[3];
471         struct vpdma_adb_hdr    us1_hdr;
472         u32                     us1_regs[8];
473         struct vpdma_adb_hdr    us2_hdr;
474         u32                     us2_regs[8];
475         struct vpdma_adb_hdr    us3_hdr;
476         u32                     us3_regs[8];
477         struct vpdma_adb_hdr    dei_hdr;
478         u32                     dei_regs[8];
479         struct vpdma_adb_hdr    sc_hdr0;
480         u32                     sc_regs0[7];
481         u32                     sc_pad0[1];
482         struct vpdma_adb_hdr    sc_hdr8;
483         u32                     sc_regs8[6];
484         u32                     sc_pad8[2];
485         struct vpdma_adb_hdr    sc_hdr17;
486         u32                     sc_regs17[9];
487         u32                     sc_pad17[3];
488         struct vpdma_adb_hdr    csc_hdr;
489         u32                     csc_regs[6];
490         u32                     csc_pad[2];
491 };
492 
493 #define GET_OFFSET_TOP(ctx, obj, reg)   \
494         ((obj)->res->start - ctx->dev->res->start + reg)
495 
496 #define VPE_SET_MMR_ADB_HDR(ctx, hdr, regs, offset_a)   \
497         VPDMA_SET_MMR_ADB_HDR(ctx->mmr_adb, vpe_mmr_adb, hdr, regs, offset_a)
498 /*
499  * Set the headers for all of the address/data block structures.
500  */
501 static void init_adb_hdrs(struct vpe_ctx *ctx)
502 {
503         VPE_SET_MMR_ADB_HDR(ctx, out_fmt_hdr, out_fmt_reg, VPE_CLK_FORMAT_SELECT);
504         VPE_SET_MMR_ADB_HDR(ctx, us1_hdr, us1_regs, VPE_US1_R0);
505         VPE_SET_MMR_ADB_HDR(ctx, us2_hdr, us2_regs, VPE_US2_R0);
506         VPE_SET_MMR_ADB_HDR(ctx, us3_hdr, us3_regs, VPE_US3_R0);
507         VPE_SET_MMR_ADB_HDR(ctx, dei_hdr, dei_regs, VPE_DEI_FRAME_SIZE);
508         VPE_SET_MMR_ADB_HDR(ctx, sc_hdr0, sc_regs0,
509                 GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC0));
510         VPE_SET_MMR_ADB_HDR(ctx, sc_hdr8, sc_regs8,
511                 GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC8));
512         VPE_SET_MMR_ADB_HDR(ctx, sc_hdr17, sc_regs17,
513                 GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC17));
514         VPE_SET_MMR_ADB_HDR(ctx, csc_hdr, csc_regs,
515                 GET_OFFSET_TOP(ctx, ctx->dev->csc, CSC_CSC00));
516 };
517 
518 /*
519  * Allocate or re-allocate the motion vector DMA buffers
520  * There are two buffers, one for input and one for output.
521  * However, the roles are reversed after each field is processed.
522  * In other words, after each field is processed, the previous
523  * output (dst) MV buffer becomes the new input (src) MV buffer.
524  */
525 static int realloc_mv_buffers(struct vpe_ctx *ctx, size_t size)
526 {
527         struct device *dev = ctx->dev->v4l2_dev.dev;
528 
529         if (ctx->mv_buf_size == size)
530                 return 0;
531 
532         if (ctx->mv_buf[0])
533                 dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[0],
534                         ctx->mv_buf_dma[0]);
535 
536         if (ctx->mv_buf[1])
537                 dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[1],
538                         ctx->mv_buf_dma[1]);
539 
540         if (size == 0)
541                 return 0;
542 
543         ctx->mv_buf[0] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[0],
544                                 GFP_KERNEL);
545         if (!ctx->mv_buf[0]) {
546                 vpe_err(ctx->dev, "failed to allocate motion vector buffer\n");
547                 return -ENOMEM;
548         }
549 
550         ctx->mv_buf[1] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[1],
551                                 GFP_KERNEL);
552         if (!ctx->mv_buf[1]) {
553                 vpe_err(ctx->dev, "failed to allocate motion vector buffer\n");
554                 dma_free_coherent(dev, size, ctx->mv_buf[0],
555                         ctx->mv_buf_dma[0]);
556 
557                 return -ENOMEM;
558         }
559 
560         ctx->mv_buf_size = size;
561         ctx->src_mv_buf_selector = 0;
562 
563         return 0;
564 }
565 
566 static void free_mv_buffers(struct vpe_ctx *ctx)
567 {
568         realloc_mv_buffers(ctx, 0);
569 }
570 
571 /*
572  * While de-interlacing, we keep the two most recent input buffers
573  * around.  This function frees those two buffers when we have
574  * finished processing the current stream.
575  */
576 static void free_vbs(struct vpe_ctx *ctx)
577 {
578         struct vpe_dev *dev = ctx->dev;
579         unsigned long flags;
580 
581         if (ctx->src_vbs[2] == NULL)
582                 return;
583 
584         spin_lock_irqsave(&dev->lock, flags);
585         if (ctx->src_vbs[2]) {
586                 v4l2_m2m_buf_done(ctx->src_vbs[2], VB2_BUF_STATE_DONE);
587                 v4l2_m2m_buf_done(ctx->src_vbs[1], VB2_BUF_STATE_DONE);
588         }
589         spin_unlock_irqrestore(&dev->lock, flags);
590 }
591 
592 /*
593  * Enable or disable the VPE clocks
594  */
595 static void vpe_set_clock_enable(struct vpe_dev *dev, bool on)
596 {
597         u32 val = 0;
598 
599         if (on)
600                 val = VPE_DATA_PATH_CLK_ENABLE | VPE_VPEDMA_CLK_ENABLE;
601         write_reg(dev, VPE_CLK_ENABLE, val);
602 }
603 
604 static void vpe_top_reset(struct vpe_dev *dev)
605 {
606 
607         write_field_reg(dev, VPE_CLK_RESET, 1, VPE_DATA_PATH_CLK_RESET_MASK,
608                 VPE_DATA_PATH_CLK_RESET_SHIFT);
609 
610         usleep_range(100, 150);
611 
612         write_field_reg(dev, VPE_CLK_RESET, 0, VPE_DATA_PATH_CLK_RESET_MASK,
613                 VPE_DATA_PATH_CLK_RESET_SHIFT);
614 }
615 
616 static void vpe_top_vpdma_reset(struct vpe_dev *dev)
617 {
618         write_field_reg(dev, VPE_CLK_RESET, 1, VPE_VPDMA_CLK_RESET_MASK,
619                 VPE_VPDMA_CLK_RESET_SHIFT);
620 
621         usleep_range(100, 150);
622 
623         write_field_reg(dev, VPE_CLK_RESET, 0, VPE_VPDMA_CLK_RESET_MASK,
624                 VPE_VPDMA_CLK_RESET_SHIFT);
625 }
626 
627 /*
628  * Load the correct of upsampler coefficients into the shadow MMRs
629  */
630 static void set_us_coefficients(struct vpe_ctx *ctx)
631 {
632         struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
633         struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
634         u32 *us1_reg = &mmr_adb->us1_regs[0];
635         u32 *us2_reg = &mmr_adb->us2_regs[0];
636         u32 *us3_reg = &mmr_adb->us3_regs[0];
637         const unsigned short *cp, *end_cp;
638 
639         cp = &us_coeffs[0].anchor_fid0_c0;
640 
641         if (s_q_data->flags & Q_DATA_INTERLACED)        /* interlaced */
642                 cp += sizeof(us_coeffs[0]) / sizeof(*cp);
643 
644         end_cp = cp + sizeof(us_coeffs[0]) / sizeof(*cp);
645 
646         while (cp < end_cp) {
647                 write_field(us1_reg, *cp++, VPE_US_C0_MASK, VPE_US_C0_SHIFT);
648                 write_field(us1_reg, *cp++, VPE_US_C1_MASK, VPE_US_C1_SHIFT);
649                 *us2_reg++ = *us1_reg;
650                 *us3_reg++ = *us1_reg++;
651         }
652         ctx->load_mmrs = true;
653 }
654 
655 /*
656  * Set the upsampler config mode and the VPDMA line mode in the shadow MMRs.
657  */
658 static void set_cfg_and_line_modes(struct vpe_ctx *ctx)
659 {
660         struct vpe_fmt *fmt = ctx->q_data[Q_DATA_SRC].fmt;
661         struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
662         u32 *us1_reg0 = &mmr_adb->us1_regs[0];
663         u32 *us2_reg0 = &mmr_adb->us2_regs[0];
664         u32 *us3_reg0 = &mmr_adb->us3_regs[0];
665         int line_mode = 1;
666         int cfg_mode = 1;
667 
668         /*
669          * Cfg Mode 0: YUV420 source, enable upsampler, DEI is de-interlacing.
670          * Cfg Mode 1: YUV422 source, disable upsampler, DEI is de-interlacing.
671          */
672 
673         if (fmt->fourcc == V4L2_PIX_FMT_NV12) {
674                 cfg_mode = 0;
675                 line_mode = 0;          /* double lines to line buffer */
676         }
677 
678         write_field(us1_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
679         write_field(us2_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
680         write_field(us3_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
681 
682         /* regs for now */
683         vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA1_IN);
684         vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA2_IN);
685         vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA3_IN);
686 
687         /* frame start for input luma */
688         vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
689                 VPE_CHAN_LUMA1_IN);
690         vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
691                 VPE_CHAN_LUMA2_IN);
692         vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
693                 VPE_CHAN_LUMA3_IN);
694 
695         /* frame start for input chroma */
696         vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
697                 VPE_CHAN_CHROMA1_IN);
698         vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
699                 VPE_CHAN_CHROMA2_IN);
700         vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
701                 VPE_CHAN_CHROMA3_IN);
702 
703         /* frame start for MV in client */
704         vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
705                 VPE_CHAN_MV_IN);
706 
707         ctx->load_mmrs = true;
708 }
709 
710 /*
711  * Set the shadow registers that are modified when the source
712  * format changes.
713  */
714 static void set_src_registers(struct vpe_ctx *ctx)
715 {
716         set_us_coefficients(ctx);
717 }
718 
719 /*
720  * Set the shadow registers that are modified when the destination
721  * format changes.
722  */
723 static void set_dst_registers(struct vpe_ctx *ctx)
724 {
725         struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
726         enum v4l2_colorspace clrspc = ctx->q_data[Q_DATA_DST].colorspace;
727         struct vpe_fmt *fmt = ctx->q_data[Q_DATA_DST].fmt;
728         u32 val = 0;
729 
730         if (clrspc == V4L2_COLORSPACE_SRGB)
731                 val |= VPE_RGB_OUT_SELECT;
732         else if (fmt->fourcc == V4L2_PIX_FMT_NV16)
733                 val |= VPE_COLOR_SEPARATE_422;
734 
735         /*
736          * the source of CHR_DS and CSC is always the scaler, irrespective of
737          * whether it's used or not
738          */
739         val |= VPE_DS_SRC_DEI_SCALER | VPE_CSC_SRC_DEI_SCALER;
740 
741         if (fmt->fourcc != V4L2_PIX_FMT_NV12)
742                 val |= VPE_DS_BYPASS;
743 
744         mmr_adb->out_fmt_reg[0] = val;
745 
746         ctx->load_mmrs = true;
747 }
748 
749 /*
750  * Set the de-interlacer shadow register values
751  */
752 static void set_dei_regs(struct vpe_ctx *ctx)
753 {
754         struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
755         struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
756         unsigned int src_h = s_q_data->c_rect.height;
757         unsigned int src_w = s_q_data->c_rect.width;
758         u32 *dei_mmr0 = &mmr_adb->dei_regs[0];
759         bool deinterlace = true;
760         u32 val = 0;
761 
762         /*
763          * according to TRM, we should set DEI in progressive bypass mode when
764          * the input content is progressive, however, DEI is bypassed correctly
765          * for both progressive and interlace content in interlace bypass mode.
766          * It has been recommended not to use progressive bypass mode.
767          */
768         if ((!ctx->deinterlacing && (s_q_data->flags & Q_DATA_INTERLACED)) ||
769                         !(s_q_data->flags & Q_DATA_INTERLACED)) {
770                 deinterlace = false;
771                 val = VPE_DEI_INTERLACE_BYPASS;
772         }
773 
774         src_h = deinterlace ? src_h * 2 : src_h;
775 
776         val |= (src_h << VPE_DEI_HEIGHT_SHIFT) |
777                 (src_w << VPE_DEI_WIDTH_SHIFT) |
778                 VPE_DEI_FIELD_FLUSH;
779 
780         *dei_mmr0 = val;
781 
782         ctx->load_mmrs = true;
783 }
784 
785 static void set_dei_shadow_registers(struct vpe_ctx *ctx)
786 {
787         struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
788         u32 *dei_mmr = &mmr_adb->dei_regs[0];
789         const struct vpe_dei_regs *cur = &dei_regs;
790 
791         dei_mmr[2]  = cur->mdt_spacial_freq_thr_reg;
792         dei_mmr[3]  = cur->edi_config_reg;
793         dei_mmr[4]  = cur->edi_lut_reg0;
794         dei_mmr[5]  = cur->edi_lut_reg1;
795         dei_mmr[6]  = cur->edi_lut_reg2;
796         dei_mmr[7]  = cur->edi_lut_reg3;
797 
798         ctx->load_mmrs = true;
799 }
800 
801 /*
802  * Set the shadow registers whose values are modified when either the
803  * source or destination format is changed.
804  */
805 static int set_srcdst_params(struct vpe_ctx *ctx)
806 {
807         struct vpe_q_data *s_q_data =  &ctx->q_data[Q_DATA_SRC];
808         struct vpe_q_data *d_q_data =  &ctx->q_data[Q_DATA_DST];
809         struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
810         unsigned int src_w = s_q_data->c_rect.width;
811         unsigned int src_h = s_q_data->c_rect.height;
812         unsigned int dst_w = d_q_data->c_rect.width;
813         unsigned int dst_h = d_q_data->c_rect.height;
814         size_t mv_buf_size;
815         int ret;
816 
817         ctx->sequence = 0;
818         ctx->field = V4L2_FIELD_TOP;
819 
820         if ((s_q_data->flags & Q_DATA_INTERLACED) &&
821                         !(d_q_data->flags & Q_DATA_INTERLACED)) {
822                 int bytes_per_line;
823                 const struct vpdma_data_format *mv =
824                         &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
825 
826                 /*
827                  * we make sure that the source image has a 16 byte aligned
828                  * stride, we need to do the same for the motion vector buffer
829                  * by aligning it's stride to the next 16 byte boundry. this
830                  * extra space will not be used by the de-interlacer, but will
831                  * ensure that vpdma operates correctly
832                  */
833                 bytes_per_line = ALIGN((s_q_data->width * mv->depth) >> 3,
834                                         VPDMA_STRIDE_ALIGN);
835                 mv_buf_size = bytes_per_line * s_q_data->height;
836 
837                 ctx->deinterlacing = 1;
838                 src_h <<= 1;
839         } else {
840                 ctx->deinterlacing = 0;
841                 mv_buf_size = 0;
842         }
843 
844         free_vbs(ctx);
845 
846         ret = realloc_mv_buffers(ctx, mv_buf_size);
847         if (ret)
848                 return ret;
849 
850         set_cfg_and_line_modes(ctx);
851         set_dei_regs(ctx);
852 
853         csc_set_coeff(ctx->dev->csc, &mmr_adb->csc_regs[0],
854                 s_q_data->colorspace, d_q_data->colorspace);
855 
856         sc_set_hs_coeffs(ctx->dev->sc, ctx->sc_coeff_h.addr, src_w, dst_w);
857         sc_set_vs_coeffs(ctx->dev->sc, ctx->sc_coeff_v.addr, src_h, dst_h);
858 
859         sc_config_scaler(ctx->dev->sc, &mmr_adb->sc_regs0[0],
860                 &mmr_adb->sc_regs8[0], &mmr_adb->sc_regs17[0],
861                 src_w, src_h, dst_w, dst_h);
862 
863         return 0;
864 }
865 
866 /*
867  * Return the vpe_ctx structure for a given struct file
868  */
869 static struct vpe_ctx *file2ctx(struct file *file)
870 {
871         return container_of(file->private_data, struct vpe_ctx, fh);
872 }
873 
874 /*
875  * mem2mem callbacks
876  */
877 
878 /**
879  * job_ready() - check whether an instance is ready to be scheduled to run
880  */
881 static int job_ready(void *priv)
882 {
883         struct vpe_ctx *ctx = priv;
884         int needed = ctx->bufs_per_job;
885 
886         if (ctx->deinterlacing && ctx->src_vbs[2] == NULL)
887                 needed += 2;    /* need additional two most recent fields */
888 
889         if (v4l2_m2m_num_src_bufs_ready(ctx->m2m_ctx) < needed)
890                 return 0;
891 
892         if (v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx) < needed)
893                 return 0;
894 
895         return 1;
896 }
897 
898 static void job_abort(void *priv)
899 {
900         struct vpe_ctx *ctx = priv;
901 
902         /* Will cancel the transaction in the next interrupt handler */
903         ctx->aborting = 1;
904 }
905 
906 /*
907  * Lock access to the device
908  */
909 static void vpe_lock(void *priv)
910 {
911         struct vpe_ctx *ctx = priv;
912         struct vpe_dev *dev = ctx->dev;
913         mutex_lock(&dev->dev_mutex);
914 }
915 
916 static void vpe_unlock(void *priv)
917 {
918         struct vpe_ctx *ctx = priv;
919         struct vpe_dev *dev = ctx->dev;
920         mutex_unlock(&dev->dev_mutex);
921 }
922 
923 static void vpe_dump_regs(struct vpe_dev *dev)
924 {
925 #define DUMPREG(r) vpe_dbg(dev, "%-35s %08x\n", #r, read_reg(dev, VPE_##r))
926 
927         vpe_dbg(dev, "VPE Registers:\n");
928 
929         DUMPREG(PID);
930         DUMPREG(SYSCONFIG);
931         DUMPREG(INT0_STATUS0_RAW);
932         DUMPREG(INT0_STATUS0);
933         DUMPREG(INT0_ENABLE0);
934         DUMPREG(INT0_STATUS1_RAW);
935         DUMPREG(INT0_STATUS1);
936         DUMPREG(INT0_ENABLE1);
937         DUMPREG(CLK_ENABLE);
938         DUMPREG(CLK_RESET);
939         DUMPREG(CLK_FORMAT_SELECT);
940         DUMPREG(CLK_RANGE_MAP);
941         DUMPREG(US1_R0);
942         DUMPREG(US1_R1);
943         DUMPREG(US1_R2);
944         DUMPREG(US1_R3);
945         DUMPREG(US1_R4);
946         DUMPREG(US1_R5);
947         DUMPREG(US1_R6);
948         DUMPREG(US1_R7);
949         DUMPREG(US2_R0);
950         DUMPREG(US2_R1);
951         DUMPREG(US2_R2);
952         DUMPREG(US2_R3);
953         DUMPREG(US2_R4);
954         DUMPREG(US2_R5);
955         DUMPREG(US2_R6);
956         DUMPREG(US2_R7);
957         DUMPREG(US3_R0);
958         DUMPREG(US3_R1);
959         DUMPREG(US3_R2);
960         DUMPREG(US3_R3);
961         DUMPREG(US3_R4);
962         DUMPREG(US3_R5);
963         DUMPREG(US3_R6);
964         DUMPREG(US3_R7);
965         DUMPREG(DEI_FRAME_SIZE);
966         DUMPREG(MDT_BYPASS);
967         DUMPREG(MDT_SF_THRESHOLD);
968         DUMPREG(EDI_CONFIG);
969         DUMPREG(DEI_EDI_LUT_R0);
970         DUMPREG(DEI_EDI_LUT_R1);
971         DUMPREG(DEI_EDI_LUT_R2);
972         DUMPREG(DEI_EDI_LUT_R3);
973         DUMPREG(DEI_FMD_WINDOW_R0);
974         DUMPREG(DEI_FMD_WINDOW_R1);
975         DUMPREG(DEI_FMD_CONTROL_R0);
976         DUMPREG(DEI_FMD_CONTROL_R1);
977         DUMPREG(DEI_FMD_STATUS_R0);
978         DUMPREG(DEI_FMD_STATUS_R1);
979         DUMPREG(DEI_FMD_STATUS_R2);
980 #undef DUMPREG
981 
982         sc_dump_regs(dev->sc);
983         csc_dump_regs(dev->csc);
984 }
985 
986 static void add_out_dtd(struct vpe_ctx *ctx, int port)
987 {
988         struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_DST];
989         const struct vpe_port_data *p_data = &port_data[port];
990         struct vb2_buffer *vb = ctx->dst_vb;
991         struct vpe_fmt *fmt = q_data->fmt;
992         const struct vpdma_data_format *vpdma_fmt;
993         int mv_buf_selector = !ctx->src_mv_buf_selector;
994         dma_addr_t dma_addr;
995         u32 flags = 0;
996 
997         if (port == VPE_PORT_MV_OUT) {
998                 vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
999                 dma_addr = ctx->mv_buf_dma[mv_buf_selector];
1000         } else {
1001                 /* to incorporate interleaved formats */
1002                 int plane = fmt->coplanar ? p_data->vb_part : 0;
1003 
1004                 vpdma_fmt = fmt->vpdma_fmt[plane];
1005                 dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane);
1006                 if (!dma_addr) {
1007                         vpe_err(ctx->dev,
1008                                 "acquiring output buffer(%d) dma_addr failed\n",
1009                                 port);
1010                         return;
1011                 }
1012         }
1013 
1014         if (q_data->flags & Q_DATA_FRAME_1D)
1015                 flags |= VPDMA_DATA_FRAME_1D;
1016         if (q_data->flags & Q_DATA_MODE_TILED)
1017                 flags |= VPDMA_DATA_MODE_TILED;
1018 
1019         vpdma_add_out_dtd(&ctx->desc_list, q_data->width, &q_data->c_rect,
1020                 vpdma_fmt, dma_addr, p_data->channel, flags);
1021 }
1022 
1023 static void add_in_dtd(struct vpe_ctx *ctx, int port)
1024 {
1025         struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_SRC];
1026         const struct vpe_port_data *p_data = &port_data[port];
1027         struct vb2_buffer *vb = ctx->src_vbs[p_data->vb_index];
1028         struct vpe_fmt *fmt = q_data->fmt;
1029         const struct vpdma_data_format *vpdma_fmt;
1030         int mv_buf_selector = ctx->src_mv_buf_selector;
1031         int field = vb->v4l2_buf.field == V4L2_FIELD_BOTTOM;
1032         int frame_width, frame_height;
1033         dma_addr_t dma_addr;
1034         u32 flags = 0;
1035 
1036         if (port == VPE_PORT_MV_IN) {
1037                 vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
1038                 dma_addr = ctx->mv_buf_dma[mv_buf_selector];
1039         } else {
1040                 /* to incorporate interleaved formats */
1041                 int plane = fmt->coplanar ? p_data->vb_part : 0;
1042 
1043                 vpdma_fmt = fmt->vpdma_fmt[plane];
1044 
1045                 dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane);
1046                 if (!dma_addr) {
1047                         vpe_err(ctx->dev,
1048                                 "acquiring input buffer(%d) dma_addr failed\n",
1049                                 port);
1050                         return;
1051                 }
1052         }
1053 
1054         if (q_data->flags & Q_DATA_FRAME_1D)
1055                 flags |= VPDMA_DATA_FRAME_1D;
1056         if (q_data->flags & Q_DATA_MODE_TILED)
1057                 flags |= VPDMA_DATA_MODE_TILED;
1058 
1059         frame_width = q_data->c_rect.width;
1060         frame_height = q_data->c_rect.height;
1061 
1062         if (p_data->vb_part && fmt->fourcc == V4L2_PIX_FMT_NV12)
1063                 frame_height /= 2;
1064 
1065         vpdma_add_in_dtd(&ctx->desc_list, q_data->width, &q_data->c_rect,
1066                 vpdma_fmt, dma_addr, p_data->channel, field, flags, frame_width,
1067                 frame_height, 0, 0);
1068 }
1069 
1070 /*
1071  * Enable the expected IRQ sources
1072  */
1073 static void enable_irqs(struct vpe_ctx *ctx)
1074 {
1075         write_reg(ctx->dev, VPE_INT0_ENABLE0_SET, VPE_INT0_LIST0_COMPLETE);
1076         write_reg(ctx->dev, VPE_INT0_ENABLE1_SET, VPE_DEI_ERROR_INT |
1077                                 VPE_DS1_UV_ERROR_INT);
1078 
1079         vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, true);
1080 }
1081 
1082 static void disable_irqs(struct vpe_ctx *ctx)
1083 {
1084         write_reg(ctx->dev, VPE_INT0_ENABLE0_CLR, 0xffffffff);
1085         write_reg(ctx->dev, VPE_INT0_ENABLE1_CLR, 0xffffffff);
1086 
1087         vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, false);
1088 }
1089 
1090 /* device_run() - prepares and starts the device
1091  *
1092  * This function is only called when both the source and destination
1093  * buffers are in place.
1094  */
1095 static void device_run(void *priv)
1096 {
1097         struct vpe_ctx *ctx = priv;
1098         struct sc_data *sc = ctx->dev->sc;
1099         struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
1100 
1101         if (ctx->deinterlacing && ctx->src_vbs[2] == NULL) {
1102                 ctx->src_vbs[2] = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
1103                 WARN_ON(ctx->src_vbs[2] == NULL);
1104                 ctx->src_vbs[1] = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
1105                 WARN_ON(ctx->src_vbs[1] == NULL);
1106         }
1107 
1108         ctx->src_vbs[0] = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
1109         WARN_ON(ctx->src_vbs[0] == NULL);
1110         ctx->dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
1111         WARN_ON(ctx->dst_vb == NULL);
1112 
1113         /* config descriptors */
1114         if (ctx->dev->loaded_mmrs != ctx->mmr_adb.dma_addr || ctx->load_mmrs) {
1115                 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->mmr_adb);
1116                 vpdma_add_cfd_adb(&ctx->desc_list, CFD_MMR_CLIENT, &ctx->mmr_adb);
1117                 ctx->dev->loaded_mmrs = ctx->mmr_adb.dma_addr;
1118                 ctx->load_mmrs = false;
1119         }
1120 
1121         if (sc->loaded_coeff_h != ctx->sc_coeff_h.dma_addr ||
1122                         sc->load_coeff_h) {
1123                 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->sc_coeff_h);
1124                 vpdma_add_cfd_block(&ctx->desc_list, CFD_SC_CLIENT,
1125                         &ctx->sc_coeff_h, 0);
1126 
1127                 sc->loaded_coeff_h = ctx->sc_coeff_h.dma_addr;
1128                 sc->load_coeff_h = false;
1129         }
1130 
1131         if (sc->loaded_coeff_v != ctx->sc_coeff_v.dma_addr ||
1132                         sc->load_coeff_v) {
1133                 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->sc_coeff_v);
1134                 vpdma_add_cfd_block(&ctx->desc_list, CFD_SC_CLIENT,
1135                         &ctx->sc_coeff_v, SC_COEF_SRAM_SIZE >> 4);
1136 
1137                 sc->loaded_coeff_v = ctx->sc_coeff_v.dma_addr;
1138                 sc->load_coeff_v = false;
1139         }
1140 
1141         /* output data descriptors */
1142         if (ctx->deinterlacing)
1143                 add_out_dtd(ctx, VPE_PORT_MV_OUT);
1144 
1145         if (d_q_data->colorspace == V4L2_COLORSPACE_SRGB) {
1146                 add_out_dtd(ctx, VPE_PORT_RGB_OUT);
1147         } else {
1148                 add_out_dtd(ctx, VPE_PORT_LUMA_OUT);
1149                 if (d_q_data->fmt->coplanar)
1150                         add_out_dtd(ctx, VPE_PORT_CHROMA_OUT);
1151         }
1152 
1153         /* input data descriptors */
1154         if (ctx->deinterlacing) {
1155                 add_in_dtd(ctx, VPE_PORT_LUMA3_IN);
1156                 add_in_dtd(ctx, VPE_PORT_CHROMA3_IN);
1157 
1158                 add_in_dtd(ctx, VPE_PORT_LUMA2_IN);
1159                 add_in_dtd(ctx, VPE_PORT_CHROMA2_IN);
1160         }
1161 
1162         add_in_dtd(ctx, VPE_PORT_LUMA1_IN);
1163         add_in_dtd(ctx, VPE_PORT_CHROMA1_IN);
1164 
1165         if (ctx->deinterlacing)
1166                 add_in_dtd(ctx, VPE_PORT_MV_IN);
1167 
1168         /* sync on channel control descriptors for input ports */
1169         vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_LUMA1_IN);
1170         vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_CHROMA1_IN);
1171 
1172         if (ctx->deinterlacing) {
1173                 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1174                         VPE_CHAN_LUMA2_IN);
1175                 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1176                         VPE_CHAN_CHROMA2_IN);
1177 
1178                 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1179                         VPE_CHAN_LUMA3_IN);
1180                 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1181                         VPE_CHAN_CHROMA3_IN);
1182 
1183                 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_IN);
1184         }
1185 
1186         /* sync on channel control descriptors for output ports */
1187         if (d_q_data->colorspace == V4L2_COLORSPACE_SRGB) {
1188                 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1189                         VPE_CHAN_RGB_OUT);
1190         } else {
1191                 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1192                         VPE_CHAN_LUMA_OUT);
1193                 if (d_q_data->fmt->coplanar)
1194                         vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1195                                 VPE_CHAN_CHROMA_OUT);
1196         }
1197 
1198         if (ctx->deinterlacing)
1199                 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_OUT);
1200 
1201         enable_irqs(ctx);
1202 
1203         vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->desc_list.buf);
1204         vpdma_submit_descs(ctx->dev->vpdma, &ctx->desc_list);
1205 }
1206 
1207 static void dei_error(struct vpe_ctx *ctx)
1208 {
1209         dev_warn(ctx->dev->v4l2_dev.dev,
1210                 "received DEI error interrupt\n");
1211 }
1212 
1213 static void ds1_uv_error(struct vpe_ctx *ctx)
1214 {
1215         dev_warn(ctx->dev->v4l2_dev.dev,
1216                 "received downsampler error interrupt\n");
1217 }
1218 
1219 static irqreturn_t vpe_irq(int irq_vpe, void *data)
1220 {
1221         struct vpe_dev *dev = (struct vpe_dev *)data;
1222         struct vpe_ctx *ctx;
1223         struct vpe_q_data *d_q_data;
1224         struct vb2_buffer *s_vb, *d_vb;
1225         struct v4l2_buffer *s_buf, *d_buf;
1226         unsigned long flags;
1227         u32 irqst0, irqst1;
1228 
1229         irqst0 = read_reg(dev, VPE_INT0_STATUS0);
1230         if (irqst0) {
1231                 write_reg(dev, VPE_INT0_STATUS0_CLR, irqst0);
1232                 vpe_dbg(dev, "INT0_STATUS0 = 0x%08x\n", irqst0);
1233         }
1234 
1235         irqst1 = read_reg(dev, VPE_INT0_STATUS1);
1236         if (irqst1) {
1237                 write_reg(dev, VPE_INT0_STATUS1_CLR, irqst1);
1238                 vpe_dbg(dev, "INT0_STATUS1 = 0x%08x\n", irqst1);
1239         }
1240 
1241         ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
1242         if (!ctx) {
1243                 vpe_err(dev, "instance released before end of transaction\n");
1244                 goto handled;
1245         }
1246 
1247         if (irqst1) {
1248                 if (irqst1 & VPE_DEI_ERROR_INT) {
1249                         irqst1 &= ~VPE_DEI_ERROR_INT;
1250                         dei_error(ctx);
1251                 }
1252                 if (irqst1 & VPE_DS1_UV_ERROR_INT) {
1253                         irqst1 &= ~VPE_DS1_UV_ERROR_INT;
1254                         ds1_uv_error(ctx);
1255                 }
1256         }
1257 
1258         if (irqst0) {
1259                 if (irqst0 & VPE_INT0_LIST0_COMPLETE)
1260                         vpdma_clear_list_stat(ctx->dev->vpdma);
1261 
1262                 irqst0 &= ~(VPE_INT0_LIST0_COMPLETE);
1263         }
1264 
1265         if (irqst0 | irqst1) {
1266                 dev_warn(dev->v4l2_dev.dev, "Unexpected interrupt: "
1267                         "INT0_STATUS0 = 0x%08x, INT0_STATUS1 = 0x%08x\n",
1268                         irqst0, irqst1);
1269         }
1270 
1271         disable_irqs(ctx);
1272 
1273         vpdma_unmap_desc_buf(dev->vpdma, &ctx->desc_list.buf);
1274         vpdma_unmap_desc_buf(dev->vpdma, &ctx->mmr_adb);
1275         vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_h);
1276         vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_v);
1277 
1278         vpdma_reset_desc_list(&ctx->desc_list);
1279 
1280          /* the previous dst mv buffer becomes the next src mv buffer */
1281         ctx->src_mv_buf_selector = !ctx->src_mv_buf_selector;
1282 
1283         if (ctx->aborting)
1284                 goto finished;
1285 
1286         s_vb = ctx->src_vbs[0];
1287         d_vb = ctx->dst_vb;
1288         s_buf = &s_vb->v4l2_buf;
1289         d_buf = &d_vb->v4l2_buf;
1290 
1291         d_buf->flags = s_buf->flags;
1292 
1293         d_buf->timestamp = s_buf->timestamp;
1294         if (s_buf->flags & V4L2_BUF_FLAG_TIMECODE)
1295                 d_buf->timecode = s_buf->timecode;
1296 
1297         d_buf->sequence = ctx->sequence;
1298 
1299         d_q_data = &ctx->q_data[Q_DATA_DST];
1300         if (d_q_data->flags & Q_DATA_INTERLACED) {
1301                 d_buf->field = ctx->field;
1302                 if (ctx->field == V4L2_FIELD_BOTTOM) {
1303                         ctx->sequence++;
1304                         ctx->field = V4L2_FIELD_TOP;
1305                 } else {
1306                         WARN_ON(ctx->field != V4L2_FIELD_TOP);
1307                         ctx->field = V4L2_FIELD_BOTTOM;
1308                 }
1309         } else {
1310                 d_buf->field = V4L2_FIELD_NONE;
1311                 ctx->sequence++;
1312         }
1313 
1314         if (ctx->deinterlacing)
1315                 s_vb = ctx->src_vbs[2];
1316 
1317         spin_lock_irqsave(&dev->lock, flags);
1318         v4l2_m2m_buf_done(s_vb, VB2_BUF_STATE_DONE);
1319         v4l2_m2m_buf_done(d_vb, VB2_BUF_STATE_DONE);
1320         spin_unlock_irqrestore(&dev->lock, flags);
1321 
1322         if (ctx->deinterlacing) {
1323                 ctx->src_vbs[2] = ctx->src_vbs[1];
1324                 ctx->src_vbs[1] = ctx->src_vbs[0];
1325         }
1326 
1327         ctx->bufs_completed++;
1328         if (ctx->bufs_completed < ctx->bufs_per_job) {
1329                 device_run(ctx);
1330                 goto handled;
1331         }
1332 
1333 finished:
1334         vpe_dbg(ctx->dev, "finishing transaction\n");
1335         ctx->bufs_completed = 0;
1336         v4l2_m2m_job_finish(dev->m2m_dev, ctx->m2m_ctx);
1337 handled:
1338         return IRQ_HANDLED;
1339 }
1340 
1341 /*
1342  * video ioctls
1343  */
1344 static int vpe_querycap(struct file *file, void *priv,
1345                         struct v4l2_capability *cap)
1346 {
1347         strncpy(cap->driver, VPE_MODULE_NAME, sizeof(cap->driver) - 1);
1348         strncpy(cap->card, VPE_MODULE_NAME, sizeof(cap->card) - 1);
1349         snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
1350                 VPE_MODULE_NAME);
1351         cap->device_caps  = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING;
1352         cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
1353         return 0;
1354 }
1355 
1356 static int __enum_fmt(struct v4l2_fmtdesc *f, u32 type)
1357 {
1358         int i, index;
1359         struct vpe_fmt *fmt = NULL;
1360 
1361         index = 0;
1362         for (i = 0; i < ARRAY_SIZE(vpe_formats); ++i) {
1363                 if (vpe_formats[i].types & type) {
1364                         if (index == f->index) {
1365                                 fmt = &vpe_formats[i];
1366                                 break;
1367                         }
1368                         index++;
1369                 }
1370         }
1371 
1372         if (!fmt)
1373                 return -EINVAL;
1374 
1375         strncpy(f->description, fmt->name, sizeof(f->description) - 1);
1376         f->pixelformat = fmt->fourcc;
1377         return 0;
1378 }
1379 
1380 static int vpe_enum_fmt(struct file *file, void *priv,
1381                                 struct v4l2_fmtdesc *f)
1382 {
1383         if (V4L2_TYPE_IS_OUTPUT(f->type))
1384                 return __enum_fmt(f, VPE_FMT_TYPE_OUTPUT);
1385 
1386         return __enum_fmt(f, VPE_FMT_TYPE_CAPTURE);
1387 }
1388 
1389 static int vpe_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
1390 {
1391         struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1392         struct vpe_ctx *ctx = file2ctx(file);
1393         struct vb2_queue *vq;
1394         struct vpe_q_data *q_data;
1395         int i;
1396 
1397         vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
1398         if (!vq)
1399                 return -EINVAL;
1400 
1401         q_data = get_q_data(ctx, f->type);
1402 
1403         pix->width = q_data->width;
1404         pix->height = q_data->height;
1405         pix->pixelformat = q_data->fmt->fourcc;
1406         pix->field = q_data->field;
1407 
1408         if (V4L2_TYPE_IS_OUTPUT(f->type)) {
1409                 pix->colorspace = q_data->colorspace;
1410         } else {
1411                 struct vpe_q_data *s_q_data;
1412 
1413                 /* get colorspace from the source queue */
1414                 s_q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
1415 
1416                 pix->colorspace = s_q_data->colorspace;
1417         }
1418 
1419         pix->num_planes = q_data->fmt->coplanar ? 2 : 1;
1420 
1421         for (i = 0; i < pix->num_planes; i++) {
1422                 pix->plane_fmt[i].bytesperline = q_data->bytesperline[i];
1423                 pix->plane_fmt[i].sizeimage = q_data->sizeimage[i];
1424         }
1425 
1426         return 0;
1427 }
1428 
1429 static int __vpe_try_fmt(struct vpe_ctx *ctx, struct v4l2_format *f,
1430                        struct vpe_fmt *fmt, int type)
1431 {
1432         struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1433         struct v4l2_plane_pix_format *plane_fmt;
1434         unsigned int w_align;
1435         int i, depth, depth_bytes;
1436 
1437         if (!fmt || !(fmt->types & type)) {
1438                 vpe_err(ctx->dev, "Fourcc format (0x%08x) invalid.\n",
1439                         pix->pixelformat);
1440                 return -EINVAL;
1441         }
1442 
1443         if (pix->field != V4L2_FIELD_NONE && pix->field != V4L2_FIELD_ALTERNATE)
1444                 pix->field = V4L2_FIELD_NONE;
1445 
1446         depth = fmt->vpdma_fmt[VPE_LUMA]->depth;
1447 
1448         /*
1449          * the line stride should 16 byte aligned for VPDMA to work, based on
1450          * the bytes per pixel, figure out how much the width should be aligned
1451          * to make sure line stride is 16 byte aligned
1452          */
1453         depth_bytes = depth >> 3;
1454 
1455         if (depth_bytes == 3)
1456                 /*
1457                  * if bpp is 3(as in some RGB formats), the pixel width doesn't
1458                  * really help in ensuring line stride is 16 byte aligned
1459                  */
1460                 w_align = 4;
1461         else
1462                 /*
1463                  * for the remainder bpp(4, 2 and 1), the pixel width alignment
1464                  * can ensure a line stride alignment of 16 bytes. For example,
1465                  * if bpp is 2, then the line stride can be 16 byte aligned if
1466                  * the width is 8 byte aligned
1467                  */
1468                 w_align = order_base_2(VPDMA_DESC_ALIGN / depth_bytes);
1469 
1470         v4l_bound_align_image(&pix->width, MIN_W, MAX_W, w_align,
1471                               &pix->height, MIN_H, MAX_H, H_ALIGN,
1472                               S_ALIGN);
1473 
1474         pix->num_planes = fmt->coplanar ? 2 : 1;
1475         pix->pixelformat = fmt->fourcc;
1476 
1477         if (!pix->colorspace) {
1478                 if (fmt->fourcc == V4L2_PIX_FMT_RGB24 ||
1479                                 fmt->fourcc == V4L2_PIX_FMT_BGR24 ||
1480                                 fmt->fourcc == V4L2_PIX_FMT_RGB32 ||
1481                                 fmt->fourcc == V4L2_PIX_FMT_BGR32) {
1482                         pix->colorspace = V4L2_COLORSPACE_SRGB;
1483                 } else {
1484                         if (pix->height > 1280) /* HD */
1485                                 pix->colorspace = V4L2_COLORSPACE_REC709;
1486                         else                    /* SD */
1487                                 pix->colorspace = V4L2_COLORSPACE_SMPTE170M;
1488                 }
1489         }
1490 
1491         memset(pix->reserved, 0, sizeof(pix->reserved));
1492         for (i = 0; i < pix->num_planes; i++) {
1493                 plane_fmt = &pix->plane_fmt[i];
1494                 depth = fmt->vpdma_fmt[i]->depth;
1495 
1496                 if (i == VPE_LUMA)
1497                         plane_fmt->bytesperline = (pix->width * depth) >> 3;
1498                 else
1499                         plane_fmt->bytesperline = pix->width;
1500 
1501                 plane_fmt->sizeimage =
1502                                 (pix->height * pix->width * depth) >> 3;
1503 
1504                 memset(plane_fmt->reserved, 0, sizeof(plane_fmt->reserved));
1505         }
1506 
1507         return 0;
1508 }
1509 
1510 static int vpe_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
1511 {
1512         struct vpe_ctx *ctx = file2ctx(file);
1513         struct vpe_fmt *fmt = find_format(f);
1514 
1515         if (V4L2_TYPE_IS_OUTPUT(f->type))
1516                 return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_OUTPUT);
1517         else
1518                 return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_CAPTURE);
1519 }
1520 
1521 static int __vpe_s_fmt(struct vpe_ctx *ctx, struct v4l2_format *f)
1522 {
1523         struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1524         struct v4l2_plane_pix_format *plane_fmt;
1525         struct vpe_q_data *q_data;
1526         struct vb2_queue *vq;
1527         int i;
1528 
1529         vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
1530         if (!vq)
1531                 return -EINVAL;
1532 
1533         if (vb2_is_busy(vq)) {
1534                 vpe_err(ctx->dev, "queue busy\n");
1535                 return -EBUSY;
1536         }
1537 
1538         q_data = get_q_data(ctx, f->type);
1539         if (!q_data)
1540                 return -EINVAL;
1541 
1542         q_data->fmt             = find_format(f);
1543         q_data->width           = pix->width;
1544         q_data->height          = pix->height;
1545         q_data->colorspace      = pix->colorspace;
1546         q_data->field           = pix->field;
1547 
1548         for (i = 0; i < pix->num_planes; i++) {
1549                 plane_fmt = &pix->plane_fmt[i];
1550 
1551                 q_data->bytesperline[i] = plane_fmt->bytesperline;
1552                 q_data->sizeimage[i]    = plane_fmt->sizeimage;
1553         }
1554 
1555         q_data->c_rect.left     = 0;
1556         q_data->c_rect.top      = 0;
1557         q_data->c_rect.width    = q_data->width;
1558         q_data->c_rect.height   = q_data->height;
1559 
1560         if (q_data->field == V4L2_FIELD_ALTERNATE)
1561                 q_data->flags |= Q_DATA_INTERLACED;
1562         else
1563                 q_data->flags &= ~Q_DATA_INTERLACED;
1564 
1565         vpe_dbg(ctx->dev, "Setting format for type %d, wxh: %dx%d, fmt: %d bpl_y %d",
1566                 f->type, q_data->width, q_data->height, q_data->fmt->fourcc,
1567                 q_data->bytesperline[VPE_LUMA]);
1568         if (q_data->fmt->coplanar)
1569                 vpe_dbg(ctx->dev, " bpl_uv %d\n",
1570                         q_data->bytesperline[VPE_CHROMA]);
1571 
1572         return 0;
1573 }
1574 
1575 static int vpe_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
1576 {
1577         int ret;
1578         struct vpe_ctx *ctx = file2ctx(file);
1579 
1580         ret = vpe_try_fmt(file, priv, f);
1581         if (ret)
1582                 return ret;
1583 
1584         ret = __vpe_s_fmt(ctx, f);
1585         if (ret)
1586                 return ret;
1587 
1588         if (V4L2_TYPE_IS_OUTPUT(f->type))
1589                 set_src_registers(ctx);
1590         else
1591                 set_dst_registers(ctx);
1592 
1593         return set_srcdst_params(ctx);
1594 }
1595 
1596 static int __vpe_try_selection(struct vpe_ctx *ctx, struct v4l2_selection *s)
1597 {
1598         struct vpe_q_data *q_data;
1599 
1600         if ((s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
1601             (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT))
1602                 return -EINVAL;
1603 
1604         q_data = get_q_data(ctx, s->type);
1605         if (!q_data)
1606                 return -EINVAL;
1607 
1608         switch (s->target) {
1609         case V4L2_SEL_TGT_COMPOSE:
1610                 /*
1611                  * COMPOSE target is only valid for capture buffer type, return
1612                  * error for output buffer type
1613                  */
1614                 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1615                         return -EINVAL;
1616                 break;
1617         case V4L2_SEL_TGT_CROP:
1618                 /*
1619                  * CROP target is only valid for output buffer type, return
1620                  * error for capture buffer type
1621                  */
1622                 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1623                         return -EINVAL;
1624                 break;
1625         /*
1626          * bound and default crop/compose targets are invalid targets to
1627          * try/set
1628          */
1629         default:
1630                 return -EINVAL;
1631         }
1632 
1633         if (s->r.top < 0 || s->r.left < 0) {
1634                 vpe_err(ctx->dev, "negative values for top and left\n");
1635                 s->r.top = s->r.left = 0;
1636         }
1637 
1638         v4l_bound_align_image(&s->r.width, MIN_W, q_data->width, 1,
1639                 &s->r.height, MIN_H, q_data->height, H_ALIGN, S_ALIGN);
1640 
1641         /* adjust left/top if cropping rectangle is out of bounds */
1642         if (s->r.left + s->r.width > q_data->width)
1643                 s->r.left = q_data->width - s->r.width;
1644         if (s->r.top + s->r.height > q_data->height)
1645                 s->r.top = q_data->height - s->r.height;
1646 
1647         return 0;
1648 }
1649 
1650 static int vpe_g_selection(struct file *file, void *fh,
1651                 struct v4l2_selection *s)
1652 {
1653         struct vpe_ctx *ctx = file2ctx(file);
1654         struct vpe_q_data *q_data;
1655         bool use_c_rect = false;
1656 
1657         if ((s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
1658             (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT))
1659                 return -EINVAL;
1660 
1661         q_data = get_q_data(ctx, s->type);
1662         if (!q_data)
1663                 return -EINVAL;
1664 
1665         switch (s->target) {
1666         case V4L2_SEL_TGT_COMPOSE_DEFAULT:
1667         case V4L2_SEL_TGT_COMPOSE_BOUNDS:
1668                 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1669                         return -EINVAL;
1670                 break;
1671         case V4L2_SEL_TGT_CROP_BOUNDS:
1672         case V4L2_SEL_TGT_CROP_DEFAULT:
1673                 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1674                         return -EINVAL;
1675                 break;
1676         case V4L2_SEL_TGT_COMPOSE:
1677                 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1678                         return -EINVAL;
1679                 use_c_rect = true;
1680                 break;
1681         case V4L2_SEL_TGT_CROP:
1682                 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1683                         return -EINVAL;
1684                 use_c_rect = true;
1685                 break;
1686         default:
1687                 return -EINVAL;
1688         }
1689 
1690         if (use_c_rect) {
1691                 /*
1692                  * for CROP/COMPOSE target type, return c_rect params from the
1693                  * respective buffer type
1694                  */
1695                 s->r = q_data->c_rect;
1696         } else {
1697                 /*
1698                  * for DEFAULT/BOUNDS target type, return width and height from
1699                  * S_FMT of the respective buffer type
1700                  */
1701                 s->r.left = 0;
1702                 s->r.top = 0;
1703                 s->r.width = q_data->width;
1704                 s->r.height = q_data->height;
1705         }
1706 
1707         return 0;
1708 }
1709 
1710 
1711 static int vpe_s_selection(struct file *file, void *fh,
1712                 struct v4l2_selection *s)
1713 {
1714         struct vpe_ctx *ctx = file2ctx(file);
1715         struct vpe_q_data *q_data;
1716         struct v4l2_selection sel = *s;
1717         int ret;
1718 
1719         ret = __vpe_try_selection(ctx, &sel);
1720         if (ret)
1721                 return ret;
1722 
1723         q_data = get_q_data(ctx, sel.type);
1724         if (!q_data)
1725                 return -EINVAL;
1726 
1727         if ((q_data->c_rect.left == sel.r.left) &&
1728                         (q_data->c_rect.top == sel.r.top) &&
1729                         (q_data->c_rect.width == sel.r.width) &&
1730                         (q_data->c_rect.height == sel.r.height)) {
1731                 vpe_dbg(ctx->dev,
1732                         "requested crop/compose values are already set\n");
1733                 return 0;
1734         }
1735 
1736         q_data->c_rect = sel.r;
1737 
1738         return set_srcdst_params(ctx);
1739 }
1740 
1741 static int vpe_reqbufs(struct file *file, void *priv,
1742                        struct v4l2_requestbuffers *reqbufs)
1743 {
1744         struct vpe_ctx *ctx = file2ctx(file);
1745 
1746         return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
1747 }
1748 
1749 static int vpe_querybuf(struct file *file, void *priv, struct v4l2_buffer *buf)
1750 {
1751         struct vpe_ctx *ctx = file2ctx(file);
1752 
1753         return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
1754 }
1755 
1756 static int vpe_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
1757 {
1758         struct vpe_ctx *ctx = file2ctx(file);
1759 
1760         return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
1761 }
1762 
1763 static int vpe_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
1764 {
1765         struct vpe_ctx *ctx = file2ctx(file);
1766 
1767         return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
1768 }
1769 
1770 static int vpe_streamon(struct file *file, void *priv, enum v4l2_buf_type type)
1771 {
1772         struct vpe_ctx *ctx = file2ctx(file);
1773 
1774         return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
1775 }
1776 
1777 static int vpe_streamoff(struct file *file, void *priv, enum v4l2_buf_type type)
1778 {
1779         struct vpe_ctx *ctx = file2ctx(file);
1780 
1781         vpe_dump_regs(ctx->dev);
1782         vpdma_dump_regs(ctx->dev->vpdma);
1783 
1784         return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
1785 }
1786 
1787 /*
1788  * defines number of buffers/frames a context can process with VPE before
1789  * switching to a different context. default value is 1 buffer per context
1790  */
1791 #define V4L2_CID_VPE_BUFS_PER_JOB               (V4L2_CID_USER_TI_VPE_BASE + 0)
1792 
1793 static int vpe_s_ctrl(struct v4l2_ctrl *ctrl)
1794 {
1795         struct vpe_ctx *ctx =
1796                 container_of(ctrl->handler, struct vpe_ctx, hdl);
1797 
1798         switch (ctrl->id) {
1799         case V4L2_CID_VPE_BUFS_PER_JOB:
1800                 ctx->bufs_per_job = ctrl->val;
1801                 break;
1802 
1803         default:
1804                 vpe_err(ctx->dev, "Invalid control\n");
1805                 return -EINVAL;
1806         }
1807 
1808         return 0;
1809 }
1810 
1811 static const struct v4l2_ctrl_ops vpe_ctrl_ops = {
1812         .s_ctrl = vpe_s_ctrl,
1813 };
1814 
1815 static const struct v4l2_ioctl_ops vpe_ioctl_ops = {
1816         .vidioc_querycap        = vpe_querycap,
1817 
1818         .vidioc_enum_fmt_vid_cap_mplane = vpe_enum_fmt,
1819         .vidioc_g_fmt_vid_cap_mplane    = vpe_g_fmt,
1820         .vidioc_try_fmt_vid_cap_mplane  = vpe_try_fmt,
1821         .vidioc_s_fmt_vid_cap_mplane    = vpe_s_fmt,
1822 
1823         .vidioc_enum_fmt_vid_out_mplane = vpe_enum_fmt,
1824         .vidioc_g_fmt_vid_out_mplane    = vpe_g_fmt,
1825         .vidioc_try_fmt_vid_out_mplane  = vpe_try_fmt,
1826         .vidioc_s_fmt_vid_out_mplane    = vpe_s_fmt,
1827 
1828         .vidioc_g_selection             = vpe_g_selection,
1829         .vidioc_s_selection             = vpe_s_selection,
1830 
1831         .vidioc_reqbufs         = vpe_reqbufs,
1832         .vidioc_querybuf        = vpe_querybuf,
1833 
1834         .vidioc_qbuf            = vpe_qbuf,
1835         .vidioc_dqbuf           = vpe_dqbuf,
1836 
1837         .vidioc_streamon        = vpe_streamon,
1838         .vidioc_streamoff       = vpe_streamoff,
1839         .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1840         .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1841 };
1842 
1843 /*
1844  * Queue operations
1845  */
1846 static int vpe_queue_setup(struct vb2_queue *vq,
1847                            const struct v4l2_format *fmt,
1848                            unsigned int *nbuffers, unsigned int *nplanes,
1849                            unsigned int sizes[], void *alloc_ctxs[])
1850 {
1851         int i;
1852         struct vpe_ctx *ctx = vb2_get_drv_priv(vq);
1853         struct vpe_q_data *q_data;
1854 
1855         q_data = get_q_data(ctx, vq->type);
1856 
1857         *nplanes = q_data->fmt->coplanar ? 2 : 1;
1858 
1859         for (i = 0; i < *nplanes; i++) {
1860                 sizes[i] = q_data->sizeimage[i];
1861                 alloc_ctxs[i] = ctx->dev->alloc_ctx;
1862         }
1863 
1864         vpe_dbg(ctx->dev, "get %d buffer(s) of size %d", *nbuffers,
1865                 sizes[VPE_LUMA]);
1866         if (q_data->fmt->coplanar)
1867                 vpe_dbg(ctx->dev, " and %d\n", sizes[VPE_CHROMA]);
1868 
1869         return 0;
1870 }
1871 
1872 static int vpe_buf_prepare(struct vb2_buffer *vb)
1873 {
1874         struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1875         struct vpe_q_data *q_data;
1876         int i, num_planes;
1877 
1878         vpe_dbg(ctx->dev, "type: %d\n", vb->vb2_queue->type);
1879 
1880         q_data = get_q_data(ctx, vb->vb2_queue->type);
1881         num_planes = q_data->fmt->coplanar ? 2 : 1;
1882 
1883         if (vb->vb2_queue->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1884                 if (!(q_data->flags & Q_DATA_INTERLACED)) {
1885                         vb->v4l2_buf.field = V4L2_FIELD_NONE;
1886                 } else {
1887                         if (vb->v4l2_buf.field != V4L2_FIELD_TOP &&
1888                                         vb->v4l2_buf.field != V4L2_FIELD_BOTTOM)
1889                                 return -EINVAL;
1890                 }
1891         }
1892 
1893         for (i = 0; i < num_planes; i++) {
1894                 if (vb2_plane_size(vb, i) < q_data->sizeimage[i]) {
1895                         vpe_err(ctx->dev,
1896                                 "data will not fit into plane (%lu < %lu)\n",
1897                                 vb2_plane_size(vb, i),
1898                                 (long) q_data->sizeimage[i]);
1899                         return -EINVAL;
1900                 }
1901         }
1902 
1903         for (i = 0; i < num_planes; i++)
1904                 vb2_set_plane_payload(vb, i, q_data->sizeimage[i]);
1905 
1906         return 0;
1907 }
1908 
1909 static void vpe_buf_queue(struct vb2_buffer *vb)
1910 {
1911         struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1912         v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
1913 }
1914 
1915 static void vpe_wait_prepare(struct vb2_queue *q)
1916 {
1917         struct vpe_ctx *ctx = vb2_get_drv_priv(q);
1918         vpe_unlock(ctx);
1919 }
1920 
1921 static void vpe_wait_finish(struct vb2_queue *q)
1922 {
1923         struct vpe_ctx *ctx = vb2_get_drv_priv(q);
1924         vpe_lock(ctx);
1925 }
1926 
1927 static struct vb2_ops vpe_qops = {
1928         .queue_setup     = vpe_queue_setup,
1929         .buf_prepare     = vpe_buf_prepare,
1930         .buf_queue       = vpe_buf_queue,
1931         .wait_prepare    = vpe_wait_prepare,
1932         .wait_finish     = vpe_wait_finish,
1933 };
1934 
1935 static int queue_init(void *priv, struct vb2_queue *src_vq,
1936                       struct vb2_queue *dst_vq)
1937 {
1938         struct vpe_ctx *ctx = priv;
1939         int ret;
1940 
1941         memset(src_vq, 0, sizeof(*src_vq));
1942         src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
1943         src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
1944         src_vq->drv_priv = ctx;
1945         src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1946         src_vq->ops = &vpe_qops;
1947         src_vq->mem_ops = &vb2_dma_contig_memops;
1948         src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
1949 
1950         ret = vb2_queue_init(src_vq);
1951         if (ret)
1952                 return ret;
1953 
1954         memset(dst_vq, 0, sizeof(*dst_vq));
1955         dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1956         dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
1957         dst_vq->drv_priv = ctx;
1958         dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1959         dst_vq->ops = &vpe_qops;
1960         dst_vq->mem_ops = &vb2_dma_contig_memops;
1961         dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
1962 
1963         return vb2_queue_init(dst_vq);
1964 }
1965 
1966 static const struct v4l2_ctrl_config vpe_bufs_per_job = {
1967         .ops = &vpe_ctrl_ops,
1968         .id = V4L2_CID_VPE_BUFS_PER_JOB,
1969         .name = "Buffers Per Transaction",
1970         .type = V4L2_CTRL_TYPE_INTEGER,
1971         .def = VPE_DEF_BUFS_PER_JOB,
1972         .min = 1,
1973         .max = VIDEO_MAX_FRAME,
1974         .step = 1,
1975 };
1976 
1977 /*
1978  * File operations
1979  */
1980 static int vpe_open(struct file *file)
1981 {
1982         struct vpe_dev *dev = video_drvdata(file);
1983         struct vpe_ctx *ctx = NULL;
1984         struct vpe_q_data *s_q_data;
1985         struct v4l2_ctrl_handler *hdl;
1986         int ret;
1987 
1988         vpe_dbg(dev, "vpe_open\n");
1989 
1990         ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
1991         if (!ctx)
1992                 return -ENOMEM;
1993 
1994         ctx->dev = dev;
1995 
1996         if (mutex_lock_interruptible(&dev->dev_mutex)) {
1997                 ret = -ERESTARTSYS;
1998                 goto free_ctx;
1999         }
2000 
2001         ret = vpdma_create_desc_list(&ctx->desc_list, VPE_DESC_LIST_SIZE,
2002                         VPDMA_LIST_TYPE_NORMAL);
2003         if (ret != 0)
2004                 goto unlock;
2005 
2006         ret = vpdma_alloc_desc_buf(&ctx->mmr_adb, sizeof(struct vpe_mmr_adb));
2007         if (ret != 0)
2008                 goto free_desc_list;
2009 
2010         ret = vpdma_alloc_desc_buf(&ctx->sc_coeff_h, SC_COEF_SRAM_SIZE);
2011         if (ret != 0)
2012                 goto free_mmr_adb;
2013 
2014         ret = vpdma_alloc_desc_buf(&ctx->sc_coeff_v, SC_COEF_SRAM_SIZE);
2015         if (ret != 0)
2016                 goto free_sc_h;
2017 
2018         init_adb_hdrs(ctx);
2019 
2020         v4l2_fh_init(&ctx->fh, video_devdata(file));
2021         file->private_data = &ctx->fh;
2022 
2023         hdl = &ctx->hdl;
2024         v4l2_ctrl_handler_init(hdl, 1);
2025         v4l2_ctrl_new_custom(hdl, &vpe_bufs_per_job, NULL);
2026         if (hdl->error) {
2027                 ret = hdl->error;
2028                 goto exit_fh;
2029         }
2030         ctx->fh.ctrl_handler = hdl;
2031         v4l2_ctrl_handler_setup(hdl);
2032 
2033         s_q_data = &ctx->q_data[Q_DATA_SRC];
2034         s_q_data->fmt = &vpe_formats[2];
2035         s_q_data->width = 1920;
2036         s_q_data->height = 1080;
2037         s_q_data->bytesperline[VPE_LUMA] = (s_q_data->width *
2038                         s_q_data->fmt->vpdma_fmt[VPE_LUMA]->depth) >> 3;
2039         s_q_data->sizeimage[VPE_LUMA] = (s_q_data->bytesperline[VPE_LUMA] *
2040                         s_q_data->height);
2041         s_q_data->colorspace = V4L2_COLORSPACE_REC709;
2042         s_q_data->field = V4L2_FIELD_NONE;
2043         s_q_data->c_rect.left = 0;
2044         s_q_data->c_rect.top = 0;
2045         s_q_data->c_rect.width = s_q_data->width;
2046         s_q_data->c_rect.height = s_q_data->height;
2047         s_q_data->flags = 0;
2048 
2049         ctx->q_data[Q_DATA_DST] = *s_q_data;
2050 
2051         set_dei_shadow_registers(ctx);
2052         set_src_registers(ctx);
2053         set_dst_registers(ctx);
2054         ret = set_srcdst_params(ctx);
2055         if (ret)
2056                 goto exit_fh;
2057 
2058         ctx->m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init);
2059 
2060         if (IS_ERR(ctx->m2m_ctx)) {
2061                 ret = PTR_ERR(ctx->m2m_ctx);
2062                 goto exit_fh;
2063         }
2064 
2065         v4l2_fh_add(&ctx->fh);
2066 
2067         /*
2068          * for now, just report the creation of the first instance, we can later
2069          * optimize the driver to enable or disable clocks when the first
2070          * instance is created or the last instance released
2071          */
2072         if (atomic_inc_return(&dev->num_instances) == 1)
2073                 vpe_dbg(dev, "first instance created\n");
2074 
2075         ctx->bufs_per_job = VPE_DEF_BUFS_PER_JOB;
2076 
2077         ctx->load_mmrs = true;
2078 
2079         vpe_dbg(dev, "created instance %p, m2m_ctx: %p\n",
2080                 ctx, ctx->m2m_ctx);
2081 
2082         mutex_unlock(&dev->dev_mutex);
2083 
2084         return 0;
2085 exit_fh:
2086         v4l2_ctrl_handler_free(hdl);
2087         v4l2_fh_exit(&ctx->fh);
2088         vpdma_free_desc_buf(&ctx->sc_coeff_v);
2089 free_sc_h:
2090         vpdma_free_desc_buf(&ctx->sc_coeff_h);
2091 free_mmr_adb:
2092         vpdma_free_desc_buf(&ctx->mmr_adb);
2093 free_desc_list:
2094         vpdma_free_desc_list(&ctx->desc_list);
2095 unlock:
2096         mutex_unlock(&dev->dev_mutex);
2097 free_ctx:
2098         kfree(ctx);
2099         return ret;
2100 }
2101 
2102 static int vpe_release(struct file *file)
2103 {
2104         struct vpe_dev *dev = video_drvdata(file);
2105         struct vpe_ctx *ctx = file2ctx(file);
2106 
2107         vpe_dbg(dev, "releasing instance %p\n", ctx);
2108 
2109         mutex_lock(&dev->dev_mutex);
2110         free_vbs(ctx);
2111         free_mv_buffers(ctx);
2112         vpdma_free_desc_list(&ctx->desc_list);
2113         vpdma_free_desc_buf(&ctx->mmr_adb);
2114 
2115         v4l2_fh_del(&ctx->fh);
2116         v4l2_fh_exit(&ctx->fh);
2117         v4l2_ctrl_handler_free(&ctx->hdl);
2118         v4l2_m2m_ctx_release(ctx->m2m_ctx);
2119 
2120         kfree(ctx);
2121 
2122         /*
2123          * for now, just report the release of the last instance, we can later
2124          * optimize the driver to enable or disable clocks when the first
2125          * instance is created or the last instance released
2126          */
2127         if (atomic_dec_return(&dev->num_instances) == 0)
2128                 vpe_dbg(dev, "last instance released\n");
2129 
2130         mutex_unlock(&dev->dev_mutex);
2131 
2132         return 0;
2133 }
2134 
2135 static unsigned int vpe_poll(struct file *file,
2136                              struct poll_table_struct *wait)
2137 {
2138         struct vpe_ctx *ctx = file2ctx(file);
2139         struct vpe_dev *dev = ctx->dev;
2140         int ret;
2141 
2142         mutex_lock(&dev->dev_mutex);
2143         ret = v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
2144         mutex_unlock(&dev->dev_mutex);
2145         return ret;
2146 }
2147 
2148 static int vpe_mmap(struct file *file, struct vm_area_struct *vma)
2149 {
2150         struct vpe_ctx *ctx = file2ctx(file);
2151         struct vpe_dev *dev = ctx->dev;
2152         int ret;
2153 
2154         if (mutex_lock_interruptible(&dev->dev_mutex))
2155                 return -ERESTARTSYS;
2156         ret = v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
2157         mutex_unlock(&dev->dev_mutex);
2158         return ret;
2159 }
2160 
2161 static const struct v4l2_file_operations vpe_fops = {
2162         .owner          = THIS_MODULE,
2163         .open           = vpe_open,
2164         .release        = vpe_release,
2165         .poll           = vpe_poll,
2166         .unlocked_ioctl = video_ioctl2,
2167         .mmap           = vpe_mmap,
2168 };
2169 
2170 static struct video_device vpe_videodev = {
2171         .name           = VPE_MODULE_NAME,
2172         .fops           = &vpe_fops,
2173         .ioctl_ops      = &vpe_ioctl_ops,
2174         .minor          = -1,
2175         .release        = video_device_release_empty,
2176         .vfl_dir        = VFL_DIR_M2M,
2177 };
2178 
2179 static struct v4l2_m2m_ops m2m_ops = {
2180         .device_run     = device_run,
2181         .job_ready      = job_ready,
2182         .job_abort      = job_abort,
2183         .lock           = vpe_lock,
2184         .unlock         = vpe_unlock,
2185 };
2186 
2187 static int vpe_runtime_get(struct platform_device *pdev)
2188 {
2189         int r;
2190 
2191         dev_dbg(&pdev->dev, "vpe_runtime_get\n");
2192 
2193         r = pm_runtime_get_sync(&pdev->dev);
2194         WARN_ON(r < 0);
2195         return r < 0 ? r : 0;
2196 }
2197 
2198 static void vpe_runtime_put(struct platform_device *pdev)
2199 {
2200 
2201         int r;
2202 
2203         dev_dbg(&pdev->dev, "vpe_runtime_put\n");
2204 
2205         r = pm_runtime_put_sync(&pdev->dev);
2206         WARN_ON(r < 0 && r != -ENOSYS);
2207 }
2208 
2209 static void vpe_fw_cb(struct platform_device *pdev)
2210 {
2211         struct vpe_dev *dev = platform_get_drvdata(pdev);
2212         struct video_device *vfd;
2213         int ret;
2214 
2215         vfd = &dev->vfd;
2216         *vfd = vpe_videodev;
2217         vfd->lock = &dev->dev_mutex;
2218         vfd->v4l2_dev = &dev->v4l2_dev;
2219 
2220         ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
2221         if (ret) {
2222                 vpe_err(dev, "Failed to register video device\n");
2223 
2224                 vpe_set_clock_enable(dev, 0);
2225                 vpe_runtime_put(pdev);
2226                 pm_runtime_disable(&pdev->dev);
2227                 v4l2_m2m_release(dev->m2m_dev);
2228                 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
2229                 v4l2_device_unregister(&dev->v4l2_dev);
2230 
2231                 return;
2232         }
2233 
2234         video_set_drvdata(vfd, dev);
2235         snprintf(vfd->name, sizeof(vfd->name), "%s", vpe_videodev.name);
2236         dev_info(dev->v4l2_dev.dev, "Device registered as /dev/video%d\n",
2237                 vfd->num);
2238 }
2239 
2240 static int vpe_probe(struct platform_device *pdev)
2241 {
2242         struct vpe_dev *dev;
2243         int ret, irq, func;
2244 
2245         dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
2246         if (!dev)
2247                 return -ENOMEM;
2248 
2249         spin_lock_init(&dev->lock);
2250 
2251         ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
2252         if (ret)
2253                 return ret;
2254 
2255         atomic_set(&dev->num_instances, 0);
2256         mutex_init(&dev->dev_mutex);
2257 
2258         dev->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2259                         "vpe_top");
2260         /*
2261          * HACK: we get resource info from device tree in the form of a list of
2262          * VPE sub blocks, the driver currently uses only the base of vpe_top
2263          * for register access, the driver should be changed later to access
2264          * registers based on the sub block base addresses
2265          */
2266         dev->base = devm_ioremap(&pdev->dev, dev->res->start, SZ_32K);
2267         if (!dev->base) {
2268                 ret = -ENOMEM;
2269                 goto v4l2_dev_unreg;
2270         }
2271 
2272         irq = platform_get_irq(pdev, 0);
2273         ret = devm_request_irq(&pdev->dev, irq, vpe_irq, 0, VPE_MODULE_NAME,
2274                         dev);
2275         if (ret)
2276                 goto v4l2_dev_unreg;
2277 
2278         platform_set_drvdata(pdev, dev);
2279 
2280         dev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
2281         if (IS_ERR(dev->alloc_ctx)) {
2282                 vpe_err(dev, "Failed to alloc vb2 context\n");
2283                 ret = PTR_ERR(dev->alloc_ctx);
2284                 goto v4l2_dev_unreg;
2285         }
2286 
2287         dev->m2m_dev = v4l2_m2m_init(&m2m_ops);
2288         if (IS_ERR(dev->m2m_dev)) {
2289                 vpe_err(dev, "Failed to init mem2mem device\n");
2290                 ret = PTR_ERR(dev->m2m_dev);
2291                 goto rel_ctx;
2292         }
2293 
2294         pm_runtime_enable(&pdev->dev);
2295 
2296         ret = vpe_runtime_get(pdev);
2297         if (ret)
2298                 goto rel_m2m;
2299 
2300         /* Perform clk enable followed by reset */
2301         vpe_set_clock_enable(dev, 1);
2302 
2303         vpe_top_reset(dev);
2304 
2305         func = read_field_reg(dev, VPE_PID, VPE_PID_FUNC_MASK,
2306                 VPE_PID_FUNC_SHIFT);
2307         vpe_dbg(dev, "VPE PID function %x\n", func);
2308 
2309         vpe_top_vpdma_reset(dev);
2310 
2311         dev->sc = sc_create(pdev);
2312         if (IS_ERR(dev->sc)) {
2313                 ret = PTR_ERR(dev->sc);
2314                 goto runtime_put;
2315         }
2316 
2317         dev->csc = csc_create(pdev);
2318         if (IS_ERR(dev->csc)) {
2319                 ret = PTR_ERR(dev->csc);
2320                 goto runtime_put;
2321         }
2322 
2323         dev->vpdma = vpdma_create(pdev, vpe_fw_cb);
2324         if (IS_ERR(dev->vpdma)) {
2325                 ret = PTR_ERR(dev->vpdma);
2326                 goto runtime_put;
2327         }
2328 
2329         return 0;
2330 
2331 runtime_put:
2332         vpe_runtime_put(pdev);
2333 rel_m2m:
2334         pm_runtime_disable(&pdev->dev);
2335         v4l2_m2m_release(dev->m2m_dev);
2336 rel_ctx:
2337         vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
2338 v4l2_dev_unreg:
2339         v4l2_device_unregister(&dev->v4l2_dev);
2340 
2341         return ret;
2342 }
2343 
2344 static int vpe_remove(struct platform_device *pdev)
2345 {
2346         struct vpe_dev *dev =
2347                 (struct vpe_dev *) platform_get_drvdata(pdev);
2348 
2349         v4l2_info(&dev->v4l2_dev, "Removing " VPE_MODULE_NAME);
2350 
2351         v4l2_m2m_release(dev->m2m_dev);
2352         video_unregister_device(&dev->vfd);
2353         v4l2_device_unregister(&dev->v4l2_dev);
2354         vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
2355 
2356         vpe_set_clock_enable(dev, 0);
2357         vpe_runtime_put(pdev);
2358         pm_runtime_disable(&pdev->dev);
2359 
2360         return 0;
2361 }
2362 
2363 #if defined(CONFIG_OF)
2364 static const struct of_device_id vpe_of_match[] = {
2365         {
2366                 .compatible = "ti,vpe",
2367         },
2368         {},
2369 };
2370 #else
2371 #define vpe_of_match NULL
2372 #endif
2373 
2374 static struct platform_driver vpe_pdrv = {
2375         .probe          = vpe_probe,
2376         .remove         = vpe_remove,
2377         .driver         = {
2378                 .name   = VPE_MODULE_NAME,
2379                 .owner  = THIS_MODULE,
2380                 .of_match_table = vpe_of_match,
2381         },
2382 };
2383 
2384 module_platform_driver(vpe_pdrv);
2385 
2386 MODULE_DESCRIPTION("TI VPE driver");
2387 MODULE_AUTHOR("Dale Farnsworth, <dale@farnsworth.org>");
2388 MODULE_LICENSE("GPL");
2389 

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