Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/drivers/media/platform/soc_camera/mx2_camera.c

  1 /*
  2  * V4L2 Driver for i.MX27 camera host
  3  *
  4  * Copyright (C) 2008, Sascha Hauer, Pengutronix
  5  * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography
  6  * Copyright (C) 2012, Javier Martin, Vista Silicon S.L.
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License, or
 11  * (at your option) any later version.
 12  */
 13 
 14 #include <linux/init.h>
 15 #include <linux/module.h>
 16 #include <linux/io.h>
 17 #include <linux/delay.h>
 18 #include <linux/slab.h>
 19 #include <linux/dma-mapping.h>
 20 #include <linux/errno.h>
 21 #include <linux/fs.h>
 22 #include <linux/gcd.h>
 23 #include <linux/interrupt.h>
 24 #include <linux/kernel.h>
 25 #include <linux/math64.h>
 26 #include <linux/mm.h>
 27 #include <linux/moduleparam.h>
 28 #include <linux/time.h>
 29 #include <linux/device.h>
 30 #include <linux/platform_device.h>
 31 #include <linux/clk.h>
 32 
 33 #include <media/v4l2-common.h>
 34 #include <media/v4l2-dev.h>
 35 #include <media/videobuf2-core.h>
 36 #include <media/videobuf2-dma-contig.h>
 37 #include <media/soc_camera.h>
 38 #include <media/soc_mediabus.h>
 39 
 40 #include <linux/videodev2.h>
 41 
 42 #include <linux/platform_data/camera-mx2.h>
 43 
 44 #include <asm/dma.h>
 45 
 46 #define MX2_CAM_DRV_NAME "mx2-camera"
 47 #define MX2_CAM_VERSION "0.0.6"
 48 #define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera"
 49 
 50 /* reset values */
 51 #define CSICR1_RESET_VAL        0x40000800
 52 #define CSICR2_RESET_VAL        0x0
 53 #define CSICR3_RESET_VAL        0x0
 54 
 55 /* csi control reg 1 */
 56 #define CSICR1_SWAP16_EN        (1 << 31)
 57 #define CSICR1_EXT_VSYNC        (1 << 30)
 58 #define CSICR1_EOF_INTEN        (1 << 29)
 59 #define CSICR1_PRP_IF_EN        (1 << 28)
 60 #define CSICR1_CCIR_MODE        (1 << 27)
 61 #define CSICR1_COF_INTEN        (1 << 26)
 62 #define CSICR1_SF_OR_INTEN      (1 << 25)
 63 #define CSICR1_RF_OR_INTEN      (1 << 24)
 64 #define CSICR1_STATFF_LEVEL     (3 << 22)
 65 #define CSICR1_STATFF_INTEN     (1 << 21)
 66 #define CSICR1_RXFF_LEVEL(l)    (((l) & 3) << 19)
 67 #define CSICR1_RXFF_INTEN       (1 << 18)
 68 #define CSICR1_SOF_POL          (1 << 17)
 69 #define CSICR1_SOF_INTEN        (1 << 16)
 70 #define CSICR1_MCLKDIV(d)       (((d) & 0xF) << 12)
 71 #define CSICR1_HSYNC_POL        (1 << 11)
 72 #define CSICR1_CCIR_EN          (1 << 10)
 73 #define CSICR1_MCLKEN           (1 << 9)
 74 #define CSICR1_FCC              (1 << 8)
 75 #define CSICR1_PACK_DIR         (1 << 7)
 76 #define CSICR1_CLR_STATFIFO     (1 << 6)
 77 #define CSICR1_CLR_RXFIFO       (1 << 5)
 78 #define CSICR1_GCLK_MODE        (1 << 4)
 79 #define CSICR1_INV_DATA         (1 << 3)
 80 #define CSICR1_INV_PCLK         (1 << 2)
 81 #define CSICR1_REDGE            (1 << 1)
 82 #define CSICR1_FMT_MASK         (CSICR1_PACK_DIR | CSICR1_SWAP16_EN)
 83 
 84 #define SHIFT_STATFF_LEVEL      22
 85 #define SHIFT_RXFF_LEVEL        19
 86 #define SHIFT_MCLKDIV           12
 87 
 88 #define SHIFT_FRMCNT            16
 89 
 90 #define CSICR1                  0x00
 91 #define CSICR2                  0x04
 92 #define CSISR                   0x08
 93 #define CSISTATFIFO             0x0c
 94 #define CSIRFIFO                0x10
 95 #define CSIRXCNT                0x14
 96 #define CSICR3                  0x1c
 97 #define CSIDMASA_STATFIFO       0x20
 98 #define CSIDMATA_STATFIFO       0x24
 99 #define CSIDMASA_FB1            0x28
100 #define CSIDMASA_FB2            0x2c
101 #define CSIFBUF_PARA            0x30
102 #define CSIIMAG_PARA            0x34
103 
104 /* EMMA PrP */
105 #define PRP_CNTL                        0x00
106 #define PRP_INTR_CNTL                   0x04
107 #define PRP_INTRSTATUS                  0x08
108 #define PRP_SOURCE_Y_PTR                0x0c
109 #define PRP_SOURCE_CB_PTR               0x10
110 #define PRP_SOURCE_CR_PTR               0x14
111 #define PRP_DEST_RGB1_PTR               0x18
112 #define PRP_DEST_RGB2_PTR               0x1c
113 #define PRP_DEST_Y_PTR                  0x20
114 #define PRP_DEST_CB_PTR                 0x24
115 #define PRP_DEST_CR_PTR                 0x28
116 #define PRP_SRC_FRAME_SIZE              0x2c
117 #define PRP_DEST_CH1_LINE_STRIDE        0x30
118 #define PRP_SRC_PIXEL_FORMAT_CNTL       0x34
119 #define PRP_CH1_PIXEL_FORMAT_CNTL       0x38
120 #define PRP_CH1_OUT_IMAGE_SIZE          0x3c
121 #define PRP_CH2_OUT_IMAGE_SIZE          0x40
122 #define PRP_SRC_LINE_STRIDE             0x44
123 #define PRP_CSC_COEF_012                0x48
124 #define PRP_CSC_COEF_345                0x4c
125 #define PRP_CSC_COEF_678                0x50
126 #define PRP_CH1_RZ_HORI_COEF1           0x54
127 #define PRP_CH1_RZ_HORI_COEF2           0x58
128 #define PRP_CH1_RZ_HORI_VALID           0x5c
129 #define PRP_CH1_RZ_VERT_COEF1           0x60
130 #define PRP_CH1_RZ_VERT_COEF2           0x64
131 #define PRP_CH1_RZ_VERT_VALID           0x68
132 #define PRP_CH2_RZ_HORI_COEF1           0x6c
133 #define PRP_CH2_RZ_HORI_COEF2           0x70
134 #define PRP_CH2_RZ_HORI_VALID           0x74
135 #define PRP_CH2_RZ_VERT_COEF1           0x78
136 #define PRP_CH2_RZ_VERT_COEF2           0x7c
137 #define PRP_CH2_RZ_VERT_VALID           0x80
138 
139 #define PRP_CNTL_CH1EN          (1 << 0)
140 #define PRP_CNTL_CH2EN          (1 << 1)
141 #define PRP_CNTL_CSIEN          (1 << 2)
142 #define PRP_CNTL_DATA_IN_YUV420 (0 << 3)
143 #define PRP_CNTL_DATA_IN_YUV422 (1 << 3)
144 #define PRP_CNTL_DATA_IN_RGB16  (2 << 3)
145 #define PRP_CNTL_DATA_IN_RGB32  (3 << 3)
146 #define PRP_CNTL_CH1_OUT_RGB8   (0 << 5)
147 #define PRP_CNTL_CH1_OUT_RGB16  (1 << 5)
148 #define PRP_CNTL_CH1_OUT_RGB32  (2 << 5)
149 #define PRP_CNTL_CH1_OUT_YUV422 (3 << 5)
150 #define PRP_CNTL_CH2_OUT_YUV420 (0 << 7)
151 #define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
152 #define PRP_CNTL_CH2_OUT_YUV444 (2 << 7)
153 #define PRP_CNTL_CH1_LEN        (1 << 9)
154 #define PRP_CNTL_CH2_LEN        (1 << 10)
155 #define PRP_CNTL_SKIP_FRAME     (1 << 11)
156 #define PRP_CNTL_SWRST          (1 << 12)
157 #define PRP_CNTL_CLKEN          (1 << 13)
158 #define PRP_CNTL_WEN            (1 << 14)
159 #define PRP_CNTL_CH1BYP         (1 << 15)
160 #define PRP_CNTL_IN_TSKIP(x)    ((x) << 16)
161 #define PRP_CNTL_CH1_TSKIP(x)   ((x) << 19)
162 #define PRP_CNTL_CH2_TSKIP(x)   ((x) << 22)
163 #define PRP_CNTL_INPUT_FIFO_LEVEL(x)    ((x) << 25)
164 #define PRP_CNTL_RZ_FIFO_LEVEL(x)       ((x) << 27)
165 #define PRP_CNTL_CH2B1EN        (1 << 29)
166 #define PRP_CNTL_CH2B2EN        (1 << 30)
167 #define PRP_CNTL_CH2FEN         (1 << 31)
168 
169 /* IRQ Enable and status register */
170 #define PRP_INTR_RDERR          (1 << 0)
171 #define PRP_INTR_CH1WERR        (1 << 1)
172 #define PRP_INTR_CH2WERR        (1 << 2)
173 #define PRP_INTR_CH1FC          (1 << 3)
174 #define PRP_INTR_CH2FC          (1 << 5)
175 #define PRP_INTR_LBOVF          (1 << 7)
176 #define PRP_INTR_CH2OVF         (1 << 8)
177 
178 /* Resizing registers */
179 #define PRP_RZ_VALID_TBL_LEN(x) ((x) << 24)
180 #define PRP_RZ_VALID_BILINEAR   (1 << 31)
181 
182 #define MAX_VIDEO_MEM   16
183 
184 #define RESIZE_NUM_MIN  1
185 #define RESIZE_NUM_MAX  20
186 #define BC_COEF         3
187 #define SZ_COEF         (1 << BC_COEF)
188 
189 #define RESIZE_DIR_H    0
190 #define RESIZE_DIR_V    1
191 
192 #define RESIZE_ALGO_BILINEAR 0
193 #define RESIZE_ALGO_AVERAGING 1
194 
195 struct mx2_prp_cfg {
196         int channel;
197         u32 in_fmt;
198         u32 out_fmt;
199         u32 src_pixel;
200         u32 ch1_pixel;
201         u32 irq_flags;
202         u32 csicr1;
203 };
204 
205 /* prp resizing parameters */
206 struct emma_prp_resize {
207         int             algo; /* type of algorithm used */
208         int             len; /* number of coefficients */
209         unsigned char   s[RESIZE_NUM_MAX]; /* table of coefficients */
210 };
211 
212 /* prp configuration for a client-host fmt pair */
213 struct mx2_fmt_cfg {
214         enum v4l2_mbus_pixelcode        in_fmt;
215         u32                             out_fmt;
216         struct mx2_prp_cfg              cfg;
217 };
218 
219 struct mx2_buf_internal {
220         struct list_head        queue;
221         int                     bufnum;
222         bool                    discard;
223 };
224 
225 /* buffer for one video frame */
226 struct mx2_buffer {
227         /* common v4l buffer stuff -- must be first */
228         struct vb2_buffer               vb;
229         struct mx2_buf_internal         internal;
230 };
231 
232 enum mx2_camera_type {
233         IMX27_CAMERA,
234 };
235 
236 struct mx2_camera_dev {
237         struct device           *dev;
238         struct soc_camera_host  soc_host;
239         struct clk              *clk_emma_ahb, *clk_emma_ipg;
240         struct clk              *clk_csi_ahb, *clk_csi_per;
241 
242         void __iomem            *base_csi, *base_emma;
243 
244         struct mx2_camera_platform_data *pdata;
245         unsigned long           platform_flags;
246 
247         struct list_head        capture;
248         struct list_head        active_bufs;
249         struct list_head        discard;
250 
251         spinlock_t              lock;
252 
253         int                     dma;
254         struct mx2_buffer       *active;
255         struct mx2_buffer       *fb1_active;
256         struct mx2_buffer       *fb2_active;
257 
258         u32                     csicr1;
259         enum mx2_camera_type    devtype;
260 
261         struct mx2_buf_internal buf_discard[2];
262         void                    *discard_buffer;
263         dma_addr_t              discard_buffer_dma;
264         size_t                  discard_size;
265         struct mx2_fmt_cfg      *emma_prp;
266         struct emma_prp_resize  resizing[2];
267         unsigned int            s_width, s_height;
268         u32                     frame_count;
269         struct vb2_alloc_ctx    *alloc_ctx;
270 };
271 
272 static struct platform_device_id mx2_camera_devtype[] = {
273         {
274                 .name = "imx27-camera",
275                 .driver_data = IMX27_CAMERA,
276         }, {
277                 /* sentinel */
278         }
279 };
280 MODULE_DEVICE_TABLE(platform, mx2_camera_devtype);
281 
282 static struct mx2_buffer *mx2_ibuf_to_buf(struct mx2_buf_internal *int_buf)
283 {
284         return container_of(int_buf, struct mx2_buffer, internal);
285 }
286 
287 static struct mx2_fmt_cfg mx27_emma_prp_table[] = {
288         /*
289          * This is a generic configuration which is valid for most
290          * prp input-output format combinations.
291          * We set the incoming and outgoing pixelformat to a
292          * 16 Bit wide format and adjust the bytesperline
293          * accordingly. With this configuration the inputdata
294          * will not be changed by the emma and could be any type
295          * of 16 Bit Pixelformat.
296          */
297         {
298                 .in_fmt         = 0,
299                 .out_fmt        = 0,
300                 .cfg            = {
301                         .channel        = 1,
302                         .in_fmt         = PRP_CNTL_DATA_IN_RGB16,
303                         .out_fmt        = PRP_CNTL_CH1_OUT_RGB16,
304                         .src_pixel      = 0x2ca00565, /* RGB565 */
305                         .ch1_pixel      = 0x2ca00565, /* RGB565 */
306                         .irq_flags      = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
307                                                 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
308                         .csicr1         = 0,
309                 }
310         },
311         {
312                 .in_fmt         = V4L2_MBUS_FMT_UYVY8_2X8,
313                 .out_fmt        = V4L2_PIX_FMT_YUYV,
314                 .cfg            = {
315                         .channel        = 1,
316                         .in_fmt         = PRP_CNTL_DATA_IN_YUV422,
317                         .out_fmt        = PRP_CNTL_CH1_OUT_YUV422,
318                         .src_pixel      = 0x22000888, /* YUV422 (YUYV) */
319                         .ch1_pixel      = 0x62000888, /* YUV422 (YUYV) */
320                         .irq_flags      = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
321                                                 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
322                         .csicr1         = CSICR1_SWAP16_EN,
323                 }
324         },
325         {
326                 .in_fmt         = V4L2_MBUS_FMT_YUYV8_2X8,
327                 .out_fmt        = V4L2_PIX_FMT_YUYV,
328                 .cfg            = {
329                         .channel        = 1,
330                         .in_fmt         = PRP_CNTL_DATA_IN_YUV422,
331                         .out_fmt        = PRP_CNTL_CH1_OUT_YUV422,
332                         .src_pixel      = 0x22000888, /* YUV422 (YUYV) */
333                         .ch1_pixel      = 0x62000888, /* YUV422 (YUYV) */
334                         .irq_flags      = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
335                                                 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
336                         .csicr1         = CSICR1_PACK_DIR,
337                 }
338         },
339         {
340                 .in_fmt         = V4L2_MBUS_FMT_YUYV8_2X8,
341                 .out_fmt        = V4L2_PIX_FMT_YUV420,
342                 .cfg            = {
343                         .channel        = 2,
344                         .in_fmt         = PRP_CNTL_DATA_IN_YUV422,
345                         .out_fmt        = PRP_CNTL_CH2_OUT_YUV420,
346                         .src_pixel      = 0x22000888, /* YUV422 (YUYV) */
347                         .irq_flags      = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
348                                         PRP_INTR_CH2FC | PRP_INTR_LBOVF |
349                                         PRP_INTR_CH2OVF,
350                         .csicr1         = CSICR1_PACK_DIR,
351                 }
352         },
353         {
354                 .in_fmt         = V4L2_MBUS_FMT_UYVY8_2X8,
355                 .out_fmt        = V4L2_PIX_FMT_YUV420,
356                 .cfg            = {
357                         .channel        = 2,
358                         .in_fmt         = PRP_CNTL_DATA_IN_YUV422,
359                         .out_fmt        = PRP_CNTL_CH2_OUT_YUV420,
360                         .src_pixel      = 0x22000888, /* YUV422 (YUYV) */
361                         .irq_flags      = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
362                                         PRP_INTR_CH2FC | PRP_INTR_LBOVF |
363                                         PRP_INTR_CH2OVF,
364                         .csicr1         = CSICR1_SWAP16_EN,
365                 }
366         },
367 };
368 
369 static struct mx2_fmt_cfg *mx27_emma_prp_get_format(
370                                         enum v4l2_mbus_pixelcode in_fmt,
371                                         u32 out_fmt)
372 {
373         int i;
374 
375         for (i = 1; i < ARRAY_SIZE(mx27_emma_prp_table); i++)
376                 if ((mx27_emma_prp_table[i].in_fmt == in_fmt) &&
377                                 (mx27_emma_prp_table[i].out_fmt == out_fmt)) {
378                         return &mx27_emma_prp_table[i];
379                 }
380         /* If no match return the most generic configuration */
381         return &mx27_emma_prp_table[0];
382 };
383 
384 static void mx27_update_emma_buf(struct mx2_camera_dev *pcdev,
385                                  unsigned long phys, int bufnum)
386 {
387         struct mx2_fmt_cfg *prp = pcdev->emma_prp;
388 
389         if (prp->cfg.channel == 1) {
390                 writel(phys, pcdev->base_emma +
391                                 PRP_DEST_RGB1_PTR + 4 * bufnum);
392         } else {
393                 writel(phys, pcdev->base_emma +
394                         PRP_DEST_Y_PTR - 0x14 * bufnum);
395                 if (prp->out_fmt == V4L2_PIX_FMT_YUV420) {
396                         u32 imgsize = pcdev->soc_host.icd->user_height *
397                                         pcdev->soc_host.icd->user_width;
398 
399                         writel(phys + imgsize, pcdev->base_emma +
400                                 PRP_DEST_CB_PTR - 0x14 * bufnum);
401                         writel(phys + ((5 * imgsize) / 4), pcdev->base_emma +
402                                 PRP_DEST_CR_PTR - 0x14 * bufnum);
403                 }
404         }
405 }
406 
407 static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev)
408 {
409         clk_disable_unprepare(pcdev->clk_csi_ahb);
410         clk_disable_unprepare(pcdev->clk_csi_per);
411         writel(0, pcdev->base_csi + CSICR1);
412         writel(0, pcdev->base_emma + PRP_CNTL);
413 }
414 
415 static int mx2_camera_add_device(struct soc_camera_device *icd)
416 {
417         dev_info(icd->parent, "Camera driver attached to camera %d\n",
418                  icd->devnum);
419 
420         return 0;
421 }
422 
423 static void mx2_camera_remove_device(struct soc_camera_device *icd)
424 {
425         dev_info(icd->parent, "Camera driver detached from camera %d\n",
426                  icd->devnum);
427 }
428 
429 /*
430  * The following two functions absolutely depend on the fact, that
431  * there can be only one camera on mx2 camera sensor interface
432  */
433 static int mx2_camera_clock_start(struct soc_camera_host *ici)
434 {
435         struct mx2_camera_dev *pcdev = ici->priv;
436         int ret;
437         u32 csicr1;
438 
439         ret = clk_prepare_enable(pcdev->clk_csi_ahb);
440         if (ret < 0)
441                 return ret;
442 
443         ret = clk_prepare_enable(pcdev->clk_csi_per);
444         if (ret < 0)
445                 goto exit_csi_ahb;
446 
447         csicr1 = CSICR1_MCLKEN | CSICR1_PRP_IF_EN | CSICR1_FCC |
448                 CSICR1_RXFF_LEVEL(0);
449 
450         pcdev->csicr1 = csicr1;
451         writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
452 
453         pcdev->frame_count = 0;
454 
455         return 0;
456 
457 exit_csi_ahb:
458         clk_disable_unprepare(pcdev->clk_csi_ahb);
459 
460         return ret;
461 }
462 
463 static void mx2_camera_clock_stop(struct soc_camera_host *ici)
464 {
465         struct mx2_camera_dev *pcdev = ici->priv;
466 
467         mx2_camera_deactivate(pcdev);
468 }
469 
470 /*
471  *  Videobuf operations
472  */
473 static int mx2_videobuf_setup(struct vb2_queue *vq,
474                         const struct v4l2_format *fmt,
475                         unsigned int *count, unsigned int *num_planes,
476                         unsigned int sizes[], void *alloc_ctxs[])
477 {
478         struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
479         struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
480         struct mx2_camera_dev *pcdev = ici->priv;
481 
482         dev_dbg(icd->parent, "count=%d, size=%d\n", *count, sizes[0]);
483 
484         /* TODO: support for VIDIOC_CREATE_BUFS not ready */
485         if (fmt != NULL)
486                 return -ENOTTY;
487 
488         alloc_ctxs[0] = pcdev->alloc_ctx;
489 
490         sizes[0] = icd->sizeimage;
491 
492         if (0 == *count)
493                 *count = 32;
494         if (!*num_planes &&
495             sizes[0] * *count > MAX_VIDEO_MEM * 1024 * 1024)
496                 *count = (MAX_VIDEO_MEM * 1024 * 1024) / sizes[0];
497 
498         *num_planes = 1;
499 
500         return 0;
501 }
502 
503 static int mx2_videobuf_prepare(struct vb2_buffer *vb)
504 {
505         struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
506         int ret = 0;
507 
508         dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
509                 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
510 
511 #ifdef DEBUG
512         /*
513          * This can be useful if you want to see if we actually fill
514          * the buffer with something
515          */
516         memset((void *)vb2_plane_vaddr(vb, 0),
517                0xaa, vb2_get_plane_payload(vb, 0));
518 #endif
519 
520         vb2_set_plane_payload(vb, 0, icd->sizeimage);
521         if (vb2_plane_vaddr(vb, 0) &&
522             vb2_get_plane_payload(vb, 0) > vb2_plane_size(vb, 0)) {
523                 ret = -EINVAL;
524                 goto out;
525         }
526 
527         return 0;
528 
529 out:
530         return ret;
531 }
532 
533 static void mx2_videobuf_queue(struct vb2_buffer *vb)
534 {
535         struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
536         struct soc_camera_host *ici =
537                 to_soc_camera_host(icd->parent);
538         struct mx2_camera_dev *pcdev = ici->priv;
539         struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
540         unsigned long flags;
541 
542         dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
543                 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
544 
545         spin_lock_irqsave(&pcdev->lock, flags);
546 
547         list_add_tail(&buf->internal.queue, &pcdev->capture);
548 
549         spin_unlock_irqrestore(&pcdev->lock, flags);
550 }
551 
552 static void mx27_camera_emma_buf_init(struct soc_camera_device *icd,
553                 int bytesperline)
554 {
555         struct soc_camera_host *ici =
556                 to_soc_camera_host(icd->parent);
557         struct mx2_camera_dev *pcdev = ici->priv;
558         struct mx2_fmt_cfg *prp = pcdev->emma_prp;
559 
560         writel((pcdev->s_width << 16) | pcdev->s_height,
561                pcdev->base_emma + PRP_SRC_FRAME_SIZE);
562         writel(prp->cfg.src_pixel,
563                pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL);
564         if (prp->cfg.channel == 1) {
565                 writel((icd->user_width << 16) | icd->user_height,
566                         pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE);
567                 writel(bytesperline,
568                         pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE);
569                 writel(prp->cfg.ch1_pixel,
570                         pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL);
571         } else { /* channel 2 */
572                 writel((icd->user_width << 16) | icd->user_height,
573                         pcdev->base_emma + PRP_CH2_OUT_IMAGE_SIZE);
574         }
575 
576         /* Enable interrupts */
577         writel(prp->cfg.irq_flags, pcdev->base_emma + PRP_INTR_CNTL);
578 }
579 
580 static void mx2_prp_resize_commit(struct mx2_camera_dev *pcdev)
581 {
582         int dir;
583 
584         for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) {
585                 unsigned char *s = pcdev->resizing[dir].s;
586                 int len = pcdev->resizing[dir].len;
587                 unsigned int coeff[2] = {0, 0};
588                 unsigned int valid  = 0;
589                 int i;
590 
591                 if (len == 0)
592                         continue;
593 
594                 for (i = RESIZE_NUM_MAX - 1; i >= 0; i--) {
595                         int j;
596 
597                         j = i > 9 ? 1 : 0;
598                         coeff[j] = (coeff[j] << BC_COEF) |
599                                         (s[i] & (SZ_COEF - 1));
600 
601                         if (i == 5 || i == 15)
602                                 coeff[j] <<= 1;
603 
604                         valid = (valid << 1) | (s[i] >> BC_COEF);
605                 }
606 
607                 valid |= PRP_RZ_VALID_TBL_LEN(len);
608 
609                 if (pcdev->resizing[dir].algo == RESIZE_ALGO_BILINEAR)
610                         valid |= PRP_RZ_VALID_BILINEAR;
611 
612                 if (pcdev->emma_prp->cfg.channel == 1) {
613                         if (dir == RESIZE_DIR_H) {
614                                 writel(coeff[0], pcdev->base_emma +
615                                                         PRP_CH1_RZ_HORI_COEF1);
616                                 writel(coeff[1], pcdev->base_emma +
617                                                         PRP_CH1_RZ_HORI_COEF2);
618                                 writel(valid, pcdev->base_emma +
619                                                         PRP_CH1_RZ_HORI_VALID);
620                         } else {
621                                 writel(coeff[0], pcdev->base_emma +
622                                                         PRP_CH1_RZ_VERT_COEF1);
623                                 writel(coeff[1], pcdev->base_emma +
624                                                         PRP_CH1_RZ_VERT_COEF2);
625                                 writel(valid, pcdev->base_emma +
626                                                         PRP_CH1_RZ_VERT_VALID);
627                         }
628                 } else {
629                         if (dir == RESIZE_DIR_H) {
630                                 writel(coeff[0], pcdev->base_emma +
631                                                         PRP_CH2_RZ_HORI_COEF1);
632                                 writel(coeff[1], pcdev->base_emma +
633                                                         PRP_CH2_RZ_HORI_COEF2);
634                                 writel(valid, pcdev->base_emma +
635                                                         PRP_CH2_RZ_HORI_VALID);
636                         } else {
637                                 writel(coeff[0], pcdev->base_emma +
638                                                         PRP_CH2_RZ_VERT_COEF1);
639                                 writel(coeff[1], pcdev->base_emma +
640                                                         PRP_CH2_RZ_VERT_COEF2);
641                                 writel(valid, pcdev->base_emma +
642                                                         PRP_CH2_RZ_VERT_VALID);
643                         }
644                 }
645         }
646 }
647 
648 static int mx2_start_streaming(struct vb2_queue *q, unsigned int count)
649 {
650         struct soc_camera_device *icd = soc_camera_from_vb2q(q);
651         struct soc_camera_host *ici =
652                 to_soc_camera_host(icd->parent);
653         struct mx2_camera_dev *pcdev = ici->priv;
654         struct mx2_fmt_cfg *prp = pcdev->emma_prp;
655         struct vb2_buffer *vb;
656         struct mx2_buffer *buf;
657         unsigned long phys;
658         int bytesperline;
659         unsigned long flags;
660 
661         if (count < 2)
662                 return -ENOBUFS;
663 
664         spin_lock_irqsave(&pcdev->lock, flags);
665 
666         buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
667                                internal.queue);
668         buf->internal.bufnum = 0;
669         vb = &buf->vb;
670 
671         phys = vb2_dma_contig_plane_dma_addr(vb, 0);
672         mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
673         list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
674 
675         buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
676                                internal.queue);
677         buf->internal.bufnum = 1;
678         vb = &buf->vb;
679 
680         phys = vb2_dma_contig_plane_dma_addr(vb, 0);
681         mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
682         list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
683 
684         bytesperline = soc_mbus_bytes_per_line(icd->user_width,
685                                                icd->current_fmt->host_fmt);
686         if (bytesperline < 0) {
687                 spin_unlock_irqrestore(&pcdev->lock, flags);
688                 return bytesperline;
689         }
690 
691         /*
692          * I didn't manage to properly enable/disable the prp
693          * on a per frame basis during running transfers,
694          * thus we allocate a buffer here and use it to
695          * discard frames when no buffer is available.
696          * Feel free to work on this ;)
697          */
698         pcdev->discard_size = icd->user_height * bytesperline;
699         pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev,
700                                         pcdev->discard_size,
701                                         &pcdev->discard_buffer_dma, GFP_ATOMIC);
702         if (!pcdev->discard_buffer) {
703                 spin_unlock_irqrestore(&pcdev->lock, flags);
704                 return -ENOMEM;
705         }
706 
707         pcdev->buf_discard[0].discard = true;
708         list_add_tail(&pcdev->buf_discard[0].queue,
709                       &pcdev->discard);
710 
711         pcdev->buf_discard[1].discard = true;
712         list_add_tail(&pcdev->buf_discard[1].queue,
713                       &pcdev->discard);
714 
715         mx2_prp_resize_commit(pcdev);
716 
717         mx27_camera_emma_buf_init(icd, bytesperline);
718 
719         if (prp->cfg.channel == 1) {
720                 writel(PRP_CNTL_CH1EN |
721                        PRP_CNTL_CSIEN |
722                        prp->cfg.in_fmt |
723                        prp->cfg.out_fmt |
724                        PRP_CNTL_CH1_LEN |
725                        PRP_CNTL_CH1BYP |
726                        PRP_CNTL_CH1_TSKIP(0) |
727                        PRP_CNTL_IN_TSKIP(0),
728                        pcdev->base_emma + PRP_CNTL);
729         } else {
730                 writel(PRP_CNTL_CH2EN |
731                        PRP_CNTL_CSIEN |
732                        prp->cfg.in_fmt |
733                        prp->cfg.out_fmt |
734                        PRP_CNTL_CH2_LEN |
735                        PRP_CNTL_CH2_TSKIP(0) |
736                        PRP_CNTL_IN_TSKIP(0),
737                        pcdev->base_emma + PRP_CNTL);
738         }
739         spin_unlock_irqrestore(&pcdev->lock, flags);
740 
741         return 0;
742 }
743 
744 static void mx2_stop_streaming(struct vb2_queue *q)
745 {
746         struct soc_camera_device *icd = soc_camera_from_vb2q(q);
747         struct soc_camera_host *ici =
748                 to_soc_camera_host(icd->parent);
749         struct mx2_camera_dev *pcdev = ici->priv;
750         struct mx2_fmt_cfg *prp = pcdev->emma_prp;
751         unsigned long flags;
752         void *b;
753         u32 cntl;
754 
755         spin_lock_irqsave(&pcdev->lock, flags);
756 
757         cntl = readl(pcdev->base_emma + PRP_CNTL);
758         if (prp->cfg.channel == 1) {
759                 writel(cntl & ~PRP_CNTL_CH1EN,
760                        pcdev->base_emma + PRP_CNTL);
761         } else {
762                 writel(cntl & ~PRP_CNTL_CH2EN,
763                        pcdev->base_emma + PRP_CNTL);
764         }
765         INIT_LIST_HEAD(&pcdev->capture);
766         INIT_LIST_HEAD(&pcdev->active_bufs);
767         INIT_LIST_HEAD(&pcdev->discard);
768 
769         b = pcdev->discard_buffer;
770         pcdev->discard_buffer = NULL;
771 
772         spin_unlock_irqrestore(&pcdev->lock, flags);
773 
774         dma_free_coherent(ici->v4l2_dev.dev,
775                           pcdev->discard_size, b, pcdev->discard_buffer_dma);
776 }
777 
778 static struct vb2_ops mx2_videobuf_ops = {
779         .queue_setup     = mx2_videobuf_setup,
780         .buf_prepare     = mx2_videobuf_prepare,
781         .buf_queue       = mx2_videobuf_queue,
782         .start_streaming = mx2_start_streaming,
783         .stop_streaming  = mx2_stop_streaming,
784 };
785 
786 static int mx2_camera_init_videobuf(struct vb2_queue *q,
787                               struct soc_camera_device *icd)
788 {
789         q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
790         q->io_modes = VB2_MMAP | VB2_USERPTR;
791         q->drv_priv = icd;
792         q->ops = &mx2_videobuf_ops;
793         q->mem_ops = &vb2_dma_contig_memops;
794         q->buf_struct_size = sizeof(struct mx2_buffer);
795         q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
796 
797         return vb2_queue_init(q);
798 }
799 
800 #define MX2_BUS_FLAGS   (V4L2_MBUS_MASTER | \
801                         V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
802                         V4L2_MBUS_VSYNC_ACTIVE_LOW | \
803                         V4L2_MBUS_HSYNC_ACTIVE_HIGH | \
804                         V4L2_MBUS_HSYNC_ACTIVE_LOW | \
805                         V4L2_MBUS_PCLK_SAMPLE_RISING | \
806                         V4L2_MBUS_PCLK_SAMPLE_FALLING | \
807                         V4L2_MBUS_DATA_ACTIVE_HIGH | \
808                         V4L2_MBUS_DATA_ACTIVE_LOW)
809 
810 static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev)
811 {
812         int count = 0;
813 
814         readl(pcdev->base_emma + PRP_CNTL);
815         writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL);
816         while (count++ < 100) {
817                 if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST))
818                         return 0;
819                 barrier();
820                 udelay(1);
821         }
822 
823         return -ETIMEDOUT;
824 }
825 
826 static int mx2_camera_set_bus_param(struct soc_camera_device *icd)
827 {
828         struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
829         struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
830         struct mx2_camera_dev *pcdev = ici->priv;
831         struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
832         unsigned long common_flags;
833         int ret;
834         int bytesperline;
835         u32 csicr1 = pcdev->csicr1;
836 
837         ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
838         if (!ret) {
839                 common_flags = soc_mbus_config_compatible(&cfg, MX2_BUS_FLAGS);
840                 if (!common_flags) {
841                         dev_warn(icd->parent,
842                                  "Flags incompatible: camera 0x%x, host 0x%x\n",
843                                  cfg.flags, MX2_BUS_FLAGS);
844                         return -EINVAL;
845                 }
846         } else if (ret != -ENOIOCTLCMD) {
847                 return ret;
848         } else {
849                 common_flags = MX2_BUS_FLAGS;
850         }
851 
852         if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
853             (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
854                 if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH)
855                         common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
856                 else
857                         common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
858         }
859 
860         if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
861             (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
862                 if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING)
863                         common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
864                 else
865                         common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
866         }
867 
868         cfg.flags = common_flags;
869         ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
870         if (ret < 0 && ret != -ENOIOCTLCMD) {
871                 dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n",
872                         common_flags, ret);
873                 return ret;
874         }
875 
876         csicr1 = (csicr1 & ~CSICR1_FMT_MASK) | pcdev->emma_prp->cfg.csicr1;
877 
878         if (common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
879                 csicr1 |= CSICR1_REDGE;
880         if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
881                 csicr1 |= CSICR1_SOF_POL;
882         if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
883                 csicr1 |= CSICR1_HSYNC_POL;
884         if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC)
885                 csicr1 |= CSICR1_EXT_VSYNC;
886         if (pcdev->platform_flags & MX2_CAMERA_CCIR)
887                 csicr1 |= CSICR1_CCIR_EN;
888         if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE)
889                 csicr1 |= CSICR1_CCIR_MODE;
890         if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK)
891                 csicr1 |= CSICR1_GCLK_MODE;
892         if (pcdev->platform_flags & MX2_CAMERA_INV_DATA)
893                 csicr1 |= CSICR1_INV_DATA;
894 
895         pcdev->csicr1 = csicr1;
896 
897         bytesperline = soc_mbus_bytes_per_line(icd->user_width,
898                         icd->current_fmt->host_fmt);
899         if (bytesperline < 0)
900                 return bytesperline;
901 
902         ret = mx27_camera_emma_prp_reset(pcdev);
903         if (ret)
904                 return ret;
905 
906         writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
907 
908         return 0;
909 }
910 
911 static int mx2_camera_set_crop(struct soc_camera_device *icd,
912                                 const struct v4l2_crop *a)
913 {
914         struct v4l2_crop a_writable = *a;
915         struct v4l2_rect *rect = &a_writable.c;
916         struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
917         struct v4l2_mbus_framefmt mf;
918         int ret;
919 
920         soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
921         soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
922 
923         ret = v4l2_subdev_call(sd, video, s_crop, a);
924         if (ret < 0)
925                 return ret;
926 
927         /* The capture device might have changed its output  */
928         ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
929         if (ret < 0)
930                 return ret;
931 
932         dev_dbg(icd->parent, "Sensor cropped %dx%d\n",
933                 mf.width, mf.height);
934 
935         icd->user_width         = mf.width;
936         icd->user_height        = mf.height;
937 
938         return ret;
939 }
940 
941 static int mx2_camera_get_formats(struct soc_camera_device *icd,
942                                   unsigned int idx,
943                                   struct soc_camera_format_xlate *xlate)
944 {
945         struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
946         const struct soc_mbus_pixelfmt *fmt;
947         struct device *dev = icd->parent;
948         enum v4l2_mbus_pixelcode code;
949         int ret, formats = 0;
950 
951         ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
952         if (ret < 0)
953                 /* no more formats */
954                 return 0;
955 
956         fmt = soc_mbus_get_fmtdesc(code);
957         if (!fmt) {
958                 dev_err(dev, "Invalid format code #%u: %d\n", idx, code);
959                 return 0;
960         }
961 
962         if (code == V4L2_MBUS_FMT_YUYV8_2X8 ||
963             code == V4L2_MBUS_FMT_UYVY8_2X8) {
964                 formats++;
965                 if (xlate) {
966                         /*
967                          * CH2 can output YUV420 which is a standard format in
968                          * soc_mediabus.c
969                          */
970                         xlate->host_fmt =
971                                 soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_1_5X8);
972                         xlate->code     = code;
973                         dev_dbg(dev, "Providing host format %s for sensor code %d\n",
974                                xlate->host_fmt->name, code);
975                         xlate++;
976                 }
977         }
978 
979         if (code == V4L2_MBUS_FMT_UYVY8_2X8) {
980                 formats++;
981                 if (xlate) {
982                         xlate->host_fmt =
983                                 soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_2X8);
984                         xlate->code     = code;
985                         dev_dbg(dev, "Providing host format %s for sensor code %d\n",
986                                 xlate->host_fmt->name, code);
987                         xlate++;
988                 }
989         }
990 
991         /* Generic pass-trough */
992         formats++;
993         if (xlate) {
994                 xlate->host_fmt = fmt;
995                 xlate->code     = code;
996                 xlate++;
997         }
998         return formats;
999 }
1000 
1001 static int mx2_emmaprp_resize(struct mx2_camera_dev *pcdev,
1002                               struct v4l2_mbus_framefmt *mf_in,
1003                               struct v4l2_pix_format *pix_out, bool apply)
1004 {
1005         unsigned int num, den;
1006         unsigned long m;
1007         int i, dir;
1008 
1009         for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) {
1010                 struct emma_prp_resize tmprsz;
1011                 unsigned char *s = tmprsz.s;
1012                 int len = 0;
1013                 int in, out;
1014 
1015                 if (dir == RESIZE_DIR_H) {
1016                         in = mf_in->width;
1017                         out = pix_out->width;
1018                 } else {
1019                         in = mf_in->height;
1020                         out = pix_out->height;
1021                 }
1022 
1023                 if (in < out)
1024                         return -EINVAL;
1025                 else if (in == out)
1026                         continue;
1027 
1028                 /* Calculate ratio */
1029                 m = gcd(in, out);
1030                 num = in / m;
1031                 den = out / m;
1032                 if (num > RESIZE_NUM_MAX)
1033                         return -EINVAL;
1034 
1035                 if ((num >= 2 * den) && (den == 1) &&
1036                     (num < 9) && (!(num & 0x01))) {
1037                         int sum = 0;
1038                         int j;
1039 
1040                         /* Average scaling for >= 2:1 ratios */
1041                         /* Support can be added for num >=9 and odd values */
1042 
1043                         tmprsz.algo = RESIZE_ALGO_AVERAGING;
1044                         len = num;
1045 
1046                         for (i = 0; i < (len / 2); i++)
1047                                 s[i] = 8;
1048 
1049                         do {
1050                                 for (i = 0; i < (len / 2); i++) {
1051                                         s[i] = s[i] >> 1;
1052                                         sum = 0;
1053                                         for (j = 0; j < (len / 2); j++)
1054                                                 sum += s[j];
1055                                         if (sum == 4)
1056                                                 break;
1057                                 }
1058                         } while (sum != 4);
1059 
1060                         for (i = (len / 2); i < len; i++)
1061                                 s[i] = s[len - i - 1];
1062 
1063                         s[len - 1] |= SZ_COEF;
1064                 } else {
1065                         /* bilinear scaling for < 2:1 ratios */
1066                         int v; /* overflow counter */
1067                         int coeff, nxt; /* table output */
1068                         int in_pos_inc = 2 * den;
1069                         int out_pos = num;
1070                         int out_pos_inc = 2 * num;
1071                         int init_carry = num - den;
1072                         int carry = init_carry;
1073 
1074                         tmprsz.algo = RESIZE_ALGO_BILINEAR;
1075                         v = den + in_pos_inc;
1076                         do {
1077                                 coeff = v - out_pos;
1078                                 out_pos += out_pos_inc;
1079                                 carry += out_pos_inc;
1080                                 for (nxt = 0; v < out_pos; nxt++) {
1081                                         v += in_pos_inc;
1082                                         carry -= in_pos_inc;
1083                                 }
1084 
1085                                 if (len > RESIZE_NUM_MAX)
1086                                         return -EINVAL;
1087 
1088                                 coeff = ((coeff << BC_COEF) +
1089                                         (in_pos_inc >> 1)) / in_pos_inc;
1090 
1091                                 if (coeff >= (SZ_COEF - 1))
1092                                         coeff--;
1093 
1094                                 coeff |= SZ_COEF;
1095                                 s[len] = (unsigned char)coeff;
1096                                 len++;
1097 
1098                                 for (i = 1; i < nxt; i++) {
1099                                         if (len >= RESIZE_NUM_MAX)
1100                                                 return -EINVAL;
1101                                         s[len] = 0;
1102                                         len++;
1103                                 }
1104                         } while (carry != init_carry);
1105                 }
1106                 tmprsz.len = len;
1107                 if (dir == RESIZE_DIR_H)
1108                         mf_in->width = pix_out->width;
1109                 else
1110                         mf_in->height = pix_out->height;
1111 
1112                 if (apply)
1113                         memcpy(&pcdev->resizing[dir], &tmprsz, sizeof(tmprsz));
1114         }
1115         return 0;
1116 }
1117 
1118 static int mx2_camera_set_fmt(struct soc_camera_device *icd,
1119                                struct v4l2_format *f)
1120 {
1121         struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1122         struct mx2_camera_dev *pcdev = ici->priv;
1123         struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1124         const struct soc_camera_format_xlate *xlate;
1125         struct v4l2_pix_format *pix = &f->fmt.pix;
1126         struct v4l2_mbus_framefmt mf;
1127         int ret;
1128 
1129         dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n",
1130                 __func__, pix->width, pix->height);
1131 
1132         xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1133         if (!xlate) {
1134                 dev_warn(icd->parent, "Format %x not found\n",
1135                                 pix->pixelformat);
1136                 return -EINVAL;
1137         }
1138 
1139         mf.width        = pix->width;
1140         mf.height       = pix->height;
1141         mf.field        = pix->field;
1142         mf.colorspace   = pix->colorspace;
1143         mf.code         = xlate->code;
1144 
1145         ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
1146         if (ret < 0 && ret != -ENOIOCTLCMD)
1147                 return ret;
1148 
1149         /* Store width and height returned by the sensor for resizing */
1150         pcdev->s_width = mf.width;
1151         pcdev->s_height = mf.height;
1152         dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n",
1153                 __func__, pcdev->s_width, pcdev->s_height);
1154 
1155         pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code,
1156                                                    xlate->host_fmt->fourcc);
1157 
1158         memset(pcdev->resizing, 0, sizeof(pcdev->resizing));
1159         if ((mf.width != pix->width || mf.height != pix->height) &&
1160                 pcdev->emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) {
1161                 if (mx2_emmaprp_resize(pcdev, &mf, pix, true) < 0)
1162                         dev_dbg(icd->parent, "%s: can't resize\n", __func__);
1163         }
1164 
1165         if (mf.code != xlate->code)
1166                 return -EINVAL;
1167 
1168         pix->width              = mf.width;
1169         pix->height             = mf.height;
1170         pix->field              = mf.field;
1171         pix->colorspace         = mf.colorspace;
1172         icd->current_fmt        = xlate;
1173 
1174         dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n",
1175                 __func__, pix->width, pix->height);
1176 
1177         return 0;
1178 }
1179 
1180 static int mx2_camera_try_fmt(struct soc_camera_device *icd,
1181                                   struct v4l2_format *f)
1182 {
1183         struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1184         const struct soc_camera_format_xlate *xlate;
1185         struct v4l2_pix_format *pix = &f->fmt.pix;
1186         struct v4l2_mbus_framefmt mf;
1187         __u32 pixfmt = pix->pixelformat;
1188         struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1189         struct mx2_camera_dev *pcdev = ici->priv;
1190         struct mx2_fmt_cfg *emma_prp;
1191         int ret;
1192 
1193         dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n",
1194                 __func__, pix->width, pix->height);
1195 
1196         xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1197         if (pixfmt && !xlate) {
1198                 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
1199                 return -EINVAL;
1200         }
1201 
1202         /*
1203          * limit to MX27 hardware capabilities: width must be a multiple of 8 as
1204          * requested by the CSI. (Table 39-2 in the i.MX27 Reference Manual).
1205          */
1206         pix->width &= ~0x7;
1207 
1208         /* limit to sensor capabilities */
1209         mf.width        = pix->width;
1210         mf.height       = pix->height;
1211         mf.field        = pix->field;
1212         mf.colorspace   = pix->colorspace;
1213         mf.code         = xlate->code;
1214 
1215         ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
1216         if (ret < 0)
1217                 return ret;
1218 
1219         dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n",
1220                 __func__, pcdev->s_width, pcdev->s_height);
1221 
1222         /* If the sensor does not support image size try PrP resizing */
1223         emma_prp = mx27_emma_prp_get_format(xlate->code,
1224                                             xlate->host_fmt->fourcc);
1225 
1226         if ((mf.width != pix->width || mf.height != pix->height) &&
1227                 emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) {
1228                 if (mx2_emmaprp_resize(pcdev, &mf, pix, false) < 0)
1229                         dev_dbg(icd->parent, "%s: can't resize\n", __func__);
1230         }
1231 
1232         if (mf.field == V4L2_FIELD_ANY)
1233                 mf.field = V4L2_FIELD_NONE;
1234         /*
1235          * Driver supports interlaced images provided they have
1236          * both fields so that they can be processed as if they
1237          * were progressive.
1238          */
1239         if (mf.field != V4L2_FIELD_NONE && !V4L2_FIELD_HAS_BOTH(mf.field)) {
1240                 dev_err(icd->parent, "Field type %d unsupported.\n",
1241                                 mf.field);
1242                 return -EINVAL;
1243         }
1244 
1245         pix->width      = mf.width;
1246         pix->height     = mf.height;
1247         pix->field      = mf.field;
1248         pix->colorspace = mf.colorspace;
1249 
1250         dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n",
1251                 __func__, pix->width, pix->height);
1252 
1253         return 0;
1254 }
1255 
1256 static int mx2_camera_querycap(struct soc_camera_host *ici,
1257                                struct v4l2_capability *cap)
1258 {
1259         /* cap->name is set by the friendly caller:-> */
1260         strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card));
1261         cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1262 
1263         return 0;
1264 }
1265 
1266 static unsigned int mx2_camera_poll(struct file *file, poll_table *pt)
1267 {
1268         struct soc_camera_device *icd = file->private_data;
1269 
1270         return vb2_poll(&icd->vb2_vidq, file, pt);
1271 }
1272 
1273 static struct soc_camera_host_ops mx2_soc_camera_host_ops = {
1274         .owner          = THIS_MODULE,
1275         .add            = mx2_camera_add_device,
1276         .remove         = mx2_camera_remove_device,
1277         .clock_start    = mx2_camera_clock_start,
1278         .clock_stop     = mx2_camera_clock_stop,
1279         .set_fmt        = mx2_camera_set_fmt,
1280         .set_crop       = mx2_camera_set_crop,
1281         .get_formats    = mx2_camera_get_formats,
1282         .try_fmt        = mx2_camera_try_fmt,
1283         .init_videobuf2 = mx2_camera_init_videobuf,
1284         .poll           = mx2_camera_poll,
1285         .querycap       = mx2_camera_querycap,
1286         .set_bus_param  = mx2_camera_set_bus_param,
1287 };
1288 
1289 static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev,
1290                 int bufnum, bool err)
1291 {
1292 #ifdef DEBUG
1293         struct mx2_fmt_cfg *prp = pcdev->emma_prp;
1294 #endif
1295         struct mx2_buf_internal *ibuf;
1296         struct mx2_buffer *buf;
1297         struct vb2_buffer *vb;
1298         unsigned long phys;
1299 
1300         ibuf = list_first_entry(&pcdev->active_bufs, struct mx2_buf_internal,
1301                                queue);
1302 
1303         BUG_ON(ibuf->bufnum != bufnum);
1304 
1305         if (ibuf->discard) {
1306                 /*
1307                  * Discard buffer must not be returned to user space.
1308                  * Just return it to the discard queue.
1309                  */
1310                 list_move_tail(pcdev->active_bufs.next, &pcdev->discard);
1311         } else {
1312                 buf = mx2_ibuf_to_buf(ibuf);
1313 
1314                 vb = &buf->vb;
1315 #ifdef DEBUG
1316                 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1317                 if (prp->cfg.channel == 1) {
1318                         if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR +
1319                                 4 * bufnum) != phys) {
1320                                 dev_err(pcdev->dev, "%lx != %x\n", phys,
1321                                         readl(pcdev->base_emma +
1322                                         PRP_DEST_RGB1_PTR + 4 * bufnum));
1323                         }
1324                 } else {
1325                         if (readl(pcdev->base_emma + PRP_DEST_Y_PTR -
1326                                 0x14 * bufnum) != phys) {
1327                                 dev_err(pcdev->dev, "%lx != %x\n", phys,
1328                                         readl(pcdev->base_emma +
1329                                         PRP_DEST_Y_PTR - 0x14 * bufnum));
1330                         }
1331                 }
1332 #endif
1333                 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__, vb,
1334                                 vb2_plane_vaddr(vb, 0),
1335                                 vb2_get_plane_payload(vb, 0));
1336 
1337                 list_del_init(&buf->internal.queue);
1338                 v4l2_get_timestamp(&vb->v4l2_buf.timestamp);
1339                 vb->v4l2_buf.sequence = pcdev->frame_count;
1340                 if (err)
1341                         vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
1342                 else
1343                         vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
1344         }
1345 
1346         pcdev->frame_count++;
1347 
1348         if (list_empty(&pcdev->capture)) {
1349                 if (list_empty(&pcdev->discard)) {
1350                         dev_warn(pcdev->dev, "%s: trying to access empty discard list\n",
1351                                  __func__);
1352                         return;
1353                 }
1354 
1355                 ibuf = list_first_entry(&pcdev->discard,
1356                                         struct mx2_buf_internal, queue);
1357                 ibuf->bufnum = bufnum;
1358 
1359                 list_move_tail(pcdev->discard.next, &pcdev->active_bufs);
1360                 mx27_update_emma_buf(pcdev, pcdev->discard_buffer_dma, bufnum);
1361                 return;
1362         }
1363 
1364         buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
1365                                internal.queue);
1366 
1367         buf->internal.bufnum = bufnum;
1368 
1369         list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
1370 
1371         vb = &buf->vb;
1372 
1373         phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1374         mx27_update_emma_buf(pcdev, phys, bufnum);
1375 }
1376 
1377 static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data)
1378 {
1379         struct mx2_camera_dev *pcdev = data;
1380         unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS);
1381         struct mx2_buf_internal *ibuf;
1382 
1383         spin_lock(&pcdev->lock);
1384 
1385         if (list_empty(&pcdev->active_bufs)) {
1386                 dev_warn(pcdev->dev, "%s: called while active list is empty\n",
1387                         __func__);
1388 
1389                 if (!status) {
1390                         spin_unlock(&pcdev->lock);
1391                         return IRQ_NONE;
1392                 }
1393         }
1394 
1395         if (status & (1 << 7)) { /* overflow */
1396                 u32 cntl = readl(pcdev->base_emma + PRP_CNTL);
1397                 writel(cntl & ~(PRP_CNTL_CH1EN | PRP_CNTL_CH2EN),
1398                        pcdev->base_emma + PRP_CNTL);
1399                 writel(cntl, pcdev->base_emma + PRP_CNTL);
1400 
1401                 ibuf = list_first_entry(&pcdev->active_bufs,
1402                                         struct mx2_buf_internal, queue);
1403                 mx27_camera_frame_done_emma(pcdev,
1404                                         ibuf->bufnum, true);
1405 
1406                 status &= ~(1 << 7);
1407         } else if (((status & (3 << 5)) == (3 << 5)) ||
1408                 ((status & (3 << 3)) == (3 << 3))) {
1409                 /*
1410                  * Both buffers have triggered, process the one we're expecting
1411                  * to first
1412                  */
1413                 ibuf = list_first_entry(&pcdev->active_bufs,
1414                                         struct mx2_buf_internal, queue);
1415                 mx27_camera_frame_done_emma(pcdev, ibuf->bufnum, false);
1416                 status &= ~(1 << (6 - ibuf->bufnum)); /* mark processed */
1417         } else if ((status & (1 << 6)) || (status & (1 << 4))) {
1418                 mx27_camera_frame_done_emma(pcdev, 0, false);
1419         } else if ((status & (1 << 5)) || (status & (1 << 3))) {
1420                 mx27_camera_frame_done_emma(pcdev, 1, false);
1421         }
1422 
1423         spin_unlock(&pcdev->lock);
1424         writel(status, pcdev->base_emma + PRP_INTRSTATUS);
1425 
1426         return IRQ_HANDLED;
1427 }
1428 
1429 static int mx27_camera_emma_init(struct platform_device *pdev)
1430 {
1431         struct mx2_camera_dev *pcdev = platform_get_drvdata(pdev);
1432         struct resource *res_emma;
1433         int irq_emma;
1434         int err = 0;
1435 
1436         res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1437         irq_emma = platform_get_irq(pdev, 1);
1438         if (!res_emma || !irq_emma) {
1439                 dev_err(pcdev->dev, "no EMMA resources\n");
1440                 err = -ENODEV;
1441                 goto out;
1442         }
1443 
1444         pcdev->base_emma = devm_ioremap_resource(pcdev->dev, res_emma);
1445         if (IS_ERR(pcdev->base_emma)) {
1446                 err = PTR_ERR(pcdev->base_emma);
1447                 goto out;
1448         }
1449 
1450         err = devm_request_irq(pcdev->dev, irq_emma, mx27_camera_emma_irq, 0,
1451                                MX2_CAM_DRV_NAME, pcdev);
1452         if (err) {
1453                 dev_err(pcdev->dev, "Camera EMMA interrupt register failed\n");
1454                 goto out;
1455         }
1456 
1457         pcdev->clk_emma_ipg = devm_clk_get(pcdev->dev, "emma-ipg");
1458         if (IS_ERR(pcdev->clk_emma_ipg)) {
1459                 err = PTR_ERR(pcdev->clk_emma_ipg);
1460                 goto out;
1461         }
1462 
1463         clk_prepare_enable(pcdev->clk_emma_ipg);
1464 
1465         pcdev->clk_emma_ahb = devm_clk_get(pcdev->dev, "emma-ahb");
1466         if (IS_ERR(pcdev->clk_emma_ahb)) {
1467                 err = PTR_ERR(pcdev->clk_emma_ahb);
1468                 goto exit_clk_emma_ipg;
1469         }
1470 
1471         clk_prepare_enable(pcdev->clk_emma_ahb);
1472 
1473         err = mx27_camera_emma_prp_reset(pcdev);
1474         if (err)
1475                 goto exit_clk_emma_ahb;
1476 
1477         return err;
1478 
1479 exit_clk_emma_ahb:
1480         clk_disable_unprepare(pcdev->clk_emma_ahb);
1481 exit_clk_emma_ipg:
1482         clk_disable_unprepare(pcdev->clk_emma_ipg);
1483 out:
1484         return err;
1485 }
1486 
1487 static int mx2_camera_probe(struct platform_device *pdev)
1488 {
1489         struct mx2_camera_dev *pcdev;
1490         struct resource *res_csi;
1491         int irq_csi;
1492         int err = 0;
1493 
1494         dev_dbg(&pdev->dev, "initialising\n");
1495 
1496         res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1497         irq_csi = platform_get_irq(pdev, 0);
1498         if (res_csi == NULL || irq_csi < 0) {
1499                 dev_err(&pdev->dev, "Missing platform resources data\n");
1500                 err = -ENODEV;
1501                 goto exit;
1502         }
1503 
1504         pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
1505         if (!pcdev) {
1506                 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1507                 err = -ENOMEM;
1508                 goto exit;
1509         }
1510 
1511         pcdev->clk_csi_ahb = devm_clk_get(&pdev->dev, "ahb");
1512         if (IS_ERR(pcdev->clk_csi_ahb)) {
1513                 dev_err(&pdev->dev, "Could not get csi ahb clock\n");
1514                 err = PTR_ERR(pcdev->clk_csi_ahb);
1515                 goto exit;
1516         }
1517 
1518         pcdev->clk_csi_per = devm_clk_get(&pdev->dev, "per");
1519         if (IS_ERR(pcdev->clk_csi_per)) {
1520                 dev_err(&pdev->dev, "Could not get csi per clock\n");
1521                 err = PTR_ERR(pcdev->clk_csi_per);
1522                 goto exit;
1523         }
1524 
1525         pcdev->pdata = pdev->dev.platform_data;
1526         if (pcdev->pdata) {
1527                 long rate;
1528 
1529                 pcdev->platform_flags = pcdev->pdata->flags;
1530 
1531                 rate = clk_round_rate(pcdev->clk_csi_per,
1532                                                 pcdev->pdata->clk * 2);
1533                 if (rate <= 0) {
1534                         err = -ENODEV;
1535                         goto exit;
1536                 }
1537                 err = clk_set_rate(pcdev->clk_csi_per, rate);
1538                 if (err < 0)
1539                         goto exit;
1540         }
1541 
1542         INIT_LIST_HEAD(&pcdev->capture);
1543         INIT_LIST_HEAD(&pcdev->active_bufs);
1544         INIT_LIST_HEAD(&pcdev->discard);
1545         spin_lock_init(&pcdev->lock);
1546 
1547         pcdev->base_csi = devm_ioremap_resource(&pdev->dev, res_csi);
1548         if (IS_ERR(pcdev->base_csi)) {
1549                 err = PTR_ERR(pcdev->base_csi);
1550                 goto exit;
1551         }
1552 
1553         pcdev->dev = &pdev->dev;
1554         platform_set_drvdata(pdev, pcdev);
1555 
1556         err = mx27_camera_emma_init(pdev);
1557         if (err)
1558                 goto exit;
1559 
1560         /*
1561          * We're done with drvdata here.  Clear the pointer so that
1562          * v4l2 core can start using drvdata on its purpose.
1563          */
1564         platform_set_drvdata(pdev, NULL);
1565 
1566         pcdev->soc_host.drv_name        = MX2_CAM_DRV_NAME,
1567         pcdev->soc_host.ops             = &mx2_soc_camera_host_ops,
1568         pcdev->soc_host.priv            = pcdev;
1569         pcdev->soc_host.v4l2_dev.dev    = &pdev->dev;
1570         pcdev->soc_host.nr              = pdev->id;
1571 
1572         pcdev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1573         if (IS_ERR(pcdev->alloc_ctx)) {
1574                 err = PTR_ERR(pcdev->alloc_ctx);
1575                 goto eallocctx;
1576         }
1577         err = soc_camera_host_register(&pcdev->soc_host);
1578         if (err)
1579                 goto exit_free_emma;
1580 
1581         dev_info(&pdev->dev, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n",
1582                         clk_get_rate(pcdev->clk_csi_per));
1583 
1584         return 0;
1585 
1586 exit_free_emma:
1587         vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1588 eallocctx:
1589         clk_disable_unprepare(pcdev->clk_emma_ipg);
1590         clk_disable_unprepare(pcdev->clk_emma_ahb);
1591 exit:
1592         return err;
1593 }
1594 
1595 static int mx2_camera_remove(struct platform_device *pdev)
1596 {
1597         struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1598         struct mx2_camera_dev *pcdev = container_of(soc_host,
1599                         struct mx2_camera_dev, soc_host);
1600 
1601         soc_camera_host_unregister(&pcdev->soc_host);
1602 
1603         vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1604 
1605         clk_disable_unprepare(pcdev->clk_emma_ipg);
1606         clk_disable_unprepare(pcdev->clk_emma_ahb);
1607 
1608         dev_info(&pdev->dev, "MX2 Camera driver unloaded\n");
1609 
1610         return 0;
1611 }
1612 
1613 static struct platform_driver mx2_camera_driver = {
1614         .driver         = {
1615                 .name   = MX2_CAM_DRV_NAME,
1616         },
1617         .id_table       = mx2_camera_devtype,
1618         .remove         = mx2_camera_remove,
1619 };
1620 
1621 module_platform_driver_probe(mx2_camera_driver, mx2_camera_probe);
1622 
1623 MODULE_DESCRIPTION("i.MX27 SoC Camera Host driver");
1624 MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>");
1625 MODULE_LICENSE("GPL");
1626 MODULE_VERSION(MX2_CAM_VERSION);
1627 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us