Version:  2.0.40 2.2.26 2.4.37 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15

Linux/drivers/media/platform/exynos4-is/fimc-is.c

  1 /*
  2  * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
  3  *
  4  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
  5  *
  6  * Authors: Sylwester Nawrocki <s.nawrocki@samsung.com>
  7  *          Younghwan Joo <yhwan.joo@samsung.com>
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2 as
 11  * published by the Free Software Foundation.
 12  */
 13 #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
 14 
 15 #include <linux/device.h>
 16 #include <linux/debugfs.h>
 17 #include <linux/delay.h>
 18 #include <linux/dma-contiguous.h>
 19 #include <linux/errno.h>
 20 #include <linux/firmware.h>
 21 #include <linux/interrupt.h>
 22 #include <linux/kernel.h>
 23 #include <linux/module.h>
 24 #include <linux/i2c.h>
 25 #include <linux/of_irq.h>
 26 #include <linux/of_address.h>
 27 #include <linux/of_graph.h>
 28 #include <linux/of_platform.h>
 29 #include <linux/platform_device.h>
 30 #include <linux/pm_runtime.h>
 31 #include <linux/slab.h>
 32 #include <linux/types.h>
 33 #include <linux/videodev2.h>
 34 #include <media/videobuf2-dma-contig.h>
 35 
 36 #include "media-dev.h"
 37 #include "fimc-is.h"
 38 #include "fimc-is-command.h"
 39 #include "fimc-is-errno.h"
 40 #include "fimc-is-i2c.h"
 41 #include "fimc-is-param.h"
 42 #include "fimc-is-regs.h"
 43 
 44 
 45 static char *fimc_is_clocks[ISS_CLKS_MAX] = {
 46         [ISS_CLK_PPMUISPX]              = "ppmuispx",
 47         [ISS_CLK_PPMUISPMX]             = "ppmuispmx",
 48         [ISS_CLK_LITE0]                 = "lite0",
 49         [ISS_CLK_LITE1]                 = "lite1",
 50         [ISS_CLK_MPLL]                  = "mpll",
 51         [ISS_CLK_ISP]                   = "isp",
 52         [ISS_CLK_DRC]                   = "drc",
 53         [ISS_CLK_FD]                    = "fd",
 54         [ISS_CLK_MCUISP]                = "mcuisp",
 55         [ISS_CLK_UART]                  = "uart",
 56         [ISS_CLK_ISP_DIV0]              = "ispdiv0",
 57         [ISS_CLK_ISP_DIV1]              = "ispdiv1",
 58         [ISS_CLK_MCUISP_DIV0]           = "mcuispdiv0",
 59         [ISS_CLK_MCUISP_DIV1]           = "mcuispdiv1",
 60         [ISS_CLK_ACLK200]               = "aclk200",
 61         [ISS_CLK_ACLK200_DIV]           = "div_aclk200",
 62         [ISS_CLK_ACLK400MCUISP]         = "aclk400mcuisp",
 63         [ISS_CLK_ACLK400MCUISP_DIV]     = "div_aclk400mcuisp",
 64 };
 65 
 66 static void fimc_is_put_clocks(struct fimc_is *is)
 67 {
 68         int i;
 69 
 70         for (i = 0; i < ISS_CLKS_MAX; i++) {
 71                 if (IS_ERR(is->clocks[i]))
 72                         continue;
 73                 clk_put(is->clocks[i]);
 74                 is->clocks[i] = ERR_PTR(-EINVAL);
 75         }
 76 }
 77 
 78 static int fimc_is_get_clocks(struct fimc_is *is)
 79 {
 80         int i, ret;
 81 
 82         for (i = 0; i < ISS_CLKS_MAX; i++)
 83                 is->clocks[i] = ERR_PTR(-EINVAL);
 84 
 85         for (i = 0; i < ISS_CLKS_MAX; i++) {
 86                 is->clocks[i] = clk_get(&is->pdev->dev, fimc_is_clocks[i]);
 87                 if (IS_ERR(is->clocks[i])) {
 88                         ret = PTR_ERR(is->clocks[i]);
 89                         goto err;
 90                 }
 91         }
 92 
 93         return 0;
 94 err:
 95         fimc_is_put_clocks(is);
 96         dev_err(&is->pdev->dev, "failed to get clock: %s\n",
 97                 fimc_is_clocks[i]);
 98         return ret;
 99 }
100 
101 static int fimc_is_setup_clocks(struct fimc_is *is)
102 {
103         int ret;
104 
105         ret = clk_set_parent(is->clocks[ISS_CLK_ACLK200],
106                                         is->clocks[ISS_CLK_ACLK200_DIV]);
107         if (ret < 0)
108                 return ret;
109 
110         ret = clk_set_parent(is->clocks[ISS_CLK_ACLK400MCUISP],
111                                         is->clocks[ISS_CLK_ACLK400MCUISP_DIV]);
112         if (ret < 0)
113                 return ret;
114 
115         ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV0], ACLK_AXI_FREQUENCY);
116         if (ret < 0)
117                 return ret;
118 
119         ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV1], ACLK_AXI_FREQUENCY);
120         if (ret < 0)
121                 return ret;
122 
123         ret = clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV0],
124                                         ATCLK_MCUISP_FREQUENCY);
125         if (ret < 0)
126                 return ret;
127 
128         return clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV1],
129                                         ATCLK_MCUISP_FREQUENCY);
130 }
131 
132 static int fimc_is_enable_clocks(struct fimc_is *is)
133 {
134         int i, ret;
135 
136         for (i = 0; i < ISS_GATE_CLKS_MAX; i++) {
137                 if (IS_ERR(is->clocks[i]))
138                         continue;
139                 ret = clk_prepare_enable(is->clocks[i]);
140                 if (ret < 0) {
141                         dev_err(&is->pdev->dev, "clock %s enable failed\n",
142                                 fimc_is_clocks[i]);
143                         for (--i; i >= 0; i--)
144                                 clk_disable(is->clocks[i]);
145                         return ret;
146                 }
147                 pr_debug("enabled clock: %s\n", fimc_is_clocks[i]);
148         }
149         return 0;
150 }
151 
152 static void fimc_is_disable_clocks(struct fimc_is *is)
153 {
154         int i;
155 
156         for (i = 0; i < ISS_GATE_CLKS_MAX; i++) {
157                 if (!IS_ERR(is->clocks[i])) {
158                         clk_disable_unprepare(is->clocks[i]);
159                         pr_debug("disabled clock: %s\n", fimc_is_clocks[i]);
160                 }
161         }
162 }
163 
164 static int fimc_is_parse_sensor_config(struct fimc_is *is, unsigned int index,
165                                                 struct device_node *node)
166 {
167         struct fimc_is_sensor *sensor = &is->sensor[index];
168         u32 tmp = 0;
169         int ret;
170 
171         sensor->drvdata = fimc_is_sensor_get_drvdata(node);
172         if (!sensor->drvdata) {
173                 dev_err(&is->pdev->dev, "no driver data found for: %s\n",
174                                                          node->full_name);
175                 return -EINVAL;
176         }
177 
178         node = of_graph_get_next_endpoint(node, NULL);
179         if (!node)
180                 return -ENXIO;
181 
182         node = of_graph_get_remote_port(node);
183         if (!node)
184                 return -ENXIO;
185 
186         /* Use MIPI-CSIS channel id to determine the ISP I2C bus index. */
187         ret = of_property_read_u32(node, "reg", &tmp);
188         if (ret < 0) {
189                 dev_err(&is->pdev->dev, "reg property not found at: %s\n",
190                                                          node->full_name);
191                 return ret;
192         }
193 
194         sensor->i2c_bus = tmp - FIMC_INPUT_MIPI_CSI2_0;
195         return 0;
196 }
197 
198 static int fimc_is_register_subdevs(struct fimc_is *is)
199 {
200         struct device_node *i2c_bus, *child;
201         int ret, index = 0;
202 
203         ret = fimc_isp_subdev_create(&is->isp);
204         if (ret < 0)
205                 return ret;
206 
207         /* Initialize memory allocator context for the ISP DMA. */
208         is->isp.alloc_ctx = is->alloc_ctx;
209 
210         for_each_compatible_node(i2c_bus, NULL, FIMC_IS_I2C_COMPATIBLE) {
211                 for_each_available_child_of_node(i2c_bus, child) {
212                         ret = fimc_is_parse_sensor_config(is, index, child);
213 
214                         if (ret < 0 || index >= FIMC_IS_SENSORS_NUM) {
215                                 of_node_put(child);
216                                 return ret;
217                         }
218                         index++;
219                 }
220         }
221         return 0;
222 }
223 
224 static int fimc_is_unregister_subdevs(struct fimc_is *is)
225 {
226         fimc_isp_subdev_destroy(&is->isp);
227         return 0;
228 }
229 
230 static int fimc_is_load_setfile(struct fimc_is *is, char *file_name)
231 {
232         const struct firmware *fw;
233         void *buf;
234         int ret;
235 
236         ret = request_firmware(&fw, file_name, &is->pdev->dev);
237         if (ret < 0) {
238                 dev_err(&is->pdev->dev, "firmware request failed (%d)\n", ret);
239                 return ret;
240         }
241         buf = is->memory.vaddr + is->setfile.base;
242         memcpy(buf, fw->data, fw->size);
243         fimc_is_mem_barrier();
244         is->setfile.size = fw->size;
245 
246         pr_debug("mem vaddr: %p, setfile buf: %p\n", is->memory.vaddr, buf);
247 
248         memcpy(is->fw.setfile_info,
249                 fw->data + fw->size - FIMC_IS_SETFILE_INFO_LEN,
250                 FIMC_IS_SETFILE_INFO_LEN - 1);
251 
252         is->fw.setfile_info[FIMC_IS_SETFILE_INFO_LEN - 1] = '\0';
253         is->setfile.state = 1;
254 
255         pr_debug("FIMC-IS setfile loaded: base: %#x, size: %zu B\n",
256                  is->setfile.base, fw->size);
257 
258         release_firmware(fw);
259         return ret;
260 }
261 
262 int fimc_is_cpu_set_power(struct fimc_is *is, int on)
263 {
264         unsigned int timeout = FIMC_IS_POWER_ON_TIMEOUT;
265 
266         if (on) {
267                 /* Disable watchdog */
268                 mcuctl_write(0, is, REG_WDT_ISP);
269 
270                 /* Cortex-A5 start address setting */
271                 mcuctl_write(is->memory.paddr, is, MCUCTL_REG_BBOAR);
272 
273                 /* Enable and start Cortex-A5 */
274                 pmuisp_write(0x18000, is, REG_PMU_ISP_ARM_OPTION);
275                 pmuisp_write(0x1, is, REG_PMU_ISP_ARM_CONFIGURATION);
276         } else {
277                 /* A5 power off */
278                 pmuisp_write(0x10000, is, REG_PMU_ISP_ARM_OPTION);
279                 pmuisp_write(0x0, is, REG_PMU_ISP_ARM_CONFIGURATION);
280 
281                 while (pmuisp_read(is, REG_PMU_ISP_ARM_STATUS) & 1) {
282                         if (timeout == 0)
283                                 return -ETIME;
284                         timeout--;
285                         udelay(1);
286                 }
287         }
288 
289         return 0;
290 }
291 
292 /* Wait until @bit of @is->state is set to @state in the interrupt handler. */
293 int fimc_is_wait_event(struct fimc_is *is, unsigned long bit,
294                        unsigned int state, unsigned int timeout)
295 {
296 
297         int ret = wait_event_timeout(is->irq_queue,
298                                      !state ^ test_bit(bit, &is->state),
299                                      timeout);
300         if (ret == 0) {
301                 dev_WARN(&is->pdev->dev, "%s() timed out\n", __func__);
302                 return -ETIME;
303         }
304         return 0;
305 }
306 
307 int fimc_is_start_firmware(struct fimc_is *is)
308 {
309         struct device *dev = &is->pdev->dev;
310         int ret;
311 
312         if (is->fw.f_w == NULL) {
313                 dev_err(dev, "firmware is not loaded\n");
314                 return -EINVAL;
315         }
316 
317         memcpy(is->memory.vaddr, is->fw.f_w->data, is->fw.f_w->size);
318         wmb();
319 
320         ret = fimc_is_cpu_set_power(is, 1);
321         if (ret < 0)
322                 return ret;
323 
324         ret = fimc_is_wait_event(is, IS_ST_A5_PWR_ON, 1,
325                                  msecs_to_jiffies(FIMC_IS_FW_LOAD_TIMEOUT));
326         if (ret < 0)
327                 dev_err(dev, "FIMC-IS CPU power on failed\n");
328 
329         return ret;
330 }
331 
332 /* Allocate working memory for the FIMC-IS CPU. */
333 static int fimc_is_alloc_cpu_memory(struct fimc_is *is)
334 {
335         struct device *dev = &is->pdev->dev;
336 
337         is->memory.vaddr = dma_alloc_coherent(dev, FIMC_IS_CPU_MEM_SIZE,
338                                               &is->memory.paddr, GFP_KERNEL);
339         if (is->memory.vaddr == NULL)
340                 return -ENOMEM;
341 
342         is->memory.size = FIMC_IS_CPU_MEM_SIZE;
343         memset(is->memory.vaddr, 0, is->memory.size);
344 
345         dev_info(dev, "FIMC-IS CPU memory base: %#x\n", (u32)is->memory.paddr);
346 
347         if (((u32)is->memory.paddr) & FIMC_IS_FW_ADDR_MASK) {
348                 dev_err(dev, "invalid firmware memory alignment: %#x\n",
349                         (u32)is->memory.paddr);
350                 dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
351                                   is->memory.paddr);
352                 return -EIO;
353         }
354 
355         is->is_p_region = (struct is_region *)(is->memory.vaddr +
356                                 FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE);
357 
358         is->is_dma_p_region = is->memory.paddr +
359                                 FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE;
360 
361         is->is_shared_region = (struct is_share_region *)(is->memory.vaddr +
362                                 FIMC_IS_SHARED_REGION_OFFSET);
363         return 0;
364 }
365 
366 static void fimc_is_free_cpu_memory(struct fimc_is *is)
367 {
368         struct device *dev = &is->pdev->dev;
369 
370         dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
371                           is->memory.paddr);
372 }
373 
374 static void fimc_is_load_firmware(const struct firmware *fw, void *context)
375 {
376         struct fimc_is *is = context;
377         struct device *dev = &is->pdev->dev;
378         void *buf;
379         int ret;
380 
381         if (fw == NULL) {
382                 dev_err(dev, "firmware request failed\n");
383                 return;
384         }
385         mutex_lock(&is->lock);
386 
387         if (fw->size < FIMC_IS_FW_SIZE_MIN || fw->size > FIMC_IS_FW_SIZE_MAX) {
388                 dev_err(dev, "wrong firmware size: %d\n", fw->size);
389                 goto done;
390         }
391 
392         is->fw.size = fw->size;
393 
394         ret = fimc_is_alloc_cpu_memory(is);
395         if (ret < 0) {
396                 dev_err(dev, "failed to allocate FIMC-IS CPU memory\n");
397                 goto done;
398         }
399 
400         memcpy(is->memory.vaddr, fw->data, fw->size);
401         wmb();
402 
403         /* Read firmware description. */
404         buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_DESC_LEN);
405         memcpy(&is->fw.info, buf, FIMC_IS_FW_INFO_LEN);
406         is->fw.info[FIMC_IS_FW_INFO_LEN] = 0;
407 
408         buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_VER_LEN);
409         memcpy(&is->fw.version, buf, FIMC_IS_FW_VER_LEN);
410         is->fw.version[FIMC_IS_FW_VER_LEN - 1] = 0;
411 
412         is->fw.state = 1;
413 
414         dev_info(dev, "loaded firmware: %s, rev. %s\n",
415                  is->fw.info, is->fw.version);
416         dev_dbg(dev, "FW size: %d, paddr: %#x\n", fw->size, is->memory.paddr);
417 
418         is->is_shared_region->chip_id = 0xe4412;
419         is->is_shared_region->chip_rev_no = 1;
420 
421         fimc_is_mem_barrier();
422 
423         /*
424          * FIXME: The firmware is not being released for now, as it is
425          * needed around for copying to the IS working memory every
426          * time before the Cortex-A5 is restarted.
427          */
428         if (is->fw.f_w)
429                 release_firmware(is->fw.f_w);
430         is->fw.f_w = fw;
431 done:
432         mutex_unlock(&is->lock);
433 }
434 
435 static int fimc_is_request_firmware(struct fimc_is *is, const char *fw_name)
436 {
437         return request_firmware_nowait(THIS_MODULE,
438                                 FW_ACTION_HOTPLUG, fw_name, &is->pdev->dev,
439                                 GFP_KERNEL, is, fimc_is_load_firmware);
440 }
441 
442 /* General IS interrupt handler */
443 static void fimc_is_general_irq_handler(struct fimc_is *is)
444 {
445         is->i2h_cmd.cmd = mcuctl_read(is, MCUCTL_REG_ISSR(10));
446 
447         switch (is->i2h_cmd.cmd) {
448         case IHC_GET_SENSOR_NUM:
449                 fimc_is_hw_get_params(is, 1);
450                 fimc_is_hw_wait_intmsr0_intmsd0(is);
451                 fimc_is_hw_set_sensor_num(is);
452                 pr_debug("ISP FW version: %#x\n", is->i2h_cmd.args[0]);
453                 break;
454         case IHC_SET_FACE_MARK:
455         case IHC_FRAME_DONE:
456                 fimc_is_hw_get_params(is, 2);
457                 break;
458         case IHC_SET_SHOT_MARK:
459         case IHC_AA_DONE:
460         case IH_REPLY_DONE:
461                 fimc_is_hw_get_params(is, 3);
462                 break;
463         case IH_REPLY_NOT_DONE:
464                 fimc_is_hw_get_params(is, 4);
465                 break;
466         case IHC_NOT_READY:
467                 break;
468         default:
469                 pr_info("unknown command: %#x\n", is->i2h_cmd.cmd);
470         }
471 
472         fimc_is_fw_clear_irq1(is, FIMC_IS_INT_GENERAL);
473 
474         switch (is->i2h_cmd.cmd) {
475         case IHC_GET_SENSOR_NUM:
476                 fimc_is_hw_set_intgr0_gd0(is);
477                 set_bit(IS_ST_A5_PWR_ON, &is->state);
478                 break;
479 
480         case IHC_SET_SHOT_MARK:
481                 break;
482 
483         case IHC_SET_FACE_MARK:
484                 is->fd_header.count = is->i2h_cmd.args[0];
485                 is->fd_header.index = is->i2h_cmd.args[1];
486                 is->fd_header.offset = 0;
487                 break;
488 
489         case IHC_FRAME_DONE:
490                 break;
491 
492         case IHC_AA_DONE:
493                 pr_debug("AA_DONE - %d, %d, %d\n", is->i2h_cmd.args[0],
494                          is->i2h_cmd.args[1], is->i2h_cmd.args[2]);
495                 break;
496 
497         case IH_REPLY_DONE:
498                 pr_debug("ISR_DONE: args[0]: %#x\n", is->i2h_cmd.args[0]);
499 
500                 switch (is->i2h_cmd.args[0]) {
501                 case HIC_PREVIEW_STILL...HIC_CAPTURE_VIDEO:
502                         /* Get CAC margin */
503                         set_bit(IS_ST_CHANGE_MODE, &is->state);
504                         is->isp.cac_margin_x = is->i2h_cmd.args[1];
505                         is->isp.cac_margin_y = is->i2h_cmd.args[2];
506                         pr_debug("CAC margin (x,y): (%d,%d)\n",
507                                  is->isp.cac_margin_x, is->isp.cac_margin_y);
508                         break;
509 
510                 case HIC_STREAM_ON:
511                         clear_bit(IS_ST_STREAM_OFF, &is->state);
512                         set_bit(IS_ST_STREAM_ON, &is->state);
513                         break;
514 
515                 case HIC_STREAM_OFF:
516                         clear_bit(IS_ST_STREAM_ON, &is->state);
517                         set_bit(IS_ST_STREAM_OFF, &is->state);
518                         break;
519 
520                 case HIC_SET_PARAMETER:
521                         is->config[is->config_index].p_region_index[0] = 0;
522                         is->config[is->config_index].p_region_index[1] = 0;
523                         set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
524                         pr_debug("HIC_SET_PARAMETER\n");
525                         break;
526 
527                 case HIC_GET_PARAMETER:
528                         break;
529 
530                 case HIC_SET_TUNE:
531                         break;
532 
533                 case HIC_GET_STATUS:
534                         break;
535 
536                 case HIC_OPEN_SENSOR:
537                         set_bit(IS_ST_OPEN_SENSOR, &is->state);
538                         pr_debug("data lanes: %d, settle line: %d\n",
539                                  is->i2h_cmd.args[2], is->i2h_cmd.args[1]);
540                         break;
541 
542                 case HIC_CLOSE_SENSOR:
543                         clear_bit(IS_ST_OPEN_SENSOR, &is->state);
544                         is->sensor_index = 0;
545                         break;
546 
547                 case HIC_MSG_TEST:
548                         pr_debug("config MSG level completed\n");
549                         break;
550 
551                 case HIC_POWER_DOWN:
552                         clear_bit(IS_ST_PWR_SUBIP_ON, &is->state);
553                         break;
554 
555                 case HIC_GET_SET_FILE_ADDR:
556                         is->setfile.base = is->i2h_cmd.args[1];
557                         set_bit(IS_ST_SETFILE_LOADED, &is->state);
558                         break;
559 
560                 case HIC_LOAD_SET_FILE:
561                         set_bit(IS_ST_SETFILE_LOADED, &is->state);
562                         break;
563                 }
564                 break;
565 
566         case IH_REPLY_NOT_DONE:
567                 pr_err("ISR_NDONE: %d: %#x, %s\n", is->i2h_cmd.args[0],
568                        is->i2h_cmd.args[1],
569                        fimc_is_strerr(is->i2h_cmd.args[1]));
570 
571                 if (is->i2h_cmd.args[1] & IS_ERROR_TIME_OUT_FLAG)
572                         pr_err("IS_ERROR_TIME_OUT\n");
573 
574                 switch (is->i2h_cmd.args[1]) {
575                 case IS_ERROR_SET_PARAMETER:
576                         fimc_is_mem_barrier();
577                 }
578 
579                 switch (is->i2h_cmd.args[0]) {
580                 case HIC_SET_PARAMETER:
581                         is->config[is->config_index].p_region_index[0] = 0;
582                         is->config[is->config_index].p_region_index[1] = 0;
583                         set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
584                         break;
585                 }
586                 break;
587 
588         case IHC_NOT_READY:
589                 pr_err("IS control sequence error: Not Ready\n");
590                 break;
591         }
592 
593         wake_up(&is->irq_queue);
594 }
595 
596 static irqreturn_t fimc_is_irq_handler(int irq, void *priv)
597 {
598         struct fimc_is *is = priv;
599         unsigned long flags;
600         u32 status;
601 
602         spin_lock_irqsave(&is->slock, flags);
603         status = mcuctl_read(is, MCUCTL_REG_INTSR1);
604 
605         if (status & (1UL << FIMC_IS_INT_GENERAL))
606                 fimc_is_general_irq_handler(is);
607 
608         if (status & (1UL << FIMC_IS_INT_FRAME_DONE_ISP))
609                 fimc_isp_irq_handler(is);
610 
611         spin_unlock_irqrestore(&is->slock, flags);
612         return IRQ_HANDLED;
613 }
614 
615 static int fimc_is_hw_open_sensor(struct fimc_is *is,
616                                   struct fimc_is_sensor *sensor)
617 {
618         struct sensor_open_extended *soe = (void *)&is->is_p_region->shared;
619 
620         fimc_is_hw_wait_intmsr0_intmsd0(is);
621 
622         soe->self_calibration_mode = 1;
623         soe->actuator_type = 0;
624         soe->mipi_lane_num = 0;
625         soe->mclk = 0;
626         soe->mipi_speed = 0;
627         soe->fast_open_sensor = 0;
628         soe->i2c_sclk = 88000000;
629 
630         fimc_is_mem_barrier();
631 
632         mcuctl_write(HIC_OPEN_SENSOR, is, MCUCTL_REG_ISSR(0));
633         mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
634         mcuctl_write(sensor->drvdata->id, is, MCUCTL_REG_ISSR(2));
635         mcuctl_write(sensor->i2c_bus, is, MCUCTL_REG_ISSR(3));
636         mcuctl_write(is->is_dma_p_region, is, MCUCTL_REG_ISSR(4));
637 
638         fimc_is_hw_set_intgr0_gd0(is);
639 
640         return fimc_is_wait_event(is, IS_ST_OPEN_SENSOR, 1,
641                                   sensor->drvdata->open_timeout);
642 }
643 
644 
645 int fimc_is_hw_initialize(struct fimc_is *is)
646 {
647         const int config_ids[] = {
648                 IS_SC_PREVIEW_STILL, IS_SC_PREVIEW_VIDEO,
649                 IS_SC_CAPTURE_STILL, IS_SC_CAPTURE_VIDEO
650         };
651         struct device *dev = &is->pdev->dev;
652         u32 prev_id;
653         int i, ret;
654 
655         /* Sensor initialization. Only one sensor is currently supported. */
656         ret = fimc_is_hw_open_sensor(is, &is->sensor[0]);
657         if (ret < 0)
658                 return ret;
659 
660         /* Get the setfile address. */
661         fimc_is_hw_get_setfile_addr(is);
662 
663         ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1,
664                                  FIMC_IS_CONFIG_TIMEOUT);
665         if (ret < 0) {
666                 dev_err(dev, "get setfile address timed out\n");
667                 return ret;
668         }
669         pr_debug("setfile.base: %#x\n", is->setfile.base);
670 
671         /* Load the setfile. */
672         fimc_is_load_setfile(is, FIMC_IS_SETFILE_6A3);
673         clear_bit(IS_ST_SETFILE_LOADED, &is->state);
674         fimc_is_hw_load_setfile(is);
675         ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1,
676                                  FIMC_IS_CONFIG_TIMEOUT);
677         if (ret < 0) {
678                 dev_err(dev, "loading setfile timed out\n");
679                 return ret;
680         }
681 
682         pr_debug("setfile: base: %#x, size: %d\n",
683                  is->setfile.base, is->setfile.size);
684         pr_info("FIMC-IS Setfile info: %s\n", is->fw.setfile_info);
685 
686         /* Check magic number. */
687         if (is->is_p_region->shared[MAX_SHARED_COUNT - 1] !=
688             FIMC_IS_MAGIC_NUMBER) {
689                 dev_err(dev, "magic number error!\n");
690                 return -EIO;
691         }
692 
693         pr_debug("shared region: %#x, parameter region: %#x\n",
694                  is->memory.paddr + FIMC_IS_SHARED_REGION_OFFSET,
695                  is->is_dma_p_region);
696 
697         is->setfile.sub_index = 0;
698 
699         /* Stream off. */
700         fimc_is_hw_stream_off(is);
701         ret = fimc_is_wait_event(is, IS_ST_STREAM_OFF, 1,
702                                  FIMC_IS_CONFIG_TIMEOUT);
703         if (ret < 0) {
704                 dev_err(dev, "stream off timeout\n");
705                 return ret;
706         }
707 
708         /* Preserve previous mode. */
709         prev_id = is->config_index;
710 
711         /* Set initial parameter values. */
712         for (i = 0; i < ARRAY_SIZE(config_ids); i++) {
713                 is->config_index = config_ids[i];
714                 fimc_is_set_initial_params(is);
715                 ret = fimc_is_itf_s_param(is, true);
716                 if (ret < 0) {
717                         is->config_index = prev_id;
718                         return ret;
719                 }
720         }
721         is->config_index = prev_id;
722 
723         set_bit(IS_ST_INIT_DONE, &is->state);
724         dev_info(dev, "initialization sequence completed (%d)\n",
725                                                 is->config_index);
726         return 0;
727 }
728 
729 static int fimc_is_log_show(struct seq_file *s, void *data)
730 {
731         struct fimc_is *is = s->private;
732         const u8 *buf = is->memory.vaddr + FIMC_IS_DEBUG_REGION_OFFSET;
733 
734         if (is->memory.vaddr == NULL) {
735                 dev_err(&is->pdev->dev, "firmware memory is not initialized\n");
736                 return -EIO;
737         }
738 
739         seq_printf(s, "%s\n", buf);
740         return 0;
741 }
742 
743 static int fimc_is_debugfs_open(struct inode *inode, struct file *file)
744 {
745         return single_open(file, fimc_is_log_show, inode->i_private);
746 }
747 
748 static const struct file_operations fimc_is_debugfs_fops = {
749         .open           = fimc_is_debugfs_open,
750         .read           = seq_read,
751         .llseek         = seq_lseek,
752         .release        = single_release,
753 };
754 
755 static void fimc_is_debugfs_remove(struct fimc_is *is)
756 {
757         debugfs_remove_recursive(is->debugfs_entry);
758         is->debugfs_entry = NULL;
759 }
760 
761 static int fimc_is_debugfs_create(struct fimc_is *is)
762 {
763         struct dentry *dentry;
764 
765         is->debugfs_entry = debugfs_create_dir("fimc_is", NULL);
766 
767         dentry = debugfs_create_file("fw_log", S_IRUGO, is->debugfs_entry,
768                                      is, &fimc_is_debugfs_fops);
769         if (!dentry)
770                 fimc_is_debugfs_remove(is);
771 
772         return is->debugfs_entry == NULL ? -EIO : 0;
773 }
774 
775 static int fimc_is_runtime_resume(struct device *dev);
776 static int fimc_is_runtime_suspend(struct device *dev);
777 
778 static int fimc_is_probe(struct platform_device *pdev)
779 {
780         struct device *dev = &pdev->dev;
781         struct fimc_is *is;
782         struct resource res;
783         struct device_node *node;
784         int ret;
785 
786         is = devm_kzalloc(&pdev->dev, sizeof(*is), GFP_KERNEL);
787         if (!is)
788                 return -ENOMEM;
789 
790         is->pdev = pdev;
791         is->isp.pdev = pdev;
792 
793         init_waitqueue_head(&is->irq_queue);
794         spin_lock_init(&is->slock);
795         mutex_init(&is->lock);
796 
797         ret = of_address_to_resource(dev->of_node, 0, &res);
798         if (ret < 0)
799                 return ret;
800 
801         is->regs = devm_ioremap_resource(dev, &res);
802         if (IS_ERR(is->regs))
803                 return PTR_ERR(is->regs);
804 
805         node = of_get_child_by_name(dev->of_node, "pmu");
806         if (!node)
807                 return -ENODEV;
808 
809         is->pmu_regs = of_iomap(node, 0);
810         if (!is->pmu_regs)
811                 return -ENOMEM;
812 
813         is->irq = irq_of_parse_and_map(dev->of_node, 0);
814         if (is->irq < 0) {
815                 dev_err(dev, "no irq found\n");
816                 return is->irq;
817         }
818 
819         ret = fimc_is_get_clocks(is);
820         if (ret < 0)
821                 return ret;
822 
823         platform_set_drvdata(pdev, is);
824 
825         ret = request_irq(is->irq, fimc_is_irq_handler, 0, dev_name(dev), is);
826         if (ret < 0) {
827                 dev_err(dev, "irq request failed\n");
828                 goto err_clk;
829         }
830         pm_runtime_enable(dev);
831 
832         if (!pm_runtime_enabled(dev)) {
833                 ret = fimc_is_runtime_resume(dev);
834                 if (ret < 0)
835                         goto err_irq;
836         }
837 
838         ret = pm_runtime_get_sync(dev);
839         if (ret < 0)
840                 goto err_pm;
841 
842         is->alloc_ctx = vb2_dma_contig_init_ctx(dev);
843         if (IS_ERR(is->alloc_ctx)) {
844                 ret = PTR_ERR(is->alloc_ctx);
845                 goto err_pm;
846         }
847         /*
848          * Register FIMC-IS V4L2 subdevs to this driver. The video nodes
849          * will be created within the subdev's registered() callback.
850          */
851         ret = fimc_is_register_subdevs(is);
852         if (ret < 0)
853                 goto err_vb;
854 
855         ret = fimc_is_debugfs_create(is);
856         if (ret < 0)
857                 goto err_sd;
858 
859         ret = fimc_is_request_firmware(is, FIMC_IS_FW_FILENAME);
860         if (ret < 0)
861                 goto err_dfs;
862 
863         pm_runtime_put_sync(dev);
864 
865         dev_dbg(dev, "FIMC-IS registered successfully\n");
866         return 0;
867 
868 err_dfs:
869         fimc_is_debugfs_remove(is);
870 err_sd:
871         fimc_is_unregister_subdevs(is);
872 err_vb:
873         vb2_dma_contig_cleanup_ctx(is->alloc_ctx);
874 err_pm:
875         if (!pm_runtime_enabled(dev))
876                 fimc_is_runtime_suspend(dev);
877 err_irq:
878         free_irq(is->irq, is);
879 err_clk:
880         fimc_is_put_clocks(is);
881         return ret;
882 }
883 
884 static int fimc_is_runtime_resume(struct device *dev)
885 {
886         struct fimc_is *is = dev_get_drvdata(dev);
887         int ret;
888 
889         ret = fimc_is_setup_clocks(is);
890         if (ret)
891                 return ret;
892 
893         return fimc_is_enable_clocks(is);
894 }
895 
896 static int fimc_is_runtime_suspend(struct device *dev)
897 {
898         struct fimc_is *is = dev_get_drvdata(dev);
899 
900         fimc_is_disable_clocks(is);
901         return 0;
902 }
903 
904 #ifdef CONFIG_PM_SLEEP
905 static int fimc_is_resume(struct device *dev)
906 {
907         /* TODO: */
908         return 0;
909 }
910 
911 static int fimc_is_suspend(struct device *dev)
912 {
913         struct fimc_is *is = dev_get_drvdata(dev);
914 
915         /* TODO: */
916         if (test_bit(IS_ST_A5_PWR_ON, &is->state))
917                 return -EBUSY;
918 
919         return 0;
920 }
921 #endif /* CONFIG_PM_SLEEP */
922 
923 static int fimc_is_remove(struct platform_device *pdev)
924 {
925         struct device *dev = &pdev->dev;
926         struct fimc_is *is = dev_get_drvdata(dev);
927 
928         pm_runtime_disable(dev);
929         pm_runtime_set_suspended(dev);
930         if (!pm_runtime_status_suspended(dev))
931                 fimc_is_runtime_suspend(dev);
932         free_irq(is->irq, is);
933         fimc_is_unregister_subdevs(is);
934         vb2_dma_contig_cleanup_ctx(is->alloc_ctx);
935         fimc_is_put_clocks(is);
936         fimc_is_debugfs_remove(is);
937         if (is->fw.f_w)
938                 release_firmware(is->fw.f_w);
939         fimc_is_free_cpu_memory(is);
940 
941         return 0;
942 }
943 
944 static const struct of_device_id fimc_is_of_match[] = {
945         { .compatible = "samsung,exynos4212-fimc-is" },
946         { /* sentinel */ },
947 };
948 MODULE_DEVICE_TABLE(of, fimc_is_of_match);
949 
950 static const struct dev_pm_ops fimc_is_pm_ops = {
951         SET_SYSTEM_SLEEP_PM_OPS(fimc_is_suspend, fimc_is_resume)
952         SET_RUNTIME_PM_OPS(fimc_is_runtime_suspend, fimc_is_runtime_resume,
953                            NULL)
954 };
955 
956 static struct platform_driver fimc_is_driver = {
957         .probe          = fimc_is_probe,
958         .remove         = fimc_is_remove,
959         .driver = {
960                 .of_match_table = fimc_is_of_match,
961                 .name           = FIMC_IS_DRV_NAME,
962                 .owner          = THIS_MODULE,
963                 .pm             = &fimc_is_pm_ops,
964         }
965 };
966 
967 static int fimc_is_module_init(void)
968 {
969         int ret;
970 
971         ret = fimc_is_register_i2c_driver();
972         if (ret < 0)
973                 return ret;
974 
975         ret = platform_driver_register(&fimc_is_driver);
976 
977         if (ret < 0)
978                 fimc_is_unregister_i2c_driver();
979 
980         return ret;
981 }
982 
983 static void fimc_is_module_exit(void)
984 {
985         fimc_is_unregister_i2c_driver();
986         platform_driver_unregister(&fimc_is_driver);
987 }
988 
989 module_init(fimc_is_module_init);
990 module_exit(fimc_is_module_exit);
991 
992 MODULE_ALIAS("platform:" FIMC_IS_DRV_NAME);
993 MODULE_AUTHOR("Younghwan Joo <yhwan.joo@samsung.com>");
994 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
995 MODULE_LICENSE("GPL v2");
996 

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