Version:  2.0.40 2.2.26 2.4.37 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8

Linux/drivers/media/platform/exynos4-is/fimc-is.c

  1 /*
  2  * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
  3  *
  4  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
  5  *
  6  * Authors: Sylwester Nawrocki <s.nawrocki@samsung.com>
  7  *          Younghwan Joo <yhwan.joo@samsung.com>
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2 as
 11  * published by the Free Software Foundation.
 12  */
 13 #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
 14 
 15 #include <linux/device.h>
 16 #include <linux/debugfs.h>
 17 #include <linux/delay.h>
 18 #include <linux/dma-contiguous.h>
 19 #include <linux/errno.h>
 20 #include <linux/firmware.h>
 21 #include <linux/interrupt.h>
 22 #include <linux/kernel.h>
 23 #include <linux/module.h>
 24 #include <linux/i2c.h>
 25 #include <linux/of_irq.h>
 26 #include <linux/of_address.h>
 27 #include <linux/of_graph.h>
 28 #include <linux/of_platform.h>
 29 #include <linux/platform_device.h>
 30 #include <linux/pm_runtime.h>
 31 #include <linux/slab.h>
 32 #include <linux/types.h>
 33 #include <linux/videodev2.h>
 34 #include <media/videobuf2-dma-contig.h>
 35 
 36 #include "media-dev.h"
 37 #include "fimc-is.h"
 38 #include "fimc-is-command.h"
 39 #include "fimc-is-errno.h"
 40 #include "fimc-is-i2c.h"
 41 #include "fimc-is-param.h"
 42 #include "fimc-is-regs.h"
 43 
 44 
 45 static char *fimc_is_clocks[ISS_CLKS_MAX] = {
 46         [ISS_CLK_PPMUISPX]              = "ppmuispx",
 47         [ISS_CLK_PPMUISPMX]             = "ppmuispmx",
 48         [ISS_CLK_LITE0]                 = "lite0",
 49         [ISS_CLK_LITE1]                 = "lite1",
 50         [ISS_CLK_MPLL]                  = "mpll",
 51         [ISS_CLK_ISP]                   = "isp",
 52         [ISS_CLK_DRC]                   = "drc",
 53         [ISS_CLK_FD]                    = "fd",
 54         [ISS_CLK_MCUISP]                = "mcuisp",
 55         [ISS_CLK_UART]                  = "uart",
 56         [ISS_CLK_ISP_DIV0]              = "ispdiv0",
 57         [ISS_CLK_ISP_DIV1]              = "ispdiv1",
 58         [ISS_CLK_MCUISP_DIV0]           = "mcuispdiv0",
 59         [ISS_CLK_MCUISP_DIV1]           = "mcuispdiv1",
 60         [ISS_CLK_ACLK200]               = "aclk200",
 61         [ISS_CLK_ACLK200_DIV]           = "div_aclk200",
 62         [ISS_CLK_ACLK400MCUISP]         = "aclk400mcuisp",
 63         [ISS_CLK_ACLK400MCUISP_DIV]     = "div_aclk400mcuisp",
 64 };
 65 
 66 static void fimc_is_put_clocks(struct fimc_is *is)
 67 {
 68         int i;
 69 
 70         for (i = 0; i < ISS_CLKS_MAX; i++) {
 71                 if (IS_ERR(is->clocks[i]))
 72                         continue;
 73                 clk_put(is->clocks[i]);
 74                 is->clocks[i] = ERR_PTR(-EINVAL);
 75         }
 76 }
 77 
 78 static int fimc_is_get_clocks(struct fimc_is *is)
 79 {
 80         int i, ret;
 81 
 82         for (i = 0; i < ISS_CLKS_MAX; i++)
 83                 is->clocks[i] = ERR_PTR(-EINVAL);
 84 
 85         for (i = 0; i < ISS_CLKS_MAX; i++) {
 86                 is->clocks[i] = clk_get(&is->pdev->dev, fimc_is_clocks[i]);
 87                 if (IS_ERR(is->clocks[i])) {
 88                         ret = PTR_ERR(is->clocks[i]);
 89                         goto err;
 90                 }
 91         }
 92 
 93         return 0;
 94 err:
 95         fimc_is_put_clocks(is);
 96         dev_err(&is->pdev->dev, "failed to get clock: %s\n",
 97                 fimc_is_clocks[i]);
 98         return ret;
 99 }
100 
101 static int fimc_is_setup_clocks(struct fimc_is *is)
102 {
103         int ret;
104 
105         ret = clk_set_parent(is->clocks[ISS_CLK_ACLK200],
106                                         is->clocks[ISS_CLK_ACLK200_DIV]);
107         if (ret < 0)
108                 return ret;
109 
110         ret = clk_set_parent(is->clocks[ISS_CLK_ACLK400MCUISP],
111                                         is->clocks[ISS_CLK_ACLK400MCUISP_DIV]);
112         if (ret < 0)
113                 return ret;
114 
115         ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV0], ACLK_AXI_FREQUENCY);
116         if (ret < 0)
117                 return ret;
118 
119         ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV1], ACLK_AXI_FREQUENCY);
120         if (ret < 0)
121                 return ret;
122 
123         ret = clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV0],
124                                         ATCLK_MCUISP_FREQUENCY);
125         if (ret < 0)
126                 return ret;
127 
128         return clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV1],
129                                         ATCLK_MCUISP_FREQUENCY);
130 }
131 
132 static int fimc_is_enable_clocks(struct fimc_is *is)
133 {
134         int i, ret;
135 
136         for (i = 0; i < ISS_GATE_CLKS_MAX; i++) {
137                 if (IS_ERR(is->clocks[i]))
138                         continue;
139                 ret = clk_prepare_enable(is->clocks[i]);
140                 if (ret < 0) {
141                         dev_err(&is->pdev->dev, "clock %s enable failed\n",
142                                 fimc_is_clocks[i]);
143                         for (--i; i >= 0; i--)
144                                 clk_disable(is->clocks[i]);
145                         return ret;
146                 }
147                 pr_debug("enabled clock: %s\n", fimc_is_clocks[i]);
148         }
149         return 0;
150 }
151 
152 static void fimc_is_disable_clocks(struct fimc_is *is)
153 {
154         int i;
155 
156         for (i = 0; i < ISS_GATE_CLKS_MAX; i++) {
157                 if (!IS_ERR(is->clocks[i])) {
158                         clk_disable_unprepare(is->clocks[i]);
159                         pr_debug("disabled clock: %s\n", fimc_is_clocks[i]);
160                 }
161         }
162 }
163 
164 static int fimc_is_parse_sensor_config(struct fimc_is *is, unsigned int index,
165                                                 struct device_node *node)
166 {
167         struct fimc_is_sensor *sensor = &is->sensor[index];
168         u32 tmp = 0;
169         int ret;
170 
171         sensor->drvdata = fimc_is_sensor_get_drvdata(node);
172         if (!sensor->drvdata) {
173                 dev_err(&is->pdev->dev, "no driver data found for: %s\n",
174                                                          node->full_name);
175                 return -EINVAL;
176         }
177 
178         node = of_graph_get_next_endpoint(node, NULL);
179         if (!node)
180                 return -ENXIO;
181 
182         node = of_graph_get_remote_port(node);
183         if (!node)
184                 return -ENXIO;
185 
186         /* Use MIPI-CSIS channel id to determine the ISP I2C bus index. */
187         ret = of_property_read_u32(node, "reg", &tmp);
188         if (ret < 0) {
189                 dev_err(&is->pdev->dev, "reg property not found at: %s\n",
190                                                          node->full_name);
191                 return ret;
192         }
193 
194         sensor->i2c_bus = tmp - FIMC_INPUT_MIPI_CSI2_0;
195         return 0;
196 }
197 
198 static int fimc_is_register_subdevs(struct fimc_is *is)
199 {
200         struct device_node *i2c_bus, *child;
201         int ret, index = 0;
202 
203         ret = fimc_isp_subdev_create(&is->isp);
204         if (ret < 0)
205                 return ret;
206 
207         for_each_compatible_node(i2c_bus, NULL, FIMC_IS_I2C_COMPATIBLE) {
208                 for_each_available_child_of_node(i2c_bus, child) {
209                         ret = fimc_is_parse_sensor_config(is, index, child);
210 
211                         if (ret < 0 || index >= FIMC_IS_SENSORS_NUM) {
212                                 of_node_put(child);
213                                 return ret;
214                         }
215                         index++;
216                 }
217         }
218         return 0;
219 }
220 
221 static int fimc_is_unregister_subdevs(struct fimc_is *is)
222 {
223         fimc_isp_subdev_destroy(&is->isp);
224         return 0;
225 }
226 
227 static int fimc_is_load_setfile(struct fimc_is *is, char *file_name)
228 {
229         const struct firmware *fw;
230         void *buf;
231         int ret;
232 
233         ret = request_firmware(&fw, file_name, &is->pdev->dev);
234         if (ret < 0) {
235                 dev_err(&is->pdev->dev, "firmware request failed (%d)\n", ret);
236                 return ret;
237         }
238         buf = is->memory.vaddr + is->setfile.base;
239         memcpy(buf, fw->data, fw->size);
240         fimc_is_mem_barrier();
241         is->setfile.size = fw->size;
242 
243         pr_debug("mem vaddr: %p, setfile buf: %p\n", is->memory.vaddr, buf);
244 
245         memcpy(is->fw.setfile_info,
246                 fw->data + fw->size - FIMC_IS_SETFILE_INFO_LEN,
247                 FIMC_IS_SETFILE_INFO_LEN - 1);
248 
249         is->fw.setfile_info[FIMC_IS_SETFILE_INFO_LEN - 1] = '\0';
250         is->setfile.state = 1;
251 
252         pr_debug("FIMC-IS setfile loaded: base: %#x, size: %zu B\n",
253                  is->setfile.base, fw->size);
254 
255         release_firmware(fw);
256         return ret;
257 }
258 
259 int fimc_is_cpu_set_power(struct fimc_is *is, int on)
260 {
261         unsigned int timeout = FIMC_IS_POWER_ON_TIMEOUT;
262 
263         if (on) {
264                 /* Disable watchdog */
265                 mcuctl_write(0, is, REG_WDT_ISP);
266 
267                 /* Cortex-A5 start address setting */
268                 mcuctl_write(is->memory.paddr, is, MCUCTL_REG_BBOAR);
269 
270                 /* Enable and start Cortex-A5 */
271                 pmuisp_write(0x18000, is, REG_PMU_ISP_ARM_OPTION);
272                 pmuisp_write(0x1, is, REG_PMU_ISP_ARM_CONFIGURATION);
273         } else {
274                 /* A5 power off */
275                 pmuisp_write(0x10000, is, REG_PMU_ISP_ARM_OPTION);
276                 pmuisp_write(0x0, is, REG_PMU_ISP_ARM_CONFIGURATION);
277 
278                 while (pmuisp_read(is, REG_PMU_ISP_ARM_STATUS) & 1) {
279                         if (timeout == 0)
280                                 return -ETIME;
281                         timeout--;
282                         udelay(1);
283                 }
284         }
285 
286         return 0;
287 }
288 
289 /* Wait until @bit of @is->state is set to @state in the interrupt handler. */
290 int fimc_is_wait_event(struct fimc_is *is, unsigned long bit,
291                        unsigned int state, unsigned int timeout)
292 {
293 
294         int ret = wait_event_timeout(is->irq_queue,
295                                      !state ^ test_bit(bit, &is->state),
296                                      timeout);
297         if (ret == 0) {
298                 dev_WARN(&is->pdev->dev, "%s() timed out\n", __func__);
299                 return -ETIME;
300         }
301         return 0;
302 }
303 
304 int fimc_is_start_firmware(struct fimc_is *is)
305 {
306         struct device *dev = &is->pdev->dev;
307         int ret;
308 
309         if (is->fw.f_w == NULL) {
310                 dev_err(dev, "firmware is not loaded\n");
311                 return -EINVAL;
312         }
313 
314         memcpy(is->memory.vaddr, is->fw.f_w->data, is->fw.f_w->size);
315         wmb();
316 
317         ret = fimc_is_cpu_set_power(is, 1);
318         if (ret < 0)
319                 return ret;
320 
321         ret = fimc_is_wait_event(is, IS_ST_A5_PWR_ON, 1,
322                                  msecs_to_jiffies(FIMC_IS_FW_LOAD_TIMEOUT));
323         if (ret < 0)
324                 dev_err(dev, "FIMC-IS CPU power on failed\n");
325 
326         return ret;
327 }
328 
329 /* Allocate working memory for the FIMC-IS CPU. */
330 static int fimc_is_alloc_cpu_memory(struct fimc_is *is)
331 {
332         struct device *dev = &is->pdev->dev;
333 
334         is->memory.vaddr = dma_alloc_coherent(dev, FIMC_IS_CPU_MEM_SIZE,
335                                               &is->memory.paddr, GFP_KERNEL);
336         if (is->memory.vaddr == NULL)
337                 return -ENOMEM;
338 
339         is->memory.size = FIMC_IS_CPU_MEM_SIZE;
340         memset(is->memory.vaddr, 0, is->memory.size);
341 
342         dev_info(dev, "FIMC-IS CPU memory base: %#x\n", (u32)is->memory.paddr);
343 
344         if (((u32)is->memory.paddr) & FIMC_IS_FW_ADDR_MASK) {
345                 dev_err(dev, "invalid firmware memory alignment: %#x\n",
346                         (u32)is->memory.paddr);
347                 dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
348                                   is->memory.paddr);
349                 return -EIO;
350         }
351 
352         is->is_p_region = (struct is_region *)(is->memory.vaddr +
353                                 FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE);
354 
355         is->is_dma_p_region = is->memory.paddr +
356                                 FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE;
357 
358         is->is_shared_region = (struct is_share_region *)(is->memory.vaddr +
359                                 FIMC_IS_SHARED_REGION_OFFSET);
360         return 0;
361 }
362 
363 static void fimc_is_free_cpu_memory(struct fimc_is *is)
364 {
365         struct device *dev = &is->pdev->dev;
366 
367         if (is->memory.vaddr == NULL)
368                 return;
369 
370         dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
371                           is->memory.paddr);
372 }
373 
374 static void fimc_is_load_firmware(const struct firmware *fw, void *context)
375 {
376         struct fimc_is *is = context;
377         struct device *dev = &is->pdev->dev;
378         void *buf;
379         int ret;
380 
381         if (fw == NULL) {
382                 dev_err(dev, "firmware request failed\n");
383                 return;
384         }
385         mutex_lock(&is->lock);
386 
387         if (fw->size < FIMC_IS_FW_SIZE_MIN || fw->size > FIMC_IS_FW_SIZE_MAX) {
388                 dev_err(dev, "wrong firmware size: %zu\n", fw->size);
389                 goto done;
390         }
391 
392         is->fw.size = fw->size;
393 
394         ret = fimc_is_alloc_cpu_memory(is);
395         if (ret < 0) {
396                 dev_err(dev, "failed to allocate FIMC-IS CPU memory\n");
397                 goto done;
398         }
399 
400         memcpy(is->memory.vaddr, fw->data, fw->size);
401         wmb();
402 
403         /* Read firmware description. */
404         buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_DESC_LEN);
405         memcpy(&is->fw.info, buf, FIMC_IS_FW_INFO_LEN);
406         is->fw.info[FIMC_IS_FW_INFO_LEN] = 0;
407 
408         buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_VER_LEN);
409         memcpy(&is->fw.version, buf, FIMC_IS_FW_VER_LEN);
410         is->fw.version[FIMC_IS_FW_VER_LEN - 1] = 0;
411 
412         is->fw.state = 1;
413 
414         dev_info(dev, "loaded firmware: %s, rev. %s\n",
415                  is->fw.info, is->fw.version);
416         dev_dbg(dev, "FW size: %zu, paddr: %pad\n", fw->size, &is->memory.paddr);
417 
418         is->is_shared_region->chip_id = 0xe4412;
419         is->is_shared_region->chip_rev_no = 1;
420 
421         fimc_is_mem_barrier();
422 
423         /*
424          * FIXME: The firmware is not being released for now, as it is
425          * needed around for copying to the IS working memory every
426          * time before the Cortex-A5 is restarted.
427          */
428         release_firmware(is->fw.f_w);
429         is->fw.f_w = fw;
430 done:
431         mutex_unlock(&is->lock);
432 }
433 
434 static int fimc_is_request_firmware(struct fimc_is *is, const char *fw_name)
435 {
436         return request_firmware_nowait(THIS_MODULE,
437                                 FW_ACTION_HOTPLUG, fw_name, &is->pdev->dev,
438                                 GFP_KERNEL, is, fimc_is_load_firmware);
439 }
440 
441 /* General IS interrupt handler */
442 static void fimc_is_general_irq_handler(struct fimc_is *is)
443 {
444         is->i2h_cmd.cmd = mcuctl_read(is, MCUCTL_REG_ISSR(10));
445 
446         switch (is->i2h_cmd.cmd) {
447         case IHC_GET_SENSOR_NUM:
448                 fimc_is_hw_get_params(is, 1);
449                 fimc_is_hw_wait_intmsr0_intmsd0(is);
450                 fimc_is_hw_set_sensor_num(is);
451                 pr_debug("ISP FW version: %#x\n", is->i2h_cmd.args[0]);
452                 break;
453         case IHC_SET_FACE_MARK:
454         case IHC_FRAME_DONE:
455                 fimc_is_hw_get_params(is, 2);
456                 break;
457         case IHC_SET_SHOT_MARK:
458         case IHC_AA_DONE:
459         case IH_REPLY_DONE:
460                 fimc_is_hw_get_params(is, 3);
461                 break;
462         case IH_REPLY_NOT_DONE:
463                 fimc_is_hw_get_params(is, 4);
464                 break;
465         case IHC_NOT_READY:
466                 break;
467         default:
468                 pr_info("unknown command: %#x\n", is->i2h_cmd.cmd);
469         }
470 
471         fimc_is_fw_clear_irq1(is, FIMC_IS_INT_GENERAL);
472 
473         switch (is->i2h_cmd.cmd) {
474         case IHC_GET_SENSOR_NUM:
475                 fimc_is_hw_set_intgr0_gd0(is);
476                 set_bit(IS_ST_A5_PWR_ON, &is->state);
477                 break;
478 
479         case IHC_SET_SHOT_MARK:
480                 break;
481 
482         case IHC_SET_FACE_MARK:
483                 is->fd_header.count = is->i2h_cmd.args[0];
484                 is->fd_header.index = is->i2h_cmd.args[1];
485                 is->fd_header.offset = 0;
486                 break;
487 
488         case IHC_FRAME_DONE:
489                 break;
490 
491         case IHC_AA_DONE:
492                 pr_debug("AA_DONE - %d, %d, %d\n", is->i2h_cmd.args[0],
493                          is->i2h_cmd.args[1], is->i2h_cmd.args[2]);
494                 break;
495 
496         case IH_REPLY_DONE:
497                 pr_debug("ISR_DONE: args[0]: %#x\n", is->i2h_cmd.args[0]);
498 
499                 switch (is->i2h_cmd.args[0]) {
500                 case HIC_PREVIEW_STILL...HIC_CAPTURE_VIDEO:
501                         /* Get CAC margin */
502                         set_bit(IS_ST_CHANGE_MODE, &is->state);
503                         is->isp.cac_margin_x = is->i2h_cmd.args[1];
504                         is->isp.cac_margin_y = is->i2h_cmd.args[2];
505                         pr_debug("CAC margin (x,y): (%d,%d)\n",
506                                  is->isp.cac_margin_x, is->isp.cac_margin_y);
507                         break;
508 
509                 case HIC_STREAM_ON:
510                         clear_bit(IS_ST_STREAM_OFF, &is->state);
511                         set_bit(IS_ST_STREAM_ON, &is->state);
512                         break;
513 
514                 case HIC_STREAM_OFF:
515                         clear_bit(IS_ST_STREAM_ON, &is->state);
516                         set_bit(IS_ST_STREAM_OFF, &is->state);
517                         break;
518 
519                 case HIC_SET_PARAMETER:
520                         is->config[is->config_index].p_region_index[0] = 0;
521                         is->config[is->config_index].p_region_index[1] = 0;
522                         set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
523                         pr_debug("HIC_SET_PARAMETER\n");
524                         break;
525 
526                 case HIC_GET_PARAMETER:
527                         break;
528 
529                 case HIC_SET_TUNE:
530                         break;
531 
532                 case HIC_GET_STATUS:
533                         break;
534 
535                 case HIC_OPEN_SENSOR:
536                         set_bit(IS_ST_OPEN_SENSOR, &is->state);
537                         pr_debug("data lanes: %d, settle line: %d\n",
538                                  is->i2h_cmd.args[2], is->i2h_cmd.args[1]);
539                         break;
540 
541                 case HIC_CLOSE_SENSOR:
542                         clear_bit(IS_ST_OPEN_SENSOR, &is->state);
543                         is->sensor_index = 0;
544                         break;
545 
546                 case HIC_MSG_TEST:
547                         pr_debug("config MSG level completed\n");
548                         break;
549 
550                 case HIC_POWER_DOWN:
551                         clear_bit(IS_ST_PWR_SUBIP_ON, &is->state);
552                         break;
553 
554                 case HIC_GET_SET_FILE_ADDR:
555                         is->setfile.base = is->i2h_cmd.args[1];
556                         set_bit(IS_ST_SETFILE_LOADED, &is->state);
557                         break;
558 
559                 case HIC_LOAD_SET_FILE:
560                         set_bit(IS_ST_SETFILE_LOADED, &is->state);
561                         break;
562                 }
563                 break;
564 
565         case IH_REPLY_NOT_DONE:
566                 pr_err("ISR_NDONE: %d: %#x, %s\n", is->i2h_cmd.args[0],
567                        is->i2h_cmd.args[1],
568                        fimc_is_strerr(is->i2h_cmd.args[1]));
569 
570                 if (is->i2h_cmd.args[1] & IS_ERROR_TIME_OUT_FLAG)
571                         pr_err("IS_ERROR_TIME_OUT\n");
572 
573                 switch (is->i2h_cmd.args[1]) {
574                 case IS_ERROR_SET_PARAMETER:
575                         fimc_is_mem_barrier();
576                 }
577 
578                 switch (is->i2h_cmd.args[0]) {
579                 case HIC_SET_PARAMETER:
580                         is->config[is->config_index].p_region_index[0] = 0;
581                         is->config[is->config_index].p_region_index[1] = 0;
582                         set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
583                         break;
584                 }
585                 break;
586 
587         case IHC_NOT_READY:
588                 pr_err("IS control sequence error: Not Ready\n");
589                 break;
590         }
591 
592         wake_up(&is->irq_queue);
593 }
594 
595 static irqreturn_t fimc_is_irq_handler(int irq, void *priv)
596 {
597         struct fimc_is *is = priv;
598         unsigned long flags;
599         u32 status;
600 
601         spin_lock_irqsave(&is->slock, flags);
602         status = mcuctl_read(is, MCUCTL_REG_INTSR1);
603 
604         if (status & (1UL << FIMC_IS_INT_GENERAL))
605                 fimc_is_general_irq_handler(is);
606 
607         if (status & (1UL << FIMC_IS_INT_FRAME_DONE_ISP))
608                 fimc_isp_irq_handler(is);
609 
610         spin_unlock_irqrestore(&is->slock, flags);
611         return IRQ_HANDLED;
612 }
613 
614 static int fimc_is_hw_open_sensor(struct fimc_is *is,
615                                   struct fimc_is_sensor *sensor)
616 {
617         struct sensor_open_extended *soe = (void *)&is->is_p_region->shared;
618 
619         fimc_is_hw_wait_intmsr0_intmsd0(is);
620 
621         soe->self_calibration_mode = 1;
622         soe->actuator_type = 0;
623         soe->mipi_lane_num = 0;
624         soe->mclk = 0;
625         soe->mipi_speed = 0;
626         soe->fast_open_sensor = 0;
627         soe->i2c_sclk = 88000000;
628 
629         fimc_is_mem_barrier();
630 
631         /*
632          * Some user space use cases hang up here without this
633          * empirically chosen delay.
634          */
635         udelay(100);
636 
637         mcuctl_write(HIC_OPEN_SENSOR, is, MCUCTL_REG_ISSR(0));
638         mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
639         mcuctl_write(sensor->drvdata->id, is, MCUCTL_REG_ISSR(2));
640         mcuctl_write(sensor->i2c_bus, is, MCUCTL_REG_ISSR(3));
641         mcuctl_write(is->is_dma_p_region, is, MCUCTL_REG_ISSR(4));
642 
643         fimc_is_hw_set_intgr0_gd0(is);
644 
645         return fimc_is_wait_event(is, IS_ST_OPEN_SENSOR, 1,
646                                   sensor->drvdata->open_timeout);
647 }
648 
649 
650 int fimc_is_hw_initialize(struct fimc_is *is)
651 {
652         const int config_ids[] = {
653                 IS_SC_PREVIEW_STILL, IS_SC_PREVIEW_VIDEO,
654                 IS_SC_CAPTURE_STILL, IS_SC_CAPTURE_VIDEO
655         };
656         struct device *dev = &is->pdev->dev;
657         u32 prev_id;
658         int i, ret;
659 
660         /* Sensor initialization. Only one sensor is currently supported. */
661         ret = fimc_is_hw_open_sensor(is, &is->sensor[0]);
662         if (ret < 0)
663                 return ret;
664 
665         /* Get the setfile address. */
666         fimc_is_hw_get_setfile_addr(is);
667 
668         ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1,
669                                  FIMC_IS_CONFIG_TIMEOUT);
670         if (ret < 0) {
671                 dev_err(dev, "get setfile address timed out\n");
672                 return ret;
673         }
674         pr_debug("setfile.base: %#x\n", is->setfile.base);
675 
676         /* Load the setfile. */
677         fimc_is_load_setfile(is, FIMC_IS_SETFILE_6A3);
678         clear_bit(IS_ST_SETFILE_LOADED, &is->state);
679         fimc_is_hw_load_setfile(is);
680         ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1,
681                                  FIMC_IS_CONFIG_TIMEOUT);
682         if (ret < 0) {
683                 dev_err(dev, "loading setfile timed out\n");
684                 return ret;
685         }
686 
687         pr_debug("setfile: base: %#x, size: %d\n",
688                  is->setfile.base, is->setfile.size);
689         pr_info("FIMC-IS Setfile info: %s\n", is->fw.setfile_info);
690 
691         /* Check magic number. */
692         if (is->is_p_region->shared[MAX_SHARED_COUNT - 1] !=
693             FIMC_IS_MAGIC_NUMBER) {
694                 dev_err(dev, "magic number error!\n");
695                 return -EIO;
696         }
697 
698         pr_debug("shared region: %pad, parameter region: %pad\n",
699                  &is->memory.paddr + FIMC_IS_SHARED_REGION_OFFSET,
700                  &is->is_dma_p_region);
701 
702         is->setfile.sub_index = 0;
703 
704         /* Stream off. */
705         fimc_is_hw_stream_off(is);
706         ret = fimc_is_wait_event(is, IS_ST_STREAM_OFF, 1,
707                                  FIMC_IS_CONFIG_TIMEOUT);
708         if (ret < 0) {
709                 dev_err(dev, "stream off timeout\n");
710                 return ret;
711         }
712 
713         /* Preserve previous mode. */
714         prev_id = is->config_index;
715 
716         /* Set initial parameter values. */
717         for (i = 0; i < ARRAY_SIZE(config_ids); i++) {
718                 is->config_index = config_ids[i];
719                 fimc_is_set_initial_params(is);
720                 ret = fimc_is_itf_s_param(is, true);
721                 if (ret < 0) {
722                         is->config_index = prev_id;
723                         return ret;
724                 }
725         }
726         is->config_index = prev_id;
727 
728         set_bit(IS_ST_INIT_DONE, &is->state);
729         dev_info(dev, "initialization sequence completed (%d)\n",
730                                                 is->config_index);
731         return 0;
732 }
733 
734 static int fimc_is_log_show(struct seq_file *s, void *data)
735 {
736         struct fimc_is *is = s->private;
737         const u8 *buf = is->memory.vaddr + FIMC_IS_DEBUG_REGION_OFFSET;
738 
739         if (is->memory.vaddr == NULL) {
740                 dev_err(&is->pdev->dev, "firmware memory is not initialized\n");
741                 return -EIO;
742         }
743 
744         seq_printf(s, "%s\n", buf);
745         return 0;
746 }
747 
748 static int fimc_is_debugfs_open(struct inode *inode, struct file *file)
749 {
750         return single_open(file, fimc_is_log_show, inode->i_private);
751 }
752 
753 static const struct file_operations fimc_is_debugfs_fops = {
754         .open           = fimc_is_debugfs_open,
755         .read           = seq_read,
756         .llseek         = seq_lseek,
757         .release        = single_release,
758 };
759 
760 static void fimc_is_debugfs_remove(struct fimc_is *is)
761 {
762         debugfs_remove_recursive(is->debugfs_entry);
763         is->debugfs_entry = NULL;
764 }
765 
766 static int fimc_is_debugfs_create(struct fimc_is *is)
767 {
768         struct dentry *dentry;
769 
770         is->debugfs_entry = debugfs_create_dir("fimc_is", NULL);
771 
772         dentry = debugfs_create_file("fw_log", S_IRUGO, is->debugfs_entry,
773                                      is, &fimc_is_debugfs_fops);
774         if (!dentry)
775                 fimc_is_debugfs_remove(is);
776 
777         return is->debugfs_entry == NULL ? -EIO : 0;
778 }
779 
780 static int fimc_is_runtime_resume(struct device *dev);
781 static int fimc_is_runtime_suspend(struct device *dev);
782 
783 static int fimc_is_probe(struct platform_device *pdev)
784 {
785         struct device *dev = &pdev->dev;
786         struct fimc_is *is;
787         struct resource res;
788         struct device_node *node;
789         int ret;
790 
791         is = devm_kzalloc(&pdev->dev, sizeof(*is), GFP_KERNEL);
792         if (!is)
793                 return -ENOMEM;
794 
795         is->pdev = pdev;
796         is->isp.pdev = pdev;
797 
798         init_waitqueue_head(&is->irq_queue);
799         spin_lock_init(&is->slock);
800         mutex_init(&is->lock);
801 
802         ret = of_address_to_resource(dev->of_node, 0, &res);
803         if (ret < 0)
804                 return ret;
805 
806         is->regs = devm_ioremap_resource(dev, &res);
807         if (IS_ERR(is->regs))
808                 return PTR_ERR(is->regs);
809 
810         node = of_get_child_by_name(dev->of_node, "pmu");
811         if (!node)
812                 return -ENODEV;
813 
814         is->pmu_regs = of_iomap(node, 0);
815         if (!is->pmu_regs)
816                 return -ENOMEM;
817 
818         is->irq = irq_of_parse_and_map(dev->of_node, 0);
819         if (!is->irq) {
820                 dev_err(dev, "no irq found\n");
821                 return -EINVAL;
822         }
823 
824         ret = fimc_is_get_clocks(is);
825         if (ret < 0)
826                 return ret;
827 
828         platform_set_drvdata(pdev, is);
829 
830         ret = request_irq(is->irq, fimc_is_irq_handler, 0, dev_name(dev), is);
831         if (ret < 0) {
832                 dev_err(dev, "irq request failed\n");
833                 goto err_clk;
834         }
835         pm_runtime_enable(dev);
836 
837         if (!pm_runtime_enabled(dev)) {
838                 ret = fimc_is_runtime_resume(dev);
839                 if (ret < 0)
840                         goto err_irq;
841         }
842 
843         ret = pm_runtime_get_sync(dev);
844         if (ret < 0)
845                 goto err_pm;
846 
847         vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32));
848         /*
849          * Register FIMC-IS V4L2 subdevs to this driver. The video nodes
850          * will be created within the subdev's registered() callback.
851          */
852         ret = fimc_is_register_subdevs(is);
853         if (ret < 0)
854                 goto err_pm;
855 
856         ret = fimc_is_debugfs_create(is);
857         if (ret < 0)
858                 goto err_sd;
859 
860         ret = fimc_is_request_firmware(is, FIMC_IS_FW_FILENAME);
861         if (ret < 0)
862                 goto err_dfs;
863 
864         pm_runtime_put_sync(dev);
865 
866         dev_dbg(dev, "FIMC-IS registered successfully\n");
867         return 0;
868 
869 err_dfs:
870         fimc_is_debugfs_remove(is);
871 err_sd:
872         fimc_is_unregister_subdevs(is);
873 err_pm:
874         if (!pm_runtime_enabled(dev))
875                 fimc_is_runtime_suspend(dev);
876 err_irq:
877         free_irq(is->irq, is);
878 err_clk:
879         fimc_is_put_clocks(is);
880         return ret;
881 }
882 
883 static int fimc_is_runtime_resume(struct device *dev)
884 {
885         struct fimc_is *is = dev_get_drvdata(dev);
886         int ret;
887 
888         ret = fimc_is_setup_clocks(is);
889         if (ret)
890                 return ret;
891 
892         return fimc_is_enable_clocks(is);
893 }
894 
895 static int fimc_is_runtime_suspend(struct device *dev)
896 {
897         struct fimc_is *is = dev_get_drvdata(dev);
898 
899         fimc_is_disable_clocks(is);
900         return 0;
901 }
902 
903 #ifdef CONFIG_PM_SLEEP
904 static int fimc_is_resume(struct device *dev)
905 {
906         /* TODO: */
907         return 0;
908 }
909 
910 static int fimc_is_suspend(struct device *dev)
911 {
912         struct fimc_is *is = dev_get_drvdata(dev);
913 
914         /* TODO: */
915         if (test_bit(IS_ST_A5_PWR_ON, &is->state))
916                 return -EBUSY;
917 
918         return 0;
919 }
920 #endif /* CONFIG_PM_SLEEP */
921 
922 static int fimc_is_remove(struct platform_device *pdev)
923 {
924         struct device *dev = &pdev->dev;
925         struct fimc_is *is = dev_get_drvdata(dev);
926 
927         pm_runtime_disable(dev);
928         pm_runtime_set_suspended(dev);
929         if (!pm_runtime_status_suspended(dev))
930                 fimc_is_runtime_suspend(dev);
931         free_irq(is->irq, is);
932         fimc_is_unregister_subdevs(is);
933         vb2_dma_contig_clear_max_seg_size(dev);
934         fimc_is_put_clocks(is);
935         fimc_is_debugfs_remove(is);
936         release_firmware(is->fw.f_w);
937         fimc_is_free_cpu_memory(is);
938 
939         return 0;
940 }
941 
942 static const struct of_device_id fimc_is_of_match[] = {
943         { .compatible = "samsung,exynos4212-fimc-is" },
944         { /* sentinel */ },
945 };
946 MODULE_DEVICE_TABLE(of, fimc_is_of_match);
947 
948 static const struct dev_pm_ops fimc_is_pm_ops = {
949         SET_SYSTEM_SLEEP_PM_OPS(fimc_is_suspend, fimc_is_resume)
950         SET_RUNTIME_PM_OPS(fimc_is_runtime_suspend, fimc_is_runtime_resume,
951                            NULL)
952 };
953 
954 static struct platform_driver fimc_is_driver = {
955         .probe          = fimc_is_probe,
956         .remove         = fimc_is_remove,
957         .driver = {
958                 .of_match_table = fimc_is_of_match,
959                 .name           = FIMC_IS_DRV_NAME,
960                 .pm             = &fimc_is_pm_ops,
961         }
962 };
963 
964 static int fimc_is_module_init(void)
965 {
966         int ret;
967 
968         ret = fimc_is_register_i2c_driver();
969         if (ret < 0)
970                 return ret;
971 
972         ret = platform_driver_register(&fimc_is_driver);
973 
974         if (ret < 0)
975                 fimc_is_unregister_i2c_driver();
976 
977         return ret;
978 }
979 
980 static void fimc_is_module_exit(void)
981 {
982         fimc_is_unregister_i2c_driver();
983         platform_driver_unregister(&fimc_is_driver);
984 }
985 
986 module_init(fimc_is_module_init);
987 module_exit(fimc_is_module_exit);
988 
989 MODULE_ALIAS("platform:" FIMC_IS_DRV_NAME);
990 MODULE_AUTHOR("Younghwan Joo <yhwan.joo@samsung.com>");
991 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
992 MODULE_LICENSE("GPL v2");
993 

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