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Linux/drivers/isdn/hardware/mISDN/hfcpci.c

  1 /*
  2  *
  3  * hfcpci.c     low level driver for CCD's hfc-pci based cards
  4  *
  5  * Author     Werner Cornelius (werner@isdn4linux.de)
  6  *            based on existing driver for CCD hfc ISA cards
  7  *            type approval valid for HFC-S PCI A based card
  8  *
  9  * Copyright 1999  by Werner Cornelius (werner@isdn-development.de)
 10  * Copyright 2008  by Karsten Keil <kkeil@novell.com>
 11  *
 12  * This program is free software; you can redistribute it and/or modify
 13  * it under the terms of the GNU General Public License as published by
 14  * the Free Software Foundation; either version 2, or (at your option)
 15  * any later version.
 16  *
 17  * This program is distributed in the hope that it will be useful,
 18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 20  * GNU General Public License for more details.
 21  *
 22  * You should have received a copy of the GNU General Public License
 23  * along with this program; if not, write to the Free Software
 24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 25  *
 26  * Module options:
 27  *
 28  * debug:
 29  *      NOTE: only one poll value must be given for all cards
 30  *      See hfc_pci.h for debug flags.
 31  *
 32  * poll:
 33  *      NOTE: only one poll value must be given for all cards
 34  *      Give the number of samples for each fifo process.
 35  *      By default 128 is used. Decrease to reduce delay, increase to
 36  *      reduce cpu load. If unsure, don't mess with it!
 37  *      A value of 128 will use controller's interrupt. Other values will
 38  *      use kernel timer, because the controller will not allow lower values
 39  *      than 128.
 40  *      Also note that the value depends on the kernel timer frequency.
 41  *      If kernel uses a frequency of 1000 Hz, steps of 8 samples are possible.
 42  *      If the kernel uses 100 Hz, steps of 80 samples are possible.
 43  *      If the kernel uses 300 Hz, steps of about 26 samples are possible.
 44  *
 45  */
 46 
 47 #include <linux/interrupt.h>
 48 #include <linux/module.h>
 49 #include <linux/pci.h>
 50 #include <linux/delay.h>
 51 #include <linux/mISDNhw.h>
 52 #include <linux/slab.h>
 53 
 54 #include "hfc_pci.h"
 55 
 56 static const char *hfcpci_revision = "2.0";
 57 
 58 static int HFC_cnt;
 59 static uint debug;
 60 static uint poll, tics;
 61 static struct timer_list hfc_tl;
 62 static unsigned long hfc_jiffies;
 63 
 64 MODULE_AUTHOR("Karsten Keil");
 65 MODULE_LICENSE("GPL");
 66 module_param(debug, uint, S_IRUGO | S_IWUSR);
 67 module_param(poll, uint, S_IRUGO | S_IWUSR);
 68 
 69 enum {
 70         HFC_CCD_2BD0,
 71         HFC_CCD_B000,
 72         HFC_CCD_B006,
 73         HFC_CCD_B007,
 74         HFC_CCD_B008,
 75         HFC_CCD_B009,
 76         HFC_CCD_B00A,
 77         HFC_CCD_B00B,
 78         HFC_CCD_B00C,
 79         HFC_CCD_B100,
 80         HFC_CCD_B700,
 81         HFC_CCD_B701,
 82         HFC_ASUS_0675,
 83         HFC_BERKOM_A1T,
 84         HFC_BERKOM_TCONCEPT,
 85         HFC_ANIGMA_MC145575,
 86         HFC_ZOLTRIX_2BD0,
 87         HFC_DIGI_DF_M_IOM2_E,
 88         HFC_DIGI_DF_M_E,
 89         HFC_DIGI_DF_M_IOM2_A,
 90         HFC_DIGI_DF_M_A,
 91         HFC_ABOCOM_2BD1,
 92         HFC_SITECOM_DC105V2,
 93 };
 94 
 95 struct hfcPCI_hw {
 96         unsigned char           cirm;
 97         unsigned char           ctmt;
 98         unsigned char           clkdel;
 99         unsigned char           states;
100         unsigned char           conn;
101         unsigned char           mst_m;
102         unsigned char           int_m1;
103         unsigned char           int_m2;
104         unsigned char           sctrl;
105         unsigned char           sctrl_r;
106         unsigned char           sctrl_e;
107         unsigned char           trm;
108         unsigned char           fifo_en;
109         unsigned char           bswapped;
110         unsigned char           protocol;
111         int                     nt_timer;
112         unsigned char __iomem   *pci_io; /* start of PCI IO memory */
113         dma_addr_t              dmahandle;
114         void                    *fifos; /* FIFO memory */
115         int                     last_bfifo_cnt[2];
116         /* marker saving last b-fifo frame count */
117         struct timer_list       timer;
118 };
119 
120 #define HFC_CFG_MASTER          1
121 #define HFC_CFG_SLAVE           2
122 #define HFC_CFG_PCM             3
123 #define HFC_CFG_2HFC            4
124 #define HFC_CFG_SLAVEHFC        5
125 #define HFC_CFG_NEG_F0          6
126 #define HFC_CFG_SW_DD_DU        7
127 
128 #define FLG_HFC_TIMER_T1        16
129 #define FLG_HFC_TIMER_T3        17
130 
131 #define NT_T1_COUNT     1120    /* number of 3.125ms interrupts (3.5s) */
132 #define NT_T3_COUNT     31      /* number of 3.125ms interrupts (97 ms) */
133 #define CLKDEL_TE       0x0e    /* CLKDEL in TE mode */
134 #define CLKDEL_NT       0x6c    /* CLKDEL in NT mode */
135 
136 
137 struct hfc_pci {
138         u_char                  subtype;
139         u_char                  chanlimit;
140         u_char                  initdone;
141         u_long                  cfg;
142         u_int                   irq;
143         u_int                   irqcnt;
144         struct pci_dev          *pdev;
145         struct hfcPCI_hw        hw;
146         spinlock_t              lock;   /* card lock */
147         struct dchannel         dch;
148         struct bchannel         bch[2];
149 };
150 
151 /* Interface functions */
152 static void
153 enable_hwirq(struct hfc_pci *hc)
154 {
155         hc->hw.int_m2 |= HFCPCI_IRQ_ENABLE;
156         Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
157 }
158 
159 static void
160 disable_hwirq(struct hfc_pci *hc)
161 {
162         hc->hw.int_m2 &= ~((u_char)HFCPCI_IRQ_ENABLE);
163         Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
164 }
165 
166 /*
167  * free hardware resources used by driver
168  */
169 static void
170 release_io_hfcpci(struct hfc_pci *hc)
171 {
172         /* disable memory mapped ports + busmaster */
173         pci_write_config_word(hc->pdev, PCI_COMMAND, 0);
174         del_timer(&hc->hw.timer);
175         pci_free_consistent(hc->pdev, 0x8000, hc->hw.fifos, hc->hw.dmahandle);
176         iounmap(hc->hw.pci_io);
177 }
178 
179 /*
180  * set mode (NT or TE)
181  */
182 static void
183 hfcpci_setmode(struct hfc_pci *hc)
184 {
185         if (hc->hw.protocol == ISDN_P_NT_S0) {
186                 hc->hw.clkdel = CLKDEL_NT;      /* ST-Bit delay for NT-Mode */
187                 hc->hw.sctrl |= SCTRL_MODE_NT;  /* NT-MODE */
188                 hc->hw.states = 1;              /* G1 */
189         } else {
190                 hc->hw.clkdel = CLKDEL_TE;      /* ST-Bit delay for TE-Mode */
191                 hc->hw.sctrl &= ~SCTRL_MODE_NT; /* TE-MODE */
192                 hc->hw.states = 2;              /* F2 */
193         }
194         Write_hfc(hc, HFCPCI_CLKDEL, hc->hw.clkdel);
195         Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | hc->hw.states);
196         udelay(10);
197         Write_hfc(hc, HFCPCI_STATES, hc->hw.states | 0x40); /* Deactivate */
198         Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
199 }
200 
201 /*
202  * function called to reset the HFC PCI chip. A complete software reset of chip
203  * and fifos is done.
204  */
205 static void
206 reset_hfcpci(struct hfc_pci *hc)
207 {
208         u_char  val;
209         int     cnt = 0;
210 
211         printk(KERN_DEBUG "reset_hfcpci: entered\n");
212         val = Read_hfc(hc, HFCPCI_CHIP_ID);
213         printk(KERN_INFO "HFC_PCI: resetting HFC ChipId(%x)\n", val);
214         /* enable memory mapped ports, disable busmaster */
215         pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
216         disable_hwirq(hc);
217         /* enable memory ports + busmaster */
218         pci_write_config_word(hc->pdev, PCI_COMMAND,
219                               PCI_ENA_MEMIO + PCI_ENA_MASTER);
220         val = Read_hfc(hc, HFCPCI_STATUS);
221         printk(KERN_DEBUG "HFC-PCI status(%x) before reset\n", val);
222         hc->hw.cirm = HFCPCI_RESET;     /* Reset On */
223         Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
224         set_current_state(TASK_UNINTERRUPTIBLE);
225         mdelay(10);                     /* Timeout 10ms */
226         hc->hw.cirm = 0;                /* Reset Off */
227         Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
228         val = Read_hfc(hc, HFCPCI_STATUS);
229         printk(KERN_DEBUG "HFC-PCI status(%x) after reset\n", val);
230         while (cnt < 50000) { /* max 50000 us */
231                 udelay(5);
232                 cnt += 5;
233                 val = Read_hfc(hc, HFCPCI_STATUS);
234                 if (!(val & 2))
235                         break;
236         }
237         printk(KERN_DEBUG "HFC-PCI status(%x) after %dus\n", val, cnt);
238 
239         hc->hw.fifo_en = 0x30;  /* only D fifos enabled */
240 
241         hc->hw.bswapped = 0;    /* no exchange */
242         hc->hw.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER;
243         hc->hw.trm = HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */
244         hc->hw.sctrl = 0x40;    /* set tx_lo mode, error in datasheet ! */
245         hc->hw.sctrl_r = 0;
246         hc->hw.sctrl_e = HFCPCI_AUTO_AWAKE;     /* S/T Auto awake */
247         hc->hw.mst_m = 0;
248         if (test_bit(HFC_CFG_MASTER, &hc->cfg))
249                 hc->hw.mst_m |= HFCPCI_MASTER;  /* HFC Master Mode */
250         if (test_bit(HFC_CFG_NEG_F0, &hc->cfg))
251                 hc->hw.mst_m |= HFCPCI_F0_NEGATIV;
252         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
253         Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
254         Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
255         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
256 
257         hc->hw.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC |
258                 HFCPCI_INTS_L1STATE | HFCPCI_INTS_TIMER;
259         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
260 
261         /* Clear already pending ints */
262         val = Read_hfc(hc, HFCPCI_INT_S1);
263 
264         /* set NT/TE mode */
265         hfcpci_setmode(hc);
266 
267         Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
268         Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
269 
270         /*
271          * Init GCI/IOM2 in master mode
272          * Slots 0 and 1 are set for B-chan 1 and 2
273          * D- and monitor/CI channel are not enabled
274          * STIO1 is used as output for data, B1+B2 from ST->IOM+HFC
275          * STIO2 is used as data input, B1+B2 from IOM->ST
276          * ST B-channel send disabled -> continuous 1s
277          * The IOM slots are always enabled
278          */
279         if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
280                 /* set data flow directions: connect B1,B2: HFC to/from PCM */
281                 hc->hw.conn = 0x09;
282         } else {
283                 hc->hw.conn = 0x36;     /* set data flow directions */
284                 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
285                         Write_hfc(hc, HFCPCI_B1_SSL, 0xC0);
286                         Write_hfc(hc, HFCPCI_B2_SSL, 0xC1);
287                         Write_hfc(hc, HFCPCI_B1_RSL, 0xC0);
288                         Write_hfc(hc, HFCPCI_B2_RSL, 0xC1);
289                 } else {
290                         Write_hfc(hc, HFCPCI_B1_SSL, 0x80);
291                         Write_hfc(hc, HFCPCI_B2_SSL, 0x81);
292                         Write_hfc(hc, HFCPCI_B1_RSL, 0x80);
293                         Write_hfc(hc, HFCPCI_B2_RSL, 0x81);
294                 }
295         }
296         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
297         val = Read_hfc(hc, HFCPCI_INT_S2);
298 }
299 
300 /*
301  * Timer function called when kernel timer expires
302  */
303 static void
304 hfcpci_Timer(struct hfc_pci *hc)
305 {
306         hc->hw.timer.expires = jiffies + 75;
307         /* WD RESET */
308 /*
309  *      WriteReg(hc, HFCD_DATA, HFCD_CTMT, hc->hw.ctmt | 0x80);
310  *      add_timer(&hc->hw.timer);
311  */
312 }
313 
314 
315 /*
316  * select a b-channel entry matching and active
317  */
318 static struct bchannel *
319 Sel_BCS(struct hfc_pci *hc, int channel)
320 {
321         if (test_bit(FLG_ACTIVE, &hc->bch[0].Flags) &&
322             (hc->bch[0].nr & channel))
323                 return &hc->bch[0];
324         else if (test_bit(FLG_ACTIVE, &hc->bch[1].Flags) &&
325                  (hc->bch[1].nr & channel))
326                 return &hc->bch[1];
327         else
328                 return NULL;
329 }
330 
331 /*
332  * clear the desired B-channel rx fifo
333  */
334 static void
335 hfcpci_clear_fifo_rx(struct hfc_pci *hc, int fifo)
336 {
337         u_char          fifo_state;
338         struct bzfifo   *bzr;
339 
340         if (fifo) {
341                 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
342                 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2RX;
343         } else {
344                 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
345                 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1RX;
346         }
347         if (fifo_state)
348                 hc->hw.fifo_en ^= fifo_state;
349         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
350         hc->hw.last_bfifo_cnt[fifo] = 0;
351         bzr->f1 = MAX_B_FRAMES;
352         bzr->f2 = bzr->f1;      /* init F pointers to remain constant */
353         bzr->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
354         bzr->za[MAX_B_FRAMES].z2 = cpu_to_le16(
355                 le16_to_cpu(bzr->za[MAX_B_FRAMES].z1));
356         if (fifo_state)
357                 hc->hw.fifo_en |= fifo_state;
358         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
359 }
360 
361 /*
362  * clear the desired B-channel tx fifo
363  */
364 static void hfcpci_clear_fifo_tx(struct hfc_pci *hc, int fifo)
365 {
366         u_char          fifo_state;
367         struct bzfifo   *bzt;
368 
369         if (fifo) {
370                 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
371                 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2TX;
372         } else {
373                 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
374                 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1TX;
375         }
376         if (fifo_state)
377                 hc->hw.fifo_en ^= fifo_state;
378         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
379         if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
380                 printk(KERN_DEBUG "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) "
381                        "z1(%x) z2(%x) state(%x)\n",
382                        fifo, bzt->f1, bzt->f2,
383                        le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
384                        le16_to_cpu(bzt->za[MAX_B_FRAMES].z2),
385                        fifo_state);
386         bzt->f2 = MAX_B_FRAMES;
387         bzt->f1 = bzt->f2;      /* init F pointers to remain constant */
388         bzt->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
389         bzt->za[MAX_B_FRAMES].z2 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 2);
390         if (fifo_state)
391                 hc->hw.fifo_en |= fifo_state;
392         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
393         if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
394                 printk(KERN_DEBUG
395                        "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) z1(%x) z2(%x)\n",
396                        fifo, bzt->f1, bzt->f2,
397                        le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
398                        le16_to_cpu(bzt->za[MAX_B_FRAMES].z2));
399 }
400 
401 /*
402  * read a complete B-frame out of the buffer
403  */
404 static void
405 hfcpci_empty_bfifo(struct bchannel *bch, struct bzfifo *bz,
406                    u_char *bdata, int count)
407 {
408         u_char          *ptr, *ptr1, new_f2;
409         int             maxlen, new_z2;
410         struct zt       *zp;
411 
412         if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
413                 printk(KERN_DEBUG "hfcpci_empty_fifo\n");
414         zp = &bz->za[bz->f2];   /* point to Z-Regs */
415         new_z2 = le16_to_cpu(zp->z2) + count;   /* new position in fifo */
416         if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
417                 new_z2 -= B_FIFO_SIZE;  /* buffer wrap */
418         new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
419         if ((count > MAX_DATA_SIZE + 3) || (count < 4) ||
420             (*(bdata + (le16_to_cpu(zp->z1) - B_SUB_VAL)))) {
421                 if (bch->debug & DEBUG_HW)
422                         printk(KERN_DEBUG "hfcpci_empty_fifo: incoming packet "
423                                "invalid length %d or crc\n", count);
424 #ifdef ERROR_STATISTIC
425                 bch->err_inv++;
426 #endif
427                 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
428                 bz->f2 = new_f2;        /* next buffer */
429         } else {
430                 bch->rx_skb = mI_alloc_skb(count - 3, GFP_ATOMIC);
431                 if (!bch->rx_skb) {
432                         printk(KERN_WARNING "HFCPCI: receive out of memory\n");
433                         return;
434                 }
435                 count -= 3;
436                 ptr = skb_put(bch->rx_skb, count);
437 
438                 if (le16_to_cpu(zp->z2) + count <= B_FIFO_SIZE + B_SUB_VAL)
439                         maxlen = count;         /* complete transfer */
440                 else
441                         maxlen = B_FIFO_SIZE + B_SUB_VAL -
442                                 le16_to_cpu(zp->z2);    /* maximum */
443 
444                 ptr1 = bdata + (le16_to_cpu(zp->z2) - B_SUB_VAL);
445                 /* start of data */
446                 memcpy(ptr, ptr1, maxlen);      /* copy data */
447                 count -= maxlen;
448 
449                 if (count) {    /* rest remaining */
450                         ptr += maxlen;
451                         ptr1 = bdata;   /* start of buffer */
452                         memcpy(ptr, ptr1, count);       /* rest */
453                 }
454                 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
455                 bz->f2 = new_f2;        /* next buffer */
456                 recv_Bchannel(bch, MISDN_ID_ANY, false);
457         }
458 }
459 
460 /*
461  * D-channel receive procedure
462  */
463 static int
464 receive_dmsg(struct hfc_pci *hc)
465 {
466         struct dchannel *dch = &hc->dch;
467         int             maxlen;
468         int             rcnt, total;
469         int             count = 5;
470         u_char          *ptr, *ptr1;
471         struct dfifo    *df;
472         struct zt       *zp;
473 
474         df = &((union fifo_area *)(hc->hw.fifos))->d_chan.d_rx;
475         while (((df->f1 & D_FREG_MASK) != (df->f2 & D_FREG_MASK)) && count--) {
476                 zp = &df->za[df->f2 & D_FREG_MASK];
477                 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
478                 if (rcnt < 0)
479                         rcnt += D_FIFO_SIZE;
480                 rcnt++;
481                 if (dch->debug & DEBUG_HW_DCHANNEL)
482                         printk(KERN_DEBUG
483                                "hfcpci recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)\n",
484                                df->f1, df->f2,
485                                le16_to_cpu(zp->z1),
486                                le16_to_cpu(zp->z2),
487                                rcnt);
488 
489                 if ((rcnt > MAX_DFRAME_LEN + 3) || (rcnt < 4) ||
490                     (df->data[le16_to_cpu(zp->z1)])) {
491                         if (dch->debug & DEBUG_HW)
492                                 printk(KERN_DEBUG
493                                        "empty_fifo hfcpci packet inv. len "
494                                        "%d or crc %d\n",
495                                        rcnt,
496                                        df->data[le16_to_cpu(zp->z1)]);
497 #ifdef ERROR_STATISTIC
498                         cs->err_rx++;
499 #endif
500                         df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
501                                 (MAX_D_FRAMES + 1);     /* next buffer */
502                         df->za[df->f2 & D_FREG_MASK].z2 =
503                                 cpu_to_le16((le16_to_cpu(zp->z2) + rcnt) &
504                                             (D_FIFO_SIZE - 1));
505                 } else {
506                         dch->rx_skb = mI_alloc_skb(rcnt - 3, GFP_ATOMIC);
507                         if (!dch->rx_skb) {
508                                 printk(KERN_WARNING
509                                        "HFC-PCI: D receive out of memory\n");
510                                 break;
511                         }
512                         total = rcnt;
513                         rcnt -= 3;
514                         ptr = skb_put(dch->rx_skb, rcnt);
515 
516                         if (le16_to_cpu(zp->z2) + rcnt <= D_FIFO_SIZE)
517                                 maxlen = rcnt;  /* complete transfer */
518                         else
519                                 maxlen = D_FIFO_SIZE - le16_to_cpu(zp->z2);
520                         /* maximum */
521 
522                         ptr1 = df->data + le16_to_cpu(zp->z2);
523                         /* start of data */
524                         memcpy(ptr, ptr1, maxlen);      /* copy data */
525                         rcnt -= maxlen;
526 
527                         if (rcnt) {     /* rest remaining */
528                                 ptr += maxlen;
529                                 ptr1 = df->data;        /* start of buffer */
530                                 memcpy(ptr, ptr1, rcnt);        /* rest */
531                         }
532                         df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
533                                 (MAX_D_FRAMES + 1);     /* next buffer */
534                         df->za[df->f2 & D_FREG_MASK].z2 = cpu_to_le16((
535                                                                               le16_to_cpu(zp->z2) + total) & (D_FIFO_SIZE - 1));
536                         recv_Dchannel(dch);
537                 }
538         }
539         return 1;
540 }
541 
542 /*
543  * check for transparent receive data and read max one 'poll' size if avail
544  */
545 static void
546 hfcpci_empty_fifo_trans(struct bchannel *bch, struct bzfifo *rxbz,
547                         struct bzfifo *txbz, u_char *bdata)
548 {
549         __le16  *z1r, *z2r, *z1t, *z2t;
550         int     new_z2, fcnt_rx, fcnt_tx, maxlen;
551         u_char  *ptr, *ptr1;
552 
553         z1r = &rxbz->za[MAX_B_FRAMES].z1;       /* pointer to z reg */
554         z2r = z1r + 1;
555         z1t = &txbz->za[MAX_B_FRAMES].z1;
556         z2t = z1t + 1;
557 
558         fcnt_rx = le16_to_cpu(*z1r) - le16_to_cpu(*z2r);
559         if (!fcnt_rx)
560                 return; /* no data avail */
561 
562         if (fcnt_rx <= 0)
563                 fcnt_rx += B_FIFO_SIZE; /* bytes actually buffered */
564         new_z2 = le16_to_cpu(*z2r) + fcnt_rx;   /* new position in fifo */
565         if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
566                 new_z2 -= B_FIFO_SIZE;  /* buffer wrap */
567 
568         fcnt_tx = le16_to_cpu(*z2t) - le16_to_cpu(*z1t);
569         if (fcnt_tx <= 0)
570                 fcnt_tx += B_FIFO_SIZE;
571         /* fcnt_tx contains available bytes in tx-fifo */
572         fcnt_tx = B_FIFO_SIZE - fcnt_tx;
573         /* remaining bytes to send (bytes in tx-fifo) */
574 
575         if (test_bit(FLG_RX_OFF, &bch->Flags)) {
576                 bch->dropcnt += fcnt_rx;
577                 *z2r = cpu_to_le16(new_z2);
578                 return;
579         }
580         maxlen = bchannel_get_rxbuf(bch, fcnt_rx);
581         if (maxlen < 0) {
582                 pr_warning("B%d: No bufferspace for %d bytes\n",
583                            bch->nr, fcnt_rx);
584         } else {
585                 ptr = skb_put(bch->rx_skb, fcnt_rx);
586                 if (le16_to_cpu(*z2r) + fcnt_rx <= B_FIFO_SIZE + B_SUB_VAL)
587                         maxlen = fcnt_rx;       /* complete transfer */
588                 else
589                         maxlen = B_FIFO_SIZE + B_SUB_VAL - le16_to_cpu(*z2r);
590                 /* maximum */
591 
592                 ptr1 = bdata + (le16_to_cpu(*z2r) - B_SUB_VAL);
593                 /* start of data */
594                 memcpy(ptr, ptr1, maxlen);      /* copy data */
595                 fcnt_rx -= maxlen;
596 
597                 if (fcnt_rx) {  /* rest remaining */
598                         ptr += maxlen;
599                         ptr1 = bdata;   /* start of buffer */
600                         memcpy(ptr, ptr1, fcnt_rx);     /* rest */
601                 }
602                 recv_Bchannel(bch, fcnt_tx, false); /* bch, id, !force */
603         }
604         *z2r = cpu_to_le16(new_z2);             /* new position */
605 }
606 
607 /*
608  * B-channel main receive routine
609  */
610 static void
611 main_rec_hfcpci(struct bchannel *bch)
612 {
613         struct hfc_pci  *hc = bch->hw;
614         int             rcnt, real_fifo;
615         int             receive = 0, count = 5;
616         struct bzfifo   *txbz, *rxbz;
617         u_char          *bdata;
618         struct zt       *zp;
619 
620         if ((bch->nr & 2) && (!hc->hw.bswapped)) {
621                 rxbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
622                 txbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
623                 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b2;
624                 real_fifo = 1;
625         } else {
626                 rxbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
627                 txbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
628                 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b1;
629                 real_fifo = 0;
630         }
631 Begin:
632         count--;
633         if (rxbz->f1 != rxbz->f2) {
634                 if (bch->debug & DEBUG_HW_BCHANNEL)
635                         printk(KERN_DEBUG "hfcpci rec ch(%x) f1(%d) f2(%d)\n",
636                                bch->nr, rxbz->f1, rxbz->f2);
637                 zp = &rxbz->za[rxbz->f2];
638 
639                 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
640                 if (rcnt < 0)
641                         rcnt += B_FIFO_SIZE;
642                 rcnt++;
643                 if (bch->debug & DEBUG_HW_BCHANNEL)
644                         printk(KERN_DEBUG
645                                "hfcpci rec ch(%x) z1(%x) z2(%x) cnt(%d)\n",
646                                bch->nr, le16_to_cpu(zp->z1),
647                                le16_to_cpu(zp->z2), rcnt);
648                 hfcpci_empty_bfifo(bch, rxbz, bdata, rcnt);
649                 rcnt = rxbz->f1 - rxbz->f2;
650                 if (rcnt < 0)
651                         rcnt += MAX_B_FRAMES + 1;
652                 if (hc->hw.last_bfifo_cnt[real_fifo] > rcnt + 1) {
653                         rcnt = 0;
654                         hfcpci_clear_fifo_rx(hc, real_fifo);
655                 }
656                 hc->hw.last_bfifo_cnt[real_fifo] = rcnt;
657                 if (rcnt > 1)
658                         receive = 1;
659                 else
660                         receive = 0;
661         } else if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
662                 hfcpci_empty_fifo_trans(bch, rxbz, txbz, bdata);
663                 return;
664         } else
665                 receive = 0;
666         if (count && receive)
667                 goto Begin;
668 
669 }
670 
671 /*
672  * D-channel send routine
673  */
674 static void
675 hfcpci_fill_dfifo(struct hfc_pci *hc)
676 {
677         struct dchannel *dch = &hc->dch;
678         int             fcnt;
679         int             count, new_z1, maxlen;
680         struct dfifo    *df;
681         u_char          *src, *dst, new_f1;
682 
683         if ((dch->debug & DEBUG_HW_DCHANNEL) && !(dch->debug & DEBUG_HW_DFIFO))
684                 printk(KERN_DEBUG "%s\n", __func__);
685 
686         if (!dch->tx_skb)
687                 return;
688         count = dch->tx_skb->len - dch->tx_idx;
689         if (count <= 0)
690                 return;
691         df = &((union fifo_area *) (hc->hw.fifos))->d_chan.d_tx;
692 
693         if (dch->debug & DEBUG_HW_DFIFO)
694                 printk(KERN_DEBUG "%s:f1(%d) f2(%d) z1(f1)(%x)\n", __func__,
695                        df->f1, df->f2,
696                        le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1));
697         fcnt = df->f1 - df->f2; /* frame count actually buffered */
698         if (fcnt < 0)
699                 fcnt += (MAX_D_FRAMES + 1);     /* if wrap around */
700         if (fcnt > (MAX_D_FRAMES - 1)) {
701                 if (dch->debug & DEBUG_HW_DCHANNEL)
702                         printk(KERN_DEBUG
703                                "hfcpci_fill_Dfifo more as 14 frames\n");
704 #ifdef ERROR_STATISTIC
705                 cs->err_tx++;
706 #endif
707                 return;
708         }
709         /* now determine free bytes in FIFO buffer */
710         maxlen = le16_to_cpu(df->za[df->f2 & D_FREG_MASK].z2) -
711                 le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) - 1;
712         if (maxlen <= 0)
713                 maxlen += D_FIFO_SIZE;  /* count now contains available bytes */
714 
715         if (dch->debug & DEBUG_HW_DCHANNEL)
716                 printk(KERN_DEBUG "hfcpci_fill_Dfifo count(%d/%d)\n",
717                        count, maxlen);
718         if (count > maxlen) {
719                 if (dch->debug & DEBUG_HW_DCHANNEL)
720                         printk(KERN_DEBUG "hfcpci_fill_Dfifo no fifo mem\n");
721                 return;
722         }
723         new_z1 = (le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) + count) &
724                 (D_FIFO_SIZE - 1);
725         new_f1 = ((df->f1 + 1) & D_FREG_MASK) | (D_FREG_MASK + 1);
726         src = dch->tx_skb->data + dch->tx_idx;  /* source pointer */
727         dst = df->data + le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
728         maxlen = D_FIFO_SIZE - le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
729         /* end fifo */
730         if (maxlen > count)
731                 maxlen = count; /* limit size */
732         memcpy(dst, src, maxlen);       /* first copy */
733 
734         count -= maxlen;        /* remaining bytes */
735         if (count) {
736                 dst = df->data; /* start of buffer */
737                 src += maxlen;  /* new position */
738                 memcpy(dst, src, count);
739         }
740         df->za[new_f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
741         /* for next buffer */
742         df->za[df->f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
743         /* new pos actual buffer */
744         df->f1 = new_f1;        /* next frame */
745         dch->tx_idx = dch->tx_skb->len;
746 }
747 
748 /*
749  * B-channel send routine
750  */
751 static void
752 hfcpci_fill_fifo(struct bchannel *bch)
753 {
754         struct hfc_pci  *hc = bch->hw;
755         int             maxlen, fcnt;
756         int             count, new_z1;
757         struct bzfifo   *bz;
758         u_char          *bdata;
759         u_char          new_f1, *src, *dst;
760         __le16 *z1t, *z2t;
761 
762         if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
763                 printk(KERN_DEBUG "%s\n", __func__);
764         if ((!bch->tx_skb) || bch->tx_skb->len == 0) {
765                 if (!test_bit(FLG_FILLEMPTY, &bch->Flags) &&
766                     !test_bit(FLG_TRANSPARENT, &bch->Flags))
767                         return;
768                 count = HFCPCI_FILLEMPTY;
769         } else {
770                 count = bch->tx_skb->len - bch->tx_idx;
771         }
772         if ((bch->nr & 2) && (!hc->hw.bswapped)) {
773                 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
774                 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b2;
775         } else {
776                 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
777                 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b1;
778         }
779 
780         if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
781                 z1t = &bz->za[MAX_B_FRAMES].z1;
782                 z2t = z1t + 1;
783                 if (bch->debug & DEBUG_HW_BCHANNEL)
784                         printk(KERN_DEBUG "hfcpci_fill_fifo_trans ch(%x) "
785                                "cnt(%d) z1(%x) z2(%x)\n", bch->nr, count,
786                                le16_to_cpu(*z1t), le16_to_cpu(*z2t));
787                 fcnt = le16_to_cpu(*z2t) - le16_to_cpu(*z1t);
788                 if (fcnt <= 0)
789                         fcnt += B_FIFO_SIZE;
790                 if (test_bit(FLG_FILLEMPTY, &bch->Flags)) {
791                         /* fcnt contains available bytes in fifo */
792                         if (count > fcnt)
793                                 count = fcnt;
794                         new_z1 = le16_to_cpu(*z1t) + count;
795                         /* new buffer Position */
796                         if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
797                                 new_z1 -= B_FIFO_SIZE;  /* buffer wrap */
798                         dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
799                         maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
800                         /* end of fifo */
801                         if (bch->debug & DEBUG_HW_BFIFO)
802                                 printk(KERN_DEBUG "hfcpci_FFt fillempty "
803                                        "fcnt(%d) maxl(%d) nz1(%x) dst(%p)\n",
804                                        fcnt, maxlen, new_z1, dst);
805                         if (maxlen > count)
806                                 maxlen = count;         /* limit size */
807                         memset(dst, bch->fill[0], maxlen); /* first copy */
808                         count -= maxlen;                /* remaining bytes */
809                         if (count) {
810                                 dst = bdata;            /* start of buffer */
811                                 memset(dst, bch->fill[0], count);
812                         }
813                         *z1t = cpu_to_le16(new_z1);     /* now send data */
814                         return;
815                 }
816                 /* fcnt contains available bytes in fifo */
817                 fcnt = B_FIFO_SIZE - fcnt;
818                 /* remaining bytes to send (bytes in fifo) */
819 
820         next_t_frame:
821                 count = bch->tx_skb->len - bch->tx_idx;
822                 /* maximum fill shall be poll*2 */
823                 if (count > (poll << 1) - fcnt)
824                         count = (poll << 1) - fcnt;
825                 if (count <= 0)
826                         return;
827                 /* data is suitable for fifo */
828                 new_z1 = le16_to_cpu(*z1t) + count;
829                 /* new buffer Position */
830                 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
831                         new_z1 -= B_FIFO_SIZE;  /* buffer wrap */
832                 src = bch->tx_skb->data + bch->tx_idx;
833                 /* source pointer */
834                 dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
835                 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
836                 /* end of fifo */
837                 if (bch->debug & DEBUG_HW_BFIFO)
838                         printk(KERN_DEBUG "hfcpci_FFt fcnt(%d) "
839                                "maxl(%d) nz1(%x) dst(%p)\n",
840                                fcnt, maxlen, new_z1, dst);
841                 fcnt += count;
842                 bch->tx_idx += count;
843                 if (maxlen > count)
844                         maxlen = count;         /* limit size */
845                 memcpy(dst, src, maxlen);       /* first copy */
846                 count -= maxlen;        /* remaining bytes */
847                 if (count) {
848                         dst = bdata;    /* start of buffer */
849                         src += maxlen;  /* new position */
850                         memcpy(dst, src, count);
851                 }
852                 *z1t = cpu_to_le16(new_z1);     /* now send data */
853                 if (bch->tx_idx < bch->tx_skb->len)
854                         return;
855                 dev_kfree_skb(bch->tx_skb);
856                 if (get_next_bframe(bch))
857                         goto next_t_frame;
858                 return;
859         }
860         if (bch->debug & DEBUG_HW_BCHANNEL)
861                 printk(KERN_DEBUG
862                        "%s: ch(%x) f1(%d) f2(%d) z1(f1)(%x)\n",
863                        __func__, bch->nr, bz->f1, bz->f2,
864                        bz->za[bz->f1].z1);
865         fcnt = bz->f1 - bz->f2; /* frame count actually buffered */
866         if (fcnt < 0)
867                 fcnt += (MAX_B_FRAMES + 1);     /* if wrap around */
868         if (fcnt > (MAX_B_FRAMES - 1)) {
869                 if (bch->debug & DEBUG_HW_BCHANNEL)
870                         printk(KERN_DEBUG
871                                "hfcpci_fill_Bfifo more as 14 frames\n");
872                 return;
873         }
874         /* now determine free bytes in FIFO buffer */
875         maxlen = le16_to_cpu(bz->za[bz->f2].z2) -
876                 le16_to_cpu(bz->za[bz->f1].z1) - 1;
877         if (maxlen <= 0)
878                 maxlen += B_FIFO_SIZE;  /* count now contains available bytes */
879 
880         if (bch->debug & DEBUG_HW_BCHANNEL)
881                 printk(KERN_DEBUG "hfcpci_fill_fifo ch(%x) count(%d/%d)\n",
882                        bch->nr, count, maxlen);
883 
884         if (maxlen < count) {
885                 if (bch->debug & DEBUG_HW_BCHANNEL)
886                         printk(KERN_DEBUG "hfcpci_fill_fifo no fifo mem\n");
887                 return;
888         }
889         new_z1 = le16_to_cpu(bz->za[bz->f1].z1) + count;
890         /* new buffer Position */
891         if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
892                 new_z1 -= B_FIFO_SIZE;  /* buffer wrap */
893 
894         new_f1 = ((bz->f1 + 1) & MAX_B_FRAMES);
895         src = bch->tx_skb->data + bch->tx_idx;  /* source pointer */
896         dst = bdata + (le16_to_cpu(bz->za[bz->f1].z1) - B_SUB_VAL);
897         maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(bz->za[bz->f1].z1);
898         /* end fifo */
899         if (maxlen > count)
900                 maxlen = count; /* limit size */
901         memcpy(dst, src, maxlen);       /* first copy */
902 
903         count -= maxlen;        /* remaining bytes */
904         if (count) {
905                 dst = bdata;    /* start of buffer */
906                 src += maxlen;  /* new position */
907                 memcpy(dst, src, count);
908         }
909         bz->za[new_f1].z1 = cpu_to_le16(new_z1);        /* for next buffer */
910         bz->f1 = new_f1;        /* next frame */
911         dev_kfree_skb(bch->tx_skb);
912         get_next_bframe(bch);
913 }
914 
915 
916 
917 /*
918  * handle L1 state changes TE
919  */
920 
921 static void
922 ph_state_te(struct dchannel *dch)
923 {
924         if (dch->debug)
925                 printk(KERN_DEBUG "%s: TE newstate %x\n",
926                        __func__, dch->state);
927         switch (dch->state) {
928         case 0:
929                 l1_event(dch->l1, HW_RESET_IND);
930                 break;
931         case 3:
932                 l1_event(dch->l1, HW_DEACT_IND);
933                 break;
934         case 5:
935         case 8:
936                 l1_event(dch->l1, ANYSIGNAL);
937                 break;
938         case 6:
939                 l1_event(dch->l1, INFO2);
940                 break;
941         case 7:
942                 l1_event(dch->l1, INFO4_P8);
943                 break;
944         }
945 }
946 
947 /*
948  * handle L1 state changes NT
949  */
950 
951 static void
952 handle_nt_timer3(struct dchannel *dch) {
953         struct hfc_pci  *hc = dch->hw;
954 
955         test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
956         hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
957         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
958         hc->hw.nt_timer = 0;
959         test_and_set_bit(FLG_ACTIVE, &dch->Flags);
960         if (test_bit(HFC_CFG_MASTER, &hc->cfg))
961                 hc->hw.mst_m |= HFCPCI_MASTER;
962         Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
963         _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
964                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
965 }
966 
967 static void
968 ph_state_nt(struct dchannel *dch)
969 {
970         struct hfc_pci  *hc = dch->hw;
971 
972         if (dch->debug)
973                 printk(KERN_DEBUG "%s: NT newstate %x\n",
974                        __func__, dch->state);
975         switch (dch->state) {
976         case 2:
977                 if (hc->hw.nt_timer < 0) {
978                         hc->hw.nt_timer = 0;
979                         test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
980                         test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
981                         hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
982                         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
983                         /* Clear already pending ints */
984                         (void) Read_hfc(hc, HFCPCI_INT_S1);
985                         Write_hfc(hc, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE);
986                         udelay(10);
987                         Write_hfc(hc, HFCPCI_STATES, 4);
988                         dch->state = 4;
989                 } else if (hc->hw.nt_timer == 0) {
990                         hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
991                         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
992                         hc->hw.nt_timer = NT_T1_COUNT;
993                         hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
994                         hc->hw.ctmt |= HFCPCI_TIM3_125;
995                         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
996                                   HFCPCI_CLTIMER);
997                         test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
998                         test_and_set_bit(FLG_HFC_TIMER_T1, &dch->Flags);
999                         /* allow G2 -> G3 transition */
1000                         Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
1001                 } else {
1002                         Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
1003                 }
1004                 break;
1005         case 1:
1006                 hc->hw.nt_timer = 0;
1007                 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
1008                 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1009                 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1010                 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1011                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
1012                 hc->hw.mst_m &= ~HFCPCI_MASTER;
1013                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1014                 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
1015                 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
1016                             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
1017                 break;
1018         case 4:
1019                 hc->hw.nt_timer = 0;
1020                 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
1021                 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1022                 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1023                 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1024                 break;
1025         case 3:
1026                 if (!test_and_set_bit(FLG_HFC_TIMER_T3, &dch->Flags)) {
1027                         if (!test_and_clear_bit(FLG_L2_ACTIVATED,
1028                                                 &dch->Flags)) {
1029                                 handle_nt_timer3(dch);
1030                                 break;
1031                         }
1032                         test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1033                         hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
1034                         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1035                         hc->hw.nt_timer = NT_T3_COUNT;
1036                         hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
1037                         hc->hw.ctmt |= HFCPCI_TIM3_125;
1038                         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
1039                                   HFCPCI_CLTIMER);
1040                 }
1041                 break;
1042         }
1043 }
1044 
1045 static void
1046 ph_state(struct dchannel *dch)
1047 {
1048         struct hfc_pci  *hc = dch->hw;
1049 
1050         if (hc->hw.protocol == ISDN_P_NT_S0) {
1051                 if (test_bit(FLG_HFC_TIMER_T3, &dch->Flags) &&
1052                     hc->hw.nt_timer < 0)
1053                         handle_nt_timer3(dch);
1054                 else
1055                         ph_state_nt(dch);
1056         } else
1057                 ph_state_te(dch);
1058 }
1059 
1060 /*
1061  * Layer 1 callback function
1062  */
1063 static int
1064 hfc_l1callback(struct dchannel *dch, u_int cmd)
1065 {
1066         struct hfc_pci          *hc = dch->hw;
1067 
1068         switch (cmd) {
1069         case INFO3_P8:
1070         case INFO3_P10:
1071                 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1072                         hc->hw.mst_m |= HFCPCI_MASTER;
1073                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1074                 break;
1075         case HW_RESET_REQ:
1076                 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3);
1077                 /* HFC ST 3 */
1078                 udelay(6);
1079                 Write_hfc(hc, HFCPCI_STATES, 3);        /* HFC ST 2 */
1080                 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1081                         hc->hw.mst_m |= HFCPCI_MASTER;
1082                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1083                 Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1084                           HFCPCI_DO_ACTION);
1085                 l1_event(dch->l1, HW_POWERUP_IND);
1086                 break;
1087         case HW_DEACT_REQ:
1088                 hc->hw.mst_m &= ~HFCPCI_MASTER;
1089                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1090                 skb_queue_purge(&dch->squeue);
1091                 if (dch->tx_skb) {
1092                         dev_kfree_skb(dch->tx_skb);
1093                         dch->tx_skb = NULL;
1094                 }
1095                 dch->tx_idx = 0;
1096                 if (dch->rx_skb) {
1097                         dev_kfree_skb(dch->rx_skb);
1098                         dch->rx_skb = NULL;
1099                 }
1100                 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1101                 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1102                         del_timer(&dch->timer);
1103                 break;
1104         case HW_POWERUP_REQ:
1105                 Write_hfc(hc, HFCPCI_STATES, HFCPCI_DO_ACTION);
1106                 break;
1107         case PH_ACTIVATE_IND:
1108                 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
1109                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1110                             GFP_ATOMIC);
1111                 break;
1112         case PH_DEACTIVATE_IND:
1113                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
1114                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1115                             GFP_ATOMIC);
1116                 break;
1117         default:
1118                 if (dch->debug & DEBUG_HW)
1119                         printk(KERN_DEBUG "%s: unknown command %x\n",
1120                                __func__, cmd);
1121                 return -1;
1122         }
1123         return 0;
1124 }
1125 
1126 /*
1127  * Interrupt handler
1128  */
1129 static inline void
1130 tx_birq(struct bchannel *bch)
1131 {
1132         if (bch->tx_skb && bch->tx_idx < bch->tx_skb->len)
1133                 hfcpci_fill_fifo(bch);
1134         else {
1135                 if (bch->tx_skb)
1136                         dev_kfree_skb(bch->tx_skb);
1137                 if (get_next_bframe(bch))
1138                         hfcpci_fill_fifo(bch);
1139         }
1140 }
1141 
1142 static inline void
1143 tx_dirq(struct dchannel *dch)
1144 {
1145         if (dch->tx_skb && dch->tx_idx < dch->tx_skb->len)
1146                 hfcpci_fill_dfifo(dch->hw);
1147         else {
1148                 if (dch->tx_skb)
1149                         dev_kfree_skb(dch->tx_skb);
1150                 if (get_next_dframe(dch))
1151                         hfcpci_fill_dfifo(dch->hw);
1152         }
1153 }
1154 
1155 static irqreturn_t
1156 hfcpci_int(int intno, void *dev_id)
1157 {
1158         struct hfc_pci  *hc = dev_id;
1159         u_char          exval;
1160         struct bchannel *bch;
1161         u_char          val, stat;
1162 
1163         spin_lock(&hc->lock);
1164         if (!(hc->hw.int_m2 & 0x08)) {
1165                 spin_unlock(&hc->lock);
1166                 return IRQ_NONE; /* not initialised */
1167         }
1168         stat = Read_hfc(hc, HFCPCI_STATUS);
1169         if (HFCPCI_ANYINT & stat) {
1170                 val = Read_hfc(hc, HFCPCI_INT_S1);
1171                 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1172                         printk(KERN_DEBUG
1173                                "HFC-PCI: stat(%02x) s1(%02x)\n", stat, val);
1174         } else {
1175                 /* shared */
1176                 spin_unlock(&hc->lock);
1177                 return IRQ_NONE;
1178         }
1179         hc->irqcnt++;
1180 
1181         if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1182                 printk(KERN_DEBUG "HFC-PCI irq %x\n", val);
1183         val &= hc->hw.int_m1;
1184         if (val & 0x40) {       /* state machine irq */
1185                 exval = Read_hfc(hc, HFCPCI_STATES) & 0xf;
1186                 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1187                         printk(KERN_DEBUG "ph_state chg %d->%d\n",
1188                                hc->dch.state, exval);
1189                 hc->dch.state = exval;
1190                 schedule_event(&hc->dch, FLG_PHCHANGE);
1191                 val &= ~0x40;
1192         }
1193         if (val & 0x80) {       /* timer irq */
1194                 if (hc->hw.protocol == ISDN_P_NT_S0) {
1195                         if ((--hc->hw.nt_timer) < 0)
1196                                 schedule_event(&hc->dch, FLG_PHCHANGE);
1197                 }
1198                 val &= ~0x80;
1199                 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt | HFCPCI_CLTIMER);
1200         }
1201         if (val & 0x08) {       /* B1 rx */
1202                 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1203                 if (bch)
1204                         main_rec_hfcpci(bch);
1205                 else if (hc->dch.debug)
1206                         printk(KERN_DEBUG "hfcpci spurious 0x08 IRQ\n");
1207         }
1208         if (val & 0x10) {       /* B2 rx */
1209                 bch = Sel_BCS(hc, 2);
1210                 if (bch)
1211                         main_rec_hfcpci(bch);
1212                 else if (hc->dch.debug)
1213                         printk(KERN_DEBUG "hfcpci spurious 0x10 IRQ\n");
1214         }
1215         if (val & 0x01) {       /* B1 tx */
1216                 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1217                 if (bch)
1218                         tx_birq(bch);
1219                 else if (hc->dch.debug)
1220                         printk(KERN_DEBUG "hfcpci spurious 0x01 IRQ\n");
1221         }
1222         if (val & 0x02) {       /* B2 tx */
1223                 bch = Sel_BCS(hc, 2);
1224                 if (bch)
1225                         tx_birq(bch);
1226                 else if (hc->dch.debug)
1227                         printk(KERN_DEBUG "hfcpci spurious 0x02 IRQ\n");
1228         }
1229         if (val & 0x20)         /* D rx */
1230                 receive_dmsg(hc);
1231         if (val & 0x04) {       /* D tx */
1232                 if (test_and_clear_bit(FLG_BUSY_TIMER, &hc->dch.Flags))
1233                         del_timer(&hc->dch.timer);
1234                 tx_dirq(&hc->dch);
1235         }
1236         spin_unlock(&hc->lock);
1237         return IRQ_HANDLED;
1238 }
1239 
1240 /*
1241  * timer callback for D-chan busy resolution. Currently no function
1242  */
1243 static void
1244 hfcpci_dbusy_timer(struct hfc_pci *hc)
1245 {
1246 }
1247 
1248 /*
1249  * activate/deactivate hardware for selected channels and mode
1250  */
1251 static int
1252 mode_hfcpci(struct bchannel *bch, int bc, int protocol)
1253 {
1254         struct hfc_pci  *hc = bch->hw;
1255         int             fifo2;
1256         u_char          rx_slot = 0, tx_slot = 0, pcm_mode;
1257 
1258         if (bch->debug & DEBUG_HW_BCHANNEL)
1259                 printk(KERN_DEBUG
1260                        "HFCPCI bchannel protocol %x-->%x ch %x-->%x\n",
1261                        bch->state, protocol, bch->nr, bc);
1262 
1263         fifo2 = bc;
1264         pcm_mode = (bc >> 24) & 0xff;
1265         if (pcm_mode) { /* PCM SLOT USE */
1266                 if (!test_bit(HFC_CFG_PCM, &hc->cfg))
1267                         printk(KERN_WARNING
1268                                "%s: pcm channel id without HFC_CFG_PCM\n",
1269                                __func__);
1270                 rx_slot = (bc >> 8) & 0xff;
1271                 tx_slot = (bc >> 16) & 0xff;
1272                 bc = bc & 0xff;
1273         } else if (test_bit(HFC_CFG_PCM, &hc->cfg) && (protocol > ISDN_P_NONE))
1274                 printk(KERN_WARNING "%s: no pcm channel id but HFC_CFG_PCM\n",
1275                        __func__);
1276         if (hc->chanlimit > 1) {
1277                 hc->hw.bswapped = 0;    /* B1 and B2 normal mode */
1278                 hc->hw.sctrl_e &= ~0x80;
1279         } else {
1280                 if (bc & 2) {
1281                         if (protocol != ISDN_P_NONE) {
1282                                 hc->hw.bswapped = 1; /* B1 and B2 exchanged */
1283                                 hc->hw.sctrl_e |= 0x80;
1284                         } else {
1285                                 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1286                                 hc->hw.sctrl_e &= ~0x80;
1287                         }
1288                         fifo2 = 1;
1289                 } else {
1290                         hc->hw.bswapped = 0;    /* B1 and B2 normal mode */
1291                         hc->hw.sctrl_e &= ~0x80;
1292                 }
1293         }
1294         switch (protocol) {
1295         case (-1): /* used for init */
1296                 bch->state = -1;
1297                 bch->nr = bc;
1298         case (ISDN_P_NONE):
1299                 if (bch->state == ISDN_P_NONE)
1300                         return 0;
1301                 if (bc & 2) {
1302                         hc->hw.sctrl &= ~SCTRL_B2_ENA;
1303                         hc->hw.sctrl_r &= ~SCTRL_B2_ENA;
1304                 } else {
1305                         hc->hw.sctrl &= ~SCTRL_B1_ENA;
1306                         hc->hw.sctrl_r &= ~SCTRL_B1_ENA;
1307                 }
1308                 if (fifo2 & 2) {
1309                         hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B2;
1310                         hc->hw.int_m1 &= ~(HFCPCI_INTS_B2TRANS |
1311                                            HFCPCI_INTS_B2REC);
1312                 } else {
1313                         hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B1;
1314                         hc->hw.int_m1 &= ~(HFCPCI_INTS_B1TRANS |
1315                                            HFCPCI_INTS_B1REC);
1316                 }
1317 #ifdef REVERSE_BITORDER
1318                 if (bch->nr & 2)
1319                         hc->hw.cirm &= 0x7f;
1320                 else
1321                         hc->hw.cirm &= 0xbf;
1322 #endif
1323                 bch->state = ISDN_P_NONE;
1324                 bch->nr = bc;
1325                 test_and_clear_bit(FLG_HDLC, &bch->Flags);
1326                 test_and_clear_bit(FLG_TRANSPARENT, &bch->Flags);
1327                 break;
1328         case (ISDN_P_B_RAW):
1329                 bch->state = protocol;
1330                 bch->nr = bc;
1331                 hfcpci_clear_fifo_rx(hc, (fifo2 & 2) ? 1 : 0);
1332                 hfcpci_clear_fifo_tx(hc, (fifo2 & 2) ? 1 : 0);
1333                 if (bc & 2) {
1334                         hc->hw.sctrl |= SCTRL_B2_ENA;
1335                         hc->hw.sctrl_r |= SCTRL_B2_ENA;
1336 #ifdef REVERSE_BITORDER
1337                         hc->hw.cirm |= 0x80;
1338 #endif
1339                 } else {
1340                         hc->hw.sctrl |= SCTRL_B1_ENA;
1341                         hc->hw.sctrl_r |= SCTRL_B1_ENA;
1342 #ifdef REVERSE_BITORDER
1343                         hc->hw.cirm |= 0x40;
1344 #endif
1345                 }
1346                 if (fifo2 & 2) {
1347                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1348                         if (!tics)
1349                                 hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS |
1350                                                   HFCPCI_INTS_B2REC);
1351                         hc->hw.ctmt |= 2;
1352                         hc->hw.conn &= ~0x18;
1353                 } else {
1354                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1355                         if (!tics)
1356                                 hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS |
1357                                                   HFCPCI_INTS_B1REC);
1358                         hc->hw.ctmt |= 1;
1359                         hc->hw.conn &= ~0x03;
1360                 }
1361                 test_and_set_bit(FLG_TRANSPARENT, &bch->Flags);
1362                 break;
1363         case (ISDN_P_B_HDLC):
1364                 bch->state = protocol;
1365                 bch->nr = bc;
1366                 hfcpci_clear_fifo_rx(hc, (fifo2 & 2) ? 1 : 0);
1367                 hfcpci_clear_fifo_tx(hc, (fifo2 & 2) ? 1 : 0);
1368                 if (bc & 2) {
1369                         hc->hw.sctrl |= SCTRL_B2_ENA;
1370                         hc->hw.sctrl_r |= SCTRL_B2_ENA;
1371                 } else {
1372                         hc->hw.sctrl |= SCTRL_B1_ENA;
1373                         hc->hw.sctrl_r |= SCTRL_B1_ENA;
1374                 }
1375                 if (fifo2 & 2) {
1376                         hc->hw.last_bfifo_cnt[1] = 0;
1377                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1378                         hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS |
1379                                           HFCPCI_INTS_B2REC);
1380                         hc->hw.ctmt &= ~2;
1381                         hc->hw.conn &= ~0x18;
1382                 } else {
1383                         hc->hw.last_bfifo_cnt[0] = 0;
1384                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1385                         hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS |
1386                                           HFCPCI_INTS_B1REC);
1387                         hc->hw.ctmt &= ~1;
1388                         hc->hw.conn &= ~0x03;
1389                 }
1390                 test_and_set_bit(FLG_HDLC, &bch->Flags);
1391                 break;
1392         default:
1393                 printk(KERN_DEBUG "prot not known %x\n", protocol);
1394                 return -ENOPROTOOPT;
1395         }
1396         if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
1397                 if ((protocol == ISDN_P_NONE) ||
1398                     (protocol == -1)) { /* init case */
1399                         rx_slot = 0;
1400                         tx_slot = 0;
1401                 } else {
1402                         if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
1403                                 rx_slot |= 0xC0;
1404                                 tx_slot |= 0xC0;
1405                         } else {
1406                                 rx_slot |= 0x80;
1407                                 tx_slot |= 0x80;
1408                         }
1409                 }
1410                 if (bc & 2) {
1411                         hc->hw.conn &= 0xc7;
1412                         hc->hw.conn |= 0x08;
1413                         printk(KERN_DEBUG "%s: Write_hfc: B2_SSL 0x%x\n",
1414                                __func__, tx_slot);
1415                         printk(KERN_DEBUG "%s: Write_hfc: B2_RSL 0x%x\n",
1416                                __func__, rx_slot);
1417                         Write_hfc(hc, HFCPCI_B2_SSL, tx_slot);
1418                         Write_hfc(hc, HFCPCI_B2_RSL, rx_slot);
1419                 } else {
1420                         hc->hw.conn &= 0xf8;
1421                         hc->hw.conn |= 0x01;
1422                         printk(KERN_DEBUG "%s: Write_hfc: B1_SSL 0x%x\n",
1423                                __func__, tx_slot);
1424                         printk(KERN_DEBUG "%s: Write_hfc: B1_RSL 0x%x\n",
1425                                __func__, rx_slot);
1426                         Write_hfc(hc, HFCPCI_B1_SSL, tx_slot);
1427                         Write_hfc(hc, HFCPCI_B1_RSL, rx_slot);
1428                 }
1429         }
1430         Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
1431         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1432         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1433         Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
1434         Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1435         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1436         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1437 #ifdef REVERSE_BITORDER
1438         Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1439 #endif
1440         return 0;
1441 }
1442 
1443 static int
1444 set_hfcpci_rxtest(struct bchannel *bch, int protocol, int chan)
1445 {
1446         struct hfc_pci  *hc = bch->hw;
1447 
1448         if (bch->debug & DEBUG_HW_BCHANNEL)
1449                 printk(KERN_DEBUG
1450                        "HFCPCI bchannel test rx protocol %x-->%x ch %x-->%x\n",
1451                        bch->state, protocol, bch->nr, chan);
1452         if (bch->nr != chan) {
1453                 printk(KERN_DEBUG
1454                        "HFCPCI rxtest wrong channel parameter %x/%x\n",
1455                        bch->nr, chan);
1456                 return -EINVAL;
1457         }
1458         switch (protocol) {
1459         case (ISDN_P_B_RAW):
1460                 bch->state = protocol;
1461                 hfcpci_clear_fifo_rx(hc, (chan & 2) ? 1 : 0);
1462                 if (chan & 2) {
1463                         hc->hw.sctrl_r |= SCTRL_B2_ENA;
1464                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1465                         if (!tics)
1466                                 hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1467                         hc->hw.ctmt |= 2;
1468                         hc->hw.conn &= ~0x18;
1469 #ifdef REVERSE_BITORDER
1470                         hc->hw.cirm |= 0x80;
1471 #endif
1472                 } else {
1473                         hc->hw.sctrl_r |= SCTRL_B1_ENA;
1474                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1475                         if (!tics)
1476                                 hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1477                         hc->hw.ctmt |= 1;
1478                         hc->hw.conn &= ~0x03;
1479 #ifdef REVERSE_BITORDER
1480                         hc->hw.cirm |= 0x40;
1481 #endif
1482                 }
1483                 break;
1484         case (ISDN_P_B_HDLC):
1485                 bch->state = protocol;
1486                 hfcpci_clear_fifo_rx(hc, (chan & 2) ? 1 : 0);
1487                 if (chan & 2) {
1488                         hc->hw.sctrl_r |= SCTRL_B2_ENA;
1489                         hc->hw.last_bfifo_cnt[1] = 0;
1490                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1491                         hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1492                         hc->hw.ctmt &= ~2;
1493                         hc->hw.conn &= ~0x18;
1494                 } else {
1495                         hc->hw.sctrl_r |= SCTRL_B1_ENA;
1496                         hc->hw.last_bfifo_cnt[0] = 0;
1497                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1498                         hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1499                         hc->hw.ctmt &= ~1;
1500                         hc->hw.conn &= ~0x03;
1501                 }
1502                 break;
1503         default:
1504                 printk(KERN_DEBUG "prot not known %x\n", protocol);
1505                 return -ENOPROTOOPT;
1506         }
1507         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1508         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1509         Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1510         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1511         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1512 #ifdef REVERSE_BITORDER
1513         Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1514 #endif
1515         return 0;
1516 }
1517 
1518 static void
1519 deactivate_bchannel(struct bchannel *bch)
1520 {
1521         struct hfc_pci  *hc = bch->hw;
1522         u_long          flags;
1523 
1524         spin_lock_irqsave(&hc->lock, flags);
1525         mISDN_clear_bchannel(bch);
1526         mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1527         spin_unlock_irqrestore(&hc->lock, flags);
1528 }
1529 
1530 /*
1531  * Layer 1 B-channel hardware access
1532  */
1533 static int
1534 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
1535 {
1536         return mISDN_ctrl_bchannel(bch, cq);
1537 }
1538 static int
1539 hfc_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1540 {
1541         struct bchannel *bch = container_of(ch, struct bchannel, ch);
1542         struct hfc_pci  *hc = bch->hw;
1543         int             ret = -EINVAL;
1544         u_long          flags;
1545 
1546         if (bch->debug & DEBUG_HW)
1547                 printk(KERN_DEBUG "%s: cmd:%x %p\n", __func__, cmd, arg);
1548         switch (cmd) {
1549         case HW_TESTRX_RAW:
1550                 spin_lock_irqsave(&hc->lock, flags);
1551                 ret = set_hfcpci_rxtest(bch, ISDN_P_B_RAW, (int)(long)arg);
1552                 spin_unlock_irqrestore(&hc->lock, flags);
1553                 break;
1554         case HW_TESTRX_HDLC:
1555                 spin_lock_irqsave(&hc->lock, flags);
1556                 ret = set_hfcpci_rxtest(bch, ISDN_P_B_HDLC, (int)(long)arg);
1557                 spin_unlock_irqrestore(&hc->lock, flags);
1558                 break;
1559         case HW_TESTRX_OFF:
1560                 spin_lock_irqsave(&hc->lock, flags);
1561                 mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1562                 spin_unlock_irqrestore(&hc->lock, flags);
1563                 ret = 0;
1564                 break;
1565         case CLOSE_CHANNEL:
1566                 test_and_clear_bit(FLG_OPEN, &bch->Flags);
1567                 deactivate_bchannel(bch);
1568                 ch->protocol = ISDN_P_NONE;
1569                 ch->peer = NULL;
1570                 module_put(THIS_MODULE);
1571                 ret = 0;
1572                 break;
1573         case CONTROL_CHANNEL:
1574                 ret = channel_bctrl(bch, arg);
1575                 break;
1576         default:
1577                 printk(KERN_WARNING "%s: unknown prim(%x)\n",
1578                        __func__, cmd);
1579         }
1580         return ret;
1581 }
1582 
1583 /*
1584  * Layer2 -> Layer 1 Dchannel data
1585  */
1586 static int
1587 hfcpci_l2l1D(struct mISDNchannel *ch, struct sk_buff *skb)
1588 {
1589         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
1590         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
1591         struct hfc_pci          *hc = dch->hw;
1592         int                     ret = -EINVAL;
1593         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
1594         unsigned int            id;
1595         u_long                  flags;
1596 
1597         switch (hh->prim) {
1598         case PH_DATA_REQ:
1599                 spin_lock_irqsave(&hc->lock, flags);
1600                 ret = dchannel_senddata(dch, skb);
1601                 if (ret > 0) { /* direct TX */
1602                         id = hh->id; /* skb can be freed */
1603                         hfcpci_fill_dfifo(dch->hw);
1604                         ret = 0;
1605                         spin_unlock_irqrestore(&hc->lock, flags);
1606                         queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1607                 } else
1608                         spin_unlock_irqrestore(&hc->lock, flags);
1609                 return ret;
1610         case PH_ACTIVATE_REQ:
1611                 spin_lock_irqsave(&hc->lock, flags);
1612                 if (hc->hw.protocol == ISDN_P_NT_S0) {
1613                         ret = 0;
1614                         if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1615                                 hc->hw.mst_m |= HFCPCI_MASTER;
1616                         Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1617                         if (test_bit(FLG_ACTIVE, &dch->Flags)) {
1618                                 spin_unlock_irqrestore(&hc->lock, flags);
1619                                 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
1620                                             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
1621                                 break;
1622                         }
1623                         test_and_set_bit(FLG_L2_ACTIVATED, &dch->Flags);
1624                         Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1625                                   HFCPCI_DO_ACTION | 1);
1626                 } else
1627                         ret = l1_event(dch->l1, hh->prim);
1628                 spin_unlock_irqrestore(&hc->lock, flags);
1629                 break;
1630         case PH_DEACTIVATE_REQ:
1631                 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
1632                 spin_lock_irqsave(&hc->lock, flags);
1633                 if (hc->hw.protocol == ISDN_P_NT_S0) {
1634                         /* prepare deactivation */
1635                         Write_hfc(hc, HFCPCI_STATES, 0x40);
1636                         skb_queue_purge(&dch->squeue);
1637                         if (dch->tx_skb) {
1638                                 dev_kfree_skb(dch->tx_skb);
1639                                 dch->tx_skb = NULL;
1640                         }
1641                         dch->tx_idx = 0;
1642                         if (dch->rx_skb) {
1643                                 dev_kfree_skb(dch->rx_skb);
1644                                 dch->rx_skb = NULL;
1645                         }
1646                         test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1647                         if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1648                                 del_timer(&dch->timer);
1649 #ifdef FIXME
1650                         if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
1651                                 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
1652 #endif
1653                         hc->hw.mst_m &= ~HFCPCI_MASTER;
1654                         Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1655                         ret = 0;
1656                 } else {
1657                         ret = l1_event(dch->l1, hh->prim);
1658                 }
1659                 spin_unlock_irqrestore(&hc->lock, flags);
1660                 break;
1661         }
1662         if (!ret)
1663                 dev_kfree_skb(skb);
1664         return ret;
1665 }
1666 
1667 /*
1668  * Layer2 -> Layer 1 Bchannel data
1669  */
1670 static int
1671 hfcpci_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb)
1672 {
1673         struct bchannel         *bch = container_of(ch, struct bchannel, ch);
1674         struct hfc_pci          *hc = bch->hw;
1675         int                     ret = -EINVAL;
1676         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
1677         unsigned long           flags;
1678 
1679         switch (hh->prim) {
1680         case PH_DATA_REQ:
1681                 spin_lock_irqsave(&hc->lock, flags);
1682                 ret = bchannel_senddata(bch, skb);
1683                 if (ret > 0) { /* direct TX */
1684                         hfcpci_fill_fifo(bch);
1685                         ret = 0;
1686                 }
1687                 spin_unlock_irqrestore(&hc->lock, flags);
1688                 return ret;
1689         case PH_ACTIVATE_REQ:
1690                 spin_lock_irqsave(&hc->lock, flags);
1691                 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
1692                         ret = mode_hfcpci(bch, bch->nr, ch->protocol);
1693                 else
1694                         ret = 0;
1695                 spin_unlock_irqrestore(&hc->lock, flags);
1696                 if (!ret)
1697                         _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
1698                                     NULL, GFP_KERNEL);
1699                 break;
1700         case PH_DEACTIVATE_REQ:
1701                 deactivate_bchannel(bch);
1702                 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
1703                             NULL, GFP_KERNEL);
1704                 ret = 0;
1705                 break;
1706         }
1707         if (!ret)
1708                 dev_kfree_skb(skb);
1709         return ret;
1710 }
1711 
1712 /*
1713  * called for card init message
1714  */
1715 
1716 static void
1717 inithfcpci(struct hfc_pci *hc)
1718 {
1719         printk(KERN_DEBUG "inithfcpci: entered\n");
1720         hc->dch.timer.function = (void *) hfcpci_dbusy_timer;
1721         hc->dch.timer.data = (long) &hc->dch;
1722         init_timer(&hc->dch.timer);
1723         hc->chanlimit = 2;
1724         mode_hfcpci(&hc->bch[0], 1, -1);
1725         mode_hfcpci(&hc->bch[1], 2, -1);
1726 }
1727 
1728 
1729 static int
1730 init_card(struct hfc_pci *hc)
1731 {
1732         int     cnt = 3;
1733         u_long  flags;
1734 
1735         printk(KERN_DEBUG "init_card: entered\n");
1736 
1737 
1738         spin_lock_irqsave(&hc->lock, flags);
1739         disable_hwirq(hc);
1740         spin_unlock_irqrestore(&hc->lock, flags);
1741         if (request_irq(hc->irq, hfcpci_int, IRQF_SHARED, "HFC PCI", hc)) {
1742                 printk(KERN_WARNING
1743                        "mISDN: couldn't get interrupt %d\n", hc->irq);
1744                 return -EIO;
1745         }
1746         spin_lock_irqsave(&hc->lock, flags);
1747         reset_hfcpci(hc);
1748         while (cnt) {
1749                 inithfcpci(hc);
1750                 /*
1751                  * Finally enable IRQ output
1752                  * this is only allowed, if an IRQ routine is already
1753                  * established for this HFC, so don't do that earlier
1754                  */
1755                 enable_hwirq(hc);
1756                 spin_unlock_irqrestore(&hc->lock, flags);
1757                 /* Timeout 80ms */
1758                 current->state = TASK_UNINTERRUPTIBLE;
1759                 schedule_timeout((80 * HZ) / 1000);
1760                 printk(KERN_INFO "HFC PCI: IRQ %d count %d\n",
1761                        hc->irq, hc->irqcnt);
1762                 /* now switch timer interrupt off */
1763                 spin_lock_irqsave(&hc->lock, flags);
1764                 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1765                 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1766                 /* reinit mode reg */
1767                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1768                 if (!hc->irqcnt) {
1769                         printk(KERN_WARNING
1770                                "HFC PCI: IRQ(%d) getting no interrupts "
1771                                "during init %d\n", hc->irq, 4 - cnt);
1772                         if (cnt == 1)
1773                                 break;
1774                         else {
1775                                 reset_hfcpci(hc);
1776                                 cnt--;
1777                         }
1778                 } else {
1779                         spin_unlock_irqrestore(&hc->lock, flags);
1780                         hc->initdone = 1;
1781                         return 0;
1782                 }
1783         }
1784         disable_hwirq(hc);
1785         spin_unlock_irqrestore(&hc->lock, flags);
1786         free_irq(hc->irq, hc);
1787         return -EIO;
1788 }
1789 
1790 static int
1791 channel_ctrl(struct hfc_pci *hc, struct mISDN_ctrl_req *cq)
1792 {
1793         int     ret = 0;
1794         u_char  slot;
1795 
1796         switch (cq->op) {
1797         case MISDN_CTRL_GETOP:
1798                 cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_CONNECT |
1799                          MISDN_CTRL_DISCONNECT | MISDN_CTRL_L1_TIMER3;
1800                 break;
1801         case MISDN_CTRL_LOOP:
1802                 /* channel 0 disabled loop */
1803                 if (cq->channel < 0 || cq->channel > 2) {
1804                         ret = -EINVAL;
1805                         break;
1806                 }
1807                 if (cq->channel & 1) {
1808                         if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1809                                 slot = 0xC0;
1810                         else
1811                                 slot = 0x80;
1812                         printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1813                                __func__, slot);
1814                         Write_hfc(hc, HFCPCI_B1_SSL, slot);
1815                         Write_hfc(hc, HFCPCI_B1_RSL, slot);
1816                         hc->hw.conn = (hc->hw.conn & ~7) | 6;
1817                         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1818                 }
1819                 if (cq->channel & 2) {
1820                         if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1821                                 slot = 0xC1;
1822                         else
1823                                 slot = 0x81;
1824                         printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1825                                __func__, slot);
1826                         Write_hfc(hc, HFCPCI_B2_SSL, slot);
1827                         Write_hfc(hc, HFCPCI_B2_RSL, slot);
1828                         hc->hw.conn = (hc->hw.conn & ~0x38) | 0x30;
1829                         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1830                 }
1831                 if (cq->channel & 3)
1832                         hc->hw.trm |= 0x80;     /* enable IOM-loop */
1833                 else {
1834                         hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1835                         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1836                         hc->hw.trm &= 0x7f;     /* disable IOM-loop */
1837                 }
1838                 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1839                 break;
1840         case MISDN_CTRL_CONNECT:
1841                 if (cq->channel == cq->p1) {
1842                         ret = -EINVAL;
1843                         break;
1844                 }
1845                 if (cq->channel < 1 || cq->channel > 2 ||
1846                     cq->p1 < 1 || cq->p1 > 2) {
1847                         ret = -EINVAL;
1848                         break;
1849                 }
1850                 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1851                         slot = 0xC0;
1852                 else
1853                         slot = 0x80;
1854                 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1855                        __func__, slot);
1856                 Write_hfc(hc, HFCPCI_B1_SSL, slot);
1857                 Write_hfc(hc, HFCPCI_B2_RSL, slot);
1858                 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1859                         slot = 0xC1;
1860                 else
1861                         slot = 0x81;
1862                 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1863                        __func__, slot);
1864                 Write_hfc(hc, HFCPCI_B2_SSL, slot);
1865                 Write_hfc(hc, HFCPCI_B1_RSL, slot);
1866                 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x36;
1867                 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1868                 hc->hw.trm |= 0x80;
1869                 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1870                 break;
1871         case MISDN_CTRL_DISCONNECT:
1872                 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1873                 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1874                 hc->hw.trm &= 0x7f;     /* disable IOM-loop */
1875                 break;
1876         case MISDN_CTRL_L1_TIMER3:
1877                 ret = l1_event(hc->dch.l1, HW_TIMER3_VALUE | (cq->p1 & 0xff));
1878                 break;
1879         default:
1880                 printk(KERN_WARNING "%s: unknown Op %x\n",
1881                        __func__, cq->op);
1882                 ret = -EINVAL;
1883                 break;
1884         }
1885         return ret;
1886 }
1887 
1888 static int
1889 open_dchannel(struct hfc_pci *hc, struct mISDNchannel *ch,
1890               struct channel_req *rq)
1891 {
1892         int err = 0;
1893 
1894         if (debug & DEBUG_HW_OPEN)
1895                 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
1896                        hc->dch.dev.id, __builtin_return_address(0));
1897         if (rq->protocol == ISDN_P_NONE)
1898                 return -EINVAL;
1899         if (rq->adr.channel == 1) {
1900                 /* TODO: E-Channel */
1901                 return -EINVAL;
1902         }
1903         if (!hc->initdone) {
1904                 if (rq->protocol == ISDN_P_TE_S0) {
1905                         err = create_l1(&hc->dch, hfc_l1callback);
1906                         if (err)
1907                                 return err;
1908                 }
1909                 hc->hw.protocol = rq->protocol;
1910                 ch->protocol = rq->protocol;
1911                 err = init_card(hc);
1912                 if (err)
1913                         return err;
1914         } else {
1915                 if (rq->protocol != ch->protocol) {
1916                         if (hc->hw.protocol == ISDN_P_TE_S0)
1917                                 l1_event(hc->dch.l1, CLOSE_CHANNEL);
1918                         if (rq->protocol == ISDN_P_TE_S0) {
1919                                 err = create_l1(&hc->dch, hfc_l1callback);
1920                                 if (err)
1921                                         return err;
1922                         }
1923                         hc->hw.protocol = rq->protocol;
1924                         ch->protocol = rq->protocol;
1925                         hfcpci_setmode(hc);
1926                 }
1927         }
1928 
1929         if (((ch->protocol == ISDN_P_NT_S0) && (hc->dch.state == 3)) ||
1930             ((ch->protocol == ISDN_P_TE_S0) && (hc->dch.state == 7))) {
1931                 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY,
1932                             0, NULL, GFP_KERNEL);
1933         }
1934         rq->ch = ch;
1935         if (!try_module_get(THIS_MODULE))
1936                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1937         return 0;
1938 }
1939 
1940 static int
1941 open_bchannel(struct hfc_pci *hc, struct channel_req *rq)
1942 {
1943         struct bchannel         *bch;
1944 
1945         if (rq->adr.channel == 0 || rq->adr.channel > 2)
1946                 return -EINVAL;
1947         if (rq->protocol == ISDN_P_NONE)
1948                 return -EINVAL;
1949         bch = &hc->bch[rq->adr.channel - 1];
1950         if (test_and_set_bit(FLG_OPEN, &bch->Flags))
1951                 return -EBUSY; /* b-channel can be only open once */
1952         bch->ch.protocol = rq->protocol;
1953         rq->ch = &bch->ch; /* TODO: E-channel */
1954         if (!try_module_get(THIS_MODULE))
1955                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1956         return 0;
1957 }
1958 
1959 /*
1960  * device control function
1961  */
1962 static int
1963 hfc_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1964 {
1965         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
1966         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
1967         struct hfc_pci          *hc = dch->hw;
1968         struct channel_req      *rq;
1969         int                     err = 0;
1970 
1971         if (dch->debug & DEBUG_HW)
1972                 printk(KERN_DEBUG "%s: cmd:%x %p\n",
1973                        __func__, cmd, arg);
1974         switch (cmd) {
1975         case OPEN_CHANNEL:
1976                 rq = arg;
1977                 if ((rq->protocol == ISDN_P_TE_S0) ||
1978                     (rq->protocol == ISDN_P_NT_S0))
1979                         err = open_dchannel(hc, ch, rq);
1980                 else
1981                         err = open_bchannel(hc, rq);
1982                 break;
1983         case CLOSE_CHANNEL:
1984                 if (debug & DEBUG_HW_OPEN)
1985                         printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
1986                                __func__, hc->dch.dev.id,
1987                                __builtin_return_address(0));
1988                 module_put(THIS_MODULE);
1989                 break;
1990         case CONTROL_CHANNEL:
1991                 err = channel_ctrl(hc, arg);
1992                 break;
1993         default:
1994                 if (dch->debug & DEBUG_HW)
1995                         printk(KERN_DEBUG "%s: unknown command %x\n",
1996                                __func__, cmd);
1997                 return -EINVAL;
1998         }
1999         return err;
2000 }
2001 
2002 static int
2003 setup_hw(struct hfc_pci *hc)
2004 {
2005         void    *buffer;
2006 
2007         printk(KERN_INFO "mISDN: HFC-PCI driver %s\n", hfcpci_revision);
2008         hc->hw.cirm = 0;
2009         hc->dch.state = 0;
2010         pci_set_master(hc->pdev);
2011         if (!hc->irq) {
2012                 printk(KERN_WARNING "HFC-PCI: No IRQ for PCI card found\n");
2013                 return 1;
2014         }
2015         hc->hw.pci_io =
2016                 (char __iomem *)(unsigned long)hc->pdev->resource[1].start;
2017 
2018         if (!hc->hw.pci_io) {
2019                 printk(KERN_WARNING "HFC-PCI: No IO-Mem for PCI card found\n");
2020                 return 1;
2021         }
2022         /* Allocate memory for FIFOS */
2023         /* the memory needs to be on a 32k boundary within the first 4G */
2024         pci_set_dma_mask(hc->pdev, 0xFFFF8000);
2025         buffer = pci_alloc_consistent(hc->pdev, 0x8000, &hc->hw.dmahandle);
2026         /* We silently assume the address is okay if nonzero */
2027         if (!buffer) {
2028                 printk(KERN_WARNING
2029                        "HFC-PCI: Error allocating memory for FIFO!\n");
2030                 return 1;
2031         }
2032         hc->hw.fifos = buffer;
2033         pci_write_config_dword(hc->pdev, 0x80, hc->hw.dmahandle);
2034         hc->hw.pci_io = ioremap((ulong) hc->hw.pci_io, 256);
2035         printk(KERN_INFO
2036                "HFC-PCI: defined at mem %#lx fifo %#lx(%#lx) IRQ %d HZ %d\n",
2037                (u_long) hc->hw.pci_io, (u_long) hc->hw.fifos,
2038                (u_long) hc->hw.dmahandle, hc->irq, HZ);
2039         /* enable memory mapped ports, disable busmaster */
2040         pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
2041         hc->hw.int_m2 = 0;
2042         disable_hwirq(hc);
2043         hc->hw.int_m1 = 0;
2044         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
2045         /* At this point the needed PCI config is done */
2046         /* fifos are still not enabled */
2047         hc->hw.timer.function = (void *) hfcpci_Timer;
2048         hc->hw.timer.data = (long) hc;
2049         init_timer(&hc->hw.timer);
2050         /* default PCM master */
2051         test_and_set_bit(HFC_CFG_MASTER, &hc->cfg);
2052         return 0;
2053 }
2054 
2055 static void
2056 release_card(struct hfc_pci *hc) {
2057         u_long  flags;
2058 
2059         spin_lock_irqsave(&hc->lock, flags);
2060         hc->hw.int_m2 = 0; /* interrupt output off ! */
2061         disable_hwirq(hc);
2062         mode_hfcpci(&hc->bch[0], 1, ISDN_P_NONE);
2063         mode_hfcpci(&hc->bch[1], 2, ISDN_P_NONE);
2064         if (hc->dch.timer.function != NULL) {
2065                 del_timer(&hc->dch.timer);
2066                 hc->dch.timer.function = NULL;
2067         }
2068         spin_unlock_irqrestore(&hc->lock, flags);
2069         if (hc->hw.protocol == ISDN_P_TE_S0)
2070                 l1_event(hc->dch.l1, CLOSE_CHANNEL);
2071         if (hc->initdone)
2072                 free_irq(hc->irq, hc);
2073         release_io_hfcpci(hc); /* must release after free_irq! */
2074         mISDN_unregister_device(&hc->dch.dev);
2075         mISDN_freebchannel(&hc->bch[1]);
2076         mISDN_freebchannel(&hc->bch[0]);
2077         mISDN_freedchannel(&hc->dch);
2078         pci_set_drvdata(hc->pdev, NULL);
2079         kfree(hc);
2080 }
2081 
2082 static int
2083 setup_card(struct hfc_pci *card)
2084 {
2085         int             err = -EINVAL;
2086         u_int           i;
2087         char            name[MISDN_MAX_IDLEN];
2088 
2089         card->dch.debug = debug;
2090         spin_lock_init(&card->lock);
2091         mISDN_initdchannel(&card->dch, MAX_DFRAME_LEN_L1, ph_state);
2092         card->dch.hw = card;
2093         card->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
2094         card->dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
2095                 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
2096         card->dch.dev.D.send = hfcpci_l2l1D;
2097         card->dch.dev.D.ctrl = hfc_dctrl;
2098         card->dch.dev.nrbchan = 2;
2099         for (i = 0; i < 2; i++) {
2100                 card->bch[i].nr = i + 1;
2101                 set_channelmap(i + 1, card->dch.dev.channelmap);
2102                 card->bch[i].debug = debug;
2103                 mISDN_initbchannel(&card->bch[i], MAX_DATA_MEM, poll >> 1);
2104                 card->bch[i].hw = card;
2105                 card->bch[i].ch.send = hfcpci_l2l1B;
2106                 card->bch[i].ch.ctrl = hfc_bctrl;
2107                 card->bch[i].ch.nr = i + 1;
2108                 list_add(&card->bch[i].ch.list, &card->dch.dev.bchannels);
2109         }
2110         err = setup_hw(card);
2111         if (err)
2112                 goto error;
2113         snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-pci.%d", HFC_cnt + 1);
2114         err = mISDN_register_device(&card->dch.dev, &card->pdev->dev, name);
2115         if (err)
2116                 goto error;
2117         HFC_cnt++;
2118         printk(KERN_INFO "HFC %d cards installed\n", HFC_cnt);
2119         return 0;
2120 error:
2121         mISDN_freebchannel(&card->bch[1]);
2122         mISDN_freebchannel(&card->bch[0]);
2123         mISDN_freedchannel(&card->dch);
2124         kfree(card);
2125         return err;
2126 }
2127 
2128 /* private data in the PCI devices list */
2129 struct _hfc_map {
2130         u_int   subtype;
2131         u_int   flag;
2132         char    *name;
2133 };
2134 
2135 static const struct _hfc_map hfc_map[] =
2136 {
2137         {HFC_CCD_2BD0, 0, "CCD/Billion/Asuscom 2BD0"},
2138         {HFC_CCD_B000, 0, "Billion B000"},
2139         {HFC_CCD_B006, 0, "Billion B006"},
2140         {HFC_CCD_B007, 0, "Billion B007"},
2141         {HFC_CCD_B008, 0, "Billion B008"},
2142         {HFC_CCD_B009, 0, "Billion B009"},
2143         {HFC_CCD_B00A, 0, "Billion B00A"},
2144         {HFC_CCD_B00B, 0, "Billion B00B"},
2145         {HFC_CCD_B00C, 0, "Billion B00C"},
2146         {HFC_CCD_B100, 0, "Seyeon B100"},
2147         {HFC_CCD_B700, 0, "Primux II S0 B700"},
2148         {HFC_CCD_B701, 0, "Primux II S0 NT B701"},
2149         {HFC_ABOCOM_2BD1, 0, "Abocom/Magitek 2BD1"},
2150         {HFC_ASUS_0675, 0, "Asuscom/Askey 675"},
2151         {HFC_BERKOM_TCONCEPT, 0, "German telekom T-Concept"},
2152         {HFC_BERKOM_A1T, 0, "German telekom A1T"},
2153         {HFC_ANIGMA_MC145575, 0, "Motorola MC145575"},
2154         {HFC_ZOLTRIX_2BD0, 0, "Zoltrix 2BD0"},
2155         {HFC_DIGI_DF_M_IOM2_E, 0,
2156          "Digi International DataFire Micro V IOM2 (Europe)"},
2157         {HFC_DIGI_DF_M_E, 0,
2158          "Digi International DataFire Micro V (Europe)"},
2159         {HFC_DIGI_DF_M_IOM2_A, 0,
2160          "Digi International DataFire Micro V IOM2 (North America)"},
2161         {HFC_DIGI_DF_M_A, 0,
2162          "Digi International DataFire Micro V (North America)"},
2163         {HFC_SITECOM_DC105V2, 0, "Sitecom Connectivity DC-105 ISDN TA"},
2164         {},
2165 };
2166 
2167 static struct pci_device_id hfc_ids[] =
2168 {
2169         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_2BD0),
2170           (unsigned long) &hfc_map[0] },
2171         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B000),
2172           (unsigned long) &hfc_map[1] },
2173         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B006),
2174           (unsigned long) &hfc_map[2] },
2175         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B007),
2176           (unsigned long) &hfc_map[3] },
2177         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B008),
2178           (unsigned long) &hfc_map[4] },
2179         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B009),
2180           (unsigned long) &hfc_map[5] },
2181         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00A),
2182           (unsigned long) &hfc_map[6] },
2183         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00B),
2184           (unsigned long) &hfc_map[7] },
2185         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00C),
2186           (unsigned long) &hfc_map[8] },
2187         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B100),
2188           (unsigned long) &hfc_map[9] },
2189         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B700),
2190           (unsigned long) &hfc_map[10] },
2191         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B701),
2192           (unsigned long) &hfc_map[11] },
2193         { PCI_VDEVICE(ABOCOM, PCI_DEVICE_ID_ABOCOM_2BD1),
2194           (unsigned long) &hfc_map[12] },
2195         { PCI_VDEVICE(ASUSTEK, PCI_DEVICE_ID_ASUSTEK_0675),
2196           (unsigned long) &hfc_map[13] },
2197         { PCI_VDEVICE(BERKOM, PCI_DEVICE_ID_BERKOM_T_CONCEPT),
2198           (unsigned long) &hfc_map[14] },
2199         { PCI_VDEVICE(BERKOM, PCI_DEVICE_ID_BERKOM_A1T),
2200           (unsigned long) &hfc_map[15] },
2201         { PCI_VDEVICE(ANIGMA, PCI_DEVICE_ID_ANIGMA_MC145575),
2202           (unsigned long) &hfc_map[16] },
2203         { PCI_VDEVICE(ZOLTRIX, PCI_DEVICE_ID_ZOLTRIX_2BD0),
2204           (unsigned long) &hfc_map[17] },
2205         { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_E),
2206           (unsigned long) &hfc_map[18] },
2207         { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_E),
2208           (unsigned long) &hfc_map[19] },
2209         { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_A),
2210           (unsigned long) &hfc_map[20] },
2211         { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_A),
2212           (unsigned long) &hfc_map[21] },
2213         { PCI_VDEVICE(SITECOM, PCI_DEVICE_ID_SITECOM_DC105V2),
2214           (unsigned long) &hfc_map[22] },
2215         {},
2216 };
2217 
2218 static int
2219 hfc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2220 {
2221         int             err = -ENOMEM;
2222         struct hfc_pci  *card;
2223         struct _hfc_map *m = (struct _hfc_map *)ent->driver_data;
2224 
2225         card = kzalloc(sizeof(struct hfc_pci), GFP_ATOMIC);
2226         if (!card) {
2227                 printk(KERN_ERR "No kmem for HFC card\n");
2228                 return err;
2229         }
2230         card->pdev = pdev;
2231         card->subtype = m->subtype;
2232         err = pci_enable_device(pdev);
2233         if (err) {
2234                 kfree(card);
2235                 return err;
2236         }
2237 
2238         printk(KERN_INFO "mISDN_hfcpci: found adapter %s at %s\n",
2239                m->name, pci_name(pdev));
2240 
2241         card->irq = pdev->irq;
2242         pci_set_drvdata(pdev, card);
2243         err = setup_card(card);
2244         if (err)
2245                 pci_set_drvdata(pdev, NULL);
2246         return err;
2247 }
2248 
2249 static void
2250 hfc_remove_pci(struct pci_dev *pdev)
2251 {
2252         struct hfc_pci  *card = pci_get_drvdata(pdev);
2253 
2254         if (card)
2255                 release_card(card);
2256         else
2257                 if (debug)
2258                         printk(KERN_DEBUG "%s: drvdata already removed\n",
2259                                __func__);
2260 }
2261 
2262 
2263 static struct pci_driver hfc_driver = {
2264         .name = "hfcpci",
2265         .probe = hfc_probe,
2266         .remove = hfc_remove_pci,
2267         .id_table = hfc_ids,
2268 };
2269 
2270 static int
2271 _hfcpci_softirq(struct device *dev, void *arg)
2272 {
2273         struct hfc_pci  *hc = dev_get_drvdata(dev);
2274         struct bchannel *bch;
2275         if (hc == NULL)
2276                 return 0;
2277 
2278         if (hc->hw.int_m2 & HFCPCI_IRQ_ENABLE) {
2279                 spin_lock(&hc->lock);
2280                 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
2281                 if (bch && bch->state == ISDN_P_B_RAW) { /* B1 rx&tx */
2282                         main_rec_hfcpci(bch);
2283                         tx_birq(bch);
2284                 }
2285                 bch = Sel_BCS(hc, hc->hw.bswapped ? 1 : 2);
2286                 if (bch && bch->state == ISDN_P_B_RAW) { /* B2 rx&tx */
2287                         main_rec_hfcpci(bch);
2288                         tx_birq(bch);
2289                 }
2290                 spin_unlock(&hc->lock);
2291         }
2292         return 0;
2293 }
2294 
2295 static void
2296 hfcpci_softirq(void *arg)
2297 {
2298         WARN_ON_ONCE(driver_for_each_device(&hfc_driver.driver, NULL, arg,
2299                                       _hfcpci_softirq) != 0);
2300 
2301         /* if next event would be in the past ... */
2302         if ((s32)(hfc_jiffies + tics - jiffies) <= 0)
2303                 hfc_jiffies = jiffies + 1;
2304         else
2305                 hfc_jiffies += tics;
2306         hfc_tl.expires = hfc_jiffies;
2307         add_timer(&hfc_tl);
2308 }
2309 
2310 static int __init
2311 HFC_init(void)
2312 {
2313         int             err;
2314 
2315         if (!poll)
2316                 poll = HFCPCI_BTRANS_THRESHOLD;
2317 
2318         if (poll != HFCPCI_BTRANS_THRESHOLD) {
2319                 tics = (poll * HZ) / 8000;
2320                 if (tics < 1)
2321                         tics = 1;
2322                 poll = (tics * 8000) / HZ;
2323                 if (poll > 256 || poll < 8) {
2324                         printk(KERN_ERR "%s: Wrong poll value %d not in range "
2325                                "of 8..256.\n", __func__, poll);
2326                         err = -EINVAL;
2327                         return err;
2328                 }
2329         }
2330         if (poll != HFCPCI_BTRANS_THRESHOLD) {
2331                 printk(KERN_INFO "%s: Using alternative poll value of %d\n",
2332                        __func__, poll);
2333                 hfc_tl.function = (void *)hfcpci_softirq;
2334                 hfc_tl.data = 0;
2335                 init_timer(&hfc_tl);
2336                 hfc_tl.expires = jiffies + tics;
2337                 hfc_jiffies = hfc_tl.expires;
2338                 add_timer(&hfc_tl);
2339         } else
2340                 tics = 0; /* indicate the use of controller's timer */
2341 
2342         err = pci_register_driver(&hfc_driver);
2343         if (err) {
2344                 if (timer_pending(&hfc_tl))
2345                         del_timer(&hfc_tl);
2346         }
2347 
2348         return err;
2349 }
2350 
2351 static void __exit
2352 HFC_cleanup(void)
2353 {
2354         if (timer_pending(&hfc_tl))
2355                 del_timer(&hfc_tl);
2356 
2357         pci_unregister_driver(&hfc_driver);
2358 }
2359 
2360 module_init(HFC_init);
2361 module_exit(HFC_cleanup);
2362 
2363 MODULE_DEVICE_TABLE(pci, hfc_ids);
2364 

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