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Linux/drivers/irqchip/irq-bcm2835.c

  1 /*
  2  * Copyright 2010 Broadcom
  3  * Copyright 2012 Simon Arlott, Chris Boot, Stephen Warren
  4  *
  5  * This program is free software; you can redistribute it and/or modify
  6  * it under the terms of the GNU General Public License as published by
  7  * the Free Software Foundation; either version 2 of the License, or
  8  * (at your option) any later version.
  9  *
 10  * This program is distributed in the hope that it will be useful,
 11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  *
 15  * Quirk 1: Shortcut interrupts don't set the bank 1/2 register pending bits
 16  *
 17  * If an interrupt fires on bank 1 that isn't in the shortcuts list, bit 8
 18  * on bank 0 is set to signify that an interrupt in bank 1 has fired, and
 19  * to look in the bank 1 status register for more information.
 20  *
 21  * If an interrupt fires on bank 1 that _is_ in the shortcuts list, its
 22  * shortcut bit in bank 0 is set as well as its interrupt bit in the bank 1
 23  * status register, but bank 0 bit 8 is _not_ set.
 24  *
 25  * Quirk 2: You can't mask the register 1/2 pending interrupts
 26  *
 27  * In a proper cascaded interrupt controller, the interrupt lines with
 28  * cascaded interrupt controllers on them are just normal interrupt lines.
 29  * You can mask the interrupts and get on with things. With this controller
 30  * you can't do that.
 31  *
 32  * Quirk 3: The shortcut interrupts can't be (un)masked in bank 0
 33  *
 34  * Those interrupts that have shortcuts can only be masked/unmasked in
 35  * their respective banks' enable/disable registers. Doing so in the bank 0
 36  * enable/disable registers has no effect.
 37  *
 38  * The FIQ control register:
 39  *  Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
 40  *  Bit    7: Enable FIQ generation
 41  *  Bits  8+: Unused
 42  *
 43  * An interrupt must be disabled before configuring it for FIQ generation
 44  * otherwise both handlers will fire at the same time!
 45  */
 46 
 47 #include <linux/io.h>
 48 #include <linux/slab.h>
 49 #include <linux/of_address.h>
 50 #include <linux/of_irq.h>
 51 #include <linux/irqdomain.h>
 52 
 53 #include <asm/exception.h>
 54 #include <asm/mach/irq.h>
 55 
 56 #include "irqchip.h"
 57 
 58 /* Put the bank and irq (32 bits) into the hwirq */
 59 #define MAKE_HWIRQ(b, n)        ((b << 5) | (n))
 60 #define HWIRQ_BANK(i)           (i >> 5)
 61 #define HWIRQ_BIT(i)            BIT(i & 0x1f)
 62 
 63 #define NR_IRQS_BANK0           8
 64 #define BANK0_HWIRQ_MASK        0xff
 65 /* Shortcuts can't be disabled so any unknown new ones need to be masked */
 66 #define SHORTCUT1_MASK          0x00007c00
 67 #define SHORTCUT2_MASK          0x001f8000
 68 #define SHORTCUT_SHIFT          10
 69 #define BANK1_HWIRQ             BIT(8)
 70 #define BANK2_HWIRQ             BIT(9)
 71 #define BANK0_VALID_MASK        (BANK0_HWIRQ_MASK | BANK1_HWIRQ | BANK2_HWIRQ \
 72                                         | SHORTCUT1_MASK | SHORTCUT2_MASK)
 73 
 74 #define REG_FIQ_CONTROL         0x0c
 75 
 76 #define NR_BANKS                3
 77 #define IRQS_PER_BANK           32
 78 
 79 static int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };
 80 static int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
 81 static int reg_disable[] __initconst = { 0x24, 0x1c, 0x20 };
 82 static int bank_irqs[] __initconst = { 8, 32, 32 };
 83 
 84 static const int shortcuts[] = {
 85         7, 9, 10, 18, 19,               /* Bank 1 */
 86         21, 22, 23, 24, 25, 30          /* Bank 2 */
 87 };
 88 
 89 struct armctrl_ic {
 90         void __iomem *base;
 91         void __iomem *pending[NR_BANKS];
 92         void __iomem *enable[NR_BANKS];
 93         void __iomem *disable[NR_BANKS];
 94         struct irq_domain *domain;
 95 };
 96 
 97 static struct armctrl_ic intc __read_mostly;
 98 static void __exception_irq_entry bcm2835_handle_irq(
 99         struct pt_regs *regs);
100 
101 static void armctrl_mask_irq(struct irq_data *d)
102 {
103         writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]);
104 }
105 
106 static void armctrl_unmask_irq(struct irq_data *d)
107 {
108         writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]);
109 }
110 
111 static struct irq_chip armctrl_chip = {
112         .name = "ARMCTRL-level",
113         .irq_mask = armctrl_mask_irq,
114         .irq_unmask = armctrl_unmask_irq
115 };
116 
117 static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
118         const u32 *intspec, unsigned int intsize,
119         unsigned long *out_hwirq, unsigned int *out_type)
120 {
121         if (WARN_ON(intsize != 2))
122                 return -EINVAL;
123 
124         if (WARN_ON(intspec[0] >= NR_BANKS))
125                 return -EINVAL;
126 
127         if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
128                 return -EINVAL;
129 
130         if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
131                 return -EINVAL;
132 
133         *out_hwirq = MAKE_HWIRQ(intspec[0], intspec[1]);
134         *out_type = IRQ_TYPE_NONE;
135         return 0;
136 }
137 
138 static struct irq_domain_ops armctrl_ops = {
139         .xlate = armctrl_xlate
140 };
141 
142 static int __init armctrl_of_init(struct device_node *node,
143         struct device_node *parent)
144 {
145         void __iomem *base;
146         int irq, b, i;
147 
148         base = of_iomap(node, 0);
149         if (!base)
150                 panic("%s: unable to map IC registers\n",
151                         node->full_name);
152 
153         intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0),
154                         &armctrl_ops, NULL);
155         if (!intc.domain)
156                 panic("%s: unable to create IRQ domain\n", node->full_name);
157 
158         for (b = 0; b < NR_BANKS; b++) {
159                 intc.pending[b] = base + reg_pending[b];
160                 intc.enable[b] = base + reg_enable[b];
161                 intc.disable[b] = base + reg_disable[b];
162 
163                 for (i = 0; i < bank_irqs[b]; i++) {
164                         irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i));
165                         BUG_ON(irq <= 0);
166                         irq_set_chip_and_handler(irq, &armctrl_chip,
167                                 handle_level_irq);
168                         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
169                 }
170         }
171 
172         set_handle_irq(bcm2835_handle_irq);
173         return 0;
174 }
175 
176 /*
177  * Handle each interrupt across the entire interrupt controller.  This reads the
178  * status register before handling each interrupt, which is necessary given that
179  * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
180  */
181 
182 static void armctrl_handle_bank(int bank, struct pt_regs *regs)
183 {
184         u32 stat, irq;
185 
186         while ((stat = readl_relaxed(intc.pending[bank]))) {
187                 irq = MAKE_HWIRQ(bank, ffs(stat) - 1);
188                 handle_IRQ(irq_linear_revmap(intc.domain, irq), regs);
189         }
190 }
191 
192 static void armctrl_handle_shortcut(int bank, struct pt_regs *regs,
193         u32 stat)
194 {
195         u32 irq = MAKE_HWIRQ(bank, shortcuts[ffs(stat >> SHORTCUT_SHIFT) - 1]);
196         handle_IRQ(irq_linear_revmap(intc.domain, irq), regs);
197 }
198 
199 static void __exception_irq_entry bcm2835_handle_irq(
200         struct pt_regs *regs)
201 {
202         u32 stat, irq;
203 
204         while ((stat = readl_relaxed(intc.pending[0]) & BANK0_VALID_MASK)) {
205                 if (stat & BANK0_HWIRQ_MASK) {
206                         irq = MAKE_HWIRQ(0, ffs(stat & BANK0_HWIRQ_MASK) - 1);
207                         handle_IRQ(irq_linear_revmap(intc.domain, irq), regs);
208                 } else if (stat & SHORTCUT1_MASK) {
209                         armctrl_handle_shortcut(1, regs, stat & SHORTCUT1_MASK);
210                 } else if (stat & SHORTCUT2_MASK) {
211                         armctrl_handle_shortcut(2, regs, stat & SHORTCUT2_MASK);
212                 } else if (stat & BANK1_HWIRQ) {
213                         armctrl_handle_bank(1, regs);
214                 } else if (stat & BANK2_HWIRQ) {
215                         armctrl_handle_bank(2, regs);
216                 } else {
217                         BUG();
218                 }
219         }
220 }
221 
222 IRQCHIP_DECLARE(bcm2835_armctrl_ic, "brcm,bcm2835-armctrl-ic", armctrl_of_init);
223 

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